From b1c581a99d1e4a466acd38048194087af2916544 Mon Sep 17 00:00:00 2001 From: Brad Gilbert Date: Tue, 14 Apr 2009 12:33:14 -0500 Subject: [PATCH] Added info to insns.dat other minor cleanups --- .gitignore | 1 + perl/README | 2 +- perl/insns.dat | 3902 ++++++++++++++++++++++++++++++++++++++++++ perl/insns.old.pl | 1022 +++++++++++ perl/insns.pl | 14 + perl/lib/Nasm/insns.pm | 6 +- perl/lib/Nasm/insns/Flags.pm | 12 +- 7 files changed, 4951 insertions(+), 8 deletions(-) create mode 100644 perl/insns.dat create mode 100755 perl/insns.old.pl create mode 100755 perl/insns.pl diff --git a/.gitignore b/.gitignore index b3439963..bf12177f 100644 --- a/.gitignore +++ b/.gitignore @@ -12,6 +12,7 @@ \#* *.bak *.tmp +*.kpf /Makefile /config.h /config.h.in diff --git a/perl/README b/perl/README index 646b8710..e10a9cc4 100644 --- a/perl/README +++ b/perl/README @@ -1,4 +1,4 @@ -cd $dir; +cd perl; prove -r; Finished / Usable diff --git a/perl/insns.dat b/perl/insns.dat new file mode 100644 index 00000000..96a88894 --- /dev/null +++ b/perl/insns.dat @@ -0,0 +1,3902 @@ +; insns.dat table of instructions for the Netwide Assembler +; +; The Netwide Assembler is copyright (C) 1996 Simon Tatham and +; Julian Hall. All rights reserved. The software is +; redistributable under the license given in the file "LICENSE" +; distributed in the NASM archive. +; +; Format of file: All four fields must be present on every functional +; line. Hence `void' for no-operand instructions, and `\0' for such +; as EQU. If the last three fields are all `ignore', no action is +; taken except to register the opcode as being present. +; +; For a detailed description of the code string (third field), please +; see the comment at the top of assemble.c. For a detailed description +; of the flags (fourth field), please see insns.h. +; +; Comments with a pound sign after the semicolon generate section +; subheaders in the NASM documentation. +; +; [name] [operands] [code string] [flags] +; +; [name] +; /^(\w[_\w]*)\s+/x +; +; [operands] +; /\G( ignore | void | )/x +; +; +; +; +; +; +; +; +; + + + +;# Special instructions... +DB ignore ignore ignore +DW ignore ignore ignore +DD ignore ignore ignore +DQ ignore ignore ignore +DT ignore ignore ignore +DO ignore ignore ignore +DY ignore ignore ignore +RESB imm \340 8086 +RESW ignore ignore ignore +RESD ignore ignore ignore +RESQ ignore ignore ignore +REST ignore ignore ignore +RESO ignore ignore ignore +RESY ignore ignore ignore + +;# Conventional instructions +AAA void \1\x37 8086,NOLONG +AAD void \2\xD5\x0A 8086,NOLONG +AAD imm \1\xD5\24 8086,SB,NOLONG +AAM void \2\xD4\x0A 8086,NOLONG +AAM imm \1\xD4\24 8086,SB,NOLONG +AAS void \1\x3F 8086,NOLONG +ADC mem,reg8 \1\x10\101 8086,SM +ADC reg8,reg8 \1\x10\101 8086 +ADC mem,reg16 \320\1\x11\101 8086,SM +ADC reg16,reg16 \320\1\x11\101 8086 +ADC mem,reg32 \321\1\x11\101 386,SM +ADC reg32,reg32 \321\1\x11\101 386 +ADC mem,reg64 \324\1\x11\101 X64,SM +ADC reg64,reg64 \324\1\x11\101 X64 +ADC reg8,mem \1\x12\110 8086,SM +ADC reg8,reg8 \1\x12\110 8086 +ADC reg16,mem \320\1\x13\110 8086,SM +ADC reg16,reg16 \320\1\x13\110 8086 +ADC reg32,mem \321\1\x13\110 386,SM +ADC reg32,reg32 \321\1\x13\110 386 +ADC reg64,mem \324\1\x13\110 X64,SM +ADC reg64,reg64 \324\1\x13\110 X64 +ADC rm16,imm8 \320\1\x83\202\275 8086 +ADC rm32,imm8 \321\1\x83\202\275 386 +ADC rm64,imm8 \324\1\x83\202\275 X64 +ADC reg_al,imm \1\x14\21 8086,SM +ADC reg_ax,sbyte16 \320\1\x83\202\275 8086,SM +ADC reg_ax,imm \320\1\x15\31 8086,SM +ADC reg_eax,sbyte32 \321\1\x83\202\275 386,SM +ADC reg_eax,imm \321\1\x15\41 386,SM +ADC reg_rax,sbyte64 \324\1\x83\202\275 X64,SM +ADC reg_rax,imm \324\1\x15\255 X64,SM +ADC rm8,imm \1\x80\202\21 8086,SM +ADC rm16,imm \320\145\x81\202\141 8086,SM +ADC rm32,imm \321\155\x81\202\151 386,SM +ADC rm64,imm \324\155\x81\202\251 X64,SM +ADC mem,imm8 \1\x80\202\21 8086,SM +ADC mem,imm16 \320\145\x81\202\141 8086,SM +ADC mem,imm32 \321\155\x81\202\151 386,SM +ADD mem,reg8 \1\x00\101 8086,SM +ADD reg8,reg8 \1\x00\101 8086 +ADD mem,reg16 \320\1\x01\101 8086,SM +ADD reg16,reg16 \320\1\x01\101 8086 +ADD mem,reg32 \321\1\x01\101 386,SM +ADD reg32,reg32 \321\1\x01\101 386 +ADD mem,reg64 \324\1\x01\101 X64,SM +ADD reg64,reg64 \324\1\x01\101 X64 +ADD reg8,mem \1\x02\110 8086,SM +ADD reg8,reg8 \1\x02\110 8086 +ADD reg16,mem \320\1\x03\110 8086,SM +ADD reg16,reg16 \320\1\x03\110 8086 +ADD reg32,mem \321\1\x03\110 386,SM +ADD reg32,reg32 \321\1\x03\110 386 +ADD reg64,mem \324\1\x03\110 X64,SM +ADD reg64,reg64 \324\1\x03\110 X64 +ADD rm16,imm8 \320\1\x83\200\275 8086 +ADD rm32,imm8 \321\1\x83\200\275 386 +ADD rm64,imm8 \324\1\x83\200\275 X64 +ADD reg_al,imm \1\x04\21 8086,SM +ADD reg_ax,sbyte16 \320\1\x83\200\275 8086,SM +ADD reg_ax,imm \320\1\x05\31 8086,SM +ADD reg_eax,sbyte32 \321\1\x83\200\275 386,SM +ADD reg_eax,imm \321\1\x05\41 386,SM +ADD reg_rax,sbyte64 \324\1\x83\200\275 X64,SM +ADD reg_rax,imm \324\1\x05\255 X64,SM +ADD rm8,imm \1\x80\200\21 8086,SM +ADD rm16,imm \320\145\x81\200\141 8086,SM +ADD rm32,imm \321\155\x81\200\151 386,SM +ADD rm64,imm \324\155\x81\200\251 X64,SM +ADD mem,imm8 \1\x80\200\21 8086,SM +ADD mem,imm16 \320\145\x81\200\141 8086,SM +ADD mem,imm32 \321\155\x81\200\151 386,SM +AND mem,reg8 \1\x20\101 8086,SM +AND reg8,reg8 \1\x20\101 8086 +AND mem,reg16 \320\1\x21\101 8086,SM +AND reg16,reg16 \320\1\x21\101 8086 +AND mem,reg32 \321\1\x21\101 386,SM +AND reg32,reg32 \321\1\x21\101 386 +AND mem,reg64 \324\1\x21\101 X64,SM +AND reg64,reg64 \324\1\x21\101 X64 +AND reg8,mem \1\x22\110 8086,SM +AND reg8,reg8 \1\x22\110 8086 +AND reg16,mem \320\1\x23\110 8086,SM +AND reg16,reg16 \320\1\x23\110 8086 +AND reg32,mem \321\1\x23\110 386,SM +AND reg32,reg32 \321\1\x23\110 386 +AND reg64,mem \324\1\x23\110 X64,SM +AND reg64,reg64 \324\1\x23\110 X64 +AND rm16,imm8 \320\1\x83\204\275 8086 +AND rm32,imm8 \321\1\x83\204\275 386 +AND rm64,imm8 \324\1\x83\204\275 X64 +AND reg_al,imm \1\x24\21 8086,SM +AND reg_ax,sbyte16 \320\1\x83\204\275 8086,SM +AND reg_ax,imm \320\1\x25\31 8086,SM +AND reg_eax,sbyte32 \321\1\x83\204\275 386,SM +AND reg_eax,imm \321\1\x25\41 386,SM +AND reg_rax,sbyte64 \324\1\x83\204\275 X64,SM +AND reg_rax,imm \324\1\x25\255 X64,SM +AND rm8,imm \1\x80\204\21 8086,SM +AND rm16,imm \320\145\x81\204\141 8086,SM +AND rm32,imm \321\155\x81\204\151 386,SM +AND rm64,imm \324\155\x81\204\251 X64,SM +AND mem,imm8 \1\x80\204\21 8086,SM +AND mem,imm16 \320\145\x81\204\141 8086,SM +AND mem,imm32 \321\155\x81\204\151 386,SM +ARPL mem,reg16 \1\x63\101 286,PROT,SM,NOLONG +ARPL reg16,reg16 \1\x63\101 286,PROT,NOLONG +BB0_RESET void \2\x0F\x3A PENT,CYRIX,ND +BB1_RESET void \2\x0F\x3B PENT,CYRIX,ND +BOUND reg16,mem \320\1\x62\110 186,NOLONG +BOUND reg32,mem \321\1\x62\110 386,NOLONG +BSF reg16,mem \320\2\x0F\xBC\110 386,SM +BSF reg16,reg16 \320\2\x0F\xBC\110 386 +BSF reg32,mem \321\2\x0F\xBC\110 386,SM +BSF reg32,reg32 \321\2\x0F\xBC\110 386 +BSF reg64,mem \324\2\x0F\xBC\110 X64,SM +BSF reg64,reg64 \324\2\x0F\xBC\110 X64 +BSR reg16,mem \320\2\x0F\xBD\110 386,SM +BSR reg16,reg16 \320\2\x0F\xBD\110 386 +BSR reg32,mem \321\2\x0F\xBD\110 386,SM +BSR reg32,reg32 \321\2\x0F\xBD\110 386 +BSR reg64,mem \324\2\x0F\xBD\110 X64,SM +BSR reg64,reg64 \324\2\x0F\xBD\110 X64 +BSWAP reg32 \321\1\x0F\10\xC8 486 +BSWAP reg64 \324\1\x0F\10\xC8 X64 +BT mem,reg16 \320\2\x0F\xA3\101 386,SM +BT reg16,reg16 \320\2\x0F\xA3\101 386 +BT mem,reg32 \321\2\x0F\xA3\101 386,SM +BT reg32,reg32 \321\2\x0F\xA3\101 386 +BT mem,reg64 \324\2\x0F\xA3\101 X64,SM +BT reg64,reg64 \324\2\x0F\xA3\101 X64 +BT rm16,imm \320\2\x0F\xBA\204\25 386,SB +BT rm32,imm \321\2\x0F\xBA\204\25 386,SB +BT rm64,imm \324\2\x0F\xBA\204\25 X64,SB +BTC mem,reg16 \320\2\x0F\xBB\101 386,SM +BTC reg16,reg16 \320\2\x0F\xBB\101 386 +BTC mem,reg32 \321\2\x0F\xBB\101 386,SM +BTC reg32,reg32 \321\2\x0F\xBB\101 386 +BTC mem,reg64 \324\2\x0F\xBB\101 X64,SM +BTC reg64,reg64 \324\2\x0F\xBB\101 X64 +BTC rm16,imm \320\2\x0F\xBA\207\25 386,SB +BTC rm32,imm \321\2\x0F\xBA\207\25 386,SB +BTC rm64,imm \324\2\x0F\xBA\207\25 X64,SB +BTR mem,reg16 \320\2\x0F\xB3\101 386,SM +BTR reg16,reg16 \320\2\x0F\xB3\101 386 +BTR mem,reg32 \321\2\x0F\xB3\101 386,SM +BTR reg32,reg32 \321\2\x0F\xB3\101 386 +BTR mem,reg64 \324\2\x0F\xB3\101 X64,SM +BTR reg64,reg64 \324\2\x0F\xB3\101 X64 +BTR rm16,imm \320\2\x0F\xBA\206\25 386,SB +BTR rm32,imm \321\2\x0F\xBA\206\25 386,SB +BTR rm64,imm \324\2\x0F\xBA\206\25 X64,SB +BTS mem,reg16 \320\2\x0F\xAB\101 386,SM +BTS reg16,reg16 \320\2\x0F\xAB\101 386 +BTS mem,reg32 \321\2\x0F\xAB\101 386,SM +BTS reg32,reg32 \321\2\x0F\xAB\101 386 +BTS mem,reg64 \324\2\x0F\xAB\101 X64,SM +BTS reg64,reg64 \324\2\x0F\xAB\101 X64 +BTS rm16,imm \320\2\x0F\xBA\205\25 386,SB +BTS rm32,imm \321\2\x0F\xBA\205\25 386,SB +BTS rm64,imm \324\2\x0F\xBA\205\25 X64,SB +CALL imm \322\1\xE8\64 8086 +CALL imm|near \322\1\xE8\64 8086 +CALL imm|far \322\1\x9A\34\74 8086,ND,NOLONG +CALL imm16 \320\1\xE8\64 8086 +CALL imm16|near \320\1\xE8\64 8086 +CALL imm16|far \320\1\x9A\34\74 8086,ND,NOLONG +CALL imm32 \321\1\xE8\64 386 +CALL imm32|near \321\1\xE8\64 386 +CALL imm32|far \321\1\x9A\34\74 386,ND,NOLONG +CALL imm:imm \322\1\x9A\35\30 8086,NOLONG +CALL imm16:imm \320\1\x9A\31\30 8086,NOLONG +CALL imm:imm16 \320\1\x9A\31\30 8086,NOLONG +CALL imm32:imm \321\1\x9A\41\30 386,NOLONG +CALL imm:imm32 \321\1\x9A\41\30 386,NOLONG +CALL mem|far \322\1\xFF\203 8086,NOLONG +CALL mem|far \324\1\xFF\203 X64 +CALL mem16|far \320\1\xFF\203 8086 +CALL mem32|far \321\1\xFF\203 386 +CALL mem64|far \324\1\xFF\203 X64 +CALL mem|near \322\1\xFF\202 8086 +CALL mem16|near \320\1\xFF\202 8086 +CALL mem32|near \321\1\xFF\202 386,NOLONG +CALL mem64|near \324\1\xFF\202 X64 +CALL reg16 \320\1\xFF\202 8086 +CALL reg32 \321\1\xFF\202 386,NOLONG +CALL reg64 \323\1\xFF\202 X64 +CALL mem \322\1\xFF\202 8086 +CALL mem16 \320\1\xFF\202 8086 +CALL mem32 \321\1\xFF\202 386,NOLONG +CALL mem64 \323\1\xFF\202 X64 +CBW void \320\1\x98 8086 +CDQ void \321\1\x99 386 +CDQE void \324\1\x98 X64 +CLC void \1\xF8 8086 +CLD void \1\xFC 8086 +CLGI void \3\x0F\x01\xDD X64,AMD +CLI void \1\xFA 8086 +CLTS void \2\x0F\x06 286,PRIV +CMC void \1\xF5 8086 +CMP mem,reg8 \1\x38\101 8086,SM +CMP reg8,reg8 \1\x38\101 8086 +CMP mem,reg16 \320\1\x39\101 8086,SM +CMP reg16,reg16 \320\1\x39\101 8086 +CMP mem,reg32 \321\1\x39\101 386,SM +CMP reg32,reg32 \321\1\x39\101 386 +CMP mem,reg64 \324\1\x39\101 X64,SM +CMP reg64,reg64 \324\1\x39\101 X64 +CMP reg8,mem \1\x3A\110 8086,SM +CMP reg8,reg8 \1\x3A\110 8086 +CMP reg16,mem \320\1\x3B\110 8086,SM +CMP reg16,reg16 \320\1\x3B\110 8086 +CMP reg32,mem \321\1\x3B\110 386,SM +CMP reg32,reg32 \321\1\x3B\110 386 +CMP reg64,mem \324\1\x3B\110 X64,SM +CMP reg64,reg64 \324\1\x3B\110 X64 +CMP rm16,imm8 \320\1\x83\207\275 8086 +CMP rm32,imm8 \321\1\x83\207\275 386 +CMP rm64,imm8 \324\1\x83\207\275 X64 +CMP reg_al,imm \1\x3C\21 8086,SM +CMP reg_ax,sbyte16 \320\1\x83\207\275 8086,SM +CMP reg_ax,imm \320\1\x3D\31 8086,SM +CMP reg_eax,sbyte32 \321\1\x83\207\275 386,SM +CMP reg_eax,imm \321\1\x3D\41 386,SM +CMP reg_rax,sbyte64 \324\1\x83\207\275 X64,SM +CMP reg_rax,imm \324\1\x3D\255 X64,SM +CMP rm8,imm \1\x80\207\21 8086,SM +CMP rm16,imm \320\145\x81\207\141 8086,SM +CMP rm32,imm \321\155\x81\207\151 386,SM +CMP rm64,imm \324\155\x81\207\251 X64,SM +CMP mem,imm8 \1\x80\207\21 8086,SM +CMP mem,imm16 \320\145\x81\207\141 8086,SM +CMP mem,imm32 \321\155\x81\207\151 386,SM +CMPSB void \335\1\xA6 8086 +CMPSD void \335\321\1\xA7 386 +CMPSQ void \335\324\1\xA7 X64 +CMPSW void \335\320\1\xA7 8086 +CMPXCHG mem,reg8 \2\x0F\xB0\101 PENT,SM +CMPXCHG reg8,reg8 \2\x0F\xB0\101 PENT +CMPXCHG mem,reg16 \320\2\x0F\xB1\101 PENT,SM +CMPXCHG reg16,reg16 \320\2\x0F\xB1\101 PENT +CMPXCHG mem,reg32 \321\2\x0F\xB1\101 PENT,SM +CMPXCHG reg32,reg32 \321\2\x0F\xB1\101 PENT +CMPXCHG mem,reg64 \324\2\x0F\xB1\101 X64,SM +CMPXCHG reg64,reg64 \324\2\x0F\xB1\101 X64 +CMPXCHG486 mem,reg8 \2\x0F\xA6\101 486,SM,UNDOC,ND +CMPXCHG486 reg8,reg8 \2\x0F\xA6\101 486,UNDOC,ND +CMPXCHG486 mem,reg16 \320\2\x0F\xA7\101 486,SM,UNDOC,ND +CMPXCHG486 reg16,reg16 \320\2\x0F\xA7\101 486,UNDOC,ND +CMPXCHG486 mem,reg32 \321\2\x0F\xA7\101 486,SM,UNDOC,ND +CMPXCHG486 reg32,reg32 \321\2\x0F\xA7\101 486,UNDOC,ND +CMPXCHG8B mem \2\x0F\xC7\201 PENT +CMPXCHG16B mem \324\2\x0F\xC7\201 X64 +CPUID void \2\x0F\xA2 PENT +CPU_READ void \2\x0F\x3D PENT,CYRIX +CPU_WRITE void \2\x0F\x3C PENT,CYRIX +CQO void \324\1\x99 X64 +CWD void \320\1\x99 8086 +CWDE void \321\1\x98 386 +DAA void \1\x27 8086,NOLONG +DAS void \1\x2F 8086,NOLONG +DEC reg16 \320\10\x48 8086,NOLONG +DEC reg32 \321\10\x48 386,NOLONG +DEC rm8 \1\xFE\201 8086 +DEC rm16 \320\1\xFF\201 8086 +DEC rm32 \321\1\xFF\201 386 +DEC rm64 \324\1\xFF\201 X64 +DIV rm8 \1\xF6\206 8086 +DIV rm16 \320\1\xF7\206 8086 +DIV rm32 \321\1\xF7\206 386 +DIV rm64 \324\1\xF7\206 X64 +DMINT void \2\x0F\x39 P6,CYRIX +EMMS void \2\x0F\x77 PENT,MMX +ENTER imm,imm \1\xC8\30\25 186 +EQU imm \0 8086 +EQU imm:imm \0 8086 +F2XM1 void \2\xD9\xF0 8086,FPU +FABS void \2\xD9\xE1 8086,FPU +FADD mem32 \1\xD8\200 8086,FPU +FADD mem64 \1\xDC\200 8086,FPU +FADD fpureg|to \1\xDC\10\xC0 8086,FPU +FADD fpureg \1\xD8\10\xC0 8086,FPU +FADD fpureg,fpu0 \1\xDC\10\xC0 8086,FPU +FADD fpu0,fpureg \1\xD8\11\xC0 8086,FPU +FADD void \2\xDE\xC1 8086,FPU,ND +FADDP fpureg \1\xDE\10\xC0 8086,FPU +FADDP fpureg,fpu0 \1\xDE\10\xC0 8086,FPU +FADDP void \2\xDE\xC1 8086,FPU,ND +FBLD mem80 \1\xDF\204 8086,FPU +FBLD mem \1\xDF\204 8086,FPU +FBSTP mem80 \1\xDF\206 8086,FPU +FBSTP mem \1\xDF\206 8086,FPU +FCHS void \2\xD9\xE0 8086,FPU +FCLEX void \341\2\xDB\xE2 8086,FPU +FCMOVB fpureg \1\xDA\10\xC0 P6,FPU +FCMOVB fpu0,fpureg \1\xDA\11\xC0 P6,FPU +FCMOVB void \2\xDA\xC1 P6,FPU,ND +FCMOVBE fpureg \1\xDA\10\xD0 P6,FPU +FCMOVBE fpu0,fpureg \1\xDA\11\xD0 P6,FPU +FCMOVBE void \2\xDA\xD1 P6,FPU,ND +FCMOVE fpureg \1\xDA\10\xC8 P6,FPU +FCMOVE fpu0,fpureg \1\xDA\11\xC8 P6,FPU +FCMOVE void \2\xDA\xC9 P6,FPU,ND +FCMOVNB fpureg \1\xDB\10\xC0 P6,FPU +FCMOVNB fpu0,fpureg \1\xDB\11\xC0 P6,FPU +FCMOVNB void \2\xDB\xC1 P6,FPU,ND +FCMOVNBE fpureg \1\xDB\10\xD0 P6,FPU +FCMOVNBE fpu0,fpureg \1\xDB\11\xD0 P6,FPU +FCMOVNBE void \2\xDB\xD1 P6,FPU,ND +FCMOVNE fpureg \1\xDB\10\xC8 P6,FPU +FCMOVNE fpu0,fpureg \1\xDB\11\xC8 P6,FPU +FCMOVNE void \2\xDB\xC9 P6,FPU,ND +FCMOVNU fpureg \1\xDB\10\xD8 P6,FPU +FCMOVNU fpu0,fpureg \1\xDB\11\xD8 P6,FPU +FCMOVNU void \2\xDB\xD9 P6,FPU,ND +FCMOVU fpureg \1\xDA\10\xD8 P6,FPU +FCMOVU fpu0,fpureg \1\xDA\11\xD8 P6,FPU +FCMOVU void \2\xDA\xD9 P6,FPU,ND +FCOM mem32 \1\xD8\202 8086,FPU +FCOM mem64 \1\xDC\202 8086,FPU +FCOM fpureg \1\xD8\10\xD0 8086,FPU +FCOM fpu0,fpureg \1\xD8\11\xD0 8086,FPU +FCOM void \2\xD8\xD1 8086,FPU,ND +FCOMI fpureg \1\xDB\10\xF0 P6,FPU +FCOMI fpu0,fpureg \1\xDB\11\xF0 P6,FPU +FCOMI void \2\xDB\xF1 P6,FPU,ND +FCOMIP fpureg \1\xDF\10\xF0 P6,FPU +FCOMIP fpu0,fpureg \1\xDF\11\xF0 P6,FPU +FCOMIP void \2\xDF\xF1 P6,FPU,ND +FCOMP mem32 \1\xD8\203 8086,FPU +FCOMP mem64 \1\xDC\203 8086,FPU +FCOMP fpureg \1\xD8\10\xD8 8086,FPU +FCOMP fpu0,fpureg \1\xD8\11\xD8 8086,FPU +FCOMP void \2\xD8\xD9 8086,FPU,ND +FCOMPP void \2\xDE\xD9 8086,FPU +FCOS void \2\xD9\xFF 386,FPU +FDECSTP void \2\xD9\xF6 8086,FPU +FDISI void \341\2\xDB\xE1 8086,FPU +FDIV mem32 \1\xD8\206 8086,FPU +FDIV mem64 \1\xDC\206 8086,FPU +FDIV fpureg|to \1\xDC\10\xF8 8086,FPU +FDIV fpureg \1\xD8\10\xF0 8086,FPU +FDIV fpureg,fpu0 \1\xDC\10\xF8 8086,FPU +FDIV fpu0,fpureg \1\xD8\11\xF0 8086,FPU +FDIV void \2\xDE\xF9 8086,FPU,ND +FDIVP fpureg \1\xDE\10\xF8 8086,FPU +FDIVP fpureg,fpu0 \1\xDE\10\xF8 8086,FPU +FDIVP void \2\xDE\xF9 8086,FPU,ND +FDIVR mem32 \1\xD8\207 8086,FPU +FDIVR mem64 \1\xDC\207 8086,FPU +FDIVR fpureg|to \1\xDC\10\xF0 8086,FPU +FDIVR fpureg,fpu0 \1\xDC\10\xF0 8086,FPU +FDIVR fpureg \1\xD8\10\xF8 8086,FPU +FDIVR fpu0,fpureg \1\xD8\11\xF8 8086,FPU +FDIVR void \2\xDE\xF1 8086,FPU,ND +FDIVRP fpureg \1\xDE\10\xF0 8086,FPU +FDIVRP fpureg,fpu0 \1\xDE\10\xF0 8086,FPU +FDIVRP void \2\xDE\xF1 8086,FPU,ND +FEMMS void \2\x0F\x0E PENT,3DNOW +FENI void \341\2\xDB\xE0 8086,FPU +FFREE fpureg \1\xDD\10\xC0 8086,FPU +FFREE void \2\xDD\xC1 8086,FPU +FFREEP fpureg \1\xDF\10\xC0 286,FPU,UNDOC +FFREEP void \2\xDF\xC1 286,FPU,UNDOC +FIADD mem32 \1\xDA\200 8086,FPU +FIADD mem16 \1\xDE\200 8086,FPU +FICOM mem32 \1\xDA\202 8086,FPU +FICOM mem16 \1\xDE\202 8086,FPU +FICOMP mem32 \1\xDA\203 8086,FPU +FICOMP mem16 \1\xDE\203 8086,FPU +FIDIV mem32 \1\xDA\206 8086,FPU +FIDIV mem16 \1\xDE\206 8086,FPU +FIDIVR mem32 \1\xDA\207 8086,FPU +FIDIVR mem16 \1\xDE\207 8086,FPU +FILD mem32 \1\xDB\200 8086,FPU +FILD mem16 \1\xDF\200 8086,FPU +FILD mem64 \1\xDF\205 8086,FPU +FIMUL mem32 \1\xDA\201 8086,FPU +FIMUL mem16 \1\xDE\201 8086,FPU +FINCSTP void \2\xD9\xF7 8086,FPU +FINIT void \341\2\xDB\xE3 8086,FPU +FIST mem32 \1\xDB\202 8086,FPU +FIST mem16 \1\xDF\202 8086,FPU +FISTP mem32 \1\xDB\203 8086,FPU +FISTP mem16 \1\xDF\203 8086,FPU +FISTP mem64 \1\xDF\207 8086,FPU +FISTTP mem16 \1\xDF\201 PRESCOTT,FPU +FISTTP mem32 \1\xDB\201 PRESCOTT,FPU +FISTTP mem64 \1\xDD\201 PRESCOTT,FPU +FISUB mem32 \1\xDA\204 8086,FPU +FISUB mem16 \1\xDE\204 8086,FPU +FISUBR mem32 \1\xDA\205 8086,FPU +FISUBR mem16 \1\xDE\205 8086,FPU +FLD mem32 \1\xD9\200 8086,FPU +FLD mem64 \1\xDD\200 8086,FPU +FLD mem80 \1\xDB\205 8086,FPU +FLD fpureg \1\xD9\10\xC0 8086,FPU +FLD void \2\xD9\xC1 8086,FPU,ND +FLD1 void \2\xD9\xE8 8086,FPU +FLDCW mem \1\xD9\205 8086,FPU,SW +FLDENV mem \1\xD9\204 8086,FPU +FLDL2E void \2\xD9\xEA 8086,FPU +FLDL2T void \2\xD9\xE9 8086,FPU +FLDLG2 void \2\xD9\xEC 8086,FPU +FLDLN2 void \2\xD9\xED 8086,FPU +FLDPI void \2\xD9\xEB 8086,FPU +FLDZ void \2\xD9\xEE 8086,FPU +FMUL mem32 \1\xD8\201 8086,FPU +FMUL mem64 \1\xDC\201 8086,FPU +FMUL fpureg|to \1\xDC\10\xC8 8086,FPU +FMUL fpureg,fpu0 \1\xDC\10\xC8 8086,FPU +FMUL fpureg \1\xD8\10\xC8 8086,FPU +FMUL fpu0,fpureg \1\xD8\11\xC8 8086,FPU +FMUL void \2\xDE\xC9 8086,FPU,ND +FMULP fpureg \1\xDE\10\xC8 8086,FPU +FMULP fpureg,fpu0 \1\xDE\10\xC8 8086,FPU +FMULP void \2\xDE\xC9 8086,FPU,ND +FNCLEX void \2\xDB\xE2 8086,FPU +FNDISI void \2\xDB\xE1 8086,FPU +FNENI void \2\xDB\xE0 8086,FPU +FNINIT void \2\xDB\xE3 8086,FPU +FNOP void \2\xD9\xD0 8086,FPU +FNSAVE mem \1\xDD\206 8086,FPU +FNSTCW mem \1\xD9\207 8086,FPU,SW +FNSTENV mem \1\xD9\206 8086,FPU +FNSTSW mem \1\xDD\207 8086,FPU,SW +FNSTSW reg_ax \2\xDF\xE0 286,FPU +FPATAN void \2\xD9\xF3 8086,FPU +FPREM void \2\xD9\xF8 8086,FPU +FPREM1 void \2\xD9\xF5 386,FPU +FPTAN void \2\xD9\xF2 8086,FPU +FRNDINT void \2\xD9\xFC 8086,FPU +FRSTOR mem \1\xDD\204 8086,FPU +FSAVE mem \341\1\xDD\206 8086,FPU +FSCALE void \2\xD9\xFD 8086,FPU +FSETPM void \2\xDB\xE4 286,FPU +FSIN void \2\xD9\xFE 386,FPU +FSINCOS void \2\xD9\xFB 386,FPU +FSQRT void \2\xD9\xFA 8086,FPU +FST mem32 \1\xD9\202 8086,FPU +FST mem64 \1\xDD\202 8086,FPU +FST fpureg \1\xDD\10\xD0 8086,FPU +FST void \2\xDD\xD1 8086,FPU,ND +FSTCW mem \341\1\xD9\207 8086,FPU,SW +FSTENV mem \341\1\xD9\206 8086,FPU +FSTP mem32 \1\xD9\203 8086,FPU +FSTP mem64 \1\xDD\203 8086,FPU +FSTP mem80 \1\xDB\207 8086,FPU +FSTP fpureg \1\xDD\10\xD8 8086,FPU +FSTP void \2\xDD\xD9 8086,FPU,ND +FSTSW mem \341\1\xDD\207 8086,FPU,SW +FSTSW reg_ax \341\2\xDF\xE0 286,FPU +FSUB mem32 \1\xD8\204 8086,FPU +FSUB mem64 \1\xDC\204 8086,FPU +FSUB fpureg|to \1\xDC\10\xE8 8086,FPU +FSUB fpureg,fpu0 \1\xDC\10\xE8 8086,FPU +FSUB fpureg \1\xD8\10\xE0 8086,FPU +FSUB fpu0,fpureg \1\xD8\11\xE0 8086,FPU +FSUB void \2\xDE\xE9 8086,FPU,ND +FSUBP fpureg \1\xDE\10\xE8 8086,FPU +FSUBP fpureg,fpu0 \1\xDE\10\xE8 8086,FPU +FSUBP void \2\xDE\xE9 8086,FPU,ND +FSUBR mem32 \1\xD8\205 8086,FPU +FSUBR mem64 \1\xDC\205 8086,FPU +FSUBR fpureg|to \1\xDC\10\xE0 8086,FPU +FSUBR fpureg,fpu0 \1\xDC\10\xE0 8086,FPU +FSUBR fpureg \1\xD8\10\xE8 8086,FPU +FSUBR fpu0,fpureg \1\xD8\11\xE8 8086,FPU +FSUBR void \2\xDE\xE1 8086,FPU,ND +FSUBRP fpureg \1\xDE\10\xE0 8086,FPU +FSUBRP fpureg,fpu0 \1\xDE\10\xE0 8086,FPU +FSUBRP void \2\xDE\xE1 8086,FPU,ND +FTST void \2\xD9\xE4 8086,FPU +FUCOM fpureg \1\xDD\10\xE0 386,FPU +FUCOM fpu0,fpureg \1\xDD\11\xE0 386,FPU +FUCOM void \2\xDD\xE1 386,FPU,ND +FUCOMI fpureg \1\xDB\10\xE8 P6,FPU +FUCOMI fpu0,fpureg \1\xDB\11\xE8 P6,FPU +FUCOMI void \2\xDB\xE9 P6,FPU,ND +FUCOMIP fpureg \1\xDF\10\xE8 P6,FPU +FUCOMIP fpu0,fpureg \1\xDF\11\xE8 P6,FPU +FUCOMIP void \2\xDF\xE9 P6,FPU,ND +FUCOMP fpureg \1\xDD\10\xE8 386,FPU +FUCOMP fpu0,fpureg \1\xDD\11\xE8 386,FPU +FUCOMP void \2\xDD\xE9 386,FPU,ND +FUCOMPP void \2\xDA\xE9 386,FPU +FXAM void \2\xD9\xE5 8086,FPU +FXCH fpureg \1\xD9\10\xC8 8086,FPU +FXCH fpureg,fpu0 \1\xD9\10\xC8 8086,FPU +FXCH fpu0,fpureg \1\xD9\11\xC8 8086,FPU +FXCH void \2\xD9\xC9 8086,FPU,ND +FXTRACT void \2\xD9\xF4 8086,FPU +FYL2X void \2\xD9\xF1 8086,FPU +FYL2XP1 void \2\xD9\xF9 8086,FPU +HLT void \1\xF4 8086,PRIV +IBTS mem,reg16 \320\2\x0F\xA7\101 386,SW,UNDOC,ND +IBTS reg16,reg16 \320\2\x0F\xA7\101 386,UNDOC,ND +IBTS mem,reg32 \321\2\x0F\xA7\101 386,SD,UNDOC,ND +IBTS reg32,reg32 \321\2\x0F\xA7\101 386,UNDOC,ND +ICEBP void \1\xF1 386,ND +IDIV rm8 \1\xF6\207 8086 +IDIV rm16 \320\1\xF7\207 8086 +IDIV rm32 \321\1\xF7\207 386 +IDIV rm64 \324\1\xF7\207 X64 +IMUL rm8 \1\xF6\205 8086 +IMUL rm16 \320\1\xF7\205 8086 +IMUL rm32 \321\1\xF7\205 386 +IMUL rm64 \324\1\xF7\205 X64 +IMUL reg16,mem \320\2\x0F\xAF\110 386,SM +IMUL reg16,reg16 \320\2\x0F\xAF\110 386 +IMUL reg32,mem \321\2\x0F\xAF\110 386,SM +IMUL reg32,reg32 \321\2\x0F\xAF\110 386 +IMUL reg64,mem \324\2\x0F\xAF\110 X64,SM +IMUL reg64,reg64 \324\2\x0F\xAF\110 X64 +IMUL reg16,mem,imm8 \320\1\x6B\110\16 186,SM +IMUL reg16,mem,sbyte16 \320\1\x6B\110\16 186,SM,ND +IMUL reg16,mem,imm16 \320\1\x69\110\32 186,SM +IMUL reg16,mem,imm \320\146\x69\110\142 186,SM,ND +IMUL reg16,reg16,imm8 \320\1\x6B\110\16 186 +IMUL reg16,reg16,sbyte32 \320\1\x6B\110\16 186,SM,ND +IMUL reg16,reg16,imm16 \320\1\x69\110\32 186 +IMUL reg16,reg16,imm \320\146\x69\110\142 186,SM,ND +IMUL reg32,mem,imm8 \321\1\x6B\110\16 386,SM +IMUL reg32,mem,sbyte64 \321\1\x6B\110\16 386,SM,ND +IMUL reg32,mem,imm32 \321\1\x69\110\42 386,SM +IMUL reg32,mem,imm \321\156\x69\110\152 386,SM,ND +IMUL reg32,reg32,imm8 \321\1\x6B\110\16 386 +IMUL reg32,reg32,sbyte16 \321\1\x6B\110\16 386,SM,ND +IMUL reg32,reg32,imm32 \321\1\x69\110\42 386 +IMUL reg32,reg32,imm \321\156\x69\110\152 386,SM,ND +IMUL reg64,mem,imm8 \324\1\x6B\110\16 X64,SM +IMUL reg64,mem,sbyte32 \324\1\x6B\110\16 X64,SM,ND +IMUL reg64,mem,imm32 \324\1\x69\110\42 X64,SM +IMUL reg64,mem,imm \324\156\x69\110\252 X64,SM,ND +IMUL reg64,reg64,imm8 \324\1\x6B\110\16 X64 +IMUL reg64,reg64,sbyte64 \324\1\x6B\110\16 X64,SM,ND +IMUL reg64,reg64,imm32 \324\1\x69\110\42 X64 +IMUL reg64,reg64,imm \324\156\x69\110\252 X64,SM,ND +IMUL reg16,imm8 \320\1\x6B\100\15 186 +IMUL reg16,sbyte16 \320\1\x6B\100\15 186,SM,ND +IMUL reg16,imm16 \320\1\x69\100\31 186 +IMUL reg16,imm \320\145\x69\100\141 186,SM,ND +IMUL reg32,imm8 \321\1\x6B\100\15 386 +IMUL reg32,sbyte32 \321\1\x6B\100\15 386,SM,ND +IMUL reg32,imm32 \321\1\x69\100\41 386 +IMUL reg32,imm \321\155\x69\100\151 386,SM,ND +IMUL reg64,imm8 \324\1\x6B\100\15 X64 +IMUL reg64,sbyte64 \324\1\x6B\100\15 X64,SM,ND +IMUL reg64,imm32 \324\1\x69\100\255 X64 +IMUL reg64,imm \324\155\x69\100\251 X64,SM,ND +IN reg_al,imm \1\xE4\25 8086,SB +IN reg_ax,imm \320\1\xE5\25 8086,SB +IN reg_eax,imm \321\1\xE5\25 386,SB +IN reg_al,reg_dx \1\xEC 8086 +IN reg_ax,reg_dx \320\1\xED 8086 +IN reg_eax,reg_dx \321\1\xED 386 +INC reg16 \320\10\x40 8086,NOLONG +INC reg32 \321\10\x40 386,NOLONG +INC rm8 \1\xFE\200 8086 +INC rm16 \320\1\xFF\200 8086 +INC rm32 \321\1\xFF\200 386 +INC rm64 \324\1\xFF\200 X64 +INCBIN ignore ignore ignore +INSB void \1\x6C 186 +INSD void \321\1\x6D 386 +INSW void \320\1\x6D 186 +INT imm \1\xCD\24 8086,SB +INT01 void \1\xF1 386,ND +INT1 void \1\xF1 386 +INT03 void \1\xCC 8086,ND +INT3 void \1\xCC 8086 +INTO void \1\xCE 8086,NOLONG +INVD void \2\x0F\x08 486,PRIV +INVLPG mem \2\x0F\x01\207 486,PRIV +INVLPGA reg_ax,reg_ecx \310\3\x0F\x01\xDF X86_64,AMD,NOLONG +INVLPGA reg_eax,reg_ecx \311\3\x0F\x01\xDF X86_64,AMD +INVLPGA reg_rax,reg_ecx \323\313\3\x0F\x01\xDF X64,AMD +INVLPGA void \3\x0F\x01\xDF X86_64,AMD +IRET void \322\1\xCF 8086 +IRETD void \321\1\xCF 386 +IRETQ void \324\1\xCF X64 +IRETW void \320\1\xCF 8086 +JCXZ imm \310\1\xE3\50 8086,NOLONG +JECXZ imm \311\1\xE3\50 386 +JMP imm|short \1\xEB\50 8086 +JMP imm \371\1\xEB\50 8086,ND +JMP imm \322\1\xE9\64 8086 +JMP imm|near \322\1\xE9\64 8086,ND +JMP imm|far \322\1\xEA\34\74 8086,ND,NOLONG +JMP imm16 \320\1\xE9\64 8086 +JMP imm16|near \320\1\xE9\64 8086,ND +JMP imm16|far \320\1\xEA\34\74 8086,ND,NOLONG +JMP imm32 \321\1\xE9\64 386 +JMP imm32|near \321\1\xE9\64 386,ND +JMP imm32|far \321\1\xEA\34\74 386,ND,NOLONG +JMP imm:imm \322\1\xEA\35\30 8086,NOLONG +JMP imm16:imm \320\1\xEA\31\30 8086,NOLONG +JMP imm:imm16 \320\1\xEA\31\30 8086,NOLONG +JMP imm32:imm \321\1\xEA\41\30 386,NOLONG +JMP imm:imm32 \321\1\xEA\41\30 386,NOLONG +JMP mem|far \322\1\xFF\205 8086,NOLONG +JMP mem|far \324\1\xFF\205 X64 +JMP mem16|far \320\1\xFF\205 8086 +JMP mem32|far \321\1\xFF\205 386 +JMP mem64|far \324\1\xFF\205 X64 +JMP mem|near \322\1\xFF\204 8086 +JMP mem16|near \320\1\xFF\204 8086 +JMP mem32|near \321\1\xFF\204 386,NOLONG +JMP mem64|near \323\1\xFF\204 X64 +JMP reg16 \320\1\xFF\204 8086 +JMP reg32 \321\1\xFF\204 386,NOLONG +JMP reg64 \323\1\xFF\204 X64 +JMP mem \322\1\xFF\204 8086 +JMP mem16 \320\1\xFF\204 8086 +JMP mem32 \321\1\xFF\204 386,NOLONG +JMP mem64 \323\1\xFF\204 X64 +JMPE imm \322\2\x0F\xB8\64 IA64 +JMPE imm16 \320\2\x0F\xB8\64 IA64 +JMPE imm32 \321\2\x0F\xB8\64 IA64 +JMPE rm16 \320\2\x0F\x00\206 IA64 +JMPE rm32 \321\2\x0F\x00\206 IA64 +JRCXZ imm \1\xE3\50 X64 +LAHF void \1\x9F 8086 +LAR reg16,mem \320\2\x0F\x02\110 286,PROT,SW +LAR reg16,reg16 \320\2\x0F\x02\110 286,PROT +LAR reg16,reg32 \320\2\x0F\x02\110 386,PROT +LAR reg16,reg64 \320\323\2\x0F\x02\110 X64,PROT,ND +LAR reg32,mem \321\2\x0F\x02\110 386,PROT,SW +LAR reg32,reg16 \321\2\x0F\x02\110 386,PROT +LAR reg32,reg32 \321\2\x0F\x02\110 386,PROT +LAR reg32,reg64 \321\323\2\x0F\x02\110 X64,PROT,ND +LAR reg64,mem \324\2\x0F\x02\110 X64,PROT,SW +LAR reg64,reg16 \324\2\x0F\x02\110 X64,PROT +LAR reg64,reg32 \324\2\x0F\x02\110 X64,PROT +LAR reg64,reg64 \324\2\x0F\x02\110 X64,PROT +LDS reg16,mem \320\1\xC5\110 8086,NOLONG +LDS reg32,mem \321\1\xC5\110 386,NOLONG +LEA reg16,mem \320\1\x8D\110 8086 +LEA reg32,mem \321\1\x8D\110 386 +LEA reg64,mem \324\1\x8D\110 X64 +LEAVE void \1\xC9 186 +LES reg16,mem \320\1\xC4\110 8086,NOLONG +LES reg32,mem \321\1\xC4\110 386,NOLONG +LFENCE void \3\x0F\xAE\xE8 X64,AMD +LFS reg16,mem \320\2\x0F\xB4\110 386 +LFS reg32,mem \321\2\x0F\xB4\110 386 +LGDT mem \2\x0F\x01\202 286,PRIV +LGS reg16,mem \320\2\x0F\xB5\110 386 +LGS reg32,mem \321\2\x0F\xB5\110 386 +LIDT mem \2\x0F\x01\203 286,PRIV +LLDT mem \2\x0F\x00\202 286,PROT,PRIV +LLDT mem16 \2\x0F\x00\202 286,PROT,PRIV +LLDT reg16 \2\x0F\x00\202 286,PROT,PRIV +LMSW mem \2\x0F\x01\206 286,PRIV +LMSW mem16 \2\x0F\x01\206 286,PRIV +LMSW reg16 \2\x0F\x01\206 286,PRIV +LOADALL void \2\x0F\x07 386,UNDOC +LOADALL286 void \2\x0F\x05 286,UNDOC +LODSB void \1\xAC 8086 +LODSD void \321\1\xAD 386 +LODSQ void \324\1\xAD X64 +LODSW void \320\1\xAD 8086 +LOOP imm \312\1\xE2\50 8086 +LOOP imm,reg_cx \310\1\xE2\50 8086,NOLONG +LOOP imm,reg_ecx \311\1\xE2\50 386 +LOOP imm,reg_rcx \313\1\xE2\50 X64 +LOOPE imm \312\1\xE1\50 8086 +LOOPE imm,reg_cx \310\1\xE1\50 8086,NOLONG +LOOPE imm,reg_ecx \311\1\xE1\50 386 +LOOPE imm,reg_rcx \313\1\xE1\50 X64 +LOOPNE imm \312\1\xE0\50 8086 +LOOPNE imm,reg_cx \310\1\xE0\50 8086,NOLONG +LOOPNE imm,reg_ecx \311\1\xE0\50 386 +LOOPNE imm,reg_rcx \313\1\xE0\50 X64 +LOOPNZ imm \312\1\xE0\50 8086 +LOOPNZ imm,reg_cx \310\1\xE0\50 8086,NOLONG +LOOPNZ imm,reg_ecx \311\1\xE0\50 386 +LOOPNZ imm,reg_rcx \313\1\xE0\50 X64 +LOOPZ imm \312\1\xE1\50 8086 +LOOPZ imm,reg_cx \310\1\xE1\50 8086,NOLONG +LOOPZ imm,reg_ecx \311\1\xE1\50 386 +LOOPZ imm,reg_rcx \313\1\xE1\50 X64 +LSL reg16,mem \320\2\x0F\x03\110 286,PROT,SW +LSL reg16,reg16 \320\2\x0F\x03\110 286,PROT +LSL reg16,reg32 \320\2\x0F\x03\110 386,PROT +LSL reg16,reg64 \320\323\2\x0F\x03\110 X64,PROT,ND +LSL reg32,mem \321\2\x0F\x03\110 386,PROT,SW +LSL reg32,reg16 \321\2\x0F\x03\110 386,PROT +LSL reg32,reg32 \321\2\x0F\x03\110 386,PROT +LSL reg32,reg64 \321\323\2\x0F\x03\110 X64,PROT,ND +LSL reg64,mem \324\2\x0F\x03\110 X64,PROT,SW +LSL reg64,reg16 \324\2\x0F\x03\110 X64,PROT +LSL reg64,reg32 \324\2\x0F\x03\110 X64,PROT +LSL reg64,reg64 \324\2\x0F\x03\110 X64,PROT +LSS reg16,mem \320\2\x0F\xB2\110 386 +LSS reg32,mem \321\2\x0F\xB2\110 386 +LTR mem \2\x0F\x00\203 286,PROT,PRIV +LTR mem16 \2\x0F\x00\203 286,PROT,PRIV +LTR reg16 \2\x0F\x00\203 286,PROT,PRIV +MFENCE void \3\x0F\xAE\xF0 X64,AMD +MONITOR void \3\x0F\x01\xC8 PRESCOTT +MONITOR reg_eax,reg_ecx,reg_edx \3\x0F\x01\xC8 PRESCOTT,ND +MOV mem,reg_sreg \1\x8C\101 8086,SM +MOV reg16,reg_sreg \320\1\x8C\101 8086 +MOV reg32,reg_sreg \321\1\x8C\101 386 +MOV reg_sreg,mem \1\x8E\110 8086,SM +MOV reg_sreg,reg16 \1\x8E\110 8086 +MOV reg_sreg,reg32 \1\x8E\110 386 +MOV reg_al,mem_offs \1\xA0\45 8086,SM +MOV reg_ax,mem_offs \320\1\xA1\45 8086,SM +MOV reg_eax,mem_offs \321\1\xA1\45 386,SM +MOV reg_rax,mem_offs \324\1\xA1\45 X64,SM +MOV mem_offs,reg_al \1\xA2\44 8086,SM +MOV mem_offs,reg_ax \320\1\xA3\44 8086,SM +MOV mem_offs,reg_eax \321\1\xA3\44 386,SM +MOV mem_offs,reg_rax \324\1\xA3\44 X64,SM +MOV reg32,reg_creg \334\2\x0F\x20\101 386,PRIV,NOLONG +MOV reg64,reg_creg \323\2\x0F\x20\101 X64,PRIV +MOV reg_creg,reg32 \334\2\x0F\x22\110 386,PRIV,NOLONG +MOV reg_creg,reg64 \323\2\x0F\x22\110 X64,PRIV +MOV reg32,reg_dreg \2\x0F\x21\101 386,PRIV,NOLONG +MOV reg64,reg_dreg \323\2\x0F\x21\101 X64,PRIV +MOV reg_dreg,reg32 \2\x0F\x23\110 386,PRIV,NOLONG +MOV reg_dreg,reg64 \323\2\x0F\x23\110 X64,PRIV +MOV reg32,reg_treg \2\x0F\x24\101 386,NOLONG,ND +MOV reg_treg,reg32 \2\x0F\x26\110 386,NOLONG,ND +MOV mem,reg8 \1\x88\101 8086,SM +MOV reg8,reg8 \1\x88\101 8086 +MOV mem,reg16 \320\1\x89\101 8086,SM +MOV reg16,reg16 \320\1\x89\101 8086 +MOV mem,reg32 \321\1\x89\101 386,SM +MOV reg32,reg32 \321\1\x89\101 386 +MOV mem,reg64 \324\1\x89\101 X64,SM +MOV reg64,reg64 \324\1\x89\101 X64 +MOV reg8,mem \1\x8A\110 8086,SM +MOV reg8,reg8 \1\x8A\110 8086 +MOV reg16,mem \320\1\x8B\110 8086,SM +MOV reg16,reg16 \320\1\x8B\110 8086 +MOV reg32,mem \321\1\x8B\110 386,SM +MOV reg32,reg32 \321\1\x8B\110 386 +MOV reg64,mem \324\1\x8B\110 X64,SM +MOV reg64,reg64 \324\1\x8B\110 X64 +MOV reg8,imm \10\xB0\21 8086,SM +MOV reg16,imm \320\10\xB8\31 8086,SM +MOV reg32,imm \321\10\xB8\41 386,SM +MOV reg64,imm \324\10\xB8\55 X64,SM +MOV reg64,imm32 \324\1\xC7\200\255 X64 +MOV rm8,imm \1\xC6\200\21 8086,SM +MOV rm16,imm \320\1\xC7\200\31 8086,SM +MOV rm32,imm \321\1\xC7\200\41 386,SM +MOV rm64,imm \324\1\xC7\200\255 X64,SM +MOV mem,imm8 \1\xC6\200\21 8086,SM +MOV mem,imm16 \320\1\xC7\200\31 8086,SM +MOV mem,imm32 \321\1\xC7\200\41 386,SM +MOVD mmxreg,mem \360\2\x0F\x6E\110 PENT,MMX,SD +MOVD mmxreg,reg32 \360\2\x0F\x6E\110 PENT,MMX +MOVD mem,mmxreg \360\2\x0F\x7E\101 PENT,MMX,SD +MOVD reg32,mmxreg \360\2\x0F\x7E\101 PENT,MMX +MOVD xmmreg,mem \360\320\2\x0F\x6E\110 X64,SD +MOVD xmmreg,reg32 \360\320\2\x0F\x6E\110 X64 +MOVD mem,xmmreg \360\320\2\x0F\x7E\101 X64,SD +MOVD reg32,xmmreg \360\320\2\x0F\x7E\101 X64,SSE +MOVQ mmxreg,mmxrm \360\323\2\x0F\x6F\110 PENT,MMX,SQ +MOVQ mmxrm,mmxreg \360\323\2\x0F\x7F\101 PENT,MMX,SQ +MOVQ mmxreg,rm64 \360\2\x0F\x6E\110 X64,MMX +MOVQ rm64,mmxreg \360\2\x0F\x7E\101 X64,MMX +MOVSB void \1\xA4 8086 +MOVSD void \321\1\xA5 386 +MOVSQ void \324\1\xA5 X64 +MOVSW void \320\1\xA5 8086 +MOVSX reg16,mem \320\2\x0F\xBE\110 386,SB +MOVSX reg16,reg8 \320\2\x0F\xBE\110 386 +MOVSX reg32,rm8 \321\2\x0F\xBE\110 386 +MOVSX reg32,rm16 \321\2\x0F\xBF\110 386 +MOVSX reg64,rm8 \324\2\x0F\xBE\110 X64 +MOVSX reg64,rm16 \324\2\x0F\xBF\110 X64 +MOVSXD reg64,rm32 \324\1\x63\110 X64 +MOVSX reg64,rm32 \324\1\x63\110 X64,ND +MOVZX reg16,mem \320\2\x0F\xB6\110 386,SB +MOVZX reg16,reg8 \320\2\x0F\xB6\110 386 +MOVZX reg32,rm8 \321\2\x0F\xB6\110 386 +MOVZX reg32,rm16 \321\2\x0F\xB7\110 386 +MOVZX reg64,rm8 \324\2\x0F\xB6\110 X64 +MOVZX reg64,rm16 \324\2\x0F\xB7\110 X64 +MUL rm8 \1\xF6\204 8086 +MUL rm16 \320\1\xF7\204 8086 +MUL rm32 \321\1\xF7\204 386 +MUL rm64 \324\1\xF7\204 X64 +MWAIT void \3\x0F\x01\xC9 PRESCOTT +MWAIT reg_eax,reg_ecx \3\x0F\x01\xC9 PRESCOTT,ND +NEG rm8 \1\xF6\203 8086 +NEG rm16 \320\1\xF7\203 8086 +NEG rm32 \321\1\xF7\203 386 +NEG rm64 \324\1\xF7\203 X64 +NOP void \314\1\x90 8086 +NOP rm16 \320\2\x0F\x1F\200 P6 +NOP rm32 \321\2\x0F\x1F\200 P6 +NOP rm64 \324\2\x0F\x1F\200 X64 +NOT rm8 \1\xF6\202 8086 +NOT rm16 \320\1\xF7\202 8086 +NOT rm32 \321\1\xF7\202 386 +NOT rm64 \324\1\xF7\202 X64 +OR mem,reg8 \1\x08\101 8086,SM +OR reg8,reg8 \1\x08\101 8086 +OR mem,reg16 \320\1\x09\101 8086,SM +OR reg16,reg16 \320\1\x09\101 8086 +OR mem,reg32 \321\1\x09\101 386,SM +OR reg32,reg32 \321\1\x09\101 386 +OR mem,reg64 \324\1\x09\101 X64,SM +OR reg64,reg64 \324\1\x09\101 X64 +OR reg8,mem \1\x0A\110 8086,SM +OR reg8,reg8 \1\x0A\110 8086 +OR reg16,mem \320\1\x0B\110 8086,SM +OR reg16,reg16 \320\1\x0B\110 8086 +OR reg32,mem \321\1\x0B\110 386,SM +OR reg32,reg32 \321\1\x0B\110 386 +OR reg64,mem \324\1\x0B\110 X64,SM +OR reg64,reg64 \324\1\x0B\110 X64 +OR rm16,imm8 \320\1\x83\201\275 8086 +OR rm32,imm8 \321\1\x83\201\275 386 +OR rm64,imm8 \324\1\x83\201\275 X64 +OR reg_al,imm \1\x0C\21 8086,SM +OR reg_ax,sbyte16 \320\1\x83\201\275 8086,SM +OR reg_ax,imm \320\1\x0D\31 8086,SM +OR reg_eax,sbyte32 \321\1\x83\201\275 386,SM +OR reg_eax,imm \321\1\x0D\41 386,SM +OR reg_rax,sbyte64 \324\1\x83\201\275 X64,SM +OR reg_rax,imm \324\1\x0D\255 X64,SM +OR rm8,imm \1\x80\201\21 8086,SM +OR rm16,imm \320\145\x81\201\141 8086,SM +OR rm32,imm \321\155\x81\201\151 386,SM +OR rm64,imm \324\155\x81\201\251 X64,SM +OR mem,imm8 \1\x80\201\21 8086,SM +OR mem,imm16 \320\145\x81\201\141 8086,SM +OR mem,imm32 \321\155\x81\201\151 386,SM +OUT imm,reg_al \1\xE6\24 8086,SB +OUT imm,reg_ax \320\1\xE7\24 8086,SB +OUT imm,reg_eax \321\1\xE7\24 386,SB +OUT reg_dx,reg_al \1\xEE 8086 +OUT reg_dx,reg_ax \320\1\xEF 8086 +OUT reg_dx,reg_eax \321\1\xEF 386 +OUTSB void \1\x6E 186 +OUTSD void \321\1\x6F 386 +OUTSW void \320\1\x6F 186 +PACKSSDW mmxreg,mmxrm \360\323\2\x0F\x6B\110 PENT,MMX,SQ +PACKSSWB mmxreg,mmxrm \360\323\2\x0F\x63\110 PENT,MMX,SQ +PACKUSWB mmxreg,mmxrm \360\323\2\x0F\x67\110 PENT,MMX,SQ +PADDB mmxreg,mmxrm \360\323\2\x0F\xFC\110 PENT,MMX,SQ +PADDD mmxreg,mmxrm \360\323\2\x0F\xFE\110 PENT,MMX,SQ +PADDSB mmxreg,mmxrm \360\323\2\x0F\xEC\110 PENT,MMX,SQ +PADDSIW mmxreg,mmxrm \323\2\x0F\x51\110 PENT,MMX,SQ,CYRIX +PADDSW mmxreg,mmxrm \360\323\2\x0F\xED\110 PENT,MMX,SQ +PADDUSB mmxreg,mmxrm \360\323\2\x0F\xDC\110 PENT,MMX,SQ +PADDUSW mmxreg,mmxrm \360\323\2\x0F\xDD\110 PENT,MMX,SQ +PADDW mmxreg,mmxrm \360\323\2\x0F\xFD\110 PENT,MMX,SQ +PAND mmxreg,mmxrm \360\323\2\x0F\xDB\110 PENT,MMX,SQ +PANDN mmxreg,mmxrm \360\323\2\x0F\xDF\110 PENT,MMX,SQ +PAUSE void \314\333\1\x90 8086 +PAVEB mmxreg,mmxrm \323\2\x0F\x50\110 PENT,MMX,SQ,CYRIX +PAVGUSB mmxreg,mmxrm \323\2\x0F\x0F\110\01\xBF PENT,3DNOW,SQ +PCMPEQB mmxreg,mmxrm \360\323\2\x0F\x74\110 PENT,MMX,SQ +PCMPEQD mmxreg,mmxrm \360\323\2\x0F\x76\110 PENT,MMX,SQ +PCMPEQW mmxreg,mmxrm \360\323\2\x0F\x75\110 PENT,MMX,SQ +PCMPGTB mmxreg,mmxrm \360\323\2\x0F\x64\110 PENT,MMX,SQ +PCMPGTD mmxreg,mmxrm \360\323\2\x0F\x66\110 PENT,MMX,SQ +PCMPGTW mmxreg,mmxrm \360\323\2\x0F\x65\110 PENT,MMX,SQ +PDISTIB mmxreg,mem \2\x0F\x54\110 PENT,MMX,SM,CYRIX +PF2ID mmxreg,mmxrm \323\2\x0F\x0F\110\01\x1D PENT,3DNOW,SQ +PFACC mmxreg,mmxrm \323\2\x0F\x0F\110\01\xAE PENT,3DNOW,SQ +PFADD mmxreg,mmxrm \323\2\x0F\x0F\110\01\x9E PENT,3DNOW,SQ +PFCMPEQ mmxreg,mmxrm \323\2\x0F\x0F\110\01\xB0 PENT,3DNOW,SQ +PFCMPGE mmxreg,mmxrm \323\2\x0F\x0F\110\01\x90 PENT,3DNOW,SQ +PFCMPGT mmxreg,mmxrm \323\2\x0F\x0F\110\01\xA0 PENT,3DNOW,SQ +PFMAX mmxreg,mmxrm \323\2\x0F\x0F\110\01\xA4 PENT,3DNOW,SQ +PFMIN mmxreg,mmxrm \323\2\x0F\x0F\110\01\x94 PENT,3DNOW,SQ +PFMUL mmxreg,mmxrm \323\2\x0F\x0F\110\01\xB4 PENT,3DNOW,SQ +PFRCP mmxreg,mmxrm \323\2\x0F\x0F\110\01\x96 PENT,3DNOW,SQ +PFRCPIT1 mmxreg,mmxrm \323\2\x0F\x0F\110\01\xA6 PENT,3DNOW,SQ +PFRCPIT2 mmxreg,mmxrm \323\2\x0F\x0F\110\01\xB6 PENT,3DNOW,SQ +PFRSQIT1 mmxreg,mmxrm \323\2\x0F\x0F\110\01\xA7 PENT,3DNOW,SQ +PFRSQRT mmxreg,mmxrm \323\2\x0F\x0F\110\01\x97 PENT,3DNOW,SQ +PFSUB mmxreg,mmxrm \323\2\x0F\x0F\110\01\x9A PENT,3DNOW,SQ +PFSUBR mmxreg,mmxrm \323\2\x0F\x0F\110\01\xAA PENT,3DNOW,SQ +PI2FD mmxreg,mmxrm \323\2\x0F\x0F\110\01\x0D PENT,3DNOW,SQ +PMACHRIW mmxreg,mem \2\x0F\x5E\110 PENT,MMX,SM,CYRIX +PMADDWD mmxreg,mmxrm \360\323\2\x0F\xF5\110 PENT,MMX,SQ +PMAGW mmxreg,mmxrm \323\2\x0F\x52\110 PENT,MMX,SQ,CYRIX +PMULHRIW mmxreg,mmxrm \323\2\x0F\x5D\110 PENT,MMX,SQ,CYRIX +PMULHRWA mmxreg,mmxrm \323\2\x0F\x0F\110\1\xB7 PENT,3DNOW,SQ +PMULHRWC mmxreg,mmxrm \323\2\x0F\x59\110 PENT,MMX,SQ,CYRIX +PMULHW mmxreg,mmxrm \360\323\2\x0F\xE5\110 PENT,MMX,SQ +PMULLW mmxreg,mmxrm \360\323\2\x0F\xD5\110 PENT,MMX,SQ +PMVGEZB mmxreg,mem \2\x0F\x5C\110 PENT,MMX,SQ,CYRIX +PMVLZB mmxreg,mem \2\x0F\x5B\110 PENT,MMX,SQ,CYRIX +PMVNZB mmxreg,mem \2\x0F\x5A\110 PENT,MMX,SQ,CYRIX +PMVZB mmxreg,mem \2\x0F\x58\110 PENT,MMX,SQ,CYRIX +POP reg16 \320\10\x58 8086 +POP reg32 \321\10\x58 386,NOLONG +POP reg64 \323\10\x58 X64 +POP rm16 \320\1\x8F\200 8086 +POP rm32 \321\1\x8F\200 386,NOLONG +POP rm64 \323\1\x8F\200 X64 +POP reg_cs \1\x0F 8086,UNDOC,ND +POP reg_dess \345 8086,NOLONG +POP reg_fsgs \1\x0F\347 386 +POPA void \322\1\x61 186,NOLONG +POPAD void \321\1\x61 386,NOLONG +POPAW void \320\1\x61 186,NOLONG +POPF void \322\1\x9D 8086 +POPFD void \321\1\x9D 386,NOLONG +POPFQ void \321\1\x9D X64 +POPFW void \320\1\x9D 8086 +POR mmxreg,mmxrm \360\323\2\x0F\xEB\110 PENT,MMX,SQ +PREFETCH mem \2\x0F\x0D\200 PENT,3DNOW,SQ +PREFETCHW mem \2\x0F\x0D\201 PENT,3DNOW,SQ +PSLLD mmxreg,mmxrm \360\323\2\x0F\xF2\110 PENT,MMX,SQ +PSLLD mmxreg,imm \360\2\x0F\x72\206\25 PENT,MMX +PSLLQ mmxreg,mmxrm \360\323\2\x0F\xF3\110 PENT,MMX,SQ +PSLLQ mmxreg,imm \360\2\x0F\x73\206\25 PENT,MMX +PSLLW mmxreg,mmxrm \360\323\2\x0F\xF1\110 PENT,MMX,SQ +PSLLW mmxreg,imm \360\2\x0F\x71\206\25 PENT,MMX +PSRAD mmxreg,mmxrm \360\323\2\x0F\xE2\110 PENT,MMX,SQ +PSRAD mmxreg,imm \360\2\x0F\x72\204\25 PENT,MMX +PSRAW mmxreg,mmxrm \360\323\2\x0F\xE1\110 PENT,MMX,SQ +PSRAW mmxreg,imm \360\2\x0F\x71\204\25 PENT,MMX +PSRLD mmxreg,mmxrm \360\323\2\x0F\xD2\110 PENT,MMX,SQ +PSRLD mmxreg,imm \360\2\x0F\x72\202\25 PENT,MMX +PSRLQ mmxreg,mmxrm \360\323\2\x0F\xD3\110 PENT,MMX,SQ +PSRLQ mmxreg,imm \360\2\x0F\x73\202\25 PENT,MMX +PSRLW mmxreg,mmxrm \360\323\2\x0F\xD1\110 PENT,MMX,SQ +PSRLW mmxreg,imm \360\2\x0F\x71\202\25 PENT,MMX +PSUBB mmxreg,mmxrm \360\323\2\x0F\xF8\110 PENT,MMX,SQ +PSUBD mmxreg,mmxrm \360\323\2\x0F\xFA\110 PENT,MMX,SQ +PSUBSB mmxreg,mmxrm \360\323\2\x0F\xE8\110 PENT,MMX,SQ +PSUBSIW mmxreg,mmxrm \323\2\x0F\x55\110 PENT,MMX,SQ,CYRIX +PSUBSW mmxreg,mmxrm \360\323\2\x0F\xE9\110 PENT,MMX,SQ +PSUBUSB mmxreg,mmxrm \360\323\2\x0F\xD8\110 PENT,MMX,SQ +PSUBUSW mmxreg,mmxrm \360\323\2\x0F\xD9\110 PENT,MMX,SQ +PSUBW mmxreg,mmxrm \360\323\2\x0F\xF9\110 PENT,MMX,SQ +PUNPCKHBW mmxreg,mmxrm \360\323\2\x0F\x68\110 PENT,MMX,SQ +PUNPCKHDQ mmxreg,mmxrm \360\323\2\x0F\x6A\110 PENT,MMX,SQ +PUNPCKHWD mmxreg,mmxrm \360\323\2\x0F\x69\110 PENT,MMX,SQ +PUNPCKLBW mmxreg,mmxrm \360\323\2\x0F\x60\110 PENT,MMX,SQ +PUNPCKLDQ mmxreg,mmxrm \360\323\2\x0F\x62\110 PENT,MMX,SQ +PUNPCKLWD mmxreg,mmxrm \360\323\2\x0F\x61\110 PENT,MMX,SQ +PUSH reg16 \320\10\x50 8086 +PUSH reg32 \321\10\x50 386,NOLONG +PUSH reg64 \323\10\x50 X64 +PUSH rm16 \320\1\xFF\206 8086 +PUSH rm32 \321\1\xFF\206 386,NOLONG +PUSH rm64 \323\1\xFF\206 X64 +PUSH reg_cs \344 8086,NOLONG +PUSH reg_dess \344 8086,NOLONG +PUSH reg_fsgs \1\x0F\346 386 +PUSH imm8 \1\x6A\274 186 +PUSH imm16 \320\144\x68\140 186,AR0,SZ +PUSH imm32 \321\154\x68\150 386,NOLONG,AR0,SZ +PUSH imm32 \321\154\x68\150 386,NOLONG,SD +PUSH imm64 \323\154\x68\250 X64,AR0,SZ +PUSHA void \322\1\x60 186,NOLONG +PUSHAD void \321\1\x60 386,NOLONG +PUSHAW void \320\1\x60 186,NOLONG +PUSHF void \322\1\x9C 8086 +PUSHFD void \321\1\x9C 386,NOLONG +PUSHFQ void \321\1\x9C X64 +PUSHFW void \320\1\x9C 8086 +PXOR mmxreg,mmxrm \360\323\2\x0F\xEF\110 PENT,MMX,SQ +RCL rm8,unity \1\xD0\202 8086 +RCL rm8,reg_cl \1\xD2\202 8086 +RCL rm8,imm \1\xC0\202\25 186,SB +RCL rm16,unity \320\1\xD1\202 8086 +RCL rm16,reg_cl \320\1\xD3\202 8086 +RCL rm16,imm \320\1\xC1\202\25 186,SB +RCL rm32,unity \321\1\xD1\202 386 +RCL rm32,reg_cl \321\1\xD3\202 386 +RCL rm32,imm \321\1\xC1\202\25 386,SB +RCL rm64,unity \324\1\xD1\202 X64 +RCL rm64,reg_cl \324\1\xD3\202 X64 +RCL rm64,imm \324\1\xC1\202\25 X64,SB +RCR rm8,unity \1\xD0\203 8086 +RCR rm8,reg_cl \1\xD2\203 8086 +RCR rm8,imm \1\xC0\203\25 186,SB +RCR rm16,unity \320\1\xD1\203 8086 +RCR rm16,reg_cl \320\1\xD3\203 8086 +RCR rm16,imm \320\1\xC1\203\25 186,SB +RCR rm32,unity \321\1\xD1\203 386 +RCR rm32,reg_cl \321\1\xD3\203 386 +RCR rm32,imm \321\1\xC1\203\25 386,SB +RCR rm64,unity \324\1\xD1\203 X64 +RCR rm64,reg_cl \324\1\xD3\203 X64 +RCR rm64,imm \324\1\xC1\203\25 X64,SB +RDSHR rm32 \321\2\x0F\x36\200 P6,CYRIX,SMM +RDMSR void \2\x0F\x32 PENT,PRIV +RDPMC void \2\x0F\x33 P6 +RDTSC void \2\x0F\x31 PENT +RDTSCP void \3\x0F\x01\xF9 X86_64 +RET void \1\xC3 8086 +RET imm \1\xC2\30 8086,SW +RETF void \1\xCB 8086 +RETF imm \1\xCA\30 8086,SW +RETN void \1\xC3 8086 +RETN imm \1\xC2\30 8086,SW +ROL rm8,unity \1\xD0\200 8086 +ROL rm8,reg_cl \1\xD2\200 8086 +ROL rm8,imm \1\xC0\200\25 186,SB +ROL rm16,unity \320\1\xD1\200 8086 +ROL rm16,reg_cl \320\1\xD3\200 8086 +ROL rm16,imm \320\1\xC1\200\25 186,SB +ROL rm32,unity \321\1\xD1\200 386 +ROL rm32,reg_cl \321\1\xD3\200 386 +ROL rm32,imm \321\1\xC1\200\25 386,SB +ROL rm64,unity \324\1\xD1\200 X64 +ROL rm64,reg_cl \324\1\xD3\200 X64 +ROL rm64,imm \324\1\xC1\200\25 X64,SB +ROR rm8,unity \1\xD0\201 8086 +ROR rm8,reg_cl \1\xD2\201 8086 +ROR rm8,imm \1\xC0\201\25 186,SB +ROR rm16,unity \320\1\xD1\201 8086 +ROR rm16,reg_cl \320\1\xD3\201 8086 +ROR rm16,imm \320\1\xC1\201\25 186,SB +ROR rm32,unity \321\1\xD1\201 386 +ROR rm32,reg_cl \321\1\xD3\201 386 +ROR rm32,imm \321\1\xC1\201\25 386,SB +ROR rm64,unity \324\1\xD1\201 X64 +ROR rm64,reg_cl \324\1\xD3\201 X64 +ROR rm64,imm \324\1\xC1\201\25 X64,SB +RDM void \2\x0F\x3A P6,CYRIX,ND +RSDC reg_sreg,mem80 \2\x0F\x79\110 486,CYRIX,SMM +RSLDT mem80 \2\x0F\x7B\200 486,CYRIX,SMM +RSM void \2\x0F\xAA PENT,SMM +RSTS mem80 \2\x0F\x7D\200 486,CYRIX,SMM +SAHF void \1\x9E 8086 +SAL rm8,unity \1\xD0\204 8086,ND +SAL rm8,reg_cl \1\xD2\204 8086,ND +SAL rm8,imm \1\xC0\204\25 186,ND,SB +SAL rm16,unity \320\1\xD1\204 8086,ND +SAL rm16,reg_cl \320\1\xD3\204 8086,ND +SAL rm16,imm \320\1\xC1\204\25 186,ND,SB +SAL rm32,unity \321\1\xD1\204 386,ND +SAL rm32,reg_cl \321\1\xD3\204 386,ND +SAL rm32,imm \321\1\xC1\204\25 386,ND,SB +SAL rm64,unity \324\1\xD1\204 X64,ND +SAL rm64,reg_cl \324\1\xD3\204 X64,ND +SAL rm64,imm \324\1\xC1\204\25 X64,ND,SB +SALC void \1\xD6 8086,UNDOC +SAR rm8,unity \1\xD0\207 8086 +SAR rm8,reg_cl \1\xD2\207 8086 +SAR rm8,imm \1\xC0\207\25 186,SB +SAR rm16,unity \320\1\xD1\207 8086 +SAR rm16,reg_cl \320\1\xD3\207 8086 +SAR rm16,imm \320\1\xC1\207\25 186,SB +SAR rm32,unity \321\1\xD1\207 386 +SAR rm32,reg_cl \321\1\xD3\207 386 +SAR rm32,imm \321\1\xC1\207\25 386,SB +SAR rm64,unity \324\1\xD1\207 X64 +SAR rm64,reg_cl \324\1\xD3\207 X64 +SAR rm64,imm \324\1\xC1\207\25 X64,SB +SBB mem,reg8 \1\x18\101 8086,SM +SBB reg8,reg8 \1\x18\101 8086 +SBB mem,reg16 \320\1\x19\101 8086,SM +SBB reg16,reg16 \320\1\x19\101 8086 +SBB mem,reg32 \321\1\x19\101 386,SM +SBB reg32,reg32 \321\1\x19\101 386 +SBB mem,reg64 \324\1\x19\101 X64,SM +SBB reg64,reg64 \324\1\x19\101 X64 +SBB reg8,mem \1\x1A\110 8086,SM +SBB reg8,reg8 \1\x1A\110 8086 +SBB reg16,mem \320\1\x1B\110 8086,SM +SBB reg16,reg16 \320\1\x1B\110 8086 +SBB reg32,mem \321\1\x1B\110 386,SM +SBB reg32,reg32 \321\1\x1B\110 386 +SBB reg64,mem \324\1\x1B\110 X64,SM +SBB reg64,reg64 \324\1\x1B\110 X64 +SBB rm16,imm8 \320\1\x83\203\275 8086 +SBB rm32,imm8 \321\1\x83\203\275 386 +SBB rm64,imm8 \324\1\x83\203\275 X64 +SBB reg_al,imm \1\x1C\21 8086,SM +SBB reg_ax,sbyte16 \320\1\x83\203\275 8086,SM +SBB reg_ax,imm \320\1\x1D\31 8086,SM +SBB reg_eax,sbyte32 \321\1\x83\203\275 386,SM +SBB reg_eax,imm \321\1\x1D\41 386,SM +SBB reg_rax,sbyte64 \324\1\x83\203\275 X64,SM +SBB reg_rax,imm \324\1\x1D\255 X64,SM +SBB rm8,imm \1\x80\203\21 8086,SM +SBB rm16,imm \320\145\x81\203\141 8086,SM +SBB rm32,imm \321\155\x81\203\151 386,SM +SBB rm64,imm \324\155\x81\203\251 X64,SM +SBB mem,imm8 \1\x80\203\21 8086,SM +SBB mem,imm16 \320\145\x81\203\141 8086,SM +SBB mem,imm32 \321\155\x81\203\151 386,SM +SCASB void \335\1\xAE 8086 +SCASD void \335\321\1\xAF 386 +SCASQ void \335\324\1\xAF X64 +SCASW void \335\320\1\xAF 8086 +SFENCE void \3\x0F\xAE\xF8 X64,AMD +SGDT mem \2\x0F\x01\200 286 +SHL rm8,unity \1\xD0\204 8086 +SHL rm8,reg_cl \1\xD2\204 8086 +SHL rm8,imm \1\xC0\204\25 186,SB +SHL rm16,unity \320\1\xD1\204 8086 +SHL rm16,reg_cl \320\1\xD3\204 8086 +SHL rm16,imm \320\1\xC1\204\25 186,SB +SHL rm32,unity \321\1\xD1\204 386 +SHL rm32,reg_cl \321\1\xD3\204 386 +SHL rm32,imm \321\1\xC1\204\25 386,SB +SHL rm64,unity \324\1\xD1\204 X64 +SHL rm64,reg_cl \324\1\xD3\204 X64 +SHL rm64,imm \324\1\xC1\204\25 X64,SB +SHLD mem,reg16,imm \320\2\x0F\xA4\101\26 386,SM2,SB,AR2 +SHLD reg16,reg16,imm \320\2\x0F\xA4\101\26 386,SM2,SB,AR2 +SHLD mem,reg32,imm \321\2\x0F\xA4\101\26 386,SM2,SB,AR2 +SHLD reg32,reg32,imm \321\2\x0F\xA4\101\26 386,SM2,SB,AR2 +SHLD mem,reg64,imm \324\2\x0F\xA4\101\26 X64,SM2,SB,AR2 +SHLD reg64,reg64,imm \324\2\x0F\xA4\101\26 X64,SM2,SB,AR2 +SHLD mem,reg16,reg_cl \320\2\x0F\xA5\101 386,SM +SHLD reg16,reg16,reg_cl \320\2\x0F\xA5\101 386 +SHLD mem,reg32,reg_cl \321\2\x0F\xA5\101 386,SM +SHLD reg32,reg32,reg_cl \321\2\x0F\xA5\101 386 +SHLD mem,reg64,reg_cl \324\2\x0F\xA5\101 X64,SM +SHLD reg64,reg64,reg_cl \324\2\x0F\xA5\101 X64 +SHR rm8,unity \1\xD0\205 8086 +SHR rm8,reg_cl \1\xD2\205 8086 +SHR rm8,imm \1\xC0\205\25 186,SB +SHR rm16,unity \320\1\xD1\205 8086 +SHR rm16,reg_cl \320\1\xD3\205 8086 +SHR rm16,imm \320\1\xC1\205\25 186,SB +SHR rm32,unity \321\1\xD1\205 386 +SHR rm32,reg_cl \321\1\xD3\205 386 +SHR rm32,imm \321\1\xC1\205\25 386,SB +SHR rm64,unity \324\1\xD1\205 X64 +SHR rm64,reg_cl \324\1\xD3\205 X64 +SHR rm64,imm \324\1\xC1\205\25 X64,SB +SHRD mem,reg16,imm \320\2\x0F\xAC\101\26 386,SM2,SB,AR2 +SHRD reg16,reg16,imm \320\2\x0F\xAC\101\26 386,SM2,SB,AR2 +SHRD mem,reg32,imm \321\2\x0F\xAC\101\26 386,SM2,SB,AR2 +SHRD reg32,reg32,imm \321\2\x0F\xAC\101\26 386,SM2,SB,AR2 +SHRD mem,reg64,imm \324\2\x0F\xAC\101\26 X64,SM2,SB,AR2 +SHRD reg64,reg64,imm \324\2\x0F\xAC\101\26 X64,SM2,SB,AR2 +SHRD mem,reg16,reg_cl \320\2\x0F\xAD\101 386,SM +SHRD reg16,reg16,reg_cl \320\2\x0F\xAD\101 386 +SHRD mem,reg32,reg_cl \321\2\x0F\xAD\101 386,SM +SHRD reg32,reg32,reg_cl \321\2\x0F\xAD\101 386 +SHRD mem,reg64,reg_cl \324\2\x0F\xAD\101 X64,SM +SHRD reg64,reg64,reg_cl \324\2\x0F\xAD\101 X64 +SIDT mem \2\x0F\x01\201 286 +SLDT mem \2\x0F\x00\200 286 +SLDT mem16 \2\x0F\x00\200 286 +SLDT reg16 \320\2\x0F\x00\200 286 +SLDT reg32 \321\2\x0F\x00\200 386 +SLDT reg64 \323\2\x0F\x00\200 X64,ND +SLDT reg64 \324\2\x0F\x00\200 X64 +SKINIT void \3\x0F\x01\xDE X64 +SMI void \1\xF1 386,UNDOC +SMINT void \2\x0F\x38 P6,CYRIX,ND +; Older Cyrix chips had this; they had to move due to conflict with MMX +SMINTOLD void \2\x0F\x7E 486,CYRIX,ND +SMSW mem \2\x0F\x01\204 286 +SMSW mem16 \2\x0F\x01\204 286 +SMSW reg16 \320\2\x0F\x01\204 286 +SMSW reg32 \321\2\x0F\x01\204 386 +STC void \1\xF9 8086 +STD void \1\xFD 8086 +STGI void \3\x0F\x01\xDC X64 +STI void \1\xFB 8086 +STOSB void \1\xAA 8086 +STOSD void \321\1\xAB 386 +STOSQ void \324\1\xAB X64 +STOSW void \320\1\xAB 8086 +STR mem \2\x0F\x00\201 286,PROT +STR mem16 \2\x0F\x00\201 286,PROT +STR reg16 \320\2\x0F\x00\201 286,PROT +STR reg32 \321\2\x0F\x00\201 386,PROT +STR reg64 \324\2\x0F\x00\201 X64 +SUB mem,reg8 \1\x28\101 8086,SM +SUB reg8,reg8 \1\x28\101 8086 +SUB mem,reg16 \320\1\x29\101 8086,SM +SUB reg16,reg16 \320\1\x29\101 8086 +SUB mem,reg32 \321\1\x29\101 386,SM +SUB reg32,reg32 \321\1\x29\101 386 +SUB mem,reg64 \324\1\x29\101 X64,SM +SUB reg64,reg64 \324\1\x29\101 X64 +SUB reg8,mem \1\x2A\110 8086,SM +SUB reg8,reg8 \1\x2A\110 8086 +SUB reg16,mem \320\1\x2B\110 8086,SM +SUB reg16,reg16 \320\1\x2B\110 8086 +SUB reg32,mem \321\1\x2B\110 386,SM +SUB reg32,reg32 \321\1\x2B\110 386 +SUB reg64,mem \324\1\x2B\110 X64,SM +SUB reg64,reg64 \324\1\x2B\110 X64 +SUB rm16,imm8 \320\1\x83\205\275 8086 +SUB rm32,imm8 \321\1\x83\205\275 386 +SUB rm64,imm8 \324\1\x83\205\275 X64 +SUB reg_al,imm \1\x2C\21 8086,SM +SUB reg_ax,sbyte16 \320\1\x83\205\275 8086,SM +SUB reg_ax,imm \320\1\x2D\31 8086,SM +SUB reg_eax,sbyte32 \321\1\x83\205\275 386,SM +SUB reg_eax,imm \321\1\x2D\41 386,SM +SUB reg_rax,sbyte64 \324\1\x83\205\275 X64,SM +SUB reg_rax,imm \324\1\x2D\255 X64,SM +SUB rm8,imm \1\x80\205\21 8086,SM +SUB rm16,imm \320\145\x81\205\141 8086,SM +SUB rm32,imm \321\155\x81\205\151 386,SM +SUB rm64,imm \324\155\x81\205\251 X64,SM +SUB mem,imm8 \1\x80\205\21 8086,SM +SUB mem,imm16 \320\145\x81\205\141 8086,SM +SUB mem,imm32 \321\155\x81\205\151 386,SM +SVDC mem80,reg_sreg \2\x0F\x78\101 486,CYRIX,SMM +SVLDT mem80 \2\x0F\x7A\200 486,CYRIX,SMM,ND +SVTS mem80 \2\x0F\x7C\200 486,CYRIX,SMM +SWAPGS void \3\x0F\x01\xF8 X64 +SYSCALL void \2\x0F\x05 P6,AMD +SYSENTER void \2\x0F\x34 P6 +SYSEXIT void \2\x0F\x35 P6,PRIV +SYSRET void \2\x0F\x07 P6,PRIV,AMD +TEST mem,reg8 \1\x84\101 8086,SM +TEST reg8,reg8 \1\x84\101 8086 +TEST mem,reg16 \320\1\x85\101 8086,SM +TEST reg16,reg16 \320\1\x85\101 8086 +TEST mem,reg32 \321\1\x85\101 386,SM +TEST reg32,reg32 \321\1\x85\101 386 +TEST mem,reg64 \324\1\x85\101 X64,SM +TEST reg64,reg64 \324\1\x85\101 X64 +TEST reg8,mem \1\x84\110 8086,SM +TEST reg16,mem \320\1\x85\110 8086,SM +TEST reg32,mem \321\1\x85\110 386,SM +TEST reg64,mem \324\1\x85\110 X64,SM +TEST reg_al,imm \1\xA8\21 8086,SM +TEST reg_ax,imm \320\1\xA9\31 8086,SM +TEST reg_eax,imm \321\1\xA9\41 386,SM +TEST reg_rax,imm \324\1\xA9\255 X64,SM +TEST rm8,imm \1\xF6\200\21 8086,SM +TEST rm16,imm \320\1\xF7\200\31 8086,SM +TEST rm32,imm \321\1\xF7\200\41 386,SM +TEST rm64,imm \324\1\xF7\200\255 X64,SM +TEST mem,imm8 \1\xF6\200\21 8086,SM +TEST mem,imm16 \320\1\xF7\200\31 8086,SM +TEST mem,imm32 \321\1\xF7\200\41 386,SM +UD0 void \2\x0F\xFF 186,UNDOC +UD1 void \2\x0F\xB9 186,UNDOC +UD2B void \2\x0F\xB9 186,UNDOC,ND +UD2 void \2\x0F\x0B 186 +UD2A void \2\x0F\x0B 186,ND +UMOV mem,reg8 \360\2\x0F\x10\101 386,UNDOC,SM,ND +UMOV reg8,reg8 \360\2\x0F\x10\101 386,UNDOC,ND +UMOV mem,reg16 \360\320\2\x0F\x11\101 386,UNDOC,SM,ND +UMOV reg16,reg16 \360\320\2\x0F\x11\101 386,UNDOC,ND +UMOV mem,reg32 \360\321\2\x0F\x11\101 386,UNDOC,SM,ND +UMOV reg32,reg32 \360\321\2\x0F\x11\101 386,UNDOC,ND +UMOV reg8,mem \360\2\x0F\x12\110 386,UNDOC,SM,ND +UMOV reg8,reg8 \360\2\x0F\x12\110 386,UNDOC,ND +UMOV reg16,mem \360\320\2\x0F\x13\110 386,UNDOC,SM,ND +UMOV reg16,reg16 \360\320\2\x0F\x13\110 386,UNDOC,ND +UMOV reg32,mem \360\321\2\x0F\x13\110 386,UNDOC,SM,ND +UMOV reg32,reg32 \360\321\2\x0F\x13\110 386,UNDOC,ND +VERR mem \2\x0F\x00\204 286,PROT +VERR mem16 \2\x0F\x00\204 286,PROT +VERR reg16 \2\x0F\x00\204 286,PROT +VERW mem \2\x0F\x00\205 286,PROT +VERW mem16 \2\x0F\x00\205 286,PROT +VERW reg16 \2\x0F\x00\205 286,PROT +FWAIT void \341 8086 +WBINVD void \2\x0F\x09 486,PRIV +WRSHR rm32 \321\2\x0F\x37\200 P6,CYRIX,SMM +WRMSR void \2\x0F\x30 PENT,PRIV +XADD mem,reg8 \2\x0F\xC0\101 486,SM +XADD reg8,reg8 \2\x0F\xC0\101 486 +XADD mem,reg16 \320\2\x0F\xC1\101 486,SM +XADD reg16,reg16 \320\2\x0F\xC1\101 486 +XADD mem,reg32 \321\2\x0F\xC1\101 486,SM +XADD reg32,reg32 \321\2\x0F\xC1\101 486 +XADD mem,reg64 \324\2\x0F\xC1\101 X64,SM +XADD reg64,reg64 \324\2\x0F\xC1\101 X64 +XBTS reg16,mem \320\2\x0F\xA6\110 386,SW,UNDOC,ND +XBTS reg16,reg16 \320\2\x0F\xA6\110 386,UNDOC,ND +XBTS reg32,mem \321\2\x0F\xA6\110 386,SD,UNDOC,ND +XBTS reg32,reg32 \321\2\x0F\xA6\110 386,UNDOC,ND +XCHG reg_ax,reg16 \320\11\x90 8086 +XCHG reg_eax,reg32na \321\11\x90 386 +XCHG reg_rax,reg64 \324\11\x90 X64 +XCHG reg16,reg_ax \320\10\x90 8086 +XCHG reg32na,reg_eax \321\10\x90 386 +XCHG reg64,reg_rax \324\10\x90 X64 +; This must be NOLONG since opcode 90 is NOP, and in 64-bit mode +; "xchg eax,eax" is *not* a NOP. +XCHG reg_eax,reg_eax \321\1\x90 386,NOLONG +XCHG reg8,mem \1\x86\110 8086,SM +XCHG reg8,reg8 \1\x86\110 8086 +XCHG reg16,mem \320\1\x87\110 8086,SM +XCHG reg16,reg16 \320\1\x87\110 8086 +XCHG reg32,mem \321\1\x87\110 386,SM +XCHG reg32,reg32 \321\1\x87\110 386 +XCHG reg64,mem \324\1\x87\110 X64,SM +XCHG reg64,reg64 \324\1\x87\110 X64 +XCHG mem,reg8 \1\x86\101 8086,SM +XCHG reg8,reg8 \1\x86\101 8086 +XCHG mem,reg16 \320\1\x87\101 8086,SM +XCHG reg16,reg16 \320\1\x87\101 8086 +XCHG mem,reg32 \321\1\x87\101 386,SM +XCHG reg32,reg32 \321\1\x87\101 386 +XCHG mem,reg64 \324\1\x87\101 X64,SM +XCHG reg64,reg64 \324\1\x87\101 X64 +XLATB void \1\xD7 8086 +XLAT void \1\xD7 8086 +XOR mem,reg8 \1\x30\101 8086,SM +XOR reg8,reg8 \1\x30\101 8086 +XOR mem,reg16 \320\1\x31\101 8086,SM +XOR reg16,reg16 \320\1\x31\101 8086 +XOR mem,reg32 \321\1\x31\101 386,SM +XOR reg32,reg32 \321\1\x31\101 386 +XOR mem,reg64 \324\1\x31\101 X64,SM +XOR reg64,reg64 \324\1\x31\101 X64 +XOR reg8,mem \1\x32\110 8086,SM +XOR reg8,reg8 \1\x32\110 8086 +XOR reg16,mem \320\1\x33\110 8086,SM +XOR reg16,reg16 \320\1\x33\110 8086 +XOR reg32,mem \321\1\x33\110 386,SM +XOR reg32,reg32 \321\1\x33\110 386 +XOR reg64,mem \324\1\x33\110 X64,SM +XOR reg64,reg64 \324\1\x33\110 X64 +XOR rm16,imm8 \320\1\x83\206\275 8086 +XOR rm32,imm8 \321\1\x83\206\275 386 +XOR rm64,imm8 \324\1\x83\206\275 X64 +XOR reg_al,imm \1\x34\21 8086,SM +XOR reg_ax,sbyte16 \320\1\x83\206\275 8086,SM +XOR reg_ax,imm \320\1\x35\31 8086,SM +XOR reg_eax,sbyte32 \321\1\x83\206\275 386,SM +XOR reg_eax,imm \321\1\x35\41 386,SM +XOR reg_rax,sbyte64 \324\1\x83\206\275 X64,SM +XOR reg_rax,imm \324\1\x35\255 X64,SM +XOR rm8,imm \1\x80\206\21 8086,SM +XOR rm16,imm \320\145\x81\206\141 8086,SM +XOR rm32,imm \321\155\x81\206\151 386,SM +XOR rm64,imm \324\155\x81\206\251 X64,SM +XOR mem,imm8 \1\x80\206\21 8086,SM +XOR mem,imm16 \320\145\x81\206\141 8086,SM +XOR mem,imm32 \321\155\x81\206\151 386,SM +CMOVcc reg16,mem \320\1\x0F\330\x40\110 P6,SM +CMOVcc reg16,reg16 \320\1\x0F\330\x40\110 P6 +CMOVcc reg32,mem \321\1\x0F\330\x40\110 P6,SM +CMOVcc reg32,reg32 \321\1\x0F\330\x40\110 P6 +CMOVcc reg64,mem \324\1\x0F\330\x40\110 X64,SM +CMOVcc reg64,reg64 \324\1\x0F\330\x40\110 X64 +Jcc imm|near \322\1\x0F\330\x80\64 386 +Jcc imm16|near \320\1\x0F\330\x80\64 386 +Jcc imm32|near \321\1\x0F\330\x80\64 386 +Jcc imm|short \330\x70\50 8086,ND +Jcc imm \370\330\x70\50 8086,ND +Jcc imm \1\x0F\330\x80\64 386,ND +Jcc imm \330\x71\373\1\xE9\64 8086,ND +Jcc imm \330\x70\50 8086 +SETcc mem \1\x0F\330\x90\200 386,SB +SETcc reg8 \1\x0F\330\x90\200 386 + +;# Katmai Streaming SIMD instructions (SSE -- a.k.a. KNI, XMM, MMX2) +ADDPS xmmreg,xmmrm \360\2\x0F\x58\110 KATMAI,SSE +ADDSS xmmreg,xmmrm \363\2\x0F\x58\110 KATMAI,SSE,SD +ANDNPS xmmreg,xmmrm \360\2\x0F\x55\110 KATMAI,SSE +ANDPS xmmreg,xmmrm \360\2\x0F\x54\110 KATMAI,SSE +CMPEQPS xmmreg,xmmrm \360\2\x0F\xC2\110\1\x00 KATMAI,SSE +CMPEQSS xmmreg,xmmrm \363\2\x0F\xC2\110\1\x00 KATMAI,SSE +CMPLEPS xmmreg,xmmrm \360\2\x0F\xC2\110\1\x02 KATMAI,SSE +CMPLESS xmmreg,xmmrm \363\2\x0F\xC2\110\1\x02 KATMAI,SSE +CMPLTPS xmmreg,xmmrm \360\2\x0F\xC2\110\1\x01 KATMAI,SSE +CMPLTSS xmmreg,xmmrm \363\2\x0F\xC2\110\1\x01 KATMAI,SSE +CMPNEQPS xmmreg,xmmrm \360\2\x0F\xC2\110\1\x04 KATMAI,SSE +CMPNEQSS xmmreg,xmmrm \363\2\x0F\xC2\110\1\x04 KATMAI,SSE +CMPNLEPS xmmreg,xmmrm \360\2\x0F\xC2\110\1\x06 KATMAI,SSE +CMPNLESS xmmreg,xmmrm \363\2\x0F\xC2\110\1\x06 KATMAI,SSE +CMPNLTPS xmmreg,xmmrm \360\2\x0F\xC2\110\1\x05 KATMAI,SSE +CMPNLTSS xmmreg,xmmrm \363\2\x0F\xC2\110\1\x05 KATMAI,SSE +CMPORDPS xmmreg,xmmrm \360\2\x0F\xC2\110\1\x07 KATMAI,SSE +CMPORDSS xmmreg,xmmrm \363\2\x0F\xC2\110\1\x07 KATMAI,SSE +CMPUNORDPS xmmreg,xmmrm \360\2\x0F\xC2\110\1\x03 KATMAI,SSE +CMPUNORDSS xmmreg,xmmrm \363\2\x0F\xC2\110\1\x03 KATMAI,SSE +; CMPPS/CMPSS must come after the specific ops; that way the disassembler will find the +; specific ops first and only disassemble illegal ones as cmpps/cmpss. +CMPPS xmmreg,mem,imm \360\2\x0F\xC2\110\26 KATMAI,SSE,SB,AR2 +CMPPS xmmreg,xmmreg,imm \360\2\x0F\xC2\110\26 KATMAI,SSE,SB,AR2 +CMPSS xmmreg,mem,imm \363\2\x0F\xC2\110\26 KATMAI,SSE,SB,AR2 +CMPSS xmmreg,xmmreg,imm \363\2\x0F\xC2\110\26 KATMAI,SSE,SB,AR2 +COMISS xmmreg,xmmrm \360\2\x0F\x2F\110 KATMAI,SSE +CVTPI2PS xmmreg,mmxrm \360\2\x0F\x2A\110 KATMAI,SSE,MMX,SQ +CVTPS2PI mmxreg,xmmrm \360\2\x0F\x2D\110 KATMAI,SSE,MMX,SQ +CVTSI2SS xmmreg,mem \363\2\x0F\x2A\110 KATMAI,SSE,SD,AR1,ND +CVTSI2SS xmmreg,rm32 \363\2\x0F\x2A\110 KATMAI,SSE,SD,AR1 +CVTSI2SS xmmreg,rm64 \324\363\2\x0F\x2A\110 X64,SSE,SQ,AR1 +CVTSS2SI reg32,xmmreg \363\2\x0F\x2D\110 KATMAI,SSE,SD,AR1 +CVTSS2SI reg32,mem \363\2\x0F\x2D\110 KATMAI,SSE,SD,AR1 +CVTSS2SI reg64,xmmreg \324\363\2\x0F\x2D\110 X64,SSE,SD,AR1 +CVTSS2SI reg64,mem \324\363\2\x0F\x2D\110 X64,SSE,SD,AR1 +CVTTPS2PI mmxreg,xmmrm \360\2\x0F\x2C\110 KATMAI,SSE,MMX,SQ +CVTTSS2SI reg32,xmmrm \363\2\x0F\x2C\110 KATMAI,SSE,SD,AR1 +CVTTSS2SI reg64,xmmrm \324\363\2\x0F\x2C\110 X64,SSE,SD,AR1 +DIVPS xmmreg,xmmrm \360\2\x0F\x5E\110 KATMAI,SSE +DIVSS xmmreg,xmmrm \363\2\x0F\x5E\110 KATMAI,SSE +LDMXCSR mem \2\x0F\xAE\202 KATMAI,SSE,SD +MAXPS xmmreg,xmmrm \360\2\x0F\x5F\110 KATMAI,SSE +MAXSS xmmreg,xmmrm \363\2\x0F\x5F\110 KATMAI,SSE +MINPS xmmreg,xmmrm \360\2\x0F\x5D\110 KATMAI,SSE +MINSS xmmreg,xmmrm \363\2\x0F\x5D\110 KATMAI,SSE +MOVAPS xmmreg,mem \360\2\x0F\x28\110 KATMAI,SSE +MOVAPS mem,xmmreg \360\2\x0F\x29\101 KATMAI,SSE +MOVAPS xmmreg,xmmreg \360\2\x0F\x28\110 KATMAI,SSE +MOVAPS xmmreg,xmmreg \360\2\x0F\x29\101 KATMAI,SSE +MOVHPS xmmreg,mem \360\2\x0F\x16\110 KATMAI,SSE +MOVHPS mem,xmmreg \360\2\x0F\x17\101 KATMAI,SSE +MOVLHPS xmmreg,xmmreg \360\2\x0F\x16\110 KATMAI,SSE +MOVLPS xmmreg,mem \360\2\x0F\x12\110 KATMAI,SSE +MOVLPS mem,xmmreg \360\2\x0F\x13\101 KATMAI,SSE +MOVHLPS xmmreg,xmmreg \360\2\x0F\x12\110 KATMAI,SSE +MOVMSKPS reg32,xmmreg \360\2\x0F\x50\110 KATMAI,SSE +MOVMSKPS reg64,xmmreg \360\324\2\x0F\x50\110 X64,SSE +MOVNTPS mem,xmmreg \360\2\x0F\x2B\101 KATMAI,SSE +MOVSS xmmreg,mem \363\2\x0F\x10\110 KATMAI,SSE +MOVSS mem,xmmreg \363\2\x0F\x11\101 KATMAI,SSE +MOVSS xmmreg,xmmreg \363\2\x0F\x10\110 KATMAI,SSE +MOVSS xmmreg,xmmreg \363\2\x0F\x11\101 KATMAI,SSE +MOVUPS xmmreg,mem \360\2\x0F\x10\110 KATMAI,SSE +MOVUPS mem,xmmreg \360\2\x0F\x11\101 KATMAI,SSE +MOVUPS xmmreg,xmmreg \360\2\x0F\x10\110 KATMAI,SSE +MOVUPS xmmreg,xmmreg \360\2\x0F\x11\101 KATMAI,SSE +MULPS xmmreg,xmmrm \360\2\x0F\x59\110 KATMAI,SSE +MULSS xmmreg,xmmrm \363\2\x0F\x59\110 KATMAI,SSE +ORPS xmmreg,xmmrm \360\2\x0F\x56\110 KATMAI,SSE +RCPPS xmmreg,xmmrm \360\2\x0F\x53\110 KATMAI,SSE +RCPSS xmmreg,xmmrm \363\2\x0F\x53\110 KATMAI,SSE +RSQRTPS xmmreg,xmmrm \360\2\x0F\x52\110 KATMAI,SSE +RSQRTSS xmmreg,xmmrm \363\2\x0F\x52\110 KATMAI,SSE +SHUFPS xmmreg,mem,imm \360\2\x0F\xC6\110\26 KATMAI,SSE,SB,AR2 +SHUFPS xmmreg,xmmreg,imm \360\2\x0F\xC6\110\26 KATMAI,SSE,SB,AR2 +SQRTPS xmmreg,xmmrm \360\2\x0F\x51\110 KATMAI,SSE +SQRTSS xmmreg,xmmrm \363\2\x0F\x51\110 KATMAI,SSE +STMXCSR mem \2\x0F\xAE\203 KATMAI,SSE,SD +SUBPS xmmreg,xmmrm \360\2\x0F\x5C\110 KATMAI,SSE +SUBSS xmmreg,xmmrm \363\2\x0F\x5C\110 KATMAI,SSE +UCOMISS xmmreg,xmmrm \360\2\x0F\x2E\110 KATMAI,SSE +UNPCKHPS xmmreg,xmmrm \360\2\x0F\x15\110 KATMAI,SSE +UNPCKLPS xmmreg,xmmrm \360\2\x0F\x14\110 KATMAI,SSE +XORPS xmmreg,xmmrm \360\2\x0F\x57\110 KATMAI,SSE + +;# Introduced in Deschutes but necessary for SSE support +FXRSTOR mem \2\x0F\xAE\201 P6,SSE,FPU +FXSAVE mem \2\x0F\xAE\200 P6,SSE,FPU + +;# XSAVE group (AVX and extended state) +; Introduced in late Penryn ... we really need to clean up the handling +; of CPU feature bits. +XGETBV void \360\3\x0F\x01\xD0 NEHALEM +XSETBV void \360\3\x0F\x01\xD1 NEHALEM,PRIV +XSAVE mem \360\2\x0F\xAE\204 NEHALEM +XRSTOR mem \360\2\x0F\xAE\205 NEHALEM + +; These instructions are not SSE-specific; they are +;# Generic memory operations +; and work even if CR4.OSFXFR == 0 +PREFETCHNTA mem \2\x0F\x18\200 KATMAI +PREFETCHT0 mem \2\x0F\x18\201 KATMAI +PREFETCHT1 mem \2\x0F\x18\202 KATMAI +PREFETCHT2 mem \2\x0F\x18\203 KATMAI +SFENCE void \3\x0F\xAE\xF8 KATMAI + +;# New MMX instructions introduced in Katmai +MASKMOVQ mmxreg,mmxreg \360\2\x0F\xF7\110 KATMAI,MMX +MOVNTQ mem,mmxreg \360\2\x0F\xE7\101 KATMAI,MMX,SQ +PAVGB mmxreg,mmxrm \360\323\2\x0F\xE0\110 KATMAI,MMX,SQ +PAVGW mmxreg,mmxrm \360\323\2\x0F\xE3\110 KATMAI,MMX,SQ +PEXTRW reg32,mmxreg,imm \360\2\x0F\xC5\110\26 KATMAI,MMX,SB,AR2 +; PINSRW is documented as using a reg32, but it's really using only 16 bit +; -- accept either, but be truthful in disassembly +PINSRW mmxreg,reg16,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2 +PINSRW mmxreg,reg32,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2,ND +PINSRW mmxreg,mem,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2 +PINSRW mmxreg,mem16,imm \360\2\x0F\xC4\110\26 KATMAI,MMX,SB,AR2,ND +PMAXSW mmxreg,mmxrm \360\323\2\x0F\xEE\110 KATMAI,MMX,SQ +PMAXUB mmxreg,mmxrm \360\323\2\x0F\xDE\110 KATMAI,MMX,SQ +PMINSW mmxreg,mmxrm \360\323\2\x0F\xEA\110 KATMAI,MMX,SQ +PMINUB mmxreg,mmxrm \360\323\2\x0F\xDA\110 KATMAI,MMX,SQ +PMOVMSKB reg32,mmxreg \360\2\x0F\xD7\110 KATMAI,MMX +PMULHUW mmxreg,mmxrm \360\323\2\x0F\xE4\110 KATMAI,MMX,SQ +PSADBW mmxreg,mmxrm \360\323\2\x0F\xF6\110 KATMAI,MMX,SQ +PSHUFW mmxreg,mmxrm,imm \360\323\2\x0F\x70\110\22 KATMAI,MMX,SM2,SB,AR2 + +;# AMD Enhanced 3DNow! (Athlon) instructions +PF2IW mmxreg,mmxrm \323\2\x0F\x0F\110\01\x1C PENT,3DNOW,SQ +PFNACC mmxreg,mmxrm \323\2\x0F\x0F\110\01\x8A PENT,3DNOW,SQ +PFPNACC mmxreg,mmxrm \323\2\x0F\x0F\110\01\x8E PENT,3DNOW,SQ +PI2FW mmxreg,mmxrm \323\2\x0F\x0F\110\01\x0C PENT,3DNOW,SQ +PSWAPD mmxreg,mmxrm \323\2\x0F\x0F\110\01\xBB PENT,3DNOW,SQ + +;# Willamette SSE2 Cacheability Instructions +MASKMOVDQU xmmreg,xmmreg \361\2\x0F\xF7\110 WILLAMETTE,SSE2 +; CLFLUSH needs its own feature flag implemented one day +CLFLUSH mem \2\x0F\xAE\207 WILLAMETTE,SSE2 +MOVNTDQ mem,xmmreg \361\2\x0F\xE7\101 WILLAMETTE,SSE2,SO +MOVNTI mem,reg32 \360\2\x0F\xC3\101 WILLAMETTE,SD +MOVNTI mem,reg64 \324\360\2\x0F\xC3\101 X64,SQ +MOVNTPD mem,xmmreg \361\2\x0F\x2B\101 WILLAMETTE,SSE2,SO +LFENCE void \3\x0F\xAE\xE8 WILLAMETTE,SSE2 +MFENCE void \3\x0F\xAE\xF0 WILLAMETTE,SSE2 + +;# Willamette MMX instructions (SSE2 SIMD Integer Instructions) +MOVD xmmreg,reg32 \361\2\x0F\x6E\110 WILLAMETTE,SSE2 +MOVD reg32,xmmreg \361\2\x0F\x7E\101 WILLAMETTE,SSE2 +MOVD mem,xmmreg \361\2\x0F\x7E\101 WILLAMETTE,SSE2,SD +MOVD xmmreg,mem \361\2\x0F\x6E\110 WILLAMETTE,SSE2,SD +MOVDQA xmmreg,xmmreg \361\2\x0F\x6F\110 WILLAMETTE,SSE2 +MOVDQA mem,xmmreg \361\2\x0F\x7F\101 WILLAMETTE,SSE2,SO +MOVDQA xmmreg,mem \361\2\x0F\x6F\110 WILLAMETTE,SSE2,SO +MOVDQA xmmreg,xmmreg \361\2\x0F\x7F\101 WILLAMETTE,SSE2 +MOVDQU xmmreg,xmmreg \363\2\x0F\x6F\110 WILLAMETTE,SSE2 +MOVDQU mem,xmmreg \363\2\x0F\x7F\101 WILLAMETTE,SSE2,SO +MOVDQU xmmreg,mem \363\2\x0F\x6F\110 WILLAMETTE,SSE2,SO +MOVDQU xmmreg,xmmreg \363\2\x0F\x7F\101 WILLAMETTE,SSE2 +MOVDQ2Q mmxreg,xmmreg \362\2\x0F\xD6\110 WILLAMETTE,SSE2 +MOVQ xmmreg,xmmreg \363\2\x0F\x7E\110 WILLAMETTE,SSE2 +MOVQ xmmreg,xmmreg \361\2\x0F\xD6\101 WILLAMETTE,SSE2 +MOVQ mem,xmmreg \361\2\x0F\xD6\101 WILLAMETTE,SSE2,SQ +MOVQ xmmreg,mem \363\2\x0F\x7E\110 WILLAMETTE,SSE2,SQ +MOVQ xmmreg,rm64 \361\324\2\x0F\x6E\110 X64,SSE2 +MOVQ rm64,xmmreg \361\324\2\x0F\x7E\101 X64,SSE2 +MOVQ2DQ xmmreg,mmxreg \363\2\x0F\xD6\110 WILLAMETTE,SSE2 +PACKSSWB xmmreg,xmmrm \361\2\x0F\x63\110 WILLAMETTE,SSE2,SO +PACKSSDW xmmreg,xmmrm \361\2\x0F\x6B\110 WILLAMETTE,SSE2,SO +PACKUSWB xmmreg,xmmrm \361\2\x0F\x67\110 WILLAMETTE,SSE2,SO +PADDB xmmreg,xmmrm \361\2\x0F\xFC\110 WILLAMETTE,SSE2,SO +PADDW xmmreg,xmmrm \361\2\x0F\xFD\110 WILLAMETTE,SSE2,SO +PADDD xmmreg,xmmrm \361\2\x0F\xFE\110 WILLAMETTE,SSE2,SO +PADDQ mmxreg,mmxrm \360\2\x0F\xD4\110 WILLAMETTE,MMX,SQ +PADDQ xmmreg,xmmrm \361\2\x0F\xD4\110 WILLAMETTE,SSE2,SO +PADDSB xmmreg,xmmrm \361\2\x0F\xEC\110 WILLAMETTE,SSE2,SO +PADDSW xmmreg,xmmrm \361\2\x0F\xED\110 WILLAMETTE,SSE2,SO +PADDUSB xmmreg,xmmrm \361\2\x0F\xDC\110 WILLAMETTE,SSE2,SO +PADDUSW xmmreg,xmmrm \361\2\x0F\xDD\110 WILLAMETTE,SSE2,SO +PAND xmmreg,xmmrm \361\2\x0F\xDB\110 WILLAMETTE,SSE2,SO +PANDN xmmreg,xmmrm \361\2\x0F\xDF\110 WILLAMETTE,SSE2,SO +PAVGB xmmreg,xmmrm \361\2\x0F\xE0\110 WILLAMETTE,SSE2,SO +PAVGW xmmreg,xmmrm \361\2\x0F\xE3\110 WILLAMETTE,SSE2,SO +PCMPEQB xmmreg,xmmrm \361\2\x0F\x74\110 WILLAMETTE,SSE2,SO +PCMPEQW xmmreg,xmmrm \361\2\x0F\x75\110 WILLAMETTE,SSE2,SO +PCMPEQD xmmreg,xmmrm \361\2\x0F\x76\110 WILLAMETTE,SSE2,SO +PCMPGTB xmmreg,xmmrm \361\2\x0F\x64\110 WILLAMETTE,SSE2,SO +PCMPGTW xmmreg,xmmrm \361\2\x0F\x65\110 WILLAMETTE,SSE2,SO +PCMPGTD xmmreg,xmmrm \361\2\x0F\x66\110 WILLAMETTE,SSE2,SO +PEXTRW reg32,xmmreg,imm \361\2\x0F\xC5\110\26 WILLAMETTE,SSE2,SB,AR2 +PINSRW xmmreg,reg16,imm \361\2\x0F\xC4\110\26 WILLAMETTE,SSE2,SB,AR2 +PINSRW xmmreg,reg32,imm \361\2\x0F\xC4\110\26 WILLAMETTE,SSE2,SB,AR2,ND +PINSRW xmmreg,mem,imm \361\2\x0F\xC4\110\26 WILLAMETTE,SSE2,SB,AR2 +PINSRW xmmreg,mem16,imm \361\2\x0F\xC4\110\26 WILLAMETTE,SSE2,SB,AR2,ND +PMADDWD xmmreg,xmmrm \361\2\x0F\xF5\110 WILLAMETTE,SSE2,SO +PMAXSW xmmreg,xmmrm \361\2\x0F\xEE\110 WILLAMETTE,SSE2,SO +PMAXUB xmmreg,xmmrm \361\2\x0F\xDE\110 WILLAMETTE,SSE2,SO +PMINSW xmmreg,xmmrm \361\2\x0F\xEA\110 WILLAMETTE,SSE2,SO +PMINUB xmmreg,xmmrm \361\2\x0F\xDA\110 WILLAMETTE,SSE2,SO +PMOVMSKB reg32,xmmreg \361\2\x0F\xD7\110 WILLAMETTE,SSE2 +PMULHUW xmmreg,xmmrm \361\2\x0F\xE4\110 WILLAMETTE,SSE2,SO +PMULHW xmmreg,xmmrm \361\2\x0F\xE5\110 WILLAMETTE,SSE2,SO +PMULLW xmmreg,xmmrm \361\2\x0F\xD5\110 WILLAMETTE,SSE2,SO +PMULUDQ mmxreg,mmxrm \360\323\2\x0F\xF4\110 WILLAMETTE,SSE2,SO +PMULUDQ xmmreg,xmmrm \361\2\x0F\xF4\110 WILLAMETTE,SSE2,SO +POR xmmreg,xmmrm \361\2\x0F\xEB\110 WILLAMETTE,SSE2,SO +PSADBW xmmreg,xmmrm \361\2\x0F\xF6\110 WILLAMETTE,SSE2,SO +PSHUFD xmmreg,xmmreg,imm \361\2\x0F\x70\110\22 WILLAMETTE,SSE2,SB,AR2 +PSHUFD xmmreg,mem,imm \361\2\x0F\x70\110\22 WILLAMETTE,SSE2,SM2,SB,AR2 +PSHUFHW xmmreg,xmmreg,imm \363\2\x0F\x70\110\22 WILLAMETTE,SSE2,SB,AR2 +PSHUFHW xmmreg,mem,imm \363\2\x0F\x70\110\22 WILLAMETTE,SSE2,SM2,SB,AR2 +PSHUFLW xmmreg,xmmreg,imm \362\2\x0F\x70\110\22 WILLAMETTE,SSE2,SB,AR2 +PSHUFLW xmmreg,mem,imm \362\2\x0F\x70\110\22 WILLAMETTE,SSE2,SM2,SB,AR2 +PSLLDQ xmmreg,imm \361\2\x0F\x73\207\25 WILLAMETTE,SSE2,SB,AR1 +PSLLW xmmreg,xmmrm \361\2\x0F\xF1\110 WILLAMETTE,SSE2,SO +PSLLW xmmreg,imm \361\2\x0F\x71\206\25 WILLAMETTE,SSE2,SB,AR1 +PSLLD xmmreg,xmmrm \361\2\x0F\xF2\110 WILLAMETTE,SSE2,SO +PSLLD xmmreg,imm \361\2\x0F\x72\206\25 WILLAMETTE,SSE2,SB,AR1 +PSLLQ xmmreg,xmmrm \361\2\x0F\xF3\110 WILLAMETTE,SSE2,SO +PSLLQ xmmreg,imm \361\2\x0F\x73\206\25 WILLAMETTE,SSE2,SB,AR1 +PSRAW xmmreg,xmmrm \361\2\x0F\xE1\110 WILLAMETTE,SSE2,SO +PSRAW xmmreg,imm \361\2\x0F\x71\204\25 WILLAMETTE,SSE2,SB,AR1 +PSRAD xmmreg,xmmrm \361\2\x0F\xE2\110 WILLAMETTE,SSE2,SO +PSRAD xmmreg,imm \361\2\x0F\x72\204\25 WILLAMETTE,SSE2,SB,AR1 +PSRLDQ xmmreg,imm \361\2\x0F\x73\203\25 WILLAMETTE,SSE2,SB,AR1 +PSRLW xmmreg,xmmrm \361\2\x0F\xD1\110 WILLAMETTE,SSE2,SO +PSRLW xmmreg,imm \361\2\x0F\x71\202\25 WILLAMETTE,SSE2,SB,AR1 +PSRLD xmmreg,xmmrm \361\2\x0F\xD2\110 WILLAMETTE,SSE2,SO +PSRLD xmmreg,imm \361\2\x0F\x72\202\25 WILLAMETTE,SSE2,SB,AR1 +PSRLQ xmmreg,xmmrm \361\2\x0F\xD3\110 WILLAMETTE,SSE2,SO +PSRLQ xmmreg,imm \361\2\x0F\x73\202\25 WILLAMETTE,SSE2,SB,AR1 +PSUBB xmmreg,xmmrm \361\2\x0F\xF8\110 WILLAMETTE,SSE2,SO +PSUBW xmmreg,xmmrm \361\2\x0F\xF9\110 WILLAMETTE,SSE2,SO +PSUBD xmmreg,xmmrm \361\2\x0F\xFA\110 WILLAMETTE,SSE2,SO +PSUBQ mmxreg,mmxrm \360\323\2\x0F\xFB\110 WILLAMETTE,SSE2,SO +PSUBQ xmmreg,xmmrm \361\2\x0F\xFB\110 WILLAMETTE,SSE2,SO +PSUBSB xmmreg,xmmrm \361\2\x0F\xE8\110 WILLAMETTE,SSE2,SO +PSUBSW xmmreg,xmmrm \361\2\x0F\xE9\110 WILLAMETTE,SSE2,SO +PSUBUSB xmmreg,xmmrm \361\2\x0F\xD8\110 WILLAMETTE,SSE2,SO +PSUBUSW xmmreg,xmmrm \361\2\x0F\xD9\110 WILLAMETTE,SSE2,SO +PUNPCKHBW xmmreg,xmmrm \361\2\x0F\x68\110 WILLAMETTE,SSE2,SO +PUNPCKHWD xmmreg,xmmrm \361\2\x0F\x69\110 WILLAMETTE,SSE2,SO +PUNPCKHDQ xmmreg,xmmrm \361\2\x0F\x6A\110 WILLAMETTE,SSE2,SO +PUNPCKHQDQ xmmreg,xmmrm \361\2\x0F\x6D\110 WILLAMETTE,SSE2,SO +PUNPCKLBW xmmreg,xmmrm \361\2\x0F\x60\110 WILLAMETTE,SSE2,SO +PUNPCKLWD xmmreg,xmmrm \361\2\x0F\x61\110 WILLAMETTE,SSE2,SO +PUNPCKLDQ xmmreg,xmmrm \361\2\x0F\x62\110 WILLAMETTE,SSE2,SO +PUNPCKLQDQ xmmreg,xmmrm \361\2\x0F\x6C\110 WILLAMETTE,SSE2,SO +PXOR xmmreg,xmmrm \361\2\x0F\xEF\110 WILLAMETTE,SSE2,SO + +;# Willamette Streaming SIMD instructions (SSE2) +ADDPD xmmreg,xmmrm \361\2\x0F\x58\110 WILLAMETTE,SSE2,SO +ADDSD xmmreg,xmmrm \362\2\x0F\x58\110 WILLAMETTE,SSE2,SQ +ANDNPD xmmreg,xmmrm \361\2\x0F\x55\110 WILLAMETTE,SSE2,SO +ANDPD xmmreg,xmmrm \361\2\x0F\x54\110 WILLAMETTE,SSE2,SO +CMPEQPD xmmreg,xmmrm \361\2\x0F\xC2\110\1\x00 WILLAMETTE,SSE2,SO +CMPEQSD xmmreg,xmmrm \362\2\x0F\xC2\110\1\x00 WILLAMETTE,SSE2 +CMPLEPD xmmreg,xmmrm \361\2\x0F\xC2\110\1\x02 WILLAMETTE,SSE2,SO +CMPLESD xmmreg,xmmrm \362\2\x0F\xC2\110\1\x02 WILLAMETTE,SSE2 +CMPLTPD xmmreg,xmmrm \361\2\x0F\xC2\110\1\x01 WILLAMETTE,SSE2,SO +CMPLTSD xmmreg,xmmrm \362\2\x0F\xC2\110\1\x01 WILLAMETTE,SSE2 +CMPNEQPD xmmreg,xmmrm \361\2\x0F\xC2\110\1\x04 WILLAMETTE,SSE2,SO +CMPNEQSD xmmreg,xmmrm \362\2\x0F\xC2\110\1\x04 WILLAMETTE,SSE2 +CMPNLEPD xmmreg,xmmrm \361\2\x0F\xC2\110\1\x06 WILLAMETTE,SSE2,SO +CMPNLESD xmmreg,xmmrm \362\2\x0F\xC2\110\1\x06 WILLAMETTE,SSE2 +CMPNLTPD xmmreg,xmmrm \361\2\x0F\xC2\110\1\x05 WILLAMETTE,SSE2,SO +CMPNLTSD xmmreg,xmmrm \362\2\x0F\xC2\110\1\x05 WILLAMETTE,SSE2 +CMPORDPD xmmreg,xmmrm \361\2\x0F\xC2\110\1\x07 WILLAMETTE,SSE2,SO +CMPORDSD xmmreg,xmmrm \362\2\x0F\xC2\110\1\x07 WILLAMETTE,SSE2 +CMPUNORDPD xmmreg,xmmrm \361\2\x0F\xC2\110\1\x03 WILLAMETTE,SSE2,SO +CMPUNORDSD xmmreg,xmmrm \362\2\x0F\xC2\110\1\x03 WILLAMETTE,SSE2 +; CMPPD/CMPSD must come after the specific ops; that way the disassembler will find the +; specific ops first and only disassemble illegal ones as cmppd/cmpsd. +CMPPD xmmreg,xmmrm,imm \361\2\x0F\xC2\110\26 WILLAMETTE,SSE2,SM2,SB,AR2 +CMPSD xmmreg,xmmrm,imm \362\2\x0F\xC2\110\26 WILLAMETTE,SSE2,SB,AR2 +COMISD xmmreg,xmmrm \361\2\x0F\x2F\110 WILLAMETTE,SSE2 +CVTDQ2PD xmmreg,xmmrm \363\2\x0F\xE6\110 WILLAMETTE,SSE2,SQ +CVTDQ2PS xmmreg,xmmrm \360\2\x0F\x5B\110 WILLAMETTE,SSE2,SO +CVTPD2DQ xmmreg,xmmrm \362\2\x0F\xE6\110 WILLAMETTE,SSE2,SO +CVTPD2PI mmxreg,xmmrm \361\2\x0F\x2D\110 WILLAMETTE,SSE2,SO +CVTPD2PS xmmreg,xmmrm \361\2\x0F\x5A\110 WILLAMETTE,SSE2,SO +CVTPI2PD xmmreg,mmxrm \361\2\x0F\x2A\110 WILLAMETTE,SSE2,SQ +CVTPS2DQ xmmreg,xmmrm \361\2\x0F\x5B\110 WILLAMETTE,SSE2,SO +CVTPS2PD xmmreg,xmmrm \360\2\x0F\x5A\110 WILLAMETTE,SSE2,SQ +CVTSD2SI reg32,xmmreg \362\2\x0F\x2D\110 WILLAMETTE,SSE2,SQ,AR1 +CVTSD2SI reg32,mem \362\2\x0F\x2D\110 WILLAMETTE,SSE2,SQ,AR1 +CVTSD2SI reg64,xmmreg \324\362\2\x0F\x2D\110 X64,SSE2,SQ,AR1 +CVTSD2SI reg64,mem \324\362\2\x0F\x2D\110 X64,SSE2,SQ,AR1 +CVTSD2SS xmmreg,xmmrm \362\2\x0F\x5A\110 WILLAMETTE,SSE2,SQ +CVTSI2SD xmmreg,mem \362\2\x0F\x2A\110 WILLAMETTE,SSE2,SD,AR1,ND +CVTSI2SD xmmreg,rm32 \362\2\x0F\x2A\110 WILLAMETTE,SSE2,SD,AR1 +CVTSI2SD xmmreg,rm64 \324\362\2\x0F\x2A\110 X64,SSE2,SQ,AR1 +CVTSS2SD xmmreg,xmmrm \363\2\x0F\x5A\110 WILLAMETTE,SSE2,SD +CVTTPD2PI mmxreg,xmmrm \361\2\x0F\x2C\110 WILLAMETTE,SSE2,SO +CVTTPD2DQ xmmreg,xmmrm \361\2\x0F\xE6\110 WILLAMETTE,SSE2,SO +CVTTPS2DQ xmmreg,xmmrm \363\2\x0F\x5B\110 WILLAMETTE,SSE2,SO +CVTTSD2SI reg32,xmmreg \362\2\x0F\x2C\110 WILLAMETTE,SSE2,SQ,AR1 +CVTTSD2SI reg32,mem \362\2\x0F\x2C\110 WILLAMETTE,SSE2,SQ,AR1 +CVTTSD2SI reg64,xmmreg \324\362\2\x0F\x2C\110 X64,SSE2,SQ,AR1 +CVTTSD2SI reg64,mem \324\362\2\x0F\x2C\110 X64,SSE2,SQ,AR1 +DIVPD xmmreg,xmmrm \361\2\x0F\x5E\110 WILLAMETTE,SSE2,SO +DIVSD xmmreg,xmmrm \362\2\x0F\x5E\110 WILLAMETTE,SSE2 +MAXPD xmmreg,xmmrm \361\2\x0F\x5F\110 WILLAMETTE,SSE2,SO +MAXSD xmmreg,xmmrm \362\2\x0F\x5F\110 WILLAMETTE,SSE2 +MINPD xmmreg,xmmrm \361\2\x0F\x5D\110 WILLAMETTE,SSE2,SO +MINSD xmmreg,xmmrm \362\2\x0F\x5D\110 WILLAMETTE,SSE2 +MOVAPD xmmreg,xmmreg \361\2\x0F\x28\110 WILLAMETTE,SSE2 +MOVAPD xmmreg,xmmreg \361\2\x0F\x29\101 WILLAMETTE,SSE2 +MOVAPD mem,xmmreg \361\2\x0F\x29\101 WILLAMETTE,SSE2,SO +MOVAPD xmmreg,mem \361\2\x0F\x28\110 WILLAMETTE,SSE2,SO +MOVHPD mem,xmmreg \361\2\x0F\x17\101 WILLAMETTE,SSE2 +MOVHPD xmmreg,mem \361\2\x0F\x16\110 WILLAMETTE,SSE2 +MOVLPD mem,xmmreg \361\2\x0F\x13\101 WILLAMETTE,SSE2 +MOVLPD xmmreg,mem \361\2\x0F\x12\110 WILLAMETTE,SSE2 +MOVMSKPD reg32,xmmreg \361\2\x0F\x50\110 WILLAMETTE,SSE2 +MOVMSKPD reg64,xmmreg \361\324\2\x0F\x50\110 X64,SSE2 +MOVSD xmmreg,xmmreg \362\2\x0F\x10\110 WILLAMETTE,SSE2 +MOVSD xmmreg,xmmreg \362\2\x0F\x11\101 WILLAMETTE,SSE2 +MOVSD mem,xmmreg \362\2\x0F\x11\101 WILLAMETTE,SSE2 +MOVSD xmmreg,mem \362\2\x0F\x10\110 WILLAMETTE,SSE2 +MOVUPD xmmreg,xmmreg \361\2\x0F\x10\110 WILLAMETTE,SSE2 +MOVUPD xmmreg,xmmreg \361\2\x0F\x11\101 WILLAMETTE,SSE2 +MOVUPD mem,xmmreg \361\2\x0F\x11\101 WILLAMETTE,SSE2,SO +MOVUPD xmmreg,mem \361\2\x0F\x10\110 WILLAMETTE,SSE2,SO +MULPD xmmreg,xmmrm \361\2\x0F\x59\110 WILLAMETTE,SSE2,SO +MULSD xmmreg,xmmrm \362\2\x0F\x59\110 WILLAMETTE,SSE2 +ORPD xmmreg,xmmrm \361\2\x0F\x56\110 WILLAMETTE,SSE2,SO +SHUFPD xmmreg,xmmreg,imm \361\2\x0F\xC6\110\26 WILLAMETTE,SSE2,SB,AR2 +SHUFPD xmmreg,mem,imm \361\2\x0F\xC6\110\26 WILLAMETTE,SSE2,SM,SB,AR2 +SQRTPD xmmreg,xmmrm \361\2\x0F\x51\110 WILLAMETTE,SSE2,SO +SQRTSD xmmreg,xmmrm \362\2\x0F\x51\110 WILLAMETTE,SSE2 +SUBPD xmmreg,xmmrm \361\2\x0F\x5C\110 WILLAMETTE,SSE2,SO +SUBSD xmmreg,xmmrm \362\2\x0F\x5C\110 WILLAMETTE,SSE2 +UCOMISD xmmreg,xmmrm \361\2\x0F\x2E\110 WILLAMETTE,SSE2 +UNPCKHPD xmmreg,xmmrm \361\2\x0F\x15\110 WILLAMETTE,SSE2,SO +UNPCKLPD xmmreg,xmmrm \361\2\x0F\x14\110 WILLAMETTE,SSE2,SO +XORPD xmmreg,xmmrm \361\2\x0F\x57\110 WILLAMETTE,SSE2,SO + +;# Prescott New Instructions (SSE3) +ADDSUBPD xmmreg,xmmrm \361\2\x0F\xD0\110 PRESCOTT,SSE3,SO +ADDSUBPS xmmreg,xmmrm \362\2\x0F\xD0\110 PRESCOTT,SSE3,SO +HADDPD xmmreg,xmmrm \361\2\x0F\x7C\110 PRESCOTT,SSE3,SO +HADDPS xmmreg,xmmrm \362\2\x0F\x7C\110 PRESCOTT,SSE3,SO +HSUBPD xmmreg,xmmrm \361\2\x0F\x7D\110 PRESCOTT,SSE3,SO +HSUBPS xmmreg,xmmrm \362\2\x0F\x7D\110 PRESCOTT,SSE3,SO +LDDQU xmmreg,mem \362\2\x0F\xF0\110 PRESCOTT,SSE3,SO +MOVDDUP xmmreg,xmmrm \362\2\x0F\x12\110 PRESCOTT,SSE3 +MOVSHDUP xmmreg,xmmrm \363\2\x0F\x16\110 PRESCOTT,SSE3 +MOVSLDUP xmmreg,xmmrm \363\2\x0F\x12\110 PRESCOTT,SSE3 + +;# VMX Instructions +VMCALL void \3\x0F\x01\xC1 VMX +VMCLEAR mem \361\2\x0F\xC7\206 VMX +VMLAUNCH void \3\x0F\x01\xC2 VMX +VMLOAD void \3\x0F\x01\xDA X64,VMX +VMMCALL void \3\x0F\x01\xD9 X64,VMX +VMPTRLD mem \2\x0F\xC7\206 VMX +VMPTRST mem \2\x0F\xC7\207 VMX +VMREAD rm32,reg32 \360\2\x0F\x78\101 VMX,NOLONG,SD +VMREAD rm64,reg64 \323\360\2\x0F\x78\101 X64,VMX,SQ +VMRESUME void \3\x0F\x01\xC3 VMX +VMRUN void \3\x0F\x01\xD8 X64,VMX +VMSAVE void \3\x0F\x01\xDB X64,VMX +VMWRITE reg32,rm32 \360\2\x0F\x79\110 VMX,NOLONG,SD +VMWRITE reg64,rm64 \323\360\2\x0F\x79\110 X64,VMX,SQ +VMXOFF void \3\x0F\x01\xC4 VMX +VMXON mem \363\2\x0F\xC7\206 VMX +;# Extended Page Tables VMX instructions +INVEPT reg32,mem [rm: 66 0f 38 80 /r] VMX,SO,NOLONG +INVEPT reg64,mem [rm: o64nw 66 0f 38 80 /r] VMX,SO,LONG +INVVPID reg32,mem [rm: 66 0f 38 81 /r] VMX,SO,NOLONG +INVVPID reg64,mem [rm: o64nw 66 0f 38 81 /r] VMX,SO,LONG + +;# Tejas New Instructions (SSSE3) +PABSB mmxreg,mmxrm \360\3\x0F\x38\x1C\110 SSSE3,MMX,SQ +PABSB xmmreg,xmmrm \361\3\x0F\x38\x1C\110 SSSE3 +PABSW mmxreg,mmxrm \360\3\x0F\x38\x1D\110 SSSE3,MMX,SQ +PABSW xmmreg,xmmrm \361\3\x0F\x38\x1D\110 SSSE3 +PABSD mmxreg,mmxrm \360\3\x0F\x38\x1E\110 SSSE3,MMX,SQ +PABSD xmmreg,xmmrm \361\3\x0F\x38\x1E\110 SSSE3 +PALIGNR mmxreg,mmxrm,imm \360\3\x0F\x3A\x0F\110\26 SSSE3,MMX,SQ +PALIGNR xmmreg,xmmrm,imm \361\3\x0F\x3A\x0F\110\26 SSSE3 +PHADDW mmxreg,mmxrm \360\3\x0F\x38\x01\110 SSSE3,MMX,SQ +PHADDW xmmreg,xmmrm \361\3\x0F\x38\x01\110 SSSE3 +PHADDD mmxreg,mmxrm \360\3\x0F\x38\x02\110 SSSE3,MMX,SQ +PHADDD xmmreg,xmmrm \361\3\x0F\x38\x02\110 SSSE3 +PHADDSW mmxreg,mmxrm \360\3\x0F\x38\x03\110 SSSE3,MMX,SQ +PHADDSW xmmreg,xmmrm \361\3\x0F\x38\x03\110 SSSE3 +PHSUBW mmxreg,mmxrm \360\3\x0F\x38\x05\110 SSSE3,MMX,SQ +PHSUBW xmmreg,xmmrm \361\3\x0F\x38\x05\110 SSSE3 +PHSUBD mmxreg,mmxrm \360\3\x0F\x38\x06\110 SSSE3,MMX,SQ +PHSUBD xmmreg,xmmrm \361\3\x0F\x38\x06\110 SSSE3 +PHSUBSW mmxreg,mmxrm \360\3\x0F\x38\x07\110 SSSE3,MMX,SQ +PHSUBSW xmmreg,xmmrm \361\3\x0F\x38\x07\110 SSSE3 +PMADDUBSW mmxreg,mmxrm \360\3\x0F\x38\x04\110 SSSE3,MMX,SQ +PMADDUBSW xmmreg,xmmrm \361\3\x0F\x38\x04\110 SSSE3 +PMULHRSW mmxreg,mmxrm \360\3\x0F\x38\x0B\110 SSSE3,MMX,SQ +PMULHRSW xmmreg,xmmrm \361\3\x0F\x38\x0B\110 SSSE3 +PSHUFB mmxreg,mmxrm \360\3\x0F\x38\x00\110 SSSE3,MMX,SQ +PSHUFB xmmreg,xmmrm \361\3\x0F\x38\x00\110 SSSE3 +PSIGNB mmxreg,mmxrm \360\3\x0F\x38\x08\110 SSSE3,MMX,SQ +PSIGNB xmmreg,xmmrm \361\3\x0F\x38\x08\110 SSSE3 +PSIGNW mmxreg,mmxrm \360\3\x0F\x38\x09\110 SSSE3,MMX,SQ +PSIGNW xmmreg,xmmrm \361\3\x0F\x38\x09\110 SSSE3 +PSIGND mmxreg,mmxrm \360\3\x0F\x38\x0A\110 SSSE3,MMX,SQ +PSIGND xmmreg,xmmrm \361\3\x0F\x38\x0A\110 SSSE3 + +;# AMD SSE4A +EXTRQ xmmreg,imm,imm \361\2\x0F\x78\200\25\26 SSE4A,AMD +EXTRQ xmmreg,xmmreg \361\2\x0F\x79\110 SSE4A,AMD +INSERTQ xmmreg,xmmreg,imm,imm \362\2\x0F\x78\110\26\27 SSE4A,AMD +INSERTQ xmmreg,xmmreg \362\2\x0F\x79\110 SSE4A,AMD +MOVNTSD mem,xmmreg \362\2\x0F\x2B\101 SSE4A,AMD,SQ +MOVNTSS mem,xmmreg \363\2\x0F\x2B\101 SSE4A,AMD,SD + +;# New instructions in Barcelona +LZCNT reg16,rm16 \320\333\2\x0F\xBD\110 P6,AMD +LZCNT reg32,rm32 \321\333\2\x0F\xBD\110 P6,AMD +LZCNT reg64,rm64 \324\333\2\x0F\xBD\110 X64,AMD + +;# Penryn New Instructions (SSE4.1) +BLENDPD xmmreg,xmmrm,imm \361\3\x0F\x3A\x0D\110\26 SSE41 +BLENDPS xmmreg,xmmrm,imm \361\3\x0F\x3A\x0C\110\26 SSE41 +BLENDVPD xmmreg,xmmrm,xmm0 \361\3\x0F\x38\x15\110 SSE41 +BLENDVPS xmmreg,xmmrm,xmm0 \361\3\x0F\x38\x14\110 SSE41 +DPPD xmmreg,xmmrm,imm \361\3\x0F\x3A\x41\110\26 SSE41 +DPPS xmmreg,xmmrm,imm \361\3\x0F\x3A\x40\110\26 SSE41 +EXTRACTPS rm32,xmmreg,imm \361\3\x0F\x3A\x17\101\26 SSE41 +EXTRACTPS reg64,xmmreg,imm \324\361\3\x0F\x3A\x17\101\26 SSE41,X64 +INSERTPS xmmreg,xmmrm,imm \361\3\x0F\x3A\x21\110\26 SSE41,SD +MOVNTDQA xmmreg,mem \361\3\x0F\x38\x2A\110 SSE41 +MPSADBW xmmreg,xmmrm,imm \361\3\x0F\x3A\x42\110\26 SSE41 +PACKUSDW xmmreg,xmmrm \361\3\x0F\x38\x2B\110 SSE41 +PBLENDVB xmmreg,xmmrm,xmm0 \361\3\x0F\x38\x10\110 SSE41 +PBLENDW xmmreg,xmmrm,imm \361\3\x0F\x3A\x0E\110\26 SSE41 +PCMPEQQ xmmreg,xmmrm \361\3\x0F\x38\x29\110 SSE41 +PEXTRB reg32,xmmreg,imm \361\3\x0F\x3A\x14\101\26 SSE41 +PEXTRB mem8,xmmreg,imm \361\3\x0F\x3A\x14\101\26 SSE41 +PEXTRB reg64,xmmreg,imm \324\361\3\x0F\x3A\x14\101\26 SSE41,X64 +PEXTRD rm32,xmmreg,imm \361\3\x0F\x3A\x16\101\26 SSE41 +PEXTRQ rm64,xmmreg,imm \324\361\3\x0F\x3A\x16\101\26 SSE41,X64 +PEXTRW reg32,xmmreg,imm \361\3\x0F\x3A\x15\101\26 SSE41 +PEXTRW mem16,xmmreg,imm \361\3\x0F\x3A\x15\101\26 SSE41 +PEXTRW reg64,xmmreg,imm \324\361\3\x0F\x3A\x15\101\26 SSE41,X64 +PHMINPOSUW xmmreg,xmmrm \361\3\x0F\x38\x41\110 SSE41 +PINSRB xmmreg,reg32,imm \361\3\x0F\x3A\x20\110\26 SSE41 +PINSRB xmmreg,mem8,imm \361\3\x0F\x3A\x20\110\26 SSE41 +PINSRD xmmreg,rm32,imm \361\3\x0F\x3A\x22\110\26 SSE41 +PINSRQ xmmreg,rm64,imm \324\361\3\x0F\x3A\x22\110\26 SSE41,X64 +PMAXSB xmmreg,xmmrm \361\3\x0F\x38\x3C\110 SSE41 +PMAXSD xmmreg,xmmrm \361\3\x0F\x38\x3D\110 SSE41 +PMAXUD xmmreg,xmmrm \361\3\x0F\x38\x3F\110 SSE41 +PMAXUW xmmreg,xmmrm \361\3\x0F\x38\x3E\110 SSE41 +PMINSB xmmreg,xmmrm \361\3\x0F\x38\x38\110 SSE41 +PMINSD xmmreg,xmmrm \361\3\x0F\x38\x39\110 SSE41 +PMINUD xmmreg,xmmrm \361\3\x0F\x38\x3B\110 SSE41 +PMINUW xmmreg,xmmrm \361\3\x0F\x38\x3A\110 SSE41 +PMOVSXBW xmmreg,xmmrm \361\3\x0F\x38\x20\110 SSE41,SQ +PMOVSXBD xmmreg,xmmrm \361\3\x0F\x38\x21\110 SSE41,SD +PMOVSXBQ xmmreg,xmmrm \361\3\x0F\x38\x22\110 SSE41,SW +PMOVSXWD xmmreg,xmmrm \361\3\x0F\x38\x23\110 SSE41,SQ +PMOVSXWQ xmmreg,xmmrm \361\3\x0F\x38\x24\110 SSE41,SD +PMOVSXDQ xmmreg,xmmrm \361\3\x0F\x38\x25\110 SSE41,SQ +PMOVZXBW xmmreg,xmmrm \361\3\x0F\x38\x30\110 SSE41,SQ +PMOVZXBD xmmreg,xmmrm \361\3\x0F\x38\x31\110 SSE41,SD +PMOVZXBQ xmmreg,xmmrm \361\3\x0F\x38\x32\110 SSE41,SW +PMOVZXWD xmmreg,xmmrm \361\3\x0F\x38\x33\110 SSE41,SQ +PMOVZXWQ xmmreg,xmmrm \361\3\x0F\x38\x34\110 SSE41,SD +PMOVZXDQ xmmreg,xmmrm \361\3\x0F\x38\x35\110 SSE41,SQ +PMULDQ xmmreg,xmmrm \361\3\x0F\x38\x28\110 SSE41 +PMULLD xmmreg,xmmrm \361\3\x0F\x38\x40\110 SSE41 +PTEST xmmreg,xmmrm \361\3\x0F\x38\x17\110 SSE41 +ROUNDPD xmmreg,xmmrm,imm \361\3\x0F\x3A\x09\110\26 SSE41 +ROUNDPS xmmreg,xmmrm,imm \361\3\x0F\x3A\x08\110\26 SSE41 +ROUNDSD xmmreg,xmmrm,imm \361\3\x0F\x3A\x0B\110\26 SSE41 +ROUNDSS xmmreg,xmmrm,imm \361\3\x0F\x3A\x0A\110\26 SSE41 + +;# Nehalem New Instructions (SSE4.2) +CRC32 reg32,rm8 \332\3\x0F\x38\xF0\110 SSE42 +CRC32 reg32,rm16 \320\332\3\x0F\x38\xF1\110 SSE42 +CRC32 reg32,rm32 \321\332\3\x0F\x38\xF1\110 SSE42 +CRC32 reg64,rm8 \324\332\3\x0F\x38\xF0\110 SSE42,X64 +CRC32 reg64,rm64 \324\332\3\x0F\x38\xF1\110 SSE42,X64 +PCMPESTRI xmmreg,xmmrm,imm \361\3\x0F\x3A\x61\110\26 SSE42 +PCMPESTRM xmmreg,xmmrm,imm \361\3\x0F\x3A\x60\110\26 SSE42 +PCMPISTRI xmmreg,xmmrm,imm \361\3\x0F\x3A\x63\110\26 SSE42 +PCMPISTRM xmmreg,xmmrm,imm \361\3\x0F\x3A\x62\110\26 SSE42 +PCMPGTQ xmmreg,xmmrm \361\3\x0F\x38\x37\110 SSE42 +POPCNT reg16,rm16 \320\333\2\x0F\xB8\110 NEHALEM,SW +POPCNT reg32,rm32 \321\333\2\x0F\xB8\110 NEHALEM,SD +POPCNT reg64,rm64 \324\333\2\x0F\xB8\110 NEHALEM,SQ,X64 + +;# AMD SSE5 instructions + +; Four operands with DREX +FMADDPS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x00\132 SSE5,AMD +FMADDPS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x00\123 SSE5,AMD +FMADDPS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x04\121 SSE5,AMD +FMADDPS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x04\112 SSE5,AMD +FMADDPD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x01\132 SSE5,AMD +FMADDPD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x01\123 SSE5,AMD +FMADDPD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x05\121 SSE5,AMD +FMADDPD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x05\112 SSE5,AMD +FMADDSS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x02\132 SSE5,AMD +FMADDSS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x02\123 SSE5,AMD +FMADDSS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x06\121 SSE5,AMD +FMADDSS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x06\112 SSE5,AMD +FMADDSD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x03\132 SSE5,AMD +FMADDSD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x03\123 SSE5,AMD +FMADDSD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x07\121 SSE5,AMD +FMADDSD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x07\112 SSE5,AMD +FMSUBPS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x08\132 SSE5,AMD +FMSUBPS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x08\123 SSE5,AMD +FMSUBPS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x0C\121 SSE5,AMD +FMSUBPS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x0C\112 SSE5,AMD +FMSUBPD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x09\132 SSE5,AMD +FMSUBPD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x09\123 SSE5,AMD +FMSUBPD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x0D\121 SSE5,AMD +FMSUBPD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x0D\112 SSE5,AMD +FMSUBSS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x0A\132 SSE5,AMD +FMSUBSS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x0A\123 SSE5,AMD +FMSUBSS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x0E\121 SSE5,AMD +FMSUBSS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x0E\112 SSE5,AMD +FMSUBSD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x0B\132 SSE5,AMD +FMSUBSD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x0B\123 SSE5,AMD +FMSUBSD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x0F\121 SSE5,AMD +FMSUBSD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x0F\112 SSE5,AMD +FNMADDPS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x10\132 SSE5,AMD +FNMADDPS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x10\123 SSE5,AMD +FNMADDPS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x14\121 SSE5,AMD +FNMADDPS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x14\112 SSE5,AMD +FNMADDPD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x11\132 SSE5,AMD +FNMADDPD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x11\123 SSE5,AMD +FNMADDPD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x15\121 SSE5,AMD +FNMADDPD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x15\112 SSE5,AMD +FNMADDSS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x12\132 SSE5,AMD +FNMADDSS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x12\123 SSE5,AMD +FNMADDSS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x16\121 SSE5,AMD +FNMADDSS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x16\112 SSE5,AMD +FNMADDSD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x13\132 SSE5,AMD +FNMADDSD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x13\123 SSE5,AMD +FNMADDSD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x17\121 SSE5,AMD +FNMADDSD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x17\112 SSE5,AMD +FNMSUBPS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x18\132 SSE5,AMD +FNMSUBPS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x18\123 SSE5,AMD +FNMSUBPS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x1C\121 SSE5,AMD +FNMSUBPS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x1C\112 SSE5,AMD +FNMSUBPD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x19\132 SSE5,AMD +FNMSUBPD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x19\123 SSE5,AMD +FNMSUBPD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x1D\121 SSE5,AMD +FNMSUBPD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x1D\112 SSE5,AMD +FNMSUBSS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x1A\132 SSE5,AMD +FNMSUBSS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x1A\123 SSE5,AMD +FNMSUBSS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x1E\121 SSE5,AMD +FNMSUBSS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x1E\112 SSE5,AMD +FNMSUBSD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x1B\132 SSE5,AMD +FNMSUBSD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x1B\123 SSE5,AMD +FNMSUBSD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x1F\121 SSE5,AMD +FNMSUBSD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x1F\112 SSE5,AMD +; COMPS: aliases for specific versions first, then generic +COMEQPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 00] SSE5,AMD,SO +COMLTPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 01] SSE5,AMD,SO +COMLEPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 02] SSE5,AMD,SO +COMUNORDPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 03] SSE5,AMD,SO +COMUNEQPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 04] SSE5,AMD,SO +COMUNLTPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 05] SSE5,AMD,SO +COMUNLEPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 06] SSE5,AMD,SO +COMORDPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 07] SSE5,AMD,SO +COMUEQPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 08] SSE5,AMD,SO +COMULTPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 09] SSE5,AMD,SO +COMULEPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 0a] SSE5,AMD,SO +COMFALSEPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 0b] SSE5,AMD,SO +COMNEQPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 0c] SSE5,AMD,SO +COMNLTPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 0d] SSE5,AMD,SO +COMNLEPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 0e] SSE5,AMD,SO +COMTRUEPS xmmreg,xmmreg,xmmrm [drm: 0f 25 2c /r /drex0 0f] SSE5,AMD,SO +COMPS xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 2c /r /drex0 ib] SSE5,AMD,SO +; COMPD: aliases for specific versions first, then generic +COMEQPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 00] SSE5,AMD,SO +COMLTPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 01] SSE5,AMD,SO +COMLEPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 02] SSE5,AMD,SO +COMUNORDPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 03] SSE5,AMD,SO +COMUNEQPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 04] SSE5,AMD,SO +COMUNLTPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 05] SSE5,AMD,SO +COMUNLEPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 06] SSE5,AMD,SO +COMORDPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 07] SSE5,AMD,SO +COMUEQPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 08] SSE5,AMD,SO +COMULTPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 09] SSE5,AMD,SO +COMULEPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 0a] SSE5,AMD,SO +COMFALSEPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 0b] SSE5,AMD,SO +COMNEQPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 0c] SSE5,AMD,SO +COMNLTPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 0d] SSE5,AMD,SO +COMNLEPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 0e] SSE5,AMD,SO +COMTRUEPD xmmreg,xmmreg,xmmrm [drm: 0f 25 2d /r /drex0 0f] SSE5,AMD,SO +COMPD xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 2d /r /drex0 ib] SSE5,AMD,SO +; COMSS: aliases for specific versions first, then generic +COMEQSS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 00] SSE5,AMD,SD +COMLTSS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 01] SSE5,AMD,SD +COMLESS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 02] SSE5,AMD,SD +COMUNORDSS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 03] SSE5,AMD,SD +COMUNEQSS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 04] SSE5,AMD,SD +COMUNLTSS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 05] SSE5,AMD,SD +COMUNLESS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 06] SSE5,AMD,SD +COMORDSS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 07] SSE5,AMD,SD +COMUEQSS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 08] SSE5,AMD,SD +COMULTSS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 09] SSE5,AMD,SD +COMULESS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 0a] SSE5,AMD,SD +COMFALSESS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 0b] SSE5,AMD,SD +COMNEQSS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 0c] SSE5,AMD,SD +COMNLTSS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 0d] SSE5,AMD,SD +COMNLESS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 0e] SSE5,AMD,SD +COMTRUESS xmmreg,xmmreg,xmmrm [drm: 0f 25 2e /r /drex0 0f] SSE5,AMD,SD +COMSS xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 2e /r /drex0 ib] SSE5,AMD,SD +; COMSD: aliases for specific versions first, then generic +COMEQSD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 00] SSE5,AMD,SQ +COMLTSD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 01] SSE5,AMD,SQ +COMLESD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 02] SSE5,AMD,SQ +COMUNORDSD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 03] SSE5,AMD,SQ +COMUNEQSD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 04] SSE5,AMD,SQ +COMUNLTSD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 05] SSE5,AMD,SQ +COMUNLESD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 06] SSE5,AMD,SQ +COMORDSD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 07] SSE5,AMD,SQ +COMUEQSD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 08] SSE5,AMD,SQ +COMULTSD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 09] SSE5,AMD,SQ +COMULESD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 0a] SSE5,AMD,SQ +COMFALSESD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 0b] SSE5,AMD,SQ +COMNEQSD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 0c] SSE5,AMD,SQ +COMNLTSD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 0d] SSE5,AMD,SQ +COMNLESD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 0e] SSE5,AMD,SQ +COMTRUESD xmmreg,xmmreg,xmmrm [drm: 0f 25 2f /r /drex0 0f] SSE5,AMD,SQ +COMSD xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 2f /r /drex0 ib] SSE5,AMD,SQ +; PCOMB: aliases for specific versions first, then generic +PCOMLTB xmmreg,xmmreg,xmmrm [drm: 0f 25 4c /r /drex0 00] SSE5,AMD,SO +PCOMLEB xmmreg,xmmreg,xmmrm [drm: 0f 25 4c /r /drex0 01] SSE5,AMD,SO +PCOMGTB xmmreg,xmmreg,xmmrm [drm: 0f 25 4c /r /drex0 02] SSE5,AMD,SO +PCOMGEB xmmreg,xmmreg,xmmrm [drm: 0f 25 4c /r /drex0 03] SSE5,AMD,SO +PCOMEQB xmmreg,xmmreg,xmmrm [drm: 0f 25 4c /r /drex0 04] SSE5,AMD,SO +PCOMNEQB xmmreg,xmmreg,xmmrm [drm: 0f 25 4c /r /drex0 05] SSE5,AMD,SO +PCOMFALSEB xmmreg,xmmreg,xmmrm [drm: 0f 25 4c /r /drex0 06] SSE5,AMD,SO +PCOMTRUEB xmmreg,xmmreg,xmmrm [drm: 0f 25 4c /r /drex0 07] SSE5,AMD,SO +PCOMB xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 4c /r /drex0 ib] SSE5,AMD,SO +; PCOMW: aliases for specific versions first, then generic +PCOMLTW xmmreg,xmmreg,xmmrm [drm: 0f 25 4d /r /drex0 00] SSE5,AMD,SO +PCOMLEW xmmreg,xmmreg,xmmrm [drm: 0f 25 4d /r /drex0 01] SSE5,AMD,SO +PCOMGTW xmmreg,xmmreg,xmmrm [drm: 0f 25 4d /r /drex0 02] SSE5,AMD,SO +PCOMGEW xmmreg,xmmreg,xmmrm [drm: 0f 25 4d /r /drex0 03] SSE5,AMD,SO +PCOMEQW xmmreg,xmmreg,xmmrm [drm: 0f 25 4d /r /drex0 04] SSE5,AMD,SO +PCOMNEQW xmmreg,xmmreg,xmmrm [drm: 0f 25 4d /r /drex0 05] SSE5,AMD,SO +PCOMFALSEW xmmreg,xmmreg,xmmrm [drm: 0f 25 4d /r /drex0 06] SSE5,AMD,SO +PCOMTRUEW xmmreg,xmmreg,xmmrm [drm: 0f 25 4d /r /drex0 07] SSE5,AMD,SO +PCOMW xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 4d /r /drex0 ib] SSE5,AMD,SO +; PCOMD: aliases for specific versions first, then generic +PCOMLTD xmmreg,xmmreg,xmmrm [drm: 0f 25 4e /r /drex0 00] SSE5,AMD,SO +PCOMLED xmmreg,xmmreg,xmmrm [drm: 0f 25 4e /r /drex0 01] SSE5,AMD,SO +PCOMGTD xmmreg,xmmreg,xmmrm [drm: 0f 25 4e /r /drex0 02] SSE5,AMD,SO +PCOMGED xmmreg,xmmreg,xmmrm [drm: 0f 25 4e /r /drex0 03] SSE5,AMD,SO +PCOMEQD xmmreg,xmmreg,xmmrm [drm: 0f 25 4e /r /drex0 04] SSE5,AMD,SO +PCOMNEQD xmmreg,xmmreg,xmmrm [drm: 0f 25 4e /r /drex0 05] SSE5,AMD,SO +PCOMFALSED xmmreg,xmmreg,xmmrm [drm: 0f 25 4e /r /drex0 06] SSE5,AMD,SO +PCOMTRUED xmmreg,xmmreg,xmmrm [drm: 0f 25 4e /r /drex0 07] SSE5,AMD,SO +PCOMD xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 4e /r /drex0 ib] SSE5,AMD,SO +; PCOMQ: aliases for specific versions first, then generic +PCOMLTQ xmmreg,xmmreg,xmmrm [drm: 0f 25 4f /r /drex0 00] SSE5,AMD,SO +PCOMLEQ xmmreg,xmmreg,xmmrm [drm: 0f 25 4f /r /drex0 01] SSE5,AMD,SO +PCOMGTQ xmmreg,xmmreg,xmmrm [drm: 0f 25 4f /r /drex0 02] SSE5,AMD,SO +PCOMGEQ xmmreg,xmmreg,xmmrm [drm: 0f 25 4f /r /drex0 03] SSE5,AMD,SO +PCOMEQQ xmmreg,xmmreg,xmmrm [drm: 0f 25 4f /r /drex0 04] SSE5,AMD,SO +PCOMNEQQ xmmreg,xmmreg,xmmrm [drm: 0f 25 4f /r /drex0 05] SSE5,AMD,SO +PCOMFALSEQ xmmreg,xmmreg,xmmrm [drm: 0f 25 4f /r /drex0 06] SSE5,AMD,SO +PCOMTRUEQ xmmreg,xmmreg,xmmrm [drm: 0f 25 4f /r /drex0 07] SSE5,AMD,SO +PCOMQ xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 4f /r /drex0 ib] SSE5,AMD,SO +; PCOMUB: aliases for specific versions first, then generic +PCOMLTUB xmmreg,xmmreg,xmmrm [drm: 0f 25 6c /r /drex0 00] SSE5,AMD,SO +PCOMLEUB xmmreg,xmmreg,xmmrm [drm: 0f 25 6c /r /drex0 01] SSE5,AMD,SO +PCOMGTUB xmmreg,xmmreg,xmmrm [drm: 0f 25 6c /r /drex0 02] SSE5,AMD,SO +PCOMGEUB xmmreg,xmmreg,xmmrm [drm: 0f 25 6c /r /drex0 03] SSE5,AMD,SO +PCOMEQUB xmmreg,xmmreg,xmmrm [drm: 0f 25 6c /r /drex0 04] SSE5,AMD,SO +PCOMNEQUB xmmreg,xmmreg,xmmrm [drm: 0f 25 6c /r /drex0 05] SSE5,AMD,SO +PCOMFALSEUB xmmreg,xmmreg,xmmrm [drm: 0f 25 6c /r /drex0 06] SSE5,AMD,SO +PCOMTRUEUB xmmreg,xmmreg,xmmrm [drm: 0f 25 6c /r /drex0 07] SSE5,AMD,SO +PCOMUB xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 6c /r /drex0 ib] SSE5,AMD,SO +; PCOMUW: aliases for specific versions first, then generic +PCOMLTUW xmmreg,xmmreg,xmmrm [drm: 0f 25 6d /r /drex0 00] SSE5,AMD,SO +PCOMLEUW xmmreg,xmmreg,xmmrm [drm: 0f 25 6d /r /drex0 01] SSE5,AMD,SO +PCOMGTUW xmmreg,xmmreg,xmmrm [drm: 0f 25 6d /r /drex0 02] SSE5,AMD,SO +PCOMGEUW xmmreg,xmmreg,xmmrm [drm: 0f 25 6d /r /drex0 03] SSE5,AMD,SO +PCOMEQUW xmmreg,xmmreg,xmmrm [drm: 0f 25 6d /r /drex0 04] SSE5,AMD,SO +PCOMNEQUW xmmreg,xmmreg,xmmrm [drm: 0f 25 6d /r /drex0 05] SSE5,AMD,SO +PCOMFALSEUW xmmreg,xmmreg,xmmrm [drm: 0f 25 6d /r /drex0 06] SSE5,AMD,SO +PCOMTRUEUW xmmreg,xmmreg,xmmrm [drm: 0f 25 6d /r /drex0 07] SSE5,AMD,SO +PCOMUW xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 6d /r /drex0 ib] SSE5,AMD,SO +; PCOMUD: aliases for specific versions first, then generic +PCOMLTUD xmmreg,xmmreg,xmmrm [drm: 0f 25 6e /r /drex0 00] SSE5,AMD,SO +PCOMLEUD xmmreg,xmmreg,xmmrm [drm: 0f 25 6e /r /drex0 01] SSE5,AMD,SO +PCOMGTUD xmmreg,xmmreg,xmmrm [drm: 0f 25 6e /r /drex0 02] SSE5,AMD,SO +PCOMGEUD xmmreg,xmmreg,xmmrm [drm: 0f 25 6e /r /drex0 03] SSE5,AMD,SO +PCOMEQUD xmmreg,xmmreg,xmmrm [drm: 0f 25 6e /r /drex0 04] SSE5,AMD,SO +PCOMNEQUD xmmreg,xmmreg,xmmrm [drm: 0f 25 6e /r /drex0 05] SSE5,AMD,SO +PCOMFALSEUD xmmreg,xmmreg,xmmrm [drm: 0f 25 6e /r /drex0 06] SSE5,AMD,SO +PCOMTRUEUD xmmreg,xmmreg,xmmrm [drm: 0f 25 6e /r /drex0 07] SSE5,AMD,SO +PCOMUD xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 6e /r /drex0 ib] SSE5,AMD,SO +; PCOMUQ: aliases for specific versions first, then generic +PCOMLTUQ xmmreg,xmmreg,xmmrm [drm: 0f 25 6f /r /drex0 00] SSE5,AMD,SO +PCOMLEUQ xmmreg,xmmreg,xmmrm [drm: 0f 25 6f /r /drex0 01] SSE5,AMD,SO +PCOMGTUQ xmmreg,xmmreg,xmmrm [drm: 0f 25 6f /r /drex0 02] SSE5,AMD,SO +PCOMGEUQ xmmreg,xmmreg,xmmrm [drm: 0f 25 6f /r /drex0 03] SSE5,AMD,SO +PCOMEQUQ xmmreg,xmmreg,xmmrm [drm: 0f 25 6f /r /drex0 04] SSE5,AMD,SO +PCOMNEQUQ xmmreg,xmmreg,xmmrm [drm: 0f 25 6f /r /drex0 05] SSE5,AMD,SO +PCOMFALSEUQ xmmreg,xmmreg,xmmrm [drm: 0f 25 6f /r /drex0 06] SSE5,AMD,SO +PCOMTRUEUQ xmmreg,xmmreg,xmmrm [drm: 0f 25 6f /r /drex0 07] SSE5,AMD,SO +PCOMUQ xmmreg,xmmreg,xmmrm,imm [drmi: 0f 25 6f /r /drex0 ib] SSE5,AMD,SO +PERMPS xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x20\132 SSE5,AMD +PERMPS xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x20\123 SSE5,AMD +PERMPS xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x24\121 SSE5,AMD +PERMPS xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x24\112 SSE5,AMD +PERMPD xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x21\132 SSE5,AMD +PERMPD xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x21\123 SSE5,AMD +PERMPD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x25\121 SSE5,AMD +PERMPD xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x25\112 SSE5,AMD +PCMOV xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x22\132 SSE5,AMD +PCMOV xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x22\123 SSE5,AMD +PCMOV xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x26\121 SSE5,AMD +PCMOV xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x26\112 SSE5,AMD +PPERM xmmreg,=0,xmmreg,xmmrm \160\3\x0F\x24\x23\132 SSE5,AMD +PPERM xmmreg,=0,xmmrm,xmmreg \164\3\x0F\x24\x23\123 SSE5,AMD +PPERM xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x27\121 SSE5,AMD +PPERM xmmreg,xmmrm,xmmreg,=0 \164\3\x0F\x24\x27\112 SSE5,AMD +PMACSSWW xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x85\121 SSE5,AMD +PMACSWW xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x95\121 SSE5,AMD +PMACSSWD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x86\121 SSE5,AMD +PMACSWD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x96\121 SSE5,AMD +PMACSSDD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x8E\121 SSE5,AMD +PMACSDD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x9E\121 SSE5,AMD +PMACSSDQL xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x87\121 SSE5,AMD +PMACSDQL xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x97\121 SSE5,AMD +PMACSSDQH xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x8F\121 SSE5,AMD +PMACSDQH xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\x9F\121 SSE5,AMD +PMADCSSWD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\xA6\121 SSE5,AMD +PMADCSWD xmmreg,xmmreg,xmmrm,=0 \160\3\x0F\x24\xB6\121 SSE5,AMD + +; Three operands with DREX +PROTB xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x40\121 SSE5,AMD +PROTB xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x40\112 SSE5,AMD +PROTW xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x41\121 SSE5,AMD +PROTW xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x41\112 SSE5,AMD +PROTD xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x42\121 SSE5,AMD +PROTD xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x42\112 SSE5,AMD +PROTQ xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x43\121 SSE5,AMD +PROTQ xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x43\112 SSE5,AMD +PSHLB xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x44\121 SSE5,AMD +PSHLB xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x44\112 SSE5,AMD +PSHLW xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x45\121 SSE5,AMD +PSHLW xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x45\112 SSE5,AMD +PSHLD xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x46\121 SSE5,AMD +PSHLD xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x46\112 SSE5,AMD +PSHLQ xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x47\121 SSE5,AMD +PSHLQ xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x47\112 SSE5,AMD +PSHAB xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x48\121 SSE5,AMD +PSHAB xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x48\112 SSE5,AMD +PSHAW xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x49\121 SSE5,AMD +PSHAW xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x49\112 SSE5,AMD +PSHAD xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x4A\121 SSE5,AMD +PSHAD xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x4A\112 SSE5,AMD +PSHAQ xmmreg,xmmreg,xmmrm \160\3\x0F\x24\x4B\121 SSE5,AMD +PSHAQ xmmreg,xmmrm,xmmreg \164\3\x0F\x24\x4B\112 SSE5,AMD + +; Non-DREX +FRCZPS xmmreg,xmmrm \360\3\x0F\x7A\x10\110 SSE5,AMD +FRCZPD xmmreg,xmmrm \360\3\x0F\x7A\x11\110 SSE5,AMD +FRCZSS xmmreg,xmmrm \360\3\x0F\x7A\x12\110 SSE5,AMD +FRCZSD xmmreg,xmmrm \360\3\x0F\x7A\x13\110 SSE5,AMD +CVTPH2PS xmmreg,xmmrm \360\3\x0F\x7A\x30\110 SSE5,AMD,SQ +CVTPS2PH xmmrm,xmmreg \360\3\x0F\x7A\x31\101 SSE5,AMD,SQ +PHADDBW xmmreg,xmmrm \360\3\x0F\x7A\x41\110 SSE5,AMD +PHADDBD xmmreg,xmmrm \360\3\x0F\x7A\x42\110 SSE5,AMD +PHADDBQ xmmreg,xmmrm \360\3\x0F\x7A\x43\110 SSE5,AMD +PHADDWD xmmreg,xmmrm \360\3\x0F\x7A\x46\110 SSE5,AMD +PHADDWQ xmmreg,xmmrm \360\3\x0F\x7A\x47\110 SSE5,AMD +PHADDDQ xmmreg,xmmrm \360\3\x0F\x7A\x4B\110 SSE5,AMD +PHADDUBW xmmreg,xmmrm \360\3\x0F\x7A\x51\110 SSE5,AMD +PHADDUBD xmmreg,xmmrm \360\3\x0F\x7A\x52\110 SSE5,AMD +PHADDUBQ xmmreg,xmmrm \360\3\x0F\x7A\x53\110 SSE5,AMD +PHADDUWD xmmreg,xmmrm \360\3\x0F\x7A\x56\110 SSE5,AMD +PHADDUWQ xmmreg,xmmrm \360\3\x0F\x7A\x57\110 SSE5,AMD +PHADDUDQ xmmreg,xmmrm \360\3\x0F\x7A\x5B\110 SSE5,AMD +PHSUBBW xmmreg,xmmrm \360\3\x0F\x7A\x61\110 SSE5,AMD +PHSUBWD xmmreg,xmmrm \360\3\x0F\x7A\x62\110 SSE5,AMD +PHSUBDQ xmmreg,xmmrm \360\3\x0F\x7A\x63\110 SSE5,AMD +PROTB xmmreg,xmmrm,imm \360\3\x0F\x7B\x40\110\26 SSE5,AMD +PROTW xmmreg,xmmrm,imm \360\3\x0F\x7B\x41\110\26 SSE5,AMD +PROTD xmmreg,xmmrm,imm \360\3\x0F\x7B\x42\110\26 SSE5,AMD +PROTQ xmmreg,xmmrm,imm \360\3\x0F\x7B\x43\110\26 SSE5,AMD +ROUNDPS xmmreg,xmmrm,imm \361\3\x0F\x3A\x08\110\26 SSE5,AMD +ROUNDPD xmmreg,xmmrm,imm \361\3\x0F\x3A\x08\110\26 SSE5,AMD +ROUNDSS xmmreg,xmmrm,imm \361\3\x0F\x3A\x08\110\26 SSE5,AMD +ROUNDSD xmmreg,xmmrm,imm \361\3\x0F\x3A\x08\110\26 SSE5,AMD + +;# Intel SMX +GETSEC void \2\x0F\x37 KATMAI + +;# Geode (Cyrix) 3DNow! additions +PFRCPV mmxreg,mmxrm \323\2\x0F\x0F\110\1\x86 PENT,3DNOW,SQ,CYRIX +PFRSQRTV mmxreg,mmxrm \323\2\x0F\x0F\110\1\x87 PENT,3DNOW,SQ,CYRIX + +;# Intel new instructions in ??? +; Is NEHALEM right here? +MOVBE reg16,mem16 [rm: o16 0f 38 f0 /r] NEHALEM,SM +MOVBE reg32,mem32 [rm: o32 0f 38 f0 /r] NEHALEM,SM +MOVBE reg64,mem64 [rm: o64 0f 38 f0 /r] NEHALEM,SM +MOVBE mem16,reg16 [mr: o16 0f 38 f1 /r] NEHALEM,SM +MOVBE mem32,reg32 [mr: o32 0f 38 f1 /r] NEHALEM,SM +MOVBE mem64,reg64 [mr: o64 0f 38 f1 /r] NEHALEM,SM + +;# Intel AES instructions +AESENC xmmreg,xmmrm [rm: 66 0f 38 dc /r] SSE,WESTMERE,SO +AESENCLAST xmmreg,xmmrm [rm: 66 0f 38 dd /r] SSE,WESTMERE,SO +AESDEC xmmreg,xmmrm [rm: 66 0f 38 de /r] SSE,WESTMERE,SO +AESDECLAST xmmreg,xmmrm [rm: 66 0f 38 df /r] SSE,WESTMERE,SO +AESIMC xmmreg,xmmrm [rm: 66 0f 38 db /r] SSE,WESTMERE,SO +AESKEYGENASSIST xmmreg,xmmrm,imm [rmi: 66 0f 3a df /r ib] SSE,WESTMERE,SO + +;# Intel AVX AES instructions +VAESENC xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 dc /r] AVX,SANDYBRIDGE,SO +VAESENC xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 dc /r] AVX,SANDYBRIDGE,SO +VAESENCLAST xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 dd /r] AVX,SANDYBRIDGE,SO +VAESENCLAST xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 dd /r] AVX,SANDYBRIDGE,SO +VAESDEC xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 de /r] AVX,SANDYBRIDGE,SO +VAESDEC xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 de /r] AVX,SANDYBRIDGE,SO +VAESDECLAST xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 df /r] AVX,SANDYBRIDGE,SO +VAESDECLAST xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 df /r] AVX,SANDYBRIDGE,SO +VAESIMC xmmreg,xmmrm [rm: vex.128.66.0f38 db /r] AVX,SANDYBRIDGE,SO +VAESKEYGENASSIST xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a df /r ib] AVX,SANDYBRIDGE,SO + +;# Intel AVX instructions +VADDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 58 /r] AVX,SANDYBRIDGE,SO +VADDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 58 /r] AVX,SANDYBRIDGE,SO +VADDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 58 /r] AVX,SANDYBRIDGE,SY +VADDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 58 /r] AVX,SANDYBRIDGE,SY +VADDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 58 /r] AVX,SANDYBRIDGE,SO +VADDPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 58 /r] AVX,SANDYBRIDGE,SO +VADDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 58 /r] AVX,SANDYBRIDGE,SY +VADDPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 58 /r] AVX,SANDYBRIDGE,SY +VADDSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 58 /r] AVX,SANDYBRIDGE,SQ +VADDSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 58 /r] AVX,SANDYBRIDGE,SQ +VADDSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 58 /r] AVX,SANDYBRIDGE,SD +VADDSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 58 /r] AVX,SANDYBRIDGE,SD +VADDSUBPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d0 /r] AVX,SANDYBRIDGE,SO +VADDSUBPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d0 /r] AVX,SANDYBRIDGE,SO +VADDSUBPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f d0 /r] AVX,SANDYBRIDGE,SY +VADDSUBPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f d0 /r] AVX,SANDYBRIDGE,SY +VADDSUBPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f d0 /r] AVX,SANDYBRIDGE,SO +VADDSUBPS xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f d0 /r] AVX,SANDYBRIDGE,SO +VADDSUBPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.f2.0f d0 /r] AVX,SANDYBRIDGE,SY +VADDSUBPS ymmreg,ymmrm [r+vm: vex.nds.256.f2.0f d0 /r] AVX,SANDYBRIDGE,SY +VANDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 54 /r] AVX,SANDYBRIDGE,SO +VANDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 54 /r] AVX,SANDYBRIDGE,SO +VANDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 54 /r] AVX,SANDYBRIDGE,SY +VANDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 54 /r] AVX,SANDYBRIDGE,SY +VANDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 54 /r] AVX,SANDYBRIDGE,SO +VANDPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 54 /r] AVX,SANDYBRIDGE,SO +VANDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 54 /r] AVX,SANDYBRIDGE,SY +VANDPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 54 /r] AVX,SANDYBRIDGE,SY +VANDNPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 55 /r] AVX,SANDYBRIDGE,SO +VANDNPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 55 /r] AVX,SANDYBRIDGE,SO +VANDNPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 55 /r] AVX,SANDYBRIDGE,SY +VANDNPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 55 /r] AVX,SANDYBRIDGE,SY +VANDNPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 55 /r] AVX,SANDYBRIDGE,SO +VANDNPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 55 /r] AVX,SANDYBRIDGE,SO +VANDNPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 55 /r] AVX,SANDYBRIDGE,SY +VANDNPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 55 /r] AVX,SANDYBRIDGE,SY +VBLENDPD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0d /r ib] AVX,SANDYBRIDGE,SO +VBLENDPD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0d /r ib] AVX,SANDYBRIDGE,SO +VBLENDPD ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 0d /r ib] AVX,SANDYBRIDGE,SY +VBLENDPD ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f3a 0d /r ib] AVX,SANDYBRIDGE,SY +VBLENDPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SO +VBLENDPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SO +VBLENDPS ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SY +VBLENDPS ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f3a 0c /r ib] AVX,SANDYBRIDGE,SY +VBLENDVPD xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a 4b /r /is4] AVX,SANDYBRIDGE,SO +VBLENDVPD xmmreg,xmmrm,xmm0 [rm-: vex.128.66.0f38 15 /r] AVX,SANDYBRIDGE,SO +VBLENDVPD ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a 4b /r /is4] AVX,SANDYBRIDGE,SY +VBLENDVPD ymmreg,ymmrm,ymm0 [rm-: vex.256.66.0f38 15 /r] AVX,SANDYBRIDGE,SY +VBLENDVPS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a 4a /r /is4] AVX,SANDYBRIDGE,SO +VBLENDVPS xmmreg,xmmrm,xmm0 [rm-: vex.128.66.0f38 14 /r] AVX,SANDYBRIDGE,SO +VBLENDVPS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a 4a /r /is4] AVX,SANDYBRIDGE,SY +VBLENDVPD ymmreg,ymmrm,ymm0 [rm-: vex.256.66.0f38 14 /r] AVX,SANDYBRIDGE,SY +VBROADCASTSS xmmreg,mem [rm: vex.128.66.0f38 18 /r] AVX,SANDYBRIDGE,SD +VBROADCASTSS ymmreg,mem [rm: vex.256.66.0f38 18 /r] AVX,SANDYBRIDGE,SD +VBROADCASTSD ymmreg,mem [rm: vex.256.66.0f38 19 /r] AVX,SANDYBRIDGE,SQ +VBROADCASTF128 ymmreg,mem [rm: vex.256.66.0f38 1a /r] AVX,SANDYBRIDGE,SO +; Specific aliases first, then the generic version, to keep the disassembler happy... +VCMPEQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 00] AVX,SANDYBRIDGE,SO +VCMPEQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 00] AVX,SANDYBRIDGE,SO +VCMPEQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 00] AVX,SANDYBRIDGE,SY +VCMPEQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 00] AVX,SANDYBRIDGE,SY +VCMPLTPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 01] AVX,SANDYBRIDGE,SO +VCMPLTPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 01] AVX,SANDYBRIDGE,SO +VCMPLTPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 01] AVX,SANDYBRIDGE,SY +VCMPLTPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 01] AVX,SANDYBRIDGE,SY +VCMPLEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 02] AVX,SANDYBRIDGE,SO +VCMPLEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 02] AVX,SANDYBRIDGE,SO +VCMPLEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 02] AVX,SANDYBRIDGE,SY +VCMPLEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 02] AVX,SANDYBRIDGE,SY +VCMPUNORDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 03] AVX,SANDYBRIDGE,SO +VCMPUNORDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 03] AVX,SANDYBRIDGE,SO +VCMPUNORDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 03] AVX,SANDYBRIDGE,SY +VCMPUNORDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 03] AVX,SANDYBRIDGE,SY +VCMPNEQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 04] AVX,SANDYBRIDGE,SO +VCMPNEQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 04] AVX,SANDYBRIDGE,SO +VCMPNEQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 04] AVX,SANDYBRIDGE,SY +VCMPNEQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 04] AVX,SANDYBRIDGE,SY +VCMPNLTPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 05] AVX,SANDYBRIDGE,SO +VCMPNLTPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 05] AVX,SANDYBRIDGE,SO +VCMPNLTPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 05] AVX,SANDYBRIDGE,SY +VCMPNLTPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 05] AVX,SANDYBRIDGE,SY +VCMPNLEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 06] AVX,SANDYBRIDGE,SO +VCMPNLEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 06] AVX,SANDYBRIDGE,SO +VCMPNLEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 06] AVX,SANDYBRIDGE,SY +VCMPNLEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 06] AVX,SANDYBRIDGE,SY +VCMPORDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 07] AVX,SANDYBRIDGE,SO +VCMPORDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 07] AVX,SANDYBRIDGE,SO +VCMPORDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 07] AVX,SANDYBRIDGE,SY +VCMPORDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 07] AVX,SANDYBRIDGE,SY +VCMPEQ_UQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 08] AVX,SANDYBRIDGE,SO +VCMPEQ_UQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 08] AVX,SANDYBRIDGE,SO +VCMPEQ_UQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 08] AVX,SANDYBRIDGE,SY +VCMPEQ_UQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 08] AVX,SANDYBRIDGE,SY +VCMPNGEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 09] AVX,SANDYBRIDGE,SO +VCMPNGEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 09] AVX,SANDYBRIDGE,SO +VCMPNGEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 09] AVX,SANDYBRIDGE,SY +VCMPNGEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 09] AVX,SANDYBRIDGE,SY +VCMPNGTPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0a] AVX,SANDYBRIDGE,SO +VCMPNGTPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0a] AVX,SANDYBRIDGE,SO +VCMPNGTPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0a] AVX,SANDYBRIDGE,SY +VCMPNGTPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0a] AVX,SANDYBRIDGE,SY +VCMPFALSEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0b] AVX,SANDYBRIDGE,SO +VCMPFALSEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0b] AVX,SANDYBRIDGE,SO +VCMPFALSEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0b] AVX,SANDYBRIDGE,SY +VCMPFALSEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0b] AVX,SANDYBRIDGE,SY +VCMPNEQ_OQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0c] AVX,SANDYBRIDGE,SY +VCMPNEQ_OQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0c] AVX,SANDYBRIDGE,SY +VCMPGEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0d] AVX,SANDYBRIDGE,SO +VCMPGEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0d] AVX,SANDYBRIDGE,SO +VCMPGEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0d] AVX,SANDYBRIDGE,SY +VCMPGEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0d] AVX,SANDYBRIDGE,SY +VCMPGTPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0e] AVX,SANDYBRIDGE,SO +VCMPGTPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0e] AVX,SANDYBRIDGE,SO +VCMPGTPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0e] AVX,SANDYBRIDGE,SY +VCMPGTPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0e] AVX,SANDYBRIDGE,SY +VCMPTRUEPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 0f] AVX,SANDYBRIDGE,SO +VCMPTRUEPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 0f] AVX,SANDYBRIDGE,SO +VCMPTRUEPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 0f] AVX,SANDYBRIDGE,SY +VCMPTRUEPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 0f] AVX,SANDYBRIDGE,SY +VCMPEQ_OSPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 10] AVX,SANDYBRIDGE,SO +VCMPEQ_OSPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 10] AVX,SANDYBRIDGE,SO +VCMPEQ_OSPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 10] AVX,SANDYBRIDGE,SY +VCMPEQ_OSPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 10] AVX,SANDYBRIDGE,SY +VCMPLT_OQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 11] AVX,SANDYBRIDGE,SO +VCMPLT_OQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 11] AVX,SANDYBRIDGE,SO +VCMPLT_OQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 11] AVX,SANDYBRIDGE,SY +VCMPLT_OQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 11] AVX,SANDYBRIDGE,SY +VCMPLE_OQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 12] AVX,SANDYBRIDGE,SO +VCMPLE_OQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 12] AVX,SANDYBRIDGE,SO +VCMPLE_OQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 12] AVX,SANDYBRIDGE,SY +VCMPLE_OQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 12] AVX,SANDYBRIDGE,SY +VCMPUNORD_SPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 13] AVX,SANDYBRIDGE,SO +VCMPUNORD_SPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 13] AVX,SANDYBRIDGE,SO +VCMPUNORD_SPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 13] AVX,SANDYBRIDGE,SY +VCMPUNORD_SPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 13] AVX,SANDYBRIDGE,SY +VCMPNEQ_USPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 14] AVX,SANDYBRIDGE,SO +VCMPNEQ_USPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 14] AVX,SANDYBRIDGE,SO +VCMPNEQ_USPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 14] AVX,SANDYBRIDGE,SY +VCMPNEQ_USPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 14] AVX,SANDYBRIDGE,SY +VCMPNLT_UQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 15] AVX,SANDYBRIDGE,SO +VCMPNLT_UQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 15] AVX,SANDYBRIDGE,SO +VCMPNLT_UQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 15] AVX,SANDYBRIDGE,SY +VCMPNLT_UQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 15] AVX,SANDYBRIDGE,SY +VCMPNLE_UQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 16] AVX,SANDYBRIDGE,SO +VCMPNLE_UQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 16] AVX,SANDYBRIDGE,SO +VCMPNLE_UQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 16] AVX,SANDYBRIDGE,SY +VCMPNLE_UQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 16] AVX,SANDYBRIDGE,SY +VCMPORD_SPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 17] AVX,SANDYBRIDGE,SO +VCMPORD_SPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 17] AVX,SANDYBRIDGE,SO +VCMPORD_SPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 17] AVX,SANDYBRIDGE,SY +VCMPORS_SPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 17] AVX,SANDYBRIDGE,SY +VCMPEQ_USPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 18] AVX,SANDYBRIDGE,SO +VCMPEQ_USPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 18] AVX,SANDYBRIDGE,SO +VCMPEQ_USPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 18] AVX,SANDYBRIDGE,SY +VCMPEQ_USPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 18] AVX,SANDYBRIDGE,SY +VCMPNGE_UQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 19] AVX,SANDYBRIDGE,SO +VCMPNGE_UQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 19] AVX,SANDYBRIDGE,SO +VCMPNGE_UQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 19] AVX,SANDYBRIDGE,SY +VCMPNGE_UQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 19] AVX,SANDYBRIDGE,SY +VCMPNGT_UQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1a] AVX,SANDYBRIDGE,SO +VCMPNGT_UQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1a] AVX,SANDYBRIDGE,SO +VCMPNGT_UQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1a] AVX,SANDYBRIDGE,SY +VCMPNGT_UQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1a] AVX,SANDYBRIDGE,SY +VCMPFALSE_OSPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1b] AVX,SANDYBRIDGE,SO +VCMPFALSE_OSPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1b] AVX,SANDYBRIDGE,SO +VCMPFALSE_OSPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1b] AVX,SANDYBRIDGE,SY +VCMPFALSE_OSPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1b] AVX,SANDYBRIDGE,SY +VCMPNEQ_OSPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OSPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OSPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1c] AVX,SANDYBRIDGE,SY +VCMPNEQ_OSPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1c] AVX,SANDYBRIDGE,SY +VCMPGE_OQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1d] AVX,SANDYBRIDGE,SO +VCMPGE_OQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1d] AVX,SANDYBRIDGE,SO +VCMPGE_OQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1d] AVX,SANDYBRIDGE,SY +VCMPGE_OQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1d] AVX,SANDYBRIDGE,SY +VCMPGT_OQPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1e] AVX,SANDYBRIDGE,SO +VCMPGT_OQPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1e] AVX,SANDYBRIDGE,SO +VCMPGT_OQPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1e] AVX,SANDYBRIDGE,SY +VCMPGT_OQPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1e] AVX,SANDYBRIDGE,SY +VCMPTRUE_USPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f c2 /r 1f] AVX,SANDYBRIDGE,SO +VCMPTRUE_USPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f c2 /r 1f] AVX,SANDYBRIDGE,SO +VCMPTRUE_USPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f c2 /r 1f] AVX,SANDYBRIDGE,SY +VCMPTRUE_USPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f c2 /r 1f] AVX,SANDYBRIDGE,SY +VCMPPD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f c2 /r ib] AVX,SANDYBRIDGE,SO +VCMPPD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f c2 /r ib] AVX,SANDYBRIDGE,SO +VCMPPD ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f c2 /r ib] AVX,SANDYBRIDGE,SY +VCMPPD ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f c2 /r ib] AVX,SANDYBRIDGE,SY +; Specific aliases first, then the generic version, to keep the disassembler happy... +VCMPEQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 00] AVX,SANDYBRIDGE,SO +VCMPEQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 00] AVX,SANDYBRIDGE,SO +VCMPEQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 00] AVX,SANDYBRIDGE,SY +VCMPEQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 00] AVX,SANDYBRIDGE,SY +VCMPLTPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 01] AVX,SANDYBRIDGE,SO +VCMPLTPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 01] AVX,SANDYBRIDGE,SO +VCMPLTPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 01] AVX,SANDYBRIDGE,SY +VCMPLTPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 01] AVX,SANDYBRIDGE,SY +VCMPLEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 02] AVX,SANDYBRIDGE,SO +VCMPLEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 02] AVX,SANDYBRIDGE,SO +VCMPLEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 02] AVX,SANDYBRIDGE,SY +VCMPLEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 02] AVX,SANDYBRIDGE,SY +VCMPUNORDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 03] AVX,SANDYBRIDGE,SO +VCMPUNORDPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 03] AVX,SANDYBRIDGE,SO +VCMPUNORDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 03] AVX,SANDYBRIDGE,SY +VCMPUNORDPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 03] AVX,SANDYBRIDGE,SY +VCMPNEQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 04] AVX,SANDYBRIDGE,SO +VCMPNEQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 04] AVX,SANDYBRIDGE,SO +VCMPNEQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 04] AVX,SANDYBRIDGE,SY +VCMPNEQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 04] AVX,SANDYBRIDGE,SY +VCMPNLTPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 05] AVX,SANDYBRIDGE,SO +VCMPNLTPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 05] AVX,SANDYBRIDGE,SO +VCMPNLTPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 05] AVX,SANDYBRIDGE,SY +VCMPNLTPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 05] AVX,SANDYBRIDGE,SY +VCMPNLEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 06] AVX,SANDYBRIDGE,SO +VCMPNLEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 06] AVX,SANDYBRIDGE,SO +VCMPNLEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 06] AVX,SANDYBRIDGE,SY +VCMPNLEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 06] AVX,SANDYBRIDGE,SY +VCMPORDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 07] AVX,SANDYBRIDGE,SO +VCMPORDPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 07] AVX,SANDYBRIDGE,SO +VCMPORDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 07] AVX,SANDYBRIDGE,SY +VCMPORDPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 07] AVX,SANDYBRIDGE,SY +VCMPEQ_UQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 08] AVX,SANDYBRIDGE,SO +VCMPEQ_UQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 08] AVX,SANDYBRIDGE,SO +VCMPEQ_UQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 08] AVX,SANDYBRIDGE,SY +VCMPEQ_UQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 08] AVX,SANDYBRIDGE,SY +VCMPNGEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 09] AVX,SANDYBRIDGE,SO +VCMPNGEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 09] AVX,SANDYBRIDGE,SO +VCMPNGEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 09] AVX,SANDYBRIDGE,SY +VCMPNGEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 09] AVX,SANDYBRIDGE,SY +VCMPNGTPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0a] AVX,SANDYBRIDGE,SO +VCMPNGTPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0a] AVX,SANDYBRIDGE,SO +VCMPNGTPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0a] AVX,SANDYBRIDGE,SY +VCMPNGTPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0a] AVX,SANDYBRIDGE,SY +VCMPFALSEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0b] AVX,SANDYBRIDGE,SO +VCMPFALSEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0b] AVX,SANDYBRIDGE,SO +VCMPFALSEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0b] AVX,SANDYBRIDGE,SY +VCMPFALSEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0b] AVX,SANDYBRIDGE,SY +VCMPNEQ_OQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0c] AVX,SANDYBRIDGE,SY +VCMPNEQ_OQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0c] AVX,SANDYBRIDGE,SY +VCMPGEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0d] AVX,SANDYBRIDGE,SO +VCMPGEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0d] AVX,SANDYBRIDGE,SO +VCMPGEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0d] AVX,SANDYBRIDGE,SY +VCMPGEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0d] AVX,SANDYBRIDGE,SY +VCMPGTPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0e] AVX,SANDYBRIDGE,SO +VCMPGTPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0e] AVX,SANDYBRIDGE,SO +VCMPGTPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0e] AVX,SANDYBRIDGE,SY +VCMPGTPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0e] AVX,SANDYBRIDGE,SY +VCMPTRUEPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 0f] AVX,SANDYBRIDGE,SO +VCMPTRUEPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 0f] AVX,SANDYBRIDGE,SO +VCMPTRUEPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 0f] AVX,SANDYBRIDGE,SY +VCMPTRUEPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 0f] AVX,SANDYBRIDGE,SY +VCMPEQ_OSPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 10] AVX,SANDYBRIDGE,SO +VCMPEQ_OSPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 10] AVX,SANDYBRIDGE,SO +VCMPEQ_OSPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 10] AVX,SANDYBRIDGE,SY +VCMPEQ_OSPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 10] AVX,SANDYBRIDGE,SY +VCMPLT_OQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 11] AVX,SANDYBRIDGE,SO +VCMPLT_OQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 11] AVX,SANDYBRIDGE,SO +VCMPLT_OQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 11] AVX,SANDYBRIDGE,SY +VCMPLT_OQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 11] AVX,SANDYBRIDGE,SY +VCMPLE_OQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 12] AVX,SANDYBRIDGE,SO +VCMPLE_OQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 12] AVX,SANDYBRIDGE,SO +VCMPLE_OQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 12] AVX,SANDYBRIDGE,SY +VCMPLE_OQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 12] AVX,SANDYBRIDGE,SY +VCMPUNORD_SPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 13] AVX,SANDYBRIDGE,SO +VCMPUNORD_SPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 13] AVX,SANDYBRIDGE,SO +VCMPUNORD_SPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 13] AVX,SANDYBRIDGE,SY +VCMPUNORD_SPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 13] AVX,SANDYBRIDGE,SY +VCMPNEQ_USPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 14] AVX,SANDYBRIDGE,SO +VCMPNEQ_USPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 14] AVX,SANDYBRIDGE,SO +VCMPNEQ_USPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 14] AVX,SANDYBRIDGE,SY +VCMPNEQ_USPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 14] AVX,SANDYBRIDGE,SY +VCMPNLT_UQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 15] AVX,SANDYBRIDGE,SO +VCMPNLT_UQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 15] AVX,SANDYBRIDGE,SO +VCMPNLT_UQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 15] AVX,SANDYBRIDGE,SY +VCMPNLT_UQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 15] AVX,SANDYBRIDGE,SY +VCMPNLE_UQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 16] AVX,SANDYBRIDGE,SO +VCMPNLE_UQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 16] AVX,SANDYBRIDGE,SO +VCMPNLE_UQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 16] AVX,SANDYBRIDGE,SY +VCMPNLE_UQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 16] AVX,SANDYBRIDGE,SY +VCMPORD_SPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 17] AVX,SANDYBRIDGE,SO +VCMPORD_SPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 17] AVX,SANDYBRIDGE,SO +VCMPORD_SPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 17] AVX,SANDYBRIDGE,SY +VCMPORS_SPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 17] AVX,SANDYBRIDGE,SY +VCMPEQ_USPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 18] AVX,SANDYBRIDGE,SO +VCMPEQ_USPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 18] AVX,SANDYBRIDGE,SO +VCMPEQ_USPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 18] AVX,SANDYBRIDGE,SY +VCMPEQ_USPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 18] AVX,SANDYBRIDGE,SY +VCMPNGE_UQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 19] AVX,SANDYBRIDGE,SO +VCMPNGE_UQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 19] AVX,SANDYBRIDGE,SO +VCMPNGE_UQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 19] AVX,SANDYBRIDGE,SY +VCMPNGE_UQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 19] AVX,SANDYBRIDGE,SY +VCMPNGT_UQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1a] AVX,SANDYBRIDGE,SO +VCMPNGT_UQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1a] AVX,SANDYBRIDGE,SO +VCMPNGT_UQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1a] AVX,SANDYBRIDGE,SY +VCMPNGT_UQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1a] AVX,SANDYBRIDGE,SY +VCMPFALSE_OSPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1b] AVX,SANDYBRIDGE,SO +VCMPFALSE_OSPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1b] AVX,SANDYBRIDGE,SO +VCMPFALSE_OSPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1b] AVX,SANDYBRIDGE,SY +VCMPFALSE_OSPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1b] AVX,SANDYBRIDGE,SY +VCMPNEQ_OSPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OSPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1c] AVX,SANDYBRIDGE,SO +VCMPNEQ_OSPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1c] AVX,SANDYBRIDGE,SY +VCMPNEQ_OSPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1c] AVX,SANDYBRIDGE,SY +VCMPGE_OQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1d] AVX,SANDYBRIDGE,SO +VCMPGE_OQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1d] AVX,SANDYBRIDGE,SO +VCMPGE_OQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1d] AVX,SANDYBRIDGE,SY +VCMPGE_OQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1d] AVX,SANDYBRIDGE,SY +VCMPGT_OQPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1e] AVX,SANDYBRIDGE,SO +VCMPGT_OQPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1e] AVX,SANDYBRIDGE,SO +VCMPGT_OQPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1e] AVX,SANDYBRIDGE,SY +VCMPGT_OQPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1e] AVX,SANDYBRIDGE,SY +VCMPTRUE_USPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f c2 /r 1f] AVX,SANDYBRIDGE,SO +VCMPTRUE_USPS xmmreg,xmmrm [r+vm: vex.nds.128.0f c2 /r 1f] AVX,SANDYBRIDGE,SO +VCMPTRUE_USPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f c2 /r 1f] AVX,SANDYBRIDGE,SY +VCMPTRUE_USPS ymmreg,ymmrm [r+vm: vex.nds.256.0f c2 /r 1f] AVX,SANDYBRIDGE,SY +VCMPPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.0f c2 /r ib] AVX,SANDYBRIDGE,SO +VCMPPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.0f c2 /r ib] AVX,SANDYBRIDGE,SO +VCMPPS ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.0f c2 /r ib] AVX,SANDYBRIDGE,SY +VCMPPS ymmreg,ymmrm,imm [r+vmi: vex.nds.256.0f c2 /r ib] AVX,SANDYBRIDGE,SY +; Specific aliases first, then the generic version, to keep the disassembler happy... +VCMPEQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 00] AVX,SANDYBRIDGE,SQ +VCMPEQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 00] AVX,SANDYBRIDGE,SQ +VCMPLTSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 01] AVX,SANDYBRIDGE,SQ +VCMPLTSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 01] AVX,SANDYBRIDGE,SQ +VCMPLESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 02] AVX,SANDYBRIDGE,SQ +VCMPLESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 02] AVX,SANDYBRIDGE,SQ +VCMPUNORDSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 03] AVX,SANDYBRIDGE,SQ +VCMPUNORDSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 03] AVX,SANDYBRIDGE,SQ +VCMPNEQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 04] AVX,SANDYBRIDGE,SQ +VCMPNEQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 04] AVX,SANDYBRIDGE,SQ +VCMPNLTSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 05] AVX,SANDYBRIDGE,SQ +VCMPNLTSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 05] AVX,SANDYBRIDGE,SQ +VCMPNLESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 06] AVX,SANDYBRIDGE,SQ +VCMPNLESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 06] AVX,SANDYBRIDGE,SQ +VCMPORDSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 07] AVX,SANDYBRIDGE,SQ +VCMPORDSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 07] AVX,SANDYBRIDGE,SQ +VCMPEQ_UQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 08] AVX,SANDYBRIDGE,SQ +VCMPEQ_UQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 08] AVX,SANDYBRIDGE,SQ +VCMPNGESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 09] AVX,SANDYBRIDGE,SQ +VCMPNGESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 09] AVX,SANDYBRIDGE,SQ +VCMPNGTSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0a] AVX,SANDYBRIDGE,SQ +VCMPNGTSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0a] AVX,SANDYBRIDGE,SQ +VCMPFALSESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0b] AVX,SANDYBRIDGE,SQ +VCMPFALSESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0b] AVX,SANDYBRIDGE,SQ +VCMPNEQ_OQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0c] AVX,SANDYBRIDGE,SQ +VCMPNEQ_OQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0c] AVX,SANDYBRIDGE,SQ +VCMPGESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0d] AVX,SANDYBRIDGE,SQ +VCMPGESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0d] AVX,SANDYBRIDGE,SQ +VCMPGTSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0e] AVX,SANDYBRIDGE,SQ +VCMPGTSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0e] AVX,SANDYBRIDGE,SQ +VCMPTRUESD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 0f] AVX,SANDYBRIDGE,SQ +VCMPTRUESD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 0f] AVX,SANDYBRIDGE,SQ +VCMPEQ_OSSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 10] AVX,SANDYBRIDGE,SQ +VCMPEQ_OSSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 10] AVX,SANDYBRIDGE,SQ +VCMPLT_OQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 11] AVX,SANDYBRIDGE,SQ +VCMPLT_OQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 11] AVX,SANDYBRIDGE,SQ +VCMPLE_OQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 12] AVX,SANDYBRIDGE,SQ +VCMPLE_OQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 12] AVX,SANDYBRIDGE,SQ +VCMPUNORD_SSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 13] AVX,SANDYBRIDGE,SQ +VCMPUNORD_SSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 13] AVX,SANDYBRIDGE,SQ +VCMPNEQ_USSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 14] AVX,SANDYBRIDGE,SQ +VCMPNEQ_USSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 14] AVX,SANDYBRIDGE,SQ +VCMPNLT_UQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 15] AVX,SANDYBRIDGE,SQ +VCMPNLT_UQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 15] AVX,SANDYBRIDGE,SQ +VCMPNLE_UQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 16] AVX,SANDYBRIDGE,SQ +VCMPNLE_UQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 16] AVX,SANDYBRIDGE,SQ +VCMPORD_SSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 17] AVX,SANDYBRIDGE,SQ +VCMPORD_SSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 17] AVX,SANDYBRIDGE,SQ +VCMPEQ_USSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 18] AVX,SANDYBRIDGE,SQ +VCMPEQ_USSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 18] AVX,SANDYBRIDGE,SQ +VCMPNGE_UQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 19] AVX,SANDYBRIDGE,SQ +VCMPNGE_UQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 19] AVX,SANDYBRIDGE,SQ +VCMPNGT_UQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1a] AVX,SANDYBRIDGE,SQ +VCMPNGT_UQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1a] AVX,SANDYBRIDGE,SQ +VCMPFALSE_OSSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1b] AVX,SANDYBRIDGE,SQ +VCMPFALSE_OSSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1b] AVX,SANDYBRIDGE,SQ +VCMPNEQ_OSSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1c] AVX,SANDYBRIDGE,SQ +VCMPNEQ_OSSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1c] AVX,SANDYBRIDGE,SQ +VCMPGE_OQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1d] AVX,SANDYBRIDGE,SQ +VCMPGE_OQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1d] AVX,SANDYBRIDGE,SQ +VCMPGT_OQSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1e] AVX,SANDYBRIDGE,SQ +VCMPGT_OQSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1e] AVX,SANDYBRIDGE,SQ +VCMPTRUE_USSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f c2 /r 1f] AVX,SANDYBRIDGE,SQ +VCMPTRUE_USSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f c2 /r 1f] AVX,SANDYBRIDGE,SQ +VCMPSD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.f2.0f c2 /r ib] AVX,SANDYBRIDGE,SQ +VCMPSD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.f2.0f c2 /r ib] AVX,SANDYBRIDGE,SQ +; Specific aliases first, then the generic version, to keep the disassembler happy... +VCMPEQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 00] AVX,SANDYBRIDGE,SD +VCMPEQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 00] AVX,SANDYBRIDGE,SD +VCMPLTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 01] AVX,SANDYBRIDGE,SD +VCMPLTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 01] AVX,SANDYBRIDGE,SD +VCMPLESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 02] AVX,SANDYBRIDGE,SD +VCMPLESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 02] AVX,SANDYBRIDGE,SD +VCMPUNORDSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 03] AVX,SANDYBRIDGE,SD +VCMPUNORDSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 03] AVX,SANDYBRIDGE,SD +VCMPNEQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 04] AVX,SANDYBRIDGE,SD +VCMPNEQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 04] AVX,SANDYBRIDGE,SD +VCMPNLTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 05] AVX,SANDYBRIDGE,SD +VCMPNLTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 05] AVX,SANDYBRIDGE,SD +VCMPNLESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 06] AVX,SANDYBRIDGE,SD +VCMPNLESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 06] AVX,SANDYBRIDGE,SD +VCMPORDSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 07] AVX,SANDYBRIDGE,SD +VCMPORDSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 07] AVX,SANDYBRIDGE,SD +VCMPEQ_UQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 08] AVX,SANDYBRIDGE,SD +VCMPEQ_UQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 08] AVX,SANDYBRIDGE,SD +VCMPNGESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 09] AVX,SANDYBRIDGE,SD +VCMPNGESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 09] AVX,SANDYBRIDGE,SD +VCMPNGTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0a] AVX,SANDYBRIDGE,SD +VCMPNGTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0a] AVX,SANDYBRIDGE,SD +VCMPFALSESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0b] AVX,SANDYBRIDGE,SD +VCMPFALSESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0b] AVX,SANDYBRIDGE,SD +VCMPNEQ_OQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0c] AVX,SANDYBRIDGE,SD +VCMPNEQ_OQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0c] AVX,SANDYBRIDGE,SD +VCMPGESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0d] AVX,SANDYBRIDGE,SD +VCMPGESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0d] AVX,SANDYBRIDGE,SD +VCMPGTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0e] AVX,SANDYBRIDGE,SD +VCMPGTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0e] AVX,SANDYBRIDGE,SD +VCMPTRUESS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 0f] AVX,SANDYBRIDGE,SD +VCMPTRUESS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 0f] AVX,SANDYBRIDGE,SD +VCMPEQ_OSSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 10] AVX,SANDYBRIDGE,SD +VCMPEQ_OSSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 10] AVX,SANDYBRIDGE,SD +VCMPLT_OQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 11] AVX,SANDYBRIDGE,SD +VCMPLT_OQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 11] AVX,SANDYBRIDGE,SD +VCMPLE_OQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 12] AVX,SANDYBRIDGE,SD +VCMPLE_OQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 12] AVX,SANDYBRIDGE,SD +VCMPUNORD_SSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 13] AVX,SANDYBRIDGE,SD +VCMPUNORD_SSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 13] AVX,SANDYBRIDGE,SD +VCMPNEQ_USSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 14] AVX,SANDYBRIDGE,SD +VCMPNEQ_USSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 14] AVX,SANDYBRIDGE,SD +VCMPNLT_UQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 15] AVX,SANDYBRIDGE,SD +VCMPNLT_UQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 15] AVX,SANDYBRIDGE,SD +VCMPNLE_UQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 16] AVX,SANDYBRIDGE,SD +VCMPNLE_UQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 16] AVX,SANDYBRIDGE,SD +VCMPORD_SSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 17] AVX,SANDYBRIDGE,SD +VCMPORD_SSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 17] AVX,SANDYBRIDGE,SD +VCMPEQ_USSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 18] AVX,SANDYBRIDGE,SD +VCMPEQ_USSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 18] AVX,SANDYBRIDGE,SD +VCMPNGE_UQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 19] AVX,SANDYBRIDGE,SD +VCMPNGE_UQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 19] AVX,SANDYBRIDGE,SD +VCMPNGT_UQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1a] AVX,SANDYBRIDGE,SD +VCMPNGT_UQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1a] AVX,SANDYBRIDGE,SD +VCMPFALSE_OSSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1b] AVX,SANDYBRIDGE,SD +VCMPFALSE_OSSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1b] AVX,SANDYBRIDGE,SD +VCMPNEQ_OSSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1c] AVX,SANDYBRIDGE,SD +VCMPNEQ_OSSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1c] AVX,SANDYBRIDGE,SD +VCMPGE_OQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1d] AVX,SANDYBRIDGE,SD +VCMPGE_OQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1d] AVX,SANDYBRIDGE,SD +VCMPGT_OQSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1e] AVX,SANDYBRIDGE,SD +VCMPGT_OQSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1e] AVX,SANDYBRIDGE,SD +VCMPTRUE_USSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f c2 /r 1f] AVX,SANDYBRIDGE,SD +VCMPTRUE_USSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f c2 /r 1f] AVX,SANDYBRIDGE,SD +VCMPSS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.f3.0f c2 /r ib] AVX,SANDYBRIDGE,SD +VCMPSS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.f3.0f c2 /r ib] AVX,SANDYBRIDGE,SD +VCOMISD xmmreg,xmmrm [rm: vex.128.66.0f 2f /r] AVX,SANDYBRIDGE,SQ +VCOMISS xmmreg,xmmrm [rm: vex.128.0f 2f /r] AVX,SANDYBRIDGE,SD +VCVTDQ2PD xmmreg,xmmrm [rm: vex.128.f3.0f e6 /r] AVX,SANDYBRIDGE,SQ +VCVTDQ2PD ymmreg,xmmrm [rm: vex.256.f3.0f e6 /r] AVX,SANDYBRIDGE,SO +VCVTDQ2PS xmmreg,xmmrm [rm: vex.128.0f 5b /r] AVX,SANDYBRIDGE,SO +VCVTDQ2PS ymmreg,ymmrm [rm: vex.256.0f 5b /r] AVX,SANDYBRIDGE,SY +VCVTPD2DQ xmmreg,xmmreg [rm: vex.128.f2.0f e6 /r] AVX,SANDYBRIDGE +VCVTPD2DQ xmmreg,mem128 [rm: vex.128.f2.0f e6 /r] AVX,SANDYBRIDGE +VCVTPD2DQ xmmreg,ymmreg [rm: vex.256.f2.0f e6 /r] AVX,SANDYBRIDGE +VCVTPD2DQ xmmreg,mem256 [rm: vex.256.f2.0f e6 /r] AVX,SANDYBRIDGE +VCVTPD2PS xmmreg,xmmreg [rm: vex.128.66.0f 5a /r] AVX,SANDYBRIDGE +VCVTPD2PS xmmreg,mem128 [rm: vex.128.66.0f 5a /r] AVX,SANDYBRIDGE +VCVTPD2PS xmmreg,ymmreg [rm: vex.256.66.0f 5a /r] AVX,SANDYBRIDGE +VCVTPD2PS xmmreg,mem256 [rm: vex.256.66.0f 5a /r] AVX,SANDYBRIDGE +VCVTPS2DQ xmmreg,xmmrm [rm: vex.128.66.0f 5b /r] AVX,SANDYBRIDGE,SO +VCVTPS2DQ ymmreg,ymmrm [rm: vex.256.66.0f 5b /r] AVX,SANDYBRIDGE,SY +VCVTPS2PD xmmreg,xmmrm [rm: vex.128.0f 5a /r] AVX,SANDYBRIDGE,SQ +VCVTPS2PD ymmreg,xmmrm [rm: vex.256.0f 5a /r] AVX,SANDYBRIDGE,SO +VCVTSD2SI reg32,xmmrm [rm: vex.128.f2.0f.w0 2d /r] AVX,SANDYBRIDGE,SQ +VCVTSD2SI reg64,xmmrm [rm: vex.128.f2.0f.w1 2d /r] AVX,SANDYBRIDGE,SQ,LONG +VCVTSD2SS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 5a /r] AVX,SANDYBRIDGE,SQ +VCVTSD2SS xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 5a /r] AVX,SANDYBRIDGE,SQ +VCVTSI2SD xmmreg,xmmreg,rm32 [rvm: vex.nds.128.f2.0f.w0 2a /r] AVX,SANDYBRIDGE +VCVTSI2SD xmmreg,rm32 [r+vm: vex.nds.128.f2.0f.w0 2a /r] AVX,SANDYBRIDGE +VCVTSI2SD xmmreg,xmmreg,mem [rvm: vex.nds.128.f2.0f.w0 2a /r] AVX,SANDYBRIDGE,SD,AR2,ND +VCVTSI2SD xmmreg,mem [r+vm: vex.nds.128.f2.0f.w0 2a /r] AVX,SANDYBRIDGE,SD,AR2,ND +VCVTSI2SD xmmreg,xmmreg,rm64 [rvm: vex.nds.128.f2.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG +VCVTSI2SD xmmreg,rm64 [r+vm: vex.nds.128.f2.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG +VCVTSI2SS xmmreg,xmmreg,rm32 [rvm: vex.nds.128.f3.0f.w0 2a /r] AVX,SANDYBRIDGE +VCVTSI2SS xmmreg,rm32 [r+vm: vex.nds.128.f3.0f.w0 2a /r] AVX,SANDYBRIDGE +VCVTSI2SS xmmreg,xmmreg,mem [rvm: vex.nds.128.f3.0f.w0 2a /r] AVX,SANDYBRIDGE,SD,AR2,ND +VCVTSI2SS xmmreg,mem [r+vm: vex.nds.128.f3.0f.w0 2a /r] AVX,SANDYBRIDGE,SD,AR2,ND +VCVTSI2SS xmmreg,xmmreg,rm64 [rvm: vex.nds.128.f3.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG +VCVTSI2SS xmmreg,rm64 [r+vm: vex.nds.128.f3.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG +VCVTSS2SD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 5a /r] AVX,SANDYBRIDGE,SD +VCVTSS2SD xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 5a /r] AVX,SANDYBRIDGE,SD +VCVTSS2SI reg32,xmmrm [rm: vex.128.f3.0f.w0 2d /r] AVX,SANDYBRIDGE,SD +VCVTSS2SI reg64,xmmrm [rm: vex.128.f3.0f.w1 2d /r] AVX,SANDYBRIDGE,SD,LONG +VCVTTPD2DQ xmmreg,xmmreg [rm: vex.128.66.0f e6 /r] AVX,SANDYBRIDGE +VCVTTPD2DQ xmmreg,mem128 [rm: vex.128.66.0f e6 /r] AVX,SANDYBRIDGE +VCVTTPD2DQ xmmreg,ymmreg [rm: vex.256.66.0f e6 /r] AVX,SANDYBRIDGE +VCVTTPD2DQ xmmreg,mem256 [rm: vex.256.66.0f e6 /r] AVX,SANDYBRIDGE +VCVTTPS2DQ xmmreg,xmmrm [rm: vex.128.f3.0f 5b /r] AVX,SANDYBRIDGE,SO +VCVTTPS2DQ ymmreg,ymmrm [rm: vex.256.f3.0f 5b /r] AVX,SANDYBRIDGE,SY +VCVTTSD2SI reg32,xmmrm [rm: vex.128.f2.0f.w0 2c /r] AVX,SANDYBRIDGE,SQ +VCVTTSD2SI reg64,xmmrm [rm: vex.128.f2.0f.w1 2c /r] AVX,SANDYBRIDGE,SQ,LONG +VCVTTSS2SI reg32,xmmrm [rm: vex.128.f3.0f.w0 2c /r] AVX,SANDYBRIDGE,SD +VCVTTSS2SI reg64,xmmrm [rm: vex.128.f3.0f.w1 2c /r] AVX,SANDYBRIDGE,SD,LONG +VDIVPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 5e /r] AVX,SANDYBRIDGE,SO +VDIVPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 5e /r] AVX,SANDYBRIDGE,SO +VDIVPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 5e /r] AVX,SANDYBRIDGE,SY +VDIVPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 5e /r] AVX,SANDYBRIDGE,SY +VDIVPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 5e /r] AVX,SANDYBRIDGE,SO +VDIVPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 5e /r] AVX,SANDYBRIDGE,SO +VDIVPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 5e /r] AVX,SANDYBRIDGE,SY +VDIVPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 5e /r] AVX,SANDYBRIDGE,SY +VDIVSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 5e /r] AVX,SANDYBRIDGE,SQ +VDIVSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 5e /r] AVX,SANDYBRIDGE,SQ +VDIVSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 5e /r] AVX,SANDYBRIDGE,SD +VDIVSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 5e /r] AVX,SANDYBRIDGE,SD +VDPPD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 41 /r ib] AVX,SANDYBRIDGE,SO +VDPPD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 41 /r ib] AVX,SANDYBRIDGE,SO +VDPPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 40 /r ib] AVX,SANDYBRIDGE,SO +VDPPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 40 /r ib] AVX,SANDYBRIDGE,SO +VDPPS ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 40 /r ib] AVX,SANDYBRIDGE,SY +VDPPS ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f3a 40 /r ib] AVX,SANDYBRIDGE,SY +VEXTRACTF128 xmmrm,xmmreg,imm [mri: vex.256.66.0f3a 19 /r ib] AVX,SANDYBRIDGE,SO +VEXTRACTPS rm32,xmmreg,imm [mri: vex.128.66.0f3a 17 /r ib] AVX,SANDYBRIDGE,SD +VHADDPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 7c /r] AVX,SANDYBRIDGE,SO +VHADDPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 7c /r] AVX,SANDYBRIDGE,SO +VHADDPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 7c /r] AVX,SANDYBRIDGE,SY +VHADDPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 7c /r] AVX,SANDYBRIDGE,SY +VHADDPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 7c /r] AVX,SANDYBRIDGE,SO +VHADDPS xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 7c /r] AVX,SANDYBRIDGE,SO +VHADDPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.f2.0f 7c /r] AVX,SANDYBRIDGE,SY +VHADDPS ymmreg,ymmrm [r+vm: vex.nds.256.f2.0f 7c /r] AVX,SANDYBRIDGE,SY +VHSUBPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 7d /r] AVX,SANDYBRIDGE,SO +VHSUBPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 7d /r] AVX,SANDYBRIDGE,SO +VHSUBPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 7d /r] AVX,SANDYBRIDGE,SY +VHSUBPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 7d /r] AVX,SANDYBRIDGE,SY +VHSUBPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 7d /r] AVX,SANDYBRIDGE,SO +VHSUBPS xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 7d /r] AVX,SANDYBRIDGE,SO +VHSUBPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.f2.0f 7d /r] AVX,SANDYBRIDGE,SY +VHSUBPS ymmreg,ymmrm [r+vm: vex.nds.256.f2.0f 7d /r] AVX,SANDYBRIDGE,SY +VINSERTF128 ymmreg,ymmreg,xmmrm,imm [rvmi: vex.nds.256.66.0f3a 18 /r ib] AVX,SANDYBRIDGE,SO +VINSERTPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 21 /r ib] AVX,SANDYBRIDGE,SD +VINSERTPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 21 /r ib] AVX,SANDYBRIDGE,SD +VLDDQU xmmreg,mem [rm: vex.128.f2.0f f0 /r] AVX,SANDYBRIDGE,SO +VLDQQU ymmreg,mem [rm: vex.256.f2.0f f0 /r] AVX,SANDYBRIDGE,SY +VLDDQU ymmreg,mem [rm: vex.256.f2.0f f0 /r] AVX,SANDYBRIDGE,SY +VLDMXCSR mem32 [m: vex.128.0f ae /2] AVX,SANDYBRIDGE,SD +VMASKMOVDQU xmmreg,xmmreg [rm: vex.128.66.0f f7 /r] AVX,SANDYBRIDGE +VMASKMOVPS xmmreg,xmmreg,mem [rvm: vex.nds.128.66.0f38 2c /r] AVX,SANDYBRIDGE,SO +VMASKMOVPS ymmreg,ymmreg,mem [rvm: vex.nds.256.66.0f38 2c /r] AVX,SANDYBRIDGE,SY +VMASKMOVPS mem,xmmreg,xmmreg [mvr: vex.nds.128.66.0f38 2e /r] AVX,SANDYBRIDGE,SO +VMASKMOVPS mem,xmmreg,xmmreg [mvr: vex.nds.256.66.0f38 2e /r] AVX,SANDYBRIDGE,SY +VMASKMOVPD xmmreg,xmmreg,mem [rvm: vex.nds.128.66.0f38 2d /r] AVX,SANDYBRIDGE,SO +VMASKMOVPD ymmreg,ymmreg,mem [rvm: vex.nds.256.66.0f38 2d /r] AVX,SANDYBRIDGE,SY +VMASKMOVPD mem,xmmreg,xmmreg [mvr: vex.nds.128.66.0f38 2f /r] AVX,SANDYBRIDGE,SO +VMASKMOVPD mem,ymmreg,ymmreg [mvr: vex.nds.256.66.0f38 2f /r] AVX,SANDYBRIDGE,SY +VMAXPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 5f /r] AVX,SANDYBRIDGE,SO +VMAXPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 5f /r] AVX,SANDYBRIDGE,SO +VMAXPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 5f /r] AVX,SANDYBRIDGE,SY +VMAXPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 5f /r] AVX,SANDYBRIDGE,SY +VMAXPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 5f /r] AVX,SANDYBRIDGE,SO +VMAXPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 5f /r] AVX,SANDYBRIDGE,SO +VMAXPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 5f /r] AVX,SANDYBRIDGE,SY +VMAXPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 5f /r] AVX,SANDYBRIDGE,SY +VMAXSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 5f /r] AVX,SANDYBRIDGE,SQ +VMAXSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 5f /r] AVX,SANDYBRIDGE,SQ +VMAXSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 5f /r] AVX,SANDYBRIDGE,SD +VMAXSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 5f /r] AVX,SANDYBRIDGE,SD +VMINPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 5d /r] AVX,SANDYBRIDGE,SO +VMINPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 5d /r] AVX,SANDYBRIDGE,SO +VMINPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 5d /r] AVX,SANDYBRIDGE,SY +VMINPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 5d /r] AVX,SANDYBRIDGE,SY +VMINPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 5d /r] AVX,SANDYBRIDGE,SO +VMINPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 5d /r] AVX,SANDYBRIDGE,SO +VMINPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 5d /r] AVX,SANDYBRIDGE,SY +VMINPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 5d /r] AVX,SANDYBRIDGE,SY +VMINSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 5d /r] AVX,SANDYBRIDGE,SQ +VMINSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 5d /r] AVX,SANDYBRIDGE,SQ +VMINSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 5d /r] AVX,SANDYBRIDGE,SD +VMINSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 5d /r] AVX,SANDYBRIDGE,SD +VMOVAPD xmmreg,xmmrm [rm: vex.128.66.0f 28 /r] AVX,SANDYBRIDGE,SO +VMOVAPD xmmrm,xmmreg [mr: vex.128.66.0f 29 /r] AVX,SANDYBRIDGE,SO +VMOVAPD ymmreg,ymmrm [rm: vex.256.66.0f 28 /r] AVX,SANDYBRIDGE,SY +VMOVAPD ymmrm,ymmreg [mr: vex.256.66.0f 29 /r] AVX,SANDYBRIDGE,SY +VMOVAPS xmmreg,xmmrm [rm: vex.128.0f 28 /r] AVX,SANDYBRIDGE,SO +VMOVAPS xmmrm,xmmreg [mr: vex.128.0f 29 /r] AVX,SANDYBRIDGE,SO +VMOVAPS ymmreg,ymmrm [rm: vex.256.0f 28 /r] AVX,SANDYBRIDGE,SY +VMOVAPS ymmrm,ymmreg [mr: vex.256.0f 29 /r] AVX,SANDYBRIDGE,SY +VMOVQ xmmreg,xmmrm [rm: vex.128.f3.0f 7e /r] AVX,SANDYBRIDGE,SQ +VMOVQ xmmrm,xmmreg [mr: vex.128.66.0f d6 /r] AVX,SANDYBRIDGE,SQ +VMOVD xmmreg,rm32 [rm: vex.128.66.0f.w0 6e /r] AVX,SANDYBRIDGE,SD +VMOVQ xmmreg,rm64 [rm: vex.128.66.0f.w1 6e /r] AVX,SANDYBRIDGE,SQ,LONG +VMOVD rm32,xmmreg [mr: vex.128.66.0f.w0 7e /r] AVX,SANDYBRIDGE,SD +VMOVQ rm64,xmmreg [mr: vex.128.66.0f.w1 7e /r] AVX,SANDYBRIDGE,SQ,LONG +VMOVDDUP xmmreg,xmmrm [rm: vex.128.f2.0f 12 /r] AVX,SANDYBRIDGE,SQ +VMOVDDUP ymmreg,ymmrm [rm: vex.256.f2.0f 12 /r] AVX,SANDYBRIDGE,SY +VMOVDQA xmmreg,xmmrm [rm: vex.128.66.0f 6f /r] AVX,SANDYBRIDGE,SO +VMOVDQA xmmrm,xmmreg [mr: vex.128.66.0f 7f /r] AVX,SANDYBRIDGE,SO +; These are officially documented as VMOVDQA, but VMOVQQA seems more logical to me... +VMOVQQA ymmreg,ymmrm [rm: vex.256.66.0f 6f /r] AVX,SANDYBRIDGE,SY +VMOVQQA ymmrm,ymmreg [mr: vex.256.66.0f 7f /r] AVX,SANDYBRIDGE,SY +VMOVDQA ymmreg,ymmrm [rm: vex.256.66.0f 6f /r] AVX,SANDYBRIDGE,SY +VMOVDQA ymmrm,ymmreg [mr: vex.256.66.0f 7f /r] AVX,SANDYBRIDGE,SY +VMOVDQU xmmreg,xmmrm [rm: vex.128.f3.0f 6f /r] AVX,SANDYBRIDGE,SO +VMOVDQU xmmrm,xmmreg [mr: vex.128.f3.0f 7f /r] AVX,SANDYBRIDGE,SO +; These are officially documented as VMOVDQU, but VMOVQQU seems more logical to me... +VMOVQQU ymmreg,ymmrm [rm: vex.256.f3.0f 6f /r] AVX,SANDYBRIDGE,SY +VMOVQQU ymmrm,ymmreg [mr: vex.256.f3.0f 7f /r] AVX,SANDYBRIDGE,SY +VMOVDQU ymmreg,ymmrm [rm: vex.256.f3.0f 6f /r] AVX,SANDYBRIDGE,SY +VMOVDQU ymmrm,ymmreg [mr: vex.256.f3.0f 7f /r] AVX,SANDYBRIDGE,SY +VMOVHLPS xmmreg,xmmreg,xmmreg [rvm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE +VMOVHLPS xmmreg,xmmreg [r+vm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE +VMOVHPD xmmreg,xmmreg,mem [rvm: vex.nds.128.66.0f 16 /r] AVX,SANDYBRIDGE,SQ +VMOVHPD xmmreg,mem [r+vm: vex.nds.128.66.0f 16 /r] AVX,SANDYBRIDGE,SQ +VMOVHPD mem,xmmreg [mr: vex.128.66.0f 17 /r] AVX,SANDYBRIDGE,SQ +VMOVHPS xmmreg,xmmreg,mem [rvm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE,SQ +VMOVHPS xmmreg,mem [r+vm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE,SQ +VMOVHPS mem,xmmreg [mr: vex.128.0f 17 /r] AVX,SANDYBRIDGE,SQ +VMOVLHPS xmmreg,xmmreg,xmmreg [rvm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE +VMOVLHPS xmmreg,xmmreg [r+vm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE +VMOVLPD xmmreg,xmmreg,mem [rvm: vex.nds.128.66.0f 12 /r] AVX,SANDYBRIDGE,SQ +VMOVLPD xmmreg,mem [r+vm: vex.nds.128.66.0f 12 /r] AVX,SANDYBRIDGE,SQ +VMOVLPD mem,xmmreg [mr: vex.128.66.0f 13 /r] AVX,SANDYBRIDGE,SQ +VMOVLPS xmmreg,xmmreg,mem [rvm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE,SQ +VMOVLPS xmmreg,mem [r+vm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE,SQ +VMOVLPS mem,xmmreg [mr: vex.128.0f 13 /r] AVX,SANDYBRIDGE,SQ +VMOVMSKPD reg64,xmmreg [rm: vex.128.66.0f 50 /r] AVX,SANDYBRIDGE,LONG +VMOVMSKPD reg32,xmmreg [rm: vex.128.66.0f 50 /r] AVX,SANDYBRIDGE +VMOVMSKPD reg64,ymmreg [rm: vex.256.66.0f 50 /r] AVX,SANDYBRIDGE,LONG +VMOVMSKPD reg32,ymmreg [rm: vex.256.66.0f 50 /r] AVX,SANDYBRIDGE +VMOVMSKPS reg64,xmmreg [rm: vex.128.0f 50 /r] AVX,SANDYBRIDGE,LONG +VMOVMSKPS reg32,xmmreg [rm: vex.128.0f 50 /r] AVX,SANDYBRIDGE +VMOVMSKPS reg64,ymmreg [rm: vex.256.0f 50 /r] AVX,SANDYBRIDGE,LONG +VMOVMSKPS reg32,ymmreg [rm: vex.256.0f 50 /r] AVX,SANDYBRIDGE +VMOVNTDQ mem,xmmreg [mr: vex.128.66.0f e7 /r] AVX,SANDYBRIDGE,SO +; Officially VMOVNTDQ, but VMOVNTQQ seems more logical to me... +VMOVNTQQ mem,ymmreg [mr: vex.256.66.0f e7 /r] AVX,SANDYBRIDGE,SY +VMOVNTDQ mem,ymmreg [mr: vex.256.66.0f e7 /r] AVX,SANDYBRIDGE,SY +VMOVNTDQA xmmreg,mem [rm: vex.128.66.0f38 2a /r] AVX,SANDYBRIDGE,SO +VMOVNTPD mem,xmmreg [mr: vex.128.66.0f 2b /r] AVX,SANDYBRIDGE,SO +VMOVNTPD mem,ymmreg [mr: vex.256.66.0f 2b /r] AVX,SANDYBRIDGE,SY +VMOVNTPS mem,xmmreg [mr: vex.128.0f 2b /r] AVX,SANDYBRIDGE,SO +VMOVNTPS mem,ymmreg [mr: vex.256.0f 2b /r] AVX,SANDYBRIDGE,SO +VMOVSD xmmreg,xmmreg,xmmreg [rvm: vex.nds.128.f2.0f 10 /r] AVX,SANDYBRIDGE +VMOVSD xmmreg,xmmreg [r+vm: vex.nds.128.f2.0f 10 /r] AVX,SANDYBRIDGE +VMOVSD xmmreg,mem [rm: vex.128.f2.0f 10 /r] AVX,SANDYBRIDGE,SQ +VMOVSD xmmreg,xmmreg,xmmreg [mvr: vex.nds.128.f2.0f 11 /r] AVX,SANDYBRIDGE +VMOVSD xmmreg,xmmreg [m+vr: vex.nds.128.f2.0f 11 /r] AVX,SANDYBRIDGE +VMOVSD mem,xmmreg [mr: vex.128.f2.0f 11 /r] AVX,SANDYBRIDGE,SQ +VMOVSHDUP xmmreg,xmmrm [rm: vex.128.f3.0f 16 /r] AVX,SANDYBRIDGE,SO +VMOVSHDUP ymmreg,ymmrm [rm: vex.256.f3.0f 16 /r] AVX,SANDYBRIDGE,SY +VMOVSLDUP xmmreg,xmmrm [rm: vex.128.f3.0f 12 /r] AVX,SANDYBRIDGE,SO +VMOVSLDUP ymmreg,ymmrm [rm: vex.256.f3.0f 12 /r] AVX,SANDYBRIDGE,SY +VMOVSS xmmreg,xmmreg,xmmreg [rvm: vex.nds.128.f3.0f 10 /r] AVX,SANDYBRIDGE +VMOVSS xmmreg,xmmreg [r+vm: vex.nds.128.f3.0f 10 /r] AVX,SANDYBRIDGE +VMOVSS xmmreg,mem [rm: vex.128.f3.0f 10 /r] AVX,SANDYBRIDGE,SQ +VMOVSS xmmreg,xmmreg,xmmreg [mvr: vex.nds.128.f3.0f 11 /r] AVX,SANDYBRIDGE +VMOVSS xmmreg,xmmreg [m+vr: vex.nds.128.f3.0f 11 /r] AVX,SANDYBRIDGE +VMOVSS mem,xmmreg [mr: vex.128.f3.0f 11 /r] AVX,SANDYBRIDGE,SQ +VMOVUPD xmmreg,xmmrm [rm: vex.128.66.0f 10 /r] AVX,SANDYBRIDGE,SO +VMOVUPD xmmrm,xmmreg [mr: vex.128.66.0f 11 /r] AVX,SANDYBRIDGE,SO +VMOVUPD ymmreg,ymmrm [rm: vex.256.66.0f 10 /r] AVX,SANDYBRIDGE,SY +VMOVUPD ymmrm,ymmreg [mr: vex.256.66.0f 11 /r] AVX,SANDYBRIDGE,SY +VMOVUPS xmmreg,xmmrm [rm: vex.128.0f 10 /r] AVX,SANDYBRIDGE,SO +VMOVUPS xmmrm,xmmreg [mr: vex.128.0f 11 /r] AVX,SANDYBRIDGE,SO +VMOVUPS ymmreg,ymmrm [rm: vex.256.0f 10 /r] AVX,SANDYBRIDGE,SY +VMOVUPS ymmrm,ymmreg [mr: vex.256.0f 11 /r] AVX,SANDYBRIDGE,SY +VMPSADBW xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 42 /r ib] AVX,SANDYBRIDGE,SO +VMPSADBW xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 42 /r ib] AVX,SANDYBRIDGE,SO +VMULPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 59 /r] AVX,SANDYBRIDGE,SO +VMULPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 59 /r] AVX,SANDYBRIDGE,SO +VMULPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 59 /r] AVX,SANDYBRIDGE,SY +VMULPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 59 /r] AVX,SANDYBRIDGE,SY +VMULPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 59 /r] AVX,SANDYBRIDGE,SO +VMULPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 59 /r] AVX,SANDYBRIDGE,SO +VMULPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 59 /r] AVX,SANDYBRIDGE,SY +VMULPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 59 /r] AVX,SANDYBRIDGE,SY +VMULSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 59 /r] AVX,SANDYBRIDGE,SQ +VMULSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 59 /r] AVX,SANDYBRIDGE,SQ +VMULSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 59 /r] AVX,SANDYBRIDGE,SD +VMULSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 59 /r] AVX,SANDYBRIDGE,SD +VORPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 56 /r] AVX,SANDYBRIDGE,SO +VORPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 56 /r] AVX,SANDYBRIDGE,SO +VORPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 56 /r] AVX,SANDYBRIDGE,SY +VORPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 56 /r] AVX,SANDYBRIDGE,SY +VORPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 56 /r] AVX,SANDYBRIDGE,SO +VORPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 56 /r] AVX,SANDYBRIDGE,SO +VORPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 56 /r] AVX,SANDYBRIDGE,SY +VORPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 56 /r] AVX,SANDYBRIDGE,SY +VPABSB xmmreg,xmmrm [rm: vex.128.66.0f38 1c /r] AVX,SANDYBRIDGE,SO +VPABSW xmmreg,xmmrm [rm: vex.128.66.0f38 1d /r] AVX,SANDYBRIDGE,SO +VPABSD xmmreg,xmmrm [rm: vex.128.66.0f38 1e /r] AVX,SANDYBRIDGE,SO +VPACKSSWB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 63 /r] AVX,SANDYBRIDGE,SO +VPACKSSWB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 63 /r] AVX,SANDYBRIDGE,SO +VPACKSSDW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 6b /r] AVX,SANDYBRIDGE,SO +VPACKSSDW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 6b /r] AVX,SANDYBRIDGE,SO +VPACKUSWB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 67 /r] AVX,SANDYBRIDGE,SO +VPACKUSWB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 67 /r] AVX,SANDYBRIDGE,SO +VPACKUSDW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 2b /r] AVX,SANDYBRIDGE,SO +VPACKUSDW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 2b /r] AVX,SANDYBRIDGE,SO +VPADDB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f fc /r] AVX,SANDYBRIDGE,SO +VPADDB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f fc /r] AVX,SANDYBRIDGE,SO +VPADDW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f fd /r] AVX,SANDYBRIDGE,SO +VPADDW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f fd /r] AVX,SANDYBRIDGE,SO +VPADDD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f fe /r] AVX,SANDYBRIDGE,SO +VPADDD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f fe /r] AVX,SANDYBRIDGE,SO +VPADDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d4 /r] AVX,SANDYBRIDGE,SO +VPADDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d4 /r] AVX,SANDYBRIDGE,SO +VPADDSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f ec /r] AVX,SANDYBRIDGE,SO +VPADDSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f ec /r] AVX,SANDYBRIDGE,SO +VPADDSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f ed /r] AVX,SANDYBRIDGE,SO +VPADDSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f ed /r] AVX,SANDYBRIDGE,SO +VPADDUSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f dc /r] AVX,SANDYBRIDGE,SO +VPADDUSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f dc /r] AVX,SANDYBRIDGE,SO +VPADDUSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f dd /r] AVX,SANDYBRIDGE,SO +VPADDUSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f dd /r] AVX,SANDYBRIDGE,SO +VPALIGNR xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0f /r ib] AVX,SANDYBRIDGE,SO +VPALIGNR xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0f /r ib] AVX,SANDYBRIDGE,SO +VPAND xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f db /r] AVX,SANDYBRIDGE,SO +VPAND xmmreg,xmmrm [r+vm: vex.nds.128.66.0f db /r] AVX,SANDYBRIDGE,SO +VPANDN xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f df /r] AVX,SANDYBRIDGE,SO +VPANDN xmmreg,xmmrm [r+vm: vex.nds.128.66.0f df /r] AVX,SANDYBRIDGE,SO +VPAVGB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e0 /r] AVX,SANDYBRIDGE,SO +VPAVGB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e0 /r] AVX,SANDYBRIDGE,SO +VPAVGW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e3 /r] AVX,SANDYBRIDGE,SO +VPAVGW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e3 /r] AVX,SANDYBRIDGE,SO +VPBLENDVB xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a 4c /r /is4] AVX,SANDYBRIDGE,SO +VPBLENDVB xmmreg,xmmrm,xmmreg [r+vms: vex.nds.128.66.0f3a 4c /r /is4] AVX,SANDYBRIDGE,SO +VPBLENDW xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0e /r ib] AVX,SANDYBRIDGE,SO +VPBLENDW xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0e /r ib] AVX,SANDYBRIDGE,SO +VPCMPESTRI xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 61 /r ib] AVX,SANDYBRIDGE,SO +VPCMPESTRM xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 60 /r ib] AVX,SANDYBRIDGE,SO +VPCMPISTRI xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 63 /r ib] AVX,SANDYBRIDGE,SO +VPCMPISTRM xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 62 /r ib] AVX,SANDYBRIDGE,SO +VPCMPEQB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 74 /r] AVX,SANDYBRIDGE,SO +VPCMPEQB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 74 /r] AVX,SANDYBRIDGE,SO +VPCMPEQW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 75 /r] AVX,SANDYBRIDGE,SO +VPCMPEQW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 75 /r] AVX,SANDYBRIDGE,SO +VPCMPEQD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 76 /r] AVX,SANDYBRIDGE,SO +VPCMPEQD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 76 /r] AVX,SANDYBRIDGE,SO +VPCMPEQQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 29 /r] AVX,SANDYBRIDGE,SO +VPCMPEQQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 29 /r] AVX,SANDYBRIDGE,SO +VPCMPGTB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 64 /r] AVX,SANDYBRIDGE,SO +VPCMPGTB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 64 /r] AVX,SANDYBRIDGE,SO +VPCMPGTW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 65 /r] AVX,SANDYBRIDGE,SO +VPCMPGTW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 65 /r] AVX,SANDYBRIDGE,SO +VPCMPGTD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 66 /r] AVX,SANDYBRIDGE,SO +VPCMPGTD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 66 /r] AVX,SANDYBRIDGE,SO +VPCMPGTQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 37 /r] AVX,SANDYBRIDGE,SO +VPCMPGTQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 37 /r] AVX,SANDYBRIDGE,SO +VPERMILPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 0d /r] AVX,SANDYBRIDGE,SO +VPERMILPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f38 0d /r] AVX,SANDYBRIDGE,SY +VPERMILPD xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 05 /r ib] AVX,SANDYBRIDGE,SO +VPERMILPD ymmreg,ymmrm,imm [rmi: vex.256.66.0f3a 05 /r ib] AVX,SANDYBRIDGE,SY +VPERMILTD2PD xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 49 /r /is4=0] AVX,SANDYBRIDGE,SO +VPERMILTD2PD xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 49 /r /is4=0] AVX,SANDYBRIDGE,SO +VPERMILTD2PD ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 49 /r /is4=0] AVX,SANDYBRIDGE,SY +VPERMILTD2PD ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 49 /r /is4=0] AVX,SANDYBRIDGE,SY +VPERMILMO2PD xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 49 /r /is4=2] AVX,SANDYBRIDGE,SO +VPERMILMO2PD xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 49 /r /is4=2] AVX,SANDYBRIDGE,SO +VPERMILMO2PD ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 49 /r /is4=2] AVX,SANDYBRIDGE,SY +VPERMILMO2PD ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 49 /r /is4=2] AVX,SANDYBRIDGE,SY +VPERMILMZ2PD xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 49 /r /is4=3] AVX,SANDYBRIDGE,SO +VPERMILMZ2PD xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 49 /r /is4=3] AVX,SANDYBRIDGE,SO +VPERMILMZ2PD ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 49 /r /is4=3] AVX,SANDYBRIDGE,SY +VPERMILMZ2PD ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 49 /r /is4=3] AVX,SANDYBRIDGE,SY +VPERMIL2PD xmmreg,xmmreg,xmmrm,xmmreg,imm [rvmsi: vex.nds.128.66.0f3a.w0 49 /r /is4] AVX,SANDYBRIDGE,SO +VPERMIL2PD xmmreg,xmmreg,xmmreg,xmmrm,imm [rvsmi: vex.nds.128.66.0f3a.w1 49 /r /is4] AVX,SANDYBRIDGE,SO +VPERMIL2PD ymmreg,ymmreg,ymmrm,ymmreg,imm [rvmsi: vex.nds.256.66.0f3a.w0 49 /r /is4] AVX,SANDYBRIDGE,SY +VPERMIL2PD ymmreg,ymmreg,ymmreg,ymmrm,imm [rvsmi: vex.nds.256.66.0f3a.w1 49 /r /is4] AVX,SANDYBRIDGE,SY +VPERMILPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 0c /r] AVX,SANDYBRIDGE,SO +VPERMILPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f38 0c /r] AVX,SANDYBRIDGE,SY +VPERMILPS xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 04 /r ib] AVX,SANDYBRIDGE,SO +VPERMILPS ymmreg,ymmrm,imm [rmi: vex.256.66.0f3a 04 /r ib] AVX,SANDYBRIDGE,SY +VPERMILTD2PS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 48 /r /is4=0] AVX,SANDYBRIDGE,SO +VPERMILTD2PS xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 48 /r /is4=0] AVX,SANDYBRIDGE,SO +VPERMILTD2PS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 48 /r /is4=0] AVX,SANDYBRIDGE,SY +VPERMILTD2PS ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 48 /r /is4=0] AVX,SANDYBRIDGE,SY +VPERMILMO2PS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 48 /r /is4=2] AVX,SANDYBRIDGE,SO +VPERMILMO2PS xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 48 /r /is4=2] AVX,SANDYBRIDGE,SO +VPERMILMO2PS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 48 /r /is4=2] AVX,SANDYBRIDGE,SY +VPERMILMO2PS ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 48 /r /is4=2] AVX,SANDYBRIDGE,SY +VPERMILMZ2PS xmmreg,xmmreg,xmmrm,xmmreg [rvms: vex.nds.128.66.0f3a.w0 48 /r /is4=3] AVX,SANDYBRIDGE,SO +VPERMILMZ2PS xmmreg,xmmreg,xmmreg,xmmrm [rvsm: vex.nds.128.66.0f3a.w1 48 /r /is4=3] AVX,SANDYBRIDGE,SO +VPERMILMZ2PS ymmreg,ymmreg,ymmrm,ymmreg [rvms: vex.nds.256.66.0f3a.w0 48 /r /is4=3] AVX,SANDYBRIDGE,SY +VPERMILMZ2PS ymmreg,ymmreg,ymmreg,ymmrm [rvsm: vex.nds.256.66.0f3a.w1 48 /r /is4=3] AVX,SANDYBRIDGE,SY +VPERMIL2PS xmmreg,xmmreg,xmmrm,xmmreg,imm [rvmsi: vex.nds.128.66.0f3a.w0 48 /r /is4] AVX,SANDYBRIDGE,SO +VPERMIL2PS xmmreg,xmmreg,xmmreg,xmmrm,imm [rvsmi: vex.nds.128.66.0f3a.w1 48 /r /is4] AVX,SANDYBRIDGE,SO +VPERMIL2PS ymmreg,ymmreg,ymmrm,ymmreg,imm [rvmsi: vex.nds.256.66.0f3a.w0 48 /r /is4] AVX,SANDYBRIDGE,SY +VPERMIL2PS ymmreg,ymmreg,ymmreg,ymmrm,imm [rvsmi: vex.nds.256.66.0f3a.w1 48 /r /is4] AVX,SANDYBRIDGE,SY +VPERM2F128 ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f3a 06 /r ib] AVX,SANDYBRIDGE,SY +VPEXTRB reg64,xmmreg,imm [mri: vex.128.66.0f3a.w0 14 /r ib] AVX,SANDYBRIDGE,LONG +VPEXTRB reg32,xmmreg,imm [mri: vex.128.66.0f3a.w0 14 /r ib] AVX,SANDYBRIDGE +VPEXTRB mem,xmmreg,imm [mri: vex.128.66.0f3a.w0 14 /r ib] AVX,SANDYBRIDGE,SB +VPEXTRW reg64,xmmreg,imm [mri: vex.128.66.0f.w0 c5 /r ib] AVX,SANDYBRIDGE,LONG +VPEXTRW reg32,xmmreg,imm [mri: vex.128.66.0f.w0 c5 /r ib] AVX,SANDYBRIDGE +VPEXTRW mem,xmmreg,imm [mri: vex.128.66.0f.w0 c5 /r ib] AVX,SANDYBRIDGE,SW +VPEXTRW reg64,xmmreg,imm [mri: vex.128.66.0f3a.w0 15 /r ib] AVX,SANDYBRIDGE,LONG +VPEXTRW reg32,xmmreg,imm [mri: vex.128.66.0f3a.w0 15 /r ib] AVX,SANDYBRIDGE +VPEXTRW mem,xmmreg,imm [mri: vex.128.66.0f3a.w0 15 /r ib] AVX,SANDYBRIDGE,SW +VPEXTRD reg64,xmmreg,imm [mri: vex.128.66.0f3a.w0 16 /r ib] AVX,SANDYBRIDGE,LONG +VPEXTRD rm32,xmmreg,imm [mri: vex.128.66.0f3a.w0 16 /r ib] AVX,SANDYBRIDGE,SD +VPEXTRQ rm64,xmmreg,imm [mri: vex.128.66.0f3a.w1 16 /r ib] AVX,SANDYBRIDGE,SQ,LONG +VPHADDW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 01 /r] AVX,SANDYBRIDGE,SO +VPHADDW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 01 /r] AVX,SANDYBRIDGE,SO +VPHADDD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 02 /r] AVX,SANDYBRIDGE,SO +VPHADDD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 02 /r] AVX,SANDYBRIDGE,SO +VPHADDSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 03 /r] AVX,SANDYBRIDGE,SO +VPHADDSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 03 /r] AVX,SANDYBRIDGE,SO +VPHMINPOSUW xmmreg,xmmrm [rm: vex.128.66.0f38 41 /r] AVX,SANDYBRIDGE,SO +VPHSUBW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 05 /r] AVX,SANDYBRIDGE,SO +VPHSUBW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 05 /r] AVX,SANDYBRIDGE,SO +VPHSUBD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 06 /r] AVX,SANDYBRIDGE,SO +VPHSUBD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 06 /r] AVX,SANDYBRIDGE,SO +VPHSUBSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 07 /r] AVX,SANDYBRIDGE,SO +VPHSUBSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 07 /r] AVX,SANDYBRIDGE,SO +VPINSRB xmmreg,xmmreg,reg32,imm [rvmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE +VPINSRB xmmreg,reg32,imm [r+vmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE +VPINSRB xmmreg,xmmreg,mem,imm [rvmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE,SB +VPINSRB xmmreg,reg32,mem,imm [r+vmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE,SB +VPINSRW xmmreg,xmmreg,reg32,imm [rvmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE +VPINSRW xmmreg,reg32,imm [r+vmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE +VPINSRW xmmreg,xmmreg,mem,imm [rvmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE,SW +VPINSRW xmmreg,reg32,mem,imm [r+vmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE,SW +VPINSRD xmmreg,xmmreg,rm32,imm [rvmi: vex.nds.128.66.0f3a.w0 22 /r ib] AVX,SANDYBRIDGE,SD +VPINSRD xmmreg,rm32,imm [r+vmi: vex.nds.128.66.0f3a.w0 22 /r ib] AVX,SANDYBRIDGE,SD +VPINSRQ xmmreg,xmmreg,rm64,imm [rvmi: vex.nds.128.66.0f3a.w1 22 /r ib] AVX,SANDYBRIDGE,SQ,LONG +VPINSRQ xmmreg,rm64,imm [r+vmi: vex.nds.128.66.0f3a.w1 22 /r ib] AVX,SANDYBRIDGE,SD,LONG +VPMADDWD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f5 /r] AVX,SANDYBRIDGE,SO +VPMADDWD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f5 /r] AVX,SANDYBRIDGE,SO +VPMADDUBSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 04 /r] AVX,SANDYBRIDGE,SO +VPMADDUBSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 04 /r] AVX,SANDYBRIDGE,SO +VPMAXSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3c /r] AVX,SANDYBRIDGE,SO +VPMAXSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3c /r] AVX,SANDYBRIDGE,SO +VPMAXSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f ee /r] AVX,SANDYBRIDGE,SO +VPMAXSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f ee /r] AVX,SANDYBRIDGE,SO +VPMAXSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3d /r] AVX,SANDYBRIDGE,SO +VPMAXSD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3d /r] AVX,SANDYBRIDGE,SO +VPMAXUB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f de /r] AVX,SANDYBRIDGE,SO +VPMAXUB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f de /r] AVX,SANDYBRIDGE,SO +VPMAXUW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3e /r] AVX,SANDYBRIDGE,SO +VPMAXUW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3e /r] AVX,SANDYBRIDGE,SO +VPMAXUD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3f /r] AVX,SANDYBRIDGE,SO +VPMAXUD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3f /r] AVX,SANDYBRIDGE,SO +VPMINSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 38 /r] AVX,SANDYBRIDGE,SO +VPMINSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 38 /r] AVX,SANDYBRIDGE,SO +VPMINSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f ea /r] AVX,SANDYBRIDGE,SO +VPMINSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f ea /r] AVX,SANDYBRIDGE,SO +VPMINSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 39 /r] AVX,SANDYBRIDGE,SO +VPMINSD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 39 /r] AVX,SANDYBRIDGE,SO +VPMINUB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f da /r] AVX,SANDYBRIDGE,SO +VPMINUB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f da /r] AVX,SANDYBRIDGE,SO +VPMINUW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3a /r] AVX,SANDYBRIDGE,SO +VPMINUW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3a /r] AVX,SANDYBRIDGE,SO +VPMINUD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 3b /r] AVX,SANDYBRIDGE,SO +VPMINUD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 3b /r] AVX,SANDYBRIDGE,SO +VPMOVMSKB reg64,xmmreg [rm: vex.128.66.0f d7 /r] AVX,SANDYBRIDGE,LONG +VPMOVMSKB reg32,xmmreg [rm: vex.128.66.0f d7 /r] AVX,SANDYBRIDGE +VPMOVSXBW xmmreg,xmmrm [rm: vex.128.66.0f38 20 /r] AVX,SANDYBRIDGE,SQ +VPMOVSXBD xmmreg,xmmrm [rm: vex.128.66.0f38 21 /r] AVX,SANDYBRIDGE,SD +VPMOVSXBQ xmmreg,xmmrm [rm: vex.128.66.0f38 22 /r] AVX,SANDYBRIDGE,SW +VPMOVSXWD xmmreg,xmmrm [rm: vex.128.66.0f38 23 /r] AVX,SANDYBRIDGE,SQ +VPMOVSXWQ xmmreg,xmmrm [rm: vex.128.66.0f38 24 /r] AVX,SANDYBRIDGE,SD +VPMOVSXDQ xmmreg,xmmrm [rm: vex.128.66.0f38 25 /r] AVX,SANDYBRIDGE,SQ +VPMOVZXBW xmmreg,xmmrm [rm: vex.128.66.0f38 30 /r] AVX,SANDYBRIDGE,SQ +VPMOVZXBD xmmreg,xmmrm [rm: vex.128.66.0f38 31 /r] AVX,SANDYBRIDGE,SD +VPMOVZXBQ xmmreg,xmmrm [rm: vex.128.66.0f38 32 /r] AVX,SANDYBRIDGE,SW +VPMOVZXWD xmmreg,xmmrm [rm: vex.128.66.0f38 33 /r] AVX,SANDYBRIDGE,SQ +VPMOVZXWQ xmmreg,xmmrm [rm: vex.128.66.0f38 34 /r] AVX,SANDYBRIDGE,SD +VPMOVZXDQ xmmreg,xmmrm [rm: vex.128.66.0f38 35 /r] AVX,SANDYBRIDGE,SQ +VPMULHUW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e4 /r] AVX,SANDYBRIDGE,SO +VPMULHUW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e4 /r] AVX,SANDYBRIDGE,SO +VPMULHRSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 0b /r] AVX,SANDYBRIDGE,SO +VPMULHRSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 0b /r] AVX,SANDYBRIDGE,SO +VPMULHW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e5 /r] AVX,SANDYBRIDGE,SO +VPMULHW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e5 /r] AVX,SANDYBRIDGE,SO +VPMULLW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d5 /r] AVX,SANDYBRIDGE,SO +VPMULLW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d5 /r] AVX,SANDYBRIDGE,SO +VPMULLD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 40 /r] AVX,SANDYBRIDGE,SO +VPMULLD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 40 /r] AVX,SANDYBRIDGE,SO +VPMULUDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f4 /r] AVX,SANDYBRIDGE,SO +VPMULUDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f4 /r] AVX,SANDYBRIDGE,SO +VPMULDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 28 /r] AVX,SANDYBRIDGE,SO +VPMULDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 28 /r] AVX,SANDYBRIDGE,SO +VPOR xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f eb /r] AVX,SANDYBRIDGE,SO +VPOR xmmreg,xmmrm [r+vm: vex.nds.128.66.0f eb /r] AVX,SANDYBRIDGE,SO +VPSADBW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f6 /r] AVX,SANDYBRIDGE,SO +VPSADBW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f6 /r] AVX,SANDYBRIDGE,SO +VPSHUFB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 00 /r] AVX,SANDYBRIDGE,SO +VPSHUFB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 00 /r] AVX,SANDYBRIDGE,SO +VPSHUFD xmmreg,xmmrm,imm [rmi: vex.128.66.0f 70 /r ib] AVX,SANDYBRIDGE,SO +VPSHUFHW xmmreg,xmmrm,imm [rmi: vex.128.f3.0f 70 /r ib] AVX,SANDYBRIDGE,SO +VPSHUFLW xmmreg,xmmrm,imm [rmi: vex.128.f2.0f 70 /r ib] AVX,SANDYBRIDGE,SO +VPSIGNB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 08 /r] AVX,SANDYBRIDGE,SO +VPSIGNB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 08 /r] AVX,SANDYBRIDGE,SO +VPSIGNW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 09 /r] AVX,SANDYBRIDGE,SO +VPSIGNW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 09 /r] AVX,SANDYBRIDGE,SO +VPSIGND xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f38 0a /r] AVX,SANDYBRIDGE,SO +VPSIGND xmmreg,xmmrm [r+vm: vex.nds.128.66.0f38 0a /r] AVX,SANDYBRIDGE,SO +VPSLLDQ xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 73 /7 ib] AVX,SANDYBRIDGE +VPSLLDQ xmmreg,imm [v+mi: vex.ndd.128.66.0f 73 /7 ib] AVX,SANDYBRIDGE +VPSRLDQ xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 73 /3 ib] AVX,SANDYBRIDGE +VPSRLDQ xmmreg,imm [v+mi: vex.ndd.128.66.0f 73 /3 ib] AVX,SANDYBRIDGE +VPSLLW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f1 /r] AVX,SANDYBRIDGE,SO +VPSLLW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f1 /r] AVX,SANDYBRIDGE,SO +VPSLLW xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 71 /6 ib] AVX,SANDYBRIDGE +VPSLLW xmmreg,imm [v+mi: vex.ndd.128.66.0f 71 /6 ib] AVX,SANDYBRIDGE +VPSLLD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f2 /r] AVX,SANDYBRIDGE,SO +VPSLLD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f2 /r] AVX,SANDYBRIDGE,SO +VPSLLD xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 72 /6 ib] AVX,SANDYBRIDGE +VPSLLD xmmreg,imm [v+mi: vex.ndd.128.66.0f 72 /6 ib] AVX,SANDYBRIDGE +VPSLLQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f3 /r] AVX,SANDYBRIDGE,SO +VPSLLQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f3 /r] AVX,SANDYBRIDGE,SO +VPSLLQ xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 73 /6 ib] AVX,SANDYBRIDGE +VPSLLQ xmmreg,imm [v+mi: vex.ndd.128.66.0f 73 /6 ib] AVX,SANDYBRIDGE +VPSRAW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e1 /r] AVX,SANDYBRIDGE,SO +VPSRAW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e1 /r] AVX,SANDYBRIDGE,SO +VPSRAW xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 71 /4 ib] AVX,SANDYBRIDGE +VPSRAW xmmreg,imm [v+mi: vex.ndd.128.66.0f 71 /4 ib] AVX,SANDYBRIDGE +VPSRAD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e2 /r] AVX,SANDYBRIDGE,SO +VPSRAD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e2 /r] AVX,SANDYBRIDGE,SO +VPSRAD xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 72 /4 ib] AVX,SANDYBRIDGE +VPSRAD xmmreg,imm [v+mi: vex.ndd.128.66.0f 72 /4 ib] AVX,SANDYBRIDGE +VPSRLW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d1 /r] AVX,SANDYBRIDGE,SO +VPSRLW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d1 /r] AVX,SANDYBRIDGE,SO +VPSRLW xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 71 /2 ib] AVX,SANDYBRIDGE +VPSRLW xmmreg,imm [v+mi: vex.ndd.128.66.0f 71 /2 ib] AVX,SANDYBRIDGE +VPSRLD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d2 /r] AVX,SANDYBRIDGE,SO +VPSRLD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d2 /r] AVX,SANDYBRIDGE,SO +VPSRLD xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 72 /2 ib] AVX,SANDYBRIDGE +VPSRLD xmmreg,imm [v+mi: vex.ndd.128.66.0f 72 /2 ib] AVX,SANDYBRIDGE +VPSRLQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d3 /r] AVX,SANDYBRIDGE,SO +VPSRLQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d3 /r] AVX,SANDYBRIDGE,SO +VPSRLQ xmmreg,xmmreg,imm [vmi: vex.ndd.128.66.0f 73 /2 ib] AVX,SANDYBRIDGE +VPSRLQ xmmreg,imm [v+mi: vex.ndd.128.66.0f 73 /2 ib] AVX,SANDYBRIDGE +VPTEST xmmreg,xmmrm [rm: vex.128.66.0f38 17 /r] AVX,SANDYBRIDGE,SO +VPTEST ymmreg,ymmrm [rm: vex.256.66.0f38 17 /r] AVX,SANDYBRIDGE,SY +VPSUBB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f8 /r] AVX,SANDYBRIDGE,SO +VPSUBB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f8 /r] AVX,SANDYBRIDGE,SO +VPSUBW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f f9 /r] AVX,SANDYBRIDGE,SO +VPSUBW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f f9 /r] AVX,SANDYBRIDGE,SO +VPSUBD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f fa /r] AVX,SANDYBRIDGE,SO +VPSUBD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f fa /r] AVX,SANDYBRIDGE,SO +VPSUBQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f fb /r] AVX,SANDYBRIDGE,SO +VPSUBQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f fb /r] AVX,SANDYBRIDGE,SO +VPSUBSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e8 /r] AVX,SANDYBRIDGE,SO +VPSUBSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e8 /r] AVX,SANDYBRIDGE,SO +VPSUBSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f e9 /r] AVX,SANDYBRIDGE,SO +VPSUBSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f e9 /r] AVX,SANDYBRIDGE,SO +VPSUBUSB xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d8 /r] AVX,SANDYBRIDGE,SO +VPSUBUSB xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d8 /r] AVX,SANDYBRIDGE,SO +VPSUBUSW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f d9 /r] AVX,SANDYBRIDGE,SO +VPSUBUSW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f d9 /r] AVX,SANDYBRIDGE,SO +VPUNPCKHBW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 68 /r] AVX,SANDYBRIDGE,SO +VPUNPCKHBW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 68 /r] AVX,SANDYBRIDGE,SO +VPUNPCKHWD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 69 /r] AVX,SANDYBRIDGE,SO +VPUNPCKHWD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 69 /r] AVX,SANDYBRIDGE,SO +VPUNPCKHDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 6a /r] AVX,SANDYBRIDGE,SO +VPUNPCKHDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 6a /r] AVX,SANDYBRIDGE,SO +VPUNPCKHQDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 6d /r] AVX,SANDYBRIDGE,SO +VPUNPCKHQDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 6d /r] AVX,SANDYBRIDGE,SO +VPUNPCKLBW xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 60 /r] AVX,SANDYBRIDGE,SO +VPUNPCKLBW xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 60 /r] AVX,SANDYBRIDGE,SO +VPUNPCKLWD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 61 /r] AVX,SANDYBRIDGE,SO +VPUNPCKLWD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 61 /r] AVX,SANDYBRIDGE,SO +VPUNPCKLDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 62 /r] AVX,SANDYBRIDGE,SO +VPUNPCKLDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 62 /r] AVX,SANDYBRIDGE,SO +VPUNPCKLQDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 6c /r] AVX,SANDYBRIDGE,SO +VPUNPCKLQDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 6c /r] AVX,SANDYBRIDGE,SO +VPXOR xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f ef /r] AVX,SANDYBRIDGE,SO +VPXOR xmmreg,xmmrm [r+vm: vex.nds.128.66.0f ef /r] AVX,SANDYBRIDGE,SO +VRCPPS xmmreg,xmmrm [rm: vex.128.0f 53 /r] AVX,SANDYBRIDGE,SO +VRCPPS ymmreg,ymmrm [rm: vex.256.0f 53 /r] AVX,SANDYBRIDGE,SY +VRCPSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 53 /r] AVX,SANDYBRIDGE,SD +VRCPSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 53 /r] AVX,SANDYBRIDGE,SD +VRSQRTPS xmmreg,xmmrm [rm: vex.128.0f 52 /r] AVX,SANDYBRIDGE,SO +VRSQRTPS ymmreg,ymmrm [rm: vex.256.0f 52 /r] AVX,SANDYBRIDGE,SY +VRSQRTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 52 /r] AVX,SANDYBRIDGE,SD +VRSQRTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 52 /r] AVX,SANDYBRIDGE,SD +VROUNDPD xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 09 /r ib] AVX,SANDYBRIDGE,SO +VROUNDPD ymmreg,ymmrm,imm [rmi: vex.256.66.0f3a 09 /r ib] AVX,SANDYBRIDGE,SY +VROUNDPS xmmreg,xmmrm,imm [rmi: vex.128.66.0f3a 08 /r ib] AVX,SANDYBRIDGE,SO +VROUNDPS ymmreg,ymmrm,imm [rmi: vex.256.66.0f3a 08 /r ib] AVX,SANDYBRIDGE,SY +VROUNDSD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0b /r ib] AVX,SANDYBRIDGE,SQ +VROUNDSD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0b /r ib] AVX,SANDYBRIDGE,SQ +VROUNDSS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 0a /r ib] AVX,SANDYBRIDGE,SD +VROUNDSS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 0a /r ib] AVX,SANDYBRIDGE,SD +VSHUFPD xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f c6 /r ib] AVX,SANDYBRIDGE,SO +VSHUFPD xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f c6 /r ib] AVX,SANDYBRIDGE,SO +VSHUFPD ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.66.0f c6 /r ib] AVX,SANDYBRIDGE,SY +VSHUFPD ymmreg,ymmrm,imm [r+vmi: vex.nds.256.66.0f c6 /r ib] AVX,SANDYBRIDGE,SY +VSHUFPS xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.0f c6 /r ib] AVX,SANDYBRIDGE,SO +VSHUFPS xmmreg,xmmrm,imm [r+vmi: vex.nds.128.0f c6 /r ib] AVX,SANDYBRIDGE,SO +VSHUFPS ymmreg,ymmreg,ymmrm,imm [rvmi: vex.nds.256.0f c6 /r ib] AVX,SANDYBRIDGE,SY +VSHUFPS ymmreg,ymmrm,imm [r+vmi: vex.nds.256.0f c6 /r ib] AVX,SANDYBRIDGE,SY +VSQRTPD xmmreg,xmmrm [rm: vex.128.66.0f 51 /r] AVX,SANDYBRIDGE,SO +VSQRTPD ymmreg,ymmrm [rm: vex.256.66.0f 51 /r] AVX,SANDYBRIDGE,SY +VSQRTPS xmmreg,xmmrm [rm: vex.128.0f 51 /r] AVX,SANDYBRIDGE,SO +VSQRTPS ymmreg,ymmrm [rm: vex.256.0f 51 /r] AVX,SANDYBRIDGE,SY +VSQRTSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 51 /r] AVX,SANDYBRIDGE,SQ +VSQRTSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 51 /r] AVX,SANDYBRIDGE,SQ +VSQRTSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 51 /r] AVX,SANDYBRIDGE,SD +VSQRTSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 51 /r] AVX,SANDYBRIDGE,SD +VSTMXCSR mem [m: vex.128.0f ae /3] AVX,SANDYBRIDGE,SD +VSUBPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 5c /r] AVX,SANDYBRIDGE,SO +VSUBPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 5c /r] AVX,SANDYBRIDGE,SO +VSUBPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 5c /r] AVX,SANDYBRIDGE,SY +VSUBPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 5c /r] AVX,SANDYBRIDGE,SY +VSUBPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 5c /r] AVX,SANDYBRIDGE,SO +VSUBPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 5c /r] AVX,SANDYBRIDGE,SO +VSUBPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 5c /r] AVX,SANDYBRIDGE,SY +VSUBPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 5c /r] AVX,SANDYBRIDGE,SY +VSUBSD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f2.0f 5c /r] AVX,SANDYBRIDGE,SQ +VSUBSD xmmreg,xmmrm [r+vm: vex.nds.128.f2.0f 5c /r] AVX,SANDYBRIDGE,SQ +VSUBSS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.f3.0f 5c /r] AVX,SANDYBRIDGE,SD +VSUBSS xmmreg,xmmrm [r+vm: vex.nds.128.f3.0f 5c /r] AVX,SANDYBRIDGE,SD +VTESTPS xmmreg,xmmrm [rm: vex.128.66.0f38 0e /r] AVX,SANDYBRIDGE,SO +VTESTPS ymmreg,ymmrm [rm: vex.256.66.0f38 0e /r] AVX,SANDYBRIDGE,SY +VTESTPD xmmreg,xmmrm [rm: vex.128.66.0f38 0f /r] AVX,SANDYBRIDGE,SO +VTESTPD ymmreg,ymmrm [rm: vex.256.66.0f38 0f /r] AVX,SANDYBRIDGE,SY +VUCOMISD xmmreg,xmmrm [rm: vex.128.66.0f 2e /r] AVX,SANDYBRIDGE,SQ +VUCOMISS xmmreg,xmmrm [rm: vex.128.0f 2e /r] AVX,SANDYBRIDGE,SD +VUNPCKHPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 15 /r] AVX,SANDYBRIDGE,SO +VUNPCKHPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 15 /r] AVX,SANDYBRIDGE,SO +VUNPCKHPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 15 /r] AVX,SANDYBRIDGE,SY +VUNPCKHPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 15 /r] AVX,SANDYBRIDGE,SY +VUNPCKHPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 15 /r] AVX,SANDYBRIDGE,SO +VUNPCKHPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 15 /r] AVX,SANDYBRIDGE,SO +VUNPCKHPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 15 /r] AVX,SANDYBRIDGE,SY +VUNPCKHPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 15 /r] AVX,SANDYBRIDGE,SY +VUNPCKLPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 14 /r] AVX,SANDYBRIDGE,SO +VUNPCKLPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 14 /r] AVX,SANDYBRIDGE,SO +VUNPCKLPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 14 /r] AVX,SANDYBRIDGE,SY +VUNPCKLPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 14 /r] AVX,SANDYBRIDGE,SY +VUNPCKLPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 14 /r] AVX,SANDYBRIDGE,SO +VUNPCKLPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 14 /r] AVX,SANDYBRIDGE,SO +VUNPCKLPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 14 /r] AVX,SANDYBRIDGE,SY +VUNPCKLPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 14 /r] AVX,SANDYBRIDGE,SY +VXORPD xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f 57 /r] AVX,SANDYBRIDGE,SO +VXORPD xmmreg,xmmrm [r+vm: vex.nds.128.66.0f 57 /r] AVX,SANDYBRIDGE,SO +VXORPD ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.66.0f 57 /r] AVX,SANDYBRIDGE,SY +VXORPD ymmreg,ymmrm [r+vm: vex.nds.256.66.0f 57 /r] AVX,SANDYBRIDGE,SY +VXORPS xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.0f 57 /r] AVX,SANDYBRIDGE,SO +VXORPS xmmreg,xmmrm [r+vm: vex.nds.128.0f 57 /r] AVX,SANDYBRIDGE,SO +VXORPS ymmreg,ymmreg,ymmrm [rvm: vex.nds.256.0f 57 /r] AVX,SANDYBRIDGE,SY +VXORPS ymmreg,ymmrm [r+vm: vex.nds.256.0f 57 /r] AVX,SANDYBRIDGE,SY +VZEROALL void [ vex.256.0f 77] AVX,SANDYBRIDGE +VZEROUPPER void [ vex.128.0f 77] AVX,SANDYBRIDGE + +;# Intel Carry-Less Multiplication instructions (CLMUL) +PCLMULLQLQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 00] SSE,WESTMERE,SO +PCLMULHQLQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 01] SSE,WESTMERE,SO +PCLMULLQHQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 10] SSE,WESTMERE,SO +PCLMULHQHQDQ xmmreg,xmmrm [rm: 66 0f 3a 44 /r 11] SSE,WESTMERE,SO +PCLMULQDQ xmmreg,xmmrm,imm [rmi: 66 0f 3a 44 /r ib] SSE,WESTMERE,SO + +;# Intel AVX Carry-Less Multiplication instructions (CLMUL) +VPCLMULLQLQDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f3a 44 /r 00] AVX,SANDYBRIDGE,SO +VPCLMULLQLQDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f3a 44 /r 00] AVX,SANDYBRIDGE,SO +VPCLMULHQLQDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f3a 44 /r 01] AVX,SANDYBRIDGE,SO +VPCLMULHQLQDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f3a 44 /r 01] AVX,SANDYBRIDGE,SO +VPCLMULLQHQDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f3a 44 /r 10] AVX,SANDYBRIDGE,SO +VPCLMULLQHQDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f3a 44 /r 10] AVX,SANDYBRIDGE,SO +VPCLMULHQHQDQ xmmreg,xmmreg,xmmrm [rvm: vex.nds.128.66.0f3a 44 /r 11] AVX,SANDYBRIDGE,SO +VPCLMULHQHQDQ xmmreg,xmmrm [r+vm: vex.nds.128.66.0f3a 44 /r 11] AVX,SANDYBRIDGE,SO +VPCLMULQDQ xmmreg,xmmreg,xmmrm,imm [rvmi: vex.nds.128.66.0f3a 44 /r ib] AVX,SANDYBRIDGE,SO +VPCLMULQDQ xmmreg,xmmrm,imm [r+vmi: vex.nds.128.66.0f3a 44 /r ib] AVX,SANDYBRIDGE,SO + +;# Intel Fused Multiply-Add instructions (FMA) +VFMADD132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 98 /r] FMA,FUTURE,SO +VFMADD132PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 98 /r] FMA,FUTURE,SO +VFMADD132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 98 /r] FMA,FUTURE,SY +VFMADD132PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 98 /r] FMA,FUTURE,SY +VFMADD132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 98 /r] FMA,FUTURE,SO +VFMADD132PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 98 /r] FMA,FUTURE,SO +VFMADD132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 98 /r] FMA,FUTURE,SY +VFMADD132PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 98 /r] FMA,FUTURE,SY +VFMADD312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 98 /r] FMA,FUTURE,SO +VFMADD312PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 98 /r] FMA,FUTURE,SO +VFMADD312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 98 /r] FMA,FUTURE,SY +VFMADD312PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 98 /r] FMA,FUTURE,SY +VFMADD312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 98 /r] FMA,FUTURE,SO +VFMADD312PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 98 /r] FMA,FUTURE,SO +VFMADD312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 98 /r] FMA,FUTURE,SY +VFMADD312PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 98 /r] FMA,FUTURE,SY +VFMADD213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a8 /r] FMA,FUTURE,SO +VFMADD213PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 a8 /r] FMA,FUTURE,SO +VFMADD213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a8 /r] FMA,FUTURE,SY +VFMADD213PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 a8 /r] FMA,FUTURE,SY +VFMADD213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a8 /r] FMA,FUTURE,SO +VFMADD213PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 a8 /r] FMA,FUTURE,SO +VFMADD213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a8 /r] FMA,FUTURE,SY +VFMADD213PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 a8 /r] FMA,FUTURE,SY +VFMADD123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a8 /r] FMA,FUTURE,SO +VFMADD123PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 a8 /r] FMA,FUTURE,SO +VFMADD123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a8 /r] FMA,FUTURE,SY +VFMADD123PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 a8 /r] FMA,FUTURE,SY +VFMADD123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a8 /r] FMA,FUTURE,SO +VFMADD123PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 a8 /r] FMA,FUTURE,SO +VFMADD123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a8 /r] FMA,FUTURE,SY +VFMADD123PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 a8 /r] FMA,FUTURE,SY +VFMADD231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b8 /r] FMA,FUTURE,SO +VFMADD231PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 b8 /r] FMA,FUTURE,SO +VFMADD231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b8 /r] FMA,FUTURE,SY +VFMADD231PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 b8 /r] FMA,FUTURE,SY +VFMADD231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b8 /r] FMA,FUTURE,SO +VFMADD231PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 b8 /r] FMA,FUTURE,SO +VFMADD231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b8 /r] FMA,FUTURE,SY +VFMADD231PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 b8 /r] FMA,FUTURE,SY +VFMADD321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b8 /r] FMA,FUTURE,SO +VFMADD321PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 b8 /r] FMA,FUTURE,SO +VFMADD321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b8 /r] FMA,FUTURE,SY +VFMADD321PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 b8 /r] FMA,FUTURE,SY +VFMADD321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b8 /r] FMA,FUTURE,SO +VFMADD321PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 b8 /r] FMA,FUTURE,SO +VFMADD321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b8 /r] FMA,FUTURE,SY +VFMADD321PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 b8 /r] FMA,FUTURE,SY +VFMADDSUB132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 96 /r] FMA,FUTURE,SO +VFMADDSUB132PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 96 /r] FMA,FUTURE,SO +VFMADDSUB132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 96 /r] FMA,FUTURE,SY +VFMADDSUB132PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 96 /r] FMA,FUTURE,SY +VFMADDSUB132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 96 /r] FMA,FUTURE,SO +VFMADDSUB132PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 96 /r] FMA,FUTURE,SO +VFMADDSUB132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 96 /r] FMA,FUTURE,SY +VFMADDSUB132PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 96 /r] FMA,FUTURE,SY +VFMADDSUB312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 96 /r] FMA,FUTURE,SO +VFMADDSUB312PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 96 /r] FMA,FUTURE,SO +VFMADDSUB312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 96 /r] FMA,FUTURE,SY +VFMADDSUB312PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 96 /r] FMA,FUTURE,SY +VFMADDSUB312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 96 /r] FMA,FUTURE,SO +VFMADDSUB312PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 96 /r] FMA,FUTURE,SO +VFMADDSUB312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 96 /r] FMA,FUTURE,SY +VFMADDSUB312PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 96 /r] FMA,FUTURE,SY +VFMADDSUB213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a6 /r] FMA,FUTURE,SO +VFMADDSUB213PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 a6 /r] FMA,FUTURE,SO +VFMADDSUB213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a6 /r] FMA,FUTURE,SY +VFMADDSUB213PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 a6 /r] FMA,FUTURE,SY +VFMADDSUB213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a6 /r] FMA,FUTURE,SO +VFMADDSUB213PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 a6 /r] FMA,FUTURE,SO +VFMADDSUB213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a6 /r] FMA,FUTURE,SY +VFMADDSUB213PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 a6 /r] FMA,FUTURE,SY +VFMADDSUB123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a6 /r] FMA,FUTURE,SO +VFMADDSUB123PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 a6 /r] FMA,FUTURE,SO +VFMADDSUB123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a6 /r] FMA,FUTURE,SY +VFMADDSUB123PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 a6 /r] FMA,FUTURE,SY +VFMADDSUB123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a6 /r] FMA,FUTURE,SO +VFMADDSUB123PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 a6 /r] FMA,FUTURE,SO +VFMADDSUB123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a6 /r] FMA,FUTURE,SY +VFMADDSUB123PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 a6 /r] FMA,FUTURE,SY +VFMADDSUB231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b6 /r] FMA,FUTURE,SO +VFMADDSUB231PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 b6 /r] FMA,FUTURE,SO +VFMADDSUB231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b6 /r] FMA,FUTURE,SY +VFMADDSUB231PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 b6 /r] FMA,FUTURE,SY +VFMADDSUB231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b6 /r] FMA,FUTURE,SO +VFMADDSUB231PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 b6 /r] FMA,FUTURE,SO +VFMADDSUB231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b6 /r] FMA,FUTURE,SY +VFMADDSUB231PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 b6 /r] FMA,FUTURE,SY +VFMADDSUB321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b6 /r] FMA,FUTURE,SO +VFMADDSUB321PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 b6 /r] FMA,FUTURE,SO +VFMADDSUB321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b6 /r] FMA,FUTURE,SY +VFMADDSUB321PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 b6 /r] FMA,FUTURE,SY +VFMADDSUB321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b6 /r] FMA,FUTURE,SO +VFMADDSUB321PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 b6 /r] FMA,FUTURE,SO +VFMADDSUB321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b6 /r] FMA,FUTURE,SY +VFMADDSUB321PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 b6 /r] FMA,FUTURE,SY +VFMSUB132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9a /r] FMA,FUTURE,SO +VFMSUB132PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9a /r] FMA,FUTURE,SO +VFMSUB132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9a /r] FMA,FUTURE,SY +VFMSUB132PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 9a /r] FMA,FUTURE,SY +VFMSUB132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9a /r] FMA,FUTURE,SO +VFMSUB132PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9a /r] FMA,FUTURE,SO +VFMSUB132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9a /r] FMA,FUTURE,SY +VFMSUB132PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 9a /r] FMA,FUTURE,SY +VFMSUB312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9a /r] FMA,FUTURE,SO +VFMSUB312PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9a /r] FMA,FUTURE,SO +VFMSUB312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9a /r] FMA,FUTURE,SY +VFMSUB312PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 9a /r] FMA,FUTURE,SY +VFMSUB312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9a /r] FMA,FUTURE,SO +VFMSUB312PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9a /r] FMA,FUTURE,SO +VFMSUB312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9a /r] FMA,FUTURE,SY +VFMSUB312PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 9a /r] FMA,FUTURE,SY +VFMSUB213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 aa /r] FMA,FUTURE,SO +VFMSUB213PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 aa /r] FMA,FUTURE,SO +VFMSUB213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 aa /r] FMA,FUTURE,SY +VFMSUB213PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 aa /r] FMA,FUTURE,SY +VFMSUB213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 aa /r] FMA,FUTURE,SO +VFMSUB213PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 aa /r] FMA,FUTURE,SO +VFMSUB213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 aa /r] FMA,FUTURE,SY +VFMSUB213PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 aa /r] FMA,FUTURE,SY +VFMSUB123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 aa /r] FMA,FUTURE,SO +VFMSUB123PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 aa /r] FMA,FUTURE,SO +VFMSUB123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 aa /r] FMA,FUTURE,SY +VFMSUB123PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 aa /r] FMA,FUTURE,SY +VFMSUB123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 aa /r] FMA,FUTURE,SO +VFMSUB123PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 aa /r] FMA,FUTURE,SO +VFMSUB123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 aa /r] FMA,FUTURE,SY +VFMSUB123PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 aa /r] FMA,FUTURE,SY +VFMSUB231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ba /r] FMA,FUTURE,SO +VFMSUB231PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 ba /r] FMA,FUTURE,SO +VFMSUB231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ba /r] FMA,FUTURE,SY +VFMSUB231PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 ba /r] FMA,FUTURE,SY +VFMSUB231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ba /r] FMA,FUTURE,SO +VFMSUB231PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 ba /r] FMA,FUTURE,SO +VFMSUB231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ba /r] FMA,FUTURE,SY +VFMSUB231PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 ba /r] FMA,FUTURE,SY +VFMSUB321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ba /r] FMA,FUTURE,SO +VFMSUB321PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 ba /r] FMA,FUTURE,SO +VFMSUB321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ba /r] FMA,FUTURE,SY +VFMSUB321PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 ba /r] FMA,FUTURE,SY +VFMSUB321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ba /r] FMA,FUTURE,SO +VFMSUB321PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 ba /r] FMA,FUTURE,SO +VFMSUB321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ba /r] FMA,FUTURE,SY +VFMSUB321PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 ba /r] FMA,FUTURE,SY +VFMSUBADD132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 97 /r] FMA,FUTURE,SO +VFMSUBADD132PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 97 /r] FMA,FUTURE,SO +VFMSUBADD132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 97 /r] FMA,FUTURE,SY +VFMSUBADD132PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 97 /r] FMA,FUTURE,SY +VFMSUBADD132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 97 /r] FMA,FUTURE,SO +VFMSUBADD132PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 97 /r] FMA,FUTURE,SO +VFMSUBADD132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 97 /r] FMA,FUTURE,SY +VFMSUBADD132PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 97 /r] FMA,FUTURE,SY +VFMSUBADD312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 97 /r] FMA,FUTURE,SO +VFMSUBADD312PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 97 /r] FMA,FUTURE,SO +VFMSUBADD312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 97 /r] FMA,FUTURE,SY +VFMSUBADD312PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 97 /r] FMA,FUTURE,SY +VFMSUBADD312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 97 /r] FMA,FUTURE,SO +VFMSUBADD312PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 97 /r] FMA,FUTURE,SO +VFMSUBADD312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 97 /r] FMA,FUTURE,SY +VFMSUBADD312PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 97 /r] FMA,FUTURE,SY +VFMSUBADD213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a7 /r] FMA,FUTURE,SO +VFMSUBADD213PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 a7 /r] FMA,FUTURE,SO +VFMSUBADD213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a7 /r] FMA,FUTURE,SY +VFMSUBADD213PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 a7 /r] FMA,FUTURE,SY +VFMSUBADD213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a7 /r] FMA,FUTURE,SO +VFMSUBADD213PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 a7 /r] FMA,FUTURE,SO +VFMSUBADD213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a7 /r] FMA,FUTURE,SY +VFMSUBADD213PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 a7 /r] FMA,FUTURE,SY +VFMSUBADD123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a7 /r] FMA,FUTURE,SO +VFMSUBADD123PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 a7 /r] FMA,FUTURE,SO +VFMSUBADD123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 a7 /r] FMA,FUTURE,SY +VFMSUBADD123PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 a7 /r] FMA,FUTURE,SY +VFMSUBADD123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a7 /r] FMA,FUTURE,SO +VFMSUBADD123PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 a7 /r] FMA,FUTURE,SO +VFMSUBADD123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 a7 /r] FMA,FUTURE,SY +VFMSUBADD123PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 a7 /r] FMA,FUTURE,SY +VFMSUBADD231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b7 /r] FMA,FUTURE,SO +VFMSUBADD231PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 b7 /r] FMA,FUTURE,SO +VFMSUBADD231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b7 /r] FMA,FUTURE,SY +VFMSUBADD231PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 b7 /r] FMA,FUTURE,SY +VFMSUBADD231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b7 /r] FMA,FUTURE,SO +VFMSUBADD231PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 b7 /r] FMA,FUTURE,SO +VFMSUBADD231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b7 /r] FMA,FUTURE,SY +VFMSUBADD231PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 b7 /r] FMA,FUTURE,SY +VFMSUBADD321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b7 /r] FMA,FUTURE,SO +VFMSUBADD321PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 b7 /r] FMA,FUTURE,SO +VFMSUBADD321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 b7 /r] FMA,FUTURE,SY +VFMSUBADD321PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 b7 /r] FMA,FUTURE,SY +VFMSUBADD321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b7 /r] FMA,FUTURE,SO +VFMSUBADD321PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 b7 /r] FMA,FUTURE,SO +VFMSUBADD321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 b7 /r] FMA,FUTURE,SY +VFMSUBADD321PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 b7 /r] FMA,FUTURE,SY +VFNMADD132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9c /r] FMA,FUTURE,SO +VFNMADD132PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9c /r] FMA,FUTURE,SO +VFNMADD132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9c /r] FMA,FUTURE,SY +VFNMADD132PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 9c /r] FMA,FUTURE,SY +VFNMADD132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9c /r] FMA,FUTURE,SO +VFNMADD132PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9c /r] FMA,FUTURE,SO +VFNMADD132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9c /r] FMA,FUTURE,SY +VFNMADD132PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 9c /r] FMA,FUTURE,SY +VFNMADD312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9c /r] FMA,FUTURE,SO +VFNMADD312PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9c /r] FMA,FUTURE,SO +VFNMADD312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9c /r] FMA,FUTURE,SY +VFNMADD312PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 9c /r] FMA,FUTURE,SY +VFNMADD312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9c /r] FMA,FUTURE,SO +VFNMADD312PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9c /r] FMA,FUTURE,SO +VFNMADD312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9c /r] FMA,FUTURE,SY +VFNMADD312PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 9c /r] FMA,FUTURE,SY +VFNMADD213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ac /r] FMA,FUTURE,SO +VFNMADD213PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 ac /r] FMA,FUTURE,SO +VFNMADD213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ac /r] FMA,FUTURE,SY +VFNMADD213PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 ac /r] FMA,FUTURE,SY +VFNMADD213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ac /r] FMA,FUTURE,SO +VFNMADD213PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 ac /r] FMA,FUTURE,SO +VFNMADD213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ac /r] FMA,FUTURE,SY +VFNMADD213PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 ac /r] FMA,FUTURE,SY +VFNMADD123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ac /r] FMA,FUTURE,SO +VFNMADD123PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 ac /r] FMA,FUTURE,SO +VFNMADD123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ac /r] FMA,FUTURE,SY +VFNMADD123PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 ac /r] FMA,FUTURE,SY +VFNMADD123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ac /r] FMA,FUTURE,SO +VFNMADD123PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 ac /r] FMA,FUTURE,SO +VFNMADD123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ac /r] FMA,FUTURE,SY +VFNMADD123PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 ac /r] FMA,FUTURE,SY +VFNMADD231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bc /r] FMA,FUTURE,SO +VFNMADD231PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 bc /r] FMA,FUTURE,SO +VFNMADD231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 bc /r] FMA,FUTURE,SY +VFNMADD231PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 bc /r] FMA,FUTURE,SY +VFNMADD231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bc /r] FMA,FUTURE,SO +VFNMADD231PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 bc /r] FMA,FUTURE,SO +VFNMADD231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 bc /r] FMA,FUTURE,SY +VFNMADD231PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 bc /r] FMA,FUTURE,SY +VFNMADD321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bc /r] FMA,FUTURE,SO +VFNMADD321PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 bc /r] FMA,FUTURE,SO +VFNMADD321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 bc /r] FMA,FUTURE,SY +VFNMADD321PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 bc /r] FMA,FUTURE,SY +VFNMADD321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bc /r] FMA,FUTURE,SO +VFNMADD321PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 bc /r] FMA,FUTURE,SO +VFNMADD321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 bc /r] FMA,FUTURE,SY +VFNMADD321PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 bc /r] FMA,FUTURE,SY +VFNMSUB132PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9e /r] FMA,FUTURE,SO +VFNMSUB132PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9e /r] FMA,FUTURE,SO +VFNMSUB132PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9e /r] FMA,FUTURE,SY +VFNMSUB132PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 9e /r] FMA,FUTURE,SY +VFNMSUB132PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9e /r] FMA,FUTURE,SO +VFNMSUB132PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9e /r] FMA,FUTURE,SO +VFNMSUB132PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9e /r] FMA,FUTURE,SY +VFNMSUB132PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 9e /r] FMA,FUTURE,SY +VFNMSUB312PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9e /r] FMA,FUTURE,SO +VFNMSUB312PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9e /r] FMA,FUTURE,SO +VFNMSUB312PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 9e /r] FMA,FUTURE,SY +VFNMSUB312PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 9e /r] FMA,FUTURE,SY +VFNMSUB312PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9e /r] FMA,FUTURE,SO +VFNMSUB312PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9e /r] FMA,FUTURE,SO +VFNMSUB312PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 9e /r] FMA,FUTURE,SY +VFNMSUB312PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 9e /r] FMA,FUTURE,SY +VFNMSUB213PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ae /r] FMA,FUTURE,SO +VFNMSUB213PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 ae /r] FMA,FUTURE,SO +VFNMSUB213PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ae /r] FMA,FUTURE,SY +VFNMSUB213PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 ae /r] FMA,FUTURE,SY +VFNMSUB213PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ae /r] FMA,FUTURE,SO +VFNMSUB213PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 ae /r] FMA,FUTURE,SO +VFNMSUB213PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ae /r] FMA,FUTURE,SY +VFNMSUB213PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 ae /r] FMA,FUTURE,SY +VFNMSUB123PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ae /r] FMA,FUTURE,SO +VFNMSUB123PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 ae /r] FMA,FUTURE,SO +VFNMSUB123PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 ae /r] FMA,FUTURE,SY +VFNMSUB123PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 ae /r] FMA,FUTURE,SY +VFNMSUB123PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ae /r] FMA,FUTURE,SO +VFNMSUB123PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 ae /r] FMA,FUTURE,SO +VFNMSUB123PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 ae /r] FMA,FUTURE,SY +VFNMSUB123PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 ae /r] FMA,FUTURE,SY +VFNMSUB231PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 be /r] FMA,FUTURE,SO +VFNMSUB231PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 be /r] FMA,FUTURE,SO +VFNMSUB231PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 be /r] FMA,FUTURE,SY +VFNMSUB231PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 be /r] FMA,FUTURE,SY +VFNMSUB231PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 be /r] FMA,FUTURE,SO +VFNMSUB231PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 be /r] FMA,FUTURE,SO +VFNMSUB231PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 be /r] FMA,FUTURE,SY +VFNMSUB231PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 be /r] FMA,FUTURE,SY +VFNMSUB321PS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 be /r] FMA,FUTURE,SO +VFNMSUB321PS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 be /r] FMA,FUTURE,SO +VFNMSUB321PS ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w0 be /r] FMA,FUTURE,SY +VFNMSUB321PS ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w0 be /r] FMA,FUTURE,SY +VFNMSUB321PD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 be /r] FMA,FUTURE,SO +VFNMSUB321PD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 be /r] FMA,FUTURE,SO +VFNMSUB321PD ymmreg,ymmreg,ymmrm [rvm: vex.dds.256.66.0f38.w1 be /r] FMA,FUTURE,SY +VFNMSUB321PD ymmreg,ymmrm [r+vm: vex.dds.256.66.0f38.w1 be /r] FMA,FUTURE,SY +VFMADD132SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 99 /r] FMA,FUTURE,SD +VFMADD132SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 99 /r] FMA,FUTURE,SD +VFMADD132SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 99 /r] FMA,FUTURE,SQ +VFMADD132SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 99 /r] FMA,FUTURE,SQ +VFMADD312SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 99 /r] FMA,FUTURE,SD +VFMADD312SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 99 /r] FMA,FUTURE,SD +VFMADD312SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 99 /r] FMA,FUTURE,SQ +VFMADD312SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 99 /r] FMA,FUTURE,SQ +VFMADD213SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a9 /r] FMA,FUTURE,SD +VFMADD213SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 a9 /r] FMA,FUTURE,SD +VFMADD213SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a9 /r] FMA,FUTURE,SQ +VFMADD213SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 a9 /r] FMA,FUTURE,SQ +VFMADD123SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 a9 /r] FMA,FUTURE,SD +VFMADD123SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 a9 /r] FMA,FUTURE,SD +VFMADD123SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 a9 /r] FMA,FUTURE,SQ +VFMADD123SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 a9 /r] FMA,FUTURE,SQ +VFMADD231SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b9 /r] FMA,FUTURE,SD +VFMADD231SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 b9 /r] FMA,FUTURE,SD +VFMADD231SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b9 /r] FMA,FUTURE,SQ +VFMADD231SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 b9 /r] FMA,FUTURE,SQ +VFMADD321SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 b9 /r] FMA,FUTURE,SD +VFMADD321SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 b9 /r] FMA,FUTURE,SD +VFMADD321SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 b9 /r] FMA,FUTURE,SQ +VFMADD321SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 b9 /r] FMA,FUTURE,SQ +VFMSUB132SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9b /r] FMA,FUTURE,SD +VFMSUB132SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9b /r] FMA,FUTURE,SD +VFMSUB132SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9b /r] FMA,FUTURE,SQ +VFMSUB132SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9b /r] FMA,FUTURE,SQ +VFMSUB312SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9b /r] FMA,FUTURE,SD +VFMSUB312SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9b /r] FMA,FUTURE,SD +VFMSUB312SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9b /r] FMA,FUTURE,SQ +VFMSUB312SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9b /r] FMA,FUTURE,SQ +VFMSUB213SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ab /r] FMA,FUTURE,SD +VFMSUB213SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 ab /r] FMA,FUTURE,SD +VFMSUB213SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ab /r] FMA,FUTURE,SQ +VFMSUB213SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 ab /r] FMA,FUTURE,SQ +VFMSUB123SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ab /r] FMA,FUTURE,SD +VFMSUB123SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 ab /r] FMA,FUTURE,SD +VFMSUB123SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ab /r] FMA,FUTURE,SQ +VFMSUB123SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 ab /r] FMA,FUTURE,SQ +VFMSUB231SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bb /r] FMA,FUTURE,SD +VFMSUB231SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 bb /r] FMA,FUTURE,SD +VFMSUB231SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bb /r] FMA,FUTURE,SQ +VFMSUB231SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 bb /r] FMA,FUTURE,SQ +VFMSUB321SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bb /r] FMA,FUTURE,SD +VFMSUB321SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 bb /r] FMA,FUTURE,SD +VFMSUB321SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bb /r] FMA,FUTURE,SQ +VFMSUB321SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 bb /r] FMA,FUTURE,SQ +VFNMADD132SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9d /r] FMA,FUTURE,SD +VFNMADD132SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9d /r] FMA,FUTURE,SD +VFNMADD132SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9d /r] FMA,FUTURE,SQ +VFNMADD132SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9d /r] FMA,FUTURE,SQ +VFNMADD312SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9d /r] FMA,FUTURE,SD +VFNMADD312SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9d /r] FMA,FUTURE,SD +VFNMADD312SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9d /r] FMA,FUTURE,SQ +VFNMADD312SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9d /r] FMA,FUTURE,SQ +VFNMADD213SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ad /r] FMA,FUTURE,SD +VFNMADD213SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 ad /r] FMA,FUTURE,SD +VFNMADD213SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ad /r] FMA,FUTURE,SQ +VFNMADD213SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 ad /r] FMA,FUTURE,SQ +VFNMADD123SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 ad /r] FMA,FUTURE,SD +VFNMADD123SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 ad /r] FMA,FUTURE,SD +VFNMADD123SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 ad /r] FMA,FUTURE,SQ +VFNMADD123SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 ad /r] FMA,FUTURE,SQ +VFNMADD231SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bd /r] FMA,FUTURE,SD +VFNMADD231SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 bd /r] FMA,FUTURE,SD +VFNMADD231SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bd /r] FMA,FUTURE,SQ +VFNMADD231SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 bd /r] FMA,FUTURE,SQ +VFNMADD321SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bd /r] FMA,FUTURE,SD +VFNMADD321SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 bd /r] FMA,FUTURE,SD +VFNMADD321SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bd /r] FMA,FUTURE,SQ +VFNMADD321SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 bd /r] FMA,FUTURE,SQ +VFNMSUB132SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9f /r] FMA,FUTURE,SD +VFNMSUB132SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9f /r] FMA,FUTURE,SD +VFNMSUB132SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9f /r] FMA,FUTURE,SQ +VFNMSUB132SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9f /r] FMA,FUTURE,SQ +VFNMSUB312SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 9f /r] FMA,FUTURE,SD +VFNMSUB312SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 9f /r] FMA,FUTURE,SD +VFNMSUB312SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 9f /r] FMA,FUTURE,SQ +VFNMSUB312SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 9f /r] FMA,FUTURE,SQ +VFNMSUB213SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 af /r] FMA,FUTURE,SD +VFNMSUB213SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 af /r] FMA,FUTURE,SD +VFNMSUB213SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 af /r] FMA,FUTURE,SQ +VFNMSUB213SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 af /r] FMA,FUTURE,SQ +VFNMSUB123SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 af /r] FMA,FUTURE,SD +VFNMSUB123SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 af /r] FMA,FUTURE,SD +VFNMSUB123SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 af /r] FMA,FUTURE,SQ +VFNMSUB123SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 af /r] FMA,FUTURE,SQ +VFNMSUB231SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bf /r] FMA,FUTURE,SD +VFNMSUB231SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 bf /r] FMA,FUTURE,SD +VFNMSUB231SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bf /r] FMA,FUTURE,SQ +VFNMSUB231SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 bf /r] FMA,FUTURE,SQ +VFNMSUB321SS xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w0 bf /r] FMA,FUTURE,SD +VFNMSUB321SS xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w0 bf /r] FMA,FUTURE,SD +VFNMSUB321SD xmmreg,xmmreg,xmmrm [rvm: vex.dds.128.66.0f38.w1 bf /r] FMA,FUTURE,SQ +VFNMSUB321SD xmmreg,xmmrm [r+vm: vex.dds.128.66.0f38.w1 bf /r] FMA,FUTURE,SQ + +;# VIA (Centaur) security instructions +XSTORE void \3\x0F\xA7\xC0 PENT,CYRIX +XCRYPTECB void \336\3\x0F\xA7\xC8 PENT,CYRIX +XCRYPTCBC void \336\3\x0F\xA7\xD0 PENT,CYRIX +XCRYPTCTR void \336\3\x0F\xA7\xD8 PENT,CYRIX +XCRYPTCFB void \336\3\x0F\xA7\xE0 PENT,CYRIX +XCRYPTOFB void \336\3\x0F\xA7\xE8 PENT,CYRIX +MONTMUL void \336\3\x0F\xA6\xC0 PENT,CYRIX +XSHA1 void \336\3\x0F\xA6\xC8 PENT,CYRIX +XSHA256 void \336\3\x0F\xA6\xD0 PENT,CYRIX + +;# Systematic names for the hinting nop instructions +; These should be last in the file +HINT_NOP0 rm16 \320\2\x0F\x18\200 P6,UNDOC +HINT_NOP0 rm32 \321\2\x0F\x18\200 P6,UNDOC +HINT_NOP0 rm64 \324\2\x0F\x18\200 X64,UNDOC +HINT_NOP1 rm16 \320\2\x0F\x18\201 P6,UNDOC +HINT_NOP1 rm32 \321\2\x0F\x18\201 P6,UNDOC +HINT_NOP1 rm64 \324\2\x0F\x18\201 X64,UNDOC +HINT_NOP2 rm16 \320\2\x0F\x18\202 P6,UNDOC +HINT_NOP2 rm32 \321\2\x0F\x18\202 P6,UNDOC +HINT_NOP2 rm64 \324\2\x0F\x18\202 X64,UNDOC +HINT_NOP3 rm16 \320\2\x0F\x18\203 P6,UNDOC +HINT_NOP3 rm32 \321\2\x0F\x18\203 P6,UNDOC +HINT_NOP3 rm64 \324\2\x0F\x18\203 X64,UNDOC +HINT_NOP4 rm16 \320\2\x0F\x18\204 P6,UNDOC +HINT_NOP4 rm32 \321\2\x0F\x18\204 P6,UNDOC +HINT_NOP4 rm64 \324\2\x0F\x18\204 X64,UNDOC +HINT_NOP5 rm16 \320\2\x0F\x18\205 P6,UNDOC +HINT_NOP5 rm32 \321\2\x0F\x18\205 P6,UNDOC +HINT_NOP5 rm64 \324\2\x0F\x18\205 X64,UNDOC +HINT_NOP6 rm16 \320\2\x0F\x18\206 P6,UNDOC +HINT_NOP6 rm32 \321\2\x0F\x18\206 P6,UNDOC +HINT_NOP6 rm64 \324\2\x0F\x18\206 X64,UNDOC +HINT_NOP7 rm16 \320\2\x0F\x18\207 P6,UNDOC +HINT_NOP7 rm32 \321\2\x0F\x18\207 P6,UNDOC +HINT_NOP7 rm64 \324\2\x0F\x18\207 X64,UNDOC +HINT_NOP8 rm16 \320\2\x0F\x19\200 P6,UNDOC +HINT_NOP8 rm32 \321\2\x0F\x19\200 P6,UNDOC +HINT_NOP8 rm64 \324\2\x0F\x19\200 X64,UNDOC +HINT_NOP9 rm16 \320\2\x0F\x19\201 P6,UNDOC +HINT_NOP9 rm32 \321\2\x0F\x19\201 P6,UNDOC +HINT_NOP9 rm64 \324\2\x0F\x19\201 X64,UNDOC +HINT_NOP10 rm16 \320\2\x0F\x19\202 P6,UNDOC +HINT_NOP10 rm32 \321\2\x0F\x19\202 P6,UNDOC +HINT_NOP10 rm64 \324\2\x0F\x19\202 X64,UNDOC +HINT_NOP11 rm16 \320\2\x0F\x19\203 P6,UNDOC +HINT_NOP11 rm32 \321\2\x0F\x19\203 P6,UNDOC +HINT_NOP11 rm64 \324\2\x0F\x19\203 X64,UNDOC +HINT_NOP12 rm16 \320\2\x0F\x19\204 P6,UNDOC +HINT_NOP12 rm32 \321\2\x0F\x19\204 P6,UNDOC +HINT_NOP12 rm64 \324\2\x0F\x19\204 X64,UNDOC +HINT_NOP13 rm16 \320\2\x0F\x19\205 P6,UNDOC +HINT_NOP13 rm32 \321\2\x0F\x19\205 P6,UNDOC +HINT_NOP13 rm64 \324\2\x0F\x19\205 X64,UNDOC +HINT_NOP14 rm16 \320\2\x0F\x19\206 P6,UNDOC +HINT_NOP14 rm32 \321\2\x0F\x19\206 P6,UNDOC +HINT_NOP14 rm64 \324\2\x0F\x19\206 X64,UNDOC +HINT_NOP15 rm16 \320\2\x0F\x19\207 P6,UNDOC +HINT_NOP15 rm32 \321\2\x0F\x19\207 P6,UNDOC +HINT_NOP15 rm64 \324\2\x0F\x19\207 X64,UNDOC +HINT_NOP16 rm16 \320\2\x0F\x1A\200 P6,UNDOC +HINT_NOP16 rm32 \321\2\x0F\x1A\200 P6,UNDOC +HINT_NOP16 rm64 \324\2\x0F\x1A\200 X64,UNDOC +HINT_NOP17 rm16 \320\2\x0F\x1A\201 P6,UNDOC +HINT_NOP17 rm32 \321\2\x0F\x1A\201 P6,UNDOC +HINT_NOP17 rm64 \324\2\x0F\x1A\201 X64,UNDOC +HINT_NOP18 rm16 \320\2\x0F\x1A\202 P6,UNDOC +HINT_NOP18 rm32 \321\2\x0F\x1A\202 P6,UNDOC +HINT_NOP18 rm64 \324\2\x0F\x1A\202 X64,UNDOC +HINT_NOP19 rm16 \320\2\x0F\x1A\203 P6,UNDOC +HINT_NOP19 rm32 \321\2\x0F\x1A\203 P6,UNDOC +HINT_NOP19 rm64 \324\2\x0F\x1A\203 X64,UNDOC +HINT_NOP20 rm16 \320\2\x0F\x1A\204 P6,UNDOC +HINT_NOP20 rm32 \321\2\x0F\x1A\204 P6,UNDOC +HINT_NOP20 rm64 \324\2\x0F\x1A\204 X64,UNDOC +HINT_NOP21 rm16 \320\2\x0F\x1A\205 P6,UNDOC +HINT_NOP21 rm32 \321\2\x0F\x1A\205 P6,UNDOC +HINT_NOP21 rm64 \324\2\x0F\x1A\205 X64,UNDOC +HINT_NOP22 rm16 \320\2\x0F\x1A\206 P6,UNDOC +HINT_NOP22 rm32 \321\2\x0F\x1A\206 P6,UNDOC +HINT_NOP22 rm64 \324\2\x0F\x1A\206 X64,UNDOC +HINT_NOP23 rm16 \320\2\x0F\x1A\207 P6,UNDOC +HINT_NOP23 rm32 \321\2\x0F\x1A\207 P6,UNDOC +HINT_NOP23 rm64 \324\2\x0F\x1A\207 X64,UNDOC +HINT_NOP24 rm16 \320\2\x0F\x1B\200 P6,UNDOC +HINT_NOP24 rm32 \321\2\x0F\x1B\200 P6,UNDOC +HINT_NOP24 rm64 \324\2\x0F\x1B\200 X64,UNDOC +HINT_NOP25 rm16 \320\2\x0F\x1B\201 P6,UNDOC +HINT_NOP25 rm32 \321\2\x0F\x1B\201 P6,UNDOC +HINT_NOP25 rm64 \324\2\x0F\x1B\201 X64,UNDOC +HINT_NOP26 rm16 \320\2\x0F\x1B\202 P6,UNDOC +HINT_NOP26 rm32 \321\2\x0F\x1B\202 P6,UNDOC +HINT_NOP26 rm64 \324\2\x0F\x1B\202 X64,UNDOC +HINT_NOP27 rm16 \320\2\x0F\x1B\203 P6,UNDOC +HINT_NOP27 rm32 \321\2\x0F\x1B\203 P6,UNDOC +HINT_NOP27 rm64 \324\2\x0F\x1B\203 X64,UNDOC +HINT_NOP28 rm16 \320\2\x0F\x1B\204 P6,UNDOC +HINT_NOP28 rm32 \321\2\x0F\x1B\204 P6,UNDOC +HINT_NOP28 rm64 \324\2\x0F\x1B\204 X64,UNDOC +HINT_NOP29 rm16 \320\2\x0F\x1B\205 P6,UNDOC +HINT_NOP29 rm32 \321\2\x0F\x1B\205 P6,UNDOC +HINT_NOP29 rm64 \324\2\x0F\x1B\205 X64,UNDOC +HINT_NOP30 rm16 \320\2\x0F\x1B\206 P6,UNDOC +HINT_NOP30 rm32 \321\2\x0F\x1B\206 P6,UNDOC +HINT_NOP30 rm64 \324\2\x0F\x1B\206 X64,UNDOC +HINT_NOP31 rm16 \320\2\x0F\x1B\207 P6,UNDOC +HINT_NOP31 rm32 \321\2\x0F\x1B\207 P6,UNDOC +HINT_NOP31 rm64 \324\2\x0F\x1B\207 X64,UNDOC +HINT_NOP32 rm16 \320\2\x0F\x1C\200 P6,UNDOC +HINT_NOP32 rm32 \321\2\x0F\x1C\200 P6,UNDOC +HINT_NOP32 rm64 \324\2\x0F\x1C\200 X64,UNDOC +HINT_NOP33 rm16 \320\2\x0F\x1C\201 P6,UNDOC +HINT_NOP33 rm32 \321\2\x0F\x1C\201 P6,UNDOC +HINT_NOP33 rm64 \324\2\x0F\x1C\201 X64,UNDOC +HINT_NOP34 rm16 \320\2\x0F\x1C\202 P6,UNDOC +HINT_NOP34 rm32 \321\2\x0F\x1C\202 P6,UNDOC +HINT_NOP34 rm64 \324\2\x0F\x1C\202 X64,UNDOC +HINT_NOP35 rm16 \320\2\x0F\x1C\203 P6,UNDOC +HINT_NOP35 rm32 \321\2\x0F\x1C\203 P6,UNDOC +HINT_NOP35 rm64 \324\2\x0F\x1C\203 X64,UNDOC +HINT_NOP36 rm16 \320\2\x0F\x1C\204 P6,UNDOC +HINT_NOP36 rm32 \321\2\x0F\x1C\204 P6,UNDOC +HINT_NOP36 rm64 \324\2\x0F\x1C\204 X64,UNDOC +HINT_NOP37 rm16 \320\2\x0F\x1C\205 P6,UNDOC +HINT_NOP37 rm32 \321\2\x0F\x1C\205 P6,UNDOC +HINT_NOP37 rm64 \324\2\x0F\x1C\205 X64,UNDOC +HINT_NOP38 rm16 \320\2\x0F\x1C\206 P6,UNDOC +HINT_NOP38 rm32 \321\2\x0F\x1C\206 P6,UNDOC +HINT_NOP38 rm64 \324\2\x0F\x1C\206 X64,UNDOC +HINT_NOP39 rm16 \320\2\x0F\x1C\207 P6,UNDOC +HINT_NOP39 rm32 \321\2\x0F\x1C\207 P6,UNDOC +HINT_NOP39 rm64 \324\2\x0F\x1C\207 X64,UNDOC +HINT_NOP40 rm16 \320\2\x0F\x1D\200 P6,UNDOC +HINT_NOP40 rm32 \321\2\x0F\x1D\200 P6,UNDOC +HINT_NOP40 rm64 \324\2\x0F\x1D\200 X64,UNDOC +HINT_NOP41 rm16 \320\2\x0F\x1D\201 P6,UNDOC +HINT_NOP41 rm32 \321\2\x0F\x1D\201 P6,UNDOC +HINT_NOP41 rm64 \324\2\x0F\x1D\201 X64,UNDOC +HINT_NOP42 rm16 \320\2\x0F\x1D\202 P6,UNDOC +HINT_NOP42 rm32 \321\2\x0F\x1D\202 P6,UNDOC +HINT_NOP42 rm64 \324\2\x0F\x1D\202 X64,UNDOC +HINT_NOP43 rm16 \320\2\x0F\x1D\203 P6,UNDOC +HINT_NOP43 rm32 \321\2\x0F\x1D\203 P6,UNDOC +HINT_NOP43 rm64 \324\2\x0F\x1D\203 X64,UNDOC +HINT_NOP44 rm16 \320\2\x0F\x1D\204 P6,UNDOC +HINT_NOP44 rm32 \321\2\x0F\x1D\204 P6,UNDOC +HINT_NOP44 rm64 \324\2\x0F\x1D\204 X64,UNDOC +HINT_NOP45 rm16 \320\2\x0F\x1D\205 P6,UNDOC +HINT_NOP45 rm32 \321\2\x0F\x1D\205 P6,UNDOC +HINT_NOP45 rm64 \324\2\x0F\x1D\205 X64,UNDOC +HINT_NOP46 rm16 \320\2\x0F\x1D\206 P6,UNDOC +HINT_NOP46 rm32 \321\2\x0F\x1D\206 P6,UNDOC +HINT_NOP46 rm64 \324\2\x0F\x1D\206 X64,UNDOC +HINT_NOP47 rm16 \320\2\x0F\x1D\207 P6,UNDOC +HINT_NOP47 rm32 \321\2\x0F\x1D\207 P6,UNDOC +HINT_NOP47 rm64 \324\2\x0F\x1D\207 X64,UNDOC +HINT_NOP48 rm16 \320\2\x0F\x1E\200 P6,UNDOC +HINT_NOP48 rm32 \321\2\x0F\x1E\200 P6,UNDOC +HINT_NOP48 rm64 \324\2\x0F\x1E\200 X64,UNDOC +HINT_NOP49 rm16 \320\2\x0F\x1E\201 P6,UNDOC +HINT_NOP49 rm32 \321\2\x0F\x1E\201 P6,UNDOC +HINT_NOP49 rm64 \324\2\x0F\x1E\201 X64,UNDOC +HINT_NOP50 rm16 \320\2\x0F\x1E\202 P6,UNDOC +HINT_NOP50 rm32 \321\2\x0F\x1E\202 P6,UNDOC +HINT_NOP50 rm64 \324\2\x0F\x1E\202 X64,UNDOC +HINT_NOP51 rm16 \320\2\x0F\x1E\203 P6,UNDOC +HINT_NOP51 rm32 \321\2\x0F\x1E\203 P6,UNDOC +HINT_NOP51 rm64 \324\2\x0F\x1E\203 X64,UNDOC +HINT_NOP52 rm16 \320\2\x0F\x1E\204 P6,UNDOC +HINT_NOP52 rm32 \321\2\x0F\x1E\204 P6,UNDOC +HINT_NOP52 rm64 \324\2\x0F\x1E\204 X64,UNDOC +HINT_NOP53 rm16 \320\2\x0F\x1E\205 P6,UNDOC +HINT_NOP53 rm32 \321\2\x0F\x1E\205 P6,UNDOC +HINT_NOP53 rm64 \324\2\x0F\x1E\205 X64,UNDOC +HINT_NOP54 rm16 \320\2\x0F\x1E\206 P6,UNDOC +HINT_NOP54 rm32 \321\2\x0F\x1E\206 P6,UNDOC +HINT_NOP54 rm64 \324\2\x0F\x1E\206 X64,UNDOC +HINT_NOP55 rm16 \320\2\x0F\x1E\207 P6,UNDOC +HINT_NOP55 rm32 \321\2\x0F\x1E\207 P6,UNDOC +HINT_NOP55 rm64 \324\2\x0F\x1E\207 X64,UNDOC +HINT_NOP56 rm16 \320\2\x0F\x1F\200 P6,UNDOC +HINT_NOP56 rm32 \321\2\x0F\x1F\200 P6,UNDOC +HINT_NOP56 rm64 \324\2\x0F\x1F\200 X64,UNDOC +HINT_NOP57 rm16 \320\2\x0F\x1F\201 P6,UNDOC +HINT_NOP57 rm32 \321\2\x0F\x1F\201 P6,UNDOC +HINT_NOP57 rm64 \324\2\x0F\x1F\201 X64,UNDOC +HINT_NOP58 rm16 \320\2\x0F\x1F\202 P6,UNDOC +HINT_NOP58 rm32 \321\2\x0F\x1F\202 P6,UNDOC +HINT_NOP58 rm64 \324\2\x0F\x1F\202 X64,UNDOC +HINT_NOP59 rm16 \320\2\x0F\x1F\203 P6,UNDOC +HINT_NOP59 rm32 \321\2\x0F\x1F\203 P6,UNDOC +HINT_NOP59 rm64 \324\2\x0F\x1F\203 X64,UNDOC +HINT_NOP60 rm16 \320\2\x0F\x1F\204 P6,UNDOC +HINT_NOP60 rm32 \321\2\x0F\x1F\204 P6,UNDOC +HINT_NOP60 rm64 \324\2\x0F\x1F\204 X64,UNDOC +HINT_NOP61 rm16 \320\2\x0F\x1F\205 P6,UNDOC +HINT_NOP61 rm32 \321\2\x0F\x1F\205 P6,UNDOC +HINT_NOP61 rm64 \324\2\x0F\x1F\205 X64,UNDOC +HINT_NOP62 rm16 \320\2\x0F\x1F\206 P6,UNDOC +HINT_NOP62 rm32 \321\2\x0F\x1F\206 P6,UNDOC +HINT_NOP62 rm64 \324\2\x0F\x1F\206 X64,UNDOC +HINT_NOP63 rm16 \320\2\x0F\x1F\207 P6,UNDOC +HINT_NOP63 rm32 \321\2\x0F\x1F\207 P6,UNDOC +HINT_NOP63 rm64 \324\2\x0F\x1F\207 X64,UNDOC diff --git a/perl/insns.old.pl b/perl/insns.old.pl new file mode 100755 index 00000000..2f15e8b9 --- /dev/null +++ b/perl/insns.old.pl @@ -0,0 +1,1022 @@ +#!/usr/bin/perl +use lib 'lib'; +use warnings; +use strict; +# +# insns.pl produce insnsa.c, insnsd.c, insnsi.h, insnsn.c from insns.dat +# +# The Netwide Assembler is copyright (C) 1996 Simon Tatham and +# Julian Hall. All rights reserved. The software is +# redistributable under the license given in the file "LICENSE" +# distributed in the NASM archive. + +# Opcode prefixes which need their own opcode tables +# LONGER PREFIXES FIRST! +our @disasm_prefixes = qw(0F24 0F25 0F38 0F3A 0F7A 0FA6 0FA7 0F); + +# This should match MAX_OPERANDS from nasm.h +our $MAX_OPERANDS = 5; + +# Add VEX prefixes +our @vexlist; +for( my $m = 0; $m < 32; $m++ ){ + for( my $lp = 0; $lp < 8; $lp++ ){ + push(@vexlist, sprintf("VEX%02X%01X", $m, $lp)); + } +} +@disasm_prefixes = (@vexlist, @disasm_prefixes); + +our @bytecode_count = (0) x 256; + + +sub byte_code_compile($); +sub startseq($); +sub count_bytecodes(@); +sub format_insn(@); +sub codesubst($); +sub addprefix ($@); +sub hexstr(@); +sub decodify($); + + + +print STDERR "Reading insns.dat...\n"; + +our @args; +our $output; +for my $arg ( @ARGV ) { + if ( $arg =~ /^\-/ ) { + if ( $arg =~ /^\-([abdin])$/ ) { + $output = $1; + } else { + die "$0: Unknown option: ${arg}\n"; + } + } else { + push (@args, $arg); + } +} + +our $fname = "insns.dat" unless $fname = $args[0]; +open (F, $fname) || die "unable to open $fname"; + +our( %dinstables, @bytecode_list ); + +our $line = 0; +our $insns = 0; +our( %k_opcodes_cc, %k_opcodes, @big ); +while () { + $line++; + chomp; + next if ( /^\s*(\;.*|)$/ ); # comments or blank lines + + unless (/^\s*(\S+)\s+(\S+)\s+(\S+|\[.*\])\s+(\S+)\s*$/) { + warn "line $line does not contain four fields\n"; + next; + } + my @fields = ($1, $2, $3, $4); + my ($formatted, $nd) = format_insn(@fields); + if ($formatted) { + $insns++; + my $aname = "aa_$fields[0]"; + no strict 'refs'; + push @$aname, $formatted; + } + if ( $fields[0] =~ /cc$/ ) { + # Conditional instruction + $k_opcodes_cc{$fields[0]}++; + } else { + # Unconditional instruction + $k_opcodes{$fields[0]}++; + } + if ($formatted && !$nd) { + push @big, $formatted; + my @sseq = startseq($fields[2]); + for my $i (@sseq) { + if (!defined($dinstables{$i})) { + $dinstables{$i} = []; + } + push(@{$dinstables{$i}}, $#big); + } + } +} + +close F; + +# +# Generate the bytecode array. At this point, @bytecode_list contains +# the full set of bytecodes. +# + +# Sort by descending length +@bytecode_list = sort { scalar(@$b) <=> scalar(@$a) } @bytecode_list; + +our( @bytecode_array, %bytecode_pos ); +my $bytecode_next = 0; + +for my $bl (@bytecode_list) { + my $h = hexstr(@$bl); + next if (defined($bytecode_pos{$h})); + + push(@bytecode_array, $bl); + while ($h ne '') { + $bytecode_pos{$h} = $bytecode_next; + $h = substr($h, 2); + $bytecode_next++; + } +} +undef @bytecode_list; + +our @opcodes = sort keys(%k_opcodes); +our @opcodes_cc = sort keys(%k_opcodes_cc); + + + + + + +=comment +#include "nasm.h" +#include "insns.h" + +const uint8_t nasm_bytecodes[20479] = { + /* 0 */ 0324,0361,03,017,072,027,0101,026,0, + /* 9 */ 0324,0361,03,017,072,024,0101,026,0, + /* 18 */ 0324,0361,03,017,072,026,0101,026,0, + /* 27 */ 0324,0361,03,017,072,025,0101,026,0, + /* 36 */ 0324,0361,03,017,072,042,0110,026,0, + /* 45 */ 0160,03,017,045,054,0121,01,0,0, + /* 54 */ 0160,03,017,045,054,0121,01,01,0, + + + /* 20464 */ 01,0313,0, + /* 20467 */ 01,0326,0, + /* 20470 */ 01,0375,0, + /* 20473 */ 01,0373,0, + /* 20476 */ 01,0327,0, +}; + +/* + * Bytecode frequencies (including reuse): + * + * 0:3745 | 40: 4 | 100: 12 | 140: 1 | 200: 101 | 240: 0 | 300: 0 | 340: 1 + * 1:2848 | 41: 19 | 101: 280 | 141: 17 | 201: 71 | 241: 0 | 301: 0 | 341: 10 + * 2: 960 | 42: 8 | 102: 6 | 142: 2 | 202: 88 | 242: 0 | 302: 0 | 342: 0 + * 3: 446 | 43: 4 | 103: 0 | 143: 0 | 203: 75 | 243: 0 | 303: 0 | 343: 0 + * 4: 0 | 44: 4 | 104: 0 | 144: 1 | 204: 101 | 244: 0 | 304: 0 | 344: 2 + * 5: 0 | 45: 4 | 105: 0 | 145: 17 | 205: 72 | 245: 0 | 305: 0 | 345: 1 + * 6: 0 | 46: 0 | 106: 0 | 146: 2 | 206: 74 | 246: 0 | 306: 0 | 346: 1 + * 7: 0 | 47: 0 | 107: 0 | 147: 0 | 207: 71 | 247: 0 | 307: 0 | 347: 1 + * 10: 72 | 50: 28 | 110:1420 | 150: 2 | 210: 0 | 250: 1 | 310: 7 | 350: 0 + * 11: 26 | 51: 0 | 111: 0 | 151: 17 | 211: 0 | 251: 9 | 311: 7 | 351: 0 + * 12: 0 | 52: 0 | 112: 32 | 152: 2 | 212: 3 | 252: 2 | 312: 5 | 352: 0 + * 13: 0 | 53: 0 | 113: 0 | 153: 0 | 213: 1 | 253: 0 | 313: 6 | 353: 0 + * 14: 0 | 54: 0 | 114: 0 | 154: 3 | 214: 2 | 254: 0 | 314: 2 | 354: 0 + * 15: 6 | 55: 1 | 115: 0 | 155: 26 | 215: 0 | 255: 13 | 315: 0 | 355: 0 + * 16: 12 | 56: 0 | 116: 0 | 156: 4 | 216: 3 | 256: 0 | 316: 0 | 356: 0 + * 17: 0 | 57: 0 | 117: 0 | 157: 0 | 217: 1 | 257: 0 | 317: 0 | 357: 0 + * 20: 0 | 60: 4 | 120: 627 | 160: 204 | 220: 0 | 260: 619 | 320: 322 | 360: 198 + * 21: 40 | 61: 0 | 121: 184 | 161: 0 | 221: 0 | 261: 649 | 321: 325 | 361: 237 + * 22: 79 | 62: 4 | 122: 0 | 162: 0 | 222: 0 | 262: 0 | 322: 21 | 362: 44 + * 23: 44 | 63: 4 | 123: 20 | 163: 0 | 223: 0 | 263: 0 | 323: 113 | 363: 48 + * 24: 6 | 64: 20 | 124: 0 | 164: 52 | 224: 0 | 264: 0 | 324: 282 | 364: 0 + * 25: 67 | 65: 0 | 125: 0 | 165: 0 | 225: 0 | 265: 0 | 325: 0 | 365: 0 + * 26: 73 | 66: 0 | 126: 0 | 166: 0 | 226: 0 | 266: 0 | 326: 0 | 366: 0 + * 27: 1 | 67: 0 | 127: 0 | 167: 0 | 227: 0 | 267: 0 | 327: 0 | 367: 0 + * 30: 14 | 70: 0 | 130: 16 | 170: 0 | 230: 0 | 270: 177 | 330: 16 | 370: 1 + * 31: 19 | 71: 0 | 131: 0 | 171: 0 | 231: 0 | 271: 0 | 331: 0 | 371: 1 + * 32: 2 | 72: 0 | 132: 20 | 172: 8 | 232: 0 | 272: 0 | 332: 5 | 372: 0 + * 33: 0 | 73: 0 | 133: 0 | 173: 24 | 233: 0 | 273: 0 | 333: 7 | 373: 1 + * 34: 6 | 74: 6 | 134: 0 | 174: 6 | 234: 0 | 274: 1 | 334: 2 | 374: 0 + * 35: 2 | 75: 0 | 135: 0 | 175: 0 | 235: 0 | 275: 48 | 335: 8 | 375: 0 + * 36: 0 | 76: 0 | 136: 0 | 176: 0 | 236: 0 | 276: 0 | 336: 8 | 376: 0 + * 37: 0 | 77: 0 | 137: 0 | 177: 0 | 237: 0 | 277: 0 | 337: 0 | 377: 0 + */ + +=requires + +@bytecode_array +$bytecode_next +@bytecode_count + +=cut +if ( !defined($output) || $output eq 'b') { + print STDERR "Writing insnsb.c...\n"; + + open B, ">insnsb.c"; + + print B "/* This file auto-generated from insns.dat by insns.pl" . + " - don't edit it */\n\n"; + + print B "#include \"nasm.h\"\n"; + print B "#include \"insns.h\"\n\n"; + + print B "const uint8_t nasm_bytecodes[$bytecode_next] = {\n"; + + my $p = 0; + for my $bl (@bytecode_array) { + printf B " /* %5d */ ", $p; + for my $d (@$bl) { + printf B "%#o,", $d; + $p++; + } + printf B "\n"; + } + print B "};\n"; + + print B "\n"; + print B "/*\n"; + print B " * Bytecode frequencies (including reuse):\n"; + print B " *\n"; + for( my $i = 0; $i < 32; $i++) { + print B " *"; + for ( my $j = 0; $j < 256; $j += 32) { + print B " |" if ($j); + printf B " %3o:%4d", $i+$j, $bytecode_count[$i+$j]; + } + print B "\n"; + } + print B " */\n"; + + close B; +} + + + +=requires + +@opcodes +@opcodes_cc + +aa_* + +=cut +if ( !defined($output) || $output eq 'a' ) { + print STDERR "Writing insnsa.c...\n"; + + open A, ">insnsa.c"; + + print A "/* This file auto-generated from insns.dat by insns.pl" . + " - don't edit it */\n\n"; + + print A "#include \"nasm.h\"\n"; + print A "#include \"insns.h\"\n\n"; + + for my $i (@opcodes, @opcodes_cc) { + print A "static const struct itemplate instrux_${i}[] = {\n"; + my $aname = "aa_$i"; + no strict 'refs'; + for my $j (@$aname) { + print A " ", codesubst($j), "\n"; + } + print A " ITEMPLATE_END\n};\n\n"; + } + print A "const struct itemplate * const nasm_instructions[] = {\n"; + for my $i (@opcodes, @opcodes_cc) { + print A " instrux_${i},\n"; + } + print A "};\n"; + + close A; +} + + + + + + +=requires + +@opcodes +@opcodes_cc +%dinstables +@disasm_prefixes + +=creates + +%is_prefix +@prefix_list + +=cut +if ( !defined($output) || $output eq 'd' ) { + print STDERR "Writing insnsd.c...\n"; + + open D, ">insnsd.c"; + + print D "/* This file auto-generated from insns.dat by insns.pl" . + " - don't edit it */\n\n"; + + print D "#include \"nasm.h\"\n"; + print D "#include \"insns.h\"\n\n"; + + print D "static const struct itemplate instrux[] = {\n"; + my $n = 0; + for my $j (@big) { + printf D " /* %4d */ %s\n", $n++, codesubst($j); + } + print D "};\n"; + + for my $h (sort(keys(%dinstables))) { + next if ($h eq ''); # Skip pseudo-instructions + print D "\nstatic const struct itemplate * const itable_${h}[] = {\n"; + for my $j (@{$dinstables{$h}}) { + print D " instrux + $j,\n"; + } + print D "};\n"; + } + + my %is_prefix; + my @prefix_list; + + for my $h (@disasm_prefixes, '' ){ + for( my $c = 0; $c < 256; $c++ ){ + my $nn = sprintf("%s%02X", $h, $c); + if ($is_prefix{$nn} || defined($dinstables{$nn})) { + # At least one entry in this prefix table + push(@prefix_list, $h); + $is_prefix{$h} = 1; + last; + } + } + } + + for my $h (@prefix_list) { + print D "\n"; + print D "static " unless ($h eq ''); + print D "const struct disasm_index "; + print D ($h eq '') ? 'itable' : "itable_$h"; + print D "[256] = {\n"; + for( my $c = 0; $c < 256; $c++ ){ + my $nn = sprintf("%s%02X", $h, $c); + if ($is_prefix{$nn}) { + die "$fname: ambiguous decoding of $nn\n" + if (defined($dinstables{$nn})); + printf D " { itable_%s, -1 },\n", $nn; + } elsif (defined($dinstables{$nn})) { + printf D " { itable_%s, %u },\n", + $nn, scalar(@{$dinstables{$nn}}); + } else { + printf D " { NULL, 0 },\n"; + } + } + print D "};\n"; + } + + print D "\nconst struct disasm_index * const itable_VEX[32][8] = {\n "; + for( my $m = 0; $m < 32; $m++ ){ + print D " {\n"; + for( my $lp = 0; $lp < 8; $lp++ ){ + my $vp = sprintf("VEX%02X%01X", $m, $lp); + if ($is_prefix{$vp}) { + printf D " itable_%s,\n", $vp; + } else { + print D " NULL,\n"; + } + } + print D " },"; + } + print D "\n};\n"; + + close D; +} + + + + + +=comment + +/* This file in included by nasm.h */ + +/* Instruction names */ + +#ifndef NASM_INSNSI_H +#define NASM_INSNSI_H 1 + +enum opcode { + I_AAA, + I_AAD, + I_AAM, + I_AAS, + I_ADC, + I_ADD, + I_ADDPD, + I_ADDPS, + I_ADDSD, + + + I_XSAVE, + I_XSETBV, + I_XSHA1, + I_XSHA256, + I_XSTORE, + I_CMOVcc, + I_Jcc, + I_SETcc, + I_none = -1 + +}; + +#define MAX_INSLEN 16 +#define FIRST_COND_OPCODE I_CMOVcc + +#endif /* NASM_INSNSI_H */ + +=requires + +@opcodes +@opcodes_cc + +=cut +if ( !defined($output) || $output eq 'i' ) { + print STDERR "Writing insnsi.h...\n"; + + open I, ">insnsi.h"; + + print I "/* This file is auto-generated from insns.dat by insns.pl" . + " - don't edit it */\n\n"; + print I "/* This file in included by nasm.h */\n\n"; + + print I "/* Instruction names */\n\n"; + print I "#ifndef NASM_INSNSI_H\n"; + print I "#define NASM_INSNSI_H 1\n\n"; + print I "enum opcode {\n"; + my $maxlen = 0; + for my $i (@opcodes, @opcodes_cc) { + print I "\tI_${i},\n"; + my $len = length($i); + $len++ if ( $i =~ /cc$/ ); # Condition codes can be 3 characters long + $maxlen = $len if ( $len > $maxlen ); + } + print I "\tI_none = -1\n"; + print I "\n};\n\n"; + print I "#define MAX_INSLEN ", $maxlen, "\n"; + print I "#define FIRST_COND_OPCODE I_", $opcodes_cc[0], "\n\n"; + print I "#endif /* NASM_INSNSI_H */\n"; + + close I; +} + + + + + + + + +=comment insnsn.c + +#include "tables.h" + +const char * const nasm_insn_names[] = { + "aaa", + "aad", + "aam", + "aas", + "adc", + "add", + "addpd", + + "xsha256", + "xstore", + "cmov", + "j", + "set" +}; + +=requires + +@opcodes +@opcodes_cc + +=cut +if ( !defined($output) || $output eq 'n' ) { + print STDERR "Writing insnsn.c...\n"; + + open N, ">insnsn.c"; + + print N "/* This file is auto-generated from insns.dat by insns.pl" . + " - don't edit it */\n\n"; + print N "#include \"tables.h\"\n\n"; + + print N "const char * const nasm_insn_names[] = {"; + my $first = 1; + for my $i (@opcodes, @opcodes_cc) { + print N "," if ( !$first ); + $first = 0; + my $ilower = $i; + $ilower =~ s/cc$//; # Remove conditional cc suffix + $ilower =~ tr/A-Z/a-z/; # Change to lower case (Perl 4 compatible) + print N "\n\t\"${ilower}\""; + } + print N "\n};\n"; + close N; +} + + +use strict; +use warnings; +printf STDERR "Done: %d instructions\n", $insns; + +# Count primary bytecodes, for statistics +sub count_bytecodes(@) { + my $skip = 0; + for my $bc (@_) { + if ($skip) { + $skip--; + next; + } + $bytecode_count[$bc]++; + if ($bc >= 01 && $bc <= 04) { + $skip = $bc; + } elsif (($bc & ~03) == 010) { + $skip = 1; + } elsif (($bc & ~013) == 0144) { + $skip = 1; + } elsif ($bc == 0172) { + $skip = 1; + } elsif ($bc >= 0260 && $bc <= 0270) { + $skip = 2; + } elsif ($bc == 0330) { + $skip = 1; + } + } +} + +sub format_insn(@) { + my ($opcode, $operands, $codes, $flags) = @_; + my( $num, $nd ) ; + my @bytecode; + + return (undef, undef) if $operands eq "ignore"; + + # format the operands + $operands =~ s/:/|colon,/g; + $operands =~ s/mem(\d+)/mem|bits$1/g; + $operands =~ s/mem/memory/g; + $operands =~ s/memory_offs/mem_offs/g; + $operands =~ s/imm(\d+)/imm|bits$1/g; + $operands =~ s/imm/immediate/g; + $operands =~ s/rm(\d+)/rm_gpr|bits$1/g; + $operands =~ s/(mmx|xmm|ymm)rm/rm_$1/g; + $operands =~ s/\=([0-9]+)/same_as|$1/g; + my @ops; + if ($operands eq 'void') { + @ops = (); + } else { + @ops = split(/\,/, $operands); + } + $num = scalar(@ops); + while (scalar(@ops) < $MAX_OPERANDS) { + push(@ops, '0'); + } + $operands = join(',', @ops); + $operands =~ tr/a-z/A-Z/; + + # format the flags + $flags =~ s/,/|IF_/g; + $flags =~ s/(\|IF_ND|IF_ND\|)//, $nd = 1 if $flags =~ /IF_ND/; + $flags = "IF_" . $flags; + + @bytecode = (decodify($codes), 0); + push(@bytecode_list, [@bytecode]); + $codes = hexstr(@bytecode); + count_bytecodes(@bytecode); + + ("{I_$opcode, $num, {$operands}, \@\@CODES-$codes\@\@, $flags},", $nd); +} + +# +# Look for @@CODES-xxx@@ sequences and replace them with the appropriate +# offset into nasm_bytecodes +# +sub codesubst($) { + my($s) = @_; + my $n; + + while ($s =~ /\@\@CODES-([0-9A-F]+)\@\@/) { + my $pos = $bytecode_pos{$1}; + if (!defined($pos)) { + die "$fname: no position assigned to byte code $1\n"; + } + $s = $` . "nasm_bytecodes+${pos}" . "$'"; + } + return $s; +} + +sub addprefix ($@) { + my ($prefix, @list) = @_; + my @return = map { + sprintf("%s%02X", $prefix, $_) + } @list; + + return @return; +} + +# +# Turn a code string into a sequence of bytes +# +sub decodify($) { + # Although these are C-syntax strings, by convention they should have + # only octal escapes (for directives) and hexadecimal escapes + # (for verbatim bytes) + my($codestr) = @_; + + if ($codestr =~ /^\s*\[([^\]]*)\]\s*$/) { + return byte_code_compile($1); + } + + my $c = $codestr; + my @codes = (); + + while ($c ne '') { + if ($c =~ /^\\x([0-9a-f]+)(.*)$/i) { + push(@codes, hex $1); + $c = $2; + next; + } elsif ($c =~ /^\\([0-7]{1,3})(.*)$/) { + push(@codes, oct $1); + $c = $2; + next; + } else { + die "$fname: unknown code format in \"$codestr\"\n"; + } + } + + return @codes; +} + +# Turn a numeric list into a hex string +sub hexstr(@) { + use Nasm::Utils qw'str2hex'; + return scalar str2hex @_; +} + +# Here we determine the range of possible starting bytes for a given +# instruction. We need only consider the codes: +# \[1234] mean literal bytes, of course +# \1[0123] mean byte plus register value +# \330 means byte plus condition code +# \0 or \340 mean give up and return empty set +# \34[4567] mean PUSH/POP of segment registers: special case +# \17[234] skip is4 control byte +# \26x \270 skip VEX control bytes +sub startseq($) { + my ($codestr) = @_; + my( $word, @range); + my @codes; + my $c = $codestr; + my( $c0, $c1, $i ); + my $prefix = ''; + + @codes = decodify($codestr); + + while ($c0 = shift(@codes)) { + $c1 = $codes[0]; + + if ($c0 >= 01 && $c0 <= 04) { + # Fixed byte string + my $fbs = $prefix; + + while (1) { + no warnings 'uninitialized'; + if ($c0 >= 01 && $c0 <= 04) { + while ($c0--) { + $fbs .= sprintf("%02X", shift(@codes)); + } + } else { + last; + } + $c0 = shift(@codes); + } + + for my $pfx (@disasm_prefixes) { + if (substr($fbs, 0, length($pfx)) eq $pfx) { + $prefix = $pfx; + $fbs = substr($fbs, length($pfx)); + last; + } + } + + if ($fbs ne '') { + return ($prefix.substr($fbs,0,2)); + } + + unshift(@codes, $c0); + } elsif ($c0 >= 010 && $c0 <= 013) { + return addprefix($prefix, $c1..($c1+7)); + } elsif (($c0 & ~013) == 0144) { + return addprefix($prefix, $c1, $c1|2); + } elsif ($c0 == 0330) { + return addprefix($prefix, $c1..($c1+15)); + } elsif ($c0 == 0 || $c0 == 0340) { + return $prefix; + } elsif ($c0 == 0344) { + return addprefix($prefix, 0x06, 0x0E, 0x16, 0x1E); + } elsif ($c0 == 0345) { + return addprefix($prefix, 0x07, 0x17, 0x1F); + } elsif ($c0 == 0346) { + return addprefix($prefix, 0xA0, 0xA8); + } elsif ($c0 == 0347) { + return addprefix($prefix, 0xA1, 0xA9); + } elsif (($c0 & ~3) == 0260 || $c0 == 0270) { + my( $m,$wlp,$vxp ); + $m = shift(@codes); + $wlp = shift(@codes); + $prefix .= sprintf('VEX%02X%01X', $m, $wlp & 7); + } elsif ($c0 >= 0172 && $c0 <= 174) { + shift(@codes); # Skip is4 control byte + } else { + # We really need to be able to distinguish "forbidden" + # and "ignorable" codes here + } + } + return $prefix; +} + +# +# This function takes a series of byte codes in a format which is more +# typical of the Intel documentation, and encode it. +# +# The format looks like: +# +# [operands: opcodes] +# +# The operands word lists the order of the operands: +# +# r = register field in the modr/m +# m = modr/m +# v = VEX "v" field +# d = DREX "dst" field +# i = immediate +# s = register field of is4/imz2 field +# - = implicit (unencoded) operand +# +# For an operand that should be filled into more than one field, +# enter it as e.g. "r+v". +# +sub byte_code_compile($) { + my($str) = @_; + my $opr; + my $opc; + my @codes = (); + my $litix = undef; + my %oppos = (); + my $i; + my( $op, $oq); + my $opex; + + unless ($str =~ /^(([^\s:]*)\:|)\s*(.*\S)\s*$/) { + die "$fname: $line: cannot parse: [$str]\n"; + } + $opr = "\L$2"; + $opc = "\L$3"; + + $op = 0; + for ($i = 0; $i < length($opr); $i++) { + my $c = substr($opr,$i,1); + if ($c eq '+') { + $op--; + } else { + $oppos{$c} = $op++; + } + } + my $s_pos; + + my $prefix_ok = 1; + for my $op (split(/\s*(?:\s|(?=[\/\\]))/, $opc)) { + if ($op eq 'o16') { + push(@codes, 0320); + } elsif ($op eq 'o32') { + push(@codes, 0321); + } elsif ($op eq 'o64') { # 64-bit operand size requiring REX.W + push(@codes, 0324); + } elsif ($op eq 'o64nw') { # Implied 64-bit operand size (no REX.W) + push(@codes, 0323); + } elsif ($op eq 'a16') { + push(@codes, 0310); + } elsif ($op eq 'a32') { + push(@codes, 0311); + } elsif ($op eq 'a64') { + push(@codes, 0313); + } elsif ($op eq '!osp') { + push(@codes, 0364); + } elsif ($op eq '!asp') { + push(@codes, 0365); + } elsif ($op eq 'rex.l') { + push(@codes, 0334); + } elsif ($op eq 'repe') { + push(@codes, 0335); + } elsif ($prefix_ok && $op =~ /^(66|f2|f3|np)$/) { + # 66/F2/F3 prefix used as an opcode extension, or np = no prefix + if ($op eq '66') { + push(@codes, 0361); + } elsif ($op eq 'f2') { + push(@codes, 0362); + } elsif ($op eq 'f3') { + push(@codes, 0363); + } else { + push(@codes, 0360); + } + } elsif ($op =~ /^[0-9a-f]{2}$/) { + if (defined($litix) && $litix+$codes[$litix]+1 == scalar @codes && + $codes[$litix] < 4) { + $codes[$litix]++; + push(@codes, hex $op); + } else { + $litix = scalar(@codes); + push(@codes, 01, hex $op); + } + $prefix_ok = 0; + } elsif ($op eq '/r') { + if (!defined($oppos{'r'}) || !defined($oppos{'m'})) { + die "$fname: $line: $op requires r and m operands\n"; + } + $opex = (($oppos{'m'} & 4) ? 06 : 0) | + (($oppos{'r'} & 4) ? 05 : 0); + push(@codes, $opex) if ($opex); + push(@codes, 0100 + (($oppos{'m'} & 3) << 3) + ($oppos{'r'} & 3)); + $prefix_ok = 0; + } elsif ($op =~ m:^/([0-7])$:) { + if (!defined($oppos{'m'})) { + die "$fname: $line: $op requires m operand\n"; + } + push(@codes, 06) if ($oppos{'m'} & 4); + push(@codes, 0200 + (($oppos{'m'} & 3) << 3) + $1); + $prefix_ok = 0; + } elsif ($op =~ /^vex(|\..*)$/) { + my ($m,$w,$l,$p) = (undef,2,undef,0); + my $has_nds = 0; + for my $oq (split(/\./, $op)) { + if ($oq eq 'vex') { + # prefix + } elsif ($oq eq '128' || $oq eq 'l0') { + $l = 0; + } elsif ($oq eq '256' || $oq eq 'l1') { + $l = 1; + } elsif ($oq eq 'w0') { + $w = 0; + } elsif ($oq eq 'w1') { + $w = 1; + } elsif ($oq eq 'wx') { + $w = 2; + } elsif ($oq eq 'ww') { + $w = 3; + } elsif ($oq eq '66') { + $p = 1; + } elsif ($oq eq 'f3') { + $p = 2; + } elsif ($oq eq 'f2') { + $p = 3; + } elsif ($oq eq '0f') { + $m = 1; + } elsif ($oq eq '0f38') { + $m = 2; + } elsif ($oq eq '0f3a') { + $m = 3; + } elsif ($oq =~ /^m([0-9]+)$/) { + $m = $1+0; + } elsif ($oq eq 'nds' || $oq eq 'ndd' || $oq eq 'dds') { + if (!defined($oppos{'v'})) { + die "$fname: $line: vex.$oq without 'v' operand\n"; + } + $has_nds = 1; + } else { + die "$fname: $line: undefined VEX subcode: $oq\n"; + } + } + if (!defined($m) || !defined($w) || !defined($l) || !defined($p)) { + die "$fname: $line: missing fields in VEX specification\n"; + } + if (defined($oppos{'v'}) && !$has_nds) { + die "$fname: $line: 'v' operand without vex.nds or vex.ndd\n"; + } + push(@codes, defined($oppos{'v'}) ? 0260+($oppos{'v'} & 3) : 0270, + $m, ($w << 3)+($l << 2)+$p); + $prefix_ok = 0; + } elsif ($op =~ /^\/drex([01])$/) { + my $oc0 = $1; + if (!defined($oppos{'d'})) { + die "$fname: $line: DREX without a 'd' operand\n"; + } + # Note the use of *unshift* here, as opposed to *push*. + # This is because NASM want this byte code at the start of + # the instruction sequence, but the AMD documentation puts + # this at (roughly) the position of the drex byte itself. + # This allows us to match the AMD documentation and still + # do the right thing. + unshift(@codes, 0160+($oppos{'d'} & 3)+($oc0 ? 4 : 0)); + unshift(@codes, 05) if ($oppos{'d'} & 4); + } elsif ($op =~ /^(ib\,s|ib|ibx|ib\,w|iw|iwd|id|idx|iwdq|rel|rel8|rel16|rel32|iq|seg|ibw|ibd|ibd,s)$/) { + if (!defined($oppos{'i'})) { + die "$fname: $line: $op without 'i' operand\n"; + } + if ($op eq 'ib,s') { # Signed imm8 + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 014+($oppos{'i'} & 3)); + } elsif ($op eq 'ib') { # imm8 + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 020+($oppos{'i'} & 3)); + } elsif ($op eq 'ib,u') { # Unsigned imm8 + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 024+($oppos{'i'} & 3)); + } elsif ($op eq 'iw') { # imm16 + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 030+($oppos{'i'} & 3)); + } elsif ($op eq 'ibx') { # imm8 sign-extended to opsize + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 0274+($oppos{'i'} & 3)); + } elsif ($op eq 'iwd') { # imm16 or imm32, depending on opsize + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 034+($oppos{'i'} & 3)); + } elsif ($op eq 'id') { # imm32 + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 040+($oppos{'i'} & 3)); + } elsif ($op eq 'idx') { # imm32 extended to 64 bits + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 0254+($oppos{'i'} & 3)); + } elsif ($op eq 'iwdq') { # imm16/32/64, depending on opsize + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 044+($oppos{'i'} & 3)); + } elsif ($op eq 'rel8') { + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 050+($oppos{'i'} & 3)); + } elsif ($op eq 'iq') { + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 054+($oppos{'i'} & 3)); + } elsif ($op eq 'rel16') { + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 060+($oppos{'i'} & 3)); + } elsif ($op eq 'rel') { # 16 or 32 bit relative operand + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 064+($oppos{'i'} & 3)); + } elsif ($op eq 'rel32') { + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 070+($oppos{'i'} & 3)); + } elsif ($op eq 'seg') { + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 074+($oppos{'i'} & 3)); + } elsif ($op eq 'ibw') { # imm16 that can be bytified + if (!defined($s_pos)) { + die "$fname: $line: $op without a +s byte\n"; + } + $codes[$s_pos] += 0144; + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 0140+($oppos{'i'} & 3)); + } elsif ($op eq 'ibd') { # imm32 that can be bytified + if (!defined($s_pos)) { + die "$fname: $line: $op without a +s byte\n"; + } + $codes[$s_pos] += 0154; + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 0150+($oppos{'i'} & 3)); + } elsif ($op eq 'ibd,s') { + # imm32 that can be bytified, sign extended to 64 bits + if (!defined($s_pos)) { + die "$fname: $line: $op without a +s byte\n"; + } + $codes[$s_pos] += 0154; + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, 0250+($oppos{'i'} & 3)); + } + $prefix_ok = 0; + } elsif ($op eq '/is4') { + if (!defined($oppos{'s'})) { + die "$fname: $line: $op without 's' operand\n"; + } + if (defined($oppos{'i'})) { + push(@codes, 0172, ($oppos{'s'} << 3)+$oppos{'i'}); + } else { + push(@codes, 0174, $oppos{'s'}); + } + $prefix_ok = 0; + } elsif ($op =~ /^\/is4\=([0-9]+)$/) { + my $imm = $1; + if (!defined($oppos{'s'})) { + die "$fname: $line: $op without 's' operand\n"; + } + if ($imm < 0 || $imm > 15) { + die "$fname: $line: invalid imm4 value for $op: $imm\n"; + } + push(@codes, 0173, ($oppos{'s'} << 4) + $imm); + $prefix_ok = 0; + } elsif ($op =~ /^([0-9a-f]{2})\+s$/) { + if (!defined($oppos{'i'})) { + die "$fname: $line: $op without 'i' operand\n"; + } + $s_pos = scalar @codes; + push(@codes, 05) if ($oppos{'i'} & 4); + push(@codes, $oppos{'i'} & 3, hex $1); + $prefix_ok = 0; + } elsif ($op =~ /^([0-9a-f]{2})\+c$/) { + push(@codes, 0330, hex $1); + $prefix_ok = 0; + } elsif ($op =~ /^\\([0-7]+|x[0-9a-f]{2})$/) { + # Escape to enter literal bytecodes + push(@codes, oct $1); + } else { + die "$fname: $line: unknown operation: $op\n"; + } + } + + return @codes; +} diff --git a/perl/insns.pl b/perl/insns.pl new file mode 100755 index 00000000..53edf2a8 --- /dev/null +++ b/perl/insns.pl @@ -0,0 +1,14 @@ +#! /usr/bin/env perl +use strict; +use warnings; +use lib qw'lib'; + +use Nasm::insns; + +my $self = Nasm::insns->new('insns.dat'); +__END__ +use Data::Dump 'dump'; + +use 5.010; + +say dump $self; diff --git a/perl/lib/Nasm/insns.pm b/perl/lib/Nasm/insns.pm index b4845906..563b4fca 100644 --- a/perl/lib/Nasm/insns.pm +++ b/perl/lib/Nasm/insns.pm @@ -17,9 +17,9 @@ our $MAX_OPERANDS = 5; # Add VEX prefixes our @vexlist; for( my $m = 0; $m < 32; $m++ ){ - for( my $lp = 0; $lp < 8; $lp++ ){ - push(@vexlist, sprintf("VEX%02X%01X", $m, $lp)); - } + for( my $lp = 0; $lp < 8; $lp++ ){ + push(@vexlist, sprintf("VEX%02X%01X", $m, $lp)); + } } @disasm_prefixes = (@vexlist, @disasm_prefixes); diff --git a/perl/lib/Nasm/insns/Flags.pm b/perl/lib/Nasm/insns/Flags.pm index 9a7ad9c4..fa8ca5c6 100644 --- a/perl/lib/Nasm/insns/Flags.pm +++ b/perl/lib/Nasm/insns/Flags.pm @@ -34,8 +34,8 @@ our( %map2id, %also_enable, @arch); close $data; } - use Data::Dump 'dump'; - use 5.010; + #use Data::Dump 'dump'; + #use 5.010; use Scalar::Util qw'reftype'; my $dir = Load $yaml_streams[0]; @@ -54,8 +54,10 @@ our( %map2id, %also_enable, @arch); my $reftype = reftype $ref; my %type_map = ( - HASH => '%', - ARRAY => '@' + HASH => '%', + ARRAY => '@', + SCALAR => '$', + REF => '$' ); $type ||= $type_map{$reftype}; @@ -66,6 +68,8 @@ our( %map2id, %also_enable, @arch); }elsif( $type eq '@' ){ die unless $reftype eq 'ARRAY'; @{*$variable_name} = @$ref; + }elsif( $type eq '$' ){ + ${*$variable_name} = $ref; } } } -- 2.11.4.GIT