From 09f6acbb75d7f58aa78691844620b85b6c44919b Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Tue, 30 Apr 2002 21:05:55 +0000 Subject: [PATCH] NASM 0.98.21 --- assemble.c | 3 ++- insns.dat | 28 ++++++++++------------------ nasm.h | 4 +--- parser.c | 3 +-- 4 files changed, 14 insertions(+), 24 deletions(-) diff --git a/assemble.c b/assemble.c index f560112e..ff308f61 100644 --- a/assemble.c +++ b/assemble.c @@ -552,7 +552,8 @@ static int is_sbyte (insn *ins, int op, int size) int ret; ret = !(ins->forw_ref && ins->oprs[op].opflags ) && /* dead in the water on forward reference or External */ - (optimizing>0 || !(ins->oprs[op].type & (BITS16|BITS32))) && + optimizing>=0 && +/* !(ins->oprs[op].type & (BITS16|BITS32)) && */ ins->oprs[op].wrt==NO_SEG && ins->oprs[op].segment==NO_SEG; v = ins->oprs[op].offset; diff --git a/insns.dat b/insns.dat index d626fcd6..ca6c3b98 100644 --- a/insns.dat +++ b/insns.dat @@ -38,8 +38,7 @@ ADC rm32,imm8 \321\300\1\x83\202\15 386 ADC reg_al,imm \1\x14\21 8086,SM ADC reg_ax,imm \320\1\x15\31 8086,SM ADC reg_eax,sbyte \321\1\x83\202\15 386,SM,ND -ADC reg_eax,sbig \321\1\x15\41 386,SM,ND -ADC reg_eax,imm32 \321\1\x15\41 386 +ADC reg_eax,imm \321\1\x15\41 386,SM ADC rm8,imm \300\1\x80\202\21 8086,SM ADC rm16,imm \320\300\134\1\x81\202\131 8086,SM ADC rm32,imm \321\300\144\1\x81\202\141 386,SM @@ -63,8 +62,7 @@ ADD rm32,imm8 \321\300\1\x83\200\15 386 ADD reg_al,imm \1\x04\21 8086,SM ADD reg_ax,imm \320\1\x05\31 8086,SM ADD reg_eax,sbyte \321\1\x83\200\15 386,SM,ND -ADD reg_eax,sbig \321\1\x05\41 386,SM,ND -ADD reg_eax,imm32 \321\1\x05\41 386 +ADD reg_eax,imm \321\1\x05\41 386,SM ADD rm8,imm \300\1\x80\200\21 8086,SM ADD rm16,imm \320\300\134\1\x81\200\131 8086,SM ADD rm32,imm \321\300\144\1\x81\200\141 386,SM @@ -88,8 +86,7 @@ AND rm32,imm8 \321\300\1\x83\204\15 386 AND reg_al,imm \1\x24\21 8086,SM AND reg_ax,imm \320\1\x25\31 8086,SM AND reg_eax,sbyte \321\1\x83\204\15 386,SM,ND -AND reg_eax,sbig \321\1\x25\41 386,SM,ND -AND reg_eax,imm32 \321\1\x25\41 386 +AND reg_eax,imm \321\1\x25\41 386,SM AND rm8,imm \300\1\x80\204\21 8086,SM AND rm16,imm \320\300\134\1\x81\204\131 8086,SM AND rm32,imm \321\300\144\1\x81\204\141 386,SM @@ -182,8 +179,7 @@ CMP rm32,imm8 \321\300\1\x83\207\15 386 CMP reg_al,imm \1\x3C\21 8086,SM CMP reg_ax,imm \320\1\x3D\31 8086,SM CMP reg_eax,sbyte \321\1\x83\207\15 386,SM,ND -CMP reg_eax,sbig \321\1\x3D\41 386,SM,ND -CMP reg_eax,imm32 \321\1\x3D\41 386 +CMP reg_eax,imm \321\1\x3D\41 386,SM CMP rm8,imm \300\1\x80\207\21 8086,SM CMP rm16,imm \320\300\134\1\x81\207\131 8086,SM CMP rm32,imm \321\300\144\1\x81\207\141 386,SM @@ -654,8 +650,7 @@ OR rm32,imm8 \321\300\1\x83\201\15 386 OR reg_al,imm \1\x0C\21 8086,SM OR reg_ax,imm \320\1\x0D\31 8086,SM OR reg_eax,sbyte \321\1\x83\201\15 386,SM,ND -OR reg_eax,sbig \321\1\x0D\41 386,SM,ND -OR reg_eax,imm32 \321\1\x0D\41 386 +OR reg_eax,imm \321\1\x0D\41 386,SM OR rm8,imm \300\1\x80\201\21 8086,SM OR rm16,imm \320\300\134\1\x81\201\131 8086,SM OR rm32,imm \321\300\144\1\x81\201\141 386,SM @@ -843,10 +838,10 @@ PUSH rm32 \321\300\1\xFF\206 386 PUSH reg_fsgs \1\x0F\7 386 PUSH reg_sreg \6 8086 PUSH imm8 \1\x6A\14 186 +PUSH sbyte \1\x6A\14 186,ND PUSH imm16 \320\133\1\x68\130 186 PUSH imm32 \321\143\1\x68\140 386 -PUSH sbyte \1\x6A\14 186,ND -PUSH imm \1\x68\34 186,ND +PUSH imm \1\x68\34 186 PUSHA void \322\1\x60 186 PUSHAD void \321\1\x60 386 PUSHAW void \320\1\x60 186 @@ -947,8 +942,7 @@ SBB rm32,imm8 \321\300\1\x83\203\15 8086 SBB reg_al,imm \1\x1C\21 8086,SM SBB reg_ax,imm \320\1\x1D\31 8086,SM SBB reg_eax,sbyte \321\1\x83\203\15 386,SM,ND -SBB reg_eax,sbig \321\1\x1D\41 386,SM,ND -SBB reg_eax,imm32 \321\1\x1D\41 386 +SBB reg_eax,imm \321\1\x1D\41 386,SM SBB rm8,imm \300\1\x80\203\21 8086,SM SBB rm16,imm \320\300\134\1\x81\203\131 8086,SM SBB rm32,imm \321\300\144\1\x81\203\141 386,SM @@ -1030,8 +1024,7 @@ SUB rm32,imm8 \321\300\1\x83\205\15 386 SUB reg_al,imm \1\x2C\21 8086,SM SUB reg_ax,imm \320\1\x2D\31 8086,SM SUB reg_eax,sbyte \321\1\x83\205\15 386,SM,ND -SUB reg_eax,sbig \321\1\x2D\41 386,SM,ND -SUB reg_eax,imm32 \321\1\x2D\41 386 +SUB reg_eax,imm \321\1\x2D\41 386,SM SUB rm8,imm \300\1\x80\205\21 8086,SM SUB rm16,imm \320\300\134\1\x81\205\131 8086,SM SUB rm32,imm \321\300\144\1\x81\205\141 386,SM @@ -1133,8 +1126,7 @@ XOR rm32,imm8 \321\300\1\x83\206\15 386 XOR reg_al,imm \1\x34\21 8086,SM XOR reg_ax,imm \320\1\x35\31 8086,SM XOR reg_eax,sbyte \321\1\x83\206\15 386,SM,ND -XOR reg_eax,sbig \321\1\x35\41 386,SM,ND -XOR reg_eax,imm32 \321\1\x35\41 386 +XOR reg_eax,imm \321\1\x35\41 386,SM XOR rm8,imm \300\1\x80\206\21 8086,SM XOR rm16,imm \320\300\134\1\x81\206\131 8086,SM XOR rm32,imm \321\300\144\1\x81\206\141 386,SM diff --git a/nasm.h b/nasm.h index 1ec58a30..1a58ac19 100644 --- a/nasm.h +++ b/nasm.h @@ -13,7 +13,7 @@ #define NASM_MAJOR_VER 0 #define NASM_MINOR_VER 98 -#define NASM_VER "0.98.20" +#define NASM_VER "0.98.21" #ifndef NULL #define NULL 0 @@ -428,8 +428,6 @@ enum { #define UNITY 0x00802000L /* for shift/rotate instructions */ #define BYTENESS 0x40000000L /* so SBYTE == IMMEDIATE | BYTENESS */ #define SBYTE 0x40002000L /* for op r16/32,immediate instrs. */ -#define BIGNESS 0x80000000L /* so SBIG == IMMEDIATE | BIGNESS */ -#define SBIG 0x80002000L /* for eax immediate instrs. */ /* * Next, the codes returned from the parser, for registers and diff --git a/parser.c b/parser.c index c3c00fc0..23d32926 100644 --- a/parser.c +++ b/parser.c @@ -686,11 +686,10 @@ insn *parse_line (int pass, char *buffer, insn *result, if (is_simple(value)) { if (reloc_value(value)==1) result->oprs[operand].type |= UNITY; - if (optimizing>0) { + if (optimizing>=0) { if (reloc_value(value) >= -128 && reloc_value(value) <= 127) result->oprs[operand].type |= SBYTE; - else result->oprs[operand].type |= SBIG; } } } -- 2.11.4.GIT