2 * This file is part of MPlayer.
4 * MPlayer is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * MPlayer is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with MPlayer; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 #include "cpudetect.h"
32 #if defined (__NetBSD__) || defined(__OpenBSD__)
33 #include <sys/param.h>
34 #include <sys/sysctl.h>
35 #include <machine/cpu.h>
36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
37 #include <sys/types.h>
38 #include <sys/sysctl.h>
39 #elif defined(__linux__)
41 #elif defined(__MINGW32__) || defined(__CYGWIN__)
43 #elif defined(__OS2__)
46 #elif defined(__AMIGAOS4__)
47 #include <proto/exec.h>
50 /* Thanks to the FreeBSD project for some of this cpuid code, and
51 * help understanding how to use it. Thanks to the Mesa
52 * team for SSE support detection and more cpu detect code.
55 /* I believe this code works. However, it has only been used on a PII and PIII */
57 static void check_os_katmai_support( void );
59 // return TRUE if cpuid supported
60 static int has_cpuid(void)
62 // code from libavcodec:
68 /* See if CPUID instruction is supported ... */
69 /* ... Get copies of EFLAGS into eax and ecx */
74 /* ... Toggle the ID bit in one copy and store */
75 /* to the EFLAGS reg */
76 "xor $0x200000, %0\n\t"
80 /* ... Get the (hopefully modified) EFLAGS */
93 do_cpuid(unsigned int ax
, unsigned int *p
)
98 : "=a" (p
[0]), "=b" (p
[1]), "=c" (p
[2]), "=d" (p
[3])
102 // code from libavcodec:
104 ("mov %%"REG_b
", %%"REG_S
"\n\t"
106 "xchg %%"REG_b
", %%"REG_S
107 : "=a" (p
[0]), "=S" (p
[1]),
108 "=c" (p
[2]), "=d" (p
[3])
114 void GetCpuCaps( CpuCaps
*caps
)
116 unsigned int regs
[4];
117 unsigned int regs2
[4];
119 memset(caps
, 0, sizeof(*caps
));
121 caps
->cl_size
=32; /* default */
123 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"CPUID not supported!??? (maybe an old 486?)\n");
126 do_cpuid(0x00000000, regs
); // get _max_ cpuid level and vendor name
127 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
128 (char*) (regs
+1),(char*) (regs
+3),(char*) (regs
+2), regs
[0]);
129 if (regs
[0]>=0x00000001)
131 char *tmpstr
, *ptmpstr
;
134 do_cpuid(0x00000001, regs2
);
136 caps
->cpuType
=(regs2
[0] >> 8)&0xf;
137 caps
->cpuModel
=(regs2
[0] >> 4)&0xf;
139 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
140 // System Instructions, Table 3-2: Effective family computation, page 120.
141 if(caps
->cpuType
==0xf){
142 // use extended family (P4, IA64, K8)
143 caps
->cpuType
=0xf+((regs2
[0]>>20)&255);
145 if(caps
->cpuType
==0xf || caps
->cpuType
==6)
146 caps
->cpuModel
|= ((regs2
[0]>>16)&0xf) << 4;
148 caps
->cpuStepping
=regs2
[0] & 0xf;
150 // general feature flags:
151 caps
->hasTSC
= (regs2
[3] & (1 << 8 )) >> 8; // 0x0000010
152 caps
->hasMMX
= (regs2
[3] & (1 << 23 )) >> 23; // 0x0800000
153 caps
->hasSSE
= (regs2
[3] & (1 << 25 )) >> 25; // 0x2000000
154 caps
->hasSSE2
= (regs2
[3] & (1 << 26 )) >> 26; // 0x4000000
155 caps
->hasSSE3
= (regs2
[2] & 1); // 0x0000001
156 caps
->hasSSSE3
= (regs2
[2] & (1 << 9 )) >> 9; // 0x0000200
157 caps
->hasMMX2
= caps
->hasSSE
; // SSE cpus supports mmxext too
158 cl_size
= ((regs2
[1] >> 8) & 0xFF)*8;
159 if(cl_size
) caps
->cl_size
= cl_size
;
161 ptmpstr
=tmpstr
=GetCpuFriendlyName(regs
, regs2
);
162 while(*ptmpstr
== ' ') // strip leading spaces
164 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU: %s ", ptmpstr
);
166 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"(Family: %d, Model: %d, Stepping: %d)\n",
167 caps
->cpuType
, caps
->cpuModel
, caps
->cpuStepping
);
170 do_cpuid(0x80000000, regs
);
171 if (regs
[0]>=0x80000001) {
172 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"extended cpuid-level: %d\n",regs
[0]&0x7FFFFFFF);
173 do_cpuid(0x80000001, regs2
);
174 caps
->hasMMX
|= (regs2
[3] & (1 << 23 )) >> 23; // 0x0800000
175 caps
->hasMMX2
|= (regs2
[3] & (1 << 22 )) >> 22; // 0x400000
176 caps
->has3DNow
= (regs2
[3] & (1 << 31 )) >> 31; //0x80000000
177 caps
->has3DNowExt
= (regs2
[3] & (1 << 30 )) >> 30;
178 caps
->hasSSE4a
= (regs2
[2] & (1 << 6 )) >> 6; // 0x0000040
180 if(regs
[0]>=0x80000006)
182 do_cpuid(0x80000006, regs2
);
183 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"extended cache-info: %d\n",regs2
[2]&0x7FFFFFFF);
184 caps
->cl_size
= regs2
[2] & 0xFF;
186 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"Detected cache-line size is %u bytes\n",caps
->cl_size
);
188 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
194 gCpuCaps
.has3DNowExt
);
197 /* FIXME: Does SSE2 need more OS support, too? */
199 check_os_katmai_support();
203 // caps->hasMMX2 = 0;
206 #if !CONFIG_RUNTIME_CPUDETECT
208 if(caps
->hasMMX
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"MMX supported but disabled\n");
212 if(caps
->hasMMX2
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"MMX2 supported but disabled\n");
216 if(caps
->hasSSE
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"SSE supported but disabled\n");
220 if(caps
->hasSSE2
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"SSE2 supported but disabled\n");
224 if(caps
->has3DNow
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"3DNow supported but disabled\n");
227 #if !HAVE_AMD3DNOWEXT
228 if(caps
->has3DNowExt
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"3DNowExt supported but disabled\n");
231 #endif // CONFIG_RUNTIME_CPUDETECT
234 char *GetCpuFriendlyName(unsigned int regs
[], unsigned int regs2
[]){
239 if (NULL
==(retname
=malloc(256))) {
240 mp_msg(MSGT_CPUDETECT
,MSGL_FATAL
,"Error: GetCpuFriendlyName() not enough memory\n");
245 sprintf(vendor
,"%.4s%.4s%.4s",(char*)(regs
+1),(char*)(regs
+3),(char*)(regs
+2));
247 do_cpuid(0x80000000,regs
);
248 if (regs
[0] >= 0x80000004)
250 // CPU has built-in namestring
251 for (i
= 0x80000002; i
<= 0x80000004; i
++)
254 strncat(retname
, (char*)regs
, 16);
260 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
261 static void sigill_handler_sse( int signal
, struct sigcontext sc
)
263 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SIGILL, " );
265 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
266 * instructions are 3 bytes long. We must increment the instruction
267 * pointer manually to avoid repeated execution of the offending
270 * If the SIGILL is caused by a divide-by-zero when unmasked
271 * exceptions aren't supported, the SIMD FPU status and control
272 * word will be restored at the end of the test, so we don't need
273 * to worry about doing it here. Besides, we may not be able to...
279 #endif /* __linux__ && _POSIX_SOURCE */
281 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
282 LONG CALLBACK
win32_sig_handler_sse(EXCEPTION_POINTERS
* ep
)
284 if(ep
->ExceptionRecord
->ExceptionCode
==EXCEPTION_ILLEGAL_INSTRUCTION
){
285 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SIGILL, " );
286 ep
->ContextRecord
->Eip
+=3;
288 return EXCEPTION_CONTINUE_EXECUTION
;
290 return EXCEPTION_CONTINUE_SEARCH
;
292 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
295 ULONG _System
os2_sig_handler_sse( PEXCEPTIONREPORTRECORD p1
,
296 PEXCEPTIONREGISTRATIONRECORD p2
,
300 if(p1
->ExceptionNum
== XCPT_ILLEGAL_INSTRUCTION
){
301 mp_msg(MSGT_CPUDETECT
, MSGL_V
, "SIGILL, ");
306 return XCPT_CONTINUE_EXECUTION
;
308 return XCPT_CONTINUE_SEARCH
;
312 /* If we're running on a processor that can do SSE, let's see if we
313 * are allowed to or not. This will catch 2.4.0 or later kernels that
314 * haven't been configured for a Pentium III but are running on one,
315 * and RedHat patched 2.2 kernels that have broken exception handling
316 * support for user space apps that do SSE.
319 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
320 #define SSE_SYSCTL_NAME "hw.instruction_sse"
321 #elif defined(__APPLE__)
322 #define SSE_SYSCTL_NAME "hw.optional.sse"
325 static void check_os_katmai_support( void )
330 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
332 size_t len
=sizeof(has_sse
);
334 ret
= sysctlbyname(SSE_SYSCTL_NAME
, &has_sse
, &len
, NULL
, 0);
338 #elif defined(__NetBSD__) || defined (__OpenBSD__)
339 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
340 int has_sse
, has_sse2
, ret
, mib
[2];
343 mib
[0] = CTL_MACHDEP
;
345 varlen
= sizeof(has_sse
);
347 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
348 ret
= sysctl(mib
, 2, &has_sse
, &varlen
, NULL
, 0);
349 gCpuCaps
.hasSSE
= ret
>= 0 && has_sse
;
350 mp_msg(MSGT_CPUDETECT
,MSGL_V
, gCpuCaps
.hasSSE
? "yes.\n" : "no!\n" );
353 varlen
= sizeof(has_sse2
);
354 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE2... " );
355 ret
= sysctl(mib
, 2, &has_sse2
, &varlen
, NULL
, 0);
356 gCpuCaps
.hasSSE2
= ret
>= 0 && has_sse2
;
357 mp_msg(MSGT_CPUDETECT
,MSGL_V
, gCpuCaps
.hasSSE2
? "yes.\n" : "no!\n" );
360 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "No OS support for SSE, disabling to be safe.\n" );
362 #elif defined(__MINGW32__) || defined(__CYGWIN__)
363 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil
;
364 if ( gCpuCaps
.hasSSE
) {
365 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
366 exc_fil
= SetUnhandledExceptionFilter(win32_sig_handler_sse
);
367 __asm__
volatile ("xorps %xmm0, %xmm0");
368 SetUnhandledExceptionFilter(exc_fil
);
369 mp_msg(MSGT_CPUDETECT
,MSGL_V
, gCpuCaps
.hasSSE
? "yes.\n" : "no!\n" );
371 #elif defined(__OS2__)
372 EXCEPTIONREGISTRATIONRECORD RegRec
= { 0, &os2_sig_handler_sse
};
373 if ( gCpuCaps
.hasSSE
) {
374 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
375 DosSetExceptionHandler( &RegRec
);
376 __asm__
volatile ("xorps %xmm0, %xmm0");
377 DosUnsetExceptionHandler( &RegRec
);
378 mp_msg(MSGT_CPUDETECT
,MSGL_V
, gCpuCaps
.hasSSE
? "yes.\n" : "no!\n" );
380 #elif defined(__linux__)
381 #if defined(_POSIX_SOURCE)
382 struct sigaction saved_sigill
;
384 /* Save the original signal handlers.
386 sigaction( SIGILL
, NULL
, &saved_sigill
);
388 signal( SIGILL
, (void (*)(int))sigill_handler_sse
);
390 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
391 * supports the extended FPU save and restore required for SSE. If
392 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
393 * doesn't support Streaming SIMD Exceptions, even if the processor
396 if ( gCpuCaps
.hasSSE
) {
397 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
399 // __asm__ volatile ("xorps %%xmm0, %%xmm0");
400 __asm__
volatile ("xorps %xmm0, %xmm0");
402 mp_msg(MSGT_CPUDETECT
,MSGL_V
, gCpuCaps
.hasSSE
? "yes.\n" : "no!\n" );
405 /* Restore the original signal handlers.
407 sigaction( SIGILL
, &saved_sigill
, NULL
);
409 /* If we've gotten to here and the XMM CPUID bit is still set, we're
410 * safe to go ahead and hook out the SSE code throughout Mesa.
412 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Tests of OS support for SSE %s\n", gCpuCaps
.hasSSE
? "passed." : "failed!" );
414 /* We can't use POSIX signal handling to test the availability of
415 * SSE, so we disable it by default.
417 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "Cannot test OS support for SSE, disabling to be safe.\n" );
419 #endif /* _POSIX_SOURCE */
421 /* Do nothing on other platforms for now.
423 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "Cannot test OS support for SSE, leaving disabled.\n" );
425 #endif /* __linux__ */
430 #include <sys/sysctl.h>
431 #elif defined(__AMIGAOS4__)
437 static sigjmp_buf jmpbuf
;
438 static volatile sig_atomic_t canjump
= 0;
440 static void sigill_handler (int sig
)
443 signal (sig
, SIG_DFL
);
448 siglongjmp (jmpbuf
, 1);
450 #endif /* __APPLE__ */
452 void GetCpuCaps( CpuCaps
*caps
)
467 caps
->hasAltiVec
= 0;
471 rip-off from ffmpeg altivec detection code.
472 this code also appears on Apple's AltiVec pages.
475 int sels
[2] = {CTL_HW
, HW_VECTORUNIT
};
477 size_t len
= sizeof(has_vu
);
480 err
= sysctl(sels
, 2, &has_vu
, &len
, NULL
, 0);
484 caps
->hasAltiVec
= 1;
486 #elif defined(__AMIGAOS4__)
489 GetCPUInfoTags(GCIT_VectorUnit
, &result
, TAG_DONE
);
490 if (result
== VECTORTYPE_ALTIVEC
)
491 caps
->hasAltiVec
= 1;
493 /* no Darwin, do it the brute-force way */
494 /* this is borrowed from the libmpeg2 library */
496 signal (SIGILL
, sigill_handler
);
497 if (sigsetjmp (jmpbuf
, 1)) {
498 signal (SIGILL
, SIG_DFL
);
502 __asm__
volatile ("mtspr 256, %0\n\t"
503 "vand %%v0, %%v0, %%v0"
507 signal (SIGILL
, SIG_DFL
);
508 caps
->hasAltiVec
= 1;
511 #endif /* __APPLE__ */
512 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"AltiVec %sfound\n", (caps
->hasAltiVec
? "" : "not "));
513 #endif /* HAVE_ALTIVEC */
516 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU: Intel Itanium\n");
519 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU: Sun Sparc\n");
522 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU: ARM\n");
525 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU: PowerPC\n");
528 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU: Digital Alpha\n");
531 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU: MIPS\n");
534 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU: Hewlett-Packard PA-RISC\n");
537 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU: IBM S/390\n");
540 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU: IBM S/390X\n");
543 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "CPU: Digital VAX\n" );
546 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "CPU: Tensilica Xtensa\n" );
548 #endif /* !ARCH_X86 */