3 * x86 backend for the Mono code generator
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
10 * Copyright 2003 Ximian, Inc.
11 * Copyright 2003-2011 Novell Inc.
12 * Copyright 2011 Xamarin Inc.
13 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
22 #include <mono/metadata/abi-details.h>
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internals.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-counters.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-hwcap.h>
34 #include <mono/utils/mono-threads.h>
35 #include <mono/utils/unlocked.h>
41 #include "aot-runtime.h"
42 #include "mini-runtime.h"
46 static gboolean optimize_for_xen
= TRUE
;
48 #define optimize_for_xen 0
52 static GENERATE_TRY_GET_CLASS_WITH_CACHE (math
, "System", "Math")
55 /* The single step trampoline */
56 static gpointer ss_trampoline
;
58 /* The breakpoint trampoline */
59 static gpointer bp_trampoline
;
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_DEFAULT || (sig)->call_convention == MONO_CALL_THISCALL))
67 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_THISCALL))
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
72 #define OP_SEQ_POINT_BP_OFFSET 7
75 mono_arch_regname (int reg
)
78 case X86_EAX
: return "%eax";
79 case X86_EBX
: return "%ebx";
80 case X86_ECX
: return "%ecx";
81 case X86_EDX
: return "%edx";
82 case X86_ESP
: return "%esp";
83 case X86_EBP
: return "%ebp";
84 case X86_EDI
: return "%edi";
85 case X86_ESI
: return "%esi";
91 mono_arch_fregname (int reg
)
116 mono_arch_xregname (int reg
)
141 mono_x86_patch (unsigned char* code
, gpointer target
)
143 mono_x86_patch_inline (code
, target
);
146 #define FLOAT_PARAM_REGS 0
148 static const guint32 thiscall_param_regs
[] = { X86_ECX
, X86_NREG
};
150 static const guint32
*callconv_param_regs(MonoMethodSignature
*sig
)
155 switch (sig
->call_convention
) {
156 case MONO_CALL_THISCALL
:
157 return thiscall_param_regs
;
163 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
164 #define SMALL_STRUCTS_IN_REGS
165 static X86_Reg_No return_regs
[] = { X86_EAX
, X86_EDX
};
169 add_general (guint32
*gr
, const guint32
*param_regs
, guint32
*stack_size
, ArgInfo
*ainfo
)
171 ainfo
->offset
= *stack_size
;
173 if (!param_regs
|| param_regs
[*gr
] == X86_NREG
) {
174 ainfo
->storage
= ArgOnStack
;
176 (*stack_size
) += sizeof (target_mgreg_t
);
179 ainfo
->storage
= ArgInIReg
;
180 ainfo
->reg
= param_regs
[*gr
];
186 add_general_pair (guint32
*gr
, const guint32
*param_regs
, guint32
*stack_size
, ArgInfo
*ainfo
)
188 ainfo
->offset
= *stack_size
;
190 g_assert(!param_regs
|| param_regs
[*gr
] == X86_NREG
);
192 ainfo
->storage
= ArgOnStack
;
193 (*stack_size
) += sizeof (target_mgreg_t
) * 2;
198 add_float (guint32
*gr
, guint32
*stack_size
, ArgInfo
*ainfo
, gboolean is_double
)
200 ainfo
->offset
= *stack_size
;
202 if (*gr
>= FLOAT_PARAM_REGS
) {
203 ainfo
->storage
= ArgOnStack
;
204 (*stack_size
) += is_double
? 8 : 4;
205 ainfo
->nslots
= is_double
? 2 : 1;
208 /* A double register */
210 ainfo
->storage
= ArgInDoubleSSEReg
;
212 ainfo
->storage
= ArgInFloatSSEReg
;
220 add_valuetype (MonoMethodSignature
*sig
, ArgInfo
*ainfo
, MonoType
*type
,
222 guint32
*gr
, const guint32
*param_regs
, guint32
*fr
, guint32
*stack_size
)
227 klass
= mono_class_from_mono_type_internal (type
);
228 size
= mini_type_stack_size_full (m_class_get_byval_arg (klass
), NULL
, sig
->pinvoke
);
230 #if defined(TARGET_WIN32)
232 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
233 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
234 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
235 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
236 * it must be represented in call and cannot be dropped.
238 if (size
== 0 && MONO_TYPE_ISSTRUCT (type
) && sig
->pinvoke
) {
239 /* Empty structs (1 byte size) needs to be represented in a stack slot */
240 ainfo
->pass_empty_struct
= TRUE
;
245 #ifdef SMALL_STRUCTS_IN_REGS
246 if (sig
->pinvoke
&& is_return
) {
247 MonoMarshalType
*info
;
249 info
= mono_marshal_load_type_info (klass
);
252 ainfo
->pair_storage
[0] = ainfo
->pair_storage
[1] = ArgNone
;
254 /* Ignore empty struct return value, if used. */
255 if (info
->num_fields
== 0 && ainfo
->pass_empty_struct
) {
256 ainfo
->storage
= ArgValuetypeInReg
;
261 * Windows x86 ABI for returning structs of size 4 or 8 bytes (regardless of type) dictates that
262 * values are passed in EDX:EAX register pairs, https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
263 * This is different compared to for example float or double return types (not in struct) that will be returned
264 * in ST(0), https://msdn.microsoft.com/en-us/library/ha59cbfz.aspx.
266 * Apples OSX x86 ABI for returning structs of size 4 or 8 bytes uses a slightly different approach.
267 * If a struct includes only one scalar value, it will be handled with the same rules as scalar values.
268 * This means that structs with one float or double will be returned in ST(0). For more details,
269 * https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html.
271 #if !defined(TARGET_WIN32)
273 /* Special case structs with only a float member */
274 if (info
->num_fields
== 1) {
275 int ftype
= mini_get_underlying_type (info
->fields
[0].field
->type
)->type
;
276 if ((info
->native_size
== 8) && (ftype
== MONO_TYPE_R8
)) {
277 ainfo
->storage
= ArgValuetypeInReg
;
278 ainfo
->pair_storage
[0] = ArgOnDoubleFpStack
;
281 if ((info
->native_size
== 4) && (ftype
== MONO_TYPE_R4
)) {
282 ainfo
->storage
= ArgValuetypeInReg
;
283 ainfo
->pair_storage
[0] = ArgOnFloatFpStack
;
289 if ((info
->native_size
== 1) || (info
->native_size
== 2) || (info
->native_size
== 4) || (info
->native_size
== 8)) {
290 ainfo
->storage
= ArgValuetypeInReg
;
291 ainfo
->pair_storage
[0] = ArgInIReg
;
292 ainfo
->pair_regs
[0] = return_regs
[0];
293 if (info
->native_size
> 4) {
294 ainfo
->pair_storage
[1] = ArgInIReg
;
295 ainfo
->pair_regs
[1] = return_regs
[1];
302 if (param_regs
&& param_regs
[*gr
] != X86_NREG
&& !is_return
) {
303 g_assert (size
<= 4);
304 ainfo
->storage
= ArgValuetypeInReg
;
305 ainfo
->reg
= param_regs
[*gr
];
310 ainfo
->offset
= *stack_size
;
311 ainfo
->storage
= ArgOnStack
;
312 *stack_size
+= ALIGN_TO (size
, sizeof (target_mgreg_t
));
313 ainfo
->nslots
= ALIGN_TO (size
, sizeof (target_mgreg_t
)) / sizeof (target_mgreg_t
);
319 * Obtain information about a call according to the calling convention.
320 * For x86 ELF, see the "System V Application Binary Interface Intel386
321 * Architecture Processor Supplment, Fourth Edition" document for more
323 * For x86 win32, see https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
326 get_call_info_internal (CallInfo
*cinfo
, MonoMethodSignature
*sig
)
328 guint32 i
, gr
, fr
, pstart
;
329 const guint32
*param_regs
;
331 int n
= sig
->hasthis
+ sig
->param_count
;
332 guint32 stack_size
= 0;
333 gboolean is_pinvoke
= sig
->pinvoke
;
339 param_regs
= callconv_param_regs(sig
);
343 ret_type
= mini_get_underlying_type (sig
->ret
);
344 switch (ret_type
->type
) {
354 case MONO_TYPE_FNPTR
:
355 case MONO_TYPE_OBJECT
:
356 cinfo
->ret
.storage
= ArgInIReg
;
357 cinfo
->ret
.reg
= X86_EAX
;
361 cinfo
->ret
.storage
= ArgInIReg
;
362 cinfo
->ret
.reg
= X86_EAX
;
363 cinfo
->ret
.is_pair
= TRUE
;
366 cinfo
->ret
.storage
= ArgOnFloatFpStack
;
369 cinfo
->ret
.storage
= ArgOnDoubleFpStack
;
371 case MONO_TYPE_GENERICINST
:
372 if (!mono_type_generic_inst_is_valuetype (ret_type
)) {
373 cinfo
->ret
.storage
= ArgInIReg
;
374 cinfo
->ret
.reg
= X86_EAX
;
377 if (mini_is_gsharedvt_type (ret_type
)) {
378 cinfo
->ret
.storage
= ArgOnStack
;
379 cinfo
->vtype_retaddr
= TRUE
;
383 case MONO_TYPE_VALUETYPE
:
384 case MONO_TYPE_TYPEDBYREF
: {
385 guint32 tmp_gr
= 0, tmp_fr
= 0, tmp_stacksize
= 0;
387 add_valuetype (sig
, &cinfo
->ret
, ret_type
, TRUE
, &tmp_gr
, NULL
, &tmp_fr
, &tmp_stacksize
);
388 if (cinfo
->ret
.storage
== ArgOnStack
) {
389 cinfo
->vtype_retaddr
= TRUE
;
390 /* The caller passes the address where the value is stored */
396 g_assert (mini_is_gsharedvt_type (ret_type
));
397 cinfo
->ret
.storage
= ArgOnStack
;
398 cinfo
->vtype_retaddr
= TRUE
;
401 cinfo
->ret
.storage
= ArgNone
;
404 g_error ("Can't handle as return value 0x%x", ret_type
->type
);
410 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
411 * the first argument, allowing 'this' to be always passed in the first arg reg.
412 * Also do this if the first argument is a reference type, since virtual calls
413 * are sometimes made using calli without sig->hasthis set, like in the delegate
416 if (cinfo
->vtype_retaddr
&& !is_pinvoke
&& (sig
->hasthis
|| (sig
->param_count
> 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig
->params
[0]))))) {
418 add_general (&gr
, param_regs
, &stack_size
, cinfo
->args
+ 0);
420 add_general (&gr
, param_regs
, &stack_size
, &cinfo
->args
[sig
->hasthis
+ 0]);
423 cinfo
->vret_arg_offset
= stack_size
;
424 add_general (&gr
, NULL
, &stack_size
, &cinfo
->ret
);
425 cinfo
->vret_arg_index
= 1;
429 add_general (&gr
, param_regs
, &stack_size
, cinfo
->args
+ 0);
431 if (cinfo
->vtype_retaddr
)
432 add_general (&gr
, NULL
, &stack_size
, &cinfo
->ret
);
435 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
) && (n
== 0)) {
436 fr
= FLOAT_PARAM_REGS
;
438 /* Emit the signature cookie just before the implicit arguments */
439 add_general (&gr
, param_regs
, &stack_size
, &cinfo
->sig_cookie
);
442 for (i
= pstart
; i
< sig
->param_count
; ++i
) {
443 ArgInfo
*ainfo
= &cinfo
->args
[sig
->hasthis
+ i
];
446 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
) && (i
== sig
->sentinelpos
)) {
447 /* We allways pass the sig cookie on the stack for simplicity */
449 * Prevent implicit arguments + the sig cookie from being passed
452 fr
= FLOAT_PARAM_REGS
;
454 /* Emit the signature cookie just before the implicit arguments */
455 add_general (&gr
, param_regs
, &stack_size
, &cinfo
->sig_cookie
);
458 if (sig
->params
[i
]->byref
) {
459 add_general (&gr
, param_regs
, &stack_size
, ainfo
);
462 ptype
= mini_get_underlying_type (sig
->params
[i
]);
463 switch (ptype
->type
) {
466 add_general (&gr
, param_regs
, &stack_size
, ainfo
);
470 add_general (&gr
, param_regs
, &stack_size
, ainfo
);
474 add_general (&gr
, param_regs
, &stack_size
, ainfo
);
479 case MONO_TYPE_FNPTR
:
480 case MONO_TYPE_OBJECT
:
481 add_general (&gr
, param_regs
, &stack_size
, ainfo
);
483 case MONO_TYPE_GENERICINST
:
484 if (!mono_type_generic_inst_is_valuetype (ptype
)) {
485 add_general (&gr
, param_regs
, &stack_size
, ainfo
);
488 if (mini_is_gsharedvt_type (ptype
)) {
489 /* gsharedvt arguments are passed by ref */
490 add_general (&gr
, param_regs
, &stack_size
, ainfo
);
491 g_assert (ainfo
->storage
== ArgOnStack
);
492 ainfo
->storage
= ArgGSharedVt
;
496 case MONO_TYPE_VALUETYPE
:
497 case MONO_TYPE_TYPEDBYREF
:
498 add_valuetype (sig
, ainfo
, ptype
, FALSE
, &gr
, param_regs
, &fr
, &stack_size
);
502 add_general_pair (&gr
, param_regs
, &stack_size
, ainfo
);
505 add_float (&fr
, &stack_size
, ainfo
, FALSE
);
508 add_float (&fr
, &stack_size
, ainfo
, TRUE
);
512 /* gsharedvt arguments are passed by ref */
513 g_assert (mini_is_gsharedvt_type (ptype
));
514 add_general (&gr
, param_regs
, &stack_size
, ainfo
);
515 g_assert (ainfo
->storage
== ArgOnStack
);
516 ainfo
->storage
= ArgGSharedVt
;
519 g_error ("unexpected type 0x%x", ptype
->type
);
520 g_assert_not_reached ();
524 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
) && (n
> 0) && (sig
->sentinelpos
== sig
->param_count
)) {
525 fr
= FLOAT_PARAM_REGS
;
527 /* Emit the signature cookie just before the implicit arguments */
528 add_general (&gr
, param_regs
, &stack_size
, &cinfo
->sig_cookie
);
531 if (cinfo
->vtype_retaddr
) {
532 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
533 cinfo
->callee_stack_pop
= 4;
534 } else if (CALLCONV_IS_STDCALL (sig
)) {
535 /* Have to compensate for the stack space popped by the native callee */
536 cinfo
->callee_stack_pop
= stack_size
;
539 if (mono_do_x86_stack_align
&& (stack_size
% MONO_ARCH_FRAME_ALIGNMENT
) != 0) {
540 cinfo
->need_stack_align
= TRUE
;
541 cinfo
->stack_align_amount
= MONO_ARCH_FRAME_ALIGNMENT
- (stack_size
% MONO_ARCH_FRAME_ALIGNMENT
);
542 stack_size
+= cinfo
->stack_align_amount
;
545 cinfo
->stack_usage
= stack_size
;
546 cinfo
->reg_usage
= gr
;
547 cinfo
->freg_usage
= fr
;
552 get_call_info (MonoMemPool
*mp
, MonoMethodSignature
*sig
)
554 int n
= sig
->hasthis
+ sig
->param_count
;
558 cinfo
= mono_mempool_alloc0 (mp
, sizeof (CallInfo
) + (sizeof (ArgInfo
) * n
));
560 cinfo
= g_malloc0 (sizeof (CallInfo
) + (sizeof (ArgInfo
) * n
));
562 return get_call_info_internal (cinfo
, sig
);
565 static gboolean
storage_in_ireg (ArgStorage storage
)
567 return (storage
== ArgInIReg
|| storage
== ArgValuetypeInReg
);
571 * mono_arch_get_argument_info:
572 * @csig: a method signature
573 * @param_count: the number of parameters to consider
574 * @arg_info: an array to store the result infos
576 * Gathers information on parameters such as size, alignment and
577 * padding. arg_info should be large enought to hold param_count + 1 entries.
579 * Returns the size of the argument area on the stack.
580 * This should be signal safe, since it is called from
581 * mono_arch_unwind_frame ().
582 * FIXME: The metadata calls might not be signal safe.
585 mono_arch_get_argument_info (MonoMethodSignature
*csig
, int param_count
, MonoJitArgumentInfo
*arg_info
)
587 int len
, k
, args_size
= 0;
595 /* Avoid g_malloc as it is not signal safe */
596 len
= sizeof (CallInfo
) + (sizeof (ArgInfo
) * (csig
->param_count
+ 1));
597 cinfo
= (CallInfo
*)g_alloca (len
);
598 memset (cinfo
, 0, len
);
600 cinfo
= get_call_info_internal (cinfo
, csig
);
602 arg_info
[0].offset
= offset
;
604 if (cinfo
->vtype_retaddr
&& cinfo
->vret_arg_index
== 0) {
605 args_size
+= sizeof (target_mgreg_t
);
609 if (csig
->hasthis
&& !storage_in_ireg (cinfo
->args
[0].storage
)) {
610 args_size
+= sizeof (target_mgreg_t
);
614 if (cinfo
->vtype_retaddr
&& cinfo
->vret_arg_index
== 1 && csig
->hasthis
) {
615 /* Emitted after this */
616 args_size
+= sizeof (target_mgreg_t
);
620 arg_info
[0].size
= args_size
;
623 for (k
= 0; k
< param_count
; k
++) {
624 size
= mini_type_stack_size_full (csig
->params
[k
], &align
, csig
->pinvoke
);
626 if (storage_in_ireg (cinfo
->args
[csig
->hasthis
+ k
].storage
)) {
627 /* not in stack, we'll give it an offset at the end */
628 arg_info
[k
+ 1].pad
= 0;
629 arg_info
[k
+ 1].size
= size
;
631 /* ignore alignment for now */
634 args_size
+= pad
= (align
- (args_size
& (align
- 1))) & (align
- 1);
635 arg_info
[prev_stackarg
].pad
= pad
;
637 arg_info
[k
+ 1].pad
= 0;
638 arg_info
[k
+ 1].size
= size
;
640 arg_info
[k
+ 1].offset
= offset
;
642 prev_stackarg
= k
+ 1;
645 if (k
== 0 && cinfo
->vtype_retaddr
&& cinfo
->vret_arg_index
== 1 && !csig
->hasthis
) {
646 /* Emitted after the first arg */
647 args_size
+= sizeof (target_mgreg_t
);
652 if (mono_do_x86_stack_align
&& !CALLCONV_IS_STDCALL (csig
))
653 align
= MONO_ARCH_FRAME_ALIGNMENT
;
656 args_size
+= pad
= (align
- (args_size
& (align
- 1))) & (align
- 1);
657 arg_info
[k
].pad
= pad
;
659 /* Add offsets for any reg parameters */
661 if (csig
->hasthis
&& storage_in_ireg (cinfo
->args
[0].storage
))
662 arg_info
[0].offset
= args_size
+ 4 * num_regs
++;
663 for (k
=0; k
< param_count
; k
++) {
664 if (storage_in_ireg (cinfo
->args
[csig
->hasthis
+ k
].storage
)) {
665 arg_info
[k
+ 1].offset
= args_size
+ 4 * num_regs
++;
675 mono_arch_tailcall_supported (MonoCompile
*cfg
, MonoMethodSignature
*caller_sig
, MonoMethodSignature
*callee_sig
, gboolean virtual_
)
677 g_assert (caller_sig
);
678 g_assert (callee_sig
);
680 // Direct AOT calls usually go through the PLT/GOT.
681 // Unless we can determine here if is_direct_callable will return TRUE?
682 // But the PLT/GOT is addressed with nonvolatile ebx, which
683 // gets restored before the jump.
684 // See https://github.com/mono/mono/commit/f5373adc8a89d4b0d1d549fdd6d9adc3ded4b400
685 // See https://github.com/mono/mono/issues/11265
686 if (!virtual_
&& cfg
->compile_aot
&& !cfg
->full_aot
)
689 CallInfo
*caller_info
= get_call_info (NULL
, caller_sig
);
690 CallInfo
*callee_info
= get_call_info (NULL
, callee_sig
);
693 * Tailcalls with more callee stack usage than the caller cannot be supported, since
694 * the extra stack space would be left on the stack after the tailcall.
696 gboolean res
= IS_SUPPORTED_TAILCALL (callee_info
->stack_usage
<= caller_info
->stack_usage
)
697 && IS_SUPPORTED_TAILCALL (caller_info
->ret
.storage
== callee_info
->ret
.storage
);
698 if (!res
&& !mono_tailcall_print_enabled ())
701 // Limit stack_usage to 1G.
702 res
&= IS_SUPPORTED_TAILCALL (callee_info
->stack_usage
< (1 << 30));
703 res
&= IS_SUPPORTED_TAILCALL (caller_info
->stack_usage
< (1 << 30));
706 g_free (caller_info
);
707 g_free (callee_info
);
715 * Initialize the cpu to execute managed code.
718 mono_arch_cpu_init (void)
720 /* spec compliance requires running with double precision */
724 __asm__
__volatile__ ("fnstcw %0\n": "=m" (fpcw
));
725 fpcw
&= ~X86_FPCW_PRECC_MASK
;
726 fpcw
|= X86_FPCW_PREC_DOUBLE
;
727 __asm__
__volatile__ ("fldcw %0\n": : "m" (fpcw
));
728 __asm__
__volatile__ ("fnstcw %0\n": "=m" (fpcw
));
730 _control87 (_PC_53
, MCW_PC
);
735 * Initialize architecture specific code.
738 mono_arch_init (void)
741 bp_trampoline
= mini_get_breakpoint_trampoline ();
745 * Cleanup architecture specific code.
748 mono_arch_cleanup (void)
753 * This function returns the optimizations supported on this cpu.
756 mono_arch_cpu_optimizations (guint32
*exclude_mask
)
762 if (mono_hwcap_x86_has_cmov
) {
763 opts
|= MONO_OPT_CMOV
;
765 if (mono_hwcap_x86_has_fcmov
)
766 opts
|= MONO_OPT_FCMOV
;
768 *exclude_mask
|= MONO_OPT_FCMOV
;
770 *exclude_mask
|= MONO_OPT_CMOV
;
773 if (mono_hwcap_x86_has_sse2
)
774 opts
|= MONO_OPT_SSE2
;
776 *exclude_mask
|= MONO_OPT_SSE2
;
778 #ifdef MONO_ARCH_SIMD_INTRINSICS
779 /*SIMD intrinsics require at least SSE2.*/
780 if (!mono_hwcap_x86_has_sse2
)
781 *exclude_mask
|= MONO_OPT_SIMD
;
788 * This function test for all SSE functions supported.
790 * Returns a bitmask corresponding to all supported versions.
794 mono_arch_cpu_enumerate_simd_versions (void)
796 guint32 sse_opts
= 0;
798 if (mono_hwcap_x86_has_sse1
)
799 sse_opts
|= SIMD_VERSION_SSE1
;
801 if (mono_hwcap_x86_has_sse2
)
802 sse_opts
|= SIMD_VERSION_SSE2
;
804 if (mono_hwcap_x86_has_sse3
)
805 sse_opts
|= SIMD_VERSION_SSE3
;
807 if (mono_hwcap_x86_has_ssse3
)
808 sse_opts
|= SIMD_VERSION_SSSE3
;
810 if (mono_hwcap_x86_has_sse41
)
811 sse_opts
|= SIMD_VERSION_SSE41
;
813 if (mono_hwcap_x86_has_sse42
)
814 sse_opts
|= SIMD_VERSION_SSE42
;
816 if (mono_hwcap_x86_has_sse4a
)
817 sse_opts
|= SIMD_VERSION_SSE4a
;
823 * Determine whenever the trap whose info is in SIGINFO is caused by
827 mono_arch_is_int_overflow (void *sigctx
, void *info
)
832 mono_sigctx_to_monoctx (sigctx
, &ctx
);
834 ip
= (guint8
*)ctx
.eip
;
836 if ((ip
[0] == 0xf7) && (x86_modrm_mod (ip
[1]) == 0x3) && (x86_modrm_reg (ip
[1]) == 0x7)) {
840 switch (x86_modrm_rm (ip
[1])) {
860 g_assert_not_reached ();
872 mono_arch_get_allocatable_int_vars (MonoCompile
*cfg
)
877 for (i
= 0; i
< cfg
->num_varinfo
; i
++) {
878 MonoInst
*ins
= cfg
->varinfo
[i
];
879 MonoMethodVar
*vmv
= MONO_VARINFO (cfg
, i
);
882 if (vmv
->range
.first_use
.abs_pos
>= vmv
->range
.last_use
.abs_pos
)
885 if ((ins
->flags
& (MONO_INST_IS_DEAD
|MONO_INST_VOLATILE
|MONO_INST_INDIRECT
)) ||
886 (ins
->opcode
!= OP_LOCAL
&& ins
->opcode
!= OP_ARG
))
889 /* we dont allocate I1 to registers because there is no simply way to sign extend
890 * 8bit quantities in caller saved registers on x86 */
891 if (mono_is_regsize_var (ins
->inst_vtype
) && (ins
->inst_vtype
->type
!= MONO_TYPE_I1
)) {
892 g_assert (MONO_VARINFO (cfg
, i
)->reg
== -1);
893 g_assert (i
== vmv
->idx
);
894 vars
= g_list_prepend (vars
, vmv
);
898 vars
= mono_varlist_sort (cfg
, vars
, 0);
904 mono_arch_get_global_int_regs (MonoCompile
*cfg
)
908 /* we can use 3 registers for global allocation */
909 regs
= g_list_prepend (regs
, (gpointer
)X86_EBX
);
910 regs
= g_list_prepend (regs
, (gpointer
)X86_ESI
);
911 regs
= g_list_prepend (regs
, (gpointer
)X86_EDI
);
917 * mono_arch_regalloc_cost:
919 * Return the cost, in number of memory references, of the action of
920 * allocating the variable VMV into a register during global register
924 mono_arch_regalloc_cost (MonoCompile
*cfg
, MonoMethodVar
*vmv
)
926 MonoInst
*ins
= cfg
->varinfo
[vmv
->idx
];
928 if (cfg
->method
->save_lmf
)
929 /* The register is already saved */
930 return (ins
->opcode
== OP_ARG
) ? 1 : 0;
932 /* push+pop+possible load if it is an argument */
933 return (ins
->opcode
== OP_ARG
) ? 3 : 2;
937 set_needs_stack_frame (MonoCompile
*cfg
, gboolean flag
)
939 static int inited
= FALSE
;
940 static int count
= 0;
942 if (cfg
->arch
.need_stack_frame_inited
) {
943 g_assert (cfg
->arch
.need_stack_frame
== flag
);
947 cfg
->arch
.need_stack_frame
= flag
;
948 cfg
->arch
.need_stack_frame_inited
= TRUE
;
954 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT
|MONO_COUNTER_JIT
, &count
);
959 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
963 needs_stack_frame (MonoCompile
*cfg
)
965 MonoMethodSignature
*sig
;
966 MonoMethodHeader
*header
;
967 gboolean result
= FALSE
;
969 #if defined (__APPLE__)
970 /*OSX requires stack frame code to have the correct alignment. */
974 if (cfg
->arch
.need_stack_frame_inited
)
975 return cfg
->arch
.need_stack_frame
;
977 header
= cfg
->header
;
978 sig
= mono_method_signature_internal (cfg
->method
);
980 if (cfg
->disable_omit_fp
)
982 else if (cfg
->flags
& MONO_CFG_HAS_ALLOCA
)
984 else if (cfg
->method
->save_lmf
)
986 else if (cfg
->stack_offset
)
988 else if (cfg
->param_area
)
990 else if (cfg
->flags
& (MONO_CFG_HAS_CALLS
| MONO_CFG_HAS_ALLOCA
| MONO_CFG_HAS_TAILCALL
))
992 else if (header
->num_clauses
)
994 else if (sig
->param_count
+ sig
->hasthis
)
996 else if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
))
999 set_needs_stack_frame (cfg
, result
);
1001 return cfg
->arch
.need_stack_frame
;
1005 * Set var information according to the calling convention. X86 version.
1006 * The locals var stuff should most likely be split in another method.
1009 mono_arch_allocate_vars (MonoCompile
*cfg
)
1011 MonoMethodSignature
*sig
;
1013 guint32 locals_stack_size
, locals_stack_align
;
1018 sig
= mono_method_signature_internal (cfg
->method
);
1020 if (!cfg
->arch
.cinfo
)
1021 cfg
->arch
.cinfo
= get_call_info (cfg
->mempool
, sig
);
1022 cinfo
= cfg
->arch
.cinfo
;
1024 cfg
->frame_reg
= X86_EBP
;
1027 if (cfg
->has_atomic_add_i4
|| cfg
->has_atomic_exchange_i4
) {
1028 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1029 cfg
->used_int_regs
|= (1 << X86_EBX
) | (1 << X86_EDI
) | (1 << X86_ESI
);
1032 /* Reserve space to save LMF and caller saved registers */
1034 if (cfg
->method
->save_lmf
) {
1035 /* The LMF var is allocated normally */
1037 if (cfg
->used_int_regs
& (1 << X86_EBX
)) {
1041 if (cfg
->used_int_regs
& (1 << X86_EDI
)) {
1045 if (cfg
->used_int_regs
& (1 << X86_ESI
)) {
1050 switch (cinfo
->ret
.storage
) {
1051 case ArgValuetypeInReg
:
1052 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1054 cfg
->ret
->opcode
= OP_REGOFFSET
;
1055 cfg
->ret
->inst_basereg
= X86_EBP
;
1056 cfg
->ret
->inst_offset
= - offset
;
1062 /* Allocate a local for any register arguments that need them. */
1063 for (i
= 0; i
< sig
->param_count
+ sig
->hasthis
; ++i
) {
1064 ArgInfo
*ainfo
= &cinfo
->args
[i
];
1065 inst
= cfg
->args
[i
];
1066 if (inst
->opcode
!= OP_REGVAR
&& storage_in_ireg (ainfo
->storage
)) {
1068 cfg
->args
[i
]->opcode
= OP_REGOFFSET
;
1069 cfg
->args
[i
]->inst_basereg
= X86_EBP
;
1070 cfg
->args
[i
]->inst_offset
= - offset
;
1074 /* Allocate locals */
1075 offsets
= mono_allocate_stack_slots (cfg
, TRUE
, &locals_stack_size
, &locals_stack_align
);
1076 if (locals_stack_size
> MONO_ARCH_MAX_FRAME_SIZE
) {
1077 char *mname
= mono_method_full_name (cfg
->method
, TRUE
);
1078 mono_cfg_set_exception_invalid_program (cfg
, g_strdup_printf ("Method %s stack is too big.", mname
));
1082 if (locals_stack_align
) {
1083 int prev_offset
= offset
;
1085 offset
+= (locals_stack_align
- 1);
1086 offset
&= ~(locals_stack_align
- 1);
1088 while (prev_offset
< offset
) {
1090 mini_gc_set_slot_type_from_fp (cfg
, - prev_offset
, SLOT_NOREF
);
1093 cfg
->locals_min_stack_offset
= - (offset
+ locals_stack_size
);
1094 cfg
->locals_max_stack_offset
= - offset
;
1096 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1097 * have locals larger than 8 bytes we need to make sure that
1098 * they have the appropriate offset.
1100 if (MONO_ARCH_FRAME_ALIGNMENT
> 8 && locals_stack_align
> 8) {
1101 int extra_size
= MONO_ARCH_FRAME_ALIGNMENT
- sizeof (target_mgreg_t
) * 2;
1102 offset
+= extra_size
;
1103 locals_stack_size
+= extra_size
;
1105 for (i
= cfg
->locals_start
; i
< cfg
->num_varinfo
; i
++) {
1106 if (offsets
[i
] != -1) {
1107 MonoInst
*inst
= cfg
->varinfo
[i
];
1108 inst
->opcode
= OP_REGOFFSET
;
1109 inst
->inst_basereg
= X86_EBP
;
1110 inst
->inst_offset
= - (offset
+ offsets
[i
]);
1111 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1114 offset
+= locals_stack_size
;
1118 * Allocate arguments+return value
1121 switch (cinfo
->ret
.storage
) {
1123 if (cfg
->vret_addr
) {
1125 * In the new IR, the cfg->vret_addr variable represents the
1126 * vtype return value.
1128 cfg
->vret_addr
->opcode
= OP_REGOFFSET
;
1129 cfg
->vret_addr
->inst_basereg
= cfg
->frame_reg
;
1130 cfg
->vret_addr
->inst_offset
= cinfo
->ret
.offset
+ ARGS_OFFSET
;
1131 if (G_UNLIKELY (cfg
->verbose_level
> 1)) {
1132 printf ("vret_addr =");
1133 mono_print_ins (cfg
->vret_addr
);
1136 cfg
->ret
->opcode
= OP_REGOFFSET
;
1137 cfg
->ret
->inst_basereg
= X86_EBP
;
1138 cfg
->ret
->inst_offset
= cinfo
->ret
.offset
+ ARGS_OFFSET
;
1141 case ArgValuetypeInReg
:
1144 cfg
->ret
->opcode
= OP_REGVAR
;
1145 cfg
->ret
->inst_c0
= cinfo
->ret
.reg
;
1146 cfg
->ret
->dreg
= cinfo
->ret
.reg
;
1149 case ArgOnFloatFpStack
:
1150 case ArgOnDoubleFpStack
:
1153 g_assert_not_reached ();
1156 if (sig
->call_convention
== MONO_CALL_VARARG
) {
1157 g_assert (cinfo
->sig_cookie
.storage
== ArgOnStack
);
1158 cfg
->sig_cookie
= cinfo
->sig_cookie
.offset
+ ARGS_OFFSET
;
1161 for (i
= 0; i
< sig
->param_count
+ sig
->hasthis
; ++i
) {
1162 ArgInfo
*ainfo
= &cinfo
->args
[i
];
1163 inst
= cfg
->args
[i
];
1164 if (inst
->opcode
!= OP_REGVAR
) {
1165 if (storage_in_ireg (ainfo
->storage
)) {
1166 /* We already allocated locals for register arguments. */
1168 inst
->opcode
= OP_REGOFFSET
;
1169 inst
->inst_basereg
= X86_EBP
;
1170 inst
->inst_offset
= ainfo
->offset
+ ARGS_OFFSET
;
1175 cfg
->stack_offset
= offset
;
1179 mono_arch_create_vars (MonoCompile
*cfg
)
1182 MonoMethodSignature
*sig
;
1185 sig
= mono_method_signature_internal (cfg
->method
);
1187 if (!cfg
->arch
.cinfo
)
1188 cfg
->arch
.cinfo
= get_call_info (cfg
->mempool
, sig
);
1189 cinfo
= cfg
->arch
.cinfo
;
1191 sig_ret
= mini_get_underlying_type (sig
->ret
);
1193 if (cinfo
->ret
.storage
== ArgValuetypeInReg
)
1194 cfg
->ret_var_is_local
= TRUE
;
1195 if ((cinfo
->ret
.storage
!= ArgValuetypeInReg
) && (MONO_TYPE_ISSTRUCT (sig_ret
) || mini_is_gsharedvt_variable_type (sig_ret
))) {
1196 cfg
->vret_addr
= mono_compile_create_var (cfg
, mono_get_int_type (), OP_ARG
);
1199 if (cfg
->gen_sdb_seq_points
) {
1202 ins
= mono_compile_create_var (cfg
, mono_get_int_type (), OP_LOCAL
);
1203 ins
->flags
|= MONO_INST_VOLATILE
;
1204 cfg
->arch
.ss_tramp_var
= ins
;
1206 ins
= mono_compile_create_var (cfg
, mono_get_int_type (), OP_LOCAL
);
1207 ins
->flags
|= MONO_INST_VOLATILE
;
1208 cfg
->arch
.bp_tramp_var
= ins
;
1211 if (cfg
->method
->save_lmf
) {
1212 cfg
->create_lmf_var
= TRUE
;
1216 cfg
->arch_eh_jit_info
= 1;
1220 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1221 * so we try to do it just once when we have multiple fp arguments in a row.
1222 * We don't use this mechanism generally because for int arguments the generated code
1223 * is slightly bigger and new generation cpus optimize away the dependency chains
1224 * created by push instructions on the esp value.
1225 * fp_arg_setup is the first argument in the execution sequence where the esp register
1228 static G_GNUC_UNUSED
int
1229 collect_fp_stack_space (MonoMethodSignature
*sig
, int start_arg
, int *fp_arg_setup
)
1234 for (; start_arg
< sig
->param_count
; ++start_arg
) {
1235 t
= mini_get_underlying_type (sig
->params
[start_arg
]);
1236 if (!t
->byref
&& t
->type
== MONO_TYPE_R8
) {
1237 fp_space
+= sizeof (double);
1238 *fp_arg_setup
= start_arg
;
1247 emit_sig_cookie (MonoCompile
*cfg
, MonoCallInst
*call
, CallInfo
*cinfo
)
1249 MonoMethodSignature
*tmp_sig
;
1253 * mono_ArgIterator_Setup assumes the signature cookie is
1254 * passed first and all the arguments which were before it are
1255 * passed on the stack after the signature. So compensate by
1256 * passing a different signature.
1258 tmp_sig
= mono_metadata_signature_dup (call
->signature
);
1259 tmp_sig
->param_count
-= call
->signature
->sentinelpos
;
1260 tmp_sig
->sentinelpos
= 0;
1261 memcpy (tmp_sig
->params
, call
->signature
->params
+ call
->signature
->sentinelpos
, tmp_sig
->param_count
* sizeof (MonoType
*));
1263 if (cfg
->compile_aot
) {
1264 sig_reg
= mono_alloc_ireg (cfg
);
1265 MONO_EMIT_NEW_SIGNATURECONST (cfg
, sig_reg
, tmp_sig
);
1266 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, X86_ESP
, cinfo
->sig_cookie
.offset
, sig_reg
);
1268 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg
, OP_STORE_MEMBASE_IMM
, X86_ESP
, cinfo
->sig_cookie
.offset
, tmp_sig
);
1274 mono_arch_get_llvm_call_info (MonoCompile
*cfg
, MonoMethodSignature
*sig
)
1279 LLVMCallInfo
*linfo
;
1280 MonoType
*t
, *sig_ret
;
1282 n
= sig
->param_count
+ sig
->hasthis
;
1284 cinfo
= get_call_info (cfg
->mempool
, sig
);
1287 linfo
= mono_mempool_alloc0 (cfg
->mempool
, sizeof (LLVMCallInfo
) + (sizeof (LLVMArgInfo
) * n
));
1290 * LLVM always uses the native ABI while we use our own ABI, the
1291 * only difference is the handling of vtypes:
1292 * - we only pass/receive them in registers in some cases, and only
1293 * in 1 or 2 integer registers.
1295 if (cinfo
->ret
.storage
== ArgValuetypeInReg
) {
1297 cfg
->exception_message
= g_strdup ("pinvoke + vtypes");
1298 cfg
->disable_llvm
= TRUE
;
1302 cfg
->exception_message
= g_strdup ("vtype ret in call");
1303 cfg
->disable_llvm
= TRUE
;
1305 linfo->ret.storage = LLVMArgVtypeInReg;
1306 for (j = 0; j < 2; ++j)
1307 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1311 if (mini_type_is_vtype (sig_ret
) && cinfo
->ret
.storage
== ArgInIReg
) {
1312 /* Vtype returned using a hidden argument */
1313 linfo
->ret
.storage
= LLVMArgVtypeRetAddr
;
1314 linfo
->vret_arg_index
= cinfo
->vret_arg_index
;
1317 if (mini_type_is_vtype (sig_ret
) && cinfo
->ret
.storage
!= ArgInIReg
) {
1319 cfg
->exception_message
= g_strdup ("vtype ret in call");
1320 cfg
->disable_llvm
= TRUE
;
1323 for (i
= 0; i
< n
; ++i
) {
1324 ainfo
= cinfo
->args
+ i
;
1326 if (i
>= sig
->hasthis
)
1327 t
= sig
->params
[i
- sig
->hasthis
];
1329 t
= mono_get_int_type ();
1331 linfo
->args
[i
].storage
= LLVMArgNone
;
1333 switch (ainfo
->storage
) {
1335 linfo
->args
[i
].storage
= LLVMArgNormal
;
1337 case ArgInDoubleSSEReg
:
1338 case ArgInFloatSSEReg
:
1339 linfo
->args
[i
].storage
= LLVMArgNormal
;
1342 if (mini_type_is_vtype (t
)) {
1343 if (mono_class_value_size (mono_class_from_mono_type_internal (t
), NULL
) == 0)
1344 /* LLVM seems to allocate argument space for empty structures too */
1345 linfo
->args
[i
].storage
= LLVMArgNone
;
1347 linfo
->args
[i
].storage
= LLVMArgVtypeByVal
;
1349 linfo
->args
[i
].storage
= LLVMArgNormal
;
1352 case ArgValuetypeInReg
:
1354 cfg
->exception_message
= g_strdup ("pinvoke + vtypes");
1355 cfg
->disable_llvm
= TRUE
;
1359 cfg
->exception_message
= g_strdup ("vtype arg");
1360 cfg
->disable_llvm
= TRUE
;
1362 linfo->args [i].storage = LLVMArgVtypeInReg;
1363 for (j = 0; j < 2; ++j)
1364 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1368 linfo
->args
[i
].storage
= LLVMArgGSharedVt
;
1371 cfg
->exception_message
= g_strdup ("ainfo->storage");
1372 cfg
->disable_llvm
= TRUE
;
1382 emit_gc_param_slot_def (MonoCompile
*cfg
, int sp_offset
, MonoType
*t
)
1384 if (cfg
->compute_gc_maps
) {
1387 /* Needs checking if the feature will be enabled again */
1388 g_assert_not_reached ();
1390 /* On x86, the offsets are from the sp value before the start of the call sequence */
1392 t
= mono_get_int_type ();
1393 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg
, def
, sp_offset
, t
);
1398 mono_arch_emit_call (MonoCompile
*cfg
, MonoCallInst
*call
)
1402 MonoMethodSignature
*sig
;
1405 int sentinelpos
= 0, sp_offset
= 0;
1407 sig
= call
->signature
;
1408 n
= sig
->param_count
+ sig
->hasthis
;
1409 sig_ret
= mini_get_underlying_type (sig
->ret
);
1411 cinfo
= get_call_info (cfg
->mempool
, sig
);
1412 call
->call_info
= cinfo
;
1414 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
))
1415 sentinelpos
= sig
->sentinelpos
+ (sig
->hasthis
? 1 : 0);
1417 if (sig_ret
&& MONO_TYPE_ISSTRUCT (sig_ret
)) {
1418 if (cinfo
->ret
.storage
== ArgValuetypeInReg
&& cinfo
->ret
.pair_storage
[0] != ArgNone
) {
1420 * Tell the JIT to use a more efficient calling convention: call using
1421 * OP_CALL, compute the result location after the call, and save the
1424 call
->vret_in_reg
= TRUE
;
1425 #if defined (__APPLE__)
1426 if (cinfo
->ret
.pair_storage
[0] == ArgOnDoubleFpStack
|| cinfo
->ret
.pair_storage
[0] == ArgOnFloatFpStack
)
1427 call
->vret_in_reg_fp
= TRUE
;
1430 NULLIFY_INS (call
->vret_var
);
1434 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1436 /* Handle the case where there are no implicit arguments */
1437 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
) && (n
== sentinelpos
)) {
1438 emit_sig_cookie (cfg
, call
, cinfo
);
1439 sp_offset
= cinfo
->sig_cookie
.offset
;
1440 emit_gc_param_slot_def (cfg
, sp_offset
, NULL
);
1443 /* Arguments are pushed in the reverse order */
1444 for (i
= n
- 1; i
>= 0; i
--) {
1445 ArgInfo
*ainfo
= cinfo
->args
+ i
;
1446 MonoType
*orig_type
, *t
;
1449 if (cinfo
->vtype_retaddr
&& cinfo
->vret_arg_index
== 1 && i
== 0) {
1452 /* Push the vret arg before the first argument */
1453 MONO_INST_NEW (cfg
, vtarg
, OP_STORE_MEMBASE_REG
);
1454 vtarg
->type
= STACK_MP
;
1455 vtarg
->inst_destbasereg
= X86_ESP
;
1456 vtarg
->sreg1
= call
->vret_var
->dreg
;
1457 vtarg
->inst_offset
= cinfo
->ret
.offset
;
1458 MONO_ADD_INS (cfg
->cbb
, vtarg
);
1459 emit_gc_param_slot_def (cfg
, cinfo
->ret
.offset
, NULL
);
1462 if (i
>= sig
->hasthis
)
1463 t
= sig
->params
[i
- sig
->hasthis
];
1465 t
= mono_get_int_type ();
1467 t
= mini_get_underlying_type (t
);
1469 MONO_INST_NEW (cfg
, arg
, OP_X86_PUSH
);
1471 in
= call
->args
[i
];
1472 arg
->cil_code
= in
->cil_code
;
1473 arg
->sreg1
= in
->dreg
;
1474 arg
->type
= in
->type
;
1476 g_assert (in
->dreg
!= -1);
1478 if (ainfo
->storage
== ArgGSharedVt
) {
1479 arg
->opcode
= OP_OUTARG_VT
;
1480 arg
->sreg1
= in
->dreg
;
1481 arg
->klass
= in
->klass
;
1482 arg
->inst_p1
= mono_mempool_alloc (cfg
->mempool
, sizeof (ArgInfo
));
1483 memcpy (arg
->inst_p1
, ainfo
, sizeof (ArgInfo
));
1485 MONO_ADD_INS (cfg
->cbb
, arg
);
1486 } else if ((i
>= sig
->hasthis
) && (MONO_TYPE_ISSTRUCT(t
))) {
1490 g_assert (in
->klass
);
1492 if (t
->type
== MONO_TYPE_TYPEDBYREF
) {
1493 size
= MONO_ABI_SIZEOF (MonoTypedRef
);
1494 align
= sizeof (target_mgreg_t
);
1497 size
= mini_type_stack_size_full (m_class_get_byval_arg (in
->klass
), &align
, sig
->pinvoke
);
1500 if (size
> 0 || ainfo
->pass_empty_struct
) {
1501 arg
->opcode
= OP_OUTARG_VT
;
1502 arg
->sreg1
= in
->dreg
;
1503 arg
->klass
= in
->klass
;
1504 arg
->backend
.size
= size
;
1505 arg
->inst_p0
= call
;
1506 arg
->inst_p1
= mono_mempool_alloc (cfg
->mempool
, sizeof (ArgInfo
));
1507 memcpy (arg
->inst_p1
, ainfo
, sizeof (ArgInfo
));
1509 MONO_ADD_INS (cfg
->cbb
, arg
);
1510 if (ainfo
->storage
!= ArgValuetypeInReg
) {
1511 emit_gc_param_slot_def (cfg
, ainfo
->offset
, orig_type
);
1515 switch (ainfo
->storage
) {
1518 if (t
->type
== MONO_TYPE_R4
) {
1519 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORER4_MEMBASE_REG
, X86_ESP
, ainfo
->offset
, in
->dreg
);
1521 } else if (t
->type
== MONO_TYPE_R8
) {
1522 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORER8_MEMBASE_REG
, X86_ESP
, ainfo
->offset
, in
->dreg
);
1524 } else if (t
->type
== MONO_TYPE_I8
|| t
->type
== MONO_TYPE_U8
) {
1525 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, X86_ESP
, ainfo
->offset
+ 4, MONO_LVREG_MS (in
->dreg
));
1526 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, X86_ESP
, ainfo
->offset
, MONO_LVREG_LS (in
->dreg
));
1529 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, X86_ESP
, ainfo
->offset
, in
->dreg
);
1533 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, X86_ESP
, ainfo
->offset
, in
->dreg
);
1538 arg
->opcode
= OP_MOVE
;
1539 arg
->dreg
= ainfo
->reg
;
1540 MONO_ADD_INS (cfg
->cbb
, arg
);
1544 g_assert_not_reached ();
1547 if (cfg
->compute_gc_maps
) {
1549 /* FIXME: The == STACK_OBJ check might be fragile ? */
1550 if (sig
->hasthis
&& i
== 0 && call
->args
[i
]->type
== STACK_OBJ
) {
1552 if (call
->need_unbox_trampoline
)
1553 /* The unbox trampoline transforms this into a managed pointer */
1554 emit_gc_param_slot_def (cfg
, ainfo
->offset
, m_class_get_this_arg (mono_defaults
.int_class
));
1556 emit_gc_param_slot_def (cfg
, ainfo
->offset
, mono_get_object_type ());
1558 emit_gc_param_slot_def (cfg
, ainfo
->offset
, orig_type
);
1562 for (j
= 0; j
< argsize
; j
+= 4)
1563 emit_gc_param_slot_def (cfg
, ainfo
->offset
+ j
, NULL
);
1568 if (!sig
->pinvoke
&& (sig
->call_convention
== MONO_CALL_VARARG
) && (i
== sentinelpos
)) {
1569 /* Emit the signature cookie just before the implicit arguments */
1570 emit_sig_cookie (cfg
, call
, cinfo
);
1571 emit_gc_param_slot_def (cfg
, cinfo
->sig_cookie
.offset
, NULL
);
1575 if (sig_ret
&& (MONO_TYPE_ISSTRUCT (sig_ret
) || cinfo
->vtype_retaddr
)) {
1578 if (cinfo
->ret
.storage
== ArgValuetypeInReg
) {
1581 else if (cinfo
->ret
.storage
== ArgInIReg
) {
1583 /* The return address is passed in a register */
1584 MONO_INST_NEW (cfg
, vtarg
, OP_MOVE
);
1585 vtarg
->sreg1
= call
->inst
.dreg
;
1586 vtarg
->dreg
= mono_alloc_ireg (cfg
);
1587 MONO_ADD_INS (cfg
->cbb
, vtarg
);
1589 mono_call_inst_add_outarg_reg (cfg
, call
, vtarg
->dreg
, cinfo
->ret
.reg
, FALSE
);
1590 } else if (cinfo
->vtype_retaddr
&& cinfo
->vret_arg_index
== 0) {
1591 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, X86_ESP
, cinfo
->ret
.offset
, call
->vret_var
->dreg
);
1592 emit_gc_param_slot_def (cfg
, cinfo
->ret
.offset
, NULL
);
1596 call
->stack_usage
= cinfo
->stack_usage
;
1597 call
->stack_align_amount
= cinfo
->stack_align_amount
;
1601 mono_arch_emit_outarg_vt (MonoCompile
*cfg
, MonoInst
*ins
, MonoInst
*src
)
1603 MonoCallInst
*call
= (MonoCallInst
*)ins
->inst_p0
;
1604 ArgInfo
*ainfo
= (ArgInfo
*)ins
->inst_p1
;
1605 int size
= ins
->backend
.size
;
1607 if (ainfo
->storage
== ArgValuetypeInReg
) {
1608 int dreg
= mono_alloc_ireg (cfg
);
1611 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg
, OP_LOADU1_MEMBASE
, dreg
, src
->dreg
, 0);
1614 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg
, OP_LOADU2_MEMBASE
, dreg
, src
->dreg
, 0);
1617 MONO_EMIT_NEW_LOAD_MEMBASE (cfg
, dreg
, src
->dreg
, 0);
1621 g_assert_not_reached ();
1623 mono_call_inst_add_outarg_reg (cfg
, call
, dreg
, ainfo
->reg
, FALSE
);
1626 if (cfg
->gsharedvt
&& mini_is_gsharedvt_klass (ins
->klass
)) {
1628 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, X86_ESP
, ainfo
->offset
, src
->dreg
);
1629 } else if (size
<= 4) {
1630 int dreg
= mono_alloc_ireg (cfg
);
1631 if (ainfo
->pass_empty_struct
) {
1632 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
1633 MONO_EMIT_NEW_ICONST (cfg
, dreg
, 0);
1635 MONO_EMIT_NEW_LOAD_MEMBASE (cfg
, dreg
, src
->dreg
, 0);
1637 MONO_EMIT_NEW_STORE_MEMBASE (cfg
, OP_STORE_MEMBASE_REG
, X86_ESP
, ainfo
->offset
, dreg
);
1638 } else if (size
<= 20) {
1639 mini_emit_memcpy (cfg
, X86_ESP
, ainfo
->offset
, src
->dreg
, 0, size
, 4);
1641 // FIXME: Code growth
1642 mini_emit_memcpy (cfg
, X86_ESP
, ainfo
->offset
, src
->dreg
, 0, size
, 4);
1648 mono_arch_emit_setret (MonoCompile
*cfg
, MonoMethod
*method
, MonoInst
*val
)
1650 MonoType
*ret
= mini_get_underlying_type (mono_method_signature_internal (method
)->ret
);
1653 if (ret
->type
== MONO_TYPE_R4
) {
1654 if (COMPILE_LLVM (cfg
))
1655 MONO_EMIT_NEW_UNALU (cfg
, OP_FMOVE
, cfg
->ret
->dreg
, val
->dreg
);
1658 } else if (ret
->type
== MONO_TYPE_R8
) {
1659 if (COMPILE_LLVM (cfg
))
1660 MONO_EMIT_NEW_UNALU (cfg
, OP_FMOVE
, cfg
->ret
->dreg
, val
->dreg
);
1663 } else if (ret
->type
== MONO_TYPE_I8
|| ret
->type
== MONO_TYPE_U8
) {
1664 if (COMPILE_LLVM (cfg
))
1665 MONO_EMIT_NEW_UNALU (cfg
, OP_LMOVE
, cfg
->ret
->dreg
, val
->dreg
);
1667 MONO_EMIT_NEW_UNALU (cfg
, OP_MOVE
, X86_EAX
, MONO_LVREG_LS (val
->dreg
));
1668 MONO_EMIT_NEW_UNALU (cfg
, OP_MOVE
, X86_EDX
, MONO_LVREG_MS (val
->dreg
));
1674 MONO_EMIT_NEW_UNALU (cfg
, OP_MOVE
, cfg
->ret
->dreg
, val
->dreg
);
1677 #define EMIT_COND_BRANCH(ins,cond,sign) \
1678 if (ins->inst_true_bb->native_offset) { \
1679 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1681 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1682 if ((cfg->opt & MONO_OPT_BRANCH) && \
1683 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1684 x86_branch8 (code, cond, 0, sign); \
1686 x86_branch32 (code, cond, 0, sign); \
1690 * Emit an exception if condition is fail and
1691 * if possible do a directly branch to target
1693 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1695 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1696 if (tins == NULL) { \
1697 mono_add_patch_info (cfg, code - cfg->native_code, \
1698 MONO_PATCH_INFO_EXC, exc_name); \
1699 x86_branch32 (code, cond, 0, signed); \
1701 EMIT_COND_BRANCH (tins, cond, signed); \
1705 #define EMIT_FPCOMPARE(code) do { \
1706 x86_fcompp (code); \
1707 x86_fnstsw (code); \
1711 x86_align_and_patch (MonoCompile
*cfg
, guint8
*code
, guint32 patch_type
, gconstpointer data
)
1713 gboolean needs_paddings
= TRUE
;
1715 MonoJumpInfo
*jinfo
= NULL
;
1717 if (cfg
->abs_patches
) {
1718 jinfo
= (MonoJumpInfo
*)g_hash_table_lookup (cfg
->abs_patches
, data
);
1719 if (jinfo
&& (jinfo
->type
== MONO_PATCH_INFO_JIT_ICALL_ADDR
1720 || jinfo
->type
== MONO_PATCH_INFO_SPECIFIC_TRAMPOLINE_LAZY_FETCH_ADDR
))
1721 needs_paddings
= FALSE
;
1724 if (cfg
->compile_aot
)
1725 needs_paddings
= FALSE
;
1726 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1727 This is required for code patching to be safe on SMP machines.
1729 pad_size
= (guint32
)(code
+ 1 - cfg
->native_code
) & 0x3;
1730 if (needs_paddings
&& pad_size
)
1731 x86_padding (code
, 4 - pad_size
);
1733 mono_add_patch_info (cfg
, code
- cfg
->native_code
, (MonoJumpInfoType
)patch_type
, data
);
1739 emit_call (MonoCompile
*cfg
, guint8
*code
, guint32 patch_type
, gconstpointer data
)
1741 code
= x86_align_and_patch (cfg
, code
, patch_type
, data
);
1743 x86_call_code (code
, 0);
1748 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1751 * mono_peephole_pass_1:
1753 * Perform peephole opts which should/can be performed before local regalloc
1756 mono_arch_peephole_pass_1 (MonoCompile
*cfg
, MonoBasicBlock
*bb
)
1760 MONO_BB_FOR_EACH_INS_SAFE (bb
, n
, ins
) {
1761 MonoInst
*last_ins
= mono_inst_prev (ins
, FILTER_IL_SEQ_POINT
);
1763 switch (ins
->opcode
) {
1766 if ((ins
->sreg1
< MONO_MAX_IREGS
) && (ins
->dreg
>= MONO_MAX_IREGS
)) {
1768 * X86_LEA is like ADD, but doesn't have the
1769 * sreg1==dreg restriction.
1771 ins
->opcode
= OP_X86_LEA_MEMBASE
;
1772 ins
->inst_basereg
= ins
->sreg1
;
1773 } else if ((ins
->inst_imm
== 1) && (ins
->dreg
== ins
->sreg1
))
1774 ins
->opcode
= OP_X86_INC_REG
;
1778 if ((ins
->sreg1
< MONO_MAX_IREGS
) && (ins
->dreg
>= MONO_MAX_IREGS
)) {
1779 ins
->opcode
= OP_X86_LEA_MEMBASE
;
1780 ins
->inst_basereg
= ins
->sreg1
;
1781 ins
->inst_imm
= -ins
->inst_imm
;
1782 } else if ((ins
->inst_imm
== 1) && (ins
->dreg
== ins
->sreg1
))
1783 ins
->opcode
= OP_X86_DEC_REG
;
1785 case OP_COMPARE_IMM
:
1786 case OP_ICOMPARE_IMM
:
1787 /* OP_COMPARE_IMM (reg, 0)
1789 * OP_X86_TEST_NULL (reg)
1792 ins
->opcode
= OP_X86_TEST_NULL
;
1794 case OP_X86_COMPARE_MEMBASE_IMM
:
1796 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1797 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1799 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1800 * OP_COMPARE_IMM reg, imm
1802 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1804 if (last_ins
&& (last_ins
->opcode
== OP_STOREI4_MEMBASE_REG
) &&
1805 ins
->inst_basereg
== last_ins
->inst_destbasereg
&&
1806 ins
->inst_offset
== last_ins
->inst_offset
) {
1807 ins
->opcode
= OP_COMPARE_IMM
;
1808 ins
->sreg1
= last_ins
->sreg1
;
1810 /* check if we can remove cmp reg,0 with test null */
1812 ins
->opcode
= OP_X86_TEST_NULL
;
1816 case OP_X86_PUSH_MEMBASE
:
1817 if (last_ins
&& (last_ins
->opcode
== OP_STOREI4_MEMBASE_REG
||
1818 last_ins
->opcode
== OP_STORE_MEMBASE_REG
) &&
1819 ins
->inst_basereg
== last_ins
->inst_destbasereg
&&
1820 ins
->inst_offset
== last_ins
->inst_offset
) {
1821 ins
->opcode
= OP_X86_PUSH
;
1822 ins
->sreg1
= last_ins
->sreg1
;
1827 mono_peephole_ins (bb
, ins
);
1832 mono_arch_peephole_pass_2 (MonoCompile
*cfg
, MonoBasicBlock
*bb
)
1836 MONO_BB_FOR_EACH_INS_SAFE (bb
, n
, ins
) {
1837 switch (ins
->opcode
) {
1839 /* reg = 0 -> XOR (reg, reg) */
1840 /* XOR sets cflags on x86, so we cant do it always */
1841 if (ins
->inst_c0
== 0 && (!ins
->next
|| (ins
->next
&& INST_IGNORES_CFLAGS (ins
->next
->opcode
)))) {
1844 ins
->opcode
= OP_IXOR
;
1845 ins
->sreg1
= ins
->dreg
;
1846 ins
->sreg2
= ins
->dreg
;
1849 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1850 * since it takes 3 bytes instead of 7.
1852 for (ins2
= mono_inst_next (ins
, FILTER_IL_SEQ_POINT
); ins2
; ins2
= ins2
->next
) {
1853 if ((ins2
->opcode
== OP_STORE_MEMBASE_IMM
) && (ins2
->inst_imm
== 0)) {
1854 ins2
->opcode
= OP_STORE_MEMBASE_REG
;
1855 ins2
->sreg1
= ins
->dreg
;
1857 else if ((ins2
->opcode
== OP_STOREI4_MEMBASE_IMM
) && (ins2
->inst_imm
== 0)) {
1858 ins2
->opcode
= OP_STOREI4_MEMBASE_REG
;
1859 ins2
->sreg1
= ins
->dreg
;
1861 else if ((ins2
->opcode
== OP_STOREI1_MEMBASE_IMM
) || (ins2
->opcode
== OP_STOREI2_MEMBASE_IMM
)) {
1862 /* Continue iteration */
1871 if ((ins
->inst_imm
== 1) && (ins
->dreg
== ins
->sreg1
))
1872 ins
->opcode
= OP_X86_INC_REG
;
1876 if ((ins
->inst_imm
== 1) && (ins
->dreg
== ins
->sreg1
))
1877 ins
->opcode
= OP_X86_DEC_REG
;
1881 mono_peephole_ins (bb
, ins
);
1885 #define NEW_INS(cfg,ins,dest,op) do { \
1886 MONO_INST_NEW ((cfg), (dest), (op)); \
1887 (dest)->cil_code = (ins)->cil_code; \
1888 mono_bblock_insert_before_ins (bb, ins, (dest)); \
1892 * mono_arch_lowering_pass:
1894 * Converts complex opcodes into simpler ones so that each IR instruction
1895 * corresponds to one machine instruction.
1898 mono_arch_lowering_pass (MonoCompile
*cfg
, MonoBasicBlock
*bb
)
1900 MonoInst
*ins
, *next
;
1903 * FIXME: Need to add more instructions, but the current machine
1904 * description can't model some parts of the composite instructions like
1907 MONO_BB_FOR_EACH_INS_SAFE (bb
, next
, ins
) {
1908 switch (ins
->opcode
) {
1911 case OP_IDIV_UN_IMM
:
1912 case OP_IREM_UN_IMM
:
1914 * Keep the cases where we could generated optimized code, otherwise convert
1915 * to the non-imm variant.
1917 if ((ins
->opcode
== OP_IREM_IMM
) && mono_is_power_of_two (ins
->inst_imm
) >= 0)
1919 mono_decompose_op_imm (cfg
, bb
, ins
);
1921 #ifdef MONO_ARCH_SIMD_INTRINSICS
1922 case OP_EXPAND_I1
: {
1924 int temp_reg1
= mono_alloc_ireg (cfg
);
1925 int temp_reg2
= mono_alloc_ireg (cfg
);
1926 int original_reg
= ins
->sreg1
;
1928 NEW_INS (cfg
, ins
, temp
, OP_ICONV_TO_U1
);
1929 temp
->sreg1
= original_reg
;
1930 temp
->dreg
= temp_reg1
;
1932 NEW_INS (cfg
, ins
, temp
, OP_SHL_IMM
);
1933 temp
->sreg1
= temp_reg1
;
1934 temp
->dreg
= temp_reg2
;
1937 NEW_INS (cfg
, ins
, temp
, OP_IOR
);
1938 temp
->sreg1
= temp
->dreg
= temp_reg2
;
1939 temp
->sreg2
= temp_reg1
;
1941 ins
->opcode
= OP_EXPAND_I2
;
1942 ins
->sreg1
= temp_reg2
;
1951 bb
->max_vreg
= cfg
->next_vreg
;
1955 branch_cc_table
[] = {
1956 X86_CC_EQ
, X86_CC_GE
, X86_CC_GT
, X86_CC_LE
, X86_CC_LT
,
1957 X86_CC_NE
, X86_CC_GE
, X86_CC_GT
, X86_CC_LE
, X86_CC_LT
,
1958 X86_CC_O
, X86_CC_NO
, X86_CC_C
, X86_CC_NC
1961 /* Maps CMP_... constants to X86_CC_... constants */
1964 X86_CC_EQ
, X86_CC_NE
, X86_CC_LE
, X86_CC_GE
, X86_CC_LT
, X86_CC_GT
,
1965 X86_CC_LE
, X86_CC_GE
, X86_CC_LT
, X86_CC_GT
1969 cc_signed_table
[] = {
1970 TRUE
, TRUE
, TRUE
, TRUE
, TRUE
, TRUE
,
1971 FALSE
, FALSE
, FALSE
, FALSE
1974 static unsigned char*
1975 emit_float_to_int (MonoCompile
*cfg
, guchar
*code
, int dreg
, int size
, gboolean is_signed
)
1977 #define XMM_TEMP_REG 0
1978 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
1979 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
1980 if (cfg
->opt
& MONO_OPT_SSE2
&& size
< 8 && !(cfg
->opt
& MONO_OPT_SIMD
)) {
1981 /* optimize by assigning a local var for this use so we avoid
1982 * the stack manipulations */
1983 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, 8);
1984 x86_fst_membase (code
, X86_ESP
, 0, TRUE
, TRUE
);
1985 x86_movsd_reg_membase (code
, XMM_TEMP_REG
, X86_ESP
, 0);
1986 x86_cvttsd2si (code
, dreg
, XMM_TEMP_REG
);
1987 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 8);
1989 x86_widen_reg (code
, dreg
, dreg
, is_signed
, FALSE
);
1991 x86_widen_reg (code
, dreg
, dreg
, is_signed
, TRUE
);
1994 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, 4);
1995 x86_fnstcw_membase(code
, X86_ESP
, 0);
1996 x86_mov_reg_membase (code
, dreg
, X86_ESP
, 0, 2);
1997 x86_alu_reg_imm (code
, X86_OR
, dreg
, 0xc00);
1998 x86_mov_membase_reg (code
, X86_ESP
, 2, dreg
, 2);
1999 x86_fldcw_membase (code
, X86_ESP
, 2);
2001 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, 8);
2002 x86_fist_pop_membase (code
, X86_ESP
, 0, TRUE
);
2003 x86_pop_reg (code
, dreg
);
2004 /* FIXME: need the high register
2005 * x86_pop_reg (code, dreg_high);
2008 x86_push_reg (code
, X86_EAX
); // SP = SP - 4
2009 x86_fist_pop_membase (code
, X86_ESP
, 0, FALSE
);
2010 x86_pop_reg (code
, dreg
);
2012 x86_fldcw_membase (code
, X86_ESP
, 0);
2013 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 4);
2016 x86_widen_reg (code
, dreg
, dreg
, is_signed
, FALSE
);
2018 x86_widen_reg (code
, dreg
, dreg
, is_signed
, TRUE
);
2022 static unsigned char*
2023 mono_emit_stack_alloc (MonoCompile
*cfg
, guchar
*code
, MonoInst
* tree
)
2025 int sreg
= tree
->sreg1
;
2026 int need_touch
= FALSE
;
2028 #if defined (TARGET_WIN32) || defined (MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2037 * If requested stack size is larger than one page,
2038 * perform stack-touch operation
2041 * Generate stack probe code.
2042 * Under Windows, it is necessary to allocate one page at a time,
2043 * "touching" stack after each successful sub-allocation. This is
2044 * because of the way stack growth is implemented - there is a
2045 * guard page before the lowest stack page that is currently commited.
2046 * Stack normally grows sequentially so OS traps access to the
2047 * guard page and commits more pages when needed.
2049 x86_test_reg_imm (code
, sreg
, ~0xFFF);
2050 br
[0] = code
; x86_branch8 (code
, X86_CC_Z
, 0, FALSE
);
2052 br
[2] = code
; /* loop */
2053 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, 0x1000);
2054 x86_test_membase_reg (code
, X86_ESP
, 0, X86_ESP
);
2057 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2058 * that follows only initializes the last part of the area.
2060 /* Same as the init code below with size==0x1000 */
2061 if (tree
->flags
& MONO_INST_INIT
) {
2062 x86_push_reg (code
, X86_EAX
);
2063 x86_push_reg (code
, X86_ECX
);
2064 x86_push_reg (code
, X86_EDI
);
2065 x86_mov_reg_imm (code
, X86_ECX
, (0x1000 >> 2));
2066 x86_alu_reg_reg (code
, X86_XOR
, X86_EAX
, X86_EAX
);
2067 if (cfg
->param_area
)
2068 x86_lea_membase (code
, X86_EDI
, X86_ESP
, 12 + ALIGN_TO (cfg
->param_area
, MONO_ARCH_FRAME_ALIGNMENT
));
2070 x86_lea_membase (code
, X86_EDI
, X86_ESP
, 12);
2072 x86_prefix (code
, X86_REP_PREFIX
);
2074 x86_pop_reg (code
, X86_EDI
);
2075 x86_pop_reg (code
, X86_ECX
);
2076 x86_pop_reg (code
, X86_EAX
);
2079 x86_alu_reg_imm (code
, X86_SUB
, sreg
, 0x1000);
2080 x86_alu_reg_imm (code
, X86_CMP
, sreg
, 0x1000);
2081 br
[3] = code
; x86_branch8 (code
, X86_CC_AE
, 0, FALSE
);
2082 x86_patch (br
[3], br
[2]);
2083 x86_test_reg_reg (code
, sreg
, sreg
);
2084 br
[4] = code
; x86_branch8 (code
, X86_CC_Z
, 0, FALSE
);
2085 x86_alu_reg_reg (code
, X86_SUB
, X86_ESP
, sreg
);
2087 br
[1] = code
; x86_jump8 (code
, 0);
2089 x86_patch (br
[0], code
);
2090 x86_alu_reg_reg (code
, X86_SUB
, X86_ESP
, sreg
);
2091 x86_patch (br
[1], code
);
2092 x86_patch (br
[4], code
);
2095 x86_alu_reg_reg (code
, X86_SUB
, X86_ESP
, tree
->sreg1
);
2097 if (tree
->flags
& MONO_INST_INIT
) {
2099 if (tree
->dreg
!= X86_EAX
&& sreg
!= X86_EAX
) {
2100 x86_push_reg (code
, X86_EAX
);
2103 if (tree
->dreg
!= X86_ECX
&& sreg
!= X86_ECX
) {
2104 x86_push_reg (code
, X86_ECX
);
2107 if (tree
->dreg
!= X86_EDI
&& sreg
!= X86_EDI
) {
2108 x86_push_reg (code
, X86_EDI
);
2112 x86_shift_reg_imm (code
, X86_SHR
, sreg
, 2);
2113 x86_mov_reg_reg (code
, X86_ECX
, sreg
);
2114 x86_alu_reg_reg (code
, X86_XOR
, X86_EAX
, X86_EAX
);
2116 if (cfg
->param_area
)
2117 x86_lea_membase (code
, X86_EDI
, X86_ESP
, offset
+ ALIGN_TO (cfg
->param_area
, MONO_ARCH_FRAME_ALIGNMENT
));
2119 x86_lea_membase (code
, X86_EDI
, X86_ESP
, offset
);
2121 x86_prefix (code
, X86_REP_PREFIX
);
2124 if (tree
->dreg
!= X86_EDI
&& sreg
!= X86_EDI
)
2125 x86_pop_reg (code
, X86_EDI
);
2126 if (tree
->dreg
!= X86_ECX
&& sreg
!= X86_ECX
)
2127 x86_pop_reg (code
, X86_ECX
);
2128 if (tree
->dreg
!= X86_EAX
&& sreg
!= X86_EAX
)
2129 x86_pop_reg (code
, X86_EAX
);
2136 emit_move_return_value (MonoCompile
*cfg
, MonoInst
*ins
, guint8
*code
)
2138 /* Move return value to the target register */
2139 switch (ins
->opcode
) {
2142 case OP_CALL_MEMBASE
:
2143 x86_mov_reg_reg (code
, ins
->dreg
, X86_EAX
);
2153 static int tls_gs_offset
;
2157 mono_arch_have_fast_tls (void)
2160 static gboolean have_fast_tls
= FALSE
;
2161 static gboolean inited
= FALSE
;
2164 if (mini_debug_options
.use_fallback_tls
)
2167 return have_fast_tls
;
2169 ins
= (guint32
*)pthread_getspecific
;
2171 * We're looking for these two instructions:
2173 * mov 0x4(%esp),%eax
2174 * mov %gs:[offset](,%eax,4),%eax
2176 have_fast_tls
= ins
[0] == 0x0424448b && ins
[1] == 0x85048b65;
2177 tls_gs_offset
= ins
[2];
2180 return have_fast_tls
;
2181 #elif defined(TARGET_ANDROID)
2184 if (mini_debug_options
.use_fallback_tls
)
2191 mono_x86_emit_tls_get (guint8
* code
, int dreg
, int tls_offset
)
2193 #if defined (TARGET_MACH)
2194 x86_prefix (code
, X86_GS_PREFIX
);
2195 x86_mov_reg_mem (code
, dreg
, tls_gs_offset
+ (tls_offset
* 4), 4);
2196 #elif defined (TARGET_WIN32)
2198 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2199 * Journal and/or a disassembly of the TlsGet () function.
2201 x86_prefix (code
, X86_FS_PREFIX
);
2202 x86_mov_reg_mem (code
, dreg
, 0x18, 4);
2203 if (tls_offset
< 64) {
2204 x86_mov_reg_membase (code
, dreg
, dreg
, 3600 + (tls_offset
* 4), 4);
2208 g_assert (tls_offset
< 0x440);
2209 /* Load TEB->TlsExpansionSlots */
2210 x86_mov_reg_membase (code
, dreg
, dreg
, 0xf94, 4);
2211 x86_test_reg_reg (code
, dreg
, dreg
);
2213 x86_branch (code
, X86_CC_EQ
, code
, TRUE
);
2214 x86_mov_reg_membase (code
, dreg
, dreg
, (tls_offset
* 4) - 0x100, 4);
2215 x86_patch (buf
[0], code
);
2218 if (optimize_for_xen
) {
2219 x86_prefix (code
, X86_GS_PREFIX
);
2220 x86_mov_reg_mem (code
, dreg
, 0, 4);
2221 x86_mov_reg_membase (code
, dreg
, dreg
, tls_offset
, 4);
2223 x86_prefix (code
, X86_GS_PREFIX
);
2224 x86_mov_reg_mem (code
, dreg
, tls_offset
, 4);
2231 mono_x86_emit_tls_set (guint8
* code
, int sreg
, int tls_offset
)
2233 #if defined (TARGET_MACH)
2234 x86_prefix (code
, X86_GS_PREFIX
);
2235 x86_mov_mem_reg (code
, tls_gs_offset
+ (tls_offset
* 4), sreg
, 4);
2236 #elif defined (TARGET_WIN32)
2237 g_assert_not_reached ();
2239 x86_prefix (code
, X86_GS_PREFIX
);
2240 x86_mov_mem_reg (code
, tls_offset
, sreg
, 4);
2248 * Emit code to initialize an LMF structure at LMF_OFFSET.
2251 emit_setup_lmf (MonoCompile
*cfg
, guint8
*code
, gint32 lmf_offset
, int cfa_offset
)
2253 /* save all caller saved regs */
2254 x86_mov_membase_reg (code
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, ebx
), X86_EBX
, sizeof (target_mgreg_t
));
2255 mono_emit_unwind_op_offset (cfg
, code
, X86_EBX
, - cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, ebx
));
2256 x86_mov_membase_reg (code
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, edi
), X86_EDI
, sizeof (target_mgreg_t
));
2257 mono_emit_unwind_op_offset (cfg
, code
, X86_EDI
, - cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, edi
));
2258 x86_mov_membase_reg (code
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, esi
), X86_ESI
, sizeof (target_mgreg_t
));
2259 mono_emit_unwind_op_offset (cfg
, code
, X86_ESI
, - cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, esi
));
2260 x86_mov_membase_reg (code
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, ebp
), X86_EBP
, sizeof (target_mgreg_t
));
2262 /* save the current IP */
2263 if (cfg
->compile_aot
) {
2264 /* This pushes the current ip */
2265 x86_call_imm (code
, 0);
2266 x86_pop_reg (code
, X86_EAX
);
2268 mono_add_patch_info (cfg
, code
+ 1 - cfg
->native_code
, MONO_PATCH_INFO_IP
, NULL
);
2269 x86_mov_reg_imm (code
, X86_EAX
, 0);
2271 x86_mov_membase_reg (code
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, eip
), X86_EAX
, sizeof (target_mgreg_t
));
2273 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, eip
), SLOT_NOREF
);
2274 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, ebp
), SLOT_NOREF
);
2275 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, esi
), SLOT_NOREF
);
2276 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, edi
), SLOT_NOREF
);
2277 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, ebx
), SLOT_NOREF
);
2278 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, esp
), SLOT_NOREF
);
2279 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, method
), SLOT_NOREF
);
2280 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, lmf_addr
), SLOT_NOREF
);
2281 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
+ lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, previous_lmf
), SLOT_NOREF
);
2288 #define TEB_LAST_ERROR_OFFSET 0x34
2291 emit_get_last_error (guint8
* code
, int dreg
)
2293 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
2294 x86_prefix (code
, X86_FS_PREFIX
);
2295 x86_mov_reg_mem (code
, dreg
, TEB_LAST_ERROR_OFFSET
, sizeof (guint32
));
2302 emit_get_last_error (guint8
* code
, int dreg
)
2304 g_assert_not_reached ();
2309 /* benchmark and set based on cpu */
2310 #define LOOP_ALIGNMENT 8
2311 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2315 mono_arch_output_basic_block (MonoCompile
*cfg
, MonoBasicBlock
*bb
)
2319 guint8
*code
= cfg
->native_code
+ cfg
->code_len
;
2321 if (cfg
->opt
& MONO_OPT_LOOP
) {
2322 int pad
, align
= LOOP_ALIGNMENT
;
2323 /* set alignment depending on cpu */
2324 if (bb_is_loop_start (bb
) && (pad
= (cfg
->code_len
& (align
- 1)))) {
2326 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2327 x86_padding (code
, pad
);
2328 cfg
->code_len
+= pad
;
2329 bb
->native_offset
= cfg
->code_len
;
2333 if (cfg
->verbose_level
> 2)
2334 g_print ("Basic block %d starting at offset 0x%x\n", bb
->block_num
, bb
->native_offset
);
2336 int cpos
= bb
->max_offset
;
2338 set_code_cursor (cfg
, code
);
2340 mono_debug_open_block (cfg
, bb
, code
- cfg
->native_code
);
2342 if (mono_break_at_bb_method
&& mono_method_desc_full_match (mono_break_at_bb_method
, cfg
->method
) && bb
->block_num
== mono_break_at_bb_bb_num
)
2343 x86_breakpoint (code
);
2345 MONO_BB_FOR_EACH_INS (bb
, ins
) {
2346 const guint offset
= code
- cfg
->native_code
;
2347 set_code_cursor (cfg
, code
);
2348 int max_len
= ins_get_size (ins
->opcode
);
2349 code
= realloc_code (cfg
, max_len
);
2351 if (cfg
->debug_info
)
2352 mono_debug_record_line_number (cfg
, ins
, offset
);
2354 switch (ins
->opcode
) {
2356 x86_mul_reg (code
, ins
->sreg2
, TRUE
);
2359 x86_mul_reg (code
, ins
->sreg2
, FALSE
);
2361 case OP_X86_SETEQ_MEMBASE
:
2362 case OP_X86_SETNE_MEMBASE
:
2363 x86_set_membase (code
, ins
->opcode
== OP_X86_SETEQ_MEMBASE
? X86_CC_EQ
: X86_CC_NE
,
2364 ins
->inst_basereg
, ins
->inst_offset
, TRUE
);
2366 case OP_STOREI1_MEMBASE_IMM
:
2367 x86_mov_membase_imm (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->inst_imm
, 1);
2369 case OP_STOREI2_MEMBASE_IMM
:
2370 x86_mov_membase_imm (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->inst_imm
, 2);
2372 case OP_STORE_MEMBASE_IMM
:
2373 case OP_STOREI4_MEMBASE_IMM
:
2374 x86_mov_membase_imm (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->inst_imm
, 4);
2376 case OP_STOREI1_MEMBASE_REG
:
2377 x86_mov_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
, 1);
2379 case OP_STOREI2_MEMBASE_REG
:
2380 x86_mov_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
, 2);
2382 case OP_STORE_MEMBASE_REG
:
2383 case OP_STOREI4_MEMBASE_REG
:
2384 x86_mov_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
, 4);
2386 case OP_STORE_MEM_IMM
:
2387 x86_mov_mem_imm (code
, ins
->inst_p0
, ins
->inst_c0
, 4);
2390 x86_mov_reg_mem (code
, ins
->dreg
, ins
->inst_imm
, 4);
2394 /* These are created by the cprop pass so they use inst_imm as the source */
2395 x86_mov_reg_mem (code
, ins
->dreg
, ins
->inst_imm
, 4);
2398 x86_widen_mem (code
, ins
->dreg
, ins
->inst_imm
, FALSE
, FALSE
);
2401 x86_widen_mem (code
, ins
->dreg
, ins
->inst_imm
, FALSE
, TRUE
);
2403 case OP_LOAD_MEMBASE
:
2404 case OP_LOADI4_MEMBASE
:
2405 case OP_LOADU4_MEMBASE
:
2406 x86_mov_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, 4);
2408 case OP_LOADU1_MEMBASE
:
2409 x86_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, FALSE
, FALSE
);
2411 case OP_LOADI1_MEMBASE
:
2412 x86_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
, FALSE
);
2414 case OP_LOADU2_MEMBASE
:
2415 x86_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, FALSE
, TRUE
);
2417 case OP_LOADI2_MEMBASE
:
2418 x86_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
, TRUE
);
2420 case OP_ICONV_TO_I1
:
2422 x86_widen_reg (code
, ins
->dreg
, ins
->sreg1
, TRUE
, FALSE
);
2424 case OP_ICONV_TO_I2
:
2426 x86_widen_reg (code
, ins
->dreg
, ins
->sreg1
, TRUE
, TRUE
);
2428 case OP_ICONV_TO_U1
:
2429 x86_widen_reg (code
, ins
->dreg
, ins
->sreg1
, FALSE
, FALSE
);
2431 case OP_ICONV_TO_U2
:
2432 x86_widen_reg (code
, ins
->dreg
, ins
->sreg1
, FALSE
, TRUE
);
2436 x86_alu_reg_reg (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
);
2438 case OP_COMPARE_IMM
:
2439 case OP_ICOMPARE_IMM
:
2440 x86_alu_reg_imm (code
, X86_CMP
, ins
->sreg1
, ins
->inst_imm
);
2442 case OP_X86_COMPARE_MEMBASE_REG
:
2443 x86_alu_membase_reg (code
, X86_CMP
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
);
2445 case OP_X86_COMPARE_MEMBASE_IMM
:
2446 x86_alu_membase_imm (code
, X86_CMP
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
);
2448 case OP_X86_COMPARE_MEMBASE8_IMM
:
2449 x86_alu_membase8_imm (code
, X86_CMP
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
);
2451 case OP_X86_COMPARE_REG_MEMBASE
:
2452 x86_alu_reg_membase (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
);
2454 case OP_X86_COMPARE_MEM_IMM
:
2455 x86_alu_mem_imm (code
, X86_CMP
, ins
->inst_offset
, ins
->inst_imm
);
2457 case OP_X86_TEST_NULL
:
2458 x86_test_reg_reg (code
, ins
->sreg1
, ins
->sreg1
);
2460 case OP_X86_ADD_MEMBASE_IMM
:
2461 x86_alu_membase_imm (code
, X86_ADD
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
);
2463 case OP_X86_ADD_REG_MEMBASE
:
2464 x86_alu_reg_membase (code
, X86_ADD
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
);
2466 case OP_X86_SUB_MEMBASE_IMM
:
2467 x86_alu_membase_imm (code
, X86_SUB
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
);
2469 case OP_X86_SUB_REG_MEMBASE
:
2470 x86_alu_reg_membase (code
, X86_SUB
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
);
2472 case OP_X86_AND_MEMBASE_IMM
:
2473 x86_alu_membase_imm (code
, X86_AND
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
);
2475 case OP_X86_OR_MEMBASE_IMM
:
2476 x86_alu_membase_imm (code
, X86_OR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
);
2478 case OP_X86_XOR_MEMBASE_IMM
:
2479 x86_alu_membase_imm (code
, X86_XOR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->inst_imm
);
2481 case OP_X86_ADD_MEMBASE_REG
:
2482 x86_alu_membase_reg (code
, X86_ADD
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
);
2484 case OP_X86_SUB_MEMBASE_REG
:
2485 x86_alu_membase_reg (code
, X86_SUB
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
);
2487 case OP_X86_AND_MEMBASE_REG
:
2488 x86_alu_membase_reg (code
, X86_AND
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
);
2490 case OP_X86_OR_MEMBASE_REG
:
2491 x86_alu_membase_reg (code
, X86_OR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
);
2493 case OP_X86_XOR_MEMBASE_REG
:
2494 x86_alu_membase_reg (code
, X86_XOR
, ins
->inst_basereg
, ins
->inst_offset
, ins
->sreg2
);
2496 case OP_X86_INC_MEMBASE
:
2497 x86_inc_membase (code
, ins
->inst_basereg
, ins
->inst_offset
);
2499 case OP_X86_INC_REG
:
2500 x86_inc_reg (code
, ins
->dreg
);
2502 case OP_X86_DEC_MEMBASE
:
2503 x86_dec_membase (code
, ins
->inst_basereg
, ins
->inst_offset
);
2505 case OP_X86_DEC_REG
:
2506 x86_dec_reg (code
, ins
->dreg
);
2508 case OP_X86_MUL_REG_MEMBASE
:
2509 x86_imul_reg_membase (code
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
);
2511 case OP_X86_AND_REG_MEMBASE
:
2512 x86_alu_reg_membase (code
, X86_AND
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
);
2514 case OP_X86_OR_REG_MEMBASE
:
2515 x86_alu_reg_membase (code
, X86_OR
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
);
2517 case OP_X86_XOR_REG_MEMBASE
:
2518 x86_alu_reg_membase (code
, X86_XOR
, ins
->sreg1
, ins
->sreg2
, ins
->inst_offset
);
2521 x86_breakpoint (code
);
2523 case OP_RELAXED_NOP
:
2524 x86_prefix (code
, X86_REP_PREFIX
);
2532 case OP_DUMMY_ICONST
:
2533 case OP_DUMMY_R8CONST
:
2534 case OP_DUMMY_R4CONST
:
2535 case OP_NOT_REACHED
:
2538 case OP_IL_SEQ_POINT
:
2539 mono_add_seq_point (cfg
, bb
, ins
, code
- cfg
->native_code
);
2541 case OP_SEQ_POINT
: {
2544 if (cfg
->compile_aot
)
2547 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2550 * We do this _before_ the breakpoint, so single stepping after
2551 * a breakpoint is hit will step to the next IL offset.
2553 if (ins
->flags
& MONO_INST_SINGLE_STEP_LOC
) {
2554 MonoInst
*var
= cfg
->arch
.ss_tramp_var
;
2558 g_assert (var
->opcode
== OP_REGOFFSET
);
2559 /* Load ss_tramp_var */
2560 /* This is equal to &ss_trampoline */
2561 x86_mov_reg_membase (code
, X86_ECX
, var
->inst_basereg
, var
->inst_offset
, sizeof (target_mgreg_t
));
2562 x86_mov_reg_membase (code
, X86_ECX
, X86_ECX
, 0, sizeof (target_mgreg_t
));
2563 x86_alu_reg_imm (code
, X86_CMP
, X86_ECX
, 0);
2564 br
[0] = code
; x86_branch8 (code
, X86_CC_EQ
, 0, FALSE
);
2565 x86_call_reg (code
, X86_ECX
);
2566 x86_patch (br
[0], code
);
2570 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2571 * This means we have to put the loading of bp_tramp_var after the offset.
2574 mono_add_seq_point (cfg
, bb
, ins
, code
- cfg
->native_code
);
2576 MonoInst
*var
= cfg
->arch
.bp_tramp_var
;
2579 g_assert (var
->opcode
== OP_REGOFFSET
);
2580 /* Load the address of the bp trampoline */
2581 /* This needs to be constant size */
2582 guint8
*start
= code
;
2583 x86_mov_reg_membase (code
, X86_ECX
, var
->inst_basereg
, var
->inst_offset
, 4);
2584 if (code
< start
+ OP_SEQ_POINT_BP_OFFSET
) {
2585 int size
= start
+ OP_SEQ_POINT_BP_OFFSET
- code
;
2586 x86_padding (code
, size
);
2589 * A placeholder for a possible breakpoint inserted by
2590 * mono_arch_set_breakpoint ().
2592 for (i
= 0; i
< 2; ++i
)
2595 * Add an additional nop so skipping the bp doesn't cause the ip to point
2596 * to another IL offset.
2604 x86_alu_reg_reg (code
, X86_ADD
, ins
->sreg1
, ins
->sreg2
);
2608 x86_alu_reg_reg (code
, X86_ADC
, ins
->sreg1
, ins
->sreg2
);
2613 x86_alu_reg_imm (code
, X86_ADD
, ins
->dreg
, ins
->inst_imm
);
2617 x86_alu_reg_imm (code
, X86_ADC
, ins
->dreg
, ins
->inst_imm
);
2622 x86_alu_reg_reg (code
, X86_SUB
, ins
->sreg1
, ins
->sreg2
);
2626 x86_alu_reg_reg (code
, X86_SBB
, ins
->sreg1
, ins
->sreg2
);
2631 x86_alu_reg_imm (code
, X86_SUB
, ins
->dreg
, ins
->inst_imm
);
2635 x86_alu_reg_imm (code
, X86_SBB
, ins
->dreg
, ins
->inst_imm
);
2638 x86_alu_reg_reg (code
, X86_AND
, ins
->sreg1
, ins
->sreg2
);
2642 x86_alu_reg_imm (code
, X86_AND
, ins
->sreg1
, ins
->inst_imm
);
2647 * The code is the same for div/rem, the allocator will allocate dreg
2648 * to RAX/RDX as appropriate.
2650 if (ins
->sreg2
== X86_EDX
) {
2651 /* cdq clobbers this */
2652 x86_push_reg (code
, ins
->sreg2
);
2654 x86_div_membase (code
, X86_ESP
, 0, TRUE
);
2655 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 4);
2658 x86_div_reg (code
, ins
->sreg2
, TRUE
);
2663 if (ins
->sreg2
== X86_EDX
) {
2664 x86_push_reg (code
, ins
->sreg2
);
2665 x86_alu_reg_reg (code
, X86_XOR
, X86_EDX
, X86_EDX
);
2666 x86_div_membase (code
, X86_ESP
, 0, FALSE
);
2667 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 4);
2669 x86_alu_reg_reg (code
, X86_XOR
, X86_EDX
, X86_EDX
);
2670 x86_div_reg (code
, ins
->sreg2
, FALSE
);
2674 x86_mov_reg_imm (code
, ins
->sreg2
, ins
->inst_imm
);
2676 x86_div_reg (code
, ins
->sreg2
, TRUE
);
2679 int power
= mono_is_power_of_two (ins
->inst_imm
);
2681 g_assert (ins
->sreg1
== X86_EAX
);
2682 g_assert (ins
->dreg
== X86_EAX
);
2683 g_assert (power
>= 0);
2686 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2688 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, 1);
2690 * If the divident is >= 0, this does not nothing. If it is positive, it
2691 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2693 x86_alu_reg_reg (code
, X86_XOR
, X86_EAX
, X86_EDX
);
2694 x86_alu_reg_reg (code
, X86_SUB
, X86_EAX
, X86_EDX
);
2695 } else if (power
== 0) {
2696 x86_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
2698 /* Based on gcc code */
2700 /* Add compensation for negative dividents */
2702 x86_shift_reg_imm (code
, X86_SHR
, X86_EDX
, 32 - power
);
2703 x86_alu_reg_reg (code
, X86_ADD
, X86_EAX
, X86_EDX
);
2704 /* Compute remainder */
2705 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, (1 << power
) - 1);
2706 /* Remove compensation */
2707 x86_alu_reg_reg (code
, X86_SUB
, X86_EAX
, X86_EDX
);
2712 x86_alu_reg_reg (code
, X86_OR
, ins
->sreg1
, ins
->sreg2
);
2716 x86_alu_reg_imm (code
, X86_OR
, ins
->sreg1
, ins
->inst_imm
);
2719 x86_alu_reg_reg (code
, X86_XOR
, ins
->sreg1
, ins
->sreg2
);
2723 x86_alu_reg_imm (code
, X86_XOR
, ins
->sreg1
, ins
->inst_imm
);
2726 g_assert (ins
->sreg2
== X86_ECX
);
2727 x86_shift_reg (code
, X86_SHL
, ins
->dreg
);
2730 g_assert (ins
->sreg2
== X86_ECX
);
2731 x86_shift_reg (code
, X86_SAR
, ins
->dreg
);
2735 x86_shift_reg_imm (code
, X86_SAR
, ins
->dreg
, ins
->inst_imm
);
2738 case OP_ISHR_UN_IMM
:
2739 x86_shift_reg_imm (code
, X86_SHR
, ins
->dreg
, ins
->inst_imm
);
2742 g_assert (ins
->sreg2
== X86_ECX
);
2743 x86_shift_reg (code
, X86_SHR
, ins
->dreg
);
2747 x86_shift_reg_imm (code
, X86_SHL
, ins
->dreg
, ins
->inst_imm
);
2750 guint8
*jump_to_end
;
2752 /* handle shifts below 32 bits */
2753 x86_shld_reg (code
, ins
->backend
.reg3
, ins
->sreg1
);
2754 x86_shift_reg (code
, X86_SHL
, ins
->sreg1
);
2756 x86_test_reg_imm (code
, X86_ECX
, 32);
2757 jump_to_end
= code
; x86_branch8 (code
, X86_CC_EQ
, 0, TRUE
);
2759 /* handle shift over 32 bit */
2760 x86_mov_reg_reg (code
, ins
->backend
.reg3
, ins
->sreg1
);
2761 x86_clear_reg (code
, ins
->sreg1
);
2763 x86_patch (jump_to_end
, code
);
2767 guint8
*jump_to_end
;
2769 /* handle shifts below 32 bits */
2770 x86_shrd_reg (code
, ins
->sreg1
, ins
->backend
.reg3
);
2771 x86_shift_reg (code
, X86_SAR
, ins
->backend
.reg3
);
2773 x86_test_reg_imm (code
, X86_ECX
, 32);
2774 jump_to_end
= code
; x86_branch8 (code
, X86_CC_EQ
, 0, FALSE
);
2776 /* handle shifts over 31 bits */
2777 x86_mov_reg_reg (code
, ins
->sreg1
, ins
->backend
.reg3
);
2778 x86_shift_reg_imm (code
, X86_SAR
, ins
->backend
.reg3
, 31);
2780 x86_patch (jump_to_end
, code
);
2784 guint8
*jump_to_end
;
2786 /* handle shifts below 32 bits */
2787 x86_shrd_reg (code
, ins
->sreg1
, ins
->backend
.reg3
);
2788 x86_shift_reg (code
, X86_SHR
, ins
->backend
.reg3
);
2790 x86_test_reg_imm (code
, X86_ECX
, 32);
2791 jump_to_end
= code
; x86_branch8 (code
, X86_CC_EQ
, 0, FALSE
);
2793 /* handle shifts over 31 bits */
2794 x86_mov_reg_reg (code
, ins
->sreg1
, ins
->backend
.reg3
);
2795 x86_clear_reg (code
, ins
->backend
.reg3
);
2797 x86_patch (jump_to_end
, code
);
2801 if (ins
->inst_imm
>= 32) {
2802 x86_mov_reg_reg (code
, ins
->backend
.reg3
, ins
->sreg1
);
2803 x86_clear_reg (code
, ins
->sreg1
);
2804 x86_shift_reg_imm (code
, X86_SHL
, ins
->backend
.reg3
, ins
->inst_imm
- 32);
2806 x86_shld_reg_imm (code
, ins
->backend
.reg3
, ins
->sreg1
, ins
->inst_imm
);
2807 x86_shift_reg_imm (code
, X86_SHL
, ins
->sreg1
, ins
->inst_imm
);
2811 if (ins
->inst_imm
>= 32) {
2812 x86_mov_reg_reg (code
, ins
->sreg1
, ins
->backend
.reg3
);
2813 x86_shift_reg_imm (code
, X86_SAR
, ins
->backend
.reg3
, 0x1f);
2814 x86_shift_reg_imm (code
, X86_SAR
, ins
->sreg1
, ins
->inst_imm
- 32);
2816 x86_shrd_reg_imm (code
, ins
->sreg1
, ins
->backend
.reg3
, ins
->inst_imm
);
2817 x86_shift_reg_imm (code
, X86_SAR
, ins
->backend
.reg3
, ins
->inst_imm
);
2820 case OP_LSHR_UN_IMM
:
2821 if (ins
->inst_imm
>= 32) {
2822 x86_mov_reg_reg (code
, ins
->sreg1
, ins
->backend
.reg3
);
2823 x86_clear_reg (code
, ins
->backend
.reg3
);
2824 x86_shift_reg_imm (code
, X86_SHR
, ins
->sreg1
, ins
->inst_imm
- 32);
2826 x86_shrd_reg_imm (code
, ins
->sreg1
, ins
->backend
.reg3
, ins
->inst_imm
);
2827 x86_shift_reg_imm (code
, X86_SHR
, ins
->backend
.reg3
, ins
->inst_imm
);
2831 x86_not_reg (code
, ins
->sreg1
);
2834 x86_neg_reg (code
, ins
->sreg1
);
2838 x86_imul_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
2842 switch (ins
->inst_imm
) {
2846 x86_mov_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
2847 x86_alu_reg_reg (code
, X86_ADD
, ins
->dreg
, ins
->dreg
);
2850 /* LEA r1, [r2 + r2*2] */
2851 x86_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 1);
2854 /* LEA r1, [r2 + r2*4] */
2855 x86_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 2);
2858 /* LEA r1, [r2 + r2*2] */
2860 x86_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 1);
2861 x86_alu_reg_reg (code
, X86_ADD
, ins
->dreg
, ins
->dreg
);
2864 /* LEA r1, [r2 + r2*8] */
2865 x86_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 3);
2868 /* LEA r1, [r2 + r2*4] */
2870 x86_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 2);
2871 x86_alu_reg_reg (code
, X86_ADD
, ins
->dreg
, ins
->dreg
);
2874 /* LEA r1, [r2 + r2*2] */
2876 x86_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 1);
2877 x86_shift_reg_imm (code
, X86_SHL
, ins
->dreg
, 2);
2880 /* LEA r1, [r2 + r2*4] */
2881 /* LEA r1, [r1 + r1*4] */
2882 x86_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 2);
2883 x86_lea_memindex (code
, ins
->dreg
, ins
->dreg
, 0, ins
->dreg
, 2);
2886 /* LEA r1, [r2 + r2*4] */
2888 /* LEA r1, [r1 + r1*4] */
2889 x86_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, 0, ins
->sreg1
, 2);
2890 x86_shift_reg_imm (code
, X86_SHL
, ins
->dreg
, 2);
2891 x86_lea_memindex (code
, ins
->dreg
, ins
->dreg
, 0, ins
->dreg
, 2);
2894 x86_imul_reg_reg_imm (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_imm
);
2899 x86_imul_reg_reg (code
, ins
->sreg1
, ins
->sreg2
);
2900 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O
, FALSE
, "OverflowException");
2902 case OP_IMUL_OVF_UN
: {
2903 /* the mul operation and the exception check should most likely be split */
2904 int non_eax_reg
, saved_eax
= FALSE
, saved_edx
= FALSE
;
2905 /*g_assert (ins->sreg2 == X86_EAX);
2906 g_assert (ins->dreg == X86_EAX);*/
2907 if (ins
->sreg2
== X86_EAX
) {
2908 non_eax_reg
= ins
->sreg1
;
2909 } else if (ins
->sreg1
== X86_EAX
) {
2910 non_eax_reg
= ins
->sreg2
;
2912 /* no need to save since we're going to store to it anyway */
2913 if (ins
->dreg
!= X86_EAX
) {
2915 x86_push_reg (code
, X86_EAX
);
2917 x86_mov_reg_reg (code
, X86_EAX
, ins
->sreg1
);
2918 non_eax_reg
= ins
->sreg2
;
2920 if (ins
->dreg
== X86_EDX
) {
2923 x86_push_reg (code
, X86_EAX
);
2927 x86_push_reg (code
, X86_EDX
);
2929 x86_mul_reg (code
, non_eax_reg
, FALSE
);
2930 /* save before the check since pop and mov don't change the flags */
2931 x86_mov_reg_reg (code
, ins
->dreg
, X86_EAX
);
2933 x86_pop_reg (code
, X86_EDX
);
2935 x86_pop_reg (code
, X86_EAX
);
2936 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O
, FALSE
, "OverflowException");
2940 x86_mov_reg_imm (code
, ins
->dreg
, ins
->inst_c0
);
2943 g_assert_not_reached ();
2944 mono_add_patch_info (cfg
, offset
, (MonoJumpInfoType
)(gsize
)ins
->inst_i1
, ins
->inst_p0
);
2945 x86_mov_reg_imm (code
, ins
->dreg
, 0);
2948 mono_add_patch_info (cfg
, offset
, (MonoJumpInfoType
)(gsize
)ins
->inst_i1
, ins
->inst_p0
);
2949 x86_mov_reg_imm (code
, ins
->dreg
, 0);
2951 case OP_LOAD_GOTADDR
:
2952 g_assert (ins
->dreg
== MONO_ARCH_GOT_REG
);
2953 code
= mono_arch_emit_load_got_addr (cfg
->native_code
, code
, cfg
, NULL
);
2956 mono_add_patch_info (cfg
, offset
, (MonoJumpInfoType
)(gsize
)ins
->inst_right
->inst_i1
, ins
->inst_right
->inst_p0
);
2957 x86_mov_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, 0xf0f0f0f0, 4);
2959 case OP_X86_PUSH_GOT_ENTRY
:
2960 mono_add_patch_info (cfg
, offset
, (MonoJumpInfoType
)(gsize
)ins
->inst_right
->inst_i1
, ins
->inst_right
->inst_p0
);
2961 x86_push_membase (code
, ins
->inst_basereg
, 0xf0f0f0f0);
2964 x86_mov_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
2967 case OP_TAILCALL_PARAMETER
:
2968 // This opcode helps compute sizes, i.e.
2969 // of the subsequent OP_TAILCALL, but contributes no code.
2970 g_assert (ins
->next
);
2974 case OP_TAILCALL_MEMBASE
:
2975 case OP_TAILCALL_REG
: {
2976 call
= (MonoCallInst
*)ins
;
2978 gboolean
const tailcall_membase
= ins
->opcode
== OP_TAILCALL_MEMBASE
;
2979 gboolean
const tailcall_reg
= (ins
->opcode
== OP_TAILCALL_REG
);
2980 int const sreg1
= ins
->sreg1
;
2981 gboolean
const sreg1_ecx
= sreg1
== X86_ECX
;
2982 gboolean
const tailcall_membase_ecx
= tailcall_membase
&& sreg1_ecx
;
2983 gboolean
const tailcall_membase_not_ecx
= tailcall_membase
&& !sreg1_ecx
;
2985 max_len
+= (call
->stack_usage
- call
->stack_align_amount
) / sizeof (target_mgreg_t
) * ins_get_size (OP_TAILCALL_PARAMETER
);
2986 code
= realloc_code (cfg
, max_len
);
2988 ins
->flags
|= MONO_INST_GC_CALLSITE
;
2989 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
2991 g_assert (!cfg
->method
->save_lmf
);
2993 // Ecx is volatile, not used for parameters, or rgctx/imt (edx).
2994 // It is also not used for return value, though that does not matter.
2995 // Ecx is preserved across the tailcall formation.
2997 // Eax could also be used here at the cost of a push/pop moving the parameters.
2998 // Edx must be preserved as it is rgctx/imt.
3000 // If ecx happens to be the base of the tailcall_membase, then
3001 // just end with jmp [ecx+offset] -- one instruction.
3002 // if ecx is not the base, then move ecx, [reg+offset] and later jmp [ecx] -- two instructions.
3005 g_assert (sreg1
> -1);
3006 x86_mov_reg_reg (code
, X86_ECX
, sreg1
);
3007 } else if (tailcall_membase_not_ecx
) {
3008 g_assert (sreg1
> -1);
3009 x86_mov_reg_membase (code
, X86_ECX
, sreg1
, ins
->inst_offset
, 4);
3012 /* restore callee saved registers */
3013 for (i
= 0; i
< X86_NREG
; ++i
)
3014 if (X86_IS_CALLEE_SAVED_REG (i
) && cfg
->used_int_regs
& (1 << i
))
3016 if (cfg
->used_int_regs
& (1 << X86_ESI
)) {
3017 x86_mov_reg_membase (code
, X86_ESI
, X86_EBP
, pos
, 4);
3020 if (cfg
->used_int_regs
& (1 << X86_EDI
)) {
3021 x86_mov_reg_membase (code
, X86_EDI
, X86_EBP
, pos
, 4);
3024 if (cfg
->used_int_regs
& (1 << X86_EBX
)) {
3025 x86_mov_reg_membase (code
, X86_EBX
, X86_EBP
, pos
, 4);
3029 /* Copy arguments on the stack to our argument area */
3030 // FIXME use rep mov for constant code size, before nonvolatiles
3031 // restored, first saving esi, edi into volatiles
3032 for (i
= 0; i
< call
->stack_usage
- call
->stack_align_amount
; i
+= 4) {
3033 x86_mov_reg_membase (code
, X86_EAX
, X86_ESP
, i
, 4);
3034 x86_mov_membase_reg (code
, X86_EBP
, 8 + i
, X86_EAX
, 4);
3037 /* restore ESP/EBP */
3040 if (tailcall_membase_ecx
) {
3041 x86_jump_membase (code
, X86_ECX
, ins
->inst_offset
);
3042 } else if (tailcall_reg
|| tailcall_membase_not_ecx
) {
3043 x86_jump_reg (code
, X86_ECX
);
3045 // FIXME Patch data instead of code.
3046 code
= x86_align_and_patch (cfg
, code
, MONO_PATCH_INFO_METHOD_JUMP
, call
->method
);
3047 x86_jump32 (code
, 0);
3050 ins
->flags
|= MONO_INST_GC_CALLSITE
;
3054 /* ensure ins->sreg1 is not NULL
3055 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3056 * cmp DWORD PTR [eax], 0
3058 x86_alu_membase_reg (code
, X86_CMP
, ins
->sreg1
, 0, ins
->sreg1
);
3061 int hreg
= ins
->sreg1
== X86_EAX
? X86_ECX
: X86_EAX
;
3062 x86_push_reg (code
, hreg
);
3063 x86_lea_membase (code
, hreg
, X86_EBP
, cfg
->sig_cookie
);
3064 x86_mov_membase_reg (code
, ins
->sreg1
, 0, hreg
, 4);
3065 x86_pop_reg (code
, hreg
);
3078 case OP_VOIDCALL_REG
:
3080 case OP_FCALL_MEMBASE
:
3081 case OP_LCALL_MEMBASE
:
3082 case OP_VCALL_MEMBASE
:
3083 case OP_VCALL2_MEMBASE
:
3084 case OP_VOIDCALL_MEMBASE
:
3085 case OP_CALL_MEMBASE
: {
3088 call
= (MonoCallInst
*)ins
;
3089 cinfo
= call
->call_info
;
3091 switch (ins
->opcode
) {
3098 const MonoJumpInfoTarget patch
= mono_call_to_patch (call
);
3099 code
= emit_call (cfg
, code
, patch
.type
, patch
.target
);
3106 case OP_VOIDCALL_REG
:
3108 x86_call_reg (code
, ins
->sreg1
);
3110 case OP_FCALL_MEMBASE
:
3111 case OP_LCALL_MEMBASE
:
3112 case OP_VCALL_MEMBASE
:
3113 case OP_VCALL2_MEMBASE
:
3114 case OP_VOIDCALL_MEMBASE
:
3115 case OP_CALL_MEMBASE
:
3116 x86_call_membase (code
, ins
->sreg1
, ins
->inst_offset
);
3119 g_assert_not_reached ();
3122 ins
->flags
|= MONO_INST_GC_CALLSITE
;
3123 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
3124 if (cinfo
->callee_stack_pop
) {
3125 /* Have to compensate for the stack space popped by the callee */
3126 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, cinfo
->callee_stack_pop
);
3128 code
= emit_move_return_value (cfg
, ins
, code
);
3132 x86_lea_memindex (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_imm
, ins
->sreg2
, ins
->backend
.shift_amount
);
3134 case OP_X86_LEA_MEMBASE
:
3135 x86_lea_membase (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_imm
);
3138 x86_xchg_reg_reg (code
, ins
->sreg1
, ins
->sreg2
, 4);
3141 /* keep alignment */
3142 x86_alu_reg_imm (code
, X86_ADD
, ins
->sreg1
, MONO_ARCH_LOCALLOC_ALIGNMENT
- 1);
3143 x86_alu_reg_imm (code
, X86_AND
, ins
->sreg1
, ~(MONO_ARCH_LOCALLOC_ALIGNMENT
- 1));
3144 code
= mono_emit_stack_alloc (cfg
, code
, ins
);
3145 x86_mov_reg_reg (code
, ins
->dreg
, X86_ESP
);
3146 if (cfg
->param_area
)
3147 x86_alu_reg_imm (code
, X86_ADD
, ins
->dreg
, ALIGN_TO (cfg
->param_area
, MONO_ARCH_FRAME_ALIGNMENT
));
3149 case OP_LOCALLOC_IMM
: {
3150 guint32 size
= ins
->inst_imm
;
3151 size
= (size
+ (MONO_ARCH_FRAME_ALIGNMENT
- 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT
- 1);
3153 if (ins
->flags
& MONO_INST_INIT
) {
3154 /* FIXME: Optimize this */
3155 x86_mov_reg_imm (code
, ins
->dreg
, size
);
3156 ins
->sreg1
= ins
->dreg
;
3158 code
= mono_emit_stack_alloc (cfg
, code
, ins
);
3159 x86_mov_reg_reg (code
, ins
->dreg
, X86_ESP
);
3161 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, size
);
3162 x86_mov_reg_reg (code
, ins
->dreg
, X86_ESP
);
3164 if (cfg
->param_area
)
3165 x86_alu_reg_imm (code
, X86_ADD
, ins
->dreg
, ALIGN_TO (cfg
->param_area
, MONO_ARCH_FRAME_ALIGNMENT
));
3169 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, MONO_ARCH_FRAME_ALIGNMENT
- 4);
3170 x86_push_reg (code
, ins
->sreg1
);
3171 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_JIT_ICALL_ID
,
3172 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arch_throw_exception
));
3173 ins
->flags
|= MONO_INST_GC_CALLSITE
;
3174 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
3178 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, MONO_ARCH_FRAME_ALIGNMENT
- 4);
3179 x86_push_reg (code
, ins
->sreg1
);
3180 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_JIT_ICALL_ID
,
3181 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arch_rethrow_exception
));
3182 ins
->flags
|= MONO_INST_GC_CALLSITE
;
3183 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
3186 case OP_CALL_HANDLER
:
3187 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, MONO_ARCH_FRAME_ALIGNMENT
- 4);
3188 mono_add_patch_info (cfg
, code
- cfg
->native_code
, MONO_PATCH_INFO_BB
, ins
->inst_target_bb
);
3189 x86_call_imm (code
, 0);
3190 for (GList
*tmp
= ins
->inst_eh_blocks
; tmp
!= bb
->clause_holes
; tmp
= tmp
->prev
)
3191 mono_cfg_add_try_hole (cfg
, ((MonoLeaveClause
*) tmp
->data
)->clause
, code
, bb
);
3192 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, MONO_ARCH_FRAME_ALIGNMENT
- 4);
3194 case OP_START_HANDLER
: {
3195 MonoInst
*spvar
= mono_find_spvar_for_region (cfg
, bb
->region
);
3196 x86_mov_membase_reg (code
, spvar
->inst_basereg
, spvar
->inst_offset
, X86_ESP
, 4);
3197 if (cfg
->param_area
)
3198 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, ALIGN_TO (cfg
->param_area
, MONO_ARCH_FRAME_ALIGNMENT
));
3201 case OP_ENDFINALLY
: {
3202 MonoInst
*spvar
= mono_find_spvar_for_region (cfg
, bb
->region
);
3203 x86_mov_reg_membase (code
, X86_ESP
, spvar
->inst_basereg
, spvar
->inst_offset
, 4);
3207 case OP_ENDFILTER
: {
3208 MonoInst
*spvar
= mono_find_spvar_for_region (cfg
, bb
->region
);
3209 x86_mov_reg_membase (code
, X86_ESP
, spvar
->inst_basereg
, spvar
->inst_offset
, 4);
3210 /* The local allocator will put the result into EAX */
3215 x86_mov_reg_reg (code
, ins
->dreg
, X86_EAX
);
3219 ins
->inst_c0
= code
- cfg
->native_code
;
3222 if (ins
->inst_target_bb
->native_offset
) {
3223 x86_jump_code (code
, cfg
->native_code
+ ins
->inst_target_bb
->native_offset
);
3225 mono_add_patch_info (cfg
, offset
, MONO_PATCH_INFO_BB
, ins
->inst_target_bb
);
3226 if ((cfg
->opt
& MONO_OPT_BRANCH
) &&
3227 x86_is_imm8 (ins
->inst_target_bb
->max_offset
- cpos
))
3228 x86_jump8 (code
, 0);
3230 x86_jump32 (code
, 0);
3234 x86_jump_reg (code
, ins
->sreg1
);
3253 x86_set_reg (code
, cc_table
[mono_opcode_to_cond (ins
->opcode
)], ins
->dreg
, cc_signed_table
[mono_opcode_to_cond (ins
->opcode
)]);
3254 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, FALSE
);
3256 case OP_COND_EXC_EQ
:
3257 case OP_COND_EXC_NE_UN
:
3258 case OP_COND_EXC_LT
:
3259 case OP_COND_EXC_LT_UN
:
3260 case OP_COND_EXC_GT
:
3261 case OP_COND_EXC_GT_UN
:
3262 case OP_COND_EXC_GE
:
3263 case OP_COND_EXC_GE_UN
:
3264 case OP_COND_EXC_LE
:
3265 case OP_COND_EXC_LE_UN
:
3266 case OP_COND_EXC_IEQ
:
3267 case OP_COND_EXC_INE_UN
:
3268 case OP_COND_EXC_ILT
:
3269 case OP_COND_EXC_ILT_UN
:
3270 case OP_COND_EXC_IGT
:
3271 case OP_COND_EXC_IGT_UN
:
3272 case OP_COND_EXC_IGE
:
3273 case OP_COND_EXC_IGE_UN
:
3274 case OP_COND_EXC_ILE
:
3275 case OP_COND_EXC_ILE_UN
:
3276 EMIT_COND_SYSTEM_EXCEPTION (cc_table
[mono_opcode_to_cond (ins
->opcode
)], cc_signed_table
[mono_opcode_to_cond (ins
->opcode
)], (const char*)ins
->inst_p1
);
3278 case OP_COND_EXC_OV
:
3279 case OP_COND_EXC_NO
:
3281 case OP_COND_EXC_NC
:
3282 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table
[ins
->opcode
- OP_COND_EXC_EQ
], (ins
->opcode
< OP_COND_EXC_NE_UN
), (const char*)ins
->inst_p1
);
3284 case OP_COND_EXC_IOV
:
3285 case OP_COND_EXC_INO
:
3286 case OP_COND_EXC_IC
:
3287 case OP_COND_EXC_INC
:
3288 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table
[ins
->opcode
- OP_COND_EXC_IEQ
], (ins
->opcode
< OP_COND_EXC_INE_UN
), (const char*)ins
->inst_p1
);
3300 EMIT_COND_BRANCH (ins
, cc_table
[mono_opcode_to_cond (ins
->opcode
)], cc_signed_table
[mono_opcode_to_cond (ins
->opcode
)]);
3308 case OP_CMOV_INE_UN
:
3309 case OP_CMOV_IGE_UN
:
3310 case OP_CMOV_IGT_UN
:
3311 case OP_CMOV_ILE_UN
:
3312 case OP_CMOV_ILT_UN
:
3313 g_assert (ins
->dreg
== ins
->sreg1
);
3314 x86_cmov_reg (code
, cc_table
[mono_opcode_to_cond (ins
->opcode
)], cc_signed_table
[mono_opcode_to_cond (ins
->opcode
)], ins
->dreg
, ins
->sreg2
);
3317 /* floating point opcodes */
3319 double d
= *(double *)ins
->inst_p0
;
3321 if ((d
== 0.0) && (mono_signbit (d
) == 0)) {
3323 } else if (d
== 1.0) {
3326 if (cfg
->compile_aot
) {
3327 guint32
*val
= (guint32
*)&d
;
3328 x86_push_imm (code
, val
[1]);
3329 x86_push_imm (code
, val
[0]);
3330 x86_fld_membase (code
, X86_ESP
, 0, TRUE
);
3331 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 8);
3334 mono_add_patch_info (cfg
, code
- cfg
->native_code
, MONO_PATCH_INFO_R8
, ins
->inst_p0
);
3335 x86_fld (code
, NULL
, TRUE
);
3341 float f
= *(float *)ins
->inst_p0
;
3343 if ((f
== 0.0) && (mono_signbit (f
) == 0)) {
3345 } else if (f
== 1.0) {
3348 if (cfg
->compile_aot
) {
3349 guint32 val
= *(guint32
*)&f
;
3350 x86_push_imm (code
, val
);
3351 x86_fld_membase (code
, X86_ESP
, 0, FALSE
);
3352 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 4);
3355 mono_add_patch_info (cfg
, code
- cfg
->native_code
, MONO_PATCH_INFO_R4
, ins
->inst_p0
);
3356 x86_fld (code
, NULL
, FALSE
);
3361 case OP_STORER8_MEMBASE_REG
:
3362 x86_fst_membase (code
, ins
->inst_destbasereg
, ins
->inst_offset
, TRUE
, TRUE
);
3364 case OP_LOADR8_MEMBASE
:
3365 x86_fld_membase (code
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
);
3367 case OP_STORER4_MEMBASE_REG
:
3368 x86_fst_membase (code
, ins
->inst_destbasereg
, ins
->inst_offset
, FALSE
, TRUE
);
3370 case OP_LOADR4_MEMBASE
:
3371 x86_fld_membase (code
, ins
->inst_basereg
, ins
->inst_offset
, FALSE
);
3373 case OP_ICONV_TO_R4
:
3374 x86_push_reg (code
, ins
->sreg1
);
3375 x86_fild_membase (code
, X86_ESP
, 0, FALSE
);
3376 /* Change precision */
3377 x86_fst_membase (code
, X86_ESP
, 0, FALSE
, TRUE
);
3378 x86_fld_membase (code
, X86_ESP
, 0, FALSE
);
3379 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 4);
3381 case OP_ICONV_TO_R8
:
3382 x86_push_reg (code
, ins
->sreg1
);
3383 x86_fild_membase (code
, X86_ESP
, 0, FALSE
);
3384 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 4);
3386 case OP_ICONV_TO_R_UN
:
3387 x86_push_imm (code
, 0);
3388 x86_push_reg (code
, ins
->sreg1
);
3389 x86_fild_membase (code
, X86_ESP
, 0, TRUE
);
3390 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 8);
3392 case OP_X86_FP_LOAD_I8
:
3393 x86_fild_membase (code
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
);
3395 case OP_X86_FP_LOAD_I4
:
3396 x86_fild_membase (code
, ins
->inst_basereg
, ins
->inst_offset
, FALSE
);
3398 case OP_FCONV_TO_R4
:
3399 /* Change precision */
3400 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, 4);
3401 x86_fst_membase (code
, X86_ESP
, 0, FALSE
, TRUE
);
3402 x86_fld_membase (code
, X86_ESP
, 0, FALSE
);
3403 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 4);
3405 case OP_FCONV_TO_I1
:
3406 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, 1, TRUE
);
3408 case OP_FCONV_TO_U1
:
3409 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, 1, FALSE
);
3411 case OP_FCONV_TO_I2
:
3412 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, 2, TRUE
);
3414 case OP_FCONV_TO_U2
:
3415 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, 2, FALSE
);
3417 case OP_FCONV_TO_I4
:
3419 code
= emit_float_to_int (cfg
, code
, ins
->dreg
, 4, TRUE
);
3421 case OP_FCONV_TO_I8
:
3422 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, 4);
3423 x86_fnstcw_membase(code
, X86_ESP
, 0);
3424 x86_mov_reg_membase (code
, ins
->dreg
, X86_ESP
, 0, 2);
3425 x86_alu_reg_imm (code
, X86_OR
, ins
->dreg
, 0xc00);
3426 x86_mov_membase_reg (code
, X86_ESP
, 2, ins
->dreg
, 2);
3427 x86_fldcw_membase (code
, X86_ESP
, 2);
3428 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, 8);
3429 x86_fist_pop_membase (code
, X86_ESP
, 0, TRUE
);
3430 x86_pop_reg (code
, ins
->dreg
);
3431 x86_pop_reg (code
, ins
->backend
.reg3
);
3432 x86_fldcw_membase (code
, X86_ESP
, 0);
3433 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 4);
3435 case OP_LCONV_TO_R8_2
:
3436 x86_push_reg (code
, ins
->sreg2
);
3437 x86_push_reg (code
, ins
->sreg1
);
3438 x86_fild_membase (code
, X86_ESP
, 0, TRUE
);
3439 /* Change precision */
3440 x86_fst_membase (code
, X86_ESP
, 0, TRUE
, TRUE
);
3441 x86_fld_membase (code
, X86_ESP
, 0, TRUE
);
3442 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 8);
3444 case OP_LCONV_TO_R4_2
:
3445 x86_push_reg (code
, ins
->sreg2
);
3446 x86_push_reg (code
, ins
->sreg1
);
3447 x86_fild_membase (code
, X86_ESP
, 0, TRUE
);
3448 /* Change precision */
3449 x86_fst_membase (code
, X86_ESP
, 0, FALSE
, TRUE
);
3450 x86_fld_membase (code
, X86_ESP
, 0, FALSE
);
3451 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 8);
3453 case OP_LCONV_TO_R_UN_2
: {
3454 static guint8 mn
[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3457 /* load 64bit integer to FP stack */
3458 x86_push_reg (code
, ins
->sreg2
);
3459 x86_push_reg (code
, ins
->sreg1
);
3460 x86_fild_membase (code
, X86_ESP
, 0, TRUE
);
3462 /* test if lreg is negative */
3463 x86_test_reg_reg (code
, ins
->sreg2
, ins
->sreg2
);
3464 br
= code
; x86_branch8 (code
, X86_CC_GEZ
, 0, TRUE
);
3466 /* add correction constant mn */
3467 if (cfg
->compile_aot
) {
3468 x86_push_imm (code
, (((guint32
)mn
[9]) << 24) | ((guint32
)mn
[8] << 16) | ((guint32
)mn
[7] << 8) | ((guint32
)mn
[6]));
3469 x86_push_imm (code
, (((guint32
)mn
[5]) << 24) | ((guint32
)mn
[4] << 16) | ((guint32
)mn
[3] << 8) | ((guint32
)mn
[2]));
3470 x86_push_imm (code
, (((guint32
)mn
[1]) << 24) | ((guint32
)mn
[0] << 16));
3471 x86_fld80_membase (code
, X86_ESP
, 2);
3472 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 12);
3474 x86_fld80_mem (code
, mn
);
3476 x86_fp_op_reg (code
, X86_FADD
, 1, TRUE
);
3478 x86_patch (br
, code
);
3480 /* Change precision */
3481 x86_fst_membase (code
, X86_ESP
, 0, TRUE
, TRUE
);
3482 x86_fld_membase (code
, X86_ESP
, 0, TRUE
);
3484 x86_alu_reg_imm (code
, X86_ADD
, X86_ESP
, 8);
3488 case OP_LCONV_TO_OVF_I
:
3489 case OP_LCONV_TO_OVF_I4_2
: {
3490 guint8
*br
[3], *label
[1];
3494 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3496 x86_test_reg_reg (code
, ins
->sreg1
, ins
->sreg1
);
3498 /* If the low word top bit is set, see if we are negative */
3499 br
[0] = code
; x86_branch8 (code
, X86_CC_LT
, 0, TRUE
);
3500 /* We are not negative (no top bit set, check for our top word to be zero */
3501 x86_test_reg_reg (code
, ins
->sreg2
, ins
->sreg2
);
3502 br
[1] = code
; x86_branch8 (code
, X86_CC_EQ
, 0, TRUE
);
3505 /* throw exception */
3506 tins
= mono_branch_optimize_exception_target (cfg
, bb
, "OverflowException");
3508 mono_add_patch_info (cfg
, code
- cfg
->native_code
, MONO_PATCH_INFO_BB
, tins
->inst_true_bb
);
3509 if ((cfg
->opt
& MONO_OPT_BRANCH
) && x86_is_imm8 (tins
->inst_true_bb
->max_offset
- cpos
))
3510 x86_jump8 (code
, 0);
3512 x86_jump32 (code
, 0);
3514 mono_add_patch_info (cfg
, code
- cfg
->native_code
, MONO_PATCH_INFO_EXC
, "OverflowException");
3515 x86_jump32 (code
, 0);
3519 x86_patch (br
[0], code
);
3520 /* our top bit is set, check that top word is 0xfffffff */
3521 x86_alu_reg_imm (code
, X86_CMP
, ins
->sreg2
, 0xffffffff);
3523 x86_patch (br
[1], code
);
3524 /* nope, emit exception */
3525 br
[2] = code
; x86_branch8 (code
, X86_CC_NE
, 0, TRUE
);
3526 x86_patch (br
[2], label
[0]);
3528 x86_mov_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
3532 /* Not needed on the fp stack */
3534 case OP_MOVE_F_TO_I4
:
3535 x86_fst_membase (code
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, FALSE
, TRUE
);
3536 x86_mov_reg_membase (code
, ins
->dreg
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, 4);
3538 case OP_MOVE_I4_TO_F
:
3539 x86_mov_membase_reg (code
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, ins
->sreg1
, 4);
3540 x86_fld_membase (code
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, FALSE
);
3543 x86_fp_op_reg (code
, X86_FADD
, 1, TRUE
);
3546 x86_fp_op_reg (code
, X86_FSUB
, 1, TRUE
);
3549 x86_fp_op_reg (code
, X86_FMUL
, 1, TRUE
);
3552 x86_fp_op_reg (code
, X86_FDIV
, 1, TRUE
);
3560 x86_fp_op_reg (code
, X86_FADD
, 1, TRUE
);
3565 x86_fp_op_reg (code
, X86_FADD
, 1, TRUE
);
3572 * it really doesn't make sense to inline all this code,
3573 * it's here just to show that things may not be as simple
3576 guchar
*check_pos
, *end_tan
, *pop_jump
;
3577 x86_push_reg (code
, X86_EAX
);
3580 x86_test_reg_imm (code
, X86_EAX
, X86_FP_C2
);
3582 x86_branch8 (code
, X86_CC_NE
, 0, FALSE
);
3583 x86_fstp (code
, 0); /* pop the 1.0 */
3585 x86_jump8 (code
, 0);
3587 x86_fp_op (code
, X86_FADD
, 0);
3591 x86_test_reg_imm (code
, X86_EAX
, X86_FP_C2
);
3593 x86_branch8 (code
, X86_CC_NE
, 0, FALSE
);
3596 x86_patch (pop_jump
, code
);
3597 x86_fstp (code
, 0); /* pop the 1.0 */
3598 x86_patch (check_pos
, code
);
3599 x86_patch (end_tan
, code
);
3601 x86_fp_op_reg (code
, X86_FADD
, 1, TRUE
);
3602 x86_pop_reg (code
, X86_EAX
);
3609 x86_fp_op_reg (code
, X86_FADD
, 1, TRUE
);
3618 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
3619 g_assert (ins
->dreg
== ins
->sreg1
);
3620 x86_alu_reg_reg (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
);
3621 x86_cmov_reg (code
, X86_CC_GT
, TRUE
, ins
->dreg
, ins
->sreg2
);
3624 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
3625 g_assert (ins
->dreg
== ins
->sreg1
);
3626 x86_alu_reg_reg (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
);
3627 x86_cmov_reg (code
, X86_CC_GT
, FALSE
, ins
->dreg
, ins
->sreg2
);
3630 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
3631 g_assert (ins
->dreg
== ins
->sreg1
);
3632 x86_alu_reg_reg (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
);
3633 x86_cmov_reg (code
, X86_CC_LT
, TRUE
, ins
->dreg
, ins
->sreg2
);
3636 g_assert (cfg
->opt
& MONO_OPT_CMOV
);
3637 g_assert (ins
->dreg
== ins
->sreg1
);
3638 x86_alu_reg_reg (code
, X86_CMP
, ins
->sreg1
, ins
->sreg2
);
3639 x86_cmov_reg (code
, X86_CC_LT
, FALSE
, ins
->dreg
, ins
->sreg2
);
3645 x86_fxch (code
, ins
->inst_imm
);
3650 x86_push_reg (code
, X86_EAX
);
3651 /* we need to exchange ST(0) with ST(1) */
3654 /* this requires a loop, because fprem somtimes
3655 * returns a partial remainder */
3657 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3658 /* x86_fprem1 (code); */
3661 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, X86_FP_C2
);
3663 x86_branch8 (code
, X86_CC_NE
, 0, FALSE
);
3669 x86_pop_reg (code
, X86_EAX
);
3673 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3674 x86_fcomip (code
, 1);
3678 /* this overwrites EAX */
3679 EMIT_FPCOMPARE(code
);
3680 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, X86_FP_CC_MASK
);
3684 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3685 /* zeroing the register at the start results in
3686 * shorter and faster code (we can also remove the widening op)
3688 guchar
*unordered_check
;
3689 x86_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
3690 x86_fcomip (code
, 1);
3692 unordered_check
= code
;
3693 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
3694 if (ins
->opcode
== OP_FCEQ
) {
3695 x86_set_reg (code
, X86_CC_EQ
, ins
->dreg
, FALSE
);
3696 x86_patch (unordered_check
, code
);
3698 guchar
*jump_to_end
;
3699 x86_set_reg (code
, X86_CC_NE
, ins
->dreg
, FALSE
);
3701 x86_jump8 (code
, 0);
3702 x86_patch (unordered_check
, code
);
3703 x86_inc_reg (code
, ins
->dreg
);
3704 x86_patch (jump_to_end
, code
);
3709 if (ins
->dreg
!= X86_EAX
)
3710 x86_push_reg (code
, X86_EAX
);
3712 EMIT_FPCOMPARE(code
);
3713 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, X86_FP_CC_MASK
);
3714 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, 0x4000);
3715 x86_set_reg (code
, ins
->opcode
== OP_FCEQ
? X86_CC_EQ
: X86_CC_NE
, ins
->dreg
, TRUE
);
3716 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, FALSE
);
3718 if (ins
->dreg
!= X86_EAX
)
3719 x86_pop_reg (code
, X86_EAX
);
3723 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3724 /* zeroing the register at the start results in
3725 * shorter and faster code (we can also remove the widening op)
3727 x86_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
3728 x86_fcomip (code
, 1);
3730 if (ins
->opcode
== OP_FCLT_UN
) {
3731 guchar
*unordered_check
= code
;
3732 guchar
*jump_to_end
;
3733 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
3734 x86_set_reg (code
, X86_CC_GT
, ins
->dreg
, FALSE
);
3736 x86_jump8 (code
, 0);
3737 x86_patch (unordered_check
, code
);
3738 x86_inc_reg (code
, ins
->dreg
);
3739 x86_patch (jump_to_end
, code
);
3741 x86_set_reg (code
, X86_CC_GT
, ins
->dreg
, FALSE
);
3745 if (ins
->dreg
!= X86_EAX
)
3746 x86_push_reg (code
, X86_EAX
);
3748 EMIT_FPCOMPARE(code
);
3749 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, X86_FP_CC_MASK
);
3750 if (ins
->opcode
== OP_FCLT_UN
) {
3751 guchar
*is_not_zero_check
, *end_jump
;
3752 is_not_zero_check
= code
;
3753 x86_branch8 (code
, X86_CC_NZ
, 0, TRUE
);
3755 x86_jump8 (code
, 0);
3756 x86_patch (is_not_zero_check
, code
);
3757 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_CC_MASK
);
3759 x86_patch (end_jump
, code
);
3761 x86_set_reg (code
, X86_CC_EQ
, ins
->dreg
, TRUE
);
3762 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, FALSE
);
3764 if (ins
->dreg
!= X86_EAX
)
3765 x86_pop_reg (code
, X86_EAX
);
3768 guchar
*unordered_check
;
3769 guchar
*jump_to_end
;
3770 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3771 /* zeroing the register at the start results in
3772 * shorter and faster code (we can also remove the widening op)
3774 x86_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
3775 x86_fcomip (code
, 1);
3777 unordered_check
= code
;
3778 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
3779 x86_set_reg (code
, X86_CC_NB
, ins
->dreg
, FALSE
);
3780 x86_patch (unordered_check
, code
);
3783 if (ins
->dreg
!= X86_EAX
)
3784 x86_push_reg (code
, X86_EAX
);
3786 EMIT_FPCOMPARE(code
);
3787 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, X86_FP_CC_MASK
);
3788 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, 0x4500);
3789 unordered_check
= code
;
3790 x86_branch8 (code
, X86_CC_EQ
, 0, FALSE
);
3792 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_C0
);
3793 x86_set_reg (code
, X86_CC_NE
, ins
->dreg
, TRUE
);
3794 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, FALSE
);
3796 x86_jump8 (code
, 0);
3797 x86_patch (unordered_check
, code
);
3798 x86_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
3799 x86_patch (jump_to_end
, code
);
3801 if (ins
->dreg
!= X86_EAX
)
3802 x86_pop_reg (code
, X86_EAX
);
3807 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3808 /* zeroing the register at the start results in
3809 * shorter and faster code (we can also remove the widening op)
3811 guchar
*unordered_check
;
3812 x86_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
3813 x86_fcomip (code
, 1);
3815 if (ins
->opcode
== OP_FCGT
) {
3816 unordered_check
= code
;
3817 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
3818 x86_set_reg (code
, X86_CC_LT
, ins
->dreg
, FALSE
);
3819 x86_patch (unordered_check
, code
);
3821 x86_set_reg (code
, X86_CC_LT
, ins
->dreg
, FALSE
);
3825 if (ins
->dreg
!= X86_EAX
)
3826 x86_push_reg (code
, X86_EAX
);
3828 EMIT_FPCOMPARE(code
);
3829 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, X86_FP_CC_MASK
);
3830 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_C0
);
3831 if (ins
->opcode
== OP_FCGT_UN
) {
3832 guchar
*is_not_zero_check
, *end_jump
;
3833 is_not_zero_check
= code
;
3834 x86_branch8 (code
, X86_CC_NZ
, 0, TRUE
);
3836 x86_jump8 (code
, 0);
3837 x86_patch (is_not_zero_check
, code
);
3838 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_CC_MASK
);
3840 x86_patch (end_jump
, code
);
3842 x86_set_reg (code
, X86_CC_EQ
, ins
->dreg
, TRUE
);
3843 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, FALSE
);
3845 if (ins
->dreg
!= X86_EAX
)
3846 x86_pop_reg (code
, X86_EAX
);
3849 guchar
*unordered_check
;
3850 guchar
*jump_to_end
;
3851 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3852 /* zeroing the register at the start results in
3853 * shorter and faster code (we can also remove the widening op)
3855 x86_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
3856 x86_fcomip (code
, 1);
3858 unordered_check
= code
;
3859 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
3860 x86_set_reg (code
, X86_CC_NA
, ins
->dreg
, FALSE
);
3861 x86_patch (unordered_check
, code
);
3864 if (ins
->dreg
!= X86_EAX
)
3865 x86_push_reg (code
, X86_EAX
);
3867 EMIT_FPCOMPARE(code
);
3868 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, X86_FP_CC_MASK
);
3869 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, 0x4500);
3870 unordered_check
= code
;
3871 x86_branch8 (code
, X86_CC_EQ
, 0, FALSE
);
3873 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_C0
);
3874 x86_set_reg (code
, X86_CC_GE
, ins
->dreg
, TRUE
);
3875 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, FALSE
);
3877 x86_jump8 (code
, 0);
3878 x86_patch (unordered_check
, code
);
3879 x86_alu_reg_reg (code
, X86_XOR
, ins
->dreg
, ins
->dreg
);
3880 x86_patch (jump_to_end
, code
);
3882 if (ins
->dreg
!= X86_EAX
)
3883 x86_pop_reg (code
, X86_EAX
);
3887 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3888 guchar
*jump
= code
;
3889 x86_branch8 (code
, X86_CC_P
, 0, TRUE
);
3890 EMIT_COND_BRANCH (ins
, X86_CC_EQ
, FALSE
);
3891 x86_patch (jump
, code
);
3894 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, 0x4000);
3895 EMIT_COND_BRANCH (ins
, X86_CC_EQ
, TRUE
);
3898 /* Branch if C013 != 100 */
3899 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3900 /* branch if !ZF or (PF|CF) */
3901 EMIT_COND_BRANCH (ins
, X86_CC_NE
, FALSE
);
3902 EMIT_COND_BRANCH (ins
, X86_CC_P
, FALSE
);
3903 EMIT_COND_BRANCH (ins
, X86_CC_B
, FALSE
);
3906 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_C3
);
3907 EMIT_COND_BRANCH (ins
, X86_CC_NE
, FALSE
);
3910 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3911 EMIT_COND_BRANCH (ins
, X86_CC_GT
, FALSE
);
3914 EMIT_COND_BRANCH (ins
, X86_CC_EQ
, FALSE
);
3917 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3918 EMIT_COND_BRANCH (ins
, X86_CC_P
, FALSE
);
3919 EMIT_COND_BRANCH (ins
, X86_CC_GT
, FALSE
);
3922 if (ins
->opcode
== OP_FBLT_UN
) {
3923 guchar
*is_not_zero_check
, *end_jump
;
3924 is_not_zero_check
= code
;
3925 x86_branch8 (code
, X86_CC_NZ
, 0, TRUE
);
3927 x86_jump8 (code
, 0);
3928 x86_patch (is_not_zero_check
, code
);
3929 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_CC_MASK
);
3931 x86_patch (end_jump
, code
);
3933 EMIT_COND_BRANCH (ins
, X86_CC_EQ
, FALSE
);
3937 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3938 if (ins
->opcode
== OP_FBGT
) {
3941 /* skip branch if C1=1 */
3943 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
3944 /* branch if (C0 | C3) = 1 */
3945 EMIT_COND_BRANCH (ins
, X86_CC_LT
, FALSE
);
3946 x86_patch (br1
, code
);
3948 EMIT_COND_BRANCH (ins
, X86_CC_LT
, FALSE
);
3952 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_C0
);
3953 if (ins
->opcode
== OP_FBGT_UN
) {
3954 guchar
*is_not_zero_check
, *end_jump
;
3955 is_not_zero_check
= code
;
3956 x86_branch8 (code
, X86_CC_NZ
, 0, TRUE
);
3958 x86_jump8 (code
, 0);
3959 x86_patch (is_not_zero_check
, code
);
3960 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_CC_MASK
);
3962 x86_patch (end_jump
, code
);
3964 EMIT_COND_BRANCH (ins
, X86_CC_EQ
, FALSE
);
3967 /* Branch if C013 == 100 or 001 */
3968 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3971 /* skip branch if C1=1 */
3973 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
3974 /* branch if (C0 | C3) = 1 */
3975 EMIT_COND_BRANCH (ins
, X86_CC_BE
, FALSE
);
3976 x86_patch (br1
, code
);
3979 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_C0
);
3980 EMIT_COND_BRANCH (ins
, X86_CC_EQ
, FALSE
);
3981 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_C3
);
3982 EMIT_COND_BRANCH (ins
, X86_CC_EQ
, FALSE
);
3985 /* Branch if C013 == 000 */
3986 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3987 EMIT_COND_BRANCH (ins
, X86_CC_LE
, FALSE
);
3990 EMIT_COND_BRANCH (ins
, X86_CC_NE
, FALSE
);
3993 /* Branch if C013=000 or 100 */
3994 if (cfg
->opt
& MONO_OPT_FCMOV
) {
3997 /* skip branch if C1=1 */
3999 x86_branch8 (code
, X86_CC_P
, 0, FALSE
);
4000 /* branch if C0=0 */
4001 EMIT_COND_BRANCH (ins
, X86_CC_NB
, FALSE
);
4002 x86_patch (br1
, code
);
4005 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, (X86_FP_C0
|X86_FP_C1
));
4006 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, 0);
4007 EMIT_COND_BRANCH (ins
, X86_CC_EQ
, FALSE
);
4010 /* Branch if C013 != 001 */
4011 if (cfg
->opt
& MONO_OPT_FCMOV
) {
4012 EMIT_COND_BRANCH (ins
, X86_CC_P
, FALSE
);
4013 EMIT_COND_BRANCH (ins
, X86_CC_GE
, FALSE
);
4016 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_C0
);
4017 EMIT_COND_BRANCH (ins
, X86_CC_NE
, FALSE
);
4021 x86_push_reg (code
, X86_EAX
);
4024 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, 0x4100);
4025 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, X86_FP_C0
);
4026 x86_pop_reg (code
, X86_EAX
);
4028 /* Have to clean up the fp stack before throwing the exception */
4030 x86_branch8 (code
, X86_CC_NE
, 0, FALSE
);
4033 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ
, FALSE
, "OverflowException");
4035 x86_patch (br1
, code
);
4039 code
= mono_x86_emit_tls_get (code
, ins
->dreg
, ins
->inst_offset
);
4043 code
= mono_x86_emit_tls_set (code
, ins
->sreg1
, ins
->inst_offset
);
4046 case OP_MEMORY_BARRIER
: {
4047 if (ins
->backend
.memory_barrier_kind
== MONO_MEMORY_BARRIER_SEQ
) {
4048 x86_prefix (code
, X86_LOCK_PREFIX
);
4049 x86_alu_membase_imm (code
, X86_ADD
, X86_ESP
, 0, 0);
4053 case OP_ATOMIC_ADD_I4
: {
4054 int dreg
= ins
->dreg
;
4056 g_assert (cfg
->has_atomic_add_i4
);
4058 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4059 if (ins
->sreg2
== dreg
) {
4060 if (dreg
== X86_EBX
) {
4062 if (ins
->inst_basereg
== X86_EDI
)
4066 if (ins
->inst_basereg
== X86_EBX
)
4069 } else if (ins
->inst_basereg
== dreg
) {
4070 if (dreg
== X86_EBX
) {
4072 if (ins
->sreg2
== X86_EDI
)
4076 if (ins
->sreg2
== X86_EBX
)
4081 if (dreg
!= ins
->dreg
) {
4082 x86_push_reg (code
, dreg
);
4085 x86_mov_reg_reg (code
, dreg
, ins
->sreg2
);
4086 x86_prefix (code
, X86_LOCK_PREFIX
);
4087 x86_xadd_membase_reg (code
, ins
->inst_basereg
, ins
->inst_offset
, dreg
, 4);
4088 /* dreg contains the old value, add with sreg2 value */
4089 x86_alu_reg_reg (code
, X86_ADD
, dreg
, ins
->sreg2
);
4091 if (ins
->dreg
!= dreg
) {
4092 x86_mov_reg_reg (code
, ins
->dreg
, dreg
);
4093 x86_pop_reg (code
, dreg
);
4098 case OP_ATOMIC_EXCHANGE_I4
: {
4100 int sreg2
= ins
->sreg2
;
4101 int breg
= ins
->inst_basereg
;
4103 g_assert (cfg
->has_atomic_exchange_i4
);
4105 /* cmpxchg uses eax as comperand, need to make sure we can use it
4106 * hack to overcome limits in x86 reg allocator
4107 * (req: dreg == eax and sreg2 != eax and breg != eax)
4109 g_assert (ins
->dreg
== X86_EAX
);
4111 /* We need the EAX reg for the cmpxchg */
4112 if (ins
->sreg2
== X86_EAX
) {
4113 sreg2
= (breg
== X86_EDX
) ? X86_EBX
: X86_EDX
;
4114 x86_push_reg (code
, sreg2
);
4115 x86_mov_reg_reg (code
, sreg2
, X86_EAX
);
4118 if (breg
== X86_EAX
) {
4119 breg
= (sreg2
== X86_ESI
) ? X86_EDI
: X86_ESI
;
4120 x86_push_reg (code
, breg
);
4121 x86_mov_reg_reg (code
, breg
, X86_EAX
);
4124 x86_mov_reg_membase (code
, X86_EAX
, breg
, ins
->inst_offset
, 4);
4126 br
[0] = code
; x86_prefix (code
, X86_LOCK_PREFIX
);
4127 x86_cmpxchg_membase_reg (code
, breg
, ins
->inst_offset
, sreg2
);
4128 br
[1] = code
; x86_branch8 (code
, X86_CC_NE
, -1, FALSE
);
4129 x86_patch (br
[1], br
[0]);
4131 if (breg
!= ins
->inst_basereg
)
4132 x86_pop_reg (code
, breg
);
4134 if (ins
->sreg2
!= sreg2
)
4135 x86_pop_reg (code
, sreg2
);
4139 case OP_ATOMIC_CAS_I4
: {
4140 g_assert (ins
->dreg
== X86_EAX
);
4141 g_assert (ins
->sreg3
== X86_EAX
);
4142 g_assert (ins
->sreg1
!= X86_EAX
);
4143 g_assert (ins
->sreg1
!= ins
->sreg2
);
4145 x86_prefix (code
, X86_LOCK_PREFIX
);
4146 x86_cmpxchg_membase_reg (code
, ins
->sreg1
, ins
->inst_offset
, ins
->sreg2
);
4149 case OP_ATOMIC_LOAD_I1
: {
4150 x86_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
, FALSE
);
4153 case OP_ATOMIC_LOAD_U1
: {
4154 x86_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, FALSE
, FALSE
);
4157 case OP_ATOMIC_LOAD_I2
: {
4158 x86_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, TRUE
, TRUE
);
4161 case OP_ATOMIC_LOAD_U2
: {
4162 x86_widen_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, FALSE
, TRUE
);
4165 case OP_ATOMIC_LOAD_I4
:
4166 case OP_ATOMIC_LOAD_U4
: {
4167 x86_mov_reg_membase (code
, ins
->dreg
, ins
->inst_basereg
, ins
->inst_offset
, 4);
4170 case OP_ATOMIC_LOAD_R4
:
4171 case OP_ATOMIC_LOAD_R8
: {
4172 x86_fld_membase (code
, ins
->inst_basereg
, ins
->inst_offset
, ins
->opcode
== OP_ATOMIC_LOAD_R8
);
4175 case OP_ATOMIC_STORE_I1
:
4176 case OP_ATOMIC_STORE_U1
:
4177 case OP_ATOMIC_STORE_I2
:
4178 case OP_ATOMIC_STORE_U2
:
4179 case OP_ATOMIC_STORE_I4
:
4180 case OP_ATOMIC_STORE_U4
: {
4183 switch (ins
->opcode
) {
4184 case OP_ATOMIC_STORE_I1
:
4185 case OP_ATOMIC_STORE_U1
:
4188 case OP_ATOMIC_STORE_I2
:
4189 case OP_ATOMIC_STORE_U2
:
4192 case OP_ATOMIC_STORE_I4
:
4193 case OP_ATOMIC_STORE_U4
:
4198 x86_mov_membase_reg (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->sreg1
, size
);
4200 if (ins
->backend
.memory_barrier_kind
== MONO_MEMORY_BARRIER_SEQ
)
4204 case OP_ATOMIC_STORE_R4
:
4205 case OP_ATOMIC_STORE_R8
: {
4206 x86_fst_membase (code
, ins
->inst_destbasereg
, ins
->inst_offset
, ins
->opcode
== OP_ATOMIC_STORE_R8
, TRUE
);
4208 if (ins
->backend
.memory_barrier_kind
== MONO_MEMORY_BARRIER_SEQ
)
4212 case OP_CARD_TABLE_WBARRIER
: {
4213 int ptr
= ins
->sreg1
;
4214 int value
= ins
->sreg2
;
4216 int nursery_shift
, card_table_shift
;
4217 gpointer card_table_mask
;
4218 size_t nursery_size
;
4219 gulong card_table
= (gulong
)mono_gc_get_card_table (&card_table_shift
, &card_table_mask
);
4220 gulong nursery_start
= (gulong
)mono_gc_get_nursery (&nursery_shift
, &nursery_size
);
4221 gboolean card_table_nursery_check
= mono_gc_card_table_nursery_check ();
4224 * We need one register we can clobber, we choose EDX and make sreg1
4225 * fixed EAX to work around limitations in the local register allocator.
4226 * sreg2 might get allocated to EDX, but that is not a problem since
4227 * we use it before clobbering EDX.
4229 g_assert (ins
->sreg1
== X86_EAX
);
4232 * This is the code we produce:
4235 * edx >>= nursery_shift
4236 * cmp edx, (nursery_start >> nursery_shift)
4239 * edx >>= card_table_shift
4240 * card_table[edx] = 1
4244 if (card_table_nursery_check
) {
4245 if (value
!= X86_EDX
)
4246 x86_mov_reg_reg (code
, X86_EDX
, value
);
4247 x86_shift_reg_imm (code
, X86_SHR
, X86_EDX
, nursery_shift
);
4248 x86_alu_reg_imm (code
, X86_CMP
, X86_EDX
, nursery_start
>> nursery_shift
);
4249 br
= code
; x86_branch8 (code
, X86_CC_NE
, -1, FALSE
);
4251 x86_mov_reg_reg (code
, X86_EDX
, ptr
);
4252 x86_shift_reg_imm (code
, X86_SHR
, X86_EDX
, card_table_shift
);
4253 if (card_table_mask
)
4254 x86_alu_reg_imm (code
, X86_AND
, X86_EDX
, (int)card_table_mask
);
4255 x86_mov_membase_imm (code
, X86_EDX
, card_table
, 1, 1);
4256 if (card_table_nursery_check
)
4257 x86_patch (br
, code
);
4260 #ifdef MONO_ARCH_SIMD_INTRINSICS
4262 x86_sse_alu_ps_reg_reg (code
, X86_SSE_ADD
, ins
->sreg1
, ins
->sreg2
);
4265 x86_sse_alu_ps_reg_reg (code
, X86_SSE_DIV
, ins
->sreg1
, ins
->sreg2
);
4268 x86_sse_alu_ps_reg_reg (code
, X86_SSE_MUL
, ins
->sreg1
, ins
->sreg2
);
4271 x86_sse_alu_ps_reg_reg (code
, X86_SSE_SUB
, ins
->sreg1
, ins
->sreg2
);
4274 x86_sse_alu_ps_reg_reg (code
, X86_SSE_MAX
, ins
->sreg1
, ins
->sreg2
);
4277 x86_sse_alu_ps_reg_reg (code
, X86_SSE_MIN
, ins
->sreg1
, ins
->sreg2
);
4280 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 7);
4281 x86_sse_alu_ps_reg_reg_imm (code
, X86_SSE_COMP
, ins
->sreg1
, ins
->sreg2
, ins
->inst_c0
);
4284 x86_sse_alu_ps_reg_reg (code
, X86_SSE_AND
, ins
->sreg1
, ins
->sreg2
);
4287 x86_sse_alu_ps_reg_reg (code
, X86_SSE_ANDN
, ins
->sreg1
, ins
->sreg2
);
4290 x86_sse_alu_ps_reg_reg (code
, X86_SSE_OR
, ins
->sreg1
, ins
->sreg2
);
4293 x86_sse_alu_ps_reg_reg (code
, X86_SSE_XOR
, ins
->sreg1
, ins
->sreg2
);
4296 x86_sse_alu_ps_reg_reg (code
, X86_SSE_SQRT
, ins
->dreg
, ins
->sreg1
);
4299 x86_sse_alu_ps_reg_reg (code
, X86_SSE_RSQRT
, ins
->dreg
, ins
->sreg1
);
4302 x86_sse_alu_ps_reg_reg (code
, X86_SSE_RCP
, ins
->dreg
, ins
->sreg1
);
4305 x86_sse_alu_sd_reg_reg (code
, X86_SSE_ADDSUB
, ins
->sreg1
, ins
->sreg2
);
4308 x86_sse_alu_sd_reg_reg (code
, X86_SSE_HADD
, ins
->sreg1
, ins
->sreg2
);
4311 x86_sse_alu_sd_reg_reg (code
, X86_SSE_HSUB
, ins
->sreg1
, ins
->sreg2
);
4314 x86_sse_alu_ss_reg_reg (code
, X86_SSE_MOVSHDUP
, ins
->dreg
, ins
->sreg1
);
4317 x86_sse_alu_ss_reg_reg (code
, X86_SSE_MOVSLDUP
, ins
->dreg
, ins
->sreg1
);
4320 case OP_PSHUFLEW_HIGH
:
4321 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 0xFF);
4322 x86_pshufw_reg_reg (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
, 1);
4324 case OP_PSHUFLEW_LOW
:
4325 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 0xFF);
4326 x86_pshufw_reg_reg (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
, 0);
4329 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 0xFF);
4330 x86_sse_shift_reg_imm (code
, X86_SSE_PSHUFD
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
);
4333 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 0xFF);
4334 x86_sse_alu_reg_reg_imm8 (code
, X86_SSE_SHUFP
, ins
->sreg1
, ins
->sreg2
, ins
->inst_c0
);
4337 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 0x3);
4338 x86_sse_alu_pd_reg_reg_imm8 (code
, X86_SSE_SHUFP
, ins
->sreg1
, ins
->sreg2
, ins
->inst_c0
);
4342 x86_sse_alu_pd_reg_reg (code
, X86_SSE_ADD
, ins
->sreg1
, ins
->sreg2
);
4345 x86_sse_alu_pd_reg_reg (code
, X86_SSE_DIV
, ins
->sreg1
, ins
->sreg2
);
4348 x86_sse_alu_pd_reg_reg (code
, X86_SSE_MUL
, ins
->sreg1
, ins
->sreg2
);
4351 x86_sse_alu_pd_reg_reg (code
, X86_SSE_SUB
, ins
->sreg1
, ins
->sreg2
);
4354 x86_sse_alu_pd_reg_reg (code
, X86_SSE_MAX
, ins
->sreg1
, ins
->sreg2
);
4357 x86_sse_alu_pd_reg_reg (code
, X86_SSE_MIN
, ins
->sreg1
, ins
->sreg2
);
4360 g_assert (ins
->inst_c0
>= 0 && ins
->inst_c0
<= 7);
4361 x86_sse_alu_pd_reg_reg_imm (code
, X86_SSE_COMP
, ins
->sreg1
, ins
->sreg2
, ins
->inst_c0
);
4364 x86_sse_alu_pd_reg_reg (code
, X86_SSE_AND
, ins
->sreg1
, ins
->sreg2
);
4367 x86_sse_alu_pd_reg_reg (code
, X86_SSE_ANDN
, ins
->sreg1
, ins
->sreg2
);
4370 x86_sse_alu_pd_reg_reg (code
, X86_SSE_OR
, ins
->sreg1
, ins
->sreg2
);
4373 x86_sse_alu_pd_reg_reg (code
, X86_SSE_XOR
, ins
->sreg1
, ins
->sreg2
);
4376 x86_sse_alu_pd_reg_reg (code
, X86_SSE_SQRT
, ins
->dreg
, ins
->sreg1
);
4379 x86_sse_alu_pd_reg_reg (code
, X86_SSE_ADDSUB
, ins
->sreg1
, ins
->sreg2
);
4382 x86_sse_alu_pd_reg_reg (code
, X86_SSE_HADD
, ins
->sreg1
, ins
->sreg2
);
4385 x86_sse_alu_pd_reg_reg (code
, X86_SSE_HSUB
, ins
->sreg1
, ins
->sreg2
);
4388 x86_sse_alu_sd_reg_reg (code
, X86_SSE_MOVDDUP
, ins
->dreg
, ins
->sreg1
);
4391 case OP_EXTRACT_MASK
:
4392 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PMOVMSKB
, ins
->dreg
, ins
->sreg1
);
4396 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PAND
, ins
->sreg1
, ins
->sreg2
);
4399 x86_sse_alu_pd_reg_reg (code
, X86_SSE_POR
, ins
->sreg1
, ins
->sreg2
);
4402 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PXOR
, ins
->sreg1
, ins
->sreg2
);
4406 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PADDB
, ins
->sreg1
, ins
->sreg2
);
4409 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PADDW
, ins
->sreg1
, ins
->sreg2
);
4412 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PADDD
, ins
->sreg1
, ins
->sreg2
);
4415 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PADDQ
, ins
->sreg1
, ins
->sreg2
);
4419 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PSUBB
, ins
->sreg1
, ins
->sreg2
);
4422 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PSUBW
, ins
->sreg1
, ins
->sreg2
);
4425 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PSUBD
, ins
->sreg1
, ins
->sreg2
);
4428 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PSUBQ
, ins
->sreg1
, ins
->sreg2
);
4432 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PMAXUB
, ins
->sreg1
, ins
->sreg2
);
4435 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PMAXUW
, ins
->sreg1
, ins
->sreg2
);
4438 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PMAXUD
, ins
->sreg1
, ins
->sreg2
);
4442 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PMAXSB
, ins
->sreg1
, ins
->sreg2
);
4445 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PMAXSW
, ins
->sreg1
, ins
->sreg2
);
4448 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PMAXSD
, ins
->sreg1
, ins
->sreg2
);
4452 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PAVGB
, ins
->sreg1
, ins
->sreg2
);
4455 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PAVGW
, ins
->sreg1
, ins
->sreg2
);
4459 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PMINUB
, ins
->sreg1
, ins
->sreg2
);
4462 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PMINUW
, ins
->sreg1
, ins
->sreg2
);
4465 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PMINUD
, ins
->sreg1
, ins
->sreg2
);
4469 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PMINSB
, ins
->sreg1
, ins
->sreg2
);
4472 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PMINSW
, ins
->sreg1
, ins
->sreg2
);
4475 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PMINSD
, ins
->sreg1
, ins
->sreg2
);
4479 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PCMPEQB
, ins
->sreg1
, ins
->sreg2
);
4482 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PCMPEQW
, ins
->sreg1
, ins
->sreg2
);
4485 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PCMPEQD
, ins
->sreg1
, ins
->sreg2
);
4488 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PCMPEQQ
, ins
->sreg1
, ins
->sreg2
);
4492 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PCMPGTB
, ins
->sreg1
, ins
->sreg2
);
4495 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PCMPGTW
, ins
->sreg1
, ins
->sreg2
);
4498 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PCMPGTD
, ins
->sreg1
, ins
->sreg2
);
4501 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PCMPGTQ
, ins
->sreg1
, ins
->sreg2
);
4504 case OP_PSUM_ABS_DIFF
:
4505 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PSADBW
, ins
->sreg1
, ins
->sreg2
);
4508 case OP_UNPACK_LOWB
:
4509 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PUNPCKLBW
, ins
->sreg1
, ins
->sreg2
);
4511 case OP_UNPACK_LOWW
:
4512 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PUNPCKLWD
, ins
->sreg1
, ins
->sreg2
);
4514 case OP_UNPACK_LOWD
:
4515 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PUNPCKLDQ
, ins
->sreg1
, ins
->sreg2
);
4517 case OP_UNPACK_LOWQ
:
4518 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PUNPCKLQDQ
, ins
->sreg1
, ins
->sreg2
);
4520 case OP_UNPACK_LOWPS
:
4521 x86_sse_alu_ps_reg_reg (code
, X86_SSE_UNPCKL
, ins
->sreg1
, ins
->sreg2
);
4523 case OP_UNPACK_LOWPD
:
4524 x86_sse_alu_pd_reg_reg (code
, X86_SSE_UNPCKL
, ins
->sreg1
, ins
->sreg2
);
4527 case OP_UNPACK_HIGHB
:
4528 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PUNPCKHBW
, ins
->sreg1
, ins
->sreg2
);
4530 case OP_UNPACK_HIGHW
:
4531 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PUNPCKHWD
, ins
->sreg1
, ins
->sreg2
);
4533 case OP_UNPACK_HIGHD
:
4534 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PUNPCKHDQ
, ins
->sreg1
, ins
->sreg2
);
4536 case OP_UNPACK_HIGHQ
:
4537 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PUNPCKHQDQ
, ins
->sreg1
, ins
->sreg2
);
4539 case OP_UNPACK_HIGHPS
:
4540 x86_sse_alu_ps_reg_reg (code
, X86_SSE_UNPCKH
, ins
->sreg1
, ins
->sreg2
);
4542 case OP_UNPACK_HIGHPD
:
4543 x86_sse_alu_pd_reg_reg (code
, X86_SSE_UNPCKH
, ins
->sreg1
, ins
->sreg2
);
4547 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PACKSSWB
, ins
->sreg1
, ins
->sreg2
);
4550 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PACKSSDW
, ins
->sreg1
, ins
->sreg2
);
4553 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PACKUSWB
, ins
->sreg1
, ins
->sreg2
);
4556 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PACKUSDW
, ins
->sreg1
, ins
->sreg2
);
4559 case OP_PADDB_SAT_UN
:
4560 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PADDUSB
, ins
->sreg1
, ins
->sreg2
);
4562 case OP_PSUBB_SAT_UN
:
4563 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PSUBUSB
, ins
->sreg1
, ins
->sreg2
);
4565 case OP_PADDW_SAT_UN
:
4566 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PADDUSW
, ins
->sreg1
, ins
->sreg2
);
4568 case OP_PSUBW_SAT_UN
:
4569 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PSUBUSW
, ins
->sreg1
, ins
->sreg2
);
4573 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PADDSB
, ins
->sreg1
, ins
->sreg2
);
4576 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PSUBSB
, ins
->sreg1
, ins
->sreg2
);
4579 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PADDSW
, ins
->sreg1
, ins
->sreg2
);
4582 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PSUBSW
, ins
->sreg1
, ins
->sreg2
);
4586 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PMULLW
, ins
->sreg1
, ins
->sreg2
);
4589 x86_sse_alu_sse41_reg_reg (code
, X86_SSE_PMULLD
, ins
->sreg1
, ins
->sreg2
);
4592 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PMULUDQ
, ins
->sreg1
, ins
->sreg2
);
4594 case OP_PMULW_HIGH_UN
:
4595 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PMULHUW
, ins
->sreg1
, ins
->sreg2
);
4598 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PMULHW
, ins
->sreg1
, ins
->sreg2
);
4602 x86_sse_shift_reg_imm (code
, X86_SSE_PSHIFTW
, X86_SSE_SHR
, ins
->dreg
, ins
->inst_imm
);
4605 x86_sse_shift_reg_reg (code
, X86_SSE_PSRLW_REG
, ins
->dreg
, ins
->sreg2
);
4609 x86_sse_shift_reg_imm (code
, X86_SSE_PSHIFTW
, X86_SSE_SAR
, ins
->dreg
, ins
->inst_imm
);
4612 x86_sse_shift_reg_reg (code
, X86_SSE_PSRAW_REG
, ins
->dreg
, ins
->sreg2
);
4616 x86_sse_shift_reg_imm (code
, X86_SSE_PSHIFTW
, X86_SSE_SHL
, ins
->dreg
, ins
->inst_imm
);
4619 x86_sse_shift_reg_reg (code
, X86_SSE_PSLLW_REG
, ins
->dreg
, ins
->sreg2
);
4623 x86_sse_shift_reg_imm (code
, X86_SSE_PSHIFTD
, X86_SSE_SHR
, ins
->dreg
, ins
->inst_imm
);
4626 x86_sse_shift_reg_reg (code
, X86_SSE_PSRLD_REG
, ins
->dreg
, ins
->sreg2
);
4630 x86_sse_shift_reg_imm (code
, X86_SSE_PSHIFTD
, X86_SSE_SAR
, ins
->dreg
, ins
->inst_imm
);
4633 x86_sse_shift_reg_reg (code
, X86_SSE_PSRAD_REG
, ins
->dreg
, ins
->sreg2
);
4637 x86_sse_shift_reg_imm (code
, X86_SSE_PSHIFTD
, X86_SSE_SHL
, ins
->dreg
, ins
->inst_imm
);
4640 x86_sse_shift_reg_reg (code
, X86_SSE_PSLLD_REG
, ins
->dreg
, ins
->sreg2
);
4644 x86_sse_shift_reg_imm (code
, X86_SSE_PSHIFTQ
, X86_SSE_SHR
, ins
->dreg
, ins
->inst_imm
);
4647 x86_sse_shift_reg_reg (code
, X86_SSE_PSRLQ_REG
, ins
->dreg
, ins
->sreg2
);
4651 x86_sse_shift_reg_imm (code
, X86_SSE_PSHIFTQ
, X86_SSE_SHL
, ins
->dreg
, ins
->inst_imm
);
4654 x86_sse_shift_reg_reg (code
, X86_SSE_PSLLQ_REG
, ins
->dreg
, ins
->sreg2
);
4658 x86_movd_xreg_reg (code
, ins
->dreg
, ins
->sreg1
);
4661 x86_movd_reg_xreg (code
, ins
->dreg
, ins
->sreg1
);
4665 x86_movd_reg_xreg (code
, ins
->dreg
, ins
->sreg1
);
4667 x86_shift_reg_imm (code
, X86_SHR
, ins
->dreg
, ins
->inst_c0
* 8);
4668 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, ins
->opcode
== OP_EXTRACT_I1
, FALSE
);
4672 x86_movd_reg_xreg (code
, ins
->dreg
, ins
->sreg1
);
4674 x86_shift_reg_imm (code
, X86_SHR
, ins
->dreg
, 16);
4675 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, ins
->opcode
== OP_EXTRACT_I2
, TRUE
);
4679 x86_sse_alu_pd_membase_reg (code
, X86_SSE_MOVHPD_MEMBASE_REG
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, ins
->sreg1
);
4681 x86_sse_alu_sd_membase_reg (code
, X86_SSE_MOVSD_MEMBASE_REG
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, ins
->sreg1
);
4682 x86_fld_membase (code
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, TRUE
);
4686 x86_sse_alu_pd_reg_reg_imm (code
, X86_SSE_PINSRW
, ins
->sreg1
, ins
->sreg2
, ins
->inst_c0
);
4688 case OP_EXTRACTX_U2
:
4689 x86_sse_alu_pd_reg_reg_imm (code
, X86_SSE_PEXTRW
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
);
4691 case OP_INSERTX_U1_SLOW
:
4692 /*sreg1 is the extracted ireg (scratch)
4693 /sreg2 is the to be inserted ireg (scratch)
4694 /dreg is the xreg to receive the value*/
4696 /*clear the bits from the extracted word*/
4697 x86_alu_reg_imm (code
, X86_AND
, ins
->sreg1
, ins
->inst_c0
& 1 ? 0x00FF : 0xFF00);
4698 /*shift the value to insert if needed*/
4699 if (ins
->inst_c0
& 1)
4700 x86_shift_reg_imm (code
, X86_SHL
, ins
->sreg2
, 8);
4701 /*join them together*/
4702 x86_alu_reg_reg (code
, X86_OR
, ins
->sreg1
, ins
->sreg2
);
4703 x86_sse_alu_pd_reg_reg_imm (code
, X86_SSE_PINSRW
, ins
->dreg
, ins
->sreg1
, ins
->inst_c0
/ 2);
4705 case OP_INSERTX_I4_SLOW
:
4706 x86_sse_alu_pd_reg_reg_imm (code
, X86_SSE_PINSRW
, ins
->dreg
, ins
->sreg2
, ins
->inst_c0
* 2);
4707 x86_shift_reg_imm (code
, X86_SHR
, ins
->sreg2
, 16);
4708 x86_sse_alu_pd_reg_reg_imm (code
, X86_SSE_PINSRW
, ins
->dreg
, ins
->sreg2
, ins
->inst_c0
* 2 + 1);
4711 case OP_INSERTX_R4_SLOW
:
4712 x86_fst_membase (code
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, FALSE
, TRUE
);
4713 /*TODO if inst_c0 == 0 use movss*/
4714 x86_sse_alu_pd_reg_membase_imm (code
, X86_SSE_PINSRW
, ins
->dreg
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
+ 0, ins
->inst_c0
* 2);
4715 x86_sse_alu_pd_reg_membase_imm (code
, X86_SSE_PINSRW
, ins
->dreg
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
+ 2, ins
->inst_c0
* 2 + 1);
4717 case OP_INSERTX_R8_SLOW
:
4718 x86_fst_membase (code
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, TRUE
, TRUE
);
4719 if (cfg
->verbose_level
)
4720 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins
->inst_c0
, offset
);
4722 x86_sse_alu_pd_reg_membase (code
, X86_SSE_MOVHPD_REG_MEMBASE
, ins
->dreg
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
);
4724 x86_movsd_reg_membase (code
, ins
->dreg
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
);
4727 case OP_STOREX_MEMBASE_REG
:
4728 case OP_STOREX_MEMBASE
:
4729 x86_movups_membase_reg (code
, ins
->dreg
, ins
->inst_offset
, ins
->sreg1
);
4731 case OP_LOADX_MEMBASE
:
4732 x86_movups_reg_membase (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_offset
);
4734 case OP_LOADX_ALIGNED_MEMBASE
:
4735 x86_movaps_reg_membase (code
, ins
->dreg
, ins
->sreg1
, ins
->inst_offset
);
4737 case OP_STOREX_ALIGNED_MEMBASE_REG
:
4738 x86_movaps_membase_reg (code
, ins
->dreg
, ins
->inst_offset
, ins
->sreg1
);
4740 case OP_STOREX_NTA_MEMBASE_REG
:
4741 x86_sse_alu_reg_membase (code
, X86_SSE_MOVNTPS
, ins
->dreg
, ins
->sreg1
, ins
->inst_offset
);
4743 case OP_PREFETCH_MEMBASE
:
4744 x86_sse_alu_reg_membase (code
, X86_SSE_PREFETCH
, ins
->backend
.arg_info
, ins
->sreg1
, ins
->inst_offset
);
4748 /*FIXME the peephole pass should have killed this*/
4749 if (ins
->dreg
!= ins
->sreg1
)
4750 x86_movaps_reg_reg (code
, ins
->dreg
, ins
->sreg1
);
4753 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PXOR
, ins
->dreg
, ins
->dreg
);
4756 x86_sse_alu_pd_reg_reg (code
, X86_SSE_PCMPEQB
, ins
->dreg
, ins
->dreg
);
4759 case OP_FCONV_TO_R8_X
:
4760 x86_fst_membase (code
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, TRUE
, TRUE
);
4761 x86_movsd_reg_membase (code
, ins
->dreg
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
);
4764 case OP_XCONV_R8_TO_I4
:
4765 x86_cvttsd2si (code
, ins
->dreg
, ins
->sreg1
);
4766 switch (ins
->backend
.source_opcode
) {
4767 case OP_FCONV_TO_I1
:
4768 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, TRUE
, FALSE
);
4770 case OP_FCONV_TO_U1
:
4771 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, FALSE
);
4773 case OP_FCONV_TO_I2
:
4774 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, TRUE
, TRUE
);
4776 case OP_FCONV_TO_U2
:
4777 x86_widen_reg (code
, ins
->dreg
, ins
->dreg
, FALSE
, TRUE
);
4783 x86_sse_alu_pd_reg_reg_imm (code
, X86_SSE_PINSRW
, ins
->dreg
, ins
->sreg1
, 0);
4784 x86_sse_alu_pd_reg_reg_imm (code
, X86_SSE_PINSRW
, ins
->dreg
, ins
->sreg1
, 1);
4785 x86_sse_shift_reg_imm (code
, X86_SSE_PSHUFD
, ins
->dreg
, ins
->dreg
, 0);
4788 x86_movd_xreg_reg (code
, ins
->dreg
, ins
->sreg1
);
4789 x86_sse_shift_reg_imm (code
, X86_SSE_PSHUFD
, ins
->dreg
, ins
->dreg
, 0);
4792 x86_fst_membase (code
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, FALSE
, TRUE
);
4793 x86_movd_xreg_membase (code
, ins
->dreg
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
);
4794 x86_sse_shift_reg_imm (code
, X86_SSE_PSHUFD
, ins
->dreg
, ins
->dreg
, 0);
4797 x86_fst_membase (code
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
, TRUE
, TRUE
);
4798 x86_movsd_reg_membase (code
, ins
->dreg
, ins
->backend
.spill_var
->inst_basereg
, ins
->backend
.spill_var
->inst_offset
);
4799 x86_sse_shift_reg_imm (code
, X86_SSE_PSHUFD
, ins
->dreg
, ins
->dreg
, 0x44);
4803 x86_sse_alu_ss_reg_reg (code
, X86_SSE_CVTDQ2PD
, ins
->dreg
, ins
->sreg1
);
4806 x86_sse_alu_ps_reg_reg (code
, X86_SSE_CVTDQ2PS
, ins
->dreg
, ins
->sreg1
);
4809 x86_sse_alu_sd_reg_reg (code
, X86_SSE_CVTPD2DQ
, ins
->dreg
, ins
->sreg1
);
4812 x86_sse_alu_pd_reg_reg (code
, X86_SSE_CVTPD2PS
, ins
->dreg
, ins
->sreg1
);
4815 x86_sse_alu_pd_reg_reg (code
, X86_SSE_CVTPS2DQ
, ins
->dreg
, ins
->sreg1
);
4818 x86_sse_alu_ps_reg_reg (code
, X86_SSE_CVTPS2PD
, ins
->dreg
, ins
->sreg1
);
4821 x86_sse_alu_pd_reg_reg (code
, X86_SSE_CVTTPD2DQ
, ins
->dreg
, ins
->sreg1
);
4824 x86_sse_alu_ss_reg_reg (code
, X86_SSE_CVTTPS2DQ
, ins
->dreg
, ins
->sreg1
);
4828 case OP_LIVERANGE_START
: {
4829 if (cfg
->verbose_level
> 1)
4830 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg
, ins
->inst_c0
)->vreg
, (int)(code
- cfg
->native_code
));
4831 MONO_VARINFO (cfg
, ins
->inst_c0
)->live_range_start
= code
- cfg
->native_code
;
4834 case OP_LIVERANGE_END
: {
4835 if (cfg
->verbose_level
> 1)
4836 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg
, ins
->inst_c0
)->vreg
, (int)(code
- cfg
->native_code
));
4837 MONO_VARINFO (cfg
, ins
->inst_c0
)->live_range_end
= code
- cfg
->native_code
;
4840 case OP_GC_SAFE_POINT
: {
4843 x86_test_membase_imm (code
, ins
->sreg1
, 0, 1);
4844 br
[0] = code
; x86_branch8 (code
, X86_CC_EQ
, 0, FALSE
);
4845 code
= emit_call (cfg
, code
, MONO_PATCH_INFO_JIT_ICALL_ID
, GUINT_TO_POINTER (MONO_JIT_ICALL_mono_threads_state_poll
));
4846 x86_patch (br
[0], code
);
4850 case OP_GC_LIVENESS_DEF
:
4851 case OP_GC_LIVENESS_USE
:
4852 case OP_GC_PARAM_SLOT_LIVENESS_DEF
:
4853 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
4855 case OP_GC_SPILL_SLOT_LIVENESS_DEF
:
4856 ins
->backend
.pc_offset
= code
- cfg
->native_code
;
4857 bb
->spill_slot_defs
= g_slist_prepend_mempool (cfg
->mempool
, bb
->spill_slot_defs
, ins
);
4860 x86_mov_reg_reg (code
, ins
->dreg
, X86_ESP
);
4863 x86_mov_reg_reg (code
, X86_ESP
, ins
->sreg1
);
4865 case OP_FILL_PROF_CALL_CTX
:
4866 x86_mov_membase_reg (code
, ins
->sreg1
, MONO_STRUCT_OFFSET (MonoContext
, esp
), X86_ESP
, sizeof (target_mgreg_t
));
4867 x86_mov_membase_reg (code
, ins
->sreg1
, MONO_STRUCT_OFFSET (MonoContext
, ebp
), X86_EBP
, sizeof (target_mgreg_t
));
4868 x86_mov_membase_reg (code
, ins
->sreg1
, MONO_STRUCT_OFFSET (MonoContext
, ebx
), X86_EBX
, sizeof (target_mgreg_t
));
4869 x86_mov_membase_reg (code
, ins
->sreg1
, MONO_STRUCT_OFFSET (MonoContext
, esi
), X86_ESI
, sizeof (target_mgreg_t
));
4870 x86_mov_membase_reg (code
, ins
->sreg1
, MONO_STRUCT_OFFSET (MonoContext
, edi
), X86_EDI
, sizeof (target_mgreg_t
));
4872 case OP_GET_LAST_ERROR
:
4873 code
= emit_get_last_error (code
, ins
->dreg
);
4876 g_warning ("unknown opcode %s\n", mono_inst_name (ins
->opcode
));
4877 g_assert_not_reached ();
4880 if (G_UNLIKELY ((code
- cfg
->native_code
- offset
) > max_len
)) {
4881 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4882 mono_inst_name (ins
->opcode
), max_len
, code
- cfg
->native_code
- offset
);
4883 g_assert_not_reached ();
4889 set_code_cursor (cfg
, code
);
4892 #endif /* DISABLE_JIT */
4895 mono_arch_register_lowlevel_calls (void)
4900 mono_arch_patch_code_new (MonoCompile
*cfg
, MonoDomain
*domain
, guint8
*code
, MonoJumpInfo
*ji
, gpointer target
)
4902 unsigned char *ip
= ji
->ip
.i
+ code
;
4905 case MONO_PATCH_INFO_IP
:
4906 *((gconstpointer
*)(ip
)) = target
;
4908 case MONO_PATCH_INFO_ABS
:
4909 case MONO_PATCH_INFO_METHOD
:
4910 case MONO_PATCH_INFO_METHOD_JUMP
:
4911 case MONO_PATCH_INFO_JIT_ICALL_ID
:
4912 case MONO_PATCH_INFO_BB
:
4913 case MONO_PATCH_INFO_LABEL
:
4914 case MONO_PATCH_INFO_RGCTX_FETCH
:
4915 case MONO_PATCH_INFO_JIT_ICALL_ADDR
:
4916 case MONO_PATCH_INFO_SPECIFIC_TRAMPOLINE_LAZY_FETCH_ADDR
:
4917 x86_patch (ip
, (unsigned char*)target
);
4919 case MONO_PATCH_INFO_NONE
:
4921 case MONO_PATCH_INFO_R4
:
4922 case MONO_PATCH_INFO_R8
: {
4923 guint32 offset
= mono_arch_get_patch_offset (ip
);
4924 *((gconstpointer
*)(ip
+ offset
)) = target
;
4928 guint32 offset
= mono_arch_get_patch_offset (ip
);
4929 *((gconstpointer
*)(ip
+ offset
)) = target
;
4935 static G_GNUC_UNUSED
void
4936 stack_unaligned (MonoMethod
*m
, gpointer caller
)
4938 printf ("%s\n", mono_method_full_name (m
, TRUE
));
4939 g_assert_not_reached ();
4943 mono_arch_emit_prolog (MonoCompile
*cfg
)
4945 MonoMethod
*method
= cfg
->method
;
4947 MonoMethodSignature
*sig
;
4951 int alloc_size
, pos
, max_offset
, i
, cfa_offset
;
4953 gboolean need_stack_frame
;
4955 cfg
->code_size
= MAX (cfg
->header
->code_size
* 4, 10240);
4957 code
= cfg
->native_code
= g_malloc (cfg
->code_size
);
4963 /* Check that the stack is aligned on osx */
4964 x86_mov_reg_reg (code
, X86_EAX
, X86_ESP
);
4965 x86_alu_reg_imm (code
, X86_AND
, X86_EAX
, 15);
4966 x86_alu_reg_imm (code
, X86_CMP
, X86_EAX
, 0xc);
4968 x86_branch_disp (code
, X86_CC_Z
, 0, FALSE
);
4969 x86_push_membase (code
, X86_ESP
, 0);
4970 x86_push_imm (code
, cfg
->method
);
4971 x86_mov_reg_imm (code
, X86_EAX
, stack_unaligned
);
4972 x86_call_reg (code
, X86_EAX
);
4973 x86_patch (br
[0], code
);
4977 /* Offset between RSP and the CFA */
4982 mono_emit_unwind_op_def_cfa (cfg
, code
, X86_ESP
, cfa_offset
);
4983 // IP saved at CFA - 4
4984 /* There is no IP reg on x86 */
4985 mono_emit_unwind_op_offset (cfg
, code
, X86_NREG
, -cfa_offset
);
4986 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
, SLOT_NOREF
);
4988 need_stack_frame
= needs_stack_frame (cfg
);
4990 if (need_stack_frame
) {
4991 x86_push_reg (code
, X86_EBP
);
4993 mono_emit_unwind_op_def_cfa_offset (cfg
, code
, cfa_offset
);
4994 mono_emit_unwind_op_offset (cfg
, code
, X86_EBP
, - cfa_offset
);
4995 x86_mov_reg_reg (code
, X86_EBP
, X86_ESP
);
4996 mono_emit_unwind_op_def_cfa_reg (cfg
, code
, X86_EBP
);
4997 /* These are handled automatically by the stack marking code */
4998 mini_gc_set_slot_type_from_cfa (cfg
, -cfa_offset
, SLOT_NOREF
);
5000 cfg
->frame_reg
= X86_ESP
;
5003 cfg
->stack_offset
+= cfg
->param_area
;
5004 cfg
->stack_offset
= ALIGN_TO (cfg
->stack_offset
, MONO_ARCH_FRAME_ALIGNMENT
);
5006 alloc_size
= cfg
->stack_offset
;
5009 if (!method
->save_lmf
) {
5010 if (cfg
->used_int_regs
& (1 << X86_EBX
)) {
5011 x86_push_reg (code
, X86_EBX
);
5014 mono_emit_unwind_op_offset (cfg
, code
, X86_EBX
, - cfa_offset
);
5015 /* These are handled automatically by the stack marking code */
5016 mini_gc_set_slot_type_from_cfa (cfg
, - cfa_offset
, SLOT_NOREF
);
5019 if (cfg
->used_int_regs
& (1 << X86_EDI
)) {
5020 x86_push_reg (code
, X86_EDI
);
5023 mono_emit_unwind_op_offset (cfg
, code
, X86_EDI
, - cfa_offset
);
5024 mini_gc_set_slot_type_from_cfa (cfg
, - cfa_offset
, SLOT_NOREF
);
5027 if (cfg
->used_int_regs
& (1 << X86_ESI
)) {
5028 x86_push_reg (code
, X86_ESI
);
5031 mono_emit_unwind_op_offset (cfg
, code
, X86_ESI
, - cfa_offset
);
5032 mini_gc_set_slot_type_from_cfa (cfg
, - cfa_offset
, SLOT_NOREF
);
5038 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5039 if (mono_do_x86_stack_align
&& need_stack_frame
) {
5040 int tot
= alloc_size
+ pos
+ 4; /* ret ip */
5041 if (need_stack_frame
)
5043 tot
&= MONO_ARCH_FRAME_ALIGNMENT
- 1;
5045 alloc_size
+= MONO_ARCH_FRAME_ALIGNMENT
- tot
;
5046 for (i
= 0; i
< MONO_ARCH_FRAME_ALIGNMENT
- tot
; i
+= sizeof (target_mgreg_t
))
5047 mini_gc_set_slot_type_from_fp (cfg
, - (alloc_size
+ pos
- i
), SLOT_NOREF
);
5051 cfg
->arch
.sp_fp_offset
= alloc_size
+ pos
;
5054 /* See mono_emit_stack_alloc */
5055 #if defined (TARGET_WIN32) || defined (MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5056 guint32 remaining_size
= alloc_size
;
5057 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5058 guint32 required_code_size
= ((remaining_size
/ 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5059 set_code_cursor (cfg
, code
);
5060 code
= realloc_code (cfg
, required_code_size
);
5061 while (remaining_size
>= 0x1000) {
5062 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, 0x1000);
5063 x86_test_membase_reg (code
, X86_ESP
, 0, X86_ESP
);
5064 remaining_size
-= 0x1000;
5067 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, remaining_size
);
5069 x86_alu_reg_imm (code
, X86_SUB
, X86_ESP
, alloc_size
);
5072 g_assert (need_stack_frame
);
5075 if (cfg
->method
->wrapper_type
== MONO_WRAPPER_NATIVE_TO_MANAGED
||
5076 cfg
->method
->wrapper_type
== MONO_WRAPPER_RUNTIME_INVOKE
) {
5077 x86_alu_reg_imm (code
, X86_AND
, X86_ESP
, -MONO_ARCH_FRAME_ALIGNMENT
);
5080 #if DEBUG_STACK_ALIGNMENT
5081 /* check the stack is aligned */
5082 if (need_stack_frame
&& method
->wrapper_type
== MONO_WRAPPER_NONE
) {
5083 x86_mov_reg_reg (code
, X86_ECX
, X86_ESP
);
5084 x86_alu_reg_imm (code
, X86_AND
, X86_ECX
, MONO_ARCH_FRAME_ALIGNMENT
- 1);
5085 x86_alu_reg_imm (code
, X86_CMP
, X86_ECX
, 0);
5086 x86_branch_disp (code
, X86_CC_EQ
, 3, FALSE
);
5087 x86_breakpoint (code
);
5091 /* compute max_offset in order to use short forward jumps */
5093 if (cfg
->opt
& MONO_OPT_BRANCH
) {
5094 for (bb
= cfg
->bb_entry
; bb
; bb
= bb
->next_bb
) {
5096 bb
->max_offset
= max_offset
;
5098 /* max alignment for loops */
5099 if ((cfg
->opt
& MONO_OPT_LOOP
) && bb_is_loop_start (bb
))
5100 max_offset
+= LOOP_ALIGNMENT
;
5101 MONO_BB_FOR_EACH_INS (bb
, ins
) {
5102 if (ins
->opcode
== OP_LABEL
)
5103 ins
->inst_c1
= max_offset
;
5104 max_offset
+= ins_get_size (ins
->opcode
);
5109 /* store runtime generic context */
5110 if (cfg
->rgctx_var
) {
5111 g_assert (cfg
->rgctx_var
->opcode
== OP_REGOFFSET
&& cfg
->rgctx_var
->inst_basereg
== X86_EBP
);
5113 x86_mov_membase_reg (code
, X86_EBP
, cfg
->rgctx_var
->inst_offset
, MONO_ARCH_RGCTX_REG
, 4);
5116 if (method
->save_lmf
)
5117 code
= emit_setup_lmf (cfg
, code
, cfg
->lmf_var
->inst_offset
, cfa_offset
);
5122 if (cfg
->arch
.ss_tramp_var
) {
5123 /* Initialize ss_tramp_var */
5124 ins
= cfg
->arch
.ss_tramp_var
;
5125 g_assert (ins
->opcode
== OP_REGOFFSET
);
5127 g_assert (!cfg
->compile_aot
);
5128 x86_mov_membase_imm (code
, ins
->inst_basereg
, ins
->inst_offset
, (guint32
)&ss_trampoline
, 4);
5131 if (cfg
->arch
.bp_tramp_var
) {
5132 /* Initialize bp_tramp_var */
5133 ins
= cfg
->arch
.bp_tramp_var
;
5134 g_assert (ins
->opcode
== OP_REGOFFSET
);
5136 g_assert (!cfg
->compile_aot
);
5137 x86_mov_membase_imm (code
, ins
->inst_basereg
, ins
->inst_offset
, (guint32
)&bp_trampoline
, 4);
5141 /* load arguments allocated to register from the stack */
5142 sig
= mono_method_signature_internal (method
);
5145 cinfo
= cfg
->arch
.cinfo
;
5147 for (i
= 0; i
< sig
->param_count
+ sig
->hasthis
; ++i
) {
5148 inst
= cfg
->args
[pos
];
5149 ainfo
= &cinfo
->args
[pos
];
5150 if (inst
->opcode
== OP_REGVAR
) {
5151 if (storage_in_ireg (ainfo
->storage
)) {
5152 x86_mov_reg_reg (code
, inst
->dreg
, ainfo
->reg
);
5154 g_assert (need_stack_frame
);
5155 x86_mov_reg_membase (code
, inst
->dreg
, X86_EBP
, ainfo
->offset
+ ARGS_OFFSET
, 4);
5157 if (cfg
->verbose_level
> 2)
5158 g_print ("Argument %d assigned to register %s\n", pos
, mono_arch_regname (inst
->dreg
));
5160 if (storage_in_ireg (ainfo
->storage
)) {
5161 x86_mov_membase_reg (code
, inst
->inst_basereg
, inst
->inst_offset
, ainfo
->reg
, 4);
5167 set_code_cursor (cfg
, code
);
5173 mono_arch_emit_epilog (MonoCompile
*cfg
)
5175 MonoMethod
*method
= cfg
->method
;
5176 MonoMethodSignature
*sig
= mono_method_signature_internal (method
);
5178 guint32 stack_to_pop
;
5180 int max_epilog_size
= 16;
5182 gboolean need_stack_frame
= needs_stack_frame (cfg
);
5184 if (cfg
->method
->save_lmf
)
5185 max_epilog_size
+= 128;
5187 code
= realloc_code (cfg
, max_epilog_size
);
5189 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5192 if (method
->save_lmf
) {
5193 gint32 lmf_offset
= cfg
->lmf_var
->inst_offset
;
5195 /* restore caller saved regs */
5196 if (cfg
->used_int_regs
& (1 << X86_EBX
)) {
5197 x86_mov_reg_membase (code
, X86_EBX
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, ebx
), 4);
5200 if (cfg
->used_int_regs
& (1 << X86_EDI
)) {
5201 x86_mov_reg_membase (code
, X86_EDI
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, edi
), 4);
5203 if (cfg
->used_int_regs
& (1 << X86_ESI
)) {
5204 x86_mov_reg_membase (code
, X86_ESI
, cfg
->frame_reg
, lmf_offset
+ MONO_STRUCT_OFFSET (MonoLMF
, esi
), 4);
5207 /* EBP is restored by LEAVE */
5209 for (i
= 0; i
< X86_NREG
; ++i
) {
5210 if ((cfg
->used_int_regs
& X86_CALLER_REGS
& (1 << i
)) && (i
!= X86_EBP
)) {
5215 g_assert (!pos
|| need_stack_frame
);
5217 x86_lea_membase (code
, X86_ESP
, X86_EBP
, pos
);
5220 if (cfg
->used_int_regs
& (1 << X86_ESI
)) {
5221 x86_pop_reg (code
, X86_ESI
);
5223 if (cfg
->used_int_regs
& (1 << X86_EDI
)) {
5224 x86_pop_reg (code
, X86_EDI
);
5226 if (cfg
->used_int_regs
& (1 << X86_EBX
)) {
5227 x86_pop_reg (code
, X86_EBX
);
5231 /* Load returned vtypes into registers if needed */
5232 cinfo
= cfg
->arch
.cinfo
;
5233 if (cinfo
->ret
.storage
== ArgValuetypeInReg
) {
5234 for (quad
= 0; quad
< 2; quad
++) {
5235 switch (cinfo
->ret
.pair_storage
[quad
]) {
5237 x86_mov_reg_membase (code
, cinfo
->ret
.pair_regs
[quad
], cfg
->ret
->inst_basereg
, cfg
->ret
->inst_offset
+ (quad
* sizeof (target_mgreg_t
)), 4);
5239 case ArgOnFloatFpStack
:
5240 x86_fld_membase (code
, cfg
->ret
->inst_basereg
, cfg
->ret
->inst_offset
+ (quad
* sizeof (target_mgreg_t
)), FALSE
);
5242 case ArgOnDoubleFpStack
:
5243 x86_fld_membase (code
, cfg
->ret
->inst_basereg
, cfg
->ret
->inst_offset
+ (quad
* sizeof (target_mgreg_t
)), TRUE
);
5248 g_assert_not_reached ();
5253 if (need_stack_frame
)
5256 if (CALLCONV_IS_STDCALL (sig
)) {
5257 MonoJitArgumentInfo
*arg_info
= g_newa (MonoJitArgumentInfo
, sig
->param_count
+ 1);
5259 stack_to_pop
= mono_arch_get_argument_info (sig
, sig
->param_count
, arg_info
);
5260 } else if (cinfo
->callee_stack_pop
)
5261 stack_to_pop
= cinfo
->callee_stack_pop
;
5266 g_assert (need_stack_frame
);
5267 x86_ret_imm (code
, stack_to_pop
);
5272 set_code_cursor (cfg
, code
);
5276 mono_arch_emit_exceptions (MonoCompile
*cfg
)
5278 MonoJumpInfo
*patch_info
;
5281 MonoClass
*exc_classes
[16];
5282 guint8
*exc_throw_start
[16], *exc_throw_end
[16];
5286 /* Compute needed space */
5287 for (patch_info
= cfg
->patch_info
; patch_info
; patch_info
= patch_info
->next
) {
5288 if (patch_info
->type
== MONO_PATCH_INFO_EXC
)
5293 * make sure we have enough space for exceptions
5294 * 16 is the size of two push_imm instructions and a call
5296 if (cfg
->compile_aot
)
5297 code_size
= exc_count
* 32;
5299 code_size
= exc_count
* 16;
5301 code
= realloc_code (cfg
, code_size
);
5304 for (patch_info
= cfg
->patch_info
; patch_info
; patch_info
= patch_info
->next
) {
5305 switch (patch_info
->type
) {
5306 case MONO_PATCH_INFO_EXC
: {
5307 MonoClass
*exc_class
;
5311 x86_patch (patch_info
->ip
.i
+ cfg
->native_code
, code
);
5313 exc_class
= mono_class_load_from_name (mono_defaults
.corlib
, "System", patch_info
->data
.name
);
5314 throw_ip
= patch_info
->ip
.i
;
5316 /* Find a throw sequence for the same exception class */
5317 for (i
= 0; i
< nthrows
; ++i
)
5318 if (exc_classes
[i
] == exc_class
)
5321 x86_push_imm (code
, (exc_throw_end
[i
] - cfg
->native_code
) - throw_ip
);
5322 x86_jump_code (code
, exc_throw_start
[i
]);
5323 patch_info
->type
= MONO_PATCH_INFO_NONE
;
5328 /* Compute size of code following the push <OFFSET> */
5331 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5333 if ((code
- cfg
->native_code
) - throw_ip
< 126 - size
) {
5334 /* Use the shorter form */
5336 x86_push_imm (code
, 0);
5340 x86_push_imm (code
, 0xf0f0f0f0);
5345 exc_classes
[nthrows
] = exc_class
;
5346 exc_throw_start
[nthrows
] = code
;
5349 x86_push_imm (code
, m_class_get_type_token (exc_class
) - MONO_TOKEN_TYPE_DEF
);
5350 patch_info
->data
.jit_icall_id
= MONO_JIT_ICALL_mono_arch_throw_corlib_exception
;
5351 patch_info
->type
= MONO_PATCH_INFO_JIT_ICALL_ID
;
5352 patch_info
->ip
.i
= code
- cfg
->native_code
;
5353 x86_call_code (code
, 0);
5354 x86_push_imm (buf
, (code
- cfg
->native_code
) - throw_ip
);
5359 exc_throw_end
[nthrows
] = code
;
5369 set_code_cursor (cfg
, code
);
5371 set_code_cursor (cfg
, code
);
5376 mono_arch_flush_icache (guint8
*code
, gint size
)
5378 /* call/ret required (or likely other control transfer) */
5382 mono_arch_flush_register_windows (void)
5387 mono_arch_is_inst_imm (int opcode
, int imm_opcode
, gint64 imm
)
5393 mono_arch_finish_init (void)
5395 char *mono_no_tls
= g_getenv ("MONO_NO_TLS");
5397 #ifndef TARGET_WIN32
5399 optimize_for_xen
= access ("/proc/xen", F_OK
) == 0;
5403 g_free (mono_no_tls
);
5407 // Linear handler, the bsearch head compare is shorter
5408 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5409 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5410 // x86_patch(ins,target)
5411 //[1 + 5] x86_jump_mem(inst,mem)
5414 #define BR_SMALL_SIZE 2
5415 #define BR_LARGE_SIZE 5
5416 #define JUMP_IMM_SIZE 6
5417 #define ENABLE_WRONG_METHOD_CHECK 0
5421 imt_branch_distance (MonoIMTCheckItem
**imt_entries
, int start
, int target
)
5423 int i
, distance
= 0;
5424 for (i
= start
; i
< target
; ++i
)
5425 distance
+= imt_entries
[i
]->chunk_size
;
5430 * LOCKING: called with the domain lock held
5433 mono_arch_build_imt_trampoline (MonoVTable
*vtable
, MonoDomain
*domain
, MonoIMTCheckItem
**imt_entries
, int count
,
5434 gpointer fail_tramp
)
5438 guint8
*code
, *start
;
5441 for (i
= 0; i
< count
; ++i
) {
5442 MonoIMTCheckItem
*item
= imt_entries
[i
];
5443 if (item
->is_equals
) {
5444 if (item
->check_target_idx
) {
5445 if (!item
->compare_done
)
5446 item
->chunk_size
+= CMP_SIZE
;
5447 item
->chunk_size
+= BR_SMALL_SIZE
+ JUMP_IMM_SIZE
;
5450 item
->chunk_size
+= CMP_SIZE
+ BR_SMALL_SIZE
+ JUMP_IMM_SIZE
* 2;
5452 item
->chunk_size
+= JUMP_IMM_SIZE
;
5453 #if ENABLE_WRONG_METHOD_CHECK
5454 item
->chunk_size
+= CMP_SIZE
+ BR_SMALL_SIZE
+ 1;
5459 item
->chunk_size
+= CMP_SIZE
+ BR_LARGE_SIZE
;
5460 imt_entries
[item
->check_target_idx
]->compare_done
= TRUE
;
5462 size
+= item
->chunk_size
;
5465 code
= (guint8
*)mono_method_alloc_generic_virtual_trampoline (domain
, size
);
5467 code
= mono_domain_code_reserve (domain
, size
);
5470 unwind_ops
= mono_arch_get_cie_program ();
5472 for (i
= 0; i
< count
; ++i
) {
5473 MonoIMTCheckItem
*item
= imt_entries
[i
];
5474 item
->code_target
= code
;
5475 if (item
->is_equals
) {
5476 if (item
->check_target_idx
) {
5477 if (!item
->compare_done
)
5478 x86_alu_reg_imm (code
, X86_CMP
, MONO_ARCH_IMT_REG
, (guint32
)item
->key
);
5479 item
->jmp_code
= code
;
5480 x86_branch8 (code
, X86_CC_NE
, 0, FALSE
);
5481 if (item
->has_target_code
)
5482 x86_jump_code (code
, item
->value
.target_code
);
5484 x86_jump_mem (code
, & (vtable
->vtable
[item
->value
.vtable_slot
]));
5487 x86_alu_reg_imm (code
, X86_CMP
, MONO_ARCH_IMT_REG
, (guint32
)item
->key
);
5488 item
->jmp_code
= code
;
5489 x86_branch8 (code
, X86_CC_NE
, 0, FALSE
);
5490 if (item
->has_target_code
)
5491 x86_jump_code (code
, item
->value
.target_code
);
5493 x86_jump_mem (code
, & (vtable
->vtable
[item
->value
.vtable_slot
]));
5494 x86_patch (item
->jmp_code
, code
);
5495 x86_jump_code (code
, fail_tramp
);
5496 item
->jmp_code
= NULL
;
5498 /* enable the commented code to assert on wrong method */
5499 #if ENABLE_WRONG_METHOD_CHECK
5500 x86_alu_reg_imm (code
, X86_CMP
, MONO_ARCH_IMT_REG
, (guint32
)item
->key
);
5501 item
->jmp_code
= code
;
5502 x86_branch8 (code
, X86_CC_NE
, 0, FALSE
);
5504 if (item
->has_target_code
)
5505 x86_jump_code (code
, item
->value
.target_code
);
5507 x86_jump_mem (code
, & (vtable
->vtable
[item
->value
.vtable_slot
]));
5508 #if ENABLE_WRONG_METHOD_CHECK
5509 x86_patch (item
->jmp_code
, code
);
5510 x86_breakpoint (code
);
5511 item
->jmp_code
= NULL
;
5516 x86_alu_reg_imm (code
, X86_CMP
, MONO_ARCH_IMT_REG
, (guint32
)item
->key
);
5517 item
->jmp_code
= code
;
5518 if (x86_is_imm8 (imt_branch_distance (imt_entries
, i
, item
->check_target_idx
)))
5519 x86_branch8 (code
, X86_CC_GE
, 0, FALSE
);
5521 x86_branch32 (code
, X86_CC_GE
, 0, FALSE
);
5524 /* patch the branches to get to the target items */
5525 for (i
= 0; i
< count
; ++i
) {
5526 MonoIMTCheckItem
*item
= imt_entries
[i
];
5527 if (item
->jmp_code
) {
5528 if (item
->check_target_idx
) {
5529 x86_patch (item
->jmp_code
, imt_entries
[item
->check_target_idx
]->code_target
);
5535 UnlockedAdd (&mono_stats
.imt_trampolines_size
, code
- start
);
5536 g_assertf (code
- start
<= size
, "%d %d", (int)(code
- start
), size
);
5540 char *buff
= g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", m_class_get_name_space (vtable
->klass
), m_class_get_name (vtable
->klass
), count
);
5541 mono_disassemble_code (NULL
, (guint8
*)start
, code
- start
, buff
);
5545 if (mono_jit_map_is_enabled ()) {
5548 buff
= g_strdup_printf ("imt_%s_%s_entries_%d", m_class_get_name_space (vtable
->klass
), m_class_get_name (vtable
->klass
), count
);
5550 buff
= g_strdup_printf ("imt_trampoline_entries_%d", count
);
5551 mono_emit_jit_tramp (start
, code
- start
, buff
);
5555 MONO_PROFILER_RAISE (jit_code_buffer
, (start
, code
- start
, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE
, NULL
));
5557 mono_tramp_info_register (mono_tramp_info_create (NULL
, start
, code
- start
, NULL
, unwind_ops
), domain
);
5563 mono_arch_find_imt_method (host_mgreg_t
*regs
, guint8
*code
)
5565 return (MonoMethod
*) regs
[MONO_ARCH_IMT_REG
];
5569 mono_arch_find_static_call_vtable (host_mgreg_t
*regs
, guint8
*code
)
5571 return (MonoVTable
*) regs
[MONO_ARCH_RGCTX_REG
];
5575 mono_arch_get_cie_program (void)
5579 mono_add_unwind_op_def_cfa (l
, (guint8
*)NULL
, (guint8
*)NULL
, X86_ESP
, 4);
5580 mono_add_unwind_op_offset (l
, (guint8
*)NULL
, (guint8
*)NULL
, X86_NREG
, -4);
5586 mono_arch_emit_inst_for_method (MonoCompile
*cfg
, MonoMethod
*cmethod
, MonoMethodSignature
*fsig
, MonoInst
**args
)
5588 MonoInst
*ins
= NULL
;
5591 if (cmethod
->klass
== mono_class_try_get_math_class ()) {
5592 if (strcmp (cmethod
->name
, "Sin") == 0) {
5594 } else if (strcmp (cmethod
->name
, "Cos") == 0) {
5596 } else if (strcmp (cmethod
->name
, "Tan") == 0) {
5598 } else if (strcmp (cmethod
->name
, "Atan") == 0) {
5600 } else if (strcmp (cmethod
->name
, "Sqrt") == 0) {
5602 } else if (strcmp (cmethod
->name
, "Abs") == 0 && fsig
->params
[0]->type
== MONO_TYPE_R8
) {
5604 } else if (strcmp (cmethod
->name
, "Round") == 0 && fsig
->param_count
== 1 && fsig
->params
[0]->type
== MONO_TYPE_R8
) {
5608 if (opcode
&& fsig
->param_count
== 1) {
5609 MONO_INST_NEW (cfg
, ins
, opcode
);
5610 ins
->type
= STACK_R8
;
5611 ins
->dreg
= mono_alloc_freg (cfg
);
5612 ins
->sreg1
= args
[0]->dreg
;
5613 MONO_ADD_INS (cfg
->cbb
, ins
);
5616 if (cfg
->opt
& MONO_OPT_CMOV
) {
5619 if (strcmp (cmethod
->name
, "Min") == 0) {
5620 if (fsig
->params
[0]->type
== MONO_TYPE_I4
)
5622 } else if (strcmp (cmethod
->name
, "Max") == 0) {
5623 if (fsig
->params
[0]->type
== MONO_TYPE_I4
)
5627 if (opcode
&& fsig
->param_count
== 2) {
5628 MONO_INST_NEW (cfg
, ins
, opcode
);
5629 ins
->type
= STACK_I4
;
5630 ins
->dreg
= mono_alloc_ireg (cfg
);
5631 ins
->sreg1
= args
[0]->dreg
;
5632 ins
->sreg2
= args
[1]->dreg
;
5633 MONO_ADD_INS (cfg
->cbb
, ins
);
5638 /* OP_FREM is not IEEE compatible */
5639 else if (strcmp (cmethod
->name
, "IEEERemainder") == 0 && fsig
->param_count
== 2) {
5640 MONO_INST_NEW (cfg
, ins
, OP_FREM
);
5641 ins
->inst_i0
= args
[0];
5642 ins
->inst_i1
= args
[1];
5651 mono_arch_get_patch_offset (guint8
*code
)
5653 if ((code
[0] == 0x8b) && (x86_modrm_mod (code
[1]) == 0x2))
5655 else if (code
[0] == 0xba)
5657 else if (code
[0] == 0x68)
5660 else if ((code
[0] == 0xff) && (x86_modrm_reg (code
[1]) == 0x6))
5661 /* push <OFFSET>(<REG>) */
5663 else if ((code
[0] == 0xff) && (x86_modrm_reg (code
[1]) == 0x2))
5664 /* call *<OFFSET>(<REG>) */
5666 else if ((code
[0] == 0xdd) || (code
[0] == 0xd9))
5669 else if ((code
[0] == 0x58) && (code
[1] == 0x05))
5670 /* pop %eax; add <OFFSET>, %eax */
5672 else if ((code
[0] >= 0x58) && (code
[0] <= 0x58 + X86_NREG
) && (code
[1] == 0x81))
5673 /* pop <REG>; add <OFFSET>, <REG> */
5675 else if ((code
[0] >= 0xb8) && (code
[0] < 0xb8 + 8))
5676 /* mov <REG>, imm */
5678 else if (code
[0] == 0xE9)
5681 g_assert_not_reached ();
5686 * \return TRUE if no sw breakpoint was present.
5688 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
5689 * breakpoints in the original code, they are removed in the copy.
5692 mono_breakpoint_clean_code (guint8
*method_start
, guint8
*code
, int offset
, guint8
*buf
, int size
)
5695 * If method_start is non-NULL we need to perform bound checks, since we access memory
5696 * at code - offset we could go before the start of the method and end up in a different
5697 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5700 if (!method_start
|| code
- offset
>= method_start
) {
5701 memcpy (buf
, code
- offset
, size
);
5703 int diff
= code
- method_start
;
5704 memset (buf
, 0, size
);
5705 memcpy (buf
+ offset
- diff
, method_start
, diff
+ size
- offset
);
5711 * mono_x86_get_this_arg_offset:
5713 * Return the offset of the stack location where this is passed during a virtual
5717 mono_x86_get_this_arg_offset (MonoMethodSignature
*sig
)
5723 mono_arch_get_this_arg_from_call (host_mgreg_t
*regs
, guint8
*code
)
5725 host_mgreg_t esp
= regs
[X86_ESP
];
5732 * The stack looks like:
5736 res
= ((MonoObject
**)esp
) [0];
5740 #define MAX_ARCH_DELEGATE_PARAMS 10
5743 get_delegate_invoke_impl (MonoTrampInfo
**info
, gboolean has_target
, guint32 param_count
)
5745 guint8
*code
, *start
;
5746 int code_reserve
= 64;
5749 unwind_ops
= mono_arch_get_cie_program ();
5752 * The stack contains:
5758 start
= code
= mono_global_codeman_reserve (code_reserve
);
5760 /* Replace the this argument with the target */
5761 x86_mov_reg_membase (code
, X86_EAX
, X86_ESP
, 4, 4);
5762 x86_mov_reg_membase (code
, X86_ECX
, X86_EAX
, MONO_STRUCT_OFFSET (MonoDelegate
, target
), 4);
5763 x86_mov_membase_reg (code
, X86_ESP
, 4, X86_ECX
, 4);
5764 x86_jump_membase (code
, X86_EAX
, MONO_STRUCT_OFFSET (MonoDelegate
, method_ptr
));
5767 /* 8 for mov_reg and jump, plus 8 for each parameter */
5768 code_reserve
= 8 + (param_count
* 8);
5770 * The stack contains:
5771 * <args in reverse order>
5776 * <args in reverse order>
5779 * without unbalancing the stack.
5780 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5781 * and leaving original spot of first arg as placeholder in stack so
5782 * when callee pops stack everything works.
5785 start
= code
= mono_global_codeman_reserve (code_reserve
);
5787 /* store delegate for access to method_ptr */
5788 x86_mov_reg_membase (code
, X86_ECX
, X86_ESP
, 4, 4);
5791 for (i
= 0; i
< param_count
; ++i
) {
5792 x86_mov_reg_membase (code
, X86_EAX
, X86_ESP
, (i
+2)*4, 4);
5793 x86_mov_membase_reg (code
, X86_ESP
, (i
+1)*4, X86_EAX
, 4);
5796 x86_jump_membase (code
, X86_ECX
, MONO_STRUCT_OFFSET (MonoDelegate
, method_ptr
));
5799 g_assertf ((code
- start
) <= code_reserve
, "%d %d", (int)(code
- start
), code_reserve
);
5802 *info
= mono_tramp_info_create ("delegate_invoke_impl_has_target", start
, code
- start
, NULL
, unwind_ops
);
5804 char *name
= g_strdup_printf ("delegate_invoke_impl_target_%d", param_count
);
5805 *info
= mono_tramp_info_create (name
, start
, code
- start
, NULL
, unwind_ops
);
5809 if (mono_jit_map_is_enabled ()) {
5812 buff
= (char*)"delegate_invoke_has_target";
5814 buff
= g_strdup_printf ("delegate_invoke_no_target_%d", param_count
);
5815 mono_emit_jit_tramp (start
, code
- start
, buff
);
5819 MONO_PROFILER_RAISE (jit_code_buffer
, (start
, code
- start
, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE
, NULL
));
5824 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
5827 get_delegate_virtual_invoke_impl (MonoTrampInfo
**info
, gboolean load_imt_reg
, int offset
)
5829 guint8
*code
, *start
;
5834 if (offset
/ (int)sizeof (target_mgreg_t
) > MAX_VIRTUAL_DELEGATE_OFFSET
)
5838 * The stack contains:
5842 start
= code
= mono_global_codeman_reserve (size
);
5844 unwind_ops
= mono_arch_get_cie_program ();
5846 /* Replace the this argument with the target */
5847 x86_mov_reg_membase (code
, X86_EAX
, X86_ESP
, 4, 4);
5848 x86_mov_reg_membase (code
, X86_ECX
, X86_EAX
, MONO_STRUCT_OFFSET (MonoDelegate
, target
), 4);
5849 x86_mov_membase_reg (code
, X86_ESP
, 4, X86_ECX
, 4);
5852 /* Load the IMT reg */
5853 x86_mov_reg_membase (code
, MONO_ARCH_IMT_REG
, X86_EAX
, MONO_STRUCT_OFFSET (MonoDelegate
, method
), 4);
5856 /* Load the vtable */
5857 x86_mov_reg_membase (code
, X86_EAX
, X86_ECX
, MONO_STRUCT_OFFSET (MonoObject
, vtable
), 4);
5858 x86_jump_membase (code
, X86_EAX
, offset
);
5860 g_assertf ((code
- start
) <= size
, "%d %d", (int)(code
- start
), size
);
5862 MONO_PROFILER_RAISE (jit_code_buffer
, (start
, code
- start
, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE
, NULL
));
5864 tramp_name
= mono_get_delegate_virtual_invoke_impl_name (load_imt_reg
, offset
);
5865 *info
= mono_tramp_info_create (tramp_name
, start
, code
- start
, NULL
, unwind_ops
);
5866 g_free (tramp_name
);
5873 mono_arch_get_delegate_invoke_impls (void)
5876 MonoTrampInfo
*info
;
5879 get_delegate_invoke_impl (&info
, TRUE
, 0);
5880 res
= g_slist_prepend (res
, info
);
5882 for (i
= 0; i
<= MAX_ARCH_DELEGATE_PARAMS
; ++i
) {
5883 get_delegate_invoke_impl (&info
, FALSE
, i
);
5884 res
= g_slist_prepend (res
, info
);
5887 for (i
= 0; i
<= MAX_VIRTUAL_DELEGATE_OFFSET
; ++i
) {
5888 get_delegate_virtual_invoke_impl (&info
, TRUE
, - i
* TARGET_SIZEOF_VOID_P
);
5889 res
= g_slist_prepend (res
, info
);
5891 get_delegate_virtual_invoke_impl (&info
, FALSE
, i
* TARGET_SIZEOF_VOID_P
);
5892 res
= g_slist_prepend (res
, info
);
5899 mono_arch_get_delegate_invoke_impl (MonoMethodSignature
*sig
, gboolean has_target
)
5901 guint8
*code
, *start
;
5903 if (sig
->param_count
> MAX_ARCH_DELEGATE_PARAMS
)
5906 /* FIXME: Support more cases */
5907 if (MONO_TYPE_ISSTRUCT (sig
->ret
))
5911 * The stack contains:
5917 static guint8
* cached
= NULL
;
5921 if (mono_ee_features
.use_aot_trampolines
) {
5922 start
= (guint8
*)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
5924 MonoTrampInfo
*info
;
5925 start
= (guint8
*)get_delegate_invoke_impl (&info
, TRUE
, 0);
5926 mono_tramp_info_register (info
, NULL
);
5929 mono_memory_barrier ();
5933 static guint8
* cache
[MAX_ARCH_DELEGATE_PARAMS
+ 1] = {NULL
};
5936 for (i
= 0; i
< sig
->param_count
; ++i
)
5937 if (!mono_is_regsize_var (sig
->params
[i
]))
5940 code
= cache
[sig
->param_count
];
5944 if (mono_ee_features
.use_aot_trampolines
) {
5945 char *name
= g_strdup_printf ("delegate_invoke_impl_target_%d", sig
->param_count
);
5946 start
= (guint8
*)mono_aot_get_trampoline (name
);
5949 MonoTrampInfo
*info
;
5950 start
= (guint8
*)get_delegate_invoke_impl (&info
, FALSE
, sig
->param_count
);
5951 mono_tramp_info_register (info
, NULL
);
5954 mono_memory_barrier ();
5956 cache
[sig
->param_count
] = start
;
5963 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature
*sig
, MonoMethod
*method
, int offset
, gboolean load_imt_reg
)
5965 MonoTrampInfo
*info
;
5968 code
= get_delegate_virtual_invoke_impl (&info
, load_imt_reg
, offset
);
5970 mono_tramp_info_register (info
, NULL
);
5975 mono_arch_context_get_int_reg (MonoContext
*ctx
, int reg
)
5978 case X86_EAX
: return ctx
->eax
;
5979 case X86_EBX
: return ctx
->ebx
;
5980 case X86_ECX
: return ctx
->ecx
;
5981 case X86_EDX
: return ctx
->edx
;
5982 case X86_ESP
: return ctx
->esp
;
5983 case X86_EBP
: return ctx
->ebp
;
5984 case X86_ESI
: return ctx
->esi
;
5985 case X86_EDI
: return ctx
->edi
;
5987 g_assert_not_reached ();
5993 mono_arch_context_set_int_reg (MonoContext
*ctx
, int reg
, host_mgreg_t val
)
6021 g_assert_not_reached ();
6025 #ifdef MONO_ARCH_SIMD_INTRINSICS
6028 get_float_to_x_spill_area (MonoCompile
*cfg
)
6030 if (!cfg
->fconv_to_r8_x_var
) {
6031 cfg
->fconv_to_r8_x_var
= mono_compile_create_var (cfg
, m_class_get_byval_arg (mono_defaults
.double_class
), OP_LOCAL
);
6032 cfg
->fconv_to_r8_x_var
->flags
|= MONO_INST_VOLATILE
; /*FIXME, use the don't regalloc flag*/
6034 return cfg
->fconv_to_r8_x_var
;
6038 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6041 mono_arch_decompose_opts (MonoCompile
*cfg
, MonoInst
*ins
)
6044 int dreg
, src_opcode
;
6046 if (!(cfg
->opt
& MONO_OPT_SSE2
) || !(cfg
->opt
& MONO_OPT_SIMD
) || COMPILE_LLVM (cfg
))
6049 switch (src_opcode
= ins
->opcode
) {
6050 case OP_FCONV_TO_I1
:
6051 case OP_FCONV_TO_U1
:
6052 case OP_FCONV_TO_I2
:
6053 case OP_FCONV_TO_U2
:
6054 case OP_FCONV_TO_I4
:
6061 /* dreg is the IREG and sreg1 is the FREG */
6062 MONO_INST_NEW (cfg
, fconv
, OP_FCONV_TO_R8_X
);
6063 fconv
->klass
= NULL
; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6064 fconv
->sreg1
= ins
->sreg1
;
6065 fconv
->dreg
= mono_alloc_ireg (cfg
);
6066 fconv
->type
= STACK_VTYPE
;
6067 fconv
->backend
.spill_var
= get_float_to_x_spill_area (cfg
);
6069 mono_bblock_insert_before_ins (cfg
->cbb
, ins
, fconv
);
6073 ins
->opcode
= OP_XCONV_R8_TO_I4
;
6075 ins
->klass
= mono_defaults
.int32_class
;
6076 ins
->sreg1
= fconv
->dreg
;
6078 ins
->type
= STACK_I4
;
6079 ins
->backend
.source_opcode
= src_opcode
;
6082 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6085 mono_arch_decompose_long_opts (MonoCompile
*cfg
, MonoInst
*long_ins
)
6090 if (long_ins
->opcode
== OP_LNEG
) {
6092 MONO_EMIT_NEW_UNALU (cfg
, OP_INEG
, MONO_LVREG_LS (ins
->dreg
), MONO_LVREG_LS (ins
->sreg1
));
6093 MONO_EMIT_NEW_BIALU_IMM (cfg
, OP_ADC_IMM
, MONO_LVREG_MS (ins
->dreg
), MONO_LVREG_MS (ins
->sreg1
), 0);
6094 MONO_EMIT_NEW_UNALU (cfg
, OP_INEG
, MONO_LVREG_MS (ins
->dreg
), MONO_LVREG_MS (ins
->dreg
));
6099 #ifdef MONO_ARCH_SIMD_INTRINSICS
6101 if (!(cfg
->opt
& MONO_OPT_SIMD
))
6104 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6105 switch (long_ins
->opcode
) {
6107 vreg
= long_ins
->sreg1
;
6109 if (long_ins
->inst_c0
) {
6110 MONO_INST_NEW (cfg
, ins
, OP_PSHUFLED
);
6111 ins
->klass
= long_ins
->klass
;
6112 ins
->sreg1
= long_ins
->sreg1
;
6114 ins
->type
= STACK_VTYPE
;
6115 ins
->dreg
= vreg
= alloc_ireg (cfg
);
6116 MONO_ADD_INS (cfg
->cbb
, ins
);
6119 MONO_INST_NEW (cfg
, ins
, OP_EXTRACT_I4
);
6120 ins
->klass
= mono_defaults
.int32_class
;
6122 ins
->type
= STACK_I4
;
6123 ins
->dreg
= MONO_LVREG_LS (long_ins
->dreg
);
6124 MONO_ADD_INS (cfg
->cbb
, ins
);
6126 MONO_INST_NEW (cfg
, ins
, OP_PSHUFLED
);
6127 ins
->klass
= long_ins
->klass
;
6128 ins
->sreg1
= long_ins
->sreg1
;
6129 ins
->inst_c0
= long_ins
->inst_c0
? 3 : 1;
6130 ins
->type
= STACK_VTYPE
;
6131 ins
->dreg
= vreg
= alloc_ireg (cfg
);
6132 MONO_ADD_INS (cfg
->cbb
, ins
);
6134 MONO_INST_NEW (cfg
, ins
, OP_EXTRACT_I4
);
6135 ins
->klass
= mono_defaults
.int32_class
;
6137 ins
->type
= STACK_I4
;
6138 ins
->dreg
= MONO_LVREG_MS (long_ins
->dreg
);
6139 MONO_ADD_INS (cfg
->cbb
, ins
);
6141 long_ins
->opcode
= OP_NOP
;
6143 case OP_INSERTX_I8_SLOW
:
6144 MONO_INST_NEW (cfg
, ins
, OP_INSERTX_I4_SLOW
);
6145 ins
->dreg
= long_ins
->dreg
;
6146 ins
->sreg1
= long_ins
->dreg
;
6147 ins
->sreg2
= MONO_LVREG_LS (long_ins
->sreg2
);
6148 ins
->inst_c0
= long_ins
->inst_c0
* 2;
6149 MONO_ADD_INS (cfg
->cbb
, ins
);
6151 MONO_INST_NEW (cfg
, ins
, OP_INSERTX_I4_SLOW
);
6152 ins
->dreg
= long_ins
->dreg
;
6153 ins
->sreg1
= long_ins
->dreg
;
6154 ins
->sreg2
= MONO_LVREG_MS (long_ins
->sreg2
);
6155 ins
->inst_c0
= long_ins
->inst_c0
* 2 + 1;
6156 MONO_ADD_INS (cfg
->cbb
, ins
);
6158 long_ins
->opcode
= OP_NOP
;
6161 MONO_INST_NEW (cfg
, ins
, OP_ICONV_TO_X
);
6162 ins
->dreg
= long_ins
->dreg
;
6163 ins
->sreg1
= MONO_LVREG_LS (long_ins
->sreg1
);
6164 ins
->klass
= long_ins
->klass
;
6165 ins
->type
= STACK_VTYPE
;
6166 MONO_ADD_INS (cfg
->cbb
, ins
);
6168 MONO_INST_NEW (cfg
, ins
, OP_INSERTX_I4_SLOW
);
6169 ins
->dreg
= long_ins
->dreg
;
6170 ins
->sreg1
= long_ins
->dreg
;
6171 ins
->sreg2
= MONO_LVREG_MS (long_ins
->sreg1
);
6173 ins
->klass
= long_ins
->klass
;
6174 ins
->type
= STACK_VTYPE
;
6175 MONO_ADD_INS (cfg
->cbb
, ins
);
6177 MONO_INST_NEW (cfg
, ins
, OP_PSHUFLED
);
6178 ins
->dreg
= long_ins
->dreg
;
6179 ins
->sreg1
= long_ins
->dreg
;
6180 ins
->inst_c0
= 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6181 ins
->klass
= long_ins
->klass
;
6182 ins
->type
= STACK_VTYPE
;
6183 MONO_ADD_INS (cfg
->cbb
, ins
);
6185 long_ins
->opcode
= OP_NOP
;
6188 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6192 * mono_aot_emit_load_got_addr:
6194 * Emit code to load the got address.
6195 * On x86, the result is placed into EBX.
6198 mono_arch_emit_load_got_addr (guint8
*start
, guint8
*code
, MonoCompile
*cfg
, MonoJumpInfo
**ji
)
6200 x86_call_imm (code
, 0);
6202 * The patch needs to point to the pop, since the GOT offset needs
6203 * to be added to that address.
6206 mono_add_patch_info (cfg
, code
- cfg
->native_code
, MONO_PATCH_INFO_GOT_OFFSET
, NULL
);
6208 *ji
= mono_patch_info_list_prepend (*ji
, code
- start
, MONO_PATCH_INFO_GOT_OFFSET
, NULL
);
6209 x86_pop_reg (code
, MONO_ARCH_GOT_REG
);
6210 x86_alu_reg_imm (code
, X86_ADD
, MONO_ARCH_GOT_REG
, 0xf0f0f0f0);
6212 set_code_cursor (cfg
, code
);
6217 * mono_arch_emit_load_aotconst:
6219 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6220 * TARGET from the mscorlib GOT in full-aot code.
6221 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6225 mono_arch_emit_load_aotconst (guint8
*start
, guint8
*code
, MonoJumpInfo
**ji
, MonoJumpInfoType tramp_type
, gconstpointer target
)
6227 /* Load the mscorlib got address */
6228 x86_mov_reg_membase (code
, X86_EAX
, MONO_ARCH_GOT_REG
, sizeof (target_mgreg_t
), 4);
6229 *ji
= mono_patch_info_list_prepend (*ji
, code
- start
, tramp_type
, target
);
6230 /* arch_emit_got_access () patches this */
6231 x86_mov_reg_membase (code
, X86_EAX
, X86_EAX
, 0xf0f0f0f0, 4);
6236 /* Can't put this into mini-x86.h */
6238 mono_x86_get_signal_exception_trampoline (MonoTrampInfo
**info
, gboolean aot
);
6241 mono_arch_get_trampolines (gboolean aot
)
6243 MonoTrampInfo
*info
;
6244 GSList
*tramps
= NULL
;
6246 mono_x86_get_signal_exception_trampoline (&info
, aot
);
6248 tramps
= g_slist_append (tramps
, info
);
6253 /* Soft Debug support */
6254 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6257 * mono_arch_set_breakpoint:
6259 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6260 * The location should contain code emitted by OP_SEQ_POINT.
6263 mono_arch_set_breakpoint (MonoJitInfo
*ji
, guint8
*ip
)
6265 guint8
*code
= ip
+ OP_SEQ_POINT_BP_OFFSET
;
6267 g_assert (code
[0] == 0x90);
6268 x86_call_membase (code
, X86_ECX
, 0);
6272 * mono_arch_clear_breakpoint:
6274 * Clear the breakpoint at IP.
6277 mono_arch_clear_breakpoint (MonoJitInfo
*ji
, guint8
*ip
)
6279 guint8
*code
= ip
+ OP_SEQ_POINT_BP_OFFSET
;
6282 for (i
= 0; i
< 2; ++i
)
6287 * mono_arch_start_single_stepping:
6289 * Start single stepping.
6292 mono_arch_start_single_stepping (void)
6294 ss_trampoline
= mini_get_single_step_trampoline ();
6298 * mono_arch_stop_single_stepping:
6300 * Stop single stepping.
6303 mono_arch_stop_single_stepping (void)
6305 ss_trampoline
= NULL
;
6309 * mono_arch_is_single_step_event:
6311 * Return whenever the machine state in SIGCTX corresponds to a single
6315 mono_arch_is_single_step_event (void *info
, void *sigctx
)
6317 /* We use soft breakpoints */
6322 mono_arch_is_breakpoint_event (void *info
, void *sigctx
)
6324 /* We use soft breakpoints */
6328 #define BREAKPOINT_SIZE 2
6331 * mono_arch_skip_breakpoint:
6333 * See mini-amd64.c for docs.
6336 mono_arch_skip_breakpoint (MonoContext
*ctx
, MonoJitInfo
*ji
)
6338 g_assert_not_reached ();
6342 * mono_arch_skip_single_step:
6344 * See mini-amd64.c for docs.
6347 mono_arch_skip_single_step (MonoContext
*ctx
)
6349 g_assert_not_reached ();
6353 * mono_arch_get_seq_point_info:
6355 * See mini-amd64.c for docs.
6358 mono_arch_get_seq_point_info (MonoDomain
*domain
, guint8
*code
)
6367 mono_arch_opcode_supported (int opcode
)
6370 case OP_ATOMIC_ADD_I4
:
6371 case OP_ATOMIC_EXCHANGE_I4
:
6372 case OP_ATOMIC_CAS_I4
:
6373 case OP_ATOMIC_LOAD_I1
:
6374 case OP_ATOMIC_LOAD_I2
:
6375 case OP_ATOMIC_LOAD_I4
:
6376 case OP_ATOMIC_LOAD_U1
:
6377 case OP_ATOMIC_LOAD_U2
:
6378 case OP_ATOMIC_LOAD_U4
:
6379 case OP_ATOMIC_LOAD_R4
:
6380 case OP_ATOMIC_LOAD_R8
:
6381 case OP_ATOMIC_STORE_I1
:
6382 case OP_ATOMIC_STORE_I2
:
6383 case OP_ATOMIC_STORE_I4
:
6384 case OP_ATOMIC_STORE_U1
:
6385 case OP_ATOMIC_STORE_U2
:
6386 case OP_ATOMIC_STORE_U4
:
6387 case OP_ATOMIC_STORE_R4
:
6388 case OP_ATOMIC_STORE_R8
:
6396 mono_arch_get_call_info (MonoMemPool
*mp
, MonoMethodSignature
*sig
)
6398 return get_call_info (mp
, sig
);
6402 mono_arch_load_function (MonoJitICallId jit_icall_id
)
6404 gpointer target
= NULL
;
6405 switch (jit_icall_id
) {
6406 #undef MONO_AOT_ICALL
6407 #define MONO_AOT_ICALL(x) case MONO_JIT_ICALL_ ## x: target = (gpointer)x; break;
6408 MONO_AOT_ICALL (mono_x86_start_gsharedvt_call
)
6409 MONO_AOT_ICALL (mono_x86_throw_corlib_exception
)
6410 MONO_AOT_ICALL (mono_x86_throw_exception
)