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Propagate error in mono_unicode_to_external (#14879)
[mono-project.git] / mono / mini / mini-x86.c
blob53447aafe756e2960497d16d5d62a3b3c15f3d01
1 /**
2 * \file
3 * x86 backend for the Mono code generator
4 *
5 * Authors:
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
8 * Patrik Torstensson
9 *
10 * Copyright 2003 Ximian, Inc.
11 * Copyright 2003-2011 Novell Inc.
12 * Copyright 2011 Xamarin Inc.
13 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
14 */
15 #include "mini.h"
16 #include <string.h>
17 #include <math.h>
18 #ifdef HAVE_UNISTD_H
19 #include <unistd.h>
20 #endif
21
22 #include <mono/metadata/abi-details.h>
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internals.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-counters.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-hwcap.h>
34 #include <mono/utils/mono-threads.h>
35 #include <mono/utils/unlocked.h>
36
37 #include "mini-x86.h"
38 #include "cpu-x86.h"
39 #include "ir-emit.h"
40 #include "mini-gc.h"
41 #include "aot-runtime.h"
42 #include "mini-runtime.h"
43
44 #ifndef TARGET_WIN32
45 #ifdef MONO_XEN_OPT
46 static gboolean optimize_for_xen = TRUE;
47 #else
48 #define optimize_for_xen 0
49 #endif
50 #endif
51
52 static GENERATE_TRY_GET_CLASS_WITH_CACHE (math, "System", "Math")
53
54
55 /* The single step trampoline */
56 static gpointer ss_trampoline;
57
58 /* The breakpoint trampoline */
59 static gpointer bp_trampoline;
60
61 /* This mutex protects architecture specific caches */
62 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
63 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
64 static mono_mutex_t mini_arch_mutex;
65
66 #define ARGS_OFFSET 8
67
68 #ifdef TARGET_WIN32
69 /* Under windows, the default pinvoke calling convention is stdcall */
70 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_DEFAULT || (sig)->call_convention == MONO_CALL_THISCALL))
71 #else
72 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_THISCALL))
73 #endif
74
75 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
76
77 #define OP_SEQ_POINT_BP_OFFSET 7
78
79 const char*
80 mono_arch_regname (int reg)
81 {
82 switch (reg) {
83 case X86_EAX: return "%eax";
84 case X86_EBX: return "%ebx";
85 case X86_ECX: return "%ecx";
86 case X86_EDX: return "%edx";
87 case X86_ESP: return "%esp";
88 case X86_EBP: return "%ebp";
89 case X86_EDI: return "%edi";
90 case X86_ESI: return "%esi";
91 }
92 return "unknown";
93 }
94
95 const char*
96 mono_arch_fregname (int reg)
97 {
98 switch (reg) {
99 case 0:
100 return "%fr0";
101 case 1:
102 return "%fr1";
103 case 2:
104 return "%fr2";
105 case 3:
106 return "%fr3";
107 case 4:
108 return "%fr4";
109 case 5:
110 return "%fr5";
111 case 6:
112 return "%fr6";
113 case 7:
114 return "%fr7";
115 default:
116 return "unknown";
117 }
118 }
119
120 const char *
121 mono_arch_xregname (int reg)
122 {
123 switch (reg) {
124 case 0:
125 return "%xmm0";
126 case 1:
127 return "%xmm1";
128 case 2:
129 return "%xmm2";
130 case 3:
131 return "%xmm3";
132 case 4:
133 return "%xmm4";
134 case 5:
135 return "%xmm5";
136 case 6:
137 return "%xmm6";
138 case 7:
139 return "%xmm7";
140 default:
141 return "unknown";
142 }
143 }
144
145 void
146 mono_x86_patch (unsigned char* code, gpointer target)
147 {
148 x86_patch (code, (unsigned char*)target);
149 }
150
151 #define FLOAT_PARAM_REGS 0
152
153 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
154
155 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
156 {
157 if (!sig->pinvoke)
158 return NULL;
159
160 switch (sig->call_convention) {
161 case MONO_CALL_THISCALL:
162 return thiscall_param_regs;
163 default:
164 return NULL;
165 }
166 }
167
168 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
169 #define SMALL_STRUCTS_IN_REGS
170 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
171 #endif
172
173 static void inline
174 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
175 {
176 ainfo->offset = *stack_size;
177
178 if (!param_regs || param_regs [*gr] == X86_NREG) {
179 ainfo->storage = ArgOnStack;
180 ainfo->nslots = 1;
181 (*stack_size) += sizeof (target_mgreg_t);
182 }
183 else {
184 ainfo->storage = ArgInIReg;
185 ainfo->reg = param_regs [*gr];
186 (*gr) ++;
187 }
188 }
189
190 static void inline
191 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
192 {
193 ainfo->offset = *stack_size;
194
195 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
196
197 ainfo->storage = ArgOnStack;
198 (*stack_size) += sizeof (target_mgreg_t) * 2;
199 ainfo->nslots = 2;
200 }
201
202 static void inline
203 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
204 {
205 ainfo->offset = *stack_size;
206
207 if (*gr >= FLOAT_PARAM_REGS) {
208 ainfo->storage = ArgOnStack;
209 (*stack_size) += is_double ? 8 : 4;
210 ainfo->nslots = is_double ? 2 : 1;
211 }
212 else {
213 /* A double register */
214 if (is_double)
215 ainfo->storage = ArgInDoubleSSEReg;
216 else
217 ainfo->storage = ArgInFloatSSEReg;
218 ainfo->reg = *gr;
219 (*gr) += 1;
220 }
221 }
222
223
224 static void
225 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
226 gboolean is_return,
227 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
228 {
229 guint32 size;
230 MonoClass *klass;
231
232 klass = mono_class_from_mono_type_internal (type);
233 size = mini_type_stack_size_full (m_class_get_byval_arg (klass), NULL, sig->pinvoke);
234
235 #if defined(TARGET_WIN32)
236 /*
237 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
238 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
239 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
240 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
241 * it must be represented in call and cannot be dropped.
242 */
243 if (size == 0 && MONO_TYPE_ISSTRUCT (type) && sig->pinvoke) {
244 /* Empty structs (1 byte size) needs to be represented in a stack slot */
245 ainfo->pass_empty_struct = TRUE;
246 size = 1;
247 }
248 #endif
249
250 #ifdef SMALL_STRUCTS_IN_REGS
251 if (sig->pinvoke && is_return) {
252 MonoMarshalType *info;
253
254 info = mono_marshal_load_type_info (klass);
255 g_assert (info);
256
257 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
258
259 /* Ignore empty struct return value, if used. */
260 if (info->num_fields == 0 && ainfo->pass_empty_struct) {
261 ainfo->storage = ArgValuetypeInReg;
262 return;
263 }
264
265 /*
266 * Windows x86 ABI for returning structs of size 4 or 8 bytes (regardless of type) dictates that
267 * values are passed in EDX:EAX register pairs, https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
268 * This is different compared to for example float or double return types (not in struct) that will be returned
269 * in ST(0), https://msdn.microsoft.com/en-us/library/ha59cbfz.aspx.
270 *
271 * Apples OSX x86 ABI for returning structs of size 4 or 8 bytes uses a slightly different approach.
272 * If a struct includes only one scalar value, it will be handled with the same rules as scalar values.
273 * This means that structs with one float or double will be returned in ST(0). For more details,
274 * https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html.
275 */
276 #if !defined(TARGET_WIN32)
277
278 /* Special case structs with only a float member */
279 if (info->num_fields == 1) {
280 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
281 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
282 ainfo->storage = ArgValuetypeInReg;
283 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
284 return;
285 }
286 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
287 ainfo->storage = ArgValuetypeInReg;
288 ainfo->pair_storage [0] = ArgOnFloatFpStack;
289 return;
290 }
291 }
292 #endif
293
294 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
295 ainfo->storage = ArgValuetypeInReg;
296 ainfo->pair_storage [0] = ArgInIReg;
297 ainfo->pair_regs [0] = return_regs [0];
298 if (info->native_size > 4) {
299 ainfo->pair_storage [1] = ArgInIReg;
300 ainfo->pair_regs [1] = return_regs [1];
301 }
302 return;
303 }
304 }
305 #endif
306
307 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
308 g_assert (size <= 4);
309 ainfo->storage = ArgValuetypeInReg;
310 ainfo->reg = param_regs [*gr];
311 (*gr)++;
312 return;
313 }
314
315 ainfo->offset = *stack_size;
316 ainfo->storage = ArgOnStack;
317 *stack_size += ALIGN_TO (size, sizeof (target_mgreg_t));
318 ainfo->nslots = ALIGN_TO (size, sizeof (target_mgreg_t)) / sizeof (target_mgreg_t);
319 }
320
321 /*
322 * get_call_info:
323 *
324 * Obtain information about a call according to the calling convention.
325 * For x86 ELF, see the "System V Application Binary Interface Intel386
326 * Architecture Processor Supplment, Fourth Edition" document for more
327 * information.
328 * For x86 win32, see https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
329 */
330 static CallInfo*
331 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
332 {
333 guint32 i, gr, fr, pstart;
334 const guint32 *param_regs;
335 MonoType *ret_type;
336 int n = sig->hasthis + sig->param_count;
337 guint32 stack_size = 0;
338 gboolean is_pinvoke = sig->pinvoke;
339
340 gr = 0;
341 fr = 0;
342 cinfo->nargs = n;
343
344 param_regs = callconv_param_regs(sig);
345
346 /* return value */
347 {
348 ret_type = mini_get_underlying_type (sig->ret);
349 switch (ret_type->type) {
350 case MONO_TYPE_I1:
351 case MONO_TYPE_U1:
352 case MONO_TYPE_I2:
353 case MONO_TYPE_U2:
354 case MONO_TYPE_I4:
355 case MONO_TYPE_U4:
356 case MONO_TYPE_I:
357 case MONO_TYPE_U:
358 case MONO_TYPE_PTR:
359 case MONO_TYPE_FNPTR:
360 case MONO_TYPE_OBJECT:
361 cinfo->ret.storage = ArgInIReg;
362 cinfo->ret.reg = X86_EAX;
363 break;
364 case MONO_TYPE_U8:
365 case MONO_TYPE_I8:
366 cinfo->ret.storage = ArgInIReg;
367 cinfo->ret.reg = X86_EAX;
368 cinfo->ret.is_pair = TRUE;
369 break;
370 case MONO_TYPE_R4:
371 cinfo->ret.storage = ArgOnFloatFpStack;
372 break;
373 case MONO_TYPE_R8:
374 cinfo->ret.storage = ArgOnDoubleFpStack;
375 break;
376 case MONO_TYPE_GENERICINST:
377 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
378 cinfo->ret.storage = ArgInIReg;
379 cinfo->ret.reg = X86_EAX;
380 break;
381 }
382 if (mini_is_gsharedvt_type (ret_type)) {
383 cinfo->ret.storage = ArgOnStack;
384 cinfo->vtype_retaddr = TRUE;
385 break;
386 }
387 /* Fall through */
388 case MONO_TYPE_VALUETYPE:
389 case MONO_TYPE_TYPEDBYREF: {
390 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
391
392 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
393 if (cinfo->ret.storage == ArgOnStack) {
394 cinfo->vtype_retaddr = TRUE;
395 /* The caller passes the address where the value is stored */
396 }
397 break;
398 }
399 case MONO_TYPE_VAR:
400 case MONO_TYPE_MVAR:
401 g_assert (mini_is_gsharedvt_type (ret_type));
402 cinfo->ret.storage = ArgOnStack;
403 cinfo->vtype_retaddr = TRUE;
404 break;
405 case MONO_TYPE_VOID:
406 cinfo->ret.storage = ArgNone;
407 break;
408 default:
409 g_error ("Can't handle as return value 0x%x", ret_type->type);
410 }
411 }
412
413 pstart = 0;
414 /*
415 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
416 * the first argument, allowing 'this' to be always passed in the first arg reg.
417 * Also do this if the first argument is a reference type, since virtual calls
418 * are sometimes made using calli without sig->hasthis set, like in the delegate
419 * invoke wrappers.
420 */
421 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
422 if (sig->hasthis) {
423 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
424 } else {
425 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
426 pstart = 1;
427 }
428 cinfo->vret_arg_offset = stack_size;
429 add_general (&gr, NULL, &stack_size, &cinfo->ret);
430 cinfo->vret_arg_index = 1;
431 } else {
432 /* this */
433 if (sig->hasthis)
434 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
435
436 if (cinfo->vtype_retaddr)
437 add_general (&gr, NULL, &stack_size, &cinfo->ret);
438 }
439
440 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
441 fr = FLOAT_PARAM_REGS;
442
443 /* Emit the signature cookie just before the implicit arguments */
444 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
445 }
446
447 for (i = pstart; i < sig->param_count; ++i) {
448 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
449 MonoType *ptype;
450
451 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
452 /* We allways pass the sig cookie on the stack for simplicity */
453 /*
454 * Prevent implicit arguments + the sig cookie from being passed
455 * in registers.
456 */
457 fr = FLOAT_PARAM_REGS;
458
459 /* Emit the signature cookie just before the implicit arguments */
460 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
461 }
462
463 if (sig->params [i]->byref) {
464 add_general (&gr, param_regs, &stack_size, ainfo);
465 continue;
466 }
467 ptype = mini_get_underlying_type (sig->params [i]);
468 switch (ptype->type) {
469 case MONO_TYPE_I1:
470 case MONO_TYPE_U1:
471 add_general (&gr, param_regs, &stack_size, ainfo);
472 break;
473 case MONO_TYPE_I2:
474 case MONO_TYPE_U2:
475 add_general (&gr, param_regs, &stack_size, ainfo);
476 break;
477 case MONO_TYPE_I4:
478 case MONO_TYPE_U4:
479 add_general (&gr, param_regs, &stack_size, ainfo);
480 break;
481 case MONO_TYPE_I:
482 case MONO_TYPE_U:
483 case MONO_TYPE_PTR:
484 case MONO_TYPE_FNPTR:
485 case MONO_TYPE_OBJECT:
486 add_general (&gr, param_regs, &stack_size, ainfo);
487 break;
488 case MONO_TYPE_GENERICINST:
489 if (!mono_type_generic_inst_is_valuetype (ptype)) {
490 add_general (&gr, param_regs, &stack_size, ainfo);
491 break;
492 }
493 if (mini_is_gsharedvt_type (ptype)) {
494 /* gsharedvt arguments are passed by ref */
495 add_general (&gr, param_regs, &stack_size, ainfo);
496 g_assert (ainfo->storage == ArgOnStack);
497 ainfo->storage = ArgGSharedVt;
498 break;
499 }
500 /* Fall through */
501 case MONO_TYPE_VALUETYPE:
502 case MONO_TYPE_TYPEDBYREF:
503 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
504 break;
505 case MONO_TYPE_U8:
506 case MONO_TYPE_I8:
507 add_general_pair (&gr, param_regs, &stack_size, ainfo);
508 break;
509 case MONO_TYPE_R4:
510 add_float (&fr, &stack_size, ainfo, FALSE);
511 break;
512 case MONO_TYPE_R8:
513 add_float (&fr, &stack_size, ainfo, TRUE);
514 break;
515 case MONO_TYPE_VAR:
516 case MONO_TYPE_MVAR:
517 /* gsharedvt arguments are passed by ref */
518 g_assert (mini_is_gsharedvt_type (ptype));
519 add_general (&gr, param_regs, &stack_size, ainfo);
520 g_assert (ainfo->storage == ArgOnStack);
521 ainfo->storage = ArgGSharedVt;
522 break;
523 default:
524 g_error ("unexpected type 0x%x", ptype->type);
525 g_assert_not_reached ();
526 }
527 }
528
529 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
530 fr = FLOAT_PARAM_REGS;
531
532 /* Emit the signature cookie just before the implicit arguments */
533 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
534 }
535
536 if (cinfo->vtype_retaddr) {
537 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
538 cinfo->callee_stack_pop = 4;
539 } else if (CALLCONV_IS_STDCALL (sig)) {
540 /* Have to compensate for the stack space popped by the native callee */
541 cinfo->callee_stack_pop = stack_size;
542 }
543
544 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
545 cinfo->need_stack_align = TRUE;
546 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
547 stack_size += cinfo->stack_align_amount;
548 }
549
550 cinfo->stack_usage = stack_size;
551 cinfo->reg_usage = gr;
552 cinfo->freg_usage = fr;
553 return cinfo;
554 }
555
556 static CallInfo*
557 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
558 {
559 int n = sig->hasthis + sig->param_count;
560 CallInfo *cinfo;
561
562 if (mp)
563 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
564 else
565 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
566
567 return get_call_info_internal (cinfo, sig);
568 }
569
570 static gboolean storage_in_ireg (ArgStorage storage)
571 {
572 return (storage == ArgInIReg || storage == ArgValuetypeInReg);
573 }
574
575 /*
576 * mono_arch_get_argument_info:
577 * @csig: a method signature
578 * @param_count: the number of parameters to consider
579 * @arg_info: an array to store the result infos
580 *
581 * Gathers information on parameters such as size, alignment and
582 * padding. arg_info should be large enought to hold param_count + 1 entries.
583 *
584 * Returns the size of the argument area on the stack.
585 * This should be signal safe, since it is called from
586 * mono_arch_unwind_frame ().
587 * FIXME: The metadata calls might not be signal safe.
588 */
589 int
590 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
591 {
592 int len, k, args_size = 0;
593 int size, pad;
594 guint32 align;
595 int offset = 8;
596 CallInfo *cinfo;
597 int prev_stackarg;
598 int num_regs;
599
600 /* Avoid g_malloc as it is not signal safe */
601 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
602 cinfo = (CallInfo*)g_alloca (len);
603 memset (cinfo, 0, len);
604
605 cinfo = get_call_info_internal (cinfo, csig);
606
607 arg_info [0].offset = offset;
608
609 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
610 args_size += sizeof (target_mgreg_t);
611 offset += 4;
612 }
613
614 if (csig->hasthis && !storage_in_ireg (cinfo->args [0].storage)) {
615 args_size += sizeof (target_mgreg_t);
616 offset += 4;
617 }
618
619 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
620 /* Emitted after this */
621 args_size += sizeof (target_mgreg_t);
622 offset += 4;
623 }
624
625 arg_info [0].size = args_size;
626 prev_stackarg = 0;
627
628 for (k = 0; k < param_count; k++) {
629 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
630
631 if (storage_in_ireg (cinfo->args [csig->hasthis + k].storage)) {
632 /* not in stack, we'll give it an offset at the end */
633 arg_info [k + 1].pad = 0;
634 arg_info [k + 1].size = size;
635 } else {
636 /* ignore alignment for now */
637 align = 1;
638
639 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
640 arg_info [prev_stackarg].pad = pad;
641 args_size += size;
642 arg_info [k + 1].pad = 0;
643 arg_info [k + 1].size = size;
644 offset += pad;
645 arg_info [k + 1].offset = offset;
646 offset += size;
647 prev_stackarg = k + 1;
648 }
649
650 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
651 /* Emitted after the first arg */
652 args_size += sizeof (target_mgreg_t);
653 offset += 4;
654 }
655 }
656
657 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
658 align = MONO_ARCH_FRAME_ALIGNMENT;
659 else
660 align = 4;
661 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
662 arg_info [k].pad = pad;
663
664 /* Add offsets for any reg parameters */
665 num_regs = 0;
666 if (csig->hasthis && storage_in_ireg (cinfo->args [0].storage))
667 arg_info [0].offset = args_size + 4 * num_regs++;
668 for (k=0; k < param_count; k++) {
669 if (storage_in_ireg (cinfo->args[csig->hasthis + k].storage)) {
670 arg_info [k + 1].offset = args_size + 4 * num_regs++;
671 }
672 }
673
674 return args_size;
675 }
676
677 #ifndef DISABLE_JIT
678
679 gboolean
680 mono_arch_tailcall_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig, gboolean virtual_)
681 {
682 g_assert (caller_sig);
683 g_assert (callee_sig);
684
685 // Direct AOT calls usually go through the PLT/GOT.
686 // Unless we can determine here if is_direct_callable will return TRUE?
687 // But the PLT/GOT is addressed with nonvolatile ebx, which
688 // gets restored before the jump.
689 // See https://github.com/mono/mono/commit/f5373adc8a89d4b0d1d549fdd6d9adc3ded4b400
690 // See https://github.com/mono/mono/issues/11265
691 if (!virtual_ && cfg->compile_aot && !cfg->full_aot)
692 return FALSE;
693
694 CallInfo *caller_info = get_call_info (NULL, caller_sig);
695 CallInfo *callee_info = get_call_info (NULL, callee_sig);
696
697 /*
698 * Tailcalls with more callee stack usage than the caller cannot be supported, since
699 * the extra stack space would be left on the stack after the tailcall.
700 */
701 gboolean res = IS_SUPPORTED_TAILCALL (callee_info->stack_usage <= caller_info->stack_usage)
702 && IS_SUPPORTED_TAILCALL (caller_info->ret.storage == callee_info->ret.storage);
703 if (!res && !mono_tailcall_print_enabled ())
704 goto exit;
705
706 // Limit stack_usage to 1G.
707 res &= IS_SUPPORTED_TAILCALL (callee_info->stack_usage < (1 << 30));
708 res &= IS_SUPPORTED_TAILCALL (caller_info->stack_usage < (1 << 30));
709
710 exit:
711 g_free (caller_info);
712 g_free (callee_info);
713
714 return res;
715 }
716
717 #endif
718
719 /*
720 * Initialize the cpu to execute managed code.
721 */
722 void
723 mono_arch_cpu_init (void)
724 {
725 /* spec compliance requires running with double precision */
726 #ifndef _MSC_VER
727 guint16 fpcw;
728
729 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
730 fpcw &= ~X86_FPCW_PRECC_MASK;
731 fpcw |= X86_FPCW_PREC_DOUBLE;
732 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
733 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
734 #else
735 _control87 (_PC_53, MCW_PC);
736 #endif
737 }
738
739 /*
740 * Initialize architecture specific code.
741 */
742 void
743 mono_arch_init (void)
744 {
745 mono_os_mutex_init_recursive (&mini_arch_mutex);
746
747 if (!mono_aot_only)
748 bp_trampoline = mini_get_breakpoint_trampoline ();
749 }
750
751 /*
752 * Cleanup architecture specific code.
753 */
754 void
755 mono_arch_cleanup (void)
756 {
757 mono_os_mutex_destroy (&mini_arch_mutex);
758 }
759
760 /*
761 * This function returns the optimizations supported on this cpu.
762 */
763 guint32
764 mono_arch_cpu_optimizations (guint32 *exclude_mask)
765 {
766 guint32 opts = 0;
767
768 *exclude_mask = 0;
769
770 if (mono_hwcap_x86_has_cmov) {
771 opts |= MONO_OPT_CMOV;
772
773 if (mono_hwcap_x86_has_fcmov)
774 opts |= MONO_OPT_FCMOV;
775 else
776 *exclude_mask |= MONO_OPT_FCMOV;
777 } else {
778 *exclude_mask |= MONO_OPT_CMOV;
779 }
780
781 if (mono_hwcap_x86_has_sse2)
782 opts |= MONO_OPT_SSE2;
783 else
784 *exclude_mask |= MONO_OPT_SSE2;
785
786 #ifdef MONO_ARCH_SIMD_INTRINSICS
787 /*SIMD intrinsics require at least SSE2.*/
788 if (!mono_hwcap_x86_has_sse2)
789 *exclude_mask |= MONO_OPT_SIMD;
790 #endif
791
792 return opts;
793 }
794
795 /*
796 * This function test for all SSE functions supported.
797 *
798 * Returns a bitmask corresponding to all supported versions.
799 *
800 */
801 guint32
802 mono_arch_cpu_enumerate_simd_versions (void)
803 {
804 guint32 sse_opts = 0;
805
806 if (mono_hwcap_x86_has_sse1)
807 sse_opts |= SIMD_VERSION_SSE1;
808
809 if (mono_hwcap_x86_has_sse2)
810 sse_opts |= SIMD_VERSION_SSE2;
811
812 if (mono_hwcap_x86_has_sse3)
813 sse_opts |= SIMD_VERSION_SSE3;
814
815 if (mono_hwcap_x86_has_ssse3)
816 sse_opts |= SIMD_VERSION_SSSE3;
817
818 if (mono_hwcap_x86_has_sse41)
819 sse_opts |= SIMD_VERSION_SSE41;
820
821 if (mono_hwcap_x86_has_sse42)
822 sse_opts |= SIMD_VERSION_SSE42;
823
824 if (mono_hwcap_x86_has_sse4a)
825 sse_opts |= SIMD_VERSION_SSE4a;
826
827 return sse_opts;
828 }
829
830 /*
831 * Determine whenever the trap whose info is in SIGINFO is caused by
832 * integer overflow.
833 */
834 gboolean
835 mono_arch_is_int_overflow (void *sigctx, void *info)
836 {
837 MonoContext ctx;
838 guint8* ip;
839
840 mono_sigctx_to_monoctx (sigctx, &ctx);
841
842 ip = (guint8*)ctx.eip;
843
844 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
845 gint32 reg;
846
847 /* idiv REG */
848 switch (x86_modrm_rm (ip [1])) {
849 case X86_EAX:
850 reg = ctx.eax;
851 break;
852 case X86_ECX:
853 reg = ctx.ecx;
854 break;
855 case X86_EDX:
856 reg = ctx.edx;
857 break;
858 case X86_EBX:
859 reg = ctx.ebx;
860 break;
861 case X86_ESI:
862 reg = ctx.esi;
863 break;
864 case X86_EDI:
865 reg = ctx.edi;
866 break;
867 default:
868 g_assert_not_reached ();
869 reg = -1;
870 }
871
872 if (reg == -1)
873 return TRUE;
874 }
875
876 return FALSE;
877 }
878
879 GList *
880 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
881 {
882 GList *vars = NULL;
883 int i;
884
885 for (i = 0; i < cfg->num_varinfo; i++) {
886 MonoInst *ins = cfg->varinfo [i];
887 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
888
889 /* unused vars */
890 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
891 continue;
892
893 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
894 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
895 continue;
896
897 /* we dont allocate I1 to registers because there is no simply way to sign extend
898 * 8bit quantities in caller saved registers on x86 */
899 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
900 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
901 g_assert (i == vmv->idx);
902 vars = g_list_prepend (vars, vmv);
903 }
904 }
905
906 vars = mono_varlist_sort (cfg, vars, 0);
907
908 return vars;
909 }
910
911 GList *
912 mono_arch_get_global_int_regs (MonoCompile *cfg)
913 {
914 GList *regs = NULL;
915
916 /* we can use 3 registers for global allocation */
917 regs = g_list_prepend (regs, (gpointer)X86_EBX);
918 regs = g_list_prepend (regs, (gpointer)X86_ESI);
919 regs = g_list_prepend (regs, (gpointer)X86_EDI);
920
921 return regs;
922 }
923
924 /*
925 * mono_arch_regalloc_cost:
926 *
927 * Return the cost, in number of memory references, of the action of
928 * allocating the variable VMV into a register during global register
929 * allocation.
930 */
931 guint32
932 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
933 {
934 MonoInst *ins = cfg->varinfo [vmv->idx];
935
936 if (cfg->method->save_lmf)
937 /* The register is already saved */
938 return (ins->opcode == OP_ARG) ? 1 : 0;
939 else
940 /* push+pop+possible load if it is an argument */
941 return (ins->opcode == OP_ARG) ? 3 : 2;
942 }
943
944 static void
945 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
946 {
947 static int inited = FALSE;
948 static int count = 0;
949
950 if (cfg->arch.need_stack_frame_inited) {
951 g_assert (cfg->arch.need_stack_frame == flag);
952 return;
953 }
954
955 cfg->arch.need_stack_frame = flag;
956 cfg->arch.need_stack_frame_inited = TRUE;
957
958 if (flag)
959 return;
960
961 if (!inited) {
962 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
963 inited = TRUE;
964 }
965 ++count;
966
967 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
968 }
969
970 static gboolean
971 needs_stack_frame (MonoCompile *cfg)
972 {
973 MonoMethodSignature *sig;
974 MonoMethodHeader *header;
975 gboolean result = FALSE;
976
977 #if defined (__APPLE__)
978 /*OSX requires stack frame code to have the correct alignment. */
979 return TRUE;
980 #endif
981
982 if (cfg->arch.need_stack_frame_inited)
983 return cfg->arch.need_stack_frame;
984
985 header = cfg->header;
986 sig = mono_method_signature_internal (cfg->method);
987
988 if (cfg->disable_omit_fp)
989 result = TRUE;
990 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
991 result = TRUE;
992 else if (cfg->method->save_lmf)
993 result = TRUE;
994 else if (cfg->stack_offset)
995 result = TRUE;
996 else if (cfg->param_area)
997 result = TRUE;
998 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAILCALL))
999 result = TRUE;
1000 else if (header->num_clauses)
1001 result = TRUE;
1002 else if (sig->param_count + sig->hasthis)
1003 result = TRUE;
1004 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1005 result = TRUE;
1006
1007 set_needs_stack_frame (cfg, result);
1008
1009 return cfg->arch.need_stack_frame;
1010 }
1011
1012 /*
1013 * Set var information according to the calling convention. X86 version.
1014 * The locals var stuff should most likely be split in another method.
1015 */
1016 void
1017 mono_arch_allocate_vars (MonoCompile *cfg)
1018 {
1019 MonoMethodSignature *sig;
1020 MonoMethodHeader *header;
1021 MonoInst *inst;
1022 guint32 locals_stack_size, locals_stack_align;
1023 int i, offset;
1024 gint32 *offsets;
1025 CallInfo *cinfo;
1026
1027 header = cfg->header;
1028 sig = mono_method_signature_internal (cfg->method);
1029
1030 if (!cfg->arch.cinfo)
1031 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1032 cinfo = cfg->arch.cinfo;
1033
1034 cfg->frame_reg = X86_EBP;
1035 offset = 0;
1036
1037 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1038 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1039 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1040 }
1041
1042 /* Reserve space to save LMF and caller saved registers */
1043
1044 if (cfg->method->save_lmf) {
1045 /* The LMF var is allocated normally */
1046 } else {
1047 if (cfg->used_int_regs & (1 << X86_EBX)) {
1048 offset += 4;
1049 }
1050
1051 if (cfg->used_int_regs & (1 << X86_EDI)) {
1052 offset += 4;
1053 }
1054
1055 if (cfg->used_int_regs & (1 << X86_ESI)) {
1056 offset += 4;
1057 }
1058 }
1059
1060 switch (cinfo->ret.storage) {
1061 case ArgValuetypeInReg:
1062 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1063 offset += 8;
1064 cfg->ret->opcode = OP_REGOFFSET;
1065 cfg->ret->inst_basereg = X86_EBP;
1066 cfg->ret->inst_offset = - offset;
1067 break;
1068 default:
1069 break;
1070 }
1071
1072 /* Allocate a local for any register arguments that need them. */
1073 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1074 ArgInfo *ainfo = &cinfo->args [i];
1075 inst = cfg->args [i];
1076 if (inst->opcode != OP_REGVAR && storage_in_ireg (ainfo->storage)) {
1077 offset += 4;
1078 cfg->args[i]->opcode = OP_REGOFFSET;
1079 cfg->args[i]->inst_basereg = X86_EBP;
1080 cfg->args[i]->inst_offset = - offset;
1081 }
1082 }
1083
1084 /* Allocate locals */
1085 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1086 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1087 char *mname = mono_method_full_name (cfg->method, TRUE);
1088 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1089 g_free (mname);
1090 return;
1091 }
1092 if (locals_stack_align) {
1093 int prev_offset = offset;
1094
1095 offset += (locals_stack_align - 1);
1096 offset &= ~(locals_stack_align - 1);
1097
1098 while (prev_offset < offset) {
1099 prev_offset += 4;
1100 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1101 }
1102 }
1103 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1104 cfg->locals_max_stack_offset = - offset;
1105 /*
1106 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1107 * have locals larger than 8 bytes we need to make sure that
1108 * they have the appropriate offset.
1109 */
1110 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8) {
1111 int extra_size = MONO_ARCH_FRAME_ALIGNMENT - sizeof (target_mgreg_t) * 2;
1112 offset += extra_size;
1113 locals_stack_size += extra_size;
1114 }
1115 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1116 if (offsets [i] != -1) {
1117 MonoInst *inst = cfg->varinfo [i];
1118 inst->opcode = OP_REGOFFSET;
1119 inst->inst_basereg = X86_EBP;
1120 inst->inst_offset = - (offset + offsets [i]);
1121 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1122 }
1123 }
1124 offset += locals_stack_size;
1125
1126
1127 /*
1128 * Allocate arguments+return value
1129 */
1130
1131 switch (cinfo->ret.storage) {
1132 case ArgOnStack:
1133 if (cfg->vret_addr) {
1134 /*
1135 * In the new IR, the cfg->vret_addr variable represents the
1136 * vtype return value.
1137 */
1138 cfg->vret_addr->opcode = OP_REGOFFSET;
1139 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1140 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1141 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1142 printf ("vret_addr =");
1143 mono_print_ins (cfg->vret_addr);
1144 }
1145 } else {
1146 cfg->ret->opcode = OP_REGOFFSET;
1147 cfg->ret->inst_basereg = X86_EBP;
1148 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1149 }
1150 break;
1151 case ArgValuetypeInReg:
1152 break;
1153 case ArgInIReg:
1154 cfg->ret->opcode = OP_REGVAR;
1155 cfg->ret->inst_c0 = cinfo->ret.reg;
1156 cfg->ret->dreg = cinfo->ret.reg;
1157 break;
1158 case ArgNone:
1159 case ArgOnFloatFpStack:
1160 case ArgOnDoubleFpStack:
1161 break;
1162 default:
1163 g_assert_not_reached ();
1164 }
1165
1166 if (sig->call_convention == MONO_CALL_VARARG) {
1167 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1168 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1169 }
1170
1171 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1172 ArgInfo *ainfo = &cinfo->args [i];
1173 inst = cfg->args [i];
1174 if (inst->opcode != OP_REGVAR) {
1175 if (storage_in_ireg (ainfo->storage)) {
1176 /* We already allocated locals for register arguments. */
1177 } else {
1178 inst->opcode = OP_REGOFFSET;
1179 inst->inst_basereg = X86_EBP;
1180 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1181 }
1182 }
1183 }
1184
1185 cfg->stack_offset = offset;
1186 }
1187
1188 void
1189 mono_arch_create_vars (MonoCompile *cfg)
1190 {
1191 MonoType *sig_ret;
1192 MonoMethodSignature *sig;
1193 CallInfo *cinfo;
1194
1195 sig = mono_method_signature_internal (cfg->method);
1196
1197 if (!cfg->arch.cinfo)
1198 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1199 cinfo = cfg->arch.cinfo;
1200
1201 sig_ret = mini_get_underlying_type (sig->ret);
1202
1203 if (cinfo->ret.storage == ArgValuetypeInReg)
1204 cfg->ret_var_is_local = TRUE;
1205 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1206 cfg->vret_addr = mono_compile_create_var (cfg, mono_get_int_type (), OP_ARG);
1207 }
1208
1209 if (cfg->gen_sdb_seq_points) {
1210 MonoInst *ins;
1211
1212 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
1213 ins->flags |= MONO_INST_VOLATILE;
1214 cfg->arch.ss_tramp_var = ins;
1215
1216 ins = mono_compile_create_var (cfg, mono_get_int_type (), OP_LOCAL);
1217 ins->flags |= MONO_INST_VOLATILE;
1218 cfg->arch.bp_tramp_var = ins;
1219 }
1220
1221 if (cfg->method->save_lmf) {
1222 cfg->create_lmf_var = TRUE;
1223 cfg->lmf_ir = TRUE;
1224 }
1225
1226 cfg->arch_eh_jit_info = 1;
1227 }
1228
1229 /*
1230 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1231 * so we try to do it just once when we have multiple fp arguments in a row.
1232 * We don't use this mechanism generally because for int arguments the generated code
1233 * is slightly bigger and new generation cpus optimize away the dependency chains
1234 * created by push instructions on the esp value.
1235 * fp_arg_setup is the first argument in the execution sequence where the esp register
1236 * is modified.
1237 */
1238 static G_GNUC_UNUSED int
1239 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1240 {
1241 int fp_space = 0;
1242 MonoType *t;
1243
1244 for (; start_arg < sig->param_count; ++start_arg) {
1245 t = mini_get_underlying_type (sig->params [start_arg]);
1246 if (!t->byref && t->type == MONO_TYPE_R8) {
1247 fp_space += sizeof (double);
1248 *fp_arg_setup = start_arg;
1249 } else {
1250 break;
1251 }
1252 }
1253 return fp_space;
1254 }
1255
1256 static void
1257 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1258 {
1259 MonoMethodSignature *tmp_sig;
1260 int sig_reg;
1261
1262 /*
1263 * mono_ArgIterator_Setup assumes the signature cookie is
1264 * passed first and all the arguments which were before it are
1265 * passed on the stack after the signature. So compensate by
1266 * passing a different signature.
1267 */
1268 tmp_sig = mono_metadata_signature_dup (call->signature);
1269 tmp_sig->param_count -= call->signature->sentinelpos;
1270 tmp_sig->sentinelpos = 0;
1271 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1272
1273 if (cfg->compile_aot) {
1274 sig_reg = mono_alloc_ireg (cfg);
1275 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1276 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1277 } else {
1278 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1279 }
1280 }
1281
1282 #ifdef ENABLE_LLVM
1283 LLVMCallInfo*
1284 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1285 {
1286 int i, n;
1287 CallInfo *cinfo;
1288 ArgInfo *ainfo;
1289 LLVMCallInfo *linfo;
1290 MonoType *t, *sig_ret;
1291
1292 n = sig->param_count + sig->hasthis;
1293
1294 cinfo = get_call_info (cfg->mempool, sig);
1295 sig_ret = sig->ret;
1296
1297 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1298
1299 /*
1300 * LLVM always uses the native ABI while we use our own ABI, the
1301 * only difference is the handling of vtypes:
1302 * - we only pass/receive them in registers in some cases, and only
1303 * in 1 or 2 integer registers.
1304 */
1305 if (cinfo->ret.storage == ArgValuetypeInReg) {
1306 if (sig->pinvoke) {
1307 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1308 cfg->disable_llvm = TRUE;
1309 return linfo;
1310 }
1311
1312 cfg->exception_message = g_strdup ("vtype ret in call");
1313 cfg->disable_llvm = TRUE;
1314 /*
1315 linfo->ret.storage = LLVMArgVtypeInReg;
1316 for (j = 0; j < 2; ++j)
1317 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1318 */
1319 }
1320
1321 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1322 /* Vtype returned using a hidden argument */
1323 linfo->ret.storage = LLVMArgVtypeRetAddr;
1324 linfo->vret_arg_index = cinfo->vret_arg_index;
1325 }
1326
1327 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1328 // FIXME:
1329 cfg->exception_message = g_strdup ("vtype ret in call");
1330 cfg->disable_llvm = TRUE;
1331 }
1332
1333 for (i = 0; i < n; ++i) {
1334 ainfo = cinfo->args + i;
1335
1336 if (i >= sig->hasthis)
1337 t = sig->params [i - sig->hasthis];
1338 else
1339 t = mono_get_int_type ();
1340
1341 linfo->args [i].storage = LLVMArgNone;
1342
1343 switch (ainfo->storage) {
1344 case ArgInIReg:
1345 linfo->args [i].storage = LLVMArgNormal;
1346 break;
1347 case ArgInDoubleSSEReg:
1348 case ArgInFloatSSEReg:
1349 linfo->args [i].storage = LLVMArgNormal;
1350 break;
1351 case ArgOnStack:
1352 if (mini_type_is_vtype (t)) {
1353 if (mono_class_value_size (mono_class_from_mono_type_internal (t), NULL) == 0)
1354 /* LLVM seems to allocate argument space for empty structures too */
1355 linfo->args [i].storage = LLVMArgNone;
1356 else
1357 linfo->args [i].storage = LLVMArgVtypeByVal;
1358 } else {
1359 linfo->args [i].storage = LLVMArgNormal;
1360 }
1361 break;
1362 case ArgValuetypeInReg:
1363 if (sig->pinvoke) {
1364 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1365 cfg->disable_llvm = TRUE;
1366 return linfo;
1367 }
1368
1369 cfg->exception_message = g_strdup ("vtype arg");
1370 cfg->disable_llvm = TRUE;
1371 /*
1372 linfo->args [i].storage = LLVMArgVtypeInReg;
1373 for (j = 0; j < 2; ++j)
1374 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1375 */
1376 break;
1377 case ArgGSharedVt:
1378 linfo->args [i].storage = LLVMArgGSharedVt;
1379 break;
1380 default:
1381 cfg->exception_message = g_strdup ("ainfo->storage");
1382 cfg->disable_llvm = TRUE;
1383 break;
1384 }
1385 }
1386
1387 return linfo;
1388 }
1389 #endif
1390
1391 static void
1392 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1393 {
1394 if (cfg->compute_gc_maps) {
1395 MonoInst *def;
1396
1397 /* Needs checking if the feature will be enabled again */
1398 g_assert_not_reached ();
1399
1400 /* On x86, the offsets are from the sp value before the start of the call sequence */
1401 if (t == NULL)
1402 t = mono_get_int_type ();
1403 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1404 }
1405 }
1406
1407 void
1408 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1409 {
1410 MonoType *sig_ret;
1411 MonoInst *arg, *in;
1412 MonoMethodSignature *sig;
1413 int i, j, n;
1414 CallInfo *cinfo;
1415 int sentinelpos = 0, sp_offset = 0;
1416
1417 sig = call->signature;
1418 n = sig->param_count + sig->hasthis;
1419 sig_ret = mini_get_underlying_type (sig->ret);
1420
1421 cinfo = get_call_info (cfg->mempool, sig);
1422 call->call_info = cinfo;
1423
1424 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1425 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1426
1427 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1428 if (cinfo->ret.storage == ArgValuetypeInReg && cinfo->ret.pair_storage[0] != ArgNone ) {
1429 /*
1430 * Tell the JIT to use a more efficient calling convention: call using
1431 * OP_CALL, compute the result location after the call, and save the
1432 * result there.
1433 */
1434 call->vret_in_reg = TRUE;
1435 #if defined (__APPLE__)
1436 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1437 call->vret_in_reg_fp = TRUE;
1438 #endif
1439 if (call->vret_var)
1440 NULLIFY_INS (call->vret_var);
1441 }
1442 }
1443
1444 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1445
1446 /* Handle the case where there are no implicit arguments */
1447 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1448 emit_sig_cookie (cfg, call, cinfo);
1449 sp_offset = cinfo->sig_cookie.offset;
1450 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1451 }
1452
1453 /* Arguments are pushed in the reverse order */
1454 for (i = n - 1; i >= 0; i --) {
1455 ArgInfo *ainfo = cinfo->args + i;
1456 MonoType *orig_type, *t;
1457 int argsize;
1458
1459 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1460 MonoInst *vtarg;
1461
1462 /* Push the vret arg before the first argument */
1463 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1464 vtarg->type = STACK_MP;
1465 vtarg->inst_destbasereg = X86_ESP;
1466 vtarg->sreg1 = call->vret_var->dreg;
1467 vtarg->inst_offset = cinfo->ret.offset;
1468 MONO_ADD_INS (cfg->cbb, vtarg);
1469 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1470 }
1471
1472 if (i >= sig->hasthis)
1473 t = sig->params [i - sig->hasthis];
1474 else
1475 t = mono_get_int_type ();
1476 orig_type = t;
1477 t = mini_get_underlying_type (t);
1478
1479 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1480
1481 in = call->args [i];
1482 arg->cil_code = in->cil_code;
1483 arg->sreg1 = in->dreg;
1484 arg->type = in->type;
1485
1486 g_assert (in->dreg != -1);
1487
1488 if (ainfo->storage == ArgGSharedVt) {
1489 arg->opcode = OP_OUTARG_VT;
1490 arg->sreg1 = in->dreg;
1491 arg->klass = in->klass;
1492 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1493 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1494 sp_offset += 4;
1495 MONO_ADD_INS (cfg->cbb, arg);
1496 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1497 guint32 align;
1498 guint32 size;
1499
1500 g_assert (in->klass);
1501
1502 if (t->type == MONO_TYPE_TYPEDBYREF) {
1503 size = MONO_ABI_SIZEOF (MonoTypedRef);
1504 align = sizeof (target_mgreg_t);
1505 }
1506 else {
1507 size = mini_type_stack_size_full (m_class_get_byval_arg (in->klass), &align, sig->pinvoke);
1508 }
1509
1510 if (size > 0 || ainfo->pass_empty_struct) {
1511 arg->opcode = OP_OUTARG_VT;
1512 arg->sreg1 = in->dreg;
1513 arg->klass = in->klass;
1514 arg->backend.size = size;
1515 arg->inst_p0 = call;
1516 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1517 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1518
1519 MONO_ADD_INS (cfg->cbb, arg);
1520 if (ainfo->storage != ArgValuetypeInReg) {
1521 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1522 }
1523 }
1524 } else {
1525 switch (ainfo->storage) {
1526 case ArgOnStack:
1527 if (!t->byref) {
1528 if (t->type == MONO_TYPE_R4) {
1529 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1530 argsize = 4;
1531 } else if (t->type == MONO_TYPE_R8) {
1532 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1533 argsize = 8;
1534 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1535 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1536 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1537 argsize = 4;
1538 } else {
1539 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1540 argsize = 4;
1541 }
1542 } else {
1543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1544 argsize = 4;
1545 }
1546 break;
1547 case ArgInIReg:
1548 arg->opcode = OP_MOVE;
1549 arg->dreg = ainfo->reg;
1550 MONO_ADD_INS (cfg->cbb, arg);
1551 argsize = 0;
1552 break;
1553 default:
1554 g_assert_not_reached ();
1555 }
1556
1557 if (cfg->compute_gc_maps) {
1558 if (argsize == 4) {
1559 /* FIXME: The == STACK_OBJ check might be fragile ? */
1560 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1561 /* this */
1562 if (call->need_unbox_trampoline)
1563 /* The unbox trampoline transforms this into a managed pointer */
1564 emit_gc_param_slot_def (cfg, ainfo->offset, m_class_get_this_arg (mono_defaults.int_class));
1565 else
1566 emit_gc_param_slot_def (cfg, ainfo->offset, mono_get_object_type ());
1567 } else {
1568 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1569 }
1570 } else {
1571 /* i8/r8 */
1572 for (j = 0; j < argsize; j += 4)
1573 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1574 }
1575 }
1576 }
1577
1578 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1579 /* Emit the signature cookie just before the implicit arguments */
1580 emit_sig_cookie (cfg, call, cinfo);
1581 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1582 }
1583 }
1584
1585 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1586 MonoInst *vtarg;
1587
1588 if (cinfo->ret.storage == ArgValuetypeInReg) {
1589 /* Already done */
1590 }
1591 else if (cinfo->ret.storage == ArgInIReg) {
1592 NOT_IMPLEMENTED;
1593 /* The return address is passed in a register */
1594 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1595 vtarg->sreg1 = call->inst.dreg;
1596 vtarg->dreg = mono_alloc_ireg (cfg);
1597 MONO_ADD_INS (cfg->cbb, vtarg);
1598
1599 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1600 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1601 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1602 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1603 }
1604 }
1605
1606 call->stack_usage = cinfo->stack_usage;
1607 call->stack_align_amount = cinfo->stack_align_amount;
1608 }
1609
1610 void
1611 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1612 {
1613 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1614 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1615 int size = ins->backend.size;
1616
1617 if (ainfo->storage == ArgValuetypeInReg) {
1618 int dreg = mono_alloc_ireg (cfg);
1619 switch (size) {
1620 case 1:
1621 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1622 break;
1623 case 2:
1624 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1625 break;
1626 case 4:
1627 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1628 break;
1629 case 3: /* FIXME */
1630 default:
1631 g_assert_not_reached ();
1632 }
1633 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1634 }
1635 else {
1636 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1637 /* Pass by addr */
1638 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1639 } else if (size <= 4) {
1640 int dreg = mono_alloc_ireg (cfg);
1641 if (ainfo->pass_empty_struct) {
1642 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
1643 MONO_EMIT_NEW_ICONST (cfg, dreg, 0);
1644 } else {
1645 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1646 }
1647 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1648 } else if (size <= 20) {
1649 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1650 } else {
1651 // FIXME: Code growth
1652 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1653 }
1654 }
1655 }
1656
1657 void
1658 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1659 {
1660 MonoType *ret = mini_get_underlying_type (mono_method_signature_internal (method)->ret);
1661
1662 if (!ret->byref) {
1663 if (ret->type == MONO_TYPE_R4) {
1664 if (COMPILE_LLVM (cfg))
1665 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1666 /* Nothing to do */
1667 return;
1668 } else if (ret->type == MONO_TYPE_R8) {
1669 if (COMPILE_LLVM (cfg))
1670 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1671 /* Nothing to do */
1672 return;
1673 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1674 if (COMPILE_LLVM (cfg))
1675 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1676 else {
1677 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1678 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1679 }
1680 return;
1681 }
1682 }
1683
1684 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1685 }
1686
1687 #define EMIT_COND_BRANCH(ins,cond,sign) \
1688 if (ins->inst_true_bb->native_offset) { \
1689 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1690 } else { \
1691 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1692 if ((cfg->opt & MONO_OPT_BRANCH) && \
1693 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1694 x86_branch8 (code, cond, 0, sign); \
1695 else \
1696 x86_branch32 (code, cond, 0, sign); \
1697 }
1698
1699 /*
1700 * Emit an exception if condition is fail and
1701 * if possible do a directly branch to target
1702 */
1703 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1704 do { \
1705 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1706 if (tins == NULL) { \
1707 mono_add_patch_info (cfg, code - cfg->native_code, \
1708 MONO_PATCH_INFO_EXC, exc_name); \
1709 x86_branch32 (code, cond, 0, signed); \
1710 } else { \
1711 EMIT_COND_BRANCH (tins, cond, signed); \
1712 } \
1713 } while (0);
1714
1715 #define EMIT_FPCOMPARE(code) do { \
1716 x86_fcompp (code); \
1717 x86_fnstsw (code); \
1718 } while (0);
1719
1720 static guint8*
1721 x86_align_and_patch (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1722 {
1723 gboolean needs_paddings = TRUE;
1724 guint32 pad_size;
1725 MonoJumpInfo *jinfo = NULL;
1726
1727 if (cfg->abs_patches) {
1728 jinfo = (MonoJumpInfo*)g_hash_table_lookup (cfg->abs_patches, data);
1729 if (jinfo && (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR
1730 || jinfo->type == MONO_PATCH_INFO_TRAMPOLINE_FUNC_ADDR
1731 || jinfo->type == MONO_PATCH_INFO_SPECIFIC_TRAMPOLINE_LAZY_FETCH_ADDR))
1732 needs_paddings = FALSE;
1733 }
1734
1735 if (cfg->compile_aot)
1736 needs_paddings = FALSE;
1737 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1738 This is required for code patching to be safe on SMP machines.
1739 */
1740 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1741 if (needs_paddings && pad_size)
1742 x86_padding (code, 4 - pad_size);
1743
1744 mono_add_patch_info (cfg, code - cfg->native_code, (MonoJumpInfoType)patch_type, data);
1745
1746 return code;
1747 }
1748
1749 static guint8*
1750 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1751 {
1752 code = x86_align_and_patch (cfg, code, patch_type, data);
1753
1754 x86_call_code (code, 0);
1755
1756 return code;
1757 }
1758
1759 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1760
1761 /*
1762 * mono_peephole_pass_1:
1763 *
1764 * Perform peephole opts which should/can be performed before local regalloc
1765 */
1766 void
1767 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1768 {
1769 MonoInst *ins, *n;
1770
1771 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1772 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1773
1774 switch (ins->opcode) {
1775 case OP_IADD_IMM:
1776 case OP_ADD_IMM:
1777 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1778 /*
1779 * X86_LEA is like ADD, but doesn't have the
1780 * sreg1==dreg restriction.
1781 */
1782 ins->opcode = OP_X86_LEA_MEMBASE;
1783 ins->inst_basereg = ins->sreg1;
1784 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1785 ins->opcode = OP_X86_INC_REG;
1786 break;
1787 case OP_SUB_IMM:
1788 case OP_ISUB_IMM:
1789 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1790 ins->opcode = OP_X86_LEA_MEMBASE;
1791 ins->inst_basereg = ins->sreg1;
1792 ins->inst_imm = -ins->inst_imm;
1793 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1794 ins->opcode = OP_X86_DEC_REG;
1795 break;
1796 case OP_COMPARE_IMM:
1797 case OP_ICOMPARE_IMM:
1798 /* OP_COMPARE_IMM (reg, 0)
1799 * -->
1800 * OP_X86_TEST_NULL (reg)
1801 */
1802 if (!ins->inst_imm)
1803 ins->opcode = OP_X86_TEST_NULL;
1804 break;
1805 case OP_X86_COMPARE_MEMBASE_IMM:
1806 /*
1807 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1808 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1809 * -->
1810 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1811 * OP_COMPARE_IMM reg, imm
1812 *
1813 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1814 */
1815 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1816 ins->inst_basereg == last_ins->inst_destbasereg &&
1817 ins->inst_offset == last_ins->inst_offset) {
1818 ins->opcode = OP_COMPARE_IMM;
1819 ins->sreg1 = last_ins->sreg1;
1820
1821 /* check if we can remove cmp reg,0 with test null */
1822 if (!ins->inst_imm)
1823 ins->opcode = OP_X86_TEST_NULL;
1824 }
1825
1826 break;
1827 case OP_X86_PUSH_MEMBASE:
1828 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1829 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1830 ins->inst_basereg == last_ins->inst_destbasereg &&
1831 ins->inst_offset == last_ins->inst_offset) {
1832 ins->opcode = OP_X86_PUSH;
1833 ins->sreg1 = last_ins->sreg1;
1834 }
1835 break;
1836 }
1837
1838 mono_peephole_ins (bb, ins);
1839 }
1840 }
1841
1842 void
1843 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1844 {
1845 MonoInst *ins, *n;
1846
1847 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1848 switch (ins->opcode) {
1849 case OP_ICONST:
1850 /* reg = 0 -> XOR (reg, reg) */
1851 /* XOR sets cflags on x86, so we cant do it always */
1852 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1853 MonoInst *ins2;
1854
1855 ins->opcode = OP_IXOR;
1856 ins->sreg1 = ins->dreg;
1857 ins->sreg2 = ins->dreg;
1858
1859 /*
1860 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1861 * since it takes 3 bytes instead of 7.
1862 */
1863 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
1864 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1865 ins2->opcode = OP_STORE_MEMBASE_REG;
1866 ins2->sreg1 = ins->dreg;
1867 }
1868 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1869 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1870 ins2->sreg1 = ins->dreg;
1871 }
1872 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1873 /* Continue iteration */
1874 }
1875 else
1876 break;
1877 }
1878 }
1879 break;
1880 case OP_IADD_IMM:
1881 case OP_ADD_IMM:
1882 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1883 ins->opcode = OP_X86_INC_REG;
1884 break;
1885 case OP_ISUB_IMM:
1886 case OP_SUB_IMM:
1887 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1888 ins->opcode = OP_X86_DEC_REG;
1889 break;
1890 }
1891
1892 mono_peephole_ins (bb, ins);
1893 }
1894 }
1895
1896 #define NEW_INS(cfg,ins,dest,op) do { \
1897 MONO_INST_NEW ((cfg), (dest), (op)); \
1898 (dest)->cil_code = (ins)->cil_code; \
1899 mono_bblock_insert_before_ins (bb, ins, (dest)); \
1900 } while (0)
1901
1902 /*
1903 * mono_arch_lowering_pass:
1904 *
1905 * Converts complex opcodes into simpler ones so that each IR instruction
1906 * corresponds to one machine instruction.
1907 */
1908 void
1909 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1910 {
1911 MonoInst *ins, *next;
1912
1913 /*
1914 * FIXME: Need to add more instructions, but the current machine
1915 * description can't model some parts of the composite instructions like
1916 * cdq.
1917 */
1918 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1919 switch (ins->opcode) {
1920 case OP_IREM_IMM:
1921 case OP_IDIV_IMM:
1922 case OP_IDIV_UN_IMM:
1923 case OP_IREM_UN_IMM:
1924 /*
1925 * Keep the cases where we could generated optimized code, otherwise convert
1926 * to the non-imm variant.
1927 */
1928 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1929 break;
1930 mono_decompose_op_imm (cfg, bb, ins);
1931 break;
1932 #ifdef MONO_ARCH_SIMD_INTRINSICS
1933 case OP_EXPAND_I1: {
1934 MonoInst *temp;
1935 int temp_reg1 = mono_alloc_ireg (cfg);
1936 int temp_reg2 = mono_alloc_ireg (cfg);
1937 int original_reg = ins->sreg1;
1938
1939 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
1940 temp->sreg1 = original_reg;
1941 temp->dreg = temp_reg1;
1942
1943 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
1944 temp->sreg1 = temp_reg1;
1945 temp->dreg = temp_reg2;
1946 temp->inst_imm = 8;
1947
1948 NEW_INS (cfg, ins, temp, OP_IOR);
1949 temp->sreg1 = temp->dreg = temp_reg2;
1950 temp->sreg2 = temp_reg1;
1951
1952 ins->opcode = OP_EXPAND_I2;
1953 ins->sreg1 = temp_reg2;
1954 }
1955 break;
1956 #endif
1957 default:
1958 break;
1959 }
1960 }
1961
1962 bb->max_vreg = cfg->next_vreg;
1963 }
1964
1965 static const int
1966 branch_cc_table [] = {
1967 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1968 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1969 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1970 };
1971
1972 /* Maps CMP_... constants to X86_CC_... constants */
1973 static const int
1974 cc_table [] = {
1975 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1976 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1977 };
1978
1979 static const int
1980 cc_signed_table [] = {
1981 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1982 FALSE, FALSE, FALSE, FALSE
1983 };
1984
1985 static unsigned char*
1986 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1987 {
1988 #define XMM_TEMP_REG 0
1989 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
1990 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
1991 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
1992 /* optimize by assigning a local var for this use so we avoid
1993 * the stack manipulations */
1994 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1995 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1996 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
1997 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
1998 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1999 if (size == 1)
2000 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2001 else if (size == 2)
2002 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2003 return code;
2004 }
2005 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2006 x86_fnstcw_membase(code, X86_ESP, 0);
2007 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2008 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2009 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2010 x86_fldcw_membase (code, X86_ESP, 2);
2011 if (size == 8) {
2012 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2013 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2014 x86_pop_reg (code, dreg);
2015 /* FIXME: need the high register
2016 * x86_pop_reg (code, dreg_high);
2017 */
2018 } else {
2019 x86_push_reg (code, X86_EAX); // SP = SP - 4
2020 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2021 x86_pop_reg (code, dreg);
2022 }
2023 x86_fldcw_membase (code, X86_ESP, 0);
2024 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2025
2026 if (size == 1)
2027 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2028 else if (size == 2)
2029 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2030 return code;
2031 }
2032
2033 static unsigned char*
2034 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2035 {
2036 int sreg = tree->sreg1;
2037 int need_touch = FALSE;
2038
2039 #if defined (TARGET_WIN32) || defined (MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2040 need_touch = TRUE;
2041 #endif
2042
2043 if (need_touch) {
2044 guint8* br[5];
2045
2046 /*
2047 * Under Windows:
2048 * If requested stack size is larger than one page,
2049 * perform stack-touch operation
2050 */
2051 /*
2052 * Generate stack probe code.
2053 * Under Windows, it is necessary to allocate one page at a time,
2054 * "touching" stack after each successful sub-allocation. This is
2055 * because of the way stack growth is implemented - there is a
2056 * guard page before the lowest stack page that is currently commited.
2057 * Stack normally grows sequentially so OS traps access to the
2058 * guard page and commits more pages when needed.
2059 */
2060 x86_test_reg_imm (code, sreg, ~0xFFF);
2061 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2062
2063 br[2] = code; /* loop */
2064 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2065 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2066
2067 /*
2068 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2069 * that follows only initializes the last part of the area.
2070 */
2071 /* Same as the init code below with size==0x1000 */
2072 if (tree->flags & MONO_INST_INIT) {
2073 x86_push_reg (code, X86_EAX);
2074 x86_push_reg (code, X86_ECX);
2075 x86_push_reg (code, X86_EDI);
2076 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2077 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2078 if (cfg->param_area)
2079 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2080 else
2081 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2082 x86_cld (code);
2083 x86_prefix (code, X86_REP_PREFIX);
2084 x86_stosl (code);
2085 x86_pop_reg (code, X86_EDI);
2086 x86_pop_reg (code, X86_ECX);
2087 x86_pop_reg (code, X86_EAX);
2088 }
2089
2090 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2091 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2092 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2093 x86_patch (br[3], br[2]);
2094 x86_test_reg_reg (code, sreg, sreg);
2095 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2096 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2097
2098 br[1] = code; x86_jump8 (code, 0);
2099
2100 x86_patch (br[0], code);
2101 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2102 x86_patch (br[1], code);
2103 x86_patch (br[4], code);
2104 }
2105 else
2106 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2107
2108 if (tree->flags & MONO_INST_INIT) {
2109 int offset = 0;
2110 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2111 x86_push_reg (code, X86_EAX);
2112 offset += 4;
2113 }
2114 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2115 x86_push_reg (code, X86_ECX);
2116 offset += 4;
2117 }
2118 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2119 x86_push_reg (code, X86_EDI);
2120 offset += 4;
2121 }
2122
2123 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2124 x86_mov_reg_reg (code, X86_ECX, sreg);
2125 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2126
2127 if (cfg->param_area)
2128 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2129 else
2130 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2131 x86_cld (code);
2132 x86_prefix (code, X86_REP_PREFIX);
2133 x86_stosl (code);
2134
2135 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2136 x86_pop_reg (code, X86_EDI);
2137 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2138 x86_pop_reg (code, X86_ECX);
2139 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2140 x86_pop_reg (code, X86_EAX);
2141 }
2142 return code;
2143 }
2144
2145
2146 static guint8*
2147 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2148 {
2149 /* Move return value to the target register */
2150 switch (ins->opcode) {
2151 case OP_CALL:
2152 case OP_CALL_REG:
2153 case OP_CALL_MEMBASE:
2154 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
2155 break;
2156 default:
2157 break;
2158 }
2159
2160 return code;
2161 }
2162
2163 #ifdef TARGET_MACH
2164 static int tls_gs_offset;
2165 #endif
2166
2167 gboolean
2168 mono_arch_have_fast_tls (void)
2169 {
2170 #ifdef TARGET_MACH
2171 static gboolean have_fast_tls = FALSE;
2172 static gboolean inited = FALSE;
2173 guint32 *ins;
2174
2175 if (mini_get_debug_options ()->use_fallback_tls)
2176 return FALSE;
2177 if (inited)
2178 return have_fast_tls;
2179
2180 ins = (guint32*)pthread_getspecific;
2181 /*
2182 * We're looking for these two instructions:
2183 *
2184 * mov 0x4(%esp),%eax
2185 * mov %gs:[offset](,%eax,4),%eax
2186 */
2187 have_fast_tls = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2188 tls_gs_offset = ins [2];
2189 inited = TRUE;
2190
2191 return have_fast_tls;
2192 #elif defined(TARGET_ANDROID)
2193 return FALSE;
2194 #else
2195 if (mini_get_debug_options ()->use_fallback_tls)
2196 return FALSE;
2197 return TRUE;
2198 #endif
2199 }
2200
2201 static guint8*
2202 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2203 {
2204 #if defined (TARGET_MACH)
2205 x86_prefix (code, X86_GS_PREFIX);
2206 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2207 #elif defined (TARGET_WIN32)
2208 /*
2209 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2210 * Journal and/or a disassembly of the TlsGet () function.
2211 */
2212 x86_prefix (code, X86_FS_PREFIX);
2213 x86_mov_reg_mem (code, dreg, 0x18, 4);
2214 if (tls_offset < 64) {
2215 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2216 } else {
2217 guint8 *buf [16];
2218
2219 g_assert (tls_offset < 0x440);
2220 /* Load TEB->TlsExpansionSlots */
2221 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2222 x86_test_reg_reg (code, dreg, dreg);
2223 buf [0] = code;
2224 x86_branch (code, X86_CC_EQ, code, TRUE);
2225 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2226 x86_patch (buf [0], code);
2227 }
2228 #else
2229 if (optimize_for_xen) {
2230 x86_prefix (code, X86_GS_PREFIX);
2231 x86_mov_reg_mem (code, dreg, 0, 4);
2232 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2233 } else {
2234 x86_prefix (code, X86_GS_PREFIX);
2235 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2236 }
2237 #endif
2238 return code;
2239 }
2240
2241 static guint8*
2242 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2243 {
2244 #if defined (TARGET_MACH)
2245 x86_prefix (code, X86_GS_PREFIX);
2246 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2247 #elif defined (TARGET_WIN32)
2248 g_assert_not_reached ();
2249 #else
2250 x86_prefix (code, X86_GS_PREFIX);
2251 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2252 #endif
2253 return code;
2254 }
2255
2256 /*
2257 * emit_setup_lmf:
2258 *
2259 * Emit code to initialize an LMF structure at LMF_OFFSET.
2260 */
2261 static guint8*
2262 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2263 {
2264 /* save all caller saved regs */
2265 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (target_mgreg_t));
2266 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2267 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (target_mgreg_t));
2268 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2269 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (target_mgreg_t));
2270 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2271 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (target_mgreg_t));
2272
2273 /* save the current IP */
2274 if (cfg->compile_aot) {
2275 /* This pushes the current ip */
2276 x86_call_imm (code, 0);
2277 x86_pop_reg (code, X86_EAX);
2278 } else {
2279 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2280 x86_mov_reg_imm (code, X86_EAX, 0);
2281 }
2282 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (target_mgreg_t));
2283
2284 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2285 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2286 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2287 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2288 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2289 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2290 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2291 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2292 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2293
2294 return code;
2295 }
2296
2297 /* benchmark and set based on cpu */
2298 #define LOOP_ALIGNMENT 8
2299 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2300
2301 #ifndef DISABLE_JIT
2302 void
2303 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2304 {
2305 MonoInst *ins;
2306 MonoCallInst *call;
2307 guint8 *code = cfg->native_code + cfg->code_len;
2308
2309 if (cfg->opt & MONO_OPT_LOOP) {
2310 int pad, align = LOOP_ALIGNMENT;
2311 /* set alignment depending on cpu */
2312 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2313 pad = align - pad;
2314 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2315 x86_padding (code, pad);
2316 cfg->code_len += pad;
2317 bb->native_offset = cfg->code_len;
2318 }
2319 }
2320
2321 if (cfg->verbose_level > 2)
2322 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2323
2324 int cpos = bb->max_offset;
2325
2326 set_code_cursor (cfg, code);
2327
2328 mono_debug_open_block (cfg, bb, code - cfg->native_code);
2329
2330 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2331 x86_breakpoint (code);
2332
2333 MONO_BB_FOR_EACH_INS (bb, ins) {
2334 const guint offset = code - cfg->native_code;
2335 set_code_cursor (cfg, code);
2336 int max_len = ins_get_size (ins->opcode);
2337 code = realloc_code (cfg, max_len);
2338
2339 if (cfg->debug_info)
2340 mono_debug_record_line_number (cfg, ins, offset);
2341
2342 switch (ins->opcode) {
2343 case OP_BIGMUL:
2344 x86_mul_reg (code, ins->sreg2, TRUE);
2345 break;
2346 case OP_BIGMUL_UN:
2347 x86_mul_reg (code, ins->sreg2, FALSE);
2348 break;
2349 case OP_X86_SETEQ_MEMBASE:
2350 case OP_X86_SETNE_MEMBASE:
2351 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2352 ins->inst_basereg, ins->inst_offset, TRUE);
2353 break;
2354 case OP_STOREI1_MEMBASE_IMM:
2355 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2356 break;
2357 case OP_STOREI2_MEMBASE_IMM:
2358 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2359 break;
2360 case OP_STORE_MEMBASE_IMM:
2361 case OP_STOREI4_MEMBASE_IMM:
2362 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2363 break;
2364 case OP_STOREI1_MEMBASE_REG:
2365 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2366 break;
2367 case OP_STOREI2_MEMBASE_REG:
2368 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2369 break;
2370 case OP_STORE_MEMBASE_REG:
2371 case OP_STOREI4_MEMBASE_REG:
2372 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2373 break;
2374 case OP_STORE_MEM_IMM:
2375 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2376 break;
2377 case OP_LOADU4_MEM:
2378 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2379 break;
2380 case OP_LOAD_MEM:
2381 case OP_LOADI4_MEM:
2382 /* These are created by the cprop pass so they use inst_imm as the source */
2383 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2384 break;
2385 case OP_LOADU1_MEM:
2386 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2387 break;
2388 case OP_LOADU2_MEM:
2389 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2390 break;
2391 case OP_LOAD_MEMBASE:
2392 case OP_LOADI4_MEMBASE:
2393 case OP_LOADU4_MEMBASE:
2394 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2395 break;
2396 case OP_LOADU1_MEMBASE:
2397 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2398 break;
2399 case OP_LOADI1_MEMBASE:
2400 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2401 break;
2402 case OP_LOADU2_MEMBASE:
2403 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2404 break;
2405 case OP_LOADI2_MEMBASE:
2406 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2407 break;
2408 case OP_ICONV_TO_I1:
2409 case OP_SEXT_I1:
2410 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2411 break;
2412 case OP_ICONV_TO_I2:
2413 case OP_SEXT_I2:
2414 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2415 break;
2416 case OP_ICONV_TO_U1:
2417 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2418 break;
2419 case OP_ICONV_TO_U2:
2420 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2421 break;
2422 case OP_COMPARE:
2423 case OP_ICOMPARE:
2424 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2425 break;
2426 case OP_COMPARE_IMM:
2427 case OP_ICOMPARE_IMM:
2428 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2429 break;
2430 case OP_X86_COMPARE_MEMBASE_REG:
2431 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2432 break;
2433 case OP_X86_COMPARE_MEMBASE_IMM:
2434 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2435 break;
2436 case OP_X86_COMPARE_MEMBASE8_IMM:
2437 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2438 break;
2439 case OP_X86_COMPARE_REG_MEMBASE:
2440 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2441 break;
2442 case OP_X86_COMPARE_MEM_IMM:
2443 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2444 break;
2445 case OP_X86_TEST_NULL:
2446 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2447 break;
2448 case OP_X86_ADD_MEMBASE_IMM:
2449 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2450 break;
2451 case OP_X86_ADD_REG_MEMBASE:
2452 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2453 break;
2454 case OP_X86_SUB_MEMBASE_IMM:
2455 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2456 break;
2457 case OP_X86_SUB_REG_MEMBASE:
2458 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2459 break;
2460 case OP_X86_AND_MEMBASE_IMM:
2461 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2462 break;
2463 case OP_X86_OR_MEMBASE_IMM:
2464 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2465 break;
2466 case OP_X86_XOR_MEMBASE_IMM:
2467 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2468 break;
2469 case OP_X86_ADD_MEMBASE_REG:
2470 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2471 break;
2472 case OP_X86_SUB_MEMBASE_REG:
2473 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2474 break;
2475 case OP_X86_AND_MEMBASE_REG:
2476 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2477 break;
2478 case OP_X86_OR_MEMBASE_REG:
2479 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2480 break;
2481 case OP_X86_XOR_MEMBASE_REG:
2482 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2483 break;
2484 case OP_X86_INC_MEMBASE:
2485 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2486 break;
2487 case OP_X86_INC_REG:
2488 x86_inc_reg (code, ins->dreg);
2489 break;
2490 case OP_X86_DEC_MEMBASE:
2491 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2492 break;
2493 case OP_X86_DEC_REG:
2494 x86_dec_reg (code, ins->dreg);
2495 break;
2496 case OP_X86_MUL_REG_MEMBASE:
2497 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2498 break;
2499 case OP_X86_AND_REG_MEMBASE:
2500 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2501 break;
2502 case OP_X86_OR_REG_MEMBASE:
2503 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2504 break;
2505 case OP_X86_XOR_REG_MEMBASE:
2506 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2507 break;
2508 case OP_BREAK:
2509 x86_breakpoint (code);
2510 break;
2511 case OP_RELAXED_NOP:
2512 x86_prefix (code, X86_REP_PREFIX);
2513 x86_nop (code);
2514 break;
2515 case OP_HARD_NOP:
2516 x86_nop (code);
2517 break;
2518 case OP_NOP:
2519 case OP_DUMMY_USE:
2520 case OP_DUMMY_ICONST:
2521 case OP_DUMMY_R8CONST:
2522 case OP_DUMMY_R4CONST:
2523 case OP_NOT_REACHED:
2524 case OP_NOT_NULL:
2525 break;
2526 case OP_IL_SEQ_POINT:
2527 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2528 break;
2529 case OP_SEQ_POINT: {
2530 int i;
2531
2532 if (cfg->compile_aot)
2533 NOT_IMPLEMENTED;
2534
2535 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2536
2537 /*
2538 * We do this _before_ the breakpoint, so single stepping after
2539 * a breakpoint is hit will step to the next IL offset.
2540 */
2541 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2542 MonoInst *var = cfg->arch.ss_tramp_var;
2543 guint8 *br [1];
2544
2545 g_assert (var);
2546 g_assert (var->opcode == OP_REGOFFSET);
2547 /* Load ss_tramp_var */
2548 /* This is equal to &ss_trampoline */
2549 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (target_mgreg_t));
2550 x86_mov_reg_membase (code, X86_ECX, X86_ECX, 0, sizeof (target_mgreg_t));
2551 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
2552 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2553 x86_call_reg (code, X86_ECX);
2554 x86_patch (br [0], code);
2555 }
2556
2557 /*
2558 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2559 * This means we have to put the loading of bp_tramp_var after the offset.
2560 */
2561
2562 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2563
2564 MonoInst *var = cfg->arch.bp_tramp_var;
2565
2566 g_assert (var);
2567 g_assert (var->opcode == OP_REGOFFSET);
2568 /* Load the address of the bp trampoline */
2569 /* This needs to be constant size */
2570 guint8 *start = code;
2571 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2572 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2573 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2574 x86_padding (code, size);
2575 }
2576 /*
2577 * A placeholder for a possible breakpoint inserted by
2578 * mono_arch_set_breakpoint ().
2579 */
2580 for (i = 0; i < 2; ++i)
2581 x86_nop (code);
2582 /*
2583 * Add an additional nop so skipping the bp doesn't cause the ip to point
2584 * to another IL offset.
2585 */
2586 x86_nop (code);
2587 break;
2588 }
2589 case OP_ADDCC:
2590 case OP_IADDCC:
2591 case OP_IADD:
2592 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2593 break;
2594 case OP_ADC:
2595 case OP_IADC:
2596 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2597 break;
2598 case OP_ADDCC_IMM:
2599 case OP_ADD_IMM:
2600 case OP_IADD_IMM:
2601 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2602 break;
2603 case OP_ADC_IMM:
2604 case OP_IADC_IMM:
2605 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2606 break;
2607 case OP_SUBCC:
2608 case OP_ISUBCC:
2609 case OP_ISUB:
2610 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2611 break;
2612 case OP_SBB:
2613 case OP_ISBB:
2614 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2615 break;
2616 case OP_SUBCC_IMM:
2617 case OP_SUB_IMM:
2618 case OP_ISUB_IMM:
2619 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2620 break;
2621 case OP_SBB_IMM:
2622 case OP_ISBB_IMM:
2623 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2624 break;
2625 case OP_IAND:
2626 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2627 break;
2628 case OP_AND_IMM:
2629 case OP_IAND_IMM:
2630 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2631 break;
2632 case OP_IDIV:
2633 case OP_IREM:
2634 /*
2635 * The code is the same for div/rem, the allocator will allocate dreg
2636 * to RAX/RDX as appropriate.
2637 */
2638 if (ins->sreg2 == X86_EDX) {
2639 /* cdq clobbers this */
2640 x86_push_reg (code, ins->sreg2);
2641 x86_cdq (code);
2642 x86_div_membase (code, X86_ESP, 0, TRUE);
2643 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2644 } else {
2645 x86_cdq (code);
2646 x86_div_reg (code, ins->sreg2, TRUE);
2647 }
2648 break;
2649 case OP_IDIV_UN:
2650 case OP_IREM_UN:
2651 if (ins->sreg2 == X86_EDX) {
2652 x86_push_reg (code, ins->sreg2);
2653 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2654 x86_div_membase (code, X86_ESP, 0, FALSE);
2655 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2656 } else {
2657 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2658 x86_div_reg (code, ins->sreg2, FALSE);
2659 }
2660 break;
2661 case OP_DIV_IMM:
2662 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2663 x86_cdq (code);
2664 x86_div_reg (code, ins->sreg2, TRUE);
2665 break;
2666 case OP_IREM_IMM: {
2667 int power = mono_is_power_of_two (ins->inst_imm);
2668
2669 g_assert (ins->sreg1 == X86_EAX);
2670 g_assert (ins->dreg == X86_EAX);
2671 g_assert (power >= 0);
2672
2673 if (power == 1) {
2674 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2675 x86_cdq (code);
2676 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2677 /*
2678 * If the divident is >= 0, this does not nothing. If it is positive, it
2679 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2680 */
2681 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2682 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2683 } else if (power == 0) {
2684 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2685 } else {
2686 /* Based on gcc code */
2687
2688 /* Add compensation for negative dividents */
2689 x86_cdq (code);
2690 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2691 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2692 /* Compute remainder */
2693 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2694 /* Remove compensation */
2695 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2696 }
2697 break;
2698 }
2699 case OP_IOR:
2700 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2701 break;
2702 case OP_OR_IMM:
2703 case OP_IOR_IMM:
2704 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2705 break;
2706 case OP_IXOR:
2707 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2708 break;
2709 case OP_XOR_IMM:
2710 case OP_IXOR_IMM:
2711 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2712 break;
2713 case OP_ISHL:
2714 g_assert (ins->sreg2 == X86_ECX);
2715 x86_shift_reg (code, X86_SHL, ins->dreg);
2716 break;
2717 case OP_ISHR:
2718 g_assert (ins->sreg2 == X86_ECX);
2719 x86_shift_reg (code, X86_SAR, ins->dreg);
2720 break;
2721 case OP_SHR_IMM:
2722 case OP_ISHR_IMM:
2723 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2724 break;
2725 case OP_SHR_UN_IMM:
2726 case OP_ISHR_UN_IMM:
2727 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2728 break;
2729 case OP_ISHR_UN:
2730 g_assert (ins->sreg2 == X86_ECX);
2731 x86_shift_reg (code, X86_SHR, ins->dreg);
2732 break;
2733 case OP_SHL_IMM:
2734 case OP_ISHL_IMM:
2735 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2736 break;
2737 case OP_LSHL: {
2738 guint8 *jump_to_end;
2739
2740 /* handle shifts below 32 bits */
2741 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2742 x86_shift_reg (code, X86_SHL, ins->sreg1);
2743
2744 x86_test_reg_imm (code, X86_ECX, 32);
2745 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2746
2747 /* handle shift over 32 bit */
2748 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1);
2749 x86_clear_reg (code, ins->sreg1);
2750
2751 x86_patch (jump_to_end, code);
2752 }
2753 break;
2754 case OP_LSHR: {
2755 guint8 *jump_to_end;
2756
2757 /* handle shifts below 32 bits */
2758 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2759 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2760
2761 x86_test_reg_imm (code, X86_ECX, 32);
2762 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2763
2764 /* handle shifts over 31 bits */
2765 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2766 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2767
2768 x86_patch (jump_to_end, code);
2769 }
2770 break;
2771 case OP_LSHR_UN: {
2772 guint8 *jump_to_end;
2773
2774 /* handle shifts below 32 bits */
2775 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2776 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2777
2778 x86_test_reg_imm (code, X86_ECX, 32);
2779 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2780
2781 /* handle shifts over 31 bits */
2782 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2783 x86_clear_reg (code, ins->backend.reg3);
2784
2785 x86_patch (jump_to_end, code);
2786 }
2787 break;
2788 case OP_LSHL_IMM:
2789 if (ins->inst_imm >= 32) {
2790 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1);
2791 x86_clear_reg (code, ins->sreg1);
2792 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2793 } else {
2794 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2795 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2796 }
2797 break;
2798 case OP_LSHR_IMM:
2799 if (ins->inst_imm >= 32) {
2800 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2801 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2802 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2803 } else {
2804 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2805 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2806 }
2807 break;
2808 case OP_LSHR_UN_IMM:
2809 if (ins->inst_imm >= 32) {
2810 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3);
2811 x86_clear_reg (code, ins->backend.reg3);
2812 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2813 } else {
2814 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2815 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2816 }
2817 break;
2818 case OP_INOT:
2819 x86_not_reg (code, ins->sreg1);
2820 break;
2821 case OP_INEG:
2822 x86_neg_reg (code, ins->sreg1);
2823 break;
2824
2825 case OP_IMUL:
2826 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2827 break;
2828 case OP_MUL_IMM:
2829 case OP_IMUL_IMM:
2830 switch (ins->inst_imm) {
2831 case 2:
2832 /* MOV r1, r2 */
2833 /* ADD r1, r1 */
2834 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
2835 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2836 break;
2837 case 3:
2838 /* LEA r1, [r2 + r2*2] */
2839 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2840 break;
2841 case 5:
2842 /* LEA r1, [r2 + r2*4] */
2843 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2844 break;
2845 case 6:
2846 /* LEA r1, [r2 + r2*2] */
2847 /* ADD r1, r1 */
2848 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2849 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2850 break;
2851 case 9:
2852 /* LEA r1, [r2 + r2*8] */
2853 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2854 break;
2855 case 10:
2856 /* LEA r1, [r2 + r2*4] */
2857 /* ADD r1, r1 */
2858 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2859 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2860 break;
2861 case 12:
2862 /* LEA r1, [r2 + r2*2] */
2863 /* SHL r1, 2 */
2864 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2865 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2866 break;
2867 case 25:
2868 /* LEA r1, [r2 + r2*4] */
2869 /* LEA r1, [r1 + r1*4] */
2870 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2871 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2872 break;
2873 case 100:
2874 /* LEA r1, [r2 + r2*4] */
2875 /* SHL r1, 2 */
2876 /* LEA r1, [r1 + r1*4] */
2877 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2878 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2879 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2880 break;
2881 default:
2882 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2883 break;
2884 }
2885 break;
2886 case OP_IMUL_OVF:
2887 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2888 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2889 break;
2890 case OP_IMUL_OVF_UN: {
2891 /* the mul operation and the exception check should most likely be split */
2892 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2893 /*g_assert (ins->sreg2 == X86_EAX);
2894 g_assert (ins->dreg == X86_EAX);*/
2895 if (ins->sreg2 == X86_EAX) {
2896 non_eax_reg = ins->sreg1;
2897 } else if (ins->sreg1 == X86_EAX) {
2898 non_eax_reg = ins->sreg2;
2899 } else {
2900 /* no need to save since we're going to store to it anyway */
2901 if (ins->dreg != X86_EAX) {
2902 saved_eax = TRUE;
2903 x86_push_reg (code, X86_EAX);
2904 }
2905 x86_mov_reg_reg (code, X86_EAX, ins->sreg1);
2906 non_eax_reg = ins->sreg2;
2907 }
2908 if (ins->dreg == X86_EDX) {
2909 if (!saved_eax) {
2910 saved_eax = TRUE;
2911 x86_push_reg (code, X86_EAX);
2912 }
2913 } else {
2914 saved_edx = TRUE;
2915 x86_push_reg (code, X86_EDX);
2916 }
2917 x86_mul_reg (code, non_eax_reg, FALSE);
2918 /* save before the check since pop and mov don't change the flags */
2919 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
2920 if (saved_edx)
2921 x86_pop_reg (code, X86_EDX);
2922 if (saved_eax)
2923 x86_pop_reg (code, X86_EAX);
2924 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2925 break;
2926 }
2927 case OP_ICONST:
2928 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2929 break;
2930 case OP_AOTCONST:
2931 g_assert_not_reached ();
2932 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_i1, ins->inst_p0);
2933 x86_mov_reg_imm (code, ins->dreg, 0);
2934 break;
2935 case OP_JUMP_TABLE:
2936 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_i1, ins->inst_p0);
2937 x86_mov_reg_imm (code, ins->dreg, 0);
2938 break;
2939 case OP_LOAD_GOTADDR:
2940 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
2941 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
2942 break;
2943 case OP_GOT_ENTRY:
2944 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2945 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2946 break;
2947 case OP_X86_PUSH_GOT_ENTRY:
2948 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)(gsize)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2949 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2950 break;
2951 case OP_MOVE:
2952 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
2953 break;
2954
2955 case OP_TAILCALL_PARAMETER:
2956 // This opcode helps compute sizes, i.e.
2957 // of the subsequent OP_TAILCALL, but contributes no code.
2958 g_assert (ins->next);
2959 break;
2960
2961 case OP_TAILCALL:
2962 case OP_TAILCALL_MEMBASE:
2963 case OP_TAILCALL_REG: {
2964 call = (MonoCallInst*)ins;
2965 int pos = 0, i;
2966 gboolean const tailcall_membase = ins->opcode == OP_TAILCALL_MEMBASE;
2967 gboolean const tailcall_reg = (ins->opcode == OP_TAILCALL_REG);
2968 int const sreg1 = ins->sreg1;
2969 gboolean const sreg1_ecx = sreg1 == X86_ECX;
2970 gboolean const tailcall_membase_ecx = tailcall_membase && sreg1_ecx;
2971 gboolean const tailcall_membase_not_ecx = tailcall_membase && !sreg1_ecx;
2972
2973 max_len += (call->stack_usage - call->stack_align_amount) / sizeof (target_mgreg_t) * ins_get_size (OP_TAILCALL_PARAMETER);
2974 code = realloc_code (cfg, max_len);
2975
2976 ins->flags |= MONO_INST_GC_CALLSITE;
2977 ins->backend.pc_offset = code - cfg->native_code;
2978
2979 g_assert (!cfg->method->save_lmf);
2980
2981 // Ecx is volatile, not used for parameters, or rgctx/imt (edx).
2982 // It is also not used for return value, though that does not matter.
2983 // Ecx is preserved across the tailcall formation.
2984 //
2985 // Eax could also be used here at the cost of a push/pop moving the parameters.
2986 // Edx must be preserved as it is rgctx/imt.
2987 //
2988 // If ecx happens to be the base of the tailcall_membase, then
2989 // just end with jmp [ecx+offset] -- one instruction.
2990 // if ecx is not the base, then move ecx, [reg+offset] and later jmp [ecx] -- two instructions.
2991
2992 if (tailcall_reg) {
2993 g_assert (sreg1 > -1);
2994 x86_mov_reg_reg (code, X86_ECX, sreg1);
2995 } else if (tailcall_membase_not_ecx) {
2996 g_assert (sreg1 > -1);
2997 x86_mov_reg_membase (code, X86_ECX, sreg1, ins->inst_offset, 4);
2998 }
2999
3000 /* restore callee saved registers */
3001 for (i = 0; i < X86_NREG; ++i)
3002 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3003 pos -= 4;
3004 if (cfg->used_int_regs & (1 << X86_ESI)) {
3005 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3006 pos += 4;
3007 }
3008 if (cfg->used_int_regs & (1 << X86_EDI)) {
3009 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3010 pos += 4;
3011 }
3012 if (cfg->used_int_regs & (1 << X86_EBX)) {
3013 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3014 pos += 4;
3015 }
3016
3017 /* Copy arguments on the stack to our argument area */
3018 // FIXME use rep mov for constant code size, before nonvolatiles
3019 // restored, first saving esi, edi into volatiles
3020 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3021 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3022 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3023 }
3024
3025 /* restore ESP/EBP */
3026 x86_leave (code);
3027
3028 if (tailcall_membase_ecx) {
3029 x86_jump_membase (code, X86_ECX, ins->inst_offset);
3030 } else if (tailcall_reg || tailcall_membase_not_ecx) {
3031 x86_jump_reg (code, X86_ECX);
3032 } else {
3033 // FIXME Patch data instead of code.
3034 code = x86_align_and_patch (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3035 x86_jump32 (code, 0);
3036 }
3037
3038 ins->flags |= MONO_INST_GC_CALLSITE;
3039 break;
3040 }
3041 case OP_CHECK_THIS:
3042 /* ensure ins->sreg1 is not NULL
3043 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3044 * cmp DWORD PTR [eax], 0
3045 */
3046 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3047 break;
3048 case OP_ARGLIST: {
3049 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3050 x86_push_reg (code, hreg);
3051 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3052 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3053 x86_pop_reg (code, hreg);
3054 break;
3055 }
3056 case OP_FCALL:
3057 case OP_LCALL:
3058 case OP_VCALL:
3059 case OP_VCALL2:
3060 case OP_VOIDCALL:
3061 case OP_CALL:
3062 case OP_FCALL_REG:
3063 case OP_LCALL_REG:
3064 case OP_VCALL_REG:
3065 case OP_VCALL2_REG:
3066 case OP_VOIDCALL_REG:
3067 case OP_CALL_REG:
3068 case OP_FCALL_MEMBASE:
3069 case OP_LCALL_MEMBASE:
3070 case OP_VCALL_MEMBASE:
3071 case OP_VCALL2_MEMBASE:
3072 case OP_VOIDCALL_MEMBASE:
3073 case OP_CALL_MEMBASE: {
3074 CallInfo *cinfo;
3075
3076 call = (MonoCallInst*)ins;
3077 cinfo = call->call_info;
3078
3079 switch (ins->opcode) {
3080 case OP_FCALL:
3081 case OP_LCALL:
3082 case OP_VCALL:
3083 case OP_VCALL2:
3084 case OP_VOIDCALL:
3085 case OP_CALL: {
3086 const MonoJumpInfoTarget patch = mono_call_to_patch (call);
3087 code = emit_call (cfg, code, patch.type, patch.target);
3088 break;
3089 }
3090 case OP_FCALL_REG:
3091 case OP_LCALL_REG:
3092 case OP_VCALL_REG:
3093 case OP_VCALL2_REG:
3094 case OP_VOIDCALL_REG:
3095 case OP_CALL_REG:
3096 x86_call_reg (code, ins->sreg1);
3097 break;
3098 case OP_FCALL_MEMBASE:
3099 case OP_LCALL_MEMBASE:
3100 case OP_VCALL_MEMBASE:
3101 case OP_VCALL2_MEMBASE:
3102 case OP_VOIDCALL_MEMBASE:
3103 case OP_CALL_MEMBASE:
3104 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3105 break;
3106 default:
3107 g_assert_not_reached ();
3108 break;
3109 }
3110 ins->flags |= MONO_INST_GC_CALLSITE;
3111 ins->backend.pc_offset = code - cfg->native_code;
3112 if (cinfo->callee_stack_pop) {
3113 /* Have to compensate for the stack space popped by the callee */
3114 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3115 }
3116 code = emit_move_return_value (cfg, ins, code);
3117 break;
3118 }
3119 case OP_X86_LEA:
3120 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3121 break;
3122 case OP_X86_LEA_MEMBASE:
3123 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3124 break;
3125 case OP_X86_XCHG:
3126 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3127 break;
3128 case OP_LOCALLOC:
3129 /* keep alignment */
3130 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3131 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3132 code = mono_emit_stack_alloc (cfg, code, ins);
3133 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3134 if (cfg->param_area)
3135 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3136 break;
3137 case OP_LOCALLOC_IMM: {
3138 guint32 size = ins->inst_imm;
3139 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3140
3141 if (ins->flags & MONO_INST_INIT) {
3142 /* FIXME: Optimize this */
3143 x86_mov_reg_imm (code, ins->dreg, size);
3144 ins->sreg1 = ins->dreg;
3145
3146 code = mono_emit_stack_alloc (cfg, code, ins);
3147 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3148 } else {
3149 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3150 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
3151 }
3152 if (cfg->param_area)
3153 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3154 break;
3155 }
3156 case OP_THROW: {
3157 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3158 x86_push_reg (code, ins->sreg1);
3159 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ID,
3160 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arch_throw_exception));
3161 ins->flags |= MONO_INST_GC_CALLSITE;
3162 ins->backend.pc_offset = code - cfg->native_code;
3163 break;
3164 }
3165 case OP_RETHROW: {
3166 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3167 x86_push_reg (code, ins->sreg1);
3168 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ID,
3169 GUINT_TO_POINTER (MONO_JIT_ICALL_mono_arch_rethrow_exception));
3170 ins->flags |= MONO_INST_GC_CALLSITE;
3171 ins->backend.pc_offset = code - cfg->native_code;
3172 break;
3173 }
3174 case OP_CALL_HANDLER:
3175 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3176 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3177 x86_call_imm (code, 0);
3178 for (GList *tmp = ins->inst_eh_blocks; tmp != bb->clause_holes; tmp = tmp->prev)
3179 mono_cfg_add_try_hole (cfg, ((MonoLeaveClause *) tmp->data)->clause, code, bb);
3180 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3181 break;
3182 case OP_START_HANDLER: {
3183 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3184 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3185 if (cfg->param_area)
3186 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3187 break;
3188 }
3189 case OP_ENDFINALLY: {
3190 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3191 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3192 x86_ret (code);
3193 break;
3194 }
3195 case OP_ENDFILTER: {
3196 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3197 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3198 /* The local allocator will put the result into EAX */
3199 x86_ret (code);
3200 break;
3201 }
3202 case OP_GET_EX_OBJ:
3203 x86_mov_reg_reg (code, ins->dreg, X86_EAX);
3204 break;
3205
3206 case OP_LABEL:
3207 ins->inst_c0 = code - cfg->native_code;
3208 break;
3209 case OP_BR:
3210 if (ins->inst_target_bb->native_offset) {
3211 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3212 } else {
3213 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3214 if ((cfg->opt & MONO_OPT_BRANCH) &&
3215 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3216 x86_jump8 (code, 0);
3217 else
3218 x86_jump32 (code, 0);
3219 }
3220 break;
3221 case OP_BR_REG:
3222 x86_jump_reg (code, ins->sreg1);
3223 break;
3224 case OP_ICNEQ:
3225 case OP_ICGE:
3226 case OP_ICLE:
3227 case OP_ICGE_UN:
3228 case OP_ICLE_UN:
3229
3230 case OP_CEQ:
3231 case OP_CLT:
3232 case OP_CLT_UN:
3233 case OP_CGT:
3234 case OP_CGT_UN:
3235 case OP_CNE:
3236 case OP_ICEQ:
3237 case OP_ICLT:
3238 case OP_ICLT_UN:
3239 case OP_ICGT:
3240 case OP_ICGT_UN:
3241 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3242 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3243 break;
3244 case OP_COND_EXC_EQ:
3245 case OP_COND_EXC_NE_UN:
3246 case OP_COND_EXC_LT:
3247 case OP_COND_EXC_LT_UN:
3248 case OP_COND_EXC_GT:
3249 case OP_COND_EXC_GT_UN:
3250 case OP_COND_EXC_GE:
3251 case OP_COND_EXC_GE_UN:
3252 case OP_COND_EXC_LE:
3253 case OP_COND_EXC_LE_UN:
3254 case OP_COND_EXC_IEQ:
3255 case OP_COND_EXC_INE_UN:
3256 case OP_COND_EXC_ILT:
3257 case OP_COND_EXC_ILT_UN:
3258 case OP_COND_EXC_IGT:
3259 case OP_COND_EXC_IGT_UN:
3260 case OP_COND_EXC_IGE:
3261 case OP_COND_EXC_IGE_UN:
3262 case OP_COND_EXC_ILE:
3263 case OP_COND_EXC_ILE_UN:
3264 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char*)ins->inst_p1);
3265 break;
3266 case OP_COND_EXC_OV:
3267 case OP_COND_EXC_NO:
3268 case OP_COND_EXC_C:
3269 case OP_COND_EXC_NC:
3270 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), (const char*)ins->inst_p1);
3271 break;
3272 case OP_COND_EXC_IOV:
3273 case OP_COND_EXC_INO:
3274 case OP_COND_EXC_IC:
3275 case OP_COND_EXC_INC:
3276 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), (const char*)ins->inst_p1);
3277 break;
3278 case OP_IBEQ:
3279 case OP_IBNE_UN:
3280 case OP_IBLT:
3281 case OP_IBLT_UN:
3282 case OP_IBGT:
3283 case OP_IBGT_UN:
3284 case OP_IBGE:
3285 case OP_IBGE_UN:
3286 case OP_IBLE:
3287 case OP_IBLE_UN:
3288 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3289 break;
3290
3291 case OP_CMOV_IEQ:
3292 case OP_CMOV_IGE:
3293 case OP_CMOV_IGT:
3294 case OP_CMOV_ILE:
3295 case OP_CMOV_ILT:
3296 case OP_CMOV_INE_UN:
3297 case OP_CMOV_IGE_UN:
3298 case OP_CMOV_IGT_UN:
3299 case OP_CMOV_ILE_UN:
3300 case OP_CMOV_ILT_UN:
3301 g_assert (ins->dreg == ins->sreg1);
3302 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3303 break;
3304
3305 /* floating point opcodes */
3306 case OP_R8CONST: {
3307 double d = *(double *)ins->inst_p0;
3308
3309 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3310 x86_fldz (code);
3311 } else if (d == 1.0) {
3312 x86_fld1 (code);
3313 } else {
3314 if (cfg->compile_aot) {
3315 guint32 *val = (guint32*)&d;
3316 x86_push_imm (code, val [1]);
3317 x86_push_imm (code, val [0]);
3318 x86_fld_membase (code, X86_ESP, 0, TRUE);
3319 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3320 }
3321 else {
3322 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3323 x86_fld (code, NULL, TRUE);
3324 }
3325 }
3326 break;
3327 }
3328 case OP_R4CONST: {
3329 float f = *(float *)ins->inst_p0;
3330
3331 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3332 x86_fldz (code);
3333 } else if (f == 1.0) {
3334 x86_fld1 (code);
3335 } else {
3336 if (cfg->compile_aot) {
3337 guint32 val = *(guint32*)&f;
3338 x86_push_imm (code, val);
3339 x86_fld_membase (code, X86_ESP, 0, FALSE);
3340 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3341 }
3342 else {
3343 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3344 x86_fld (code, NULL, FALSE);
3345 }
3346 }
3347 break;
3348 }
3349 case OP_STORER8_MEMBASE_REG:
3350 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3351 break;
3352 case OP_LOADR8_MEMBASE:
3353 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3354 break;
3355 case OP_STORER4_MEMBASE_REG:
3356 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3357 break;
3358 case OP_LOADR4_MEMBASE:
3359 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3360 break;
3361 case OP_ICONV_TO_R4:
3362 x86_push_reg (code, ins->sreg1);
3363 x86_fild_membase (code, X86_ESP, 0, FALSE);
3364 /* Change precision */
3365 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3366 x86_fld_membase (code, X86_ESP, 0, FALSE);
3367 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3368 break;
3369 case OP_ICONV_TO_R8:
3370 x86_push_reg (code, ins->sreg1);
3371 x86_fild_membase (code, X86_ESP, 0, FALSE);
3372 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3373 break;
3374 case OP_ICONV_TO_R_UN:
3375 x86_push_imm (code, 0);
3376 x86_push_reg (code, ins->sreg1);
3377 x86_fild_membase (code, X86_ESP, 0, TRUE);
3378 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3379 break;
3380 case OP_X86_FP_LOAD_I8:
3381 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3382 break;
3383 case OP_X86_FP_LOAD_I4:
3384 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3385 break;
3386 case OP_FCONV_TO_R4:
3387 /* Change precision */
3388 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3389 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3390 x86_fld_membase (code, X86_ESP, 0, FALSE);
3391 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3392 break;
3393 case OP_FCONV_TO_I1:
3394 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3395 break;
3396 case OP_FCONV_TO_U1:
3397 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3398 break;
3399 case OP_FCONV_TO_I2:
3400 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3401 break;
3402 case OP_FCONV_TO_U2:
3403 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3404 break;
3405 case OP_FCONV_TO_I4:
3406 case OP_FCONV_TO_I:
3407 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3408 break;
3409 case OP_FCONV_TO_I8:
3410 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3411 x86_fnstcw_membase(code, X86_ESP, 0);
3412 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3413 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3414 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3415 x86_fldcw_membase (code, X86_ESP, 2);
3416 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3417 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3418 x86_pop_reg (code, ins->dreg);
3419 x86_pop_reg (code, ins->backend.reg3);
3420 x86_fldcw_membase (code, X86_ESP, 0);
3421 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3422 break;
3423 case OP_LCONV_TO_R8_2:
3424 x86_push_reg (code, ins->sreg2);
3425 x86_push_reg (code, ins->sreg1);
3426 x86_fild_membase (code, X86_ESP, 0, TRUE);
3427 /* Change precision */
3428 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3429 x86_fld_membase (code, X86_ESP, 0, TRUE);
3430 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3431 break;
3432 case OP_LCONV_TO_R4_2:
3433 x86_push_reg (code, ins->sreg2);
3434 x86_push_reg (code, ins->sreg1);
3435 x86_fild_membase (code, X86_ESP, 0, TRUE);
3436 /* Change precision */
3437 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3438 x86_fld_membase (code, X86_ESP, 0, FALSE);
3439 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3440 break;
3441 case OP_LCONV_TO_R_UN_2: {
3442 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3443 guint8 *br;
3444
3445 /* load 64bit integer to FP stack */
3446 x86_push_reg (code, ins->sreg2);
3447 x86_push_reg (code, ins->sreg1);
3448 x86_fild_membase (code, X86_ESP, 0, TRUE);
3449
3450 /* test if lreg is negative */
3451 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3452 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3453
3454 /* add correction constant mn */
3455 if (cfg->compile_aot) {
3456 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3457 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3458 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3459 x86_fld80_membase (code, X86_ESP, 2);
3460 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3461 } else {
3462 x86_fld80_mem (code, mn);
3463 }
3464 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3465
3466 x86_patch (br, code);
3467
3468 /* Change precision */
3469 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3470 x86_fld_membase (code, X86_ESP, 0, TRUE);
3471
3472 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3473
3474 break;
3475 }
3476 case OP_LCONV_TO_OVF_I:
3477 case OP_LCONV_TO_OVF_I4_2: {
3478 guint8 *br [3], *label [1];
3479 MonoInst *tins;
3480
3481 /*
3482 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3483 */
3484 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3485
3486 /* If the low word top bit is set, see if we are negative */
3487 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3488 /* We are not negative (no top bit set, check for our top word to be zero */
3489 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3490 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3491 label [0] = code;
3492
3493 /* throw exception */
3494 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3495 if (tins) {
3496 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3497 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3498 x86_jump8 (code, 0);
3499 else
3500 x86_jump32 (code, 0);
3501 } else {
3502 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3503 x86_jump32 (code, 0);
3504 }
3505
3506
3507 x86_patch (br [0], code);
3508 /* our top bit is set, check that top word is 0xfffffff */
3509 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3510
3511 x86_patch (br [1], code);
3512 /* nope, emit exception */
3513 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3514 x86_patch (br [2], label [0]);
3515
3516 x86_mov_reg_reg (code, ins->dreg, ins->sreg1);
3517 break;
3518 }
3519 case OP_FMOVE:
3520 /* Not needed on the fp stack */
3521 break;
3522 case OP_MOVE_F_TO_I4:
3523 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3524 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3525 break;
3526 case OP_MOVE_I4_TO_F:
3527 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3528 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3529 break;
3530 case OP_FADD:
3531 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3532 break;
3533 case OP_FSUB:
3534 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3535 break;
3536 case OP_FMUL:
3537 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3538 break;
3539 case OP_FDIV:
3540 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3541 break;
3542 case OP_FNEG:
3543 x86_fchs (code);
3544 break;
3545 case OP_SIN:
3546 x86_fsin (code);
3547 x86_fldz (code);
3548 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3549 break;
3550 case OP_COS:
3551 x86_fcos (code);
3552 x86_fldz (code);
3553 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3554 break;
3555 case OP_ABS:
3556 x86_fabs (code);
3557 break;
3558 case OP_TAN: {
3559 /*
3560 * it really doesn't make sense to inline all this code,
3561 * it's here just to show that things may not be as simple
3562 * as they appear.
3563 */
3564 guchar *check_pos, *end_tan, *pop_jump;
3565 x86_push_reg (code, X86_EAX);
3566 x86_fptan (code);
3567 x86_fnstsw (code);
3568 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3569 check_pos = code;
3570 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3571 x86_fstp (code, 0); /* pop the 1.0 */
3572 end_tan = code;
3573 x86_jump8 (code, 0);
3574 x86_fldpi (code);
3575 x86_fp_op (code, X86_FADD, 0);
3576 x86_fxch (code, 1);
3577 x86_fprem1 (code);
3578 x86_fstsw (code);
3579 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3580 pop_jump = code;
3581 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3582 x86_fstp (code, 1);
3583 x86_fptan (code);
3584 x86_patch (pop_jump, code);
3585 x86_fstp (code, 0); /* pop the 1.0 */
3586 x86_patch (check_pos, code);
3587 x86_patch (end_tan, code);
3588 x86_fldz (code);
3589 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3590 x86_pop_reg (code, X86_EAX);
3591 break;
3592 }
3593 case OP_ATAN:
3594 x86_fld1 (code);
3595 x86_fpatan (code);
3596 x86_fldz (code);
3597 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3598 break;
3599 case OP_SQRT:
3600 x86_fsqrt (code);
3601 break;
3602 case OP_ROUND:
3603 x86_frndint (code);
3604 break;
3605 case OP_IMIN:
3606 g_assert (cfg->opt & MONO_OPT_CMOV);
3607 g_assert (ins->dreg == ins->sreg1);
3608 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3609 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3610 break;
3611 case OP_IMIN_UN:
3612 g_assert (cfg->opt & MONO_OPT_CMOV);
3613 g_assert (ins->dreg == ins->sreg1);
3614 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3615 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3616 break;
3617 case OP_IMAX:
3618 g_assert (cfg->opt & MONO_OPT_CMOV);
3619 g_assert (ins->dreg == ins->sreg1);
3620 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3621 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3622 break;
3623 case OP_IMAX_UN:
3624 g_assert (cfg->opt & MONO_OPT_CMOV);
3625 g_assert (ins->dreg == ins->sreg1);
3626 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3627 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3628 break;
3629 case OP_X86_FPOP:
3630 x86_fstp (code, 0);
3631 break;
3632 case OP_X86_FXCH:
3633 x86_fxch (code, ins->inst_imm);
3634 break;
3635 case OP_FREM: {
3636 guint8 *l1, *l2;
3637
3638 x86_push_reg (code, X86_EAX);
3639 /* we need to exchange ST(0) with ST(1) */
3640 x86_fxch (code, 1);
3641
3642 /* this requires a loop, because fprem somtimes
3643 * returns a partial remainder */
3644 l1 = code;
3645 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3646 /* x86_fprem1 (code); */
3647 x86_fprem (code);
3648 x86_fnstsw (code);
3649 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3650 l2 = code;
3651 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3652 x86_patch (l2, l1);
3653
3654 /* pop result */
3655 x86_fstp (code, 1);
3656
3657 x86_pop_reg (code, X86_EAX);
3658 break;
3659 }
3660 case OP_FCOMPARE:
3661 if (cfg->opt & MONO_OPT_FCMOV) {
3662 x86_fcomip (code, 1);
3663 x86_fstp (code, 0);
3664 break;
3665 }
3666 /* this overwrites EAX */
3667 EMIT_FPCOMPARE(code);
3668 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3669 break;
3670 case OP_FCEQ:
3671 case OP_FCNEQ:
3672 if (cfg->opt & MONO_OPT_FCMOV) {
3673 /* zeroing the register at the start results in
3674 * shorter and faster code (we can also remove the widening op)
3675 */
3676 guchar *unordered_check;
3677 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3678 x86_fcomip (code, 1);
3679 x86_fstp (code, 0);
3680 unordered_check = code;
3681 x86_branch8 (code, X86_CC_P, 0, FALSE);
3682 if (ins->opcode == OP_FCEQ) {
3683 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3684 x86_patch (unordered_check, code);
3685 } else {
3686 guchar *jump_to_end;
3687 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3688 jump_to_end = code;
3689 x86_jump8 (code, 0);
3690 x86_patch (unordered_check, code);
3691 x86_inc_reg (code, ins->dreg);
3692 x86_patch (jump_to_end, code);
3693 }
3694
3695 break;
3696 }
3697 if (ins->dreg != X86_EAX)
3698 x86_push_reg (code, X86_EAX);
3699
3700 EMIT_FPCOMPARE(code);
3701 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3702 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3703 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3704 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3705
3706 if (ins->dreg != X86_EAX)
3707 x86_pop_reg (code, X86_EAX);
3708 break;
3709 case OP_FCLT:
3710 case OP_FCLT_UN:
3711 if (cfg->opt & MONO_OPT_FCMOV) {
3712 /* zeroing the register at the start results in
3713 * shorter and faster code (we can also remove the widening op)
3714 */
3715 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3716 x86_fcomip (code, 1);
3717 x86_fstp (code, 0);
3718 if (ins->opcode == OP_FCLT_UN) {
3719 guchar *unordered_check = code;
3720 guchar *jump_to_end;
3721 x86_branch8 (code, X86_CC_P, 0, FALSE);
3722 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3723 jump_to_end = code;
3724 x86_jump8 (code, 0);
3725 x86_patch (unordered_check, code);
3726 x86_inc_reg (code, ins->dreg);
3727 x86_patch (jump_to_end, code);
3728 } else {
3729 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3730 }
3731 break;
3732 }
3733 if (ins->dreg != X86_EAX)
3734 x86_push_reg (code, X86_EAX);
3735
3736 EMIT_FPCOMPARE(code);
3737 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3738 if (ins->opcode == OP_FCLT_UN) {
3739 guchar *is_not_zero_check, *end_jump;
3740 is_not_zero_check = code;
3741 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3742 end_jump = code;
3743 x86_jump8 (code, 0);
3744 x86_patch (is_not_zero_check, code);
3745 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3746
3747 x86_patch (end_jump, code);
3748 }
3749 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3750 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3751
3752 if (ins->dreg != X86_EAX)
3753 x86_pop_reg (code, X86_EAX);
3754 break;
3755 case OP_FCLE: {
3756 guchar *unordered_check;
3757 guchar *jump_to_end;
3758 if (cfg->opt & MONO_OPT_FCMOV) {
3759 /* zeroing the register at the start results in
3760 * shorter and faster code (we can also remove the widening op)
3761 */
3762 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3763 x86_fcomip (code, 1);
3764 x86_fstp (code, 0);
3765 unordered_check = code;
3766 x86_branch8 (code, X86_CC_P, 0, FALSE);
3767 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3768 x86_patch (unordered_check, code);
3769 break;
3770 }
3771 if (ins->dreg != X86_EAX)
3772 x86_push_reg (code, X86_EAX);
3773
3774 EMIT_FPCOMPARE(code);
3775 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3776 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3777 unordered_check = code;
3778 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3779
3780 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3781 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3782 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3783 jump_to_end = code;
3784 x86_jump8 (code, 0);
3785 x86_patch (unordered_check, code);
3786 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3787 x86_patch (jump_to_end, code);
3788
3789 if (ins->dreg != X86_EAX)
3790 x86_pop_reg (code, X86_EAX);
3791 break;
3792 }
3793 case OP_FCGT:
3794 case OP_FCGT_UN:
3795 if (cfg->opt & MONO_OPT_FCMOV) {
3796 /* zeroing the register at the start results in
3797 * shorter and faster code (we can also remove the widening op)
3798 */
3799 guchar *unordered_check;
3800 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3801 x86_fcomip (code, 1);
3802 x86_fstp (code, 0);
3803 if (ins->opcode == OP_FCGT) {
3804 unordered_check = code;
3805 x86_branch8 (code, X86_CC_P, 0, FALSE);
3806 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3807 x86_patch (unordered_check, code);
3808 } else {
3809 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3810 }
3811 break;
3812 }
3813 if (ins->dreg != X86_EAX)
3814 x86_push_reg (code, X86_EAX);
3815
3816 EMIT_FPCOMPARE(code);
3817 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3818 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3819 if (ins->opcode == OP_FCGT_UN) {
3820 guchar *is_not_zero_check, *end_jump;
3821 is_not_zero_check = code;
3822 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3823 end_jump = code;
3824 x86_jump8 (code, 0);
3825 x86_patch (is_not_zero_check, code);
3826 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3827
3828 x86_patch (end_jump, code);
3829 }
3830 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3831 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3832
3833 if (ins->dreg != X86_EAX)
3834 x86_pop_reg (code, X86_EAX);
3835 break;
3836 case OP_FCGE: {
3837 guchar *unordered_check;
3838 guchar *jump_to_end;
3839 if (cfg->opt & MONO_OPT_FCMOV) {
3840 /* zeroing the register at the start results in
3841 * shorter and faster code (we can also remove the widening op)
3842 */
3843 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3844 x86_fcomip (code, 1);
3845 x86_fstp (code, 0);
3846 unordered_check = code;
3847 x86_branch8 (code, X86_CC_P, 0, FALSE);
3848 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
3849 x86_patch (unordered_check, code);
3850 break;
3851 }
3852 if (ins->dreg != X86_EAX)
3853 x86_push_reg (code, X86_EAX);
3854
3855 EMIT_FPCOMPARE(code);
3856 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3857 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3858 unordered_check = code;
3859 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3860
3861 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3862 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
3863 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3864 jump_to_end = code;
3865 x86_jump8 (code, 0);
3866 x86_patch (unordered_check, code);
3867 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3868 x86_patch (jump_to_end, code);
3869
3870 if (ins->dreg != X86_EAX)
3871 x86_pop_reg (code, X86_EAX);
3872 break;
3873 }
3874 case OP_FBEQ:
3875 if (cfg->opt & MONO_OPT_FCMOV) {
3876 guchar *jump = code;
3877 x86_branch8 (code, X86_CC_P, 0, TRUE);
3878 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3879 x86_patch (jump, code);
3880 break;
3881 }
3882 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3883 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3884 break;
3885 case OP_FBNE_UN:
3886 /* Branch if C013 != 100 */
3887 if (cfg->opt & MONO_OPT_FCMOV) {
3888 /* branch if !ZF or (PF|CF) */
3889 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3890 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3891 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3892 break;
3893 }
3894 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3895 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3896 break;
3897 case OP_FBLT:
3898 if (cfg->opt & MONO_OPT_FCMOV) {
3899 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3900 break;
3901 }
3902 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3903 break;
3904 case OP_FBLT_UN:
3905 if (cfg->opt & MONO_OPT_FCMOV) {
3906 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3907 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3908 break;
3909 }
3910 if (ins->opcode == OP_FBLT_UN) {
3911 guchar *is_not_zero_check, *end_jump;
3912 is_not_zero_check = code;
3913 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3914 end_jump = code;
3915 x86_jump8 (code, 0);
3916 x86_patch (is_not_zero_check, code);
3917 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3918
3919 x86_patch (end_jump, code);
3920 }
3921 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3922 break;
3923 case OP_FBGT:
3924 case OP_FBGT_UN:
3925 if (cfg->opt & MONO_OPT_FCMOV) {
3926 if (ins->opcode == OP_FBGT) {
3927 guchar *br1;
3928
3929 /* skip branch if C1=1 */
3930 br1 = code;
3931 x86_branch8 (code, X86_CC_P, 0, FALSE);
3932 /* branch if (C0 | C3) = 1 */
3933 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3934 x86_patch (br1, code);
3935 } else {
3936 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3937 }
3938 break;
3939 }
3940 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3941 if (ins->opcode == OP_FBGT_UN) {
3942 guchar *is_not_zero_check, *end_jump;
3943 is_not_zero_check = code;
3944 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3945 end_jump = code;
3946 x86_jump8 (code, 0);
3947 x86_patch (is_not_zero_check, code);
3948 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3949
3950 x86_patch (end_jump, code);
3951 }
3952 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3953 break;
3954 case OP_FBGE:
3955 /* Branch if C013 == 100 or 001 */
3956 if (cfg->opt & MONO_OPT_FCMOV) {
3957 guchar *br1;
3958
3959 /* skip branch if C1=1 */
3960 br1 = code;
3961 x86_branch8 (code, X86_CC_P, 0, FALSE);
3962 /* branch if (C0 | C3) = 1 */
3963 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3964 x86_patch (br1, code);
3965 break;
3966 }
3967 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3968 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3969 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3970 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3971 break;
3972 case OP_FBGE_UN:
3973 /* Branch if C013 == 000 */
3974 if (cfg->opt & MONO_OPT_FCMOV) {
3975 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3976 break;
3977 }
3978 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3979 break;
3980 case OP_FBLE:
3981 /* Branch if C013=000 or 100 */
3982 if (cfg->opt & MONO_OPT_FCMOV) {
3983 guchar *br1;
3984
3985 /* skip branch if C1=1 */
3986 br1 = code;
3987 x86_branch8 (code, X86_CC_P, 0, FALSE);
3988 /* branch if C0=0 */
3989 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3990 x86_patch (br1, code);
3991 break;
3992 }
3993 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3994 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3995 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3996 break;
3997 case OP_FBLE_UN:
3998 /* Branch if C013 != 001 */
3999 if (cfg->opt & MONO_OPT_FCMOV) {
4000 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4001 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4002 break;
4003 }
4004 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4005 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4006 break;
4007 case OP_CKFINITE: {
4008 guchar *br1;
4009 x86_push_reg (code, X86_EAX);
4010 x86_fxam (code);
4011 x86_fnstsw (code);
4012 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4013 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4014 x86_pop_reg (code, X86_EAX);
4015
4016 /* Have to clean up the fp stack before throwing the exception */
4017 br1 = code;
4018 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4019
4020 x86_fstp (code, 0);
4021 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4022
4023 x86_patch (br1, code);
4024 break;
4025 }
4026 case OP_TLS_GET: {
4027 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4028 break;
4029 }
4030 case OP_TLS_SET: {
4031 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4032 break;
4033 }
4034 case OP_MEMORY_BARRIER: {
4035 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4036 x86_prefix (code, X86_LOCK_PREFIX);
4037 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4038 }
4039 break;
4040 }
4041 case OP_ATOMIC_ADD_I4: {
4042 int dreg = ins->dreg;
4043
4044 g_assert (cfg->has_atomic_add_i4);
4045
4046 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4047 if (ins->sreg2 == dreg) {
4048 if (dreg == X86_EBX) {
4049 dreg = X86_EDI;
4050 if (ins->inst_basereg == X86_EDI)
4051 dreg = X86_ESI;
4052 } else {
4053 dreg = X86_EBX;
4054 if (ins->inst_basereg == X86_EBX)
4055 dreg = X86_EDI;
4056 }
4057 } else if (ins->inst_basereg == dreg) {
4058 if (dreg == X86_EBX) {
4059 dreg = X86_EDI;
4060 if (ins->sreg2 == X86_EDI)
4061 dreg = X86_ESI;
4062 } else {
4063 dreg = X86_EBX;
4064 if (ins->sreg2 == X86_EBX)
4065 dreg = X86_EDI;
4066 }
4067 }
4068
4069 if (dreg != ins->dreg) {
4070 x86_push_reg (code, dreg);
4071 }
4072
4073 x86_mov_reg_reg (code, dreg, ins->sreg2);
4074 x86_prefix (code, X86_LOCK_PREFIX);
4075 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4076 /* dreg contains the old value, add with sreg2 value */
4077 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4078
4079 if (ins->dreg != dreg) {
4080 x86_mov_reg_reg (code, ins->dreg, dreg);
4081 x86_pop_reg (code, dreg);
4082 }
4083
4084 break;
4085 }
4086 case OP_ATOMIC_EXCHANGE_I4: {
4087 guchar *br[2];
4088 int sreg2 = ins->sreg2;
4089 int breg = ins->inst_basereg;
4090
4091 g_assert (cfg->has_atomic_exchange_i4);
4092
4093 /* cmpxchg uses eax as comperand, need to make sure we can use it
4094 * hack to overcome limits in x86 reg allocator
4095 * (req: dreg == eax and sreg2 != eax and breg != eax)
4096 */
4097 g_assert (ins->dreg == X86_EAX);
4098
4099 /* We need the EAX reg for the cmpxchg */
4100 if (ins->sreg2 == X86_EAX) {
4101 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4102 x86_push_reg (code, sreg2);
4103 x86_mov_reg_reg (code, sreg2, X86_EAX);
4104 }
4105
4106 if (breg == X86_EAX) {
4107 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4108 x86_push_reg (code, breg);
4109 x86_mov_reg_reg (code, breg, X86_EAX);
4110 }
4111
4112 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4113
4114 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4115 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4116 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4117 x86_patch (br [1], br [0]);
4118
4119 if (breg != ins->inst_basereg)
4120 x86_pop_reg (code, breg);
4121
4122 if (ins->sreg2 != sreg2)
4123 x86_pop_reg (code, sreg2);
4124
4125 break;
4126 }
4127 case OP_ATOMIC_CAS_I4: {
4128 g_assert (ins->dreg == X86_EAX);
4129 g_assert (ins->sreg3 == X86_EAX);
4130 g_assert (ins->sreg1 != X86_EAX);
4131 g_assert (ins->sreg1 != ins->sreg2);
4132
4133 x86_prefix (code, X86_LOCK_PREFIX);
4134 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4135 break;
4136 }
4137 case OP_ATOMIC_LOAD_I1: {
4138 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4139 break;
4140 }
4141 case OP_ATOMIC_LOAD_U1: {
4142 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4143 break;
4144 }
4145 case OP_ATOMIC_LOAD_I2: {
4146 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4147 break;
4148 }
4149 case OP_ATOMIC_LOAD_U2: {
4150 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4151 break;
4152 }
4153 case OP_ATOMIC_LOAD_I4:
4154 case OP_ATOMIC_LOAD_U4: {
4155 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4156 break;
4157 }
4158 case OP_ATOMIC_LOAD_R4:
4159 case OP_ATOMIC_LOAD_R8: {
4160 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4161 break;
4162 }
4163 case OP_ATOMIC_STORE_I1:
4164 case OP_ATOMIC_STORE_U1:
4165 case OP_ATOMIC_STORE_I2:
4166 case OP_ATOMIC_STORE_U2:
4167 case OP_ATOMIC_STORE_I4:
4168 case OP_ATOMIC_STORE_U4: {
4169 int size;
4170
4171 switch (ins->opcode) {
4172 case OP_ATOMIC_STORE_I1:
4173 case OP_ATOMIC_STORE_U1:
4174 size = 1;
4175 break;
4176 case OP_ATOMIC_STORE_I2:
4177 case OP_ATOMIC_STORE_U2:
4178 size = 2;
4179 break;
4180 case OP_ATOMIC_STORE_I4:
4181 case OP_ATOMIC_STORE_U4:
4182 size = 4;
4183 break;
4184 }
4185
4186 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4187
4188 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4189 x86_mfence (code);
4190 break;
4191 }
4192 case OP_ATOMIC_STORE_R4:
4193 case OP_ATOMIC_STORE_R8: {
4194 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4195
4196 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4197 x86_mfence (code);
4198 break;
4199 }
4200 case OP_CARD_TABLE_WBARRIER: {
4201 int ptr = ins->sreg1;
4202 int value = ins->sreg2;
4203 guchar *br = NULL;
4204 int nursery_shift, card_table_shift;
4205 gpointer card_table_mask;
4206 size_t nursery_size;
4207 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4208 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4209 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4210
4211 /*
4212 * We need one register we can clobber, we choose EDX and make sreg1
4213 * fixed EAX to work around limitations in the local register allocator.
4214 * sreg2 might get allocated to EDX, but that is not a problem since
4215 * we use it before clobbering EDX.
4216 */
4217 g_assert (ins->sreg1 == X86_EAX);
4218
4219 /*
4220 * This is the code we produce:
4221 *
4222 * edx = value
4223 * edx >>= nursery_shift
4224 * cmp edx, (nursery_start >> nursery_shift)
4225 * jne done
4226 * edx = ptr
4227 * edx >>= card_table_shift
4228 * card_table[edx] = 1
4229 * done:
4230 */
4231
4232 if (card_table_nursery_check) {
4233 if (value != X86_EDX)
4234 x86_mov_reg_reg (code, X86_EDX, value);
4235 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4236 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4237 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4238 }
4239 x86_mov_reg_reg (code, X86_EDX, ptr);
4240 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4241 if (card_table_mask)
4242 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4243 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4244 if (card_table_nursery_check)
4245 x86_patch (br, code);
4246 break;
4247 }
4248 #ifdef MONO_ARCH_SIMD_INTRINSICS
4249 case OP_ADDPS:
4250 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4251 break;
4252 case OP_DIVPS:
4253 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4254 break;
4255 case OP_MULPS:
4256 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4257 break;
4258 case OP_SUBPS:
4259 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4260 break;
4261 case OP_MAXPS:
4262 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4263 break;
4264 case OP_MINPS:
4265 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4266 break;
4267 case OP_COMPPS:
4268 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4269 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4270 break;
4271 case OP_ANDPS:
4272 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4273 break;
4274 case OP_ANDNPS:
4275 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4276 break;
4277 case OP_ORPS:
4278 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4279 break;
4280 case OP_XORPS:
4281 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4282 break;
4283 case OP_SQRTPS:
4284 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4285 break;
4286 case OP_RSQRTPS:
4287 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4288 break;
4289 case OP_RCPPS:
4290 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4291 break;
4292 case OP_ADDSUBPS:
4293 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4294 break;
4295 case OP_HADDPS:
4296 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4297 break;
4298 case OP_HSUBPS:
4299 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4300 break;
4301 case OP_DUPPS_HIGH:
4302 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4303 break;
4304 case OP_DUPPS_LOW:
4305 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4306 break;
4307
4308 case OP_PSHUFLEW_HIGH:
4309 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4310 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4311 break;
4312 case OP_PSHUFLEW_LOW:
4313 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4314 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4315 break;
4316 case OP_PSHUFLED:
4317 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4318 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4319 break;
4320 case OP_SHUFPS:
4321 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4322 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4323 break;
4324 case OP_SHUFPD:
4325 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4326 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4327 break;
4328
4329 case OP_ADDPD:
4330 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4331 break;
4332 case OP_DIVPD:
4333 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4334 break;
4335 case OP_MULPD:
4336 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4337 break;
4338 case OP_SUBPD:
4339 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4340 break;
4341 case OP_MAXPD:
4342 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4343 break;
4344 case OP_MINPD:
4345 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4346 break;
4347 case OP_COMPPD:
4348 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4349 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4350 break;
4351 case OP_ANDPD:
4352 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4353 break;
4354 case OP_ANDNPD:
4355 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4356 break;
4357 case OP_ORPD:
4358 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4359 break;
4360 case OP_XORPD:
4361 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4362 break;
4363 case OP_SQRTPD:
4364 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4365 break;
4366 case OP_ADDSUBPD:
4367 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4368 break;
4369 case OP_HADDPD:
4370 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4371 break;
4372 case OP_HSUBPD:
4373 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4374 break;
4375 case OP_DUPPD:
4376 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4377 break;
4378
4379 case OP_EXTRACT_MASK:
4380 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4381 break;
4382
4383 case OP_PAND:
4384 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4385 break;
4386 case OP_POR:
4387 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4388 break;
4389 case OP_PXOR:
4390 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4391 break;
4392
4393 case OP_PADDB:
4394 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4395 break;
4396 case OP_PADDW:
4397 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4398 break;
4399 case OP_PADDD:
4400 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4401 break;
4402 case OP_PADDQ:
4403 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4404 break;
4405
4406 case OP_PSUBB:
4407 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4408 break;
4409 case OP_PSUBW:
4410 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4411 break;
4412 case OP_PSUBD:
4413 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4414 break;
4415 case OP_PSUBQ:
4416 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4417 break;
4418
4419 case OP_PMAXB_UN:
4420 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4421 break;
4422 case OP_PMAXW_UN:
4423 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4424 break;
4425 case OP_PMAXD_UN:
4426 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4427 break;
4428
4429 case OP_PMAXB:
4430 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4431 break;
4432 case OP_PMAXW:
4433 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4434 break;
4435 case OP_PMAXD:
4436 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4437 break;
4438
4439 case OP_PAVGB_UN:
4440 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4441 break;
4442 case OP_PAVGW_UN:
4443 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4444 break;
4445
4446 case OP_PMINB_UN:
4447 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4448 break;
4449 case OP_PMINW_UN:
4450 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4451 break;
4452 case OP_PMIND_UN:
4453 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4454 break;
4455
4456 case OP_PMINB:
4457 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4458 break;
4459 case OP_PMINW:
4460 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4461 break;
4462 case OP_PMIND:
4463 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4464 break;
4465
4466 case OP_PCMPEQB:
4467 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4468 break;
4469 case OP_PCMPEQW:
4470 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4471 break;
4472 case OP_PCMPEQD:
4473 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4474 break;
4475 case OP_PCMPEQQ:
4476 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4477 break;
4478
4479 case OP_PCMPGTB:
4480 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4481 break;
4482 case OP_PCMPGTW:
4483 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4484 break;
4485 case OP_PCMPGTD:
4486 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4487 break;
4488 case OP_PCMPGTQ:
4489 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4490 break;
4491
4492 case OP_PSUM_ABS_DIFF:
4493 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4494 break;
4495
4496 case OP_UNPACK_LOWB:
4497 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4498 break;
4499 case OP_UNPACK_LOWW:
4500 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4501 break;
4502 case OP_UNPACK_LOWD:
4503 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4504 break;
4505 case OP_UNPACK_LOWQ:
4506 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4507 break;
4508 case OP_UNPACK_LOWPS:
4509 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4510 break;
4511 case OP_UNPACK_LOWPD:
4512 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4513 break;
4514
4515 case OP_UNPACK_HIGHB:
4516 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4517 break;
4518 case OP_UNPACK_HIGHW:
4519 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4520 break;
4521 case OP_UNPACK_HIGHD:
4522 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4523 break;
4524 case OP_UNPACK_HIGHQ:
4525 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4526 break;
4527 case OP_UNPACK_HIGHPS:
4528 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4529 break;
4530 case OP_UNPACK_HIGHPD:
4531 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4532 break;
4533
4534 case OP_PACKW:
4535 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4536 break;
4537 case OP_PACKD:
4538 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4539 break;
4540 case OP_PACKW_UN:
4541 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4542 break;
4543 case OP_PACKD_UN:
4544 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4545 break;
4546
4547 case OP_PADDB_SAT_UN:
4548 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4549 break;
4550 case OP_PSUBB_SAT_UN:
4551 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4552 break;
4553 case OP_PADDW_SAT_UN:
4554 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4555 break;
4556 case OP_PSUBW_SAT_UN:
4557 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4558 break;
4559
4560 case OP_PADDB_SAT:
4561 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4562 break;
4563 case OP_PSUBB_SAT:
4564 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4565 break;
4566 case OP_PADDW_SAT:
4567 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4568 break;
4569 case OP_PSUBW_SAT:
4570 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4571 break;
4572
4573 case OP_PMULW:
4574 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4575 break;
4576 case OP_PMULD:
4577 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4578 break;
4579 case OP_PMULQ:
4580 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4581 break;
4582 case OP_PMULW_HIGH_UN:
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4584 break;
4585 case OP_PMULW_HIGH:
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4587 break;
4588
4589 case OP_PSHRW:
4590 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4591 break;
4592 case OP_PSHRW_REG:
4593 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4594 break;
4595
4596 case OP_PSARW:
4597 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4598 break;
4599 case OP_PSARW_REG:
4600 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4601 break;
4602
4603 case OP_PSHLW:
4604 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4605 break;
4606 case OP_PSHLW_REG:
4607 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4608 break;
4609
4610 case OP_PSHRD:
4611 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4612 break;
4613 case OP_PSHRD_REG:
4614 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4615 break;
4616
4617 case OP_PSARD:
4618 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4619 break;
4620 case OP_PSARD_REG:
4621 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4622 break;
4623
4624 case OP_PSHLD:
4625 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4626 break;
4627 case OP_PSHLD_REG:
4628 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4629 break;
4630
4631 case OP_PSHRQ:
4632 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4633 break;
4634 case OP_PSHRQ_REG:
4635 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4636 break;
4637
4638 case OP_PSHLQ:
4639 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4640 break;
4641 case OP_PSHLQ_REG:
4642 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4643 break;
4644
4645 case OP_ICONV_TO_X:
4646 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4647 break;
4648 case OP_EXTRACT_I4:
4649 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4650 break;
4651 case OP_EXTRACT_I1:
4652 case OP_EXTRACT_U1:
4653 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4654 if (ins->inst_c0)
4655 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4656 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4657 break;
4658 case OP_EXTRACT_I2:
4659 case OP_EXTRACT_U2:
4660 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4661 if (ins->inst_c0)
4662 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4663 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4664 break;
4665 case OP_EXTRACT_R8:
4666 if (ins->inst_c0)
4667 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4668 else
4669 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4670 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4671 break;
4672
4673 case OP_INSERT_I2:
4674 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4675 break;
4676 case OP_EXTRACTX_U2:
4677 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4678 break;
4679 case OP_INSERTX_U1_SLOW:
4680 /*sreg1 is the extracted ireg (scratch)
4681 /sreg2 is the to be inserted ireg (scratch)
4682 /dreg is the xreg to receive the value*/
4683
4684 /*clear the bits from the extracted word*/
4685 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4686 /*shift the value to insert if needed*/
4687 if (ins->inst_c0 & 1)
4688 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4689 /*join them together*/
4690 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4691 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4692 break;
4693 case OP_INSERTX_I4_SLOW:
4694 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4695 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4696 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4697 break;
4698
4699 case OP_INSERTX_R4_SLOW:
4700 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4701 /*TODO if inst_c0 == 0 use movss*/
4702 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4703 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4704 break;
4705 case OP_INSERTX_R8_SLOW:
4706 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4707 if (cfg->verbose_level)
4708 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4709 if (ins->inst_c0)
4710 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4711 else
4712 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4713 break;
4714
4715 case OP_STOREX_MEMBASE_REG:
4716 case OP_STOREX_MEMBASE:
4717 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4718 break;
4719 case OP_LOADX_MEMBASE:
4720 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4721 break;
4722 case OP_LOADX_ALIGNED_MEMBASE:
4723 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4724 break;
4725 case OP_STOREX_ALIGNED_MEMBASE_REG:
4726 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4727 break;
4728 case OP_STOREX_NTA_MEMBASE_REG:
4729 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4730 break;
4731 case OP_PREFETCH_MEMBASE:
4732 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4733
4734 break;
4735 case OP_XMOVE:
4736 /*FIXME the peephole pass should have killed this*/
4737 if (ins->dreg != ins->sreg1)
4738 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4739 break;
4740 case OP_XZERO:
4741 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4742 break;
4743 case OP_XONES:
4744 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->dreg, ins->dreg);
4745 break;
4746
4747 case OP_FCONV_TO_R8_X:
4748 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4749 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4750 break;
4751
4752 case OP_XCONV_R8_TO_I4:
4753 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4754 switch (ins->backend.source_opcode) {
4755 case OP_FCONV_TO_I1:
4756 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4757 break;
4758 case OP_FCONV_TO_U1:
4759 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4760 break;
4761 case OP_FCONV_TO_I2:
4762 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4763 break;
4764 case OP_FCONV_TO_U2:
4765 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4766 break;
4767 }
4768 break;
4769
4770 case OP_EXPAND_I2:
4771 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4772 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4773 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4774 break;
4775 case OP_EXPAND_I4:
4776 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4777 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4778 break;
4779 case OP_EXPAND_R4:
4780 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4781 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4782 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4783 break;
4784 case OP_EXPAND_R8:
4785 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4786 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4787 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4788 break;
4789
4790 case OP_CVTDQ2PD:
4791 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4792 break;
4793 case OP_CVTDQ2PS:
4794 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4795 break;
4796 case OP_CVTPD2DQ:
4797 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4798 break;
4799 case OP_CVTPD2PS:
4800 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4801 break;
4802 case OP_CVTPS2DQ:
4803 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4804 break;
4805 case OP_CVTPS2PD:
4806 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4807 break;
4808 case OP_CVTTPD2DQ:
4809 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4810 break;
4811 case OP_CVTTPS2DQ:
4812 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4813 break;
4814
4815 #endif
4816 case OP_LIVERANGE_START: {
4817 if (cfg->verbose_level > 1)
4818 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4819 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4820 break;
4821 }
4822 case OP_LIVERANGE_END: {
4823 if (cfg->verbose_level > 1)
4824 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4825 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4826 break;
4827 }
4828 case OP_GC_SAFE_POINT: {
4829 guint8 *br [1];
4830
4831 x86_test_membase_imm (code, ins->sreg1, 0, 1);
4832 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4833 code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ID, GUINT_TO_POINTER (MONO_JIT_ICALL_mono_threads_state_poll));
4834 x86_patch (br [0], code);
4835
4836 break;
4837 }
4838 case OP_GC_LIVENESS_DEF:
4839 case OP_GC_LIVENESS_USE:
4840 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4841 ins->backend.pc_offset = code - cfg->native_code;
4842 break;
4843 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4844 ins->backend.pc_offset = code - cfg->native_code;
4845 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4846 break;
4847 case OP_GET_SP:
4848 x86_mov_reg_reg (code, ins->dreg, X86_ESP);
4849 break;
4850 case OP_SET_SP:
4851 x86_mov_reg_reg (code, X86_ESP, ins->sreg1);
4852 break;
4853 case OP_FILL_PROF_CALL_CTX:
4854 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esp), X86_ESP, sizeof (target_mgreg_t));
4855 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebp), X86_EBP, sizeof (target_mgreg_t));
4856 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebx), X86_EBX, sizeof (target_mgreg_t));
4857 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esi), X86_ESI, sizeof (target_mgreg_t));
4858 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, edi), X86_EDI, sizeof (target_mgreg_t));
4859 break;
4860 default:
4861 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4862 g_assert_not_reached ();
4863 }
4864
4865 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4866 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4867 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4868 g_assert_not_reached ();
4869 }
4870
4871 cpos += max_len;
4872 }
4873
4874 set_code_cursor (cfg, code);
4875 }
4876
4877 #endif /* DISABLE_JIT */
4878
4879 void
4880 mono_arch_register_lowlevel_calls (void)
4881 {
4882 }
4883
4884 void
4885 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
4886 {
4887 unsigned char *ip = ji->ip.i + code;
4888
4889 switch (ji->type) {
4890 case MONO_PATCH_INFO_IP:
4891 *((gconstpointer *)(ip)) = target;
4892 break;
4893 case MONO_PATCH_INFO_ABS:
4894 case MONO_PATCH_INFO_METHOD:
4895 case MONO_PATCH_INFO_METHOD_JUMP:
4896 case MONO_PATCH_INFO_JIT_ICALL_ID:
4897 case MONO_PATCH_INFO_BB:
4898 case MONO_PATCH_INFO_LABEL:
4899 case MONO_PATCH_INFO_RGCTX_FETCH:
4900 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
4901 case MONO_PATCH_INFO_TRAMPOLINE_FUNC_ADDR:
4902 case MONO_PATCH_INFO_SPECIFIC_TRAMPOLINE_LAZY_FETCH_ADDR:
4903 x86_patch (ip, (unsigned char*)target);
4904 break;
4905 case MONO_PATCH_INFO_NONE:
4906 break;
4907 case MONO_PATCH_INFO_R4:
4908 case MONO_PATCH_INFO_R8: {
4909 guint32 offset = mono_arch_get_patch_offset (ip);
4910 *((gconstpointer *)(ip + offset)) = target;
4911 break;
4912 }
4913 default: {
4914 guint32 offset = mono_arch_get_patch_offset (ip);
4915 *((gconstpointer *)(ip + offset)) = target;
4916 break;
4917 }
4918 }
4919 }
4920
4921 static G_GNUC_UNUSED void
4922 stack_unaligned (MonoMethod *m, gpointer caller)
4923 {
4924 printf ("%s\n", mono_method_full_name (m, TRUE));
4925 g_assert_not_reached ();
4926 }
4927
4928 guint8 *
4929 mono_arch_emit_prolog (MonoCompile *cfg)
4930 {
4931 MonoMethod *method = cfg->method;
4932 MonoBasicBlock *bb;
4933 MonoMethodSignature *sig;
4934 MonoInst *inst;
4935 CallInfo *cinfo;
4936 ArgInfo *ainfo;
4937 int alloc_size, pos, max_offset, i, cfa_offset;
4938 guint8 *code;
4939 gboolean need_stack_frame;
4940
4941 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
4942
4943 code = cfg->native_code = g_malloc (cfg->code_size);
4944
4945 #if 0
4946 {
4947 guint8 *br [16];
4948
4949 /* Check that the stack is aligned on osx */
4950 x86_mov_reg_reg (code, X86_EAX, X86_ESP);
4951 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
4952 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
4953 br [0] = code;
4954 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
4955 x86_push_membase (code, X86_ESP, 0);
4956 x86_push_imm (code, cfg->method);
4957 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
4958 x86_call_reg (code, X86_EAX);
4959 x86_patch (br [0], code);
4960 }
4961 #endif
4962
4963 /* Offset between RSP and the CFA */
4964 cfa_offset = 0;
4965
4966 // CFA = sp + 4
4967 cfa_offset = 4;
4968 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, cfa_offset);
4969 // IP saved at CFA - 4
4970 /* There is no IP reg on x86 */
4971 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4972 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
4973
4974 need_stack_frame = needs_stack_frame (cfg);
4975
4976 if (need_stack_frame) {
4977 x86_push_reg (code, X86_EBP);
4978 cfa_offset += 4;
4979 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4980 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4981 x86_mov_reg_reg (code, X86_EBP, X86_ESP);
4982 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4983 /* These are handled automatically by the stack marking code */
4984 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
4985 } else {
4986 cfg->frame_reg = X86_ESP;
4987 }
4988
4989 cfg->stack_offset += cfg->param_area;
4990 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4991
4992 alloc_size = cfg->stack_offset;
4993 pos = 0;
4994
4995 if (!method->save_lmf) {
4996 if (cfg->used_int_regs & (1 << X86_EBX)) {
4997 x86_push_reg (code, X86_EBX);
4998 pos += 4;
4999 cfa_offset += 4;
5000 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5001 /* These are handled automatically by the stack marking code */
5002 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5003 }
5004
5005 if (cfg->used_int_regs & (1 << X86_EDI)) {
5006 x86_push_reg (code, X86_EDI);
5007 pos += 4;
5008 cfa_offset += 4;
5009 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5010 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5011 }
5012
5013 if (cfg->used_int_regs & (1 << X86_ESI)) {
5014 x86_push_reg (code, X86_ESI);
5015 pos += 4;
5016 cfa_offset += 4;
5017 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5018 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5019 }
5020 }
5021
5022 alloc_size -= pos;
5023
5024 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5025 if (mono_do_x86_stack_align && need_stack_frame) {
5026 int tot = alloc_size + pos + 4; /* ret ip */
5027 if (need_stack_frame)
5028 tot += 4; /* ebp */
5029 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5030 if (tot) {
5031 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5032 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (target_mgreg_t))
5033 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5034 }
5035 }
5036
5037 cfg->arch.sp_fp_offset = alloc_size + pos;
5038
5039 if (alloc_size) {
5040 /* See mono_emit_stack_alloc */
5041 #if defined (TARGET_WIN32) || defined (MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5042 guint32 remaining_size = alloc_size;
5043 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5044 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5045 set_code_cursor (cfg, code);
5046 code = realloc_code (cfg, required_code_size);
5047 while (remaining_size >= 0x1000) {
5048 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5049 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5050 remaining_size -= 0x1000;
5051 }
5052 if (remaining_size)
5053 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5054 #else
5055 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5056 #endif
5057
5058 g_assert (need_stack_frame);
5059 }
5060
5061 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5062 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5063 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5064 }
5065
5066 #if DEBUG_STACK_ALIGNMENT
5067 /* check the stack is aligned */
5068 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5069 x86_mov_reg_reg (code, X86_ECX, X86_ESP);
5070 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5071 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5072 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5073 x86_breakpoint (code);
5074 }
5075 #endif
5076
5077 /* compute max_offset in order to use short forward jumps */
5078 max_offset = 0;
5079 if (cfg->opt & MONO_OPT_BRANCH) {
5080 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5081 MonoInst *ins;
5082 bb->max_offset = max_offset;
5083
5084 /* max alignment for loops */
5085 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5086 max_offset += LOOP_ALIGNMENT;
5087 MONO_BB_FOR_EACH_INS (bb, ins) {
5088 if (ins->opcode == OP_LABEL)
5089 ins->inst_c1 = max_offset;
5090 max_offset += ins_get_size (ins->opcode);
5091 }
5092 }
5093 }
5094
5095 /* store runtime generic context */
5096 if (cfg->rgctx_var) {
5097 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5098
5099 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5100 }
5101
5102 if (method->save_lmf)
5103 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5104
5105 {
5106 MonoInst *ins;
5107
5108 if (cfg->arch.ss_tramp_var) {
5109 /* Initialize ss_tramp_var */
5110 ins = cfg->arch.ss_tramp_var;
5111 g_assert (ins->opcode == OP_REGOFFSET);
5112
5113 g_assert (!cfg->compile_aot);
5114 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5115 }
5116
5117 if (cfg->arch.bp_tramp_var) {
5118 /* Initialize bp_tramp_var */
5119 ins = cfg->arch.bp_tramp_var;
5120 g_assert (ins->opcode == OP_REGOFFSET);
5121
5122 g_assert (!cfg->compile_aot);
5123 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5124 }
5125 }
5126
5127 /* load arguments allocated to register from the stack */
5128 sig = mono_method_signature_internal (method);
5129 pos = 0;
5130
5131 cinfo = cfg->arch.cinfo;
5132
5133 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5134 inst = cfg->args [pos];
5135 ainfo = &cinfo->args [pos];
5136 if (inst->opcode == OP_REGVAR) {
5137 if (storage_in_ireg (ainfo->storage)) {
5138 x86_mov_reg_reg (code, inst->dreg, ainfo->reg);
5139 } else {
5140 g_assert (need_stack_frame);
5141 x86_mov_reg_membase (code, inst->dreg, X86_EBP, ainfo->offset + ARGS_OFFSET, 4);
5142 }
5143 if (cfg->verbose_level > 2)
5144 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5145 } else {
5146 if (storage_in_ireg (ainfo->storage)) {
5147 x86_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, 4);
5148 }
5149 }
5150 pos++;
5151 }
5152
5153 set_code_cursor (cfg, code);
5154
5155 return code;
5156 }
5157
5158 void
5159 mono_arch_emit_epilog (MonoCompile *cfg)
5160 {
5161 MonoMethod *method = cfg->method;
5162 MonoMethodSignature *sig = mono_method_signature_internal (method);
5163 int i, quad, pos;
5164 guint32 stack_to_pop;
5165 guint8 *code;
5166 int max_epilog_size = 16;
5167 CallInfo *cinfo;
5168 gboolean need_stack_frame = needs_stack_frame (cfg);
5169
5170 if (cfg->method->save_lmf)
5171 max_epilog_size += 128;
5172
5173 code = realloc_code (cfg, max_epilog_size);
5174
5175 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5176 pos = 0;
5177
5178 if (method->save_lmf) {
5179 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5180
5181 /* restore caller saved regs */
5182 if (cfg->used_int_regs & (1 << X86_EBX)) {
5183 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5184 }
5185
5186 if (cfg->used_int_regs & (1 << X86_EDI)) {
5187 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5188 }
5189 if (cfg->used_int_regs & (1 << X86_ESI)) {
5190 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5191 }
5192
5193 /* EBP is restored by LEAVE */
5194 } else {
5195 for (i = 0; i < X86_NREG; ++i) {
5196 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5197 pos -= 4;
5198 }
5199 }
5200
5201 g_assert (!pos || need_stack_frame);
5202 if (pos) {
5203 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5204 }
5205
5206 if (cfg->used_int_regs & (1 << X86_ESI)) {
5207 x86_pop_reg (code, X86_ESI);
5208 }
5209 if (cfg->used_int_regs & (1 << X86_EDI)) {
5210 x86_pop_reg (code, X86_EDI);
5211 }
5212 if (cfg->used_int_regs & (1 << X86_EBX)) {
5213 x86_pop_reg (code, X86_EBX);
5214 }
5215 }
5216
5217 /* Load returned vtypes into registers if needed */
5218 cinfo = cfg->arch.cinfo;
5219 if (cinfo->ret.storage == ArgValuetypeInReg) {
5220 for (quad = 0; quad < 2; quad ++) {
5221 switch (cinfo->ret.pair_storage [quad]) {
5222 case ArgInIReg:
5223 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), 4);
5224 break;
5225 case ArgOnFloatFpStack:
5226 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), FALSE);
5227 break;
5228 case ArgOnDoubleFpStack:
5229 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (target_mgreg_t)), TRUE);
5230 break;
5231 case ArgNone:
5232 break;
5233 default:
5234 g_assert_not_reached ();
5235 }
5236 }
5237 }
5238
5239 if (need_stack_frame)
5240 x86_leave (code);
5241
5242 if (CALLCONV_IS_STDCALL (sig)) {
5243 MonoJitArgumentInfo *arg_info = g_newa (MonoJitArgumentInfo, sig->param_count + 1);
5244
5245 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5246 } else if (cinfo->callee_stack_pop)
5247 stack_to_pop = cinfo->callee_stack_pop;
5248 else
5249 stack_to_pop = 0;
5250
5251 if (stack_to_pop) {
5252 g_assert (need_stack_frame);
5253 x86_ret_imm (code, stack_to_pop);
5254 } else {
5255 x86_ret (code);
5256 }
5257
5258 set_code_cursor (cfg, code);
5259 }
5260
5261 void
5262 mono_arch_emit_exceptions (MonoCompile *cfg)
5263 {
5264 MonoJumpInfo *patch_info;
5265 int nthrows, i;
5266 guint8 *code;
5267 MonoClass *exc_classes [16];
5268 guint8 *exc_throw_start [16], *exc_throw_end [16];
5269 guint32 code_size;
5270 int exc_count = 0;
5271
5272 /* Compute needed space */
5273 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5274 if (patch_info->type == MONO_PATCH_INFO_EXC)
5275 exc_count++;
5276 }
5277
5278 /*
5279 * make sure we have enough space for exceptions
5280 * 16 is the size of two push_imm instructions and a call
5281 */
5282 if (cfg->compile_aot)
5283 code_size = exc_count * 32;
5284 else
5285 code_size = exc_count * 16;
5286
5287 code = realloc_code (cfg, code_size);
5288
5289 nthrows = 0;
5290 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5291 switch (patch_info->type) {
5292 case MONO_PATCH_INFO_EXC: {
5293 MonoClass *exc_class;
5294 guint8 *buf, *buf2;
5295 guint32 throw_ip;
5296
5297 x86_patch (patch_info->ip.i + cfg->native_code, code);
5298
5299 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5300 throw_ip = patch_info->ip.i;
5301
5302 /* Find a throw sequence for the same exception class */
5303 for (i = 0; i < nthrows; ++i)
5304 if (exc_classes [i] == exc_class)
5305 break;
5306 if (i < nthrows) {
5307 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5308 x86_jump_code (code, exc_throw_start [i]);
5309 patch_info->type = MONO_PATCH_INFO_NONE;
5310 }
5311 else {
5312 guint32 size;
5313
5314 /* Compute size of code following the push <OFFSET> */
5315 size = 5 + 5;
5316
5317 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5318
5319 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5320 /* Use the shorter form */
5321 buf = buf2 = code;
5322 x86_push_imm (code, 0);
5323 }
5324 else {
5325 buf = code;
5326 x86_push_imm (code, 0xf0f0f0f0);
5327 buf2 = code;
5328 }
5329
5330 if (nthrows < 16) {
5331 exc_classes [nthrows] = exc_class;
5332 exc_throw_start [nthrows] = code;
5333 }
5334
5335 x86_push_imm (code, m_class_get_type_token (exc_class) - MONO_TOKEN_TYPE_DEF);
5336 patch_info->data.jit_icall_id = MONO_JIT_ICALL_mono_arch_throw_corlib_exception;
5337 patch_info->type = MONO_PATCH_INFO_JIT_ICALL_ID;
5338 patch_info->ip.i = code - cfg->native_code;
5339 x86_call_code (code, 0);
5340 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5341 while (buf < buf2)
5342 x86_nop (buf);
5343
5344 if (nthrows < 16) {
5345 exc_throw_end [nthrows] = code;
5346 nthrows ++;
5347 }
5348 }
5349 break;
5350 }
5351 default:
5352 /* do nothing */
5353 break;
5354 }
5355 set_code_cursor (cfg, code);
5356 }
5357 set_code_cursor (cfg, code);
5358 }
5359
5360 MONO_NEVER_INLINE
5361 void
5362 mono_arch_flush_icache (guint8 *code, gint size)
5363 {
5364 /* call/ret required (or likely other control transfer) */
5365 }
5366
5367 void
5368 mono_arch_flush_register_windows (void)
5369 {
5370 }
5371
5372 gboolean
5373 mono_arch_is_inst_imm (int opcode, int imm_opcode, gint64 imm)
5374 {
5375 return TRUE;
5376 }
5377
5378 void
5379 mono_arch_finish_init (void)
5380 {
5381 char *mono_no_tls = g_getenv ("MONO_NO_TLS");
5382 if (!mono_no_tls) {
5383 #ifndef TARGET_WIN32
5384 #if MONO_XEN_OPT
5385 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5386 #endif
5387 #endif
5388 } else {
5389 g_free (mono_no_tls);
5390 }
5391 }
5392
5393 void
5394 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5395 {
5396 }
5397
5398 // Linear handler, the bsearch head compare is shorter
5399 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5400 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5401 // x86_patch(ins,target)
5402 //[1 + 5] x86_jump_mem(inst,mem)
5403
5404 #define CMP_SIZE 6
5405 #define BR_SMALL_SIZE 2
5406 #define BR_LARGE_SIZE 5
5407 #define JUMP_IMM_SIZE 6
5408 #define ENABLE_WRONG_METHOD_CHECK 0
5409 #define DEBUG_IMT 0
5410
5411 static int
5412 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5413 {
5414 int i, distance = 0;
5415 for (i = start; i < target; ++i)
5416 distance += imt_entries [i]->chunk_size;
5417 return distance;
5418 }
5419
5420 /*
5421 * LOCKING: called with the domain lock held
5422 */
5423 gpointer
5424 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5425 gpointer fail_tramp)
5426 {
5427 int i;
5428 int size = 0;
5429 guint8 *code, *start;
5430 GSList *unwind_ops;
5431
5432 for (i = 0; i < count; ++i) {
5433 MonoIMTCheckItem *item = imt_entries [i];
5434 if (item->is_equals) {
5435 if (item->check_target_idx) {
5436 if (!item->compare_done)
5437 item->chunk_size += CMP_SIZE;
5438 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5439 } else {
5440 if (fail_tramp) {
5441 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5442 } else {
5443 item->chunk_size += JUMP_IMM_SIZE;
5444 #if ENABLE_WRONG_METHOD_CHECK
5445 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5446 #endif
5447 }
5448 }
5449 } else {
5450 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5451 imt_entries [item->check_target_idx]->compare_done = TRUE;
5452 }
5453 size += item->chunk_size;
5454 }
5455 if (fail_tramp)
5456 code = (guint8*)mono_method_alloc_generic_virtual_trampoline (domain, size);
5457 else
5458 code = mono_domain_code_reserve (domain, size);
5459 start = code;
5460
5461 unwind_ops = mono_arch_get_cie_program ();
5462
5463 for (i = 0; i < count; ++i) {
5464 MonoIMTCheckItem *item = imt_entries [i];
5465 item->code_target = code;
5466 if (item->is_equals) {
5467 if (item->check_target_idx) {
5468 if (!item->compare_done)
5469 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5470 item->jmp_code = code;
5471 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5472 if (item->has_target_code)
5473 x86_jump_code (code, item->value.target_code);
5474 else
5475 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5476 } else {
5477 if (fail_tramp) {
5478 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5479 item->jmp_code = code;
5480 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5481 if (item->has_target_code)
5482 x86_jump_code (code, item->value.target_code);
5483 else
5484 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5485 x86_patch (item->jmp_code, code);
5486 x86_jump_code (code, fail_tramp);
5487 item->jmp_code = NULL;
5488 } else {
5489 /* enable the commented code to assert on wrong method */
5490 #if ENABLE_WRONG_METHOD_CHECK
5491 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5492 item->jmp_code = code;
5493 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5494 #endif
5495 if (item->has_target_code)
5496 x86_jump_code (code, item->value.target_code);
5497 else
5498 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5499 #if ENABLE_WRONG_METHOD_CHECK
5500 x86_patch (item->jmp_code, code);
5501 x86_breakpoint (code);
5502 item->jmp_code = NULL;
5503 #endif
5504 }
5505 }
5506 } else {
5507 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5508 item->jmp_code = code;
5509 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5510 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5511 else
5512 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5513 }
5514 }
5515 /* patch the branches to get to the target items */
5516 for (i = 0; i < count; ++i) {
5517 MonoIMTCheckItem *item = imt_entries [i];
5518 if (item->jmp_code) {
5519 if (item->check_target_idx) {
5520 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5521 }
5522 }
5523 }
5524
5525 if (!fail_tramp)
5526 UnlockedAdd (&mono_stats.imt_trampolines_size, code - start);
5527 g_assert (code - start <= size);
5528
5529 #if DEBUG_IMT
5530 {
5531 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", m_class_get_name_space (vtable->klass), m_class_get_name (vtable->klass), count);
5532 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5533 g_free (buff);
5534 }
5535 #endif
5536 if (mono_jit_map_is_enabled ()) {
5537 char *buff;
5538 if (vtable)
5539 buff = g_strdup_printf ("imt_%s_%s_entries_%d", m_class_get_name_space (vtable->klass), m_class_get_name (vtable->klass), count);
5540 else
5541 buff = g_strdup_printf ("imt_trampoline_entries_%d", count);
5542 mono_emit_jit_tramp (start, code - start, buff);
5543 g_free (buff);
5544 }
5545
5546 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
5547
5548 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5549
5550 return start;
5551 }
5552
5553 MonoMethod*
5554 mono_arch_find_imt_method (host_mgreg_t *regs, guint8 *code)
5555 {
5556 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5557 }
5558
5559 MonoVTable*
5560 mono_arch_find_static_call_vtable (host_mgreg_t *regs, guint8 *code)
5561 {
5562 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5563 }
5564
5565 GSList*
5566 mono_arch_get_cie_program (void)
5567 {
5568 GSList *l = NULL;
5569
5570 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5571 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5572
5573 return l;
5574 }
5575
5576 MonoInst*
5577 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5578 {
5579 MonoInst *ins = NULL;
5580 int opcode = 0;
5581
5582 if (cmethod->klass == mono_class_try_get_math_class ()) {
5583 if (strcmp (cmethod->name, "Sin") == 0) {
5584 opcode = OP_SIN;
5585 } else if (strcmp (cmethod->name, "Cos") == 0) {
5586 opcode = OP_COS;
5587 } else if (strcmp (cmethod->name, "Tan") == 0) {
5588 opcode = OP_TAN;
5589 } else if (strcmp (cmethod->name, "Atan") == 0) {
5590 opcode = OP_ATAN;
5591 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5592 opcode = OP_SQRT;
5593 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5594 opcode = OP_ABS;
5595 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5596 opcode = OP_ROUND;
5597 }
5598
5599 if (opcode && fsig->param_count == 1) {
5600 MONO_INST_NEW (cfg, ins, opcode);
5601 ins->type = STACK_R8;
5602 ins->dreg = mono_alloc_freg (cfg);
5603 ins->sreg1 = args [0]->dreg;
5604 MONO_ADD_INS (cfg->cbb, ins);
5605 }
5606
5607 if (cfg->opt & MONO_OPT_CMOV) {
5608 opcode = 0;
5609
5610 if (strcmp (cmethod->name, "Min") == 0) {
5611 if (fsig->params [0]->type == MONO_TYPE_I4)
5612 opcode = OP_IMIN;
5613 } else if (strcmp (cmethod->name, "Max") == 0) {
5614 if (fsig->params [0]->type == MONO_TYPE_I4)
5615 opcode = OP_IMAX;
5616 }
5617
5618 if (opcode && fsig->param_count == 2) {
5619 MONO_INST_NEW (cfg, ins, opcode);
5620 ins->type = STACK_I4;
5621 ins->dreg = mono_alloc_ireg (cfg);
5622 ins->sreg1 = args [0]->dreg;
5623 ins->sreg2 = args [1]->dreg;
5624 MONO_ADD_INS (cfg->cbb, ins);
5625 }
5626 }
5627
5628 #if 0
5629 /* OP_FREM is not IEEE compatible */
5630 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5631 MONO_INST_NEW (cfg, ins, OP_FREM);
5632 ins->inst_i0 = args [0];
5633 ins->inst_i1 = args [1];
5634 }
5635 #endif
5636 }
5637
5638 return ins;
5639 }
5640
5641 guint32
5642 mono_arch_get_patch_offset (guint8 *code)
5643 {
5644 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5645 return 2;
5646 else if (code [0] == 0xba)
5647 return 1;
5648 else if (code [0] == 0x68)
5649 /* push IMM */
5650 return 1;
5651 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5652 /* push <OFFSET>(<REG>) */
5653 return 2;
5654 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5655 /* call *<OFFSET>(<REG>) */
5656 return 2;
5657 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5658 /* fldl <ADDR> */
5659 return 2;
5660 else if ((code [0] == 0x58) && (code [1] == 0x05))
5661 /* pop %eax; add <OFFSET>, %eax */
5662 return 2;
5663 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5664 /* pop <REG>; add <OFFSET>, <REG> */
5665 return 3;
5666 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5667 /* mov <REG>, imm */
5668 return 1;
5669 else if (code [0] == 0xE9)
5670 /* jmp eip+32b */
5671 return 1;
5672 g_assert_not_reached ();
5673 return -1;
5674 }
5675
5676 /**
5677 * \return TRUE if no sw breakpoint was present.
5678 *
5679 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
5680 * breakpoints in the original code, they are removed in the copy.
5681 */
5682 gboolean
5683 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5684 {
5685 /*
5686 * If method_start is non-NULL we need to perform bound checks, since we access memory
5687 * at code - offset we could go before the start of the method and end up in a different
5688 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5689 * instead.
5690 */
5691 if (!method_start || code - offset >= method_start) {
5692 memcpy (buf, code - offset, size);
5693 } else {
5694 int diff = code - method_start;
5695 memset (buf, 0, size);
5696 memcpy (buf + offset - diff, method_start, diff + size - offset);
5697 }
5698 return TRUE;
5699 }
5700
5701 /*
5702 * mono_x86_get_this_arg_offset:
5703 *
5704 * Return the offset of the stack location where this is passed during a virtual
5705 * call.
5706 */
5707 guint32
5708 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
5709 {
5710 return 0;
5711 }
5712
5713 gpointer
5714 mono_arch_get_this_arg_from_call (host_mgreg_t *regs, guint8 *code)
5715 {
5716 host_mgreg_t esp = regs [X86_ESP];
5717 gpointer res;
5718 int offset;
5719
5720 offset = 0;
5721
5722 /*
5723 * The stack looks like:
5724 * <other args>
5725 * <this=delegate>
5726 */
5727 res = ((MonoObject**)esp) [0];
5728 return res;
5729 }
5730
5731 #define MAX_ARCH_DELEGATE_PARAMS 10
5732
5733 static gpointer
5734 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
5735 {
5736 guint8 *code, *start;
5737 int code_reserve = 64;
5738 GSList *unwind_ops;
5739
5740 unwind_ops = mono_arch_get_cie_program ();
5741
5742 /*
5743 * The stack contains:
5744 * <delegate>
5745 * <return addr>
5746 */
5747
5748 if (has_target) {
5749 start = code = mono_global_codeman_reserve (code_reserve);
5750
5751 /* Replace the this argument with the target */
5752 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5753 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5754 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5755 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5756
5757 g_assert ((code - start) < code_reserve);
5758 } else {
5759 int i = 0;
5760 /* 8 for mov_reg and jump, plus 8 for each parameter */
5761 code_reserve = 8 + (param_count * 8);
5762 /*
5763 * The stack contains:
5764 * <args in reverse order>
5765 * <delegate>
5766 * <return addr>
5767 *
5768 * and we need:
5769 * <args in reverse order>
5770 * <return addr>
5771 *
5772 * without unbalancing the stack.
5773 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5774 * and leaving original spot of first arg as placeholder in stack so
5775 * when callee pops stack everything works.
5776 */
5777
5778 start = code = mono_global_codeman_reserve (code_reserve);
5779
5780 /* store delegate for access to method_ptr */
5781 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5782
5783 /* move args up */
5784 for (i = 0; i < param_count; ++i) {
5785 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5786 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5787 }
5788
5789 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5790
5791 g_assert ((code - start) < code_reserve);
5792 }
5793
5794 if (has_target) {
5795 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
5796 } else {
5797 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
5798 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
5799 g_free (name);
5800 }
5801
5802 if (mono_jit_map_is_enabled ()) {
5803 char *buff;
5804 if (has_target)
5805 buff = (char*)"delegate_invoke_has_target";
5806 else
5807 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
5808 mono_emit_jit_tramp (start, code - start, buff);
5809 if (!has_target)
5810 g_free (buff);
5811 }
5812 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5813
5814 return start;
5815 }
5816
5817 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
5818
5819 static gpointer
5820 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
5821 {
5822 guint8 *code, *start;
5823 int size = 24;
5824 char *tramp_name;
5825 GSList *unwind_ops;
5826
5827 if (offset / (int)sizeof (target_mgreg_t) > MAX_VIRTUAL_DELEGATE_OFFSET)
5828 return NULL;
5829
5830 /*
5831 * The stack contains:
5832 * <delegate>
5833 * <return addr>
5834 */
5835 start = code = mono_global_codeman_reserve (size);
5836
5837 unwind_ops = mono_arch_get_cie_program ();
5838
5839 /* Replace the this argument with the target */
5840 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5841 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5842 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5843
5844 if (load_imt_reg) {
5845 /* Load the IMT reg */
5846 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
5847 }
5848
5849 /* Load the vtable */
5850 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
5851 x86_jump_membase (code, X86_EAX, offset);
5852 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5853
5854 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
5855 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
5856 g_free (tramp_name);
5857
5858
5859 return start;
5860 }
5861
5862 GSList*
5863 mono_arch_get_delegate_invoke_impls (void)
5864 {
5865 GSList *res = NULL;
5866 MonoTrampInfo *info;
5867 int i;
5868
5869 get_delegate_invoke_impl (&info, TRUE, 0);
5870 res = g_slist_prepend (res, info);
5871
5872 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
5873 get_delegate_invoke_impl (&info, FALSE, i);
5874 res = g_slist_prepend (res, info);
5875 }
5876
5877 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
5878 get_delegate_virtual_invoke_impl (&info, TRUE, - i * TARGET_SIZEOF_VOID_P);
5879 res = g_slist_prepend (res, info);
5880
5881 get_delegate_virtual_invoke_impl (&info, FALSE, i * TARGET_SIZEOF_VOID_P);
5882 res = g_slist_prepend (res, info);
5883 }
5884
5885 return res;
5886 }
5887
5888 gpointer
5889 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5890 {
5891 guint8 *code, *start;
5892
5893 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5894 return NULL;
5895
5896 /* FIXME: Support more cases */
5897 if (MONO_TYPE_ISSTRUCT (sig->ret))
5898 return NULL;
5899
5900 /*
5901 * The stack contains:
5902 * <delegate>
5903 * <return addr>
5904 */
5905
5906 if (has_target) {
5907 static guint8* cached = NULL;
5908 if (cached)
5909 return cached;
5910
5911 if (mono_ee_features.use_aot_trampolines) {
5912 start = (guint8*)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
5913 } else {
5914 MonoTrampInfo *info;
5915 start = (guint8*)get_delegate_invoke_impl (&info, TRUE, 0);
5916 mono_tramp_info_register (info, NULL);
5917 }
5918
5919 mono_memory_barrier ();
5920
5921 cached = start;
5922 } else {
5923 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5924 int i = 0;
5925
5926 for (i = 0; i < sig->param_count; ++i)
5927 if (!mono_is_regsize_var (sig->params [i]))
5928 return NULL;
5929
5930 code = cache [sig->param_count];
5931 if (code)
5932 return code;
5933
5934 if (mono_ee_features.use_aot_trampolines) {
5935 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
5936 start = (guint8*)mono_aot_get_trampoline (name);
5937 g_free (name);
5938 } else {
5939 MonoTrampInfo *info;
5940 start = (guint8*)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
5941 mono_tramp_info_register (info, NULL);
5942 }
5943
5944 mono_memory_barrier ();
5945
5946 cache [sig->param_count] = start;
5947 }
5948
5949 return start;
5950 }
5951
5952 gpointer
5953 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
5954 {
5955 MonoTrampInfo *info;
5956 gpointer code;
5957
5958 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
5959 if (code)
5960 mono_tramp_info_register (info, NULL);
5961 return code;
5962 }
5963
5964 host_mgreg_t
5965 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5966 {
5967 switch (reg) {
5968 case X86_EAX: return ctx->eax;
5969 case X86_EBX: return ctx->ebx;
5970 case X86_ECX: return ctx->ecx;
5971 case X86_EDX: return ctx->edx;
5972 case X86_ESP: return ctx->esp;
5973 case X86_EBP: return ctx->ebp;
5974 case X86_ESI: return ctx->esi;
5975 case X86_EDI: return ctx->edi;
5976 default:
5977 g_assert_not_reached ();
5978 return 0;
5979 }
5980 }
5981
5982 void
5983 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, host_mgreg_t val)
5984 {
5985 switch (reg) {
5986 case X86_EAX:
5987 ctx->eax = val;
5988 break;
5989 case X86_EBX:
5990 ctx->ebx = val;
5991 break;
5992 case X86_ECX:
5993 ctx->ecx = val;
5994 break;
5995 case X86_EDX:
5996 ctx->edx = val;
5997 break;
5998 case X86_ESP:
5999 ctx->esp = val;
6000 break;
6001 case X86_EBP:
6002 ctx->ebp = val;
6003 break;
6004 case X86_ESI:
6005 ctx->esi = val;
6006 break;
6007 case X86_EDI:
6008 ctx->edi = val;
6009 break;
6010 default:
6011 g_assert_not_reached ();
6012 }
6013 }
6014
6015 #ifdef MONO_ARCH_SIMD_INTRINSICS
6016
6017 static MonoInst*
6018 get_float_to_x_spill_area (MonoCompile *cfg)
6019 {
6020 if (!cfg->fconv_to_r8_x_var) {
6021 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, m_class_get_byval_arg (mono_defaults.double_class), OP_LOCAL);
6022 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6023 }
6024 return cfg->fconv_to_r8_x_var;
6025 }
6026
6027 /*
6028 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6029 */
6030 void
6031 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6032 {
6033 MonoInst *fconv;
6034 int dreg, src_opcode;
6035
6036 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6037 return;
6038
6039 switch (src_opcode = ins->opcode) {
6040 case OP_FCONV_TO_I1:
6041 case OP_FCONV_TO_U1:
6042 case OP_FCONV_TO_I2:
6043 case OP_FCONV_TO_U2:
6044 case OP_FCONV_TO_I4:
6045 case OP_FCONV_TO_I:
6046 break;
6047 default:
6048 return;
6049 }
6050
6051 /* dreg is the IREG and sreg1 is the FREG */
6052 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6053 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6054 fconv->sreg1 = ins->sreg1;
6055 fconv->dreg = mono_alloc_ireg (cfg);
6056 fconv->type = STACK_VTYPE;
6057 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6058
6059 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6060
6061 dreg = ins->dreg;
6062 NULLIFY_INS (ins);
6063 ins->opcode = OP_XCONV_R8_TO_I4;
6064
6065 ins->klass = mono_defaults.int32_class;
6066 ins->sreg1 = fconv->dreg;
6067 ins->dreg = dreg;
6068 ins->type = STACK_I4;
6069 ins->backend.source_opcode = src_opcode;
6070 }
6071
6072 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6073
6074 void
6075 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6076 {
6077 MonoInst *ins;
6078 int vreg;
6079
6080 if (long_ins->opcode == OP_LNEG) {
6081 ins = long_ins;
6082 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6083 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6084 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6085 NULLIFY_INS (ins);
6086 return;
6087 }
6088
6089 #ifdef MONO_ARCH_SIMD_INTRINSICS
6090
6091 if (!(cfg->opt & MONO_OPT_SIMD))
6092 return;
6093
6094 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6095 switch (long_ins->opcode) {
6096 case OP_EXTRACT_I8:
6097 vreg = long_ins->sreg1;
6098
6099 if (long_ins->inst_c0) {
6100 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6101 ins->klass = long_ins->klass;
6102 ins->sreg1 = long_ins->sreg1;
6103 ins->inst_c0 = 2;
6104 ins->type = STACK_VTYPE;
6105 ins->dreg = vreg = alloc_ireg (cfg);
6106 MONO_ADD_INS (cfg->cbb, ins);
6107 }
6108
6109 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6110 ins->klass = mono_defaults.int32_class;
6111 ins->sreg1 = vreg;
6112 ins->type = STACK_I4;
6113 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6114 MONO_ADD_INS (cfg->cbb, ins);
6115
6116 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6117 ins->klass = long_ins->klass;
6118 ins->sreg1 = long_ins->sreg1;
6119 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6120 ins->type = STACK_VTYPE;
6121 ins->dreg = vreg = alloc_ireg (cfg);
6122 MONO_ADD_INS (cfg->cbb, ins);
6123
6124 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6125 ins->klass = mono_defaults.int32_class;
6126 ins->sreg1 = vreg;
6127 ins->type = STACK_I4;
6128 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6129 MONO_ADD_INS (cfg->cbb, ins);
6130
6131 long_ins->opcode = OP_NOP;
6132 break;
6133 case OP_INSERTX_I8_SLOW:
6134 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6135 ins->dreg = long_ins->dreg;
6136 ins->sreg1 = long_ins->dreg;
6137 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6138 ins->inst_c0 = long_ins->inst_c0 * 2;
6139 MONO_ADD_INS (cfg->cbb, ins);
6140
6141 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6142 ins->dreg = long_ins->dreg;
6143 ins->sreg1 = long_ins->dreg;
6144 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6145 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6146 MONO_ADD_INS (cfg->cbb, ins);
6147
6148 long_ins->opcode = OP_NOP;
6149 break;
6150 case OP_EXPAND_I8:
6151 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6152 ins->dreg = long_ins->dreg;
6153 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6154 ins->klass = long_ins->klass;
6155 ins->type = STACK_VTYPE;
6156 MONO_ADD_INS (cfg->cbb, ins);
6157
6158 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6159 ins->dreg = long_ins->dreg;
6160 ins->sreg1 = long_ins->dreg;
6161 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6162 ins->inst_c0 = 1;
6163 ins->klass = long_ins->klass;
6164 ins->type = STACK_VTYPE;
6165 MONO_ADD_INS (cfg->cbb, ins);
6166
6167 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6168 ins->dreg = long_ins->dreg;
6169 ins->sreg1 = long_ins->dreg;
6170 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6171 ins->klass = long_ins->klass;
6172 ins->type = STACK_VTYPE;
6173 MONO_ADD_INS (cfg->cbb, ins);
6174
6175 long_ins->opcode = OP_NOP;
6176 break;
6177 }
6178 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6179 }
6180
6181 /*
6182 * mono_aot_emit_load_got_addr:
6183 *
6184 * Emit code to load the got address.
6185 * On x86, the result is placed into EBX.
6186 */
6187 guint8*
6188 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6189 {
6190 x86_call_imm (code, 0);
6191 /*
6192 * The patch needs to point to the pop, since the GOT offset needs
6193 * to be added to that address.
6194 */
6195 if (cfg)
6196 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6197 else
6198 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6199 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6200 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6201
6202 set_code_cursor (cfg, code);
6203 return code;
6204 }
6205
6206 /*
6207 * mono_arch_emit_load_aotconst:
6208 *
6209 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6210 * TARGET from the mscorlib GOT in full-aot code.
6211 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6212 * EAX.
6213 */
6214 guint8*
6215 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6216 {
6217 /* Load the mscorlib got address */
6218 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (target_mgreg_t), 4);
6219 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6220 /* arch_emit_got_access () patches this */
6221 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6222
6223 return code;
6224 }
6225
6226 /* Can't put this into mini-x86.h */
6227 gpointer
6228 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6229
6230 GSList *
6231 mono_arch_get_trampolines (gboolean aot)
6232 {
6233 MonoTrampInfo *info;
6234 GSList *tramps = NULL;
6235
6236 mono_x86_get_signal_exception_trampoline (&info, aot);
6237
6238 tramps = g_slist_append (tramps, info);
6239
6240 return tramps;
6241 }
6242
6243 /* Soft Debug support */
6244 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6245
6246 /*
6247 * mono_arch_set_breakpoint:
6248 *
6249 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6250 * The location should contain code emitted by OP_SEQ_POINT.
6251 */
6252 void
6253 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6254 {
6255 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6256
6257 g_assert (code [0] == 0x90);
6258 x86_call_membase (code, X86_ECX, 0);
6259 }
6260
6261 /*
6262 * mono_arch_clear_breakpoint:
6263 *
6264 * Clear the breakpoint at IP.
6265 */
6266 void
6267 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6268 {
6269 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6270 int i;
6271
6272 for (i = 0; i < 2; ++i)
6273 x86_nop (code);
6274 }
6275
6276 /*
6277 * mono_arch_start_single_stepping:
6278 *
6279 * Start single stepping.
6280 */
6281 void
6282 mono_arch_start_single_stepping (void)
6283 {
6284 ss_trampoline = mini_get_single_step_trampoline ();
6285 }
6286
6287 /*
6288 * mono_arch_stop_single_stepping:
6289 *
6290 * Stop single stepping.
6291 */
6292 void
6293 mono_arch_stop_single_stepping (void)
6294 {
6295 ss_trampoline = NULL;
6296 }
6297
6298 /*
6299 * mono_arch_is_single_step_event:
6300 *
6301 * Return whenever the machine state in SIGCTX corresponds to a single
6302 * step event.
6303 */
6304 gboolean
6305 mono_arch_is_single_step_event (void *info, void *sigctx)
6306 {
6307 /* We use soft breakpoints */
6308 return FALSE;
6309 }
6310
6311 gboolean
6312 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6313 {
6314 /* We use soft breakpoints */
6315 return FALSE;
6316 }
6317
6318 #define BREAKPOINT_SIZE 2
6319
6320 /*
6321 * mono_arch_skip_breakpoint:
6322 *
6323 * See mini-amd64.c for docs.
6324 */
6325 void
6326 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6327 {
6328 g_assert_not_reached ();
6329 }
6330
6331 /*
6332 * mono_arch_skip_single_step:
6333 *
6334 * See mini-amd64.c for docs.
6335 */
6336 void
6337 mono_arch_skip_single_step (MonoContext *ctx)
6338 {
6339 g_assert_not_reached ();
6340 }
6341
6342 /*
6343 * mono_arch_get_seq_point_info:
6344 *
6345 * See mini-amd64.c for docs.
6346 */
6347 SeqPointInfo*
6348 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6349 {
6350 NOT_IMPLEMENTED;
6351 return NULL;
6352 }
6353
6354 #endif
6355
6356 gboolean
6357 mono_arch_opcode_supported (int opcode)
6358 {
6359 switch (opcode) {
6360 case OP_ATOMIC_ADD_I4:
6361 case OP_ATOMIC_EXCHANGE_I4:
6362 case OP_ATOMIC_CAS_I4:
6363 case OP_ATOMIC_LOAD_I1:
6364 case OP_ATOMIC_LOAD_I2:
6365 case OP_ATOMIC_LOAD_I4:
6366 case OP_ATOMIC_LOAD_U1:
6367 case OP_ATOMIC_LOAD_U2:
6368 case OP_ATOMIC_LOAD_U4:
6369 case OP_ATOMIC_LOAD_R4:
6370 case OP_ATOMIC_LOAD_R8:
6371 case OP_ATOMIC_STORE_I1:
6372 case OP_ATOMIC_STORE_I2:
6373 case OP_ATOMIC_STORE_I4:
6374 case OP_ATOMIC_STORE_U1:
6375 case OP_ATOMIC_STORE_U2:
6376 case OP_ATOMIC_STORE_U4:
6377 case OP_ATOMIC_STORE_R4:
6378 case OP_ATOMIC_STORE_R8:
6379 return TRUE;
6380 default:
6381 return FALSE;
6382 }
6383 }
6384
6385 CallInfo*
6386 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
6387 {
6388 return get_call_info (mp, sig);
6389 }
6390
6391 gpointer
6392 mono_arch_load_function (MonoJitICallId jit_icall_id)
6393 {
6394 gpointer target = NULL;
6395 switch (jit_icall_id) {
6396 #undef MONO_AOT_ICALL
6397 #define MONO_AOT_ICALL(x) case MONO_JIT_ICALL_ ## x: target = (gpointer)x; break;
6398 MONO_AOT_ICALL (mono_x86_start_gsharedvt_call)
6399 MONO_AOT_ICALL (mono_x86_throw_corlib_exception)
6400 MONO_AOT_ICALL (mono_x86_throw_exception)
6401 }
6402 return target;
6403 }
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