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Merge pull request #444 from knocte/xbuild_improvements
[mono-project.git] / mono / mini / mini-arm.c
blob7221fc963135dd9383597d21e0b8aa32e89cdfe3
1 /*
2 * mini-arm.c: ARM backend for the Mono code generator
3 *
4 * Authors:
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
7 *
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 */
12 #include "mini.h"
13 #include <string.h>
14
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/utils/mono-mmap.h>
18
19 #include "mini-arm.h"
20 #include "cpu-arm.h"
21 #include "trace.h"
22 #include "ir-emit.h"
23 #include "debugger-agent.h"
24 #include "mini-gc.h"
25 #include "mono/arch/arm/arm-fpa-codegen.h"
26 #include "mono/arch/arm/arm-vfp-codegen.h"
27
28 #if defined(__ARM_EABI__) && defined(__linux__) && !defined(PLATFORM_ANDROID)
29 #define HAVE_AEABI_READ_TP 1
30 #endif
31
32 #ifdef ARM_FPU_VFP_HARD
33 #define ARM_FPU_VFP 1
34 #endif
35
36 #ifdef ARM_FPU_FPA
37 #define IS_FPA 1
38 #else
39 #define IS_FPA 0
40 #endif
41
42 #ifdef ARM_FPU_VFP
43 #define IS_VFP 1
44 #else
45 #define IS_VFP 0
46 #endif
47
48 #ifdef MONO_ARCH_SOFT_FLOAT
49 #define IS_SOFT_FLOAT 1
50 #else
51 #define IS_SOFT_FLOAT 0
52 #endif
53
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
55
56 static gint lmf_tls_offset = -1;
57 static gint lmf_addr_tls_offset = -1;
58
59 /* This mutex protects architecture specific caches */
60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
62 static CRITICAL_SECTION mini_arch_mutex;
63
64 static int v5_supported = 0;
65 static int v6_supported = 0;
66 static int v7_supported = 0;
67 static int thumb_supported = 0;
68 /*
69 * Whenever to use the ARM EABI
70 */
71 static int eabi_supported = 0;
72
73 /*
74 * Whenever we are on arm/darwin aka the iphone.
75 */
76 static int darwin = 0;
77 /*
78 * Whenever to use the iphone ABI extensions:
79 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
80 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
81 * This is required for debugging/profiling tools to work, but it has some overhead so it should
82 * only be turned on in debug builds.
83 */
84 static int iphone_abi = 0;
85
86 /*
87 * The FPU we are generating code for. This is NOT runtime configurable right now,
88 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
89 */
90 static MonoArmFPU arm_fpu;
91
92 static int i8_align;
93
94 static volatile int ss_trigger_var = 0;
95
96 static gpointer single_step_func_wrapper;
97 static gpointer breakpoint_func_wrapper;
98
99 /*
100 * The code generated for sequence points reads from this location, which is
101 * made read-only when single stepping is enabled.
102 */
103 static gpointer ss_trigger_page;
104
105 /* Enabled breakpoints read from this trigger page */
106 static gpointer bp_trigger_page;
107
108 /* Structure used by the sequence points in AOTed code */
109 typedef struct {
110 gpointer ss_trigger_page;
111 gpointer bp_trigger_page;
112 guint8* bp_addrs [MONO_ZERO_LEN_ARRAY];
113 } SeqPointInfo;
114
115 /*
116 * TODO:
117 * floating point support: on ARM it is a mess, there are at least 3
118 * different setups, each of which binary incompat with the other.
119 * 1) FPA: old and ugly, but unfortunately what current distros use
120 * the double binary format has the two words swapped. 8 double registers.
121 * Implemented usually by kernel emulation.
122 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
123 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
124 * 3) VFP: the new and actually sensible and useful FP support. Implemented
125 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
126 *
127 * The plan is to write the FPA support first. softfloat can be tested in a chroot.
128 */
129 int mono_exc_esp_offset = 0;
130
131 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
132 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
133 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
134
135 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
136 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
137 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
138
139 #define ADD_LR_PC_4 ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 25) | (1 << 23) | (ARMREG_PC << 16) | (ARMREG_LR << 12) | 4)
140 #define MOV_LR_PC ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 24) | (0xa << 20) | (ARMREG_LR << 12) | ARMREG_PC)
141 #define DEBUG_IMT 0
142
143 /* A variant of ARM_LDR_IMM which can handle large offsets */
144 #define ARM_LDR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
145 if (arm_is_imm12 ((offset))) { \
146 ARM_LDR_IMM (code, (dreg), (basereg), (offset)); \
147 } else { \
148 g_assert ((scratch_reg) != (basereg)); \
149 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
150 ARM_LDR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
151 } \
152 } while (0)
153
154 #define ARM_STR_IMM_GENERAL(code, dreg, basereg, offset, scratch_reg) do { \
155 if (arm_is_imm12 ((offset))) { \
156 ARM_STR_IMM (code, (dreg), (basereg), (offset)); \
157 } else { \
158 g_assert ((scratch_reg) != (basereg)); \
159 code = mono_arm_emit_load_imm (code, (scratch_reg), (offset)); \
160 ARM_STR_REG_REG (code, (dreg), (basereg), (scratch_reg)); \
161 } \
162 } while (0)
163
164 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
165
166 const char*
167 mono_arch_regname (int reg)
168 {
169 static const char * rnames[] = {
170 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
171 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
172 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
173 "arm_pc"
174 };
175 if (reg >= 0 && reg < 16)
176 return rnames [reg];
177 return "unknown";
178 }
179
180 const char*
181 mono_arch_fregname (int reg)
182 {
183 static const char * rnames[] = {
184 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
185 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
186 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
187 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
188 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
189 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
190 "arm_f30", "arm_f31"
191 };
192 if (reg >= 0 && reg < 32)
193 return rnames [reg];
194 return "unknown";
195 }
196
197 #ifndef DISABLE_JIT
198
199 static guint8*
200 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
201 {
202 int imm8, rot_amount;
203 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
204 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
205 return code;
206 }
207 g_assert (dreg != sreg);
208 code = mono_arm_emit_load_imm (code, dreg, imm);
209 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
210 return code;
211 }
212
213 static guint8*
214 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
215 {
216 /* we can use r0-r3, since this is called only for incoming args on the stack */
217 if (size > sizeof (gpointer) * 4) {
218 guint8 *start_loop;
219 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
220 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
221 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
222 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
223 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
224 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
225 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
226 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
227 ARM_B_COND (code, ARMCOND_NE, 0);
228 arm_patch (code - 4, start_loop);
229 return code;
230 }
231 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
232 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
233 while (size >= 4) {
234 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
235 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
236 doffset += 4;
237 soffset += 4;
238 size -= 4;
239 }
240 } else if (size) {
241 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
242 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
243 doffset = soffset = 0;
244 while (size >= 4) {
245 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
246 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
247 doffset += 4;
248 soffset += 4;
249 size -= 4;
250 }
251 }
252 g_assert (size == 0);
253 return code;
254 }
255
256 static guint8*
257 emit_call_reg (guint8 *code, int reg)
258 {
259 if (v5_supported) {
260 ARM_BLX_REG (code, reg);
261 } else {
262 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
263 if (thumb_supported)
264 ARM_BX (code, reg);
265 else
266 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
267 }
268 return code;
269 }
270
271 static guint8*
272 emit_call_seq (MonoCompile *cfg, guint8 *code)
273 {
274 if (cfg->method->dynamic) {
275 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
276 ARM_B (code, 0);
277 *(gpointer*)code = NULL;
278 code += 4;
279 code = emit_call_reg (code, ARMREG_IP);
280 } else {
281 ARM_BL (code, 0);
282 }
283 return code;
284 }
285
286 static guint8*
287 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
288 {
289 switch (ins->opcode) {
290 case OP_FCALL:
291 case OP_FCALL_REG:
292 case OP_FCALL_MEMBASE:
293 if (IS_FPA) {
294 if (ins->dreg != ARM_FPA_F0)
295 ARM_FPA_MVFD (code, ins->dreg, ARM_FPA_F0);
296 } else if (IS_VFP) {
297 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
298 ARM_FMSR (code, ins->dreg, ARMREG_R0);
299 ARM_CVTS (code, ins->dreg, ins->dreg);
300 } else {
301 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
302 }
303 }
304 break;
305 }
306
307 return code;
308 }
309
310 /*
311 * emit_save_lmf:
312 *
313 * Emit code to push an LMF structure on the LMF stack.
314 * On arm, this is intermixed with the initialization of other fields of the structure.
315 */
316 static guint8*
317 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
318 {
319 gboolean get_lmf_fast = FALSE;
320 int i;
321
322 #ifdef HAVE_AEABI_READ_TP
323 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
324
325 if (lmf_addr_tls_offset != -1) {
326 get_lmf_fast = TRUE;
327
328 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
329 (gpointer)"__aeabi_read_tp");
330 code = emit_call_seq (cfg, code);
331
332 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, lmf_addr_tls_offset);
333 get_lmf_fast = TRUE;
334 }
335 #endif
336 if (!get_lmf_fast) {
337 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
338 (gpointer)"mono_get_lmf_addr");
339 code = emit_call_seq (cfg, code);
340 }
341 /* we build the MonoLMF structure on the stack - see mini-arm.h */
342 /* lmf_offset is the offset from the previous stack pointer,
343 * alloc_size is the total stack space allocated, so the offset
344 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
345 * The pointer to the struct is put in r1 (new_lmf).
346 * ip is used as scratch
347 * The callee-saved registers are already in the MonoLMF structure
348 */
349 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
350 /* r0 is the result from mono_get_lmf_addr () */
351 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, lmf_addr));
352 /* new_lmf->previous_lmf = *lmf_addr */
353 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
354 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
355 /* *(lmf_addr) = r1 */
356 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
357 /* Skip method (only needed for trampoline LMF frames) */
358 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, sp));
359 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, fp));
360 /* save the current IP */
361 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
362 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ip));
363
364 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
365 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
366
367 return code;
368 }
369
370 /*
371 * emit_save_lmf:
372 *
373 * Emit code to pop an LMF structure from the LMF stack.
374 */
375 static guint8*
376 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
377 {
378 int basereg, offset;
379
380 if (lmf_offset < 32) {
381 basereg = cfg->frame_reg;
382 offset = lmf_offset;
383 } else {
384 basereg = ARMREG_R2;
385 offset = 0;
386 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
387 }
388
389 /* ip = previous_lmf */
390 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
391 /* lr = lmf_addr */
392 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
393 /* *(lmf_addr) = previous_lmf */
394 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
395
396 return code;
397 }
398
399 #endif /* #ifndef DISABLE_JIT */
400
401 /*
402 * mono_arch_get_argument_info:
403 * @csig: a method signature
404 * @param_count: the number of parameters to consider
405 * @arg_info: an array to store the result infos
406 *
407 * Gathers information on parameters such as size, alignment and
408 * padding. arg_info should be large enought to hold param_count + 1 entries.
409 *
410 * Returns the size of the activation frame.
411 */
412 int
413 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
414 {
415 int k, frame_size = 0;
416 guint32 size, align, pad;
417 int offset = 8;
418
419 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
420 frame_size += sizeof (gpointer);
421 offset += 4;
422 }
423
424 arg_info [0].offset = offset;
425
426 if (csig->hasthis) {
427 frame_size += sizeof (gpointer);
428 offset += 4;
429 }
430
431 arg_info [0].size = frame_size;
432
433 for (k = 0; k < param_count; k++) {
434 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
435
436 /* ignore alignment for now */
437 align = 1;
438
439 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
440 arg_info [k].pad = pad;
441 frame_size += size;
442 arg_info [k + 1].pad = 0;
443 arg_info [k + 1].size = size;
444 offset += pad;
445 arg_info [k + 1].offset = offset;
446 offset += size;
447 }
448
449 align = MONO_ARCH_FRAME_ALIGNMENT;
450 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
451 arg_info [k].pad = pad;
452
453 return frame_size;
454 }
455
456 #define MAX_ARCH_DELEGATE_PARAMS 3
457
458 static gpointer
459 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
460 {
461 guint8 *code, *start;
462
463 if (has_target) {
464 start = code = mono_global_codeman_reserve (12);
465
466 /* Replace the this argument with the target */
467 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
468 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, target));
469 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
470
471 g_assert ((code - start) <= 12);
472
473 mono_arch_flush_icache (start, 12);
474 } else {
475 int size, i;
476
477 size = 8 + param_count * 4;
478 start = code = mono_global_codeman_reserve (size);
479
480 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
481 /* slide down the arguments */
482 for (i = 0; i < param_count; ++i) {
483 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
484 }
485 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
486
487 g_assert ((code - start) <= size);
488
489 mono_arch_flush_icache (start, size);
490 }
491
492 if (code_size)
493 *code_size = code - start;
494
495 return start;
496 }
497
498 /*
499 * mono_arch_get_delegate_invoke_impls:
500 *
501 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
502 * trampolines.
503 */
504 GSList*
505 mono_arch_get_delegate_invoke_impls (void)
506 {
507 GSList *res = NULL;
508 guint8 *code;
509 guint32 code_len;
510 int i;
511
512 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
513 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
514
515 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
516 code = get_delegate_invoke_impl (FALSE, i, &code_len);
517 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
518 }
519
520 return res;
521 }
522
523 gpointer
524 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
525 {
526 guint8 *code, *start;
527
528 /* FIXME: Support more cases */
529 if (MONO_TYPE_ISSTRUCT (sig->ret))
530 return NULL;
531
532 if (has_target) {
533 static guint8* cached = NULL;
534 mono_mini_arch_lock ();
535 if (cached) {
536 mono_mini_arch_unlock ();
537 return cached;
538 }
539
540 if (mono_aot_only)
541 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
542 else
543 start = get_delegate_invoke_impl (TRUE, 0, NULL);
544 cached = start;
545 mono_mini_arch_unlock ();
546 return cached;
547 } else {
548 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
549 int i;
550
551 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
552 return NULL;
553 for (i = 0; i < sig->param_count; ++i)
554 if (!mono_is_regsize_var (sig->params [i]))
555 return NULL;
556
557 mono_mini_arch_lock ();
558 code = cache [sig->param_count];
559 if (code) {
560 mono_mini_arch_unlock ();
561 return code;
562 }
563
564 if (mono_aot_only) {
565 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
566 start = mono_aot_get_trampoline (name);
567 g_free (name);
568 } else {
569 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
570 }
571 cache [sig->param_count] = start;
572 mono_mini_arch_unlock ();
573 return start;
574 }
575
576 return NULL;
577 }
578
579 gpointer
580 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
581 {
582 return (gpointer)regs [ARMREG_R0];
583 }
584
585 /*
586 * Initialize the cpu to execute managed code.
587 */
588 void
589 mono_arch_cpu_init (void)
590 {
591 #if defined(__ARM_EABI__)
592 eabi_supported = TRUE;
593 #endif
594 #if defined(__APPLE__) && defined(MONO_CROSS_COMPILE)
595 i8_align = 4;
596 #else
597 i8_align = __alignof__ (gint64);
598 #endif
599 }
600
601 static gpointer
602 create_function_wrapper (gpointer function)
603 {
604 guint8 *start, *code;
605
606 start = code = mono_global_codeman_reserve (96);
607
608 /*
609 * Construct the MonoContext structure on the stack.
610 */
611
612 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, sizeof (MonoContext));
613
614 /* save ip, lr and pc into their correspodings ctx.regs slots. */
615 ARM_STR_IMM (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + sizeof (mgreg_t) * ARMREG_IP);
616 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
617 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
618
619 /* save r0..r10 and fp */
620 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, regs));
621 ARM_STM (code, ARMREG_IP, 0x0fff);
622
623 /* now we can update fp. */
624 ARM_MOV_REG_REG (code, ARMREG_FP, ARMREG_SP);
625
626 /* make ctx.esp hold the actual value of sp at the beginning of this method. */
627 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_FP, sizeof (MonoContext));
628 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, 4 * ARMREG_SP);
629 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_SP);
630
631 /* make ctx.eip hold the address of the call. */
632 ARM_SUB_REG_IMM8 (code, ARMREG_LR, ARMREG_LR, 4);
633 ARM_STR_IMM (code, ARMREG_LR, ARMREG_SP, G_STRUCT_OFFSET (MonoContext, pc));
634
635 /* r0 now points to the MonoContext */
636 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_FP);
637
638 /* call */
639 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
640 ARM_B (code, 0);
641 *(gpointer*)code = function;
642 code += 4;
643 ARM_BLX_REG (code, ARMREG_IP);
644
645 /* we're back; save ctx.eip and ctx.esp into the corresponding regs slots. */
646 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, pc));
647 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_LR);
648 ARM_STR_IMM (code, ARMREG_R0, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs) + 4 * ARMREG_PC);
649
650 /* make ip point to the regs array, then restore everything, including pc. */
651 ARM_ADD_REG_IMM8 (code, ARMREG_IP, ARMREG_FP, G_STRUCT_OFFSET (MonoContext, regs));
652 ARM_LDM (code, ARMREG_IP, 0xffff);
653
654 mono_arch_flush_icache (start, code - start);
655
656 return start;
657 }
658
659 /*
660 * Initialize architecture specific code.
661 */
662 void
663 mono_arch_init (void)
664 {
665 InitializeCriticalSection (&mini_arch_mutex);
666
667 if (mini_get_debug_options ()->soft_breakpoints) {
668 single_step_func_wrapper = create_function_wrapper (debugger_agent_single_step_from_context);
669 breakpoint_func_wrapper = create_function_wrapper (debugger_agent_breakpoint_from_context);
670 } else {
671 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
672 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
673 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
674 }
675
676 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
677 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
678 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
679
680 #ifdef ARM_FPU_FPA
681 arm_fpu = MONO_ARM_FPU_FPA;
682 #elif defined(ARM_FPU_VFP_HARD)
683 arm_fpu = MONO_ARM_FPU_VFP_HARD;
684 #elif defined(ARM_FPU_VFP)
685 arm_fpu = MONO_ARM_FPU_VFP;
686 #else
687 arm_fpu = MONO_ARM_FPU_NONE;
688 #endif
689 }
690
691 /*
692 * Cleanup architecture specific code.
693 */
694 void
695 mono_arch_cleanup (void)
696 {
697 }
698
699 /*
700 * This function returns the optimizations supported on this cpu.
701 */
702 guint32
703 mono_arch_cpu_optimizations (guint32 *exclude_mask)
704 {
705 guint32 opts = 0;
706 const char *cpu_arch = getenv ("MONO_CPU_ARCH");
707 if (cpu_arch != NULL) {
708 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
709 if (strncmp (cpu_arch, "armv", 4) == 0) {
710 v5_supported = cpu_arch [4] >= '5';
711 v6_supported = cpu_arch [4] >= '6';
712 v7_supported = cpu_arch [4] >= '7';
713 }
714 } else {
715 #if __APPLE__
716 thumb_supported = TRUE;
717 v5_supported = TRUE;
718 darwin = TRUE;
719 iphone_abi = TRUE;
720 #else
721 char buf [512];
722 char *line;
723 FILE *file = fopen ("/proc/cpuinfo", "r");
724 if (file) {
725 while ((line = fgets (buf, 512, file))) {
726 if (strncmp (line, "Processor", 9) == 0) {
727 char *ver = strstr (line, "(v");
728 if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7'))
729 v5_supported = TRUE;
730 if (ver && (ver [2] == '6' || ver [2] == '7'))
731 v6_supported = TRUE;
732 if (ver && (ver [2] == '7'))
733 v7_supported = TRUE;
734 continue;
735 }
736 if (strncmp (line, "Features", 8) == 0) {
737 char *th = strstr (line, "thumb");
738 if (th) {
739 thumb_supported = TRUE;
740 if (v5_supported)
741 break;
742 }
743 continue;
744 }
745 }
746 fclose (file);
747 /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
748 }
749 #endif
750 }
751
752 /* no arm-specific optimizations yet */
753 *exclude_mask = 0;
754 return opts;
755 }
756
757 /*
758 * This function test for all SIMD functions supported.
759 *
760 * Returns a bitmask corresponding to all supported versions.
761 *
762 */
763 guint32
764 mono_arch_cpu_enumerate_simd_versions (void)
765 {
766 /* SIMD is currently unimplemented */
767 return 0;
768 }
769
770
771 #ifndef DISABLE_JIT
772
773 static gboolean
774 is_regsize_var (MonoType *t) {
775 if (t->byref)
776 return TRUE;
777 t = mini_type_get_underlying_type (NULL, t);
778 switch (t->type) {
779 case MONO_TYPE_I4:
780 case MONO_TYPE_U4:
781 case MONO_TYPE_I:
782 case MONO_TYPE_U:
783 case MONO_TYPE_PTR:
784 case MONO_TYPE_FNPTR:
785 return TRUE;
786 case MONO_TYPE_OBJECT:
787 case MONO_TYPE_STRING:
788 case MONO_TYPE_CLASS:
789 case MONO_TYPE_SZARRAY:
790 case MONO_TYPE_ARRAY:
791 return TRUE;
792 case MONO_TYPE_GENERICINST:
793 if (!mono_type_generic_inst_is_valuetype (t))
794 return TRUE;
795 return FALSE;
796 case MONO_TYPE_VALUETYPE:
797 return FALSE;
798 }
799 return FALSE;
800 }
801
802 GList *
803 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
804 {
805 GList *vars = NULL;
806 int i;
807
808 for (i = 0; i < cfg->num_varinfo; i++) {
809 MonoInst *ins = cfg->varinfo [i];
810 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
811
812 /* unused vars */
813 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
814 continue;
815
816 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
817 continue;
818
819 /* we can only allocate 32 bit values */
820 if (is_regsize_var (ins->inst_vtype)) {
821 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
822 g_assert (i == vmv->idx);
823 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
824 }
825 }
826
827 return vars;
828 }
829
830 #define USE_EXTRA_TEMPS 0
831
832 GList *
833 mono_arch_get_global_int_regs (MonoCompile *cfg)
834 {
835 GList *regs = NULL;
836
837 mono_arch_compute_omit_fp (cfg);
838
839 /*
840 * FIXME: Interface calls might go through a static rgctx trampoline which
841 * sets V5, but it doesn't save it, so we need to save it ourselves, and
842 * avoid using it.
843 */
844 if (cfg->flags & MONO_CFG_HAS_CALLS)
845 cfg->uses_rgctx_reg = TRUE;
846
847 if (cfg->arch.omit_fp)
848 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
849 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
850 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
851 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
852 if (darwin)
853 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
854 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
855 else
856 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
857 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
858 /* V5 is reserved for passing the vtable/rgctx/IMT method */
859 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
860 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
861 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
862
863 return regs;
864 }
865
866 /*
867 * mono_arch_regalloc_cost:
868 *
869 * Return the cost, in number of memory references, of the action of
870 * allocating the variable VMV into a register during global register
871 * allocation.
872 */
873 guint32
874 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
875 {
876 /* FIXME: */
877 return 2;
878 }
879
880 #endif /* #ifndef DISABLE_JIT */
881
882 #ifndef __GNUC_PREREQ
883 #define __GNUC_PREREQ(maj, min) (0)
884 #endif
885
886 void
887 mono_arch_flush_icache (guint8 *code, gint size)
888 {
889 #if __APPLE__
890 sys_icache_invalidate (code, size);
891 #elif __GNUC_PREREQ(4, 1)
892 __clear_cache (code, code + size);
893 #elif defined(PLATFORM_ANDROID)
894 const int syscall = 0xf0002;
895 __asm __volatile (
896 "mov r0, %0\n"
897 "mov r1, %1\n"
898 "mov r7, %2\n"
899 "mov r2, #0x0\n"
900 "svc 0x00000000\n"
901 :
902 : "r" (code), "r" (code + size), "r" (syscall)
903 : "r0", "r1", "r7", "r2"
904 );
905 #else
906 __asm __volatile ("mov r0, %0\n"
907 "mov r1, %1\n"
908 "mov r2, %2\n"
909 "swi 0x9f0002 @ sys_cacheflush"
910 : /* no outputs */
911 : "r" (code), "r" (code + size), "r" (0)
912 : "r0", "r1", "r3" );
913 #endif
914 }
915
916 typedef enum {
917 RegTypeNone,
918 RegTypeGeneral,
919 RegTypeIRegPair,
920 RegTypeBase,
921 RegTypeBaseGen,
922 RegTypeFP,
923 RegTypeStructByVal,
924 RegTypeStructByAddr
925 } ArgStorage;
926
927 typedef struct {
928 gint32 offset;
929 guint16 vtsize; /* in param area */
930 guint8 reg;
931 ArgStorage storage;
932 gint32 struct_size;
933 guint8 size : 4; /* 1, 2, 4, 8, or regs used by RegTypeStructByVal */
934 } ArgInfo;
935
936 typedef struct {
937 int nargs;
938 guint32 stack_usage;
939 gboolean vtype_retaddr;
940 /* The index of the vret arg in the argument list */
941 int vret_arg_index;
942 ArgInfo ret;
943 ArgInfo sig_cookie;
944 ArgInfo args [1];
945 } CallInfo;
946
947 #define DEBUG(a)
948
949 #ifndef __GNUC__
950 /*#define __alignof__(a) sizeof(a)*/
951 #define __alignof__(type) G_STRUCT_OFFSET(struct { char c; type x; }, x)
952 #endif
953
954 #define PARAM_REGS 4
955
956 static void inline
957 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
958 {
959 if (simple) {
960 if (*gr > ARMREG_R3) {
961 ainfo->offset = *stack_size;
962 ainfo->reg = ARMREG_SP; /* in the caller */
963 ainfo->storage = RegTypeBase;
964 *stack_size += 4;
965 } else {
966 ainfo->storage = RegTypeGeneral;
967 ainfo->reg = *gr;
968 }
969 } else {
970 gboolean split;
971
972 if (eabi_supported)
973 split = i8_align == 4;
974 else
975 split = TRUE;
976
977 if (*gr == ARMREG_R3 && split) {
978 /* first word in r3 and the second on the stack */
979 ainfo->offset = *stack_size;
980 ainfo->reg = ARMREG_SP; /* in the caller */
981 ainfo->storage = RegTypeBaseGen;
982 *stack_size += 4;
983 } else if (*gr >= ARMREG_R3) {
984 if (eabi_supported) {
985 /* darwin aligns longs to 4 byte only */
986 if (i8_align == 8) {
987 *stack_size += 7;
988 *stack_size &= ~7;
989 }
990 }
991 ainfo->offset = *stack_size;
992 ainfo->reg = ARMREG_SP; /* in the caller */
993 ainfo->storage = RegTypeBase;
994 *stack_size += 8;
995 } else {
996 if (eabi_supported) {
997 if (i8_align == 8 && ((*gr) & 1))
998 (*gr) ++;
999 }
1000 ainfo->storage = RegTypeIRegPair;
1001 ainfo->reg = *gr;
1002 }
1003 (*gr) ++;
1004 }
1005 (*gr) ++;
1006 }
1007
1008 static CallInfo*
1009 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
1010 {
1011 guint i, gr, pstart;
1012 int n = sig->hasthis + sig->param_count;
1013 MonoType *simpletype;
1014 guint32 stack_size = 0;
1015 CallInfo *cinfo;
1016 gboolean is_pinvoke = sig->pinvoke;
1017
1018 if (mp)
1019 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1020 else
1021 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1022
1023 cinfo->nargs = n;
1024 gr = ARMREG_R0;
1025
1026 /* FIXME: handle returning a struct */
1027 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1028 guint32 align;
1029
1030 if (is_pinvoke && mono_class_native_size (mono_class_from_mono_type (sig->ret), &align) <= sizeof (gpointer)) {
1031 cinfo->ret.storage = RegTypeStructByVal;
1032 } else {
1033 cinfo->vtype_retaddr = TRUE;
1034 }
1035 }
1036
1037 pstart = 0;
1038 n = 0;
1039 /*
1040 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1041 * the first argument, allowing 'this' to be always passed in the first arg reg.
1042 * Also do this if the first argument is a reference type, since virtual calls
1043 * are sometimes made using calli without sig->hasthis set, like in the delegate
1044 * invoke wrappers.
1045 */
1046 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1047 if (sig->hasthis) {
1048 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1049 } else {
1050 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1051 pstart = 1;
1052 }
1053 n ++;
1054 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1055 cinfo->vret_arg_index = 1;
1056 } else {
1057 /* this */
1058 if (sig->hasthis) {
1059 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1060 n ++;
1061 }
1062
1063 if (cinfo->vtype_retaddr)
1064 add_general (&gr, &stack_size, &cinfo->ret, TRUE);
1065 }
1066
1067 DEBUG(printf("params: %d\n", sig->param_count));
1068 for (i = pstart; i < sig->param_count; ++i) {
1069 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1070 /* Prevent implicit arguments and sig_cookie from
1071 being passed in registers */
1072 gr = ARMREG_R3 + 1;
1073 /* Emit the signature cookie just before the implicit arguments */
1074 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1075 }
1076 DEBUG(printf("param %d: ", i));
1077 if (sig->params [i]->byref) {
1078 DEBUG(printf("byref\n"));
1079 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1080 n++;
1081 continue;
1082 }
1083 simpletype = mini_type_get_underlying_type (NULL, sig->params [i]);
1084 switch (simpletype->type) {
1085 case MONO_TYPE_BOOLEAN:
1086 case MONO_TYPE_I1:
1087 case MONO_TYPE_U1:
1088 cinfo->args [n].size = 1;
1089 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1090 n++;
1091 break;
1092 case MONO_TYPE_CHAR:
1093 case MONO_TYPE_I2:
1094 case MONO_TYPE_U2:
1095 cinfo->args [n].size = 2;
1096 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1097 n++;
1098 break;
1099 case MONO_TYPE_I4:
1100 case MONO_TYPE_U4:
1101 cinfo->args [n].size = 4;
1102 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1103 n++;
1104 break;
1105 case MONO_TYPE_I:
1106 case MONO_TYPE_U:
1107 case MONO_TYPE_PTR:
1108 case MONO_TYPE_FNPTR:
1109 case MONO_TYPE_CLASS:
1110 case MONO_TYPE_OBJECT:
1111 case MONO_TYPE_STRING:
1112 case MONO_TYPE_SZARRAY:
1113 case MONO_TYPE_ARRAY:
1114 case MONO_TYPE_R4:
1115 cinfo->args [n].size = sizeof (gpointer);
1116 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1117 n++;
1118 break;
1119 case MONO_TYPE_GENERICINST:
1120 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1121 cinfo->args [n].size = sizeof (gpointer);
1122 add_general (&gr, &stack_size, cinfo->args + n, TRUE);
1123 n++;
1124 break;
1125 }
1126 /* Fall through */
1127 case MONO_TYPE_TYPEDBYREF:
1128 case MONO_TYPE_VALUETYPE: {
1129 gint size;
1130 int align_size;
1131 int nwords;
1132 guint32 align;
1133
1134 if (simpletype->type == MONO_TYPE_TYPEDBYREF) {
1135 size = sizeof (MonoTypedRef);
1136 align = sizeof (gpointer);
1137 } else {
1138 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1139 if (is_pinvoke)
1140 size = mono_class_native_size (klass, &align);
1141 else
1142 size = mono_class_value_size (klass, &align);
1143 }
1144 DEBUG(printf ("load %d bytes struct\n",
1145 mono_class_native_size (sig->params [i]->data.klass, NULL)));
1146 align_size = size;
1147 nwords = 0;
1148 align_size += (sizeof (gpointer) - 1);
1149 align_size &= ~(sizeof (gpointer) - 1);
1150 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1151 cinfo->args [n].storage = RegTypeStructByVal;
1152 cinfo->args [n].struct_size = size;
1153 /* FIXME: align stack_size if needed */
1154 if (eabi_supported) {
1155 if (align >= 8 && (gr & 1))
1156 gr ++;
1157 }
1158 if (gr > ARMREG_R3) {
1159 cinfo->args [n].size = 0;
1160 cinfo->args [n].vtsize = nwords;
1161 } else {
1162 int rest = ARMREG_R3 - gr + 1;
1163 int n_in_regs = rest >= nwords? nwords: rest;
1164
1165 cinfo->args [n].size = n_in_regs;
1166 cinfo->args [n].vtsize = nwords - n_in_regs;
1167 cinfo->args [n].reg = gr;
1168 gr += n_in_regs;
1169 nwords -= n_in_regs;
1170 }
1171 cinfo->args [n].offset = stack_size;
1172 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1173 stack_size += nwords * sizeof (gpointer);
1174 n++;
1175 break;
1176 }
1177 case MONO_TYPE_U8:
1178 case MONO_TYPE_I8:
1179 case MONO_TYPE_R8:
1180 cinfo->args [n].size = 8;
1181 add_general (&gr, &stack_size, cinfo->args + n, FALSE);
1182 n++;
1183 break;
1184 default:
1185 g_error ("Can't trampoline 0x%x", sig->params [i]->type);
1186 }
1187 }
1188
1189 /* Handle the case where there are no implicit arguments */
1190 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1191 /* Prevent implicit arguments and sig_cookie from
1192 being passed in registers */
1193 gr = ARMREG_R3 + 1;
1194 /* Emit the signature cookie just before the implicit arguments */
1195 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1196 }
1197
1198 {
1199 simpletype = mini_type_get_underlying_type (NULL, sig->ret);
1200 switch (simpletype->type) {
1201 case MONO_TYPE_BOOLEAN:
1202 case MONO_TYPE_I1:
1203 case MONO_TYPE_U1:
1204 case MONO_TYPE_I2:
1205 case MONO_TYPE_U2:
1206 case MONO_TYPE_CHAR:
1207 case MONO_TYPE_I4:
1208 case MONO_TYPE_U4:
1209 case MONO_TYPE_I:
1210 case MONO_TYPE_U:
1211 case MONO_TYPE_PTR:
1212 case MONO_TYPE_FNPTR:
1213 case MONO_TYPE_CLASS:
1214 case MONO_TYPE_OBJECT:
1215 case MONO_TYPE_SZARRAY:
1216 case MONO_TYPE_ARRAY:
1217 case MONO_TYPE_STRING:
1218 cinfo->ret.storage = RegTypeGeneral;
1219 cinfo->ret.reg = ARMREG_R0;
1220 break;
1221 case MONO_TYPE_U8:
1222 case MONO_TYPE_I8:
1223 cinfo->ret.storage = RegTypeIRegPair;
1224 cinfo->ret.reg = ARMREG_R0;
1225 break;
1226 case MONO_TYPE_R4:
1227 case MONO_TYPE_R8:
1228 cinfo->ret.storage = RegTypeFP;
1229 cinfo->ret.reg = ARMREG_R0;
1230 /* FIXME: cinfo->ret.reg = ???;
1231 cinfo->ret.storage = RegTypeFP;*/
1232 break;
1233 case MONO_TYPE_GENERICINST:
1234 if (!mono_type_generic_inst_is_valuetype (simpletype)) {
1235 cinfo->ret.storage = RegTypeGeneral;
1236 cinfo->ret.reg = ARMREG_R0;
1237 break;
1238 }
1239 /* Fall through */
1240 case MONO_TYPE_VALUETYPE:
1241 case MONO_TYPE_TYPEDBYREF:
1242 if (cinfo->ret.storage != RegTypeStructByVal)
1243 cinfo->ret.storage = RegTypeStructByAddr;
1244 break;
1245 case MONO_TYPE_VOID:
1246 break;
1247 default:
1248 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1249 }
1250 }
1251
1252 /* align stack size to 8 */
1253 DEBUG (printf (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1254 stack_size = (stack_size + 7) & ~7;
1255
1256 cinfo->stack_usage = stack_size;
1257 return cinfo;
1258 }
1259
1260 #ifndef DISABLE_JIT
1261
1262 static gboolean
1263 debug_omit_fp (void)
1264 {
1265 #if 0
1266 return mono_debug_count ();
1267 #else
1268 return TRUE;
1269 #endif
1270 }
1271
1272 /**
1273 * mono_arch_compute_omit_fp:
1274 *
1275 * Determine whenever the frame pointer can be eliminated.
1276 */
1277 static void
1278 mono_arch_compute_omit_fp (MonoCompile *cfg)
1279 {
1280 MonoMethodSignature *sig;
1281 MonoMethodHeader *header;
1282 int i, locals_size;
1283 CallInfo *cinfo;
1284
1285 if (cfg->arch.omit_fp_computed)
1286 return;
1287
1288 header = cfg->header;
1289
1290 sig = mono_method_signature (cfg->method);
1291
1292 if (!cfg->arch.cinfo)
1293 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1294 cinfo = cfg->arch.cinfo;
1295
1296 /*
1297 * FIXME: Remove some of the restrictions.
1298 */
1299 cfg->arch.omit_fp = TRUE;
1300 cfg->arch.omit_fp_computed = TRUE;
1301
1302 if (cfg->disable_omit_fp)
1303 cfg->arch.omit_fp = FALSE;
1304 if (!debug_omit_fp ())
1305 cfg->arch.omit_fp = FALSE;
1306 /*
1307 if (cfg->method->save_lmf)
1308 cfg->arch.omit_fp = FALSE;
1309 */
1310 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1311 cfg->arch.omit_fp = FALSE;
1312 if (header->num_clauses)
1313 cfg->arch.omit_fp = FALSE;
1314 if (cfg->param_area)
1315 cfg->arch.omit_fp = FALSE;
1316 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1317 cfg->arch.omit_fp = FALSE;
1318 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1319 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1320 cfg->arch.omit_fp = FALSE;
1321 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1322 ArgInfo *ainfo = &cinfo->args [i];
1323
1324 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1325 /*
1326 * The stack offset can only be determined when the frame
1327 * size is known.
1328 */
1329 cfg->arch.omit_fp = FALSE;
1330 }
1331 }
1332
1333 locals_size = 0;
1334 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1335 MonoInst *ins = cfg->varinfo [i];
1336 int ialign;
1337
1338 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1339 }
1340 }
1341
1342 /*
1343 * Set var information according to the calling convention. arm version.
1344 * The locals var stuff should most likely be split in another method.
1345 */
1346 void
1347 mono_arch_allocate_vars (MonoCompile *cfg)
1348 {
1349 MonoMethodSignature *sig;
1350 MonoMethodHeader *header;
1351 MonoInst *ins;
1352 int i, offset, size, align, curinst;
1353 CallInfo *cinfo;
1354 guint32 ualign;
1355
1356 sig = mono_method_signature (cfg->method);
1357
1358 if (!cfg->arch.cinfo)
1359 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1360 cinfo = cfg->arch.cinfo;
1361
1362 mono_arch_compute_omit_fp (cfg);
1363
1364 if (cfg->arch.omit_fp)
1365 cfg->frame_reg = ARMREG_SP;
1366 else
1367 cfg->frame_reg = ARMREG_FP;
1368
1369 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1370
1371 /* allow room for the vararg method args: void* and long/double */
1372 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1373 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1374
1375 header = cfg->header;
1376
1377 /* See mono_arch_get_global_int_regs () */
1378 if (cfg->flags & MONO_CFG_HAS_CALLS)
1379 cfg->uses_rgctx_reg = TRUE;
1380
1381 if (cfg->frame_reg != ARMREG_SP)
1382 cfg->used_int_regs |= 1 << cfg->frame_reg;
1383
1384 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1385 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1386 cfg->used_int_regs |= (1 << ARMREG_V5);
1387
1388 offset = 0;
1389 curinst = 0;
1390 if (!MONO_TYPE_ISSTRUCT (sig->ret)) {
1391 switch (mini_type_get_underlying_type (NULL, sig->ret)->type) {
1392 case MONO_TYPE_VOID:
1393 break;
1394 default:
1395 cfg->ret->opcode = OP_REGVAR;
1396 cfg->ret->inst_c0 = ARMREG_R0;
1397 break;
1398 }
1399 }
1400 /* local vars are at a positive offset from the stack pointer */
1401 /*
1402 * also note that if the function uses alloca, we use FP
1403 * to point at the local variables.
1404 */
1405 offset = 0; /* linkage area */
1406 /* align the offset to 16 bytes: not sure this is needed here */
1407 //offset += 8 - 1;
1408 //offset &= ~(8 - 1);
1409
1410 /* add parameter area size for called functions */
1411 offset += cfg->param_area;
1412 offset += 8 - 1;
1413 offset &= ~(8 - 1);
1414 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1415 offset += 8;
1416
1417 /* allow room to save the return value */
1418 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1419 offset += 8;
1420
1421 /* the MonoLMF structure is stored just below the stack pointer */
1422 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1423 if (cinfo->ret.storage == RegTypeStructByVal) {
1424 cfg->ret->opcode = OP_REGOFFSET;
1425 cfg->ret->inst_basereg = cfg->frame_reg;
1426 offset += sizeof (gpointer) - 1;
1427 offset &= ~(sizeof (gpointer) - 1);
1428 cfg->ret->inst_offset = - offset;
1429 } else {
1430 ins = cfg->vret_addr;
1431 offset += sizeof(gpointer) - 1;
1432 offset &= ~(sizeof(gpointer) - 1);
1433 ins->inst_offset = offset;
1434 ins->opcode = OP_REGOFFSET;
1435 ins->inst_basereg = cfg->frame_reg;
1436 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1437 printf ("vret_addr =");
1438 mono_print_ins (cfg->vret_addr);
1439 }
1440 }
1441 offset += sizeof(gpointer);
1442 }
1443
1444 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1445 if (cfg->arch.seq_point_info_var) {
1446 MonoInst *ins;
1447
1448 ins = cfg->arch.seq_point_info_var;
1449
1450 size = 4;
1451 align = 4;
1452 offset += align - 1;
1453 offset &= ~(align - 1);
1454 ins->opcode = OP_REGOFFSET;
1455 ins->inst_basereg = cfg->frame_reg;
1456 ins->inst_offset = offset;
1457 offset += size;
1458
1459 ins = cfg->arch.ss_trigger_page_var;
1460 size = 4;
1461 align = 4;
1462 offset += align - 1;
1463 offset &= ~(align - 1);
1464 ins->opcode = OP_REGOFFSET;
1465 ins->inst_basereg = cfg->frame_reg;
1466 ins->inst_offset = offset;
1467 offset += size;
1468 }
1469
1470 if (cfg->arch.seq_point_read_var) {
1471 MonoInst *ins;
1472
1473 ins = cfg->arch.seq_point_read_var;
1474
1475 size = 4;
1476 align = 4;
1477 offset += align - 1;
1478 offset &= ~(align - 1);
1479 ins->opcode = OP_REGOFFSET;
1480 ins->inst_basereg = cfg->frame_reg;
1481 ins->inst_offset = offset;
1482 offset += size;
1483
1484 ins = cfg->arch.seq_point_ss_method_var;
1485 size = 4;
1486 align = 4;
1487 offset += align - 1;
1488 offset &= ~(align - 1);
1489 ins->opcode = OP_REGOFFSET;
1490 ins->inst_basereg = cfg->frame_reg;
1491 ins->inst_offset = offset;
1492 offset += size;
1493
1494 ins = cfg->arch.seq_point_bp_method_var;
1495 size = 4;
1496 align = 4;
1497 offset += align - 1;
1498 offset &= ~(align - 1);
1499 ins->opcode = OP_REGOFFSET;
1500 ins->inst_basereg = cfg->frame_reg;
1501 ins->inst_offset = offset;
1502 offset += size;
1503 }
1504
1505 cfg->locals_min_stack_offset = offset;
1506
1507 curinst = cfg->locals_start;
1508 for (i = curinst; i < cfg->num_varinfo; ++i) {
1509 ins = cfg->varinfo [i];
1510 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1511 continue;
1512
1513 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1514 * pinvoke wrappers when they call functions returning structure */
1515 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (ins->inst_vtype) && ins->inst_vtype->type != MONO_TYPE_TYPEDBYREF) {
1516 size = mono_class_native_size (mono_class_from_mono_type (ins->inst_vtype), &ualign);
1517 align = ualign;
1518 }
1519 else
1520 size = mono_type_size (ins->inst_vtype, &align);
1521
1522 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1523 * since it loads/stores misaligned words, which don't do the right thing.
1524 */
1525 if (align < 4 && size >= 4)
1526 align = 4;
1527 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1528 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1529 offset += align - 1;
1530 offset &= ~(align - 1);
1531 ins->opcode = OP_REGOFFSET;
1532 ins->inst_offset = offset;
1533 ins->inst_basereg = cfg->frame_reg;
1534 offset += size;
1535 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1536 }
1537
1538 cfg->locals_max_stack_offset = offset;
1539
1540 curinst = 0;
1541 if (sig->hasthis) {
1542 ins = cfg->args [curinst];
1543 if (ins->opcode != OP_REGVAR) {
1544 ins->opcode = OP_REGOFFSET;
1545 ins->inst_basereg = cfg->frame_reg;
1546 offset += sizeof (gpointer) - 1;
1547 offset &= ~(sizeof (gpointer) - 1);
1548 ins->inst_offset = offset;
1549 offset += sizeof (gpointer);
1550 }
1551 curinst++;
1552 }
1553
1554 if (sig->call_convention == MONO_CALL_VARARG) {
1555 size = 4;
1556 align = 4;
1557
1558 /* Allocate a local slot to hold the sig cookie address */
1559 offset += align - 1;
1560 offset &= ~(align - 1);
1561 cfg->sig_cookie = offset;
1562 offset += size;
1563 }
1564
1565 for (i = 0; i < sig->param_count; ++i) {
1566 ins = cfg->args [curinst];
1567
1568 if (ins->opcode != OP_REGVAR) {
1569 ins->opcode = OP_REGOFFSET;
1570 ins->inst_basereg = cfg->frame_reg;
1571 size = mini_type_stack_size_full (NULL, sig->params [i], &ualign, sig->pinvoke);
1572 align = ualign;
1573 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1574 * since it loads/stores misaligned words, which don't do the right thing.
1575 */
1576 if (align < 4 && size >= 4)
1577 align = 4;
1578 /* The code in the prolog () stores words when storing vtypes received in a register */
1579 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
1580 align = 4;
1581 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1582 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1583 offset += align - 1;
1584 offset &= ~(align - 1);
1585 ins->inst_offset = offset;
1586 offset += size;
1587 }
1588 curinst++;
1589 }
1590
1591 /* align the offset to 8 bytes */
1592 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
1593 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1594 offset += 8 - 1;
1595 offset &= ~(8 - 1);
1596
1597 /* change sign? */
1598 cfg->stack_offset = offset;
1599 }
1600
1601 void
1602 mono_arch_create_vars (MonoCompile *cfg)
1603 {
1604 MonoMethodSignature *sig;
1605 CallInfo *cinfo;
1606
1607 sig = mono_method_signature (cfg->method);
1608
1609 if (!cfg->arch.cinfo)
1610 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1611 cinfo = cfg->arch.cinfo;
1612
1613 if (cinfo->ret.storage == RegTypeStructByVal)
1614 cfg->ret_var_is_local = TRUE;
1615
1616 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
1617 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1618 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1619 printf ("vret_addr = ");
1620 mono_print_ins (cfg->vret_addr);
1621 }
1622 }
1623
1624 if (cfg->gen_seq_points) {
1625 if (cfg->soft_breakpoints) {
1626 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1627 ins->flags |= MONO_INST_VOLATILE;
1628 cfg->arch.seq_point_read_var = ins;
1629
1630 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1631 ins->flags |= MONO_INST_VOLATILE;
1632 cfg->arch.seq_point_ss_method_var = ins;
1633
1634 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1635 ins->flags |= MONO_INST_VOLATILE;
1636 cfg->arch.seq_point_bp_method_var = ins;
1637
1638 g_assert (!cfg->compile_aot);
1639 } else if (cfg->compile_aot) {
1640 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1641 ins->flags |= MONO_INST_VOLATILE;
1642 cfg->arch.seq_point_info_var = ins;
1643
1644 /* Allocate a separate variable for this to save 1 load per seq point */
1645 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1646 ins->flags |= MONO_INST_VOLATILE;
1647 cfg->arch.ss_trigger_page_var = ins;
1648 }
1649 }
1650 }
1651
1652 static void
1653 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1654 {
1655 MonoMethodSignature *tmp_sig;
1656 int sig_reg;
1657
1658 if (call->tail_call)
1659 NOT_IMPLEMENTED;
1660
1661 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
1662
1663 /*
1664 * mono_ArgIterator_Setup assumes the signature cookie is
1665 * passed first and all the arguments which were before it are
1666 * passed on the stack after the signature. So compensate by
1667 * passing a different signature.
1668 */
1669 tmp_sig = mono_metadata_signature_dup (call->signature);
1670 tmp_sig->param_count -= call->signature->sentinelpos;
1671 tmp_sig->sentinelpos = 0;
1672 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1673
1674 sig_reg = mono_alloc_ireg (cfg);
1675 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1676
1677 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
1678 }
1679
1680 #ifdef ENABLE_LLVM
1681 LLVMCallInfo*
1682 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1683 {
1684 int i, n;
1685 CallInfo *cinfo;
1686 ArgInfo *ainfo;
1687 LLVMCallInfo *linfo;
1688
1689 n = sig->param_count + sig->hasthis;
1690
1691 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1692
1693 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1694
1695 /*
1696 * LLVM always uses the native ABI while we use our own ABI, the
1697 * only difference is the handling of vtypes:
1698 * - we only pass/receive them in registers in some cases, and only
1699 * in 1 or 2 integer registers.
1700 */
1701 if (cinfo->vtype_retaddr) {
1702 /* Vtype returned using a hidden argument */
1703 linfo->ret.storage = LLVMArgVtypeRetAddr;
1704 linfo->vret_arg_index = cinfo->vret_arg_index;
1705 } else if (cinfo->ret.storage != RegTypeGeneral && cinfo->ret.storage != RegTypeNone && cinfo->ret.storage != RegTypeFP && cinfo->ret.storage != RegTypeIRegPair) {
1706 cfg->exception_message = g_strdup ("unknown ret conv");
1707 cfg->disable_llvm = TRUE;
1708 return linfo;
1709 }
1710
1711 for (i = 0; i < n; ++i) {
1712 ainfo = cinfo->args + i;
1713
1714 linfo->args [i].storage = LLVMArgNone;
1715
1716 switch (ainfo->storage) {
1717 case RegTypeGeneral:
1718 case RegTypeIRegPair:
1719 case RegTypeBase:
1720 linfo->args [i].storage = LLVMArgInIReg;
1721 break;
1722 case RegTypeStructByVal:
1723 // FIXME: Passing entirely on the stack or split reg/stack
1724 if (ainfo->vtsize == 0 && ainfo->size <= 2) {
1725 linfo->args [i].storage = LLVMArgVtypeInReg;
1726 linfo->args [i].pair_storage [0] = LLVMArgInIReg;
1727 if (ainfo->size == 2)
1728 linfo->args [i].pair_storage [1] = LLVMArgInIReg;
1729 else
1730 linfo->args [i].pair_storage [1] = LLVMArgNone;
1731 } else {
1732 cfg->exception_message = g_strdup_printf ("vtype-by-val on stack");
1733 cfg->disable_llvm = TRUE;
1734 }
1735 break;
1736 default:
1737 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
1738 cfg->disable_llvm = TRUE;
1739 break;
1740 }
1741 }
1742
1743 return linfo;
1744 }
1745 #endif
1746
1747 void
1748 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1749 {
1750 MonoInst *in, *ins;
1751 MonoMethodSignature *sig;
1752 int i, n;
1753 CallInfo *cinfo;
1754
1755 sig = call->signature;
1756 n = sig->param_count + sig->hasthis;
1757
1758 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
1759
1760 for (i = 0; i < n; ++i) {
1761 ArgInfo *ainfo = cinfo->args + i;
1762 MonoType *t;
1763
1764 if (i >= sig->hasthis)
1765 t = sig->params [i - sig->hasthis];
1766 else
1767 t = &mono_defaults.int_class->byval_arg;
1768 t = mini_type_get_underlying_type (NULL, t);
1769
1770 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1771 /* Emit the signature cookie just before the implicit arguments */
1772 emit_sig_cookie (cfg, call, cinfo);
1773 }
1774
1775 in = call->args [i];
1776
1777 switch (ainfo->storage) {
1778 case RegTypeGeneral:
1779 case RegTypeIRegPair:
1780 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1781 MONO_INST_NEW (cfg, ins, OP_MOVE);
1782 ins->dreg = mono_alloc_ireg (cfg);
1783 ins->sreg1 = in->dreg + 1;
1784 MONO_ADD_INS (cfg->cbb, ins);
1785 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1786
1787 MONO_INST_NEW (cfg, ins, OP_MOVE);
1788 ins->dreg = mono_alloc_ireg (cfg);
1789 ins->sreg1 = in->dreg + 2;
1790 MONO_ADD_INS (cfg->cbb, ins);
1791 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1792 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
1793 if (ainfo->size == 4) {
1794 if (IS_SOFT_FLOAT) {
1795 /* mono_emit_call_args () have already done the r8->r4 conversion */
1796 /* The converted value is in an int vreg */
1797 MONO_INST_NEW (cfg, ins, OP_MOVE);
1798 ins->dreg = mono_alloc_ireg (cfg);
1799 ins->sreg1 = in->dreg;
1800 MONO_ADD_INS (cfg->cbb, ins);
1801 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1802 } else {
1803 int creg;
1804
1805 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1806 creg = mono_alloc_ireg (cfg);
1807 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1808 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1809 }
1810 } else {
1811 if (IS_SOFT_FLOAT) {
1812 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
1813 ins->dreg = mono_alloc_ireg (cfg);
1814 ins->sreg1 = in->dreg;
1815 MONO_ADD_INS (cfg->cbb, ins);
1816 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1817
1818 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
1819 ins->dreg = mono_alloc_ireg (cfg);
1820 ins->sreg1 = in->dreg;
1821 MONO_ADD_INS (cfg->cbb, ins);
1822 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
1823 } else {
1824 int creg;
1825
1826 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1827 creg = mono_alloc_ireg (cfg);
1828 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1829 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
1830 creg = mono_alloc_ireg (cfg);
1831 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
1832 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
1833 }
1834 }
1835 cfg->flags |= MONO_CFG_HAS_FPOUT;
1836 } else {
1837 MONO_INST_NEW (cfg, ins, OP_MOVE);
1838 ins->dreg = mono_alloc_ireg (cfg);
1839 ins->sreg1 = in->dreg;
1840 MONO_ADD_INS (cfg->cbb, ins);
1841
1842 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
1843 }
1844 break;
1845 case RegTypeStructByAddr:
1846 NOT_IMPLEMENTED;
1847 #if 0
1848 /* FIXME: where si the data allocated? */
1849 arg->backend.reg3 = ainfo->reg;
1850 call->used_iregs |= 1 << ainfo->reg;
1851 g_assert_not_reached ();
1852 #endif
1853 break;
1854 case RegTypeStructByVal:
1855 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
1856 ins->opcode = OP_OUTARG_VT;
1857 ins->sreg1 = in->dreg;
1858 ins->klass = in->klass;
1859 ins->inst_p0 = call;
1860 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1861 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
1862 mono_call_inst_add_outarg_vt (cfg, call, ins);
1863 MONO_ADD_INS (cfg->cbb, ins);
1864 break;
1865 case RegTypeBase:
1866 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1867 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1868 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
1869 if (t->type == MONO_TYPE_R8) {
1870 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1871 } else {
1872 if (IS_SOFT_FLOAT)
1873 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1874 else
1875 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1876 }
1877 } else {
1878 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
1879 }
1880 break;
1881 case RegTypeBaseGen:
1882 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
1883 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? in->dreg + 1 : in->dreg + 2);
1884 MONO_INST_NEW (cfg, ins, OP_MOVE);
1885 ins->dreg = mono_alloc_ireg (cfg);
1886 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? in->dreg + 2 : in->dreg + 1;
1887 MONO_ADD_INS (cfg->cbb, ins);
1888 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
1889 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
1890 int creg;
1891
1892 /* This should work for soft-float as well */
1893
1894 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
1895 creg = mono_alloc_ireg (cfg);
1896 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
1897 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
1898 creg = mono_alloc_ireg (cfg);
1899 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
1900 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
1901 cfg->flags |= MONO_CFG_HAS_FPOUT;
1902 } else {
1903 g_assert_not_reached ();
1904 }
1905 break;
1906 case RegTypeFP: {
1907 /* FIXME: */
1908 NOT_IMPLEMENTED;
1909 #if 0
1910 arg->backend.reg3 = ainfo->reg;
1911 /* FP args are passed in int regs */
1912 call->used_iregs |= 1 << ainfo->reg;
1913 if (ainfo->size == 8) {
1914 arg->opcode = OP_OUTARG_R8;
1915 call->used_iregs |= 1 << (ainfo->reg + 1);
1916 } else {
1917 arg->opcode = OP_OUTARG_R4;
1918 }
1919 #endif
1920 cfg->flags |= MONO_CFG_HAS_FPOUT;
1921 break;
1922 }
1923 default:
1924 g_assert_not_reached ();
1925 }
1926 }
1927
1928 /* Handle the case where there are no implicit arguments */
1929 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1930 emit_sig_cookie (cfg, call, cinfo);
1931
1932 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1933 MonoInst *vtarg;
1934
1935 if (cinfo->ret.storage == RegTypeStructByVal) {
1936 /* The JIT will transform this into a normal call */
1937 call->vret_in_reg = TRUE;
1938 } else {
1939 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1940 vtarg->sreg1 = call->vret_var->dreg;
1941 vtarg->dreg = mono_alloc_preg (cfg);
1942 MONO_ADD_INS (cfg->cbb, vtarg);
1943
1944 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1945 }
1946 }
1947
1948 call->stack_usage = cinfo->stack_usage;
1949
1950 g_free (cinfo);
1951 }
1952
1953 void
1954 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1955 {
1956 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1957 ArgInfo *ainfo = ins->inst_p1;
1958 int ovf_size = ainfo->vtsize;
1959 int doffset = ainfo->offset;
1960 int struct_size = ainfo->struct_size;
1961 int i, soffset, dreg, tmpreg;
1962
1963 soffset = 0;
1964 for (i = 0; i < ainfo->size; ++i) {
1965 dreg = mono_alloc_ireg (cfg);
1966 switch (struct_size) {
1967 case 1:
1968 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1969 break;
1970 case 2:
1971 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
1972 break;
1973 case 3:
1974 tmpreg = mono_alloc_ireg (cfg);
1975 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
1976 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
1977 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
1978 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1979 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
1980 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
1981 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
1982 break;
1983 default:
1984 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
1985 break;
1986 }
1987 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
1988 soffset += sizeof (gpointer);
1989 struct_size -= sizeof (gpointer);
1990 }
1991 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
1992 if (ovf_size != 0)
1993 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
1994 }
1995
1996 void
1997 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1998 {
1999 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
2000
2001 if (!ret->byref) {
2002 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2003 MonoInst *ins;
2004
2005 if (COMPILE_LLVM (cfg)) {
2006 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2007 } else {
2008 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2009 ins->sreg1 = val->dreg + 1;
2010 ins->sreg2 = val->dreg + 2;
2011 MONO_ADD_INS (cfg->cbb, ins);
2012 }
2013 return;
2014 }
2015 switch (arm_fpu) {
2016 case MONO_ARM_FPU_NONE:
2017 if (ret->type == MONO_TYPE_R8) {
2018 MonoInst *ins;
2019
2020 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2021 ins->dreg = cfg->ret->dreg;
2022 ins->sreg1 = val->dreg;
2023 MONO_ADD_INS (cfg->cbb, ins);
2024 return;
2025 }
2026 if (ret->type == MONO_TYPE_R4) {
2027 /* Already converted to an int in method_to_ir () */
2028 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2029 return;
2030 }
2031 break;
2032 case MONO_ARM_FPU_VFP:
2033 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2034 MonoInst *ins;
2035
2036 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2037 ins->dreg = cfg->ret->dreg;
2038 ins->sreg1 = val->dreg;
2039 MONO_ADD_INS (cfg->cbb, ins);
2040 return;
2041 }
2042 break;
2043 case MONO_ARM_FPU_FPA:
2044 if (ret->type == MONO_TYPE_R4 || ret->type == MONO_TYPE_R8) {
2045 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2046 return;
2047 }
2048 break;
2049 default:
2050 g_assert_not_reached ();
2051 }
2052 }
2053
2054 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2055 }
2056
2057 #endif /* #ifndef DISABLE_JIT */
2058
2059 gboolean
2060 mono_arch_is_inst_imm (gint64 imm)
2061 {
2062 return TRUE;
2063 }
2064
2065 #define DYN_CALL_STACK_ARGS 6
2066
2067 typedef struct {
2068 MonoMethodSignature *sig;
2069 CallInfo *cinfo;
2070 } ArchDynCallInfo;
2071
2072 typedef struct {
2073 mgreg_t regs [PARAM_REGS + DYN_CALL_STACK_ARGS];
2074 mgreg_t res, res2;
2075 guint8 *ret;
2076 } DynCallArgs;
2077
2078 static gboolean
2079 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2080 {
2081 int i;
2082
2083 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2084 return FALSE;
2085
2086 switch (cinfo->ret.storage) {
2087 case RegTypeNone:
2088 case RegTypeGeneral:
2089 case RegTypeIRegPair:
2090 case RegTypeStructByAddr:
2091 break;
2092 case RegTypeFP:
2093 if (IS_FPA)
2094 return FALSE;
2095 else if (IS_VFP)
2096 break;
2097 else
2098 return FALSE;
2099 default:
2100 return FALSE;
2101 }
2102
2103 for (i = 0; i < cinfo->nargs; ++i) {
2104 switch (cinfo->args [i].storage) {
2105 case RegTypeGeneral:
2106 break;
2107 case RegTypeIRegPair:
2108 break;
2109 case RegTypeBase:
2110 if (cinfo->args [i].offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2111 return FALSE;
2112 break;
2113 case RegTypeStructByVal:
2114 if (cinfo->args [i].reg + cinfo->args [i].vtsize >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2115 return FALSE;
2116 break;
2117 default:
2118 return FALSE;
2119 }
2120 }
2121
2122 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2123 for (i = 0; i < sig->param_count; ++i) {
2124 MonoType *t = sig->params [i];
2125
2126 if (t->byref)
2127 continue;
2128
2129 switch (t->type) {
2130 case MONO_TYPE_R4:
2131 case MONO_TYPE_R8:
2132 if (IS_SOFT_FLOAT)
2133 return FALSE;
2134 else
2135 break;
2136 /*
2137 case MONO_TYPE_I8:
2138 case MONO_TYPE_U8:
2139 return FALSE;
2140 */
2141 default:
2142 break;
2143 }
2144 }
2145
2146 return TRUE;
2147 }
2148
2149 MonoDynCallInfo*
2150 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2151 {
2152 ArchDynCallInfo *info;
2153 CallInfo *cinfo;
2154
2155 cinfo = get_call_info (NULL, NULL, sig);
2156
2157 if (!dyn_call_supported (cinfo, sig)) {
2158 g_free (cinfo);
2159 return NULL;
2160 }
2161
2162 info = g_new0 (ArchDynCallInfo, 1);
2163 // FIXME: Preprocess the info to speed up start_dyn_call ()
2164 info->sig = sig;
2165 info->cinfo = cinfo;
2166
2167 return (MonoDynCallInfo*)info;
2168 }
2169
2170 void
2171 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2172 {
2173 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2174
2175 g_free (ainfo->cinfo);
2176 g_free (ainfo);
2177 }
2178
2179 void
2180 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2181 {
2182 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2183 DynCallArgs *p = (DynCallArgs*)buf;
2184 int arg_index, greg, i, j, pindex;
2185 MonoMethodSignature *sig = dinfo->sig;
2186
2187 g_assert (buf_len >= sizeof (DynCallArgs));
2188
2189 p->res = 0;
2190 p->ret = ret;
2191
2192 arg_index = 0;
2193 greg = 0;
2194 pindex = 0;
2195
2196 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2197 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2198 if (!sig->hasthis)
2199 pindex = 1;
2200 }
2201
2202 if (dinfo->cinfo->vtype_retaddr)
2203 p->regs [greg ++] = (mgreg_t)ret;
2204
2205 for (i = pindex; i < sig->param_count; i++) {
2206 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2207 gpointer *arg = args [arg_index ++];
2208 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2209 int slot = -1;
2210
2211 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal)
2212 slot = ainfo->reg;
2213 else if (ainfo->storage == RegTypeBase)
2214 slot = PARAM_REGS + (ainfo->offset / 4);
2215 else
2216 g_assert_not_reached ();
2217
2218 if (t->byref) {
2219 p->regs [slot] = (mgreg_t)*arg;
2220 continue;
2221 }
2222
2223 switch (t->type) {
2224 case MONO_TYPE_STRING:
2225 case MONO_TYPE_CLASS:
2226 case MONO_TYPE_ARRAY:
2227 case MONO_TYPE_SZARRAY:
2228 case MONO_TYPE_OBJECT:
2229 case MONO_TYPE_PTR:
2230 case MONO_TYPE_I:
2231 case MONO_TYPE_U:
2232 p->regs [slot] = (mgreg_t)*arg;
2233 break;
2234 case MONO_TYPE_BOOLEAN:
2235 case MONO_TYPE_U1:
2236 p->regs [slot] = *(guint8*)arg;
2237 break;
2238 case MONO_TYPE_I1:
2239 p->regs [slot] = *(gint8*)arg;
2240 break;
2241 case MONO_TYPE_I2:
2242 p->regs [slot] = *(gint16*)arg;
2243 break;
2244 case MONO_TYPE_U2:
2245 case MONO_TYPE_CHAR:
2246 p->regs [slot] = *(guint16*)arg;
2247 break;
2248 case MONO_TYPE_I4:
2249 p->regs [slot] = *(gint32*)arg;
2250 break;
2251 case MONO_TYPE_U4:
2252 p->regs [slot] = *(guint32*)arg;
2253 break;
2254 case MONO_TYPE_I8:
2255 case MONO_TYPE_U8:
2256 p->regs [slot ++] = (mgreg_t)arg [0];
2257 p->regs [slot] = (mgreg_t)arg [1];
2258 break;
2259 case MONO_TYPE_R4:
2260 p->regs [slot] = *(mgreg_t*)arg;
2261 break;
2262 case MONO_TYPE_R8:
2263 p->regs [slot ++] = (mgreg_t)arg [0];
2264 p->regs [slot] = (mgreg_t)arg [1];
2265 break;
2266 case MONO_TYPE_GENERICINST:
2267 if (MONO_TYPE_IS_REFERENCE (t)) {
2268 p->regs [slot] = (mgreg_t)*arg;
2269 break;
2270 } else {
2271 /* Fall though */
2272 }
2273 case MONO_TYPE_VALUETYPE:
2274 g_assert (ainfo->storage == RegTypeStructByVal);
2275
2276 if (ainfo->size == 0)
2277 slot = PARAM_REGS + (ainfo->offset / 4);
2278 else
2279 slot = ainfo->reg;
2280
2281 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2282 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2283 break;
2284 default:
2285 g_assert_not_reached ();
2286 }
2287 }
2288 }
2289
2290 void
2291 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2292 {
2293 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2294 MonoMethodSignature *sig = ((ArchDynCallInfo*)info)->sig;
2295 guint8 *ret = ((DynCallArgs*)buf)->ret;
2296 mgreg_t res = ((DynCallArgs*)buf)->res;
2297 mgreg_t res2 = ((DynCallArgs*)buf)->res2;
2298
2299 switch (mono_type_get_underlying_type (sig->ret)->type) {
2300 case MONO_TYPE_VOID:
2301 *(gpointer*)ret = NULL;
2302 break;
2303 case MONO_TYPE_STRING:
2304 case MONO_TYPE_CLASS:
2305 case MONO_TYPE_ARRAY:
2306 case MONO_TYPE_SZARRAY:
2307 case MONO_TYPE_OBJECT:
2308 case MONO_TYPE_I:
2309 case MONO_TYPE_U:
2310 case MONO_TYPE_PTR:
2311 *(gpointer*)ret = (gpointer)res;
2312 break;
2313 case MONO_TYPE_I1:
2314 *(gint8*)ret = res;
2315 break;
2316 case MONO_TYPE_U1:
2317 case MONO_TYPE_BOOLEAN:
2318 *(guint8*)ret = res;
2319 break;
2320 case MONO_TYPE_I2:
2321 *(gint16*)ret = res;
2322 break;
2323 case MONO_TYPE_U2:
2324 case MONO_TYPE_CHAR:
2325 *(guint16*)ret = res;
2326 break;
2327 case MONO_TYPE_I4:
2328 *(gint32*)ret = res;
2329 break;
2330 case MONO_TYPE_U4:
2331 *(guint32*)ret = res;
2332 break;
2333 case MONO_TYPE_I8:
2334 case MONO_TYPE_U8:
2335 /* This handles endianness as well */
2336 ((gint32*)ret) [0] = res;
2337 ((gint32*)ret) [1] = res2;
2338 break;
2339 case MONO_TYPE_GENERICINST:
2340 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2341 *(gpointer*)ret = (gpointer)res;
2342 break;
2343 } else {
2344 /* Fall though */
2345 }
2346 case MONO_TYPE_VALUETYPE:
2347 g_assert (ainfo->cinfo->vtype_retaddr);
2348 /* Nothing to do */
2349 break;
2350 case MONO_TYPE_R4:
2351 g_assert (IS_VFP);
2352 *(float*)ret = *(float*)&res;
2353 break;
2354 case MONO_TYPE_R8: {
2355 mgreg_t regs [2];
2356
2357 g_assert (IS_VFP);
2358 regs [0] = res;
2359 regs [1] = res2;
2360
2361 *(double*)ret = *(double*)&regs;
2362 break;
2363 }
2364 default:
2365 g_assert_not_reached ();
2366 }
2367 }
2368
2369 #ifndef DISABLE_JIT
2370
2371 /*
2372 * Allow tracing to work with this interface (with an optional argument)
2373 */
2374
2375 void*
2376 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2377 {
2378 guchar *code = p;
2379
2380 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2381 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
2382 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
2383 code = emit_call_reg (code, ARMREG_R2);
2384 return code;
2385 }
2386
2387 enum {
2388 SAVE_NONE,
2389 SAVE_STRUCT,
2390 SAVE_ONE,
2391 SAVE_TWO,
2392 SAVE_FP
2393 };
2394
2395 void*
2396 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2397 {
2398 guchar *code = p;
2399 int save_mode = SAVE_NONE;
2400 int offset;
2401 MonoMethod *method = cfg->method;
2402 int rtype = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type;
2403 int save_offset = cfg->param_area;
2404 save_offset += 7;
2405 save_offset &= ~7;
2406
2407 offset = code - cfg->native_code;
2408 /* we need about 16 instructions */
2409 if (offset > (cfg->code_size - 16 * 4)) {
2410 cfg->code_size *= 2;
2411 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2412 code = cfg->native_code + offset;
2413 }
2414 switch (rtype) {
2415 case MONO_TYPE_VOID:
2416 /* special case string .ctor icall */
2417 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
2418 save_mode = SAVE_ONE;
2419 else
2420 save_mode = SAVE_NONE;
2421 break;
2422 case MONO_TYPE_I8:
2423 case MONO_TYPE_U8:
2424 save_mode = SAVE_TWO;
2425 break;
2426 case MONO_TYPE_R4:
2427 case MONO_TYPE_R8:
2428 save_mode = SAVE_FP;
2429 break;
2430 case MONO_TYPE_VALUETYPE:
2431 save_mode = SAVE_STRUCT;
2432 break;
2433 default:
2434 save_mode = SAVE_ONE;
2435 break;
2436 }
2437
2438 switch (save_mode) {
2439 case SAVE_TWO:
2440 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2441 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2442 if (enable_arguments) {
2443 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
2444 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2445 }
2446 break;
2447 case SAVE_ONE:
2448 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2449 if (enable_arguments) {
2450 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2451 }
2452 break;
2453 case SAVE_FP:
2454 /* FIXME: what reg? */
2455 if (enable_arguments) {
2456 /* FIXME: what reg? */
2457 }
2458 break;
2459 case SAVE_STRUCT:
2460 if (enable_arguments) {
2461 /* FIXME: get the actual address */
2462 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
2463 }
2464 break;
2465 case SAVE_NONE:
2466 default:
2467 break;
2468 }
2469
2470 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
2471 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
2472 code = emit_call_reg (code, ARMREG_IP);
2473
2474 switch (save_mode) {
2475 case SAVE_TWO:
2476 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2477 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
2478 break;
2479 case SAVE_ONE:
2480 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
2481 break;
2482 case SAVE_FP:
2483 /* FIXME */
2484 break;
2485 case SAVE_NONE:
2486 default:
2487 break;
2488 }
2489
2490 return code;
2491 }
2492
2493 /*
2494 * The immediate field for cond branches is big enough for all reasonable methods
2495 */
2496 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
2497 if (0 && ins->inst_true_bb->native_offset) { \
2498 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
2499 } else { \
2500 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2501 ARM_B_COND (code, (condcode), 0); \
2502 }
2503
2504 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
2505
2506 /* emit an exception if condition is fail
2507 *
2508 * We assign the extra code used to throw the implicit exceptions
2509 * to cfg->bb_exit as far as the big branch handling is concerned
2510 */
2511 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
2512 do { \
2513 mono_add_patch_info (cfg, code - cfg->native_code, \
2514 MONO_PATCH_INFO_EXC, exc_name); \
2515 ARM_BL_COND (code, (condcode), 0); \
2516 } while (0);
2517
2518 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
2519
2520 void
2521 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2522 {
2523 }
2524
2525 void
2526 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2527 {
2528 MonoInst *ins, *n, *last_ins = NULL;
2529
2530 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2531 switch (ins->opcode) {
2532 case OP_MUL_IMM:
2533 case OP_IMUL_IMM:
2534 /* Already done by an arch-independent pass */
2535 break;
2536 case OP_LOAD_MEMBASE:
2537 case OP_LOADI4_MEMBASE:
2538 /*
2539 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2540 * OP_LOAD_MEMBASE offset(basereg), reg
2541 */
2542 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
2543 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2544 ins->inst_basereg == last_ins->inst_destbasereg &&
2545 ins->inst_offset == last_ins->inst_offset) {
2546 if (ins->dreg == last_ins->sreg1) {
2547 MONO_DELETE_INS (bb, ins);
2548 continue;
2549 } else {
2550 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2551 ins->opcode = OP_MOVE;
2552 ins->sreg1 = last_ins->sreg1;
2553 }
2554
2555 /*
2556 * Note: reg1 must be different from the basereg in the second load
2557 * OP_LOAD_MEMBASE offset(basereg), reg1
2558 * OP_LOAD_MEMBASE offset(basereg), reg2
2559 * -->
2560 * OP_LOAD_MEMBASE offset(basereg), reg1
2561 * OP_MOVE reg1, reg2
2562 */
2563 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2564 || last_ins->opcode == OP_LOAD_MEMBASE) &&
2565 ins->inst_basereg != last_ins->dreg &&
2566 ins->inst_basereg == last_ins->inst_basereg &&
2567 ins->inst_offset == last_ins->inst_offset) {
2568
2569 if (ins->dreg == last_ins->dreg) {
2570 MONO_DELETE_INS (bb, ins);
2571 continue;
2572 } else {
2573 ins->opcode = OP_MOVE;
2574 ins->sreg1 = last_ins->dreg;
2575 }
2576
2577 //g_assert_not_reached ();
2578
2579 #if 0
2580 /*
2581 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2582 * OP_LOAD_MEMBASE offset(basereg), reg
2583 * -->
2584 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2585 * OP_ICONST reg, imm
2586 */
2587 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2588 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2589 ins->inst_basereg == last_ins->inst_destbasereg &&
2590 ins->inst_offset == last_ins->inst_offset) {
2591 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2592 ins->opcode = OP_ICONST;
2593 ins->inst_c0 = last_ins->inst_imm;
2594 g_assert_not_reached (); // check this rule
2595 #endif
2596 }
2597 break;
2598 case OP_LOADU1_MEMBASE:
2599 case OP_LOADI1_MEMBASE:
2600 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2601 ins->inst_basereg == last_ins->inst_destbasereg &&
2602 ins->inst_offset == last_ins->inst_offset) {
2603 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
2604 ins->sreg1 = last_ins->sreg1;
2605 }
2606 break;
2607 case OP_LOADU2_MEMBASE:
2608 case OP_LOADI2_MEMBASE:
2609 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2610 ins->inst_basereg == last_ins->inst_destbasereg &&
2611 ins->inst_offset == last_ins->inst_offset) {
2612 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
2613 ins->sreg1 = last_ins->sreg1;
2614 }
2615 break;
2616 case OP_MOVE:
2617 ins->opcode = OP_MOVE;
2618 /*
2619 * OP_MOVE reg, reg
2620 */
2621 if (ins->dreg == ins->sreg1) {
2622 MONO_DELETE_INS (bb, ins);
2623 continue;
2624 }
2625 /*
2626 * OP_MOVE sreg, dreg
2627 * OP_MOVE dreg, sreg
2628 */
2629 if (last_ins && last_ins->opcode == OP_MOVE &&
2630 ins->sreg1 == last_ins->dreg &&
2631 ins->dreg == last_ins->sreg1) {
2632 MONO_DELETE_INS (bb, ins);
2633 continue;
2634 }
2635 break;
2636 }
2637 last_ins = ins;
2638 ins = ins->next;
2639 }
2640 bb->last_ins = last_ins;
2641 }
2642
2643 /*
2644 * the branch_cc_table should maintain the order of these
2645 * opcodes.
2646 case CEE_BEQ:
2647 case CEE_BGE:
2648 case CEE_BGT:
2649 case CEE_BLE:
2650 case CEE_BLT:
2651 case CEE_BNE_UN:
2652 case CEE_BGE_UN:
2653 case CEE_BGT_UN:
2654 case CEE_BLE_UN:
2655 case CEE_BLT_UN:
2656 */
2657 static const guchar
2658 branch_cc_table [] = {
2659 ARMCOND_EQ,
2660 ARMCOND_GE,
2661 ARMCOND_GT,
2662 ARMCOND_LE,
2663 ARMCOND_LT,
2664
2665 ARMCOND_NE,
2666 ARMCOND_HS,
2667 ARMCOND_HI,
2668 ARMCOND_LS,
2669 ARMCOND_LO
2670 };
2671
2672 #define ADD_NEW_INS(cfg,dest,op) do { \
2673 MONO_INST_NEW ((cfg), (dest), (op)); \
2674 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2675 } while (0)
2676
2677 static int
2678 map_to_reg_reg_op (int op)
2679 {
2680 switch (op) {
2681 case OP_ADD_IMM:
2682 return OP_IADD;
2683 case OP_SUB_IMM:
2684 return OP_ISUB;
2685 case OP_AND_IMM:
2686 return OP_IAND;
2687 case OP_COMPARE_IMM:
2688 return OP_COMPARE;
2689 case OP_ICOMPARE_IMM:
2690 return OP_ICOMPARE;
2691 case OP_ADDCC_IMM:
2692 return OP_ADDCC;
2693 case OP_ADC_IMM:
2694 return OP_ADC;
2695 case OP_SUBCC_IMM:
2696 return OP_SUBCC;
2697 case OP_SBB_IMM:
2698 return OP_SBB;
2699 case OP_OR_IMM:
2700 return OP_IOR;
2701 case OP_XOR_IMM:
2702 return OP_IXOR;
2703 case OP_LOAD_MEMBASE:
2704 return OP_LOAD_MEMINDEX;
2705 case OP_LOADI4_MEMBASE:
2706 return OP_LOADI4_MEMINDEX;
2707 case OP_LOADU4_MEMBASE:
2708 return OP_LOADU4_MEMINDEX;
2709 case OP_LOADU1_MEMBASE:
2710 return OP_LOADU1_MEMINDEX;
2711 case OP_LOADI2_MEMBASE:
2712 return OP_LOADI2_MEMINDEX;
2713 case OP_LOADU2_MEMBASE:
2714 return OP_LOADU2_MEMINDEX;
2715 case OP_LOADI1_MEMBASE:
2716 return OP_LOADI1_MEMINDEX;
2717 case OP_STOREI1_MEMBASE_REG:
2718 return OP_STOREI1_MEMINDEX;
2719 case OP_STOREI2_MEMBASE_REG:
2720 return OP_STOREI2_MEMINDEX;
2721 case OP_STOREI4_MEMBASE_REG:
2722 return OP_STOREI4_MEMINDEX;
2723 case OP_STORE_MEMBASE_REG:
2724 return OP_STORE_MEMINDEX;
2725 case OP_STORER4_MEMBASE_REG:
2726 return OP_STORER4_MEMINDEX;
2727 case OP_STORER8_MEMBASE_REG:
2728 return OP_STORER8_MEMINDEX;
2729 case OP_STORE_MEMBASE_IMM:
2730 return OP_STORE_MEMBASE_REG;
2731 case OP_STOREI1_MEMBASE_IMM:
2732 return OP_STOREI1_MEMBASE_REG;
2733 case OP_STOREI2_MEMBASE_IMM:
2734 return OP_STOREI2_MEMBASE_REG;
2735 case OP_STOREI4_MEMBASE_IMM:
2736 return OP_STOREI4_MEMBASE_REG;
2737 }
2738 g_assert_not_reached ();
2739 }
2740
2741 /*
2742 * Remove from the instruction list the instructions that can't be
2743 * represented with very simple instructions with no register
2744 * requirements.
2745 */
2746 void
2747 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2748 {
2749 MonoInst *ins, *temp, *last_ins = NULL;
2750 int rot_amount, imm8, low_imm;
2751
2752 MONO_BB_FOR_EACH_INS (bb, ins) {
2753 loop_start:
2754 switch (ins->opcode) {
2755 case OP_ADD_IMM:
2756 case OP_SUB_IMM:
2757 case OP_AND_IMM:
2758 case OP_COMPARE_IMM:
2759 case OP_ICOMPARE_IMM:
2760 case OP_ADDCC_IMM:
2761 case OP_ADC_IMM:
2762 case OP_SUBCC_IMM:
2763 case OP_SBB_IMM:
2764 case OP_OR_IMM:
2765 case OP_XOR_IMM:
2766 case OP_IADD_IMM:
2767 case OP_ISUB_IMM:
2768 case OP_IAND_IMM:
2769 case OP_IADC_IMM:
2770 case OP_ISBB_IMM:
2771 case OP_IOR_IMM:
2772 case OP_IXOR_IMM:
2773 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
2774 ADD_NEW_INS (cfg, temp, OP_ICONST);
2775 temp->inst_c0 = ins->inst_imm;
2776 temp->dreg = mono_alloc_ireg (cfg);
2777 ins->sreg2 = temp->dreg;
2778 ins->opcode = mono_op_imm_to_op (ins->opcode);
2779 }
2780 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
2781 goto loop_start;
2782 else
2783 break;
2784 case OP_MUL_IMM:
2785 case OP_IMUL_IMM:
2786 if (ins->inst_imm == 1) {
2787 ins->opcode = OP_MOVE;
2788 break;
2789 }
2790 if (ins->inst_imm == 0) {
2791 ins->opcode = OP_ICONST;
2792 ins->inst_c0 = 0;
2793 break;
2794 }
2795 imm8 = mono_is_power_of_two (ins->inst_imm);
2796 if (imm8 > 0) {
2797 ins->opcode = OP_SHL_IMM;
2798 ins->inst_imm = imm8;
2799 break;
2800 }
2801 ADD_NEW_INS (cfg, temp, OP_ICONST);
2802 temp->inst_c0 = ins->inst_imm;
2803 temp->dreg = mono_alloc_ireg (cfg);
2804 ins->sreg2 = temp->dreg;
2805 ins->opcode = OP_IMUL;
2806 break;
2807 case OP_SBB:
2808 case OP_ISBB:
2809 case OP_SUBCC:
2810 case OP_ISUBCC:
2811 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2812 /* ARM sets the C flag to 1 if there was _no_ overflow */
2813 ins->next->opcode = OP_COND_EXC_NC;
2814 break;
2815 case OP_LOCALLOC_IMM:
2816 ADD_NEW_INS (cfg, temp, OP_ICONST);
2817 temp->inst_c0 = ins->inst_imm;
2818 temp->dreg = mono_alloc_ireg (cfg);
2819 ins->sreg1 = temp->dreg;
2820 ins->opcode = OP_LOCALLOC;
2821 break;
2822 case OP_LOAD_MEMBASE:
2823 case OP_LOADI4_MEMBASE:
2824 case OP_LOADU4_MEMBASE:
2825 case OP_LOADU1_MEMBASE:
2826 /* we can do two things: load the immed in a register
2827 * and use an indexed load, or see if the immed can be
2828 * represented as an ad_imm + a load with a smaller offset
2829 * that fits. We just do the first for now, optimize later.
2830 */
2831 if (arm_is_imm12 (ins->inst_offset))
2832 break;
2833 ADD_NEW_INS (cfg, temp, OP_ICONST);
2834 temp->inst_c0 = ins->inst_offset;
2835 temp->dreg = mono_alloc_ireg (cfg);
2836 ins->sreg2 = temp->dreg;
2837 ins->opcode = map_to_reg_reg_op (ins->opcode);
2838 break;
2839 case OP_LOADI2_MEMBASE:
2840 case OP_LOADU2_MEMBASE:
2841 case OP_LOADI1_MEMBASE:
2842 if (arm_is_imm8 (ins->inst_offset))
2843 break;
2844 ADD_NEW_INS (cfg, temp, OP_ICONST);
2845 temp->inst_c0 = ins->inst_offset;
2846 temp->dreg = mono_alloc_ireg (cfg);
2847 ins->sreg2 = temp->dreg;
2848 ins->opcode = map_to_reg_reg_op (ins->opcode);
2849 break;
2850 case OP_LOADR4_MEMBASE:
2851 case OP_LOADR8_MEMBASE:
2852 if (arm_is_fpimm8 (ins->inst_offset))
2853 break;
2854 low_imm = ins->inst_offset & 0x1ff;
2855 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
2856 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2857 temp->inst_imm = ins->inst_offset & ~0x1ff;
2858 temp->sreg1 = ins->inst_basereg;
2859 temp->dreg = mono_alloc_ireg (cfg);
2860 ins->inst_basereg = temp->dreg;
2861 ins->inst_offset = low_imm;
2862 } else {
2863 MonoInst *add_ins;
2864
2865 ADD_NEW_INS (cfg, temp, OP_ICONST);
2866 temp->inst_c0 = ins->inst_offset;
2867 temp->dreg = mono_alloc_ireg (cfg);
2868
2869 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2870 add_ins->sreg1 = ins->inst_basereg;
2871 add_ins->sreg2 = temp->dreg;
2872 add_ins->dreg = mono_alloc_ireg (cfg);
2873
2874 ins->inst_basereg = add_ins->dreg;
2875 ins->inst_offset = 0;
2876 }
2877 break;
2878 case OP_STORE_MEMBASE_REG:
2879 case OP_STOREI4_MEMBASE_REG:
2880 case OP_STOREI1_MEMBASE_REG:
2881 if (arm_is_imm12 (ins->inst_offset))
2882 break;
2883 ADD_NEW_INS (cfg, temp, OP_ICONST);
2884 temp->inst_c0 = ins->inst_offset;
2885 temp->dreg = mono_alloc_ireg (cfg);
2886 ins->sreg2 = temp->dreg;
2887 ins->opcode = map_to_reg_reg_op (ins->opcode);
2888 break;
2889 case OP_STOREI2_MEMBASE_REG:
2890 if (arm_is_imm8 (ins->inst_offset))
2891 break;
2892 ADD_NEW_INS (cfg, temp, OP_ICONST);
2893 temp->inst_c0 = ins->inst_offset;
2894 temp->dreg = mono_alloc_ireg (cfg);
2895 ins->sreg2 = temp->dreg;
2896 ins->opcode = map_to_reg_reg_op (ins->opcode);
2897 break;
2898 case OP_STORER4_MEMBASE_REG:
2899 case OP_STORER8_MEMBASE_REG:
2900 if (arm_is_fpimm8 (ins->inst_offset))
2901 break;
2902 low_imm = ins->inst_offset & 0x1ff;
2903 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
2904 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
2905 temp->inst_imm = ins->inst_offset & ~0x1ff;
2906 temp->sreg1 = ins->inst_destbasereg;
2907 temp->dreg = mono_alloc_ireg (cfg);
2908 ins->inst_destbasereg = temp->dreg;
2909 ins->inst_offset = low_imm;
2910 } else {
2911 MonoInst *add_ins;
2912
2913 ADD_NEW_INS (cfg, temp, OP_ICONST);
2914 temp->inst_c0 = ins->inst_offset;
2915 temp->dreg = mono_alloc_ireg (cfg);
2916
2917 ADD_NEW_INS (cfg, add_ins, OP_IADD);
2918 add_ins->sreg1 = ins->inst_destbasereg;
2919 add_ins->sreg2 = temp->dreg;
2920 add_ins->dreg = mono_alloc_ireg (cfg);
2921
2922 ins->inst_destbasereg = add_ins->dreg;
2923 ins->inst_offset = 0;
2924 }
2925 break;
2926 case OP_STORE_MEMBASE_IMM:
2927 case OP_STOREI1_MEMBASE_IMM:
2928 case OP_STOREI2_MEMBASE_IMM:
2929 case OP_STOREI4_MEMBASE_IMM:
2930 ADD_NEW_INS (cfg, temp, OP_ICONST);
2931 temp->inst_c0 = ins->inst_imm;
2932 temp->dreg = mono_alloc_ireg (cfg);
2933 ins->sreg1 = temp->dreg;
2934 ins->opcode = map_to_reg_reg_op (ins->opcode);
2935 last_ins = temp;
2936 goto loop_start; /* make it handle the possibly big ins->inst_offset */
2937 case OP_FCOMPARE: {
2938 gboolean swap = FALSE;
2939 int reg;
2940
2941 if (!ins->next) {
2942 /* Optimized away */
2943 NULLIFY_INS (ins);
2944 break;
2945 }
2946
2947 /* Some fp compares require swapped operands */
2948 switch (ins->next->opcode) {
2949 case OP_FBGT:
2950 ins->next->opcode = OP_FBLT;
2951 swap = TRUE;
2952 break;
2953 case OP_FBGT_UN:
2954 ins->next->opcode = OP_FBLT_UN;
2955 swap = TRUE;
2956 break;
2957 case OP_FBLE:
2958 ins->next->opcode = OP_FBGE;
2959 swap = TRUE;
2960 break;
2961 case OP_FBLE_UN:
2962 ins->next->opcode = OP_FBGE_UN;
2963 swap = TRUE;
2964 break;
2965 default:
2966 break;
2967 }
2968 if (swap) {
2969 reg = ins->sreg1;
2970 ins->sreg1 = ins->sreg2;
2971 ins->sreg2 = reg;
2972 }
2973 break;
2974 }
2975 }
2976
2977 last_ins = ins;
2978 }
2979 bb->last_ins = last_ins;
2980 bb->max_vreg = cfg->next_vreg;
2981 }
2982
2983 void
2984 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2985 {
2986 MonoInst *ins;
2987
2988 if (long_ins->opcode == OP_LNEG) {
2989 ins = long_ins;
2990 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, ins->dreg + 1, ins->sreg1 + 1, 0);
2991 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
2992 NULLIFY_INS (ins);
2993 }
2994 }
2995
2996 static guchar*
2997 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2998 {
2999 /* sreg is a float, dreg is an integer reg */
3000 if (IS_FPA)
3001 ARM_FPA_FIXZ (code, dreg, sreg);
3002 else if (IS_VFP) {
3003 if (is_signed)
3004 ARM_TOSIZD (code, ARM_VFP_F0, sreg);
3005 else
3006 ARM_TOUIZD (code, ARM_VFP_F0, sreg);
3007 ARM_FMRS (code, dreg, ARM_VFP_F0);
3008 }
3009 if (!is_signed) {
3010 if (size == 1)
3011 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3012 else if (size == 2) {
3013 ARM_SHL_IMM (code, dreg, dreg, 16);
3014 ARM_SHR_IMM (code, dreg, dreg, 16);
3015 }
3016 } else {
3017 if (size == 1) {
3018 ARM_SHL_IMM (code, dreg, dreg, 24);
3019 ARM_SAR_IMM (code, dreg, dreg, 24);
3020 } else if (size == 2) {
3021 ARM_SHL_IMM (code, dreg, dreg, 16);
3022 ARM_SAR_IMM (code, dreg, dreg, 16);
3023 }
3024 }
3025 return code;
3026 }
3027
3028 #endif /* #ifndef DISABLE_JIT */
3029
3030 typedef struct {
3031 guchar *code;
3032 const guchar *target;
3033 int absolute;
3034 int found;
3035 } PatchData;
3036
3037 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3038
3039 static int
3040 search_thunk_slot (void *data, int csize, int bsize, void *user_data) {
3041 PatchData *pdata = (PatchData*)user_data;
3042 guchar *code = data;
3043 guint32 *thunks = data;
3044 guint32 *endthunks = (guint32*)(code + bsize);
3045 int count = 0;
3046 int difflow, diffhigh;
3047
3048 /* always ensure a call from pdata->code can reach to the thunks without further thunks */
3049 difflow = (char*)pdata->code - (char*)thunks;
3050 diffhigh = (char*)pdata->code - (char*)endthunks;
3051 if (!((is_call_imm (thunks) && is_call_imm (endthunks)) || (is_call_imm (difflow) && is_call_imm (diffhigh))))
3052 return 0;
3053
3054 /*
3055 * The thunk is composed of 3 words:
3056 * load constant from thunks [2] into ARM_IP
3057 * bx to ARM_IP
3058 * address constant
3059 * Note that the LR register is already setup
3060 */
3061 //g_print ("thunk nentries: %d\n", ((char*)endthunks - (char*)thunks)/16);
3062 if ((pdata->found == 2) || (pdata->code >= code && pdata->code <= code + csize)) {
3063 while (thunks < endthunks) {
3064 //g_print ("looking for target: %p at %p (%08x-%08x)\n", pdata->target, thunks, thunks [0], thunks [1]);
3065 if (thunks [2] == (guint32)pdata->target) {
3066 arm_patch (pdata->code, (guchar*)thunks);
3067 mono_arch_flush_icache (pdata->code, 4);
3068 pdata->found = 1;
3069 return 1;
3070 } else if ((thunks [0] == 0) && (thunks [1] == 0) && (thunks [2] == 0)) {
3071 /* found a free slot instead: emit thunk */
3072 /* ARMREG_IP is fine to use since this can't be an IMT call
3073 * which is indirect
3074 */
3075 code = (guchar*)thunks;
3076 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3077 if (thumb_supported)
3078 ARM_BX (code, ARMREG_IP);
3079 else
3080 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3081 thunks [2] = (guint32)pdata->target;
3082 mono_arch_flush_icache ((guchar*)thunks, 12);
3083
3084 arm_patch (pdata->code, (guchar*)thunks);
3085 mono_arch_flush_icache (pdata->code, 4);
3086 pdata->found = 1;
3087 return 1;
3088 }
3089 /* skip 12 bytes, the size of the thunk */
3090 thunks += 3;
3091 count++;
3092 }
3093 //g_print ("failed thunk lookup for %p from %p at %p (%d entries)\n", pdata->target, pdata->code, data, count);
3094 }
3095 return 0;
3096 }
3097
3098 static void
3099 handle_thunk (MonoDomain *domain, int absolute, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3100 {
3101 PatchData pdata;
3102
3103 if (!domain)
3104 domain = mono_domain_get ();
3105
3106 pdata.code = code;
3107 pdata.target = target;
3108 pdata.absolute = absolute;
3109 pdata.found = 0;
3110
3111 if (dyn_code_mp) {
3112 mono_code_manager_foreach (dyn_code_mp, search_thunk_slot, &pdata);
3113 }
3114
3115 if (pdata.found != 1) {
3116 mono_domain_lock (domain);
3117 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3118
3119 if (!pdata.found) {
3120 /* this uses the first available slot */
3121 pdata.found = 2;
3122 mono_domain_code_foreach (domain, search_thunk_slot, &pdata);
3123 }
3124 mono_domain_unlock (domain);
3125 }
3126
3127 if (pdata.found != 1) {
3128 GHashTable *hash;
3129 GHashTableIter iter;
3130 MonoJitDynamicMethodInfo *ji;
3131
3132 /*
3133 * This might be a dynamic method, search its code manager. We can only
3134 * use the dynamic method containing CODE, since the others might be freed later.
3135 */
3136 pdata.found = 0;
3137
3138 mono_domain_lock (domain);
3139 hash = domain_jit_info (domain)->dynamic_code_hash;
3140 if (hash) {
3141 /* FIXME: Speed this up */
3142 g_hash_table_iter_init (&iter, hash);
3143 while (g_hash_table_iter_next (&iter, NULL, (gpointer*)&ji)) {
3144 mono_code_manager_foreach (ji->code_mp, search_thunk_slot, &pdata);
3145 if (pdata.found == 1)
3146 break;
3147 }
3148 }
3149 mono_domain_unlock (domain);
3150 }
3151 if (pdata.found != 1)
3152 g_print ("thunk failed for %p from %p\n", target, code);
3153 g_assert (pdata.found == 1);
3154 }
3155
3156 static void
3157 arm_patch_general (MonoDomain *domain, guchar *code, const guchar *target, MonoCodeManager *dyn_code_mp)
3158 {
3159 guint32 *code32 = (void*)code;
3160 guint32 ins = *code32;
3161 guint32 prim = (ins >> 25) & 7;
3162 guint32 tval = GPOINTER_TO_UINT (target);
3163
3164 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3165 if (prim == 5) { /* 101b */
3166 /* the diff starts 8 bytes from the branch opcode */
3167 gint diff = target - code - 8;
3168 gint tbits;
3169 gint tmask = 0xffffffff;
3170 if (tval & 1) { /* entering thumb mode */
3171 diff = target - 1 - code - 8;
3172 g_assert (thumb_supported);
3173 tbits = 0xf << 28; /* bl->blx bit pattern */
3174 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3175 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3176 if (diff & 2) {
3177 tbits |= 1 << 24;
3178 }
3179 tmask = ~(1 << 24); /* clear the link bit */
3180 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3181 } else {
3182 tbits = 0;
3183 }
3184 if (diff >= 0) {
3185 if (diff <= 33554431) {
3186 diff >>= 2;
3187 ins = (ins & 0xff000000) | diff;
3188 ins &= tmask;
3189 *code32 = ins | tbits;
3190 return;
3191 }
3192 } else {
3193 /* diff between 0 and -33554432 */
3194 if (diff >= -33554432) {
3195 diff >>= 2;
3196 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3197 ins &= tmask;
3198 *code32 = ins | tbits;
3199 return;
3200 }
3201 }
3202
3203 handle_thunk (domain, TRUE, code, target, dyn_code_mp);
3204 return;
3205 }
3206
3207 /*
3208 * The alternative call sequences looks like this:
3209 *
3210 * ldr ip, [pc] // loads the address constant
3211 * b 1f // jumps around the constant
3212 * address constant embedded in the code
3213 * 1f:
3214 * mov lr, pc
3215 * mov pc, ip
3216 *
3217 * There are two cases for patching:
3218 * a) at the end of method emission: in this case code points to the start
3219 * of the call sequence
3220 * b) during runtime patching of the call site: in this case code points
3221 * to the mov pc, ip instruction
3222 *
3223 * We have to handle also the thunk jump code sequence:
3224 *
3225 * ldr ip, [pc]
3226 * mov pc, ip
3227 * address constant // execution never reaches here
3228 */
3229 if ((ins & 0x0ffffff0) == 0x12fff10) {
3230 /* Branch and exchange: the address is constructed in a reg
3231 * We can patch BX when the code sequence is the following:
3232 * ldr ip, [pc, #0] ; 0x8
3233 * b 0xc
3234 * .word code_ptr
3235 * mov lr, pc
3236 * bx ips
3237 * */
3238 guint32 ccode [4];
3239 guint8 *emit = (guint8*)ccode;
3240 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3241 ARM_B (emit, 0);
3242 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3243 ARM_BX (emit, ARMREG_IP);
3244
3245 /*patching from magic trampoline*/
3246 if (ins == ccode [3]) {
3247 g_assert (code32 [-4] == ccode [0]);
3248 g_assert (code32 [-3] == ccode [1]);
3249 g_assert (code32 [-1] == ccode [2]);
3250 code32 [-2] = (guint32)target;
3251 return;
3252 }
3253 /*patching from JIT*/
3254 if (ins == ccode [0]) {
3255 g_assert (code32 [1] == ccode [1]);
3256 g_assert (code32 [3] == ccode [2]);
3257 g_assert (code32 [4] == ccode [3]);
3258 code32 [2] = (guint32)target;
3259 return;
3260 }
3261 g_assert_not_reached ();
3262 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3263 /*
3264 * ldr ip, [pc, #0]
3265 * b 0xc
3266 * .word code_ptr
3267 * blx ip
3268 */
3269 guint32 ccode [4];
3270 guint8 *emit = (guint8*)ccode;
3271 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3272 ARM_B (emit, 0);
3273 ARM_BLX_REG (emit, ARMREG_IP);
3274
3275 g_assert (code32 [-3] == ccode [0]);
3276 g_assert (code32 [-2] == ccode [1]);
3277 g_assert (code32 [0] == ccode [2]);
3278
3279 code32 [-1] = (guint32)target;
3280 } else {
3281 guint32 ccode [4];
3282 guint32 *tmp = ccode;
3283 guint8 *emit = (guint8*)tmp;
3284 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3285 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3286 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3287 ARM_BX (emit, ARMREG_IP);
3288 if (ins == ccode [2]) {
3289 g_assert_not_reached (); // should be -2 ...
3290 code32 [-1] = (guint32)target;
3291 return;
3292 }
3293 if (ins == ccode [0]) {
3294 /* handles both thunk jump code and the far call sequence */
3295 code32 [2] = (guint32)target;
3296 return;
3297 }
3298 g_assert_not_reached ();
3299 }
3300 // g_print ("patched with 0x%08x\n", ins);
3301 }
3302
3303 void
3304 arm_patch (guchar *code, const guchar *target)
3305 {
3306 arm_patch_general (NULL, code, target, NULL);
3307 }
3308
3309 /*
3310 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3311 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3312 * to be used with the emit macros.
3313 * Return -1 otherwise.
3314 */
3315 int
3316 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3317 {
3318 guint32 res, i;
3319 for (i = 0; i < 31; i+= 2) {
3320 res = (val << (32 - i)) | (val >> i);
3321 if (res & ~0xff)
3322 continue;
3323 *rot_amount = i? 32 - i: 0;
3324 return res;
3325 }
3326 return -1;
3327 }
3328
3329 /*
3330 * Emits in code a sequence of instructions that load the value 'val'
3331 * into the dreg register. Uses at most 4 instructions.
3332 */
3333 guint8*
3334 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
3335 {
3336 int imm8, rot_amount;
3337 #if 0
3338 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3339 /* skip the constant pool */
3340 ARM_B (code, 0);
3341 *(int*)code = val;
3342 code += 4;
3343 return code;
3344 #endif
3345 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
3346 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
3347 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
3348 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
3349 } else {
3350 if (v7_supported) {
3351 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
3352 if (val >> 16)
3353 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
3354 return code;
3355 }
3356 if (val & 0xFF) {
3357 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
3358 if (val & 0xFF00) {
3359 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3360 }
3361 if (val & 0xFF0000) {
3362 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3363 }
3364 if (val & 0xFF000000) {
3365 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3366 }
3367 } else if (val & 0xFF00) {
3368 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
3369 if (val & 0xFF0000) {
3370 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3371 }
3372 if (val & 0xFF000000) {
3373 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3374 }
3375 } else if (val & 0xFF0000) {
3376 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
3377 if (val & 0xFF000000) {
3378 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
3379 }
3380 }
3381 //g_assert_not_reached ();
3382 }
3383 return code;
3384 }
3385
3386 gboolean
3387 mono_arm_thumb_supported (void)
3388 {
3389 return thumb_supported;
3390 }
3391
3392 #ifndef DISABLE_JIT
3393
3394 /*
3395 * emit_load_volatile_arguments:
3396 *
3397 * Load volatile arguments from the stack to the original input registers.
3398 * Required before a tail call.
3399 */
3400 static guint8*
3401 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3402 {
3403 MonoMethod *method = cfg->method;
3404 MonoMethodSignature *sig;
3405 MonoInst *inst;
3406 CallInfo *cinfo;
3407 guint32 i, pos;
3408
3409 /* FIXME: Generate intermediate code instead */
3410
3411 sig = mono_method_signature (method);
3412
3413 /* This is the opposite of the code in emit_prolog */
3414
3415 pos = 0;
3416
3417 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
3418
3419 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
3420 ArgInfo *ainfo = &cinfo->ret;
3421 inst = cfg->vret_addr;
3422 g_assert (arm_is_imm12 (inst->inst_offset));
3423 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3424 }
3425 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3426 ArgInfo *ainfo = cinfo->args + i;
3427 inst = cfg->args [pos];
3428
3429 if (cfg->verbose_level > 2)
3430 g_print ("Loading argument %d (type: %d)\n", i, ainfo->storage);
3431 if (inst->opcode == OP_REGVAR) {
3432 if (ainfo->storage == RegTypeGeneral)
3433 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
3434 else if (ainfo->storage == RegTypeFP) {
3435 g_assert_not_reached ();
3436 } else if (ainfo->storage == RegTypeBase) {
3437 // FIXME:
3438 NOT_IMPLEMENTED;
3439 /*
3440 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
3441 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
3442 } else {
3443 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3444 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
3445 }
3446 */
3447 } else
3448 g_assert_not_reached ();
3449 } else {
3450 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
3451 switch (ainfo->size) {
3452 case 1:
3453 case 2:
3454 // FIXME:
3455 NOT_IMPLEMENTED;
3456 break;
3457 case 8:
3458 g_assert (arm_is_imm12 (inst->inst_offset));
3459 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3460 g_assert (arm_is_imm12 (inst->inst_offset + 4));
3461 ARM_LDR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3462 break;
3463 default:
3464 if (arm_is_imm12 (inst->inst_offset)) {
3465 ARM_LDR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3466 } else {
3467 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
3468 ARM_LDR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
3469 }
3470 break;
3471 }
3472 } else if (ainfo->storage == RegTypeBaseGen) {
3473 // FIXME:
3474 NOT_IMPLEMENTED;
3475 } else if (ainfo->storage == RegTypeBase) {
3476 /* Nothing to do */
3477 } else if (ainfo->storage == RegTypeFP) {
3478 g_assert_not_reached ();
3479 } else if (ainfo->storage == RegTypeStructByVal) {
3480 int doffset = inst->inst_offset;
3481 int soffset = 0;
3482 int cur_reg;
3483 int size = 0;
3484 if (mono_class_from_mono_type (inst->inst_vtype))
3485 size = mono_class_native_size (mono_class_from_mono_type (inst->inst_vtype), NULL);
3486 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
3487 if (arm_is_imm12 (doffset)) {
3488 ARM_LDR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
3489 } else {
3490 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
3491 ARM_LDR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
3492 }
3493 soffset += sizeof (gpointer);
3494 doffset += sizeof (gpointer);
3495 }
3496 if (ainfo->vtsize)
3497 // FIXME:
3498 NOT_IMPLEMENTED;
3499 } else if (ainfo->storage == RegTypeStructByAddr) {
3500 } else {
3501 // FIXME:
3502 NOT_IMPLEMENTED;
3503 }
3504 }
3505 pos ++;
3506 }
3507
3508 g_free (cinfo);
3509
3510 return code;
3511 }
3512
3513 void
3514 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3515 {
3516 MonoInst *ins;
3517 MonoCallInst *call;
3518 guint offset;
3519 guint8 *code = cfg->native_code + cfg->code_len;
3520 MonoInst *last_ins = NULL;
3521 guint last_offset = 0;
3522 int max_len, cpos;
3523 int imm8, rot_amount;
3524
3525 /* we don't align basic blocks of loops on arm */
3526
3527 if (cfg->verbose_level > 2)
3528 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3529
3530 cpos = bb->max_offset;
3531
3532 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3533 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
3534 //g_assert (!mono_compile_aot);
3535 //cpos += 6;
3536 //if (bb->cil_code)
3537 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
3538 /* this is not thread save, but good enough */
3539 /* fixme: howto handle overflows? */
3540 //x86_inc_mem (code, &cov->data [bb->dfn].count);
3541 }
3542
3543 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
3544 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3545 (gpointer)"mono_break");
3546 code = emit_call_seq (cfg, code);
3547 }
3548
3549 MONO_BB_FOR_EACH_INS (bb, ins) {
3550 offset = code - cfg->native_code;
3551
3552 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3553
3554 if (offset > (cfg->code_size - max_len - 16)) {
3555 cfg->code_size *= 2;
3556 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3557 code = cfg->native_code + offset;
3558 }
3559 // if (ins->cil_code)
3560 // g_print ("cil code\n");
3561 mono_debug_record_line_number (cfg, ins, offset);
3562
3563 switch (ins->opcode) {
3564 case OP_MEMORY_BARRIER:
3565 if (v6_supported) {
3566 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
3567 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
3568 }
3569 break;
3570 case OP_TLS_GET:
3571 #ifdef HAVE_AEABI_READ_TP
3572 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3573 (gpointer)"__aeabi_read_tp");
3574 code = emit_call_seq (cfg, code);
3575
3576 ARM_LDR_IMM (code, ins->dreg, ARMREG_R0, ins->inst_offset);
3577 #else
3578 g_assert_not_reached ();
3579 #endif
3580 break;
3581 /*case OP_BIGMUL:
3582 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3583 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
3584 break;
3585 case OP_BIGMUL_UN:
3586 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
3587 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
3588 break;*/
3589 case OP_STOREI1_MEMBASE_IMM:
3590 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
3591 g_assert (arm_is_imm12 (ins->inst_offset));
3592 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3593 break;
3594 case OP_STOREI2_MEMBASE_IMM:
3595 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
3596 g_assert (arm_is_imm8 (ins->inst_offset));
3597 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3598 break;
3599 case OP_STORE_MEMBASE_IMM:
3600 case OP_STOREI4_MEMBASE_IMM:
3601 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
3602 g_assert (arm_is_imm12 (ins->inst_offset));
3603 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3604 break;
3605 case OP_STOREI1_MEMBASE_REG:
3606 g_assert (arm_is_imm12 (ins->inst_offset));
3607 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3608 break;
3609 case OP_STOREI2_MEMBASE_REG:
3610 g_assert (arm_is_imm8 (ins->inst_offset));
3611 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3612 break;
3613 case OP_STORE_MEMBASE_REG:
3614 case OP_STOREI4_MEMBASE_REG:
3615 /* this case is special, since it happens for spill code after lowering has been called */
3616 if (arm_is_imm12 (ins->inst_offset)) {
3617 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3618 } else {
3619 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3620 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
3621 }
3622 break;
3623 case OP_STOREI1_MEMINDEX:
3624 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3625 break;
3626 case OP_STOREI2_MEMINDEX:
3627 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3628 break;
3629 case OP_STORE_MEMINDEX:
3630 case OP_STOREI4_MEMINDEX:
3631 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
3632 break;
3633 case OP_LOADU4_MEM:
3634 g_assert_not_reached ();
3635 break;
3636 case OP_LOAD_MEMINDEX:
3637 case OP_LOADI4_MEMINDEX:
3638 case OP_LOADU4_MEMINDEX:
3639 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3640 break;
3641 case OP_LOADI1_MEMINDEX:
3642 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3643 break;
3644 case OP_LOADU1_MEMINDEX:
3645 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3646 break;
3647 case OP_LOADI2_MEMINDEX:
3648 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3649 break;
3650 case OP_LOADU2_MEMINDEX:
3651 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
3652 break;
3653 case OP_LOAD_MEMBASE:
3654 case OP_LOADI4_MEMBASE:
3655 case OP_LOADU4_MEMBASE:
3656 /* this case is special, since it happens for spill code after lowering has been called */
3657 if (arm_is_imm12 (ins->inst_offset)) {
3658 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3659 } else {
3660 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
3661 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
3662 }
3663 break;
3664 case OP_LOADI1_MEMBASE:
3665 g_assert (arm_is_imm8 (ins->inst_offset));
3666 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3667 break;
3668 case OP_LOADU1_MEMBASE:
3669 g_assert (arm_is_imm12 (ins->inst_offset));
3670 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3671 break;
3672 case OP_LOADU2_MEMBASE:
3673 g_assert (arm_is_imm8 (ins->inst_offset));
3674 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3675 break;
3676 case OP_LOADI2_MEMBASE:
3677 g_assert (arm_is_imm8 (ins->inst_offset));
3678 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3679 break;
3680 case OP_ICONV_TO_I1:
3681 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
3682 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
3683 break;
3684 case OP_ICONV_TO_I2:
3685 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3686 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
3687 break;
3688 case OP_ICONV_TO_U1:
3689 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
3690 break;
3691 case OP_ICONV_TO_U2:
3692 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
3693 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
3694 break;
3695 case OP_COMPARE:
3696 case OP_ICOMPARE:
3697 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
3698 break;
3699 case OP_COMPARE_IMM:
3700 case OP_ICOMPARE_IMM:
3701 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3702 g_assert (imm8 >= 0);
3703 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
3704 break;
3705 case OP_BREAK:
3706 /*
3707 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3708 * So instead of emitting a trap, we emit a call a C function and place a
3709 * breakpoint there.
3710 */
3711 //*(int*)code = 0xef9f0001;
3712 //code += 4;
3713 //ARM_DBRK (code);
3714 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3715 (gpointer)"mono_break");
3716 code = emit_call_seq (cfg, code);
3717 break;
3718 case OP_RELAXED_NOP:
3719 ARM_NOP (code);
3720 break;
3721 case OP_NOP:
3722 case OP_DUMMY_USE:
3723 case OP_DUMMY_STORE:
3724 case OP_NOT_REACHED:
3725 case OP_NOT_NULL:
3726 break;
3727 case OP_SEQ_POINT: {
3728 int i;
3729 MonoInst *info_var = cfg->arch.seq_point_info_var;
3730 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
3731 MonoInst *ss_read_var = cfg->arch.seq_point_read_var;
3732 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
3733 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
3734 MonoInst *var;
3735 int dreg = ARMREG_LR;
3736
3737 if (cfg->soft_breakpoints) {
3738 g_assert (!cfg->compile_aot);
3739 }
3740
3741 /*
3742 * For AOT, we use one got slot per method, which will point to a
3743 * SeqPointInfo structure, containing all the information required
3744 * by the code below.
3745 */
3746 if (cfg->compile_aot) {
3747 g_assert (info_var);
3748 g_assert (info_var->opcode == OP_REGOFFSET);
3749 g_assert (arm_is_imm12 (info_var->inst_offset));
3750 }
3751
3752 if (!cfg->soft_breakpoints) {
3753 /*
3754 * Read from the single stepping trigger page. This will cause a
3755 * SIGSEGV when single stepping is enabled.
3756 * We do this _before_ the breakpoint, so single stepping after
3757 * a breakpoint is hit will step to the next IL offset.
3758 */
3759 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
3760 }
3761
3762 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3763 if (cfg->soft_breakpoints) {
3764 /* Load the address of the sequence point trigger variable. */
3765 var = ss_read_var;
3766 g_assert (var);
3767 g_assert (var->opcode == OP_REGOFFSET);
3768 g_assert (arm_is_imm12 (var->inst_offset));
3769 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3770
3771 /* Read the value and check whether it is non-zero. */
3772 ARM_LDR_IMM (code, dreg, dreg, 0);
3773 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3774
3775 /* Load the address of the sequence point method. */
3776 var = ss_method_var;
3777 g_assert (var);
3778 g_assert (var->opcode == OP_REGOFFSET);
3779 g_assert (arm_is_imm12 (var->inst_offset));
3780 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3781
3782 /* Call it conditionally. */
3783 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
3784 } else {
3785 if (cfg->compile_aot) {
3786 /* Load the trigger page addr from the variable initialized in the prolog */
3787 var = ss_trigger_page_var;
3788 g_assert (var);
3789 g_assert (var->opcode == OP_REGOFFSET);
3790 g_assert (arm_is_imm12 (var->inst_offset));
3791 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3792 } else {
3793 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
3794 ARM_B (code, 0);
3795 *(int*)code = (int)ss_trigger_page;
3796 code += 4;
3797 }
3798 ARM_LDR_IMM (code, dreg, dreg, 0);
3799 }
3800 }
3801
3802 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3803
3804 if (cfg->soft_breakpoints) {
3805 /* Load the address of the breakpoint method into ip. */
3806 var = bp_method_var;
3807 g_assert (var);
3808 g_assert (var->opcode == OP_REGOFFSET);
3809 g_assert (arm_is_imm12 (var->inst_offset));
3810 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
3811
3812 /*
3813 * A placeholder for a possible breakpoint inserted by
3814 * mono_arch_set_breakpoint ().
3815 */
3816 ARM_NOP (code);
3817 } else if (cfg->compile_aot) {
3818 guint32 offset = code - cfg->native_code;
3819 guint32 val;
3820
3821 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
3822 /* Add the offset */
3823 val = ((offset / 4) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3824 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
3825 if (val & 0xFF00)
3826 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
3827 if (val & 0xFF0000)
3828 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
3829 g_assert (!(val & 0xFF000000));
3830 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
3831 ARM_LDR_IMM (code, dreg, dreg, 0);
3832
3833 /* What is faster, a branch or a load ? */
3834 ARM_CMP_REG_IMM (code, dreg, 0, 0);
3835 /* The breakpoint instruction */
3836 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
3837 } else {
3838 /*
3839 * A placeholder for a possible breakpoint inserted by
3840 * mono_arch_set_breakpoint ().
3841 */
3842 for (i = 0; i < 4; ++i)
3843 ARM_NOP (code);
3844 }
3845 break;
3846 }
3847 case OP_ADDCC:
3848 case OP_IADDCC:
3849 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3850 break;
3851 case OP_IADD:
3852 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3853 break;
3854 case OP_ADC:
3855 case OP_IADC:
3856 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3857 break;
3858 case OP_ADDCC_IMM:
3859 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3860 g_assert (imm8 >= 0);
3861 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3862 break;
3863 case OP_ADD_IMM:
3864 case OP_IADD_IMM:
3865 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3866 g_assert (imm8 >= 0);
3867 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3868 break;
3869 case OP_ADC_IMM:
3870 case OP_IADC_IMM:
3871 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3872 g_assert (imm8 >= 0);
3873 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3874 break;
3875 case OP_IADD_OVF:
3876 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3877 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3878 break;
3879 case OP_IADD_OVF_UN:
3880 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3881 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3882 break;
3883 case OP_ISUB_OVF:
3884 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3885 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3886 break;
3887 case OP_ISUB_OVF_UN:
3888 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3889 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3890 break;
3891 case OP_ADD_OVF_CARRY:
3892 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3893 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3894 break;
3895 case OP_ADD_OVF_UN_CARRY:
3896 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3897 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3898 break;
3899 case OP_SUB_OVF_CARRY:
3900 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3901 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
3902 break;
3903 case OP_SUB_OVF_UN_CARRY:
3904 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3905 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
3906 break;
3907 case OP_SUBCC:
3908 case OP_ISUBCC:
3909 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3910 break;
3911 case OP_SUBCC_IMM:
3912 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3913 g_assert (imm8 >= 0);
3914 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3915 break;
3916 case OP_ISUB:
3917 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3918 break;
3919 case OP_SBB:
3920 case OP_ISBB:
3921 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3922 break;
3923 case OP_SUB_IMM:
3924 case OP_ISUB_IMM:
3925 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3926 g_assert (imm8 >= 0);
3927 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3928 break;
3929 case OP_SBB_IMM:
3930 case OP_ISBB_IMM:
3931 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3932 g_assert (imm8 >= 0);
3933 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3934 break;
3935 case OP_ARM_RSBS_IMM:
3936 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3937 g_assert (imm8 >= 0);
3938 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3939 break;
3940 case OP_ARM_RSC_IMM:
3941 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3942 g_assert (imm8 >= 0);
3943 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3944 break;
3945 case OP_IAND:
3946 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3947 break;
3948 case OP_AND_IMM:
3949 case OP_IAND_IMM:
3950 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3951 g_assert (imm8 >= 0);
3952 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3953 break;
3954 case OP_IDIV:
3955 case OP_IDIV_UN:
3956 case OP_DIV_IMM:
3957 case OP_IREM:
3958 case OP_IREM_UN:
3959 case OP_REM_IMM:
3960 /* crappy ARM arch doesn't have a DIV instruction */
3961 g_assert_not_reached ();
3962 case OP_IOR:
3963 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3964 break;
3965 case OP_OR_IMM:
3966 case OP_IOR_IMM:
3967 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3968 g_assert (imm8 >= 0);
3969 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3970 break;
3971 case OP_IXOR:
3972 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3973 break;
3974 case OP_XOR_IMM:
3975 case OP_IXOR_IMM:
3976 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
3977 g_assert (imm8 >= 0);
3978 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
3979 break;
3980 case OP_ISHL:
3981 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3982 break;
3983 case OP_SHL_IMM:
3984 case OP_ISHL_IMM:
3985 if (ins->inst_imm)
3986 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3987 else if (ins->dreg != ins->sreg1)
3988 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3989 break;
3990 case OP_ISHR:
3991 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
3992 break;
3993 case OP_SHR_IMM:
3994 case OP_ISHR_IMM:
3995 if (ins->inst_imm)
3996 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
3997 else if (ins->dreg != ins->sreg1)
3998 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
3999 break;
4000 case OP_SHR_UN_IMM:
4001 case OP_ISHR_UN_IMM:
4002 if (ins->inst_imm)
4003 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4004 else if (ins->dreg != ins->sreg1)
4005 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4006 break;
4007 case OP_ISHR_UN:
4008 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4009 break;
4010 case OP_INOT:
4011 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4012 break;
4013 case OP_INEG:
4014 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4015 break;
4016 case OP_IMUL:
4017 if (ins->dreg == ins->sreg2)
4018 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4019 else
4020 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4021 break;
4022 case OP_MUL_IMM:
4023 g_assert_not_reached ();
4024 break;
4025 case OP_IMUL_OVF:
4026 /* FIXME: handle ovf/ sreg2 != dreg */
4027 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4028 /* FIXME: MUL doesn't set the C/O flags on ARM */
4029 break;
4030 case OP_IMUL_OVF_UN:
4031 /* FIXME: handle ovf/ sreg2 != dreg */
4032 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4033 /* FIXME: MUL doesn't set the C/O flags on ARM */
4034 break;
4035 case OP_ICONST:
4036 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4037 break;
4038 case OP_AOTCONST:
4039 /* Load the GOT offset */
4040 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4041 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4042 ARM_B (code, 0);
4043 *(gpointer*)code = NULL;
4044 code += 4;
4045 /* Load the value from the GOT */
4046 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4047 break;
4048 case OP_ICONV_TO_I4:
4049 case OP_ICONV_TO_U4:
4050 case OP_MOVE:
4051 if (ins->dreg != ins->sreg1)
4052 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4053 break;
4054 case OP_SETLRET: {
4055 int saved = ins->sreg2;
4056 if (ins->sreg2 == ARM_LSW_REG) {
4057 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4058 saved = ARMREG_LR;
4059 }
4060 if (ins->sreg1 != ARM_LSW_REG)
4061 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4062 if (saved != ARM_MSW_REG)
4063 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4064 break;
4065 }
4066 case OP_FMOVE:
4067 if (IS_FPA)
4068 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4069 else if (IS_VFP)
4070 ARM_CPYD (code, ins->dreg, ins->sreg1);
4071 break;
4072 case OP_FCONV_TO_R4:
4073 if (IS_FPA)
4074 ARM_FPA_MVFS (code, ins->dreg, ins->sreg1);
4075 else if (IS_VFP) {
4076 ARM_CVTD (code, ins->dreg, ins->sreg1);
4077 ARM_CVTS (code, ins->dreg, ins->dreg);
4078 }
4079 break;
4080 case OP_JMP:
4081 /*
4082 * Keep in sync with mono_arch_emit_epilog
4083 */
4084 g_assert (!cfg->method->save_lmf);
4085
4086 code = emit_load_volatile_arguments (cfg, code);
4087
4088 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
4089 if (iphone_abi) {
4090 if (cfg->used_int_regs)
4091 ARM_POP (code, cfg->used_int_regs);
4092 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
4093 } else {
4094 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
4095 }
4096 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4097 if (cfg->compile_aot) {
4098 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
4099 ARM_B (code, 0);
4100 *(gpointer*)code = NULL;
4101 code += 4;
4102 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
4103 } else {
4104 ARM_B (code, 0);
4105 }
4106 break;
4107 case OP_CHECK_THIS:
4108 /* ensure ins->sreg1 is not NULL */
4109 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
4110 break;
4111 case OP_ARGLIST: {
4112 g_assert (cfg->sig_cookie < 128);
4113 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
4114 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
4115 break;
4116 }
4117 case OP_FCALL:
4118 case OP_LCALL:
4119 case OP_VCALL:
4120 case OP_VCALL2:
4121 case OP_VOIDCALL:
4122 case OP_CALL:
4123 call = (MonoCallInst*)ins;
4124 if (ins->flags & MONO_INST_HAS_METHOD)
4125 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
4126 else
4127 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
4128 code = emit_call_seq (cfg, code);
4129 ins->flags |= MONO_INST_GC_CALLSITE;
4130 ins->backend.pc_offset = code - cfg->native_code;
4131 code = emit_move_return_value (cfg, ins, code);
4132 break;
4133 case OP_FCALL_REG:
4134 case OP_LCALL_REG:
4135 case OP_VCALL_REG:
4136 case OP_VCALL2_REG:
4137 case OP_VOIDCALL_REG:
4138 case OP_CALL_REG:
4139 code = emit_call_reg (code, ins->sreg1);
4140 ins->flags |= MONO_INST_GC_CALLSITE;
4141 ins->backend.pc_offset = code - cfg->native_code;
4142 code = emit_move_return_value (cfg, ins, code);
4143 break;
4144 case OP_FCALL_MEMBASE:
4145 case OP_LCALL_MEMBASE:
4146 case OP_VCALL_MEMBASE:
4147 case OP_VCALL2_MEMBASE:
4148 case OP_VOIDCALL_MEMBASE:
4149 case OP_CALL_MEMBASE:
4150 g_assert (arm_is_imm12 (ins->inst_offset));
4151 g_assert (ins->sreg1 != ARMREG_LR);
4152 call = (MonoCallInst*)ins;
4153 if (call->dynamic_imt_arg || call->method->klass->flags & TYPE_ATTRIBUTE_INTERFACE) {
4154 ARM_ADD_REG_IMM8 (code, ARMREG_LR, ARMREG_PC, 4);
4155 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4156 /*
4157 * We can't embed the method in the code stream in PIC code, or
4158 * in gshared code.
4159 * Instead, we put it in V5 in code emitted by
4160 * mono_arch_emit_imt_argument (), and embed NULL here to
4161 * signal the IMT thunk that the value is in V5.
4162 */
4163 if (call->dynamic_imt_arg)
4164 *((gpointer*)code) = NULL;
4165 else
4166 *((gpointer*)code) = (gpointer)call->method;
4167 code += 4;
4168 } else {
4169 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4170 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
4171 }
4172 ins->flags |= MONO_INST_GC_CALLSITE;
4173 ins->backend.pc_offset = code - cfg->native_code;
4174 code = emit_move_return_value (cfg, ins, code);
4175 break;
4176 case OP_LOCALLOC: {
4177 /* keep alignment */
4178 int alloca_waste = cfg->param_area;
4179 alloca_waste += 7;
4180 alloca_waste &= ~7;
4181 /* round the size to 8 bytes */
4182 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, 7);
4183 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, 7);
4184 if (alloca_waste)
4185 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->dreg, alloca_waste);
4186 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
4187 /* memzero the area: dreg holds the size, sp is the pointer */
4188 if (ins->flags & MONO_INST_INIT) {
4189 guint8 *start_loop, *branch_to_cond;
4190 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
4191 branch_to_cond = code;
4192 ARM_B (code, 0);
4193 start_loop = code;
4194 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
4195 arm_patch (branch_to_cond, code);
4196 /* decrement by 4 and set flags */
4197 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
4198 ARM_B_COND (code, ARMCOND_GE, 0);
4199 arm_patch (code - 4, start_loop);
4200 }
4201 ARM_ADD_REG_IMM8 (code, ins->dreg, ARMREG_SP, alloca_waste);
4202 break;
4203 }
4204 case OP_DYN_CALL: {
4205 int i;
4206 MonoInst *var = cfg->dyn_call_var;
4207
4208 g_assert (var->opcode == OP_REGOFFSET);
4209 g_assert (arm_is_imm12 (var->inst_offset));
4210
4211 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
4212 ARM_MOV_REG_REG( code, ARMREG_LR, ins->sreg1);
4213 /* ip = ftn */
4214 ARM_MOV_REG_REG( code, ARMREG_IP, ins->sreg2);
4215
4216 /* Save args buffer */
4217 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4218
4219 /* Set stack slots using R0 as scratch reg */
4220 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
4221 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4222 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
4223 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4224 }
4225
4226 /* Set argument registers */
4227 for (i = 0; i < PARAM_REGS; ++i)
4228 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
4229
4230 /* Make the call */
4231 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
4232 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4233
4234 /* Save result */
4235 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
4236 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res));
4237 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, G_STRUCT_OFFSET (DynCallArgs, res2));
4238 break;
4239 }
4240 case OP_THROW: {
4241 if (ins->sreg1 != ARMREG_R0)
4242 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4243 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4244 (gpointer)"mono_arch_throw_exception");
4245 code = emit_call_seq (cfg, code);
4246 break;
4247 }
4248 case OP_RETHROW: {
4249 if (ins->sreg1 != ARMREG_R0)
4250 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4251 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4252 (gpointer)"mono_arch_rethrow_exception");
4253 code = emit_call_seq (cfg, code);
4254 break;
4255 }
4256 case OP_START_HANDLER: {
4257 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4258 int i, rot_amount;
4259
4260 /* Reserve a param area, see filter-stack.exe */
4261 if (cfg->param_area) {
4262 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4263 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4264 } else {
4265 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4266 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4267 }
4268 }
4269
4270 if (arm_is_imm12 (spvar->inst_offset)) {
4271 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4272 } else {
4273 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4274 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
4275 }
4276 break;
4277 }
4278 case OP_ENDFILTER: {
4279 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4280 int i, rot_amount;
4281
4282 /* Free the param area */
4283 if (cfg->param_area) {
4284 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4285 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4286 } else {
4287 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4288 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4289 }
4290 }
4291
4292 if (ins->sreg1 != ARMREG_R0)
4293 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
4294 if (arm_is_imm12 (spvar->inst_offset)) {
4295 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4296 } else {
4297 g_assert (ARMREG_IP != spvar->inst_basereg);
4298 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4299 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4300 }
4301 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4302 break;
4303 }
4304 case OP_ENDFINALLY: {
4305 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4306 int i, rot_amount;
4307
4308 /* Free the param area */
4309 if (cfg->param_area) {
4310 if ((i = mono_arm_is_rotated_imm8 (cfg->param_area, &rot_amount)) >= 0) {
4311 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
4312 } else {
4313 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->param_area);
4314 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
4315 }
4316 }
4317
4318 if (arm_is_imm12 (spvar->inst_offset)) {
4319 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
4320 } else {
4321 g_assert (ARMREG_IP != spvar->inst_basereg);
4322 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
4323 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
4324 }
4325 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
4326 break;
4327 }
4328 case OP_CALL_HANDLER:
4329 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4330 ARM_BL (code, 0);
4331 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4332 break;
4333 case OP_LABEL:
4334 ins->inst_c0 = code - cfg->native_code;
4335 break;
4336 case OP_BR:
4337 /*if (ins->inst_target_bb->native_offset) {
4338 ARM_B (code, 0);
4339 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4340 } else*/ {
4341 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4342 ARM_B (code, 0);
4343 }
4344 break;
4345 case OP_BR_REG:
4346 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
4347 break;
4348 case OP_SWITCH:
4349 /*
4350 * In the normal case we have:
4351 * ldr pc, [pc, ins->sreg1 << 2]
4352 * nop
4353 * If aot, we have:
4354 * ldr lr, [pc, ins->sreg1 << 2]
4355 * add pc, pc, lr
4356 * After follows the data.
4357 * FIXME: add aot support.
4358 */
4359 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
4360 max_len += 4 * GPOINTER_TO_INT (ins->klass);
4361 if (offset + max_len > (cfg->code_size - 16)) {
4362 cfg->code_size += max_len;
4363 cfg->code_size *= 2;
4364 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4365 code = cfg->native_code + offset;
4366 }
4367 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
4368 ARM_NOP (code);
4369 code += 4 * GPOINTER_TO_INT (ins->klass);
4370 break;
4371 case OP_CEQ:
4372 case OP_ICEQ:
4373 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4374 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4375 break;
4376 case OP_CLT:
4377 case OP_ICLT:
4378 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4379 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
4380 break;
4381 case OP_CLT_UN:
4382 case OP_ICLT_UN:
4383 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4384 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
4385 break;
4386 case OP_CGT:
4387 case OP_ICGT:
4388 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4389 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
4390 break;
4391 case OP_CGT_UN:
4392 case OP_ICGT_UN:
4393 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4394 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
4395 break;
4396 case OP_COND_EXC_EQ:
4397 case OP_COND_EXC_NE_UN:
4398 case OP_COND_EXC_LT:
4399 case OP_COND_EXC_LT_UN:
4400 case OP_COND_EXC_GT:
4401 case OP_COND_EXC_GT_UN:
4402 case OP_COND_EXC_GE:
4403 case OP_COND_EXC_GE_UN:
4404 case OP_COND_EXC_LE:
4405 case OP_COND_EXC_LE_UN:
4406 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
4407 break;
4408 case OP_COND_EXC_IEQ:
4409 case OP_COND_EXC_INE_UN:
4410 case OP_COND_EXC_ILT:
4411 case OP_COND_EXC_ILT_UN:
4412 case OP_COND_EXC_IGT:
4413 case OP_COND_EXC_IGT_UN:
4414 case OP_COND_EXC_IGE:
4415 case OP_COND_EXC_IGE_UN:
4416 case OP_COND_EXC_ILE:
4417 case OP_COND_EXC_ILE_UN:
4418 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
4419 break;
4420 case OP_COND_EXC_C:
4421 case OP_COND_EXC_IC:
4422 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
4423 break;
4424 case OP_COND_EXC_OV:
4425 case OP_COND_EXC_IOV:
4426 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
4427 break;
4428 case OP_COND_EXC_NC:
4429 case OP_COND_EXC_INC:
4430 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
4431 break;
4432 case OP_COND_EXC_NO:
4433 case OP_COND_EXC_INO:
4434 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
4435 break;
4436 case OP_IBEQ:
4437 case OP_IBNE_UN:
4438 case OP_IBLT:
4439 case OP_IBLT_UN:
4440 case OP_IBGT:
4441 case OP_IBGT_UN:
4442 case OP_IBGE:
4443 case OP_IBGE_UN:
4444 case OP_IBLE:
4445 case OP_IBLE_UN:
4446 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
4447 break;
4448
4449 /* floating point opcodes */
4450 #ifdef ARM_FPU_FPA
4451 case OP_R8CONST:
4452 if (cfg->compile_aot) {
4453 ARM_FPA_LDFD (code, ins->dreg, ARMREG_PC, 0);
4454 ARM_B (code, 1);
4455 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4456 code += 4;
4457 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4458 code += 4;
4459 } else {
4460 /* FIXME: we can optimize the imm load by dealing with part of
4461 * the displacement in LDFD (aligning to 512).
4462 */
4463 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4464 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4465 }
4466 break;
4467 case OP_R4CONST:
4468 if (cfg->compile_aot) {
4469 ARM_FPA_LDFS (code, ins->dreg, ARMREG_PC, 0);
4470 ARM_B (code, 0);
4471 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4472 code += 4;
4473 } else {
4474 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4475 ARM_FPA_LDFS (code, ins->dreg, ARMREG_LR, 0);
4476 }
4477 break;
4478 case OP_STORER8_MEMBASE_REG:
4479 /* This is generated by the local regalloc pass which runs after the lowering pass */
4480 if (!arm_is_fpimm8 (ins->inst_offset)) {
4481 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4482 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4483 ARM_FPA_STFD (code, ins->sreg1, ARMREG_LR, 0);
4484 } else {
4485 ARM_FPA_STFD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4486 }
4487 break;
4488 case OP_LOADR8_MEMBASE:
4489 /* This is generated by the local regalloc pass which runs after the lowering pass */
4490 if (!arm_is_fpimm8 (ins->inst_offset)) {
4491 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4492 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4493 ARM_FPA_LDFD (code, ins->dreg, ARMREG_LR, 0);
4494 } else {
4495 ARM_FPA_LDFD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4496 }
4497 break;
4498 case OP_STORER4_MEMBASE_REG:
4499 g_assert (arm_is_fpimm8 (ins->inst_offset));
4500 ARM_FPA_STFS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4501 break;
4502 case OP_LOADR4_MEMBASE:
4503 g_assert (arm_is_fpimm8 (ins->inst_offset));
4504 ARM_FPA_LDFS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4505 break;
4506 case OP_ICONV_TO_R_UN: {
4507 int tmpreg;
4508 tmpreg = ins->dreg == 0? 1: 0;
4509 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4510 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4511 ARM_B_COND (code, ARMCOND_GE, 8);
4512 /* save the temp register */
4513 ARM_SUB_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4514 ARM_FPA_STFD (code, tmpreg, ARMREG_SP, 0);
4515 ARM_FPA_LDFD (code, tmpreg, ARMREG_PC, 12);
4516 ARM_FPA_ADFD (code, ins->dreg, ins->dreg, tmpreg);
4517 ARM_FPA_LDFD (code, tmpreg, ARMREG_SP, 0);
4518 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 8);
4519 /* skip the constant pool */
4520 ARM_B (code, 8);
4521 code += 4;
4522 *(int*)code = 0x41f00000;
4523 code += 4;
4524 *(int*)code = 0;
4525 code += 4;
4526 /* FIXME: adjust:
4527 * ldfltd ftemp, [pc, #8] 0x41f00000 0x00000000
4528 * adfltd fdest, fdest, ftemp
4529 */
4530 break;
4531 }
4532 case OP_ICONV_TO_R4:
4533 ARM_FPA_FLTS (code, ins->dreg, ins->sreg1);
4534 break;
4535 case OP_ICONV_TO_R8:
4536 ARM_FPA_FLTD (code, ins->dreg, ins->sreg1);
4537 break;
4538
4539 #elif defined(ARM_FPU_VFP)
4540
4541 case OP_R8CONST:
4542 if (cfg->compile_aot) {
4543 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
4544 ARM_B (code, 1);
4545 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4546 code += 4;
4547 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
4548 code += 4;
4549 } else {
4550 /* FIXME: we can optimize the imm load by dealing with part of
4551 * the displacement in LDFD (aligning to 512).
4552 */
4553 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4554 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4555 }
4556 break;
4557 case OP_R4CONST:
4558 if (cfg->compile_aot) {
4559 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
4560 ARM_B (code, 0);
4561 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
4562 code += 4;
4563 ARM_CVTS (code, ins->dreg, ins->dreg);
4564 } else {
4565 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
4566 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4567 ARM_CVTS (code, ins->dreg, ins->dreg);
4568 }
4569 break;
4570 case OP_STORER8_MEMBASE_REG:
4571 /* This is generated by the local regalloc pass which runs after the lowering pass */
4572 if (!arm_is_fpimm8 (ins->inst_offset)) {
4573 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4574 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
4575 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4576 } else {
4577 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4578 }
4579 break;
4580 case OP_LOADR8_MEMBASE:
4581 /* This is generated by the local regalloc pass which runs after the lowering pass */
4582 if (!arm_is_fpimm8 (ins->inst_offset)) {
4583 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4584 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
4585 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4586 } else {
4587 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4588 }
4589 break;
4590 case OP_STORER4_MEMBASE_REG:
4591 g_assert (arm_is_fpimm8 (ins->inst_offset));
4592 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4593 ARM_FSTS (code, ARM_VFP_F0, ins->inst_destbasereg, ins->inst_offset);
4594 break;
4595 case OP_LOADR4_MEMBASE:
4596 g_assert (arm_is_fpimm8 (ins->inst_offset));
4597 ARM_FLDS (code, ARM_VFP_F0, ins->inst_basereg, ins->inst_offset);
4598 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4599 break;
4600 case OP_ICONV_TO_R_UN: {
4601 g_assert_not_reached ();
4602 break;
4603 }
4604 case OP_ICONV_TO_R4:
4605 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4606 ARM_FSITOS (code, ARM_VFP_F0, ARM_VFP_F0);
4607 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4608 break;
4609 case OP_ICONV_TO_R8:
4610 ARM_FMSR (code, ARM_VFP_F0, ins->sreg1);
4611 ARM_FSITOD (code, ins->dreg, ARM_VFP_F0);
4612 break;
4613
4614 case OP_SETFRET:
4615 if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4) {
4616 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
4617 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
4618 } else {
4619 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
4620 }
4621 break;
4622
4623 #endif
4624
4625 case OP_FCONV_TO_I1:
4626 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4627 break;
4628 case OP_FCONV_TO_U1:
4629 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4630 break;
4631 case OP_FCONV_TO_I2:
4632 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4633 break;
4634 case OP_FCONV_TO_U2:
4635 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4636 break;
4637 case OP_FCONV_TO_I4:
4638 case OP_FCONV_TO_I:
4639 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4640 break;
4641 case OP_FCONV_TO_U4:
4642 case OP_FCONV_TO_U:
4643 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4644 break;
4645 case OP_FCONV_TO_I8:
4646 case OP_FCONV_TO_U8:
4647 g_assert_not_reached ();
4648 /* Implemented as helper calls */
4649 break;
4650 case OP_LCONV_TO_R_UN:
4651 g_assert_not_reached ();
4652 /* Implemented as helper calls */
4653 break;
4654 case OP_LCONV_TO_OVF_I4_2: {
4655 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
4656 /*
4657 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4658 */
4659
4660 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
4661 high_bit_not_set = code;
4662 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
4663
4664 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
4665 valid_negative = code;
4666 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
4667 invalid_negative = code;
4668 ARM_B_COND (code, ARMCOND_AL, 0);
4669
4670 arm_patch (high_bit_not_set, code);
4671
4672 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
4673 valid_positive = code;
4674 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
4675
4676 arm_patch (invalid_negative, code);
4677 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
4678
4679 arm_patch (valid_negative, code);
4680 arm_patch (valid_positive, code);
4681
4682 if (ins->dreg != ins->sreg1)
4683 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4684 break;
4685 }
4686 #ifdef ARM_FPU_FPA
4687 case OP_FADD:
4688 ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4689 break;
4690 case OP_FSUB:
4691 ARM_FPA_SUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4692 break;
4693 case OP_FMUL:
4694 ARM_FPA_MUFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4695 break;
4696 case OP_FDIV:
4697 ARM_FPA_DVFD (code, ins->dreg, ins->sreg1, ins->sreg2);
4698 break;
4699 case OP_FNEG:
4700 ARM_FPA_MNFD (code, ins->dreg, ins->sreg1);
4701 break;
4702 #elif defined(ARM_FPU_VFP)
4703 case OP_FADD:
4704 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
4705 break;
4706 case OP_FSUB:
4707 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
4708 break;
4709 case OP_FMUL:
4710 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
4711 break;
4712 case OP_FDIV:
4713 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
4714 break;
4715 case OP_FNEG:
4716 ARM_NEGD (code, ins->dreg, ins->sreg1);
4717 break;
4718 #endif
4719 case OP_FREM:
4720 /* emulated */
4721 g_assert_not_reached ();
4722 break;
4723 case OP_FCOMPARE:
4724 if (IS_FPA) {
4725 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4726 } else if (IS_VFP) {
4727 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4728 ARM_FMSTAT (code);
4729 }
4730 break;
4731 case OP_FCEQ:
4732 if (IS_FPA) {
4733 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4734 } else if (IS_VFP) {
4735 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4736 ARM_FMSTAT (code);
4737 }
4738 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
4739 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
4740 break;
4741 case OP_FCLT:
4742 if (IS_FPA) {
4743 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4744 } else {
4745 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4746 ARM_FMSTAT (code);
4747 }
4748 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4749 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4750 break;
4751 case OP_FCLT_UN:
4752 if (IS_FPA) {
4753 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
4754 } else if (IS_VFP) {
4755 ARM_CMPD (code, ins->sreg1, ins->sreg2);
4756 ARM_FMSTAT (code);
4757 }
4758 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4759 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4760 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4761 break;
4762 case OP_FCGT:
4763 /* swapped */
4764 if (IS_FPA) {
4765 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4766 } else if (IS_VFP) {
4767 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4768 ARM_FMSTAT (code);
4769 }
4770 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4771 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4772 break;
4773 case OP_FCGT_UN:
4774 /* swapped */
4775 if (IS_FPA) {
4776 ARM_FPA_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
4777 } else if (IS_VFP) {
4778 ARM_CMPD (code, ins->sreg2, ins->sreg1);
4779 ARM_FMSTAT (code);
4780 }
4781 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
4782 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
4783 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
4784 break;
4785 /* ARM FPA flags table:
4786 * N Less than ARMCOND_MI
4787 * Z Equal ARMCOND_EQ
4788 * C Greater Than or Equal ARMCOND_CS
4789 * V Unordered ARMCOND_VS
4790 */
4791 case OP_FBEQ:
4792 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
4793 break;
4794 case OP_FBNE_UN:
4795 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
4796 break;
4797 case OP_FBLT:
4798 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4799 break;
4800 case OP_FBLT_UN:
4801 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4802 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
4803 break;
4804 case OP_FBGT:
4805 case OP_FBGT_UN:
4806 case OP_FBLE:
4807 case OP_FBLE_UN:
4808 g_assert_not_reached ();
4809 break;
4810 case OP_FBGE:
4811 if (IS_VFP) {
4812 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4813 } else {
4814 /* FPA requires EQ even thou the docs suggests that just CS is enough */
4815 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
4816 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
4817 }
4818 break;
4819 case OP_FBGE_UN:
4820 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
4821 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
4822 break;
4823
4824 case OP_CKFINITE: {
4825 if (IS_FPA) {
4826 if (ins->dreg != ins->sreg1)
4827 ARM_FPA_MVFD (code, ins->dreg, ins->sreg1);
4828 } else if (IS_VFP) {
4829 ARM_ABSD (code, ARM_VFP_D1, ins->sreg1);
4830 ARM_FLDD (code, ARM_VFP_D0, ARMREG_PC, 0);
4831 ARM_B (code, 1);
4832 *(guint32*)code = 0xffffffff;
4833 code += 4;
4834 *(guint32*)code = 0x7fefffff;
4835 code += 4;
4836 ARM_CMPD (code, ARM_VFP_D1, ARM_VFP_D0);
4837 ARM_FMSTAT (code);
4838 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "ArithmeticException");
4839 ARM_CMPD (code, ins->sreg1, ins->sreg1);
4840 ARM_FMSTAT (code);
4841 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "ArithmeticException");
4842 ARM_CPYD (code, ins->dreg, ins->sreg1);
4843 }
4844 break;
4845 }
4846
4847 case OP_GC_LIVENESS_DEF:
4848 case OP_GC_LIVENESS_USE:
4849 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4850 ins->backend.pc_offset = code - cfg->native_code;
4851 break;
4852 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4853 ins->backend.pc_offset = code - cfg->native_code;
4854 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4855 break;
4856
4857 default:
4858 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4859 g_assert_not_reached ();
4860 }
4861
4862 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4863 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4864 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4865 g_assert_not_reached ();
4866 }
4867
4868 cpos += max_len;
4869
4870 last_ins = ins;
4871 last_offset = offset;
4872 }
4873
4874 cfg->code_len = code - cfg->native_code;
4875 }
4876
4877 #endif /* DISABLE_JIT */
4878
4879 #ifdef HAVE_AEABI_READ_TP
4880 void __aeabi_read_tp (void);
4881 #endif
4882
4883 void
4884 mono_arch_register_lowlevel_calls (void)
4885 {
4886 /* The signature doesn't matter */
4887 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
4888 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
4889
4890 #ifndef MONO_CROSS_COMPILE
4891 #ifdef HAVE_AEABI_READ_TP
4892 mono_register_jit_icall (__aeabi_read_tp, "__aeabi_read_tp", mono_create_icall_signature ("void"), TRUE);
4893 #endif
4894 #endif
4895 }
4896
4897 #define patch_lis_ori(ip,val) do {\
4898 guint16 *__lis_ori = (guint16*)(ip); \
4899 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
4900 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
4901 } while (0)
4902
4903 void
4904 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4905 {
4906 MonoJumpInfo *patch_info;
4907 gboolean compile_aot = !run_cctors;
4908
4909 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4910 unsigned char *ip = patch_info->ip.i + code;
4911 const unsigned char *target;
4912
4913 if (patch_info->type == MONO_PATCH_INFO_SWITCH && !compile_aot) {
4914 gpointer *jt = (gpointer*)(ip + 8);
4915 int i;
4916 /* jt is the inlined jump table, 2 instructions after ip
4917 * In the normal case we store the absolute addresses,
4918 * otherwise the displacements.
4919 */
4920 for (i = 0; i < patch_info->data.table->table_size; i++)
4921 jt [i] = code + (int)patch_info->data.table->table [i];
4922 continue;
4923 }
4924 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4925
4926 if (compile_aot) {
4927 switch (patch_info->type) {
4928 case MONO_PATCH_INFO_BB:
4929 case MONO_PATCH_INFO_LABEL:
4930 break;
4931 default:
4932 /* No need to patch these */
4933 continue;
4934 }
4935 }
4936
4937 switch (patch_info->type) {
4938 case MONO_PATCH_INFO_IP:
4939 g_assert_not_reached ();
4940 patch_lis_ori (ip, ip);
4941 continue;
4942 case MONO_PATCH_INFO_METHOD_REL:
4943 g_assert_not_reached ();
4944 *((gpointer *)(ip)) = code + patch_info->data.offset;
4945 continue;
4946 case MONO_PATCH_INFO_METHODCONST:
4947 case MONO_PATCH_INFO_CLASS:
4948 case MONO_PATCH_INFO_IMAGE:
4949 case MONO_PATCH_INFO_FIELD:
4950 case MONO_PATCH_INFO_VTABLE:
4951 case MONO_PATCH_INFO_IID:
4952 case MONO_PATCH_INFO_SFLDA:
4953 case MONO_PATCH_INFO_LDSTR:
4954 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
4955 case MONO_PATCH_INFO_LDTOKEN:
4956 g_assert_not_reached ();
4957 /* from OP_AOTCONST : lis + ori */
4958 patch_lis_ori (ip, target);
4959 continue;
4960 case MONO_PATCH_INFO_R4:
4961 case MONO_PATCH_INFO_R8:
4962 g_assert_not_reached ();
4963 *((gconstpointer *)(ip + 2)) = patch_info->data.target;
4964 continue;
4965 case MONO_PATCH_INFO_EXC_NAME:
4966 g_assert_not_reached ();
4967 *((gconstpointer *)(ip + 1)) = patch_info->data.name;
4968 continue;
4969 case MONO_PATCH_INFO_NONE:
4970 case MONO_PATCH_INFO_BB_OVF:
4971 case MONO_PATCH_INFO_EXC_OVF:
4972 /* everything is dealt with at epilog output time */
4973 continue;
4974 default:
4975 break;
4976 }
4977 arm_patch_general (domain, ip, target, dyn_code_mp);
4978 }
4979 }
4980
4981 #ifndef DISABLE_JIT
4982
4983 /*
4984 * Stack frame layout:
4985 *
4986 * ------------------- fp
4987 * MonoLMF structure or saved registers
4988 * -------------------
4989 * locals
4990 * -------------------
4991 * spilled regs
4992 * -------------------
4993 * optional 8 bytes for tracing
4994 * -------------------
4995 * param area size is cfg->param_area
4996 * ------------------- sp
4997 */
4998 guint8 *
4999 mono_arch_emit_prolog (MonoCompile *cfg)
5000 {
5001 MonoMethod *method = cfg->method;
5002 MonoBasicBlock *bb;
5003 MonoMethodSignature *sig;
5004 MonoInst *inst;
5005 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount;
5006 guint8 *code;
5007 CallInfo *cinfo;
5008 int tracing = 0;
5009 int lmf_offset = 0;
5010 int prev_sp_offset, reg_offset;
5011
5012 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5013 tracing = 1;
5014
5015 sig = mono_method_signature (method);
5016 cfg->code_size = 256 + sig->param_count * 64;
5017 code = cfg->native_code = g_malloc (cfg->code_size);
5018
5019 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
5020
5021 alloc_size = cfg->stack_offset;
5022 pos = 0;
5023 prev_sp_offset = 0;
5024
5025 if (!method->save_lmf) {
5026 if (iphone_abi) {
5027 /*
5028 * The iphone uses R7 as the frame pointer, and it points at the saved
5029 * r7+lr:
5030 * <lr>
5031 * r7 -> <r7>
5032 * <rest of frame>
5033 * We can't use r7 as a frame pointer since it points into the middle of
5034 * the frame, so we keep using our own frame pointer.
5035 * FIXME: Optimize this.
5036 */
5037 g_assert (darwin);
5038 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5039 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
5040 prev_sp_offset += 8; /* r7 and lr */
5041 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5042 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
5043
5044 /* No need to push LR again */
5045 if (cfg->used_int_regs)
5046 ARM_PUSH (code, cfg->used_int_regs);
5047 } else {
5048 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
5049 prev_sp_offset += 4;
5050 }
5051 for (i = 0; i < 16; ++i) {
5052 if (cfg->used_int_regs & (1 << i))
5053 prev_sp_offset += 4;
5054 }
5055 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5056 reg_offset = 0;
5057 for (i = 0; i < 16; ++i) {
5058 if ((cfg->used_int_regs & (1 << i))) {
5059 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5060 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
5061 reg_offset += 4;
5062 }
5063 }
5064 if (iphone_abi) {
5065 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5066 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5067 } else {
5068 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
5069 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
5070 }
5071 } else {
5072 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
5073 ARM_PUSH (code, 0x5ff0);
5074 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
5075 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
5076 reg_offset = 0;
5077 for (i = 0; i < 16; ++i) {
5078 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
5079 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
5080 reg_offset += 4;
5081 }
5082 }
5083 pos += sizeof (MonoLMF) - prev_sp_offset;
5084 lmf_offset = pos;
5085 }
5086 alloc_size += pos;
5087 orig_alloc_size = alloc_size;
5088 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
5089 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
5090 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
5091 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
5092 }
5093
5094 /* the stack used in the pushed regs */
5095 if (prev_sp_offset & 4)
5096 alloc_size += 4;
5097 cfg->stack_usage = alloc_size;
5098 if (alloc_size) {
5099 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
5100 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5101 } else {
5102 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
5103 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5104 }
5105 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
5106 }
5107 if (cfg->frame_reg != ARMREG_SP) {
5108 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
5109 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
5110 }
5111 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
5112 prev_sp_offset += alloc_size;
5113
5114 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
5115 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
5116
5117 /* compute max_offset in order to use short forward jumps
5118 * we could skip do it on arm because the immediate displacement
5119 * for jumps is large enough, it may be useful later for constant pools
5120 */
5121 max_offset = 0;
5122 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5123 MonoInst *ins = bb->code;
5124 bb->max_offset = max_offset;
5125
5126 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5127 max_offset += 6;
5128
5129 MONO_BB_FOR_EACH_INS (bb, ins)
5130 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5131 }
5132
5133 /* store runtime generic context */
5134 if (cfg->rgctx_var) {
5135 MonoInst *ins = cfg->rgctx_var;
5136
5137 g_assert (ins->opcode == OP_REGOFFSET);
5138
5139 if (arm_is_imm12 (ins->inst_offset)) {
5140 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
5141 } else {
5142 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5143 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
5144 }
5145 }
5146
5147 /* load arguments allocated to register from the stack */
5148 pos = 0;
5149
5150 cinfo = get_call_info (cfg->generic_sharing_context, NULL, sig);
5151
5152 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != RegTypeStructByVal) {
5153 ArgInfo *ainfo = &cinfo->ret;
5154 inst = cfg->vret_addr;
5155 g_assert (arm_is_imm12 (inst->inst_offset));
5156 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5157 }
5158
5159 if (sig->call_convention == MONO_CALL_VARARG) {
5160 ArgInfo *cookie = &cinfo->sig_cookie;
5161
5162 /* Save the sig cookie address */
5163 g_assert (cookie->storage == RegTypeBase);
5164
5165 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
5166 g_assert (arm_is_imm12 (cfg->sig_cookie));
5167 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
5168 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5169 }
5170
5171 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5172 ArgInfo *ainfo = cinfo->args + i;
5173 inst = cfg->args [pos];
5174
5175 if (cfg->verbose_level > 2)
5176 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
5177 if (inst->opcode == OP_REGVAR) {
5178 if (ainfo->storage == RegTypeGeneral)
5179 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
5180 else if (ainfo->storage == RegTypeFP) {
5181 g_assert_not_reached ();
5182 } else if (ainfo->storage == RegTypeBase) {
5183 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5184 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5185 } else {
5186 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5187 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
5188 }
5189 } else
5190 g_assert_not_reached ();
5191
5192 if (cfg->verbose_level > 2)
5193 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5194 } else {
5195 /* the argument should be put on the stack: FIXME handle size != word */
5196 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair) {
5197 switch (ainfo->size) {
5198 case 1:
5199 if (arm_is_imm12 (inst->inst_offset))
5200 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5201 else {
5202 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5203 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5204 }
5205 break;
5206 case 2:
5207 if (arm_is_imm8 (inst->inst_offset)) {
5208 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5209 } else {
5210 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5211 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5212 }
5213 break;
5214 case 8:
5215 if (arm_is_imm12 (inst->inst_offset)) {
5216 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5217 } else {
5218 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5219 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5220 }
5221 if (arm_is_imm12 (inst->inst_offset + 4)) {
5222 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
5223 } else {
5224 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5225 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
5226 }
5227 break;
5228 default:
5229 if (arm_is_imm12 (inst->inst_offset)) {
5230 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
5231 } else {
5232 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5233 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
5234 }
5235 break;
5236 }
5237 } else if (ainfo->storage == RegTypeBaseGen) {
5238 g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
5239 g_assert (arm_is_imm12 (inst->inst_offset));
5240 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5241 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5242 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
5243 } else if (ainfo->storage == RegTypeBase) {
5244 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
5245 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
5246 } else {
5247 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
5248 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5249 }
5250
5251 switch (ainfo->size) {
5252 case 1:
5253 if (arm_is_imm8 (inst->inst_offset)) {
5254 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5255 } else {
5256 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5257 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5258 }
5259 break;
5260 case 2:
5261 if (arm_is_imm8 (inst->inst_offset)) {
5262 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5263 } else {
5264 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5265 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5266 }
5267 break;
5268 case 8:
5269 if (arm_is_imm12 (inst->inst_offset)) {
5270 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5271 } else {
5272 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5273 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5274 }
5275 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
5276 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
5277 } else {
5278 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
5279 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
5280 }
5281 if (arm_is_imm12 (inst->inst_offset + 4)) {
5282 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
5283 } else {
5284 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
5285 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5286 }
5287 break;
5288 default:
5289 if (arm_is_imm12 (inst->inst_offset)) {
5290 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
5291 } else {
5292 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
5293 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
5294 }
5295 break;
5296 }
5297 } else if (ainfo->storage == RegTypeFP) {
5298 g_assert_not_reached ();
5299 } else if (ainfo->storage == RegTypeStructByVal) {
5300 int doffset = inst->inst_offset;
5301 int soffset = 0;
5302 int cur_reg;
5303 int size = 0;
5304 size = mini_type_stack_size_full (cfg->generic_sharing_context, inst->inst_vtype, NULL, sig->pinvoke);
5305 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
5306 if (arm_is_imm12 (doffset)) {
5307 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
5308 } else {
5309 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
5310 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
5311 }
5312 soffset += sizeof (gpointer);
5313 doffset += sizeof (gpointer);
5314 }
5315 if (ainfo->vtsize) {
5316 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5317 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
5318 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
5319 }
5320 } else if (ainfo->storage == RegTypeStructByAddr) {
5321 g_assert_not_reached ();
5322 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
5323 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, inst->inst_offset, ainfo->reg, 0);
5324 } else
5325 g_assert_not_reached ();
5326 }
5327 pos++;
5328 }
5329
5330 if (method->save_lmf)
5331 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
5332
5333 if (tracing)
5334 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5335
5336 if (cfg->arch.seq_point_info_var) {
5337 MonoInst *ins = cfg->arch.seq_point_info_var;
5338
5339 /* Initialize the variable from a GOT slot */
5340 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
5341 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5342 ARM_B (code, 0);
5343 *(gpointer*)code = NULL;
5344 code += 4;
5345 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
5346
5347 g_assert (ins->opcode == OP_REGOFFSET);
5348
5349 if (arm_is_imm12 (ins->inst_offset)) {
5350 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5351 } else {
5352 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5353 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5354 }
5355 }
5356
5357 /* Initialize ss_trigger_page_var */
5358 if (!cfg->soft_breakpoints) {
5359 MonoInst *info_var = cfg->arch.seq_point_info_var;
5360 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
5361 int dreg = ARMREG_LR;
5362
5363 if (info_var) {
5364 g_assert (info_var->opcode == OP_REGOFFSET);
5365 g_assert (arm_is_imm12 (info_var->inst_offset));
5366
5367 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
5368 /* Load the trigger page addr */
5369 ARM_LDR_IMM (code, dreg, dreg, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
5370 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
5371 }
5372 }
5373
5374 if (cfg->arch.seq_point_read_var) {
5375 MonoInst *read_ins = cfg->arch.seq_point_read_var;
5376 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
5377 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
5378
5379 g_assert (read_ins->opcode == OP_REGOFFSET);
5380 g_assert (arm_is_imm12 (read_ins->inst_offset));
5381 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
5382 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
5383 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
5384 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
5385
5386 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5387 ARM_B (code, 2);
5388 *(volatile int **)code = &ss_trigger_var;
5389 code += 4;
5390 *(gpointer*)code = single_step_func_wrapper;
5391 code += 4;
5392 *(gpointer*)code = breakpoint_func_wrapper;
5393 code += 4;
5394
5395 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
5396 ARM_STR_IMM (code, ARMREG_IP, read_ins->inst_basereg, read_ins->inst_offset);
5397 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
5398 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
5399 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 8);
5400 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
5401 }
5402
5403 cfg->code_len = code - cfg->native_code;
5404 g_assert (cfg->code_len < cfg->code_size);
5405 g_free (cinfo);
5406
5407 return code;
5408 }
5409
5410 void
5411 mono_arch_emit_epilog (MonoCompile *cfg)
5412 {
5413 MonoMethod *method = cfg->method;
5414 int pos, i, rot_amount;
5415 int max_epilog_size = 16 + 20*4;
5416 guint8 *code;
5417 CallInfo *cinfo;
5418
5419 if (cfg->method->save_lmf)
5420 max_epilog_size += 128;
5421
5422 if (mono_jit_trace_calls != NULL)
5423 max_epilog_size += 50;
5424
5425 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5426 max_epilog_size += 50;
5427
5428 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5429 cfg->code_size *= 2;
5430 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5431 cfg->stat_code_reallocs++;
5432 }
5433
5434 /*
5435 * Keep in sync with OP_JMP
5436 */
5437 code = cfg->native_code + cfg->code_len;
5438
5439 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
5440 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5441 }
5442 pos = 0;
5443
5444 /* Load returned vtypes into registers if needed */
5445 cinfo = cfg->arch.cinfo;
5446 if (cinfo->ret.storage == RegTypeStructByVal) {
5447 MonoInst *ins = cfg->ret;
5448
5449 if (arm_is_imm12 (ins->inst_offset)) {
5450 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
5451 } else {
5452 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5453 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
5454 }
5455 }
5456
5457 if (method->save_lmf) {
5458 int lmf_offset, reg, sp_adj, regmask;
5459 /* all but r0-r3, sp and pc */
5460 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5461 lmf_offset = pos;
5462
5463 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
5464
5465 /* This points to r4 inside MonoLMF->iregs */
5466 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
5467 reg = ARMREG_R4;
5468 regmask = 0x9ff0; /* restore lr to pc */
5469 /* Skip caller saved registers not used by the method */
5470 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
5471 regmask &= ~(1 << reg);
5472 sp_adj += 4;
5473 reg ++;
5474 }
5475 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
5476 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
5477 /* restore iregs */
5478 ARM_POP (code, regmask);
5479 } else {
5480 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
5481 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
5482 } else {
5483 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
5484 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
5485 }
5486
5487 if (iphone_abi) {
5488 /* Restore saved gregs */
5489 if (cfg->used_int_regs)
5490 ARM_POP (code, cfg->used_int_regs);
5491 /* Restore saved r7, restore LR to PC */
5492 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
5493 } else {
5494 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
5495 }
5496 }
5497
5498 cfg->code_len = code - cfg->native_code;
5499
5500 g_assert (cfg->code_len < cfg->code_size);
5501
5502 }
5503
5504 /* remove once throw_exception_by_name is eliminated */
5505 static int
5506 exception_id_by_name (const char *name)
5507 {
5508 if (strcmp (name, "IndexOutOfRangeException") == 0)
5509 return MONO_EXC_INDEX_OUT_OF_RANGE;
5510 if (strcmp (name, "OverflowException") == 0)
5511 return MONO_EXC_OVERFLOW;
5512 if (strcmp (name, "ArithmeticException") == 0)
5513 return MONO_EXC_ARITHMETIC;
5514 if (strcmp (name, "DivideByZeroException") == 0)
5515 return MONO_EXC_DIVIDE_BY_ZERO;
5516 if (strcmp (name, "InvalidCastException") == 0)
5517 return MONO_EXC_INVALID_CAST;
5518 if (strcmp (name, "NullReferenceException") == 0)
5519 return MONO_EXC_NULL_REF;
5520 if (strcmp (name, "ArrayTypeMismatchException") == 0)
5521 return MONO_EXC_ARRAY_TYPE_MISMATCH;
5522 if (strcmp (name, "ArgumentException") == 0)
5523 return MONO_EXC_ARGUMENT;
5524 g_error ("Unknown intrinsic exception %s\n", name);
5525 return -1;
5526 }
5527
5528 void
5529 mono_arch_emit_exceptions (MonoCompile *cfg)
5530 {
5531 MonoJumpInfo *patch_info;
5532 int i;
5533 guint8 *code;
5534 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
5535 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
5536 int max_epilog_size = 50;
5537
5538 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
5539 exc_throw_pos [i] = NULL;
5540 exc_throw_found [i] = 0;
5541 }
5542
5543 /* count the number of exception infos */
5544
5545 /*
5546 * make sure we have enough space for exceptions
5547 */
5548 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5549 if (patch_info->type == MONO_PATCH_INFO_EXC) {
5550 i = exception_id_by_name (patch_info->data.target);
5551 if (!exc_throw_found [i]) {
5552 max_epilog_size += 32;
5553 exc_throw_found [i] = TRUE;
5554 }
5555 }
5556 }
5557
5558 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5559 cfg->code_size *= 2;
5560 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5561 cfg->stat_code_reallocs++;
5562 }
5563
5564 code = cfg->native_code + cfg->code_len;
5565
5566 /* add code to raise exceptions */
5567 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5568 switch (patch_info->type) {
5569 case MONO_PATCH_INFO_EXC: {
5570 MonoClass *exc_class;
5571 unsigned char *ip = patch_info->ip.i + cfg->native_code;
5572
5573 i = exception_id_by_name (patch_info->data.target);
5574 if (exc_throw_pos [i]) {
5575 arm_patch (ip, exc_throw_pos [i]);
5576 patch_info->type = MONO_PATCH_INFO_NONE;
5577 break;
5578 } else {
5579 exc_throw_pos [i] = code;
5580 }
5581 arm_patch (ip, code);
5582
5583 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5584 g_assert (exc_class);
5585
5586 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
5587 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
5588 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5589 patch_info->data.name = "mono_arch_throw_corlib_exception";
5590 patch_info->ip.i = code - cfg->native_code;
5591 ARM_BL (code, 0);
5592 *(guint32*)(gpointer)code = exc_class->type_token;
5593 code += 4;
5594 break;
5595 }
5596 default:
5597 /* do nothing */
5598 break;
5599 }
5600 }
5601
5602 cfg->code_len = code - cfg->native_code;
5603
5604 g_assert (cfg->code_len < cfg->code_size);
5605
5606 }
5607
5608 #endif /* #ifndef DISABLE_JIT */
5609
5610 void
5611 mono_arch_finish_init (void)
5612 {
5613 lmf_tls_offset = mono_get_lmf_tls_offset ();
5614 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5615 }
5616
5617 void
5618 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5619 {
5620 }
5621
5622 MonoInst*
5623 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5624 {
5625 /* FIXME: */
5626 return NULL;
5627 }
5628
5629 gboolean
5630 mono_arch_print_tree (MonoInst *tree, int arity)
5631 {
5632 return 0;
5633 }
5634
5635 MonoInst*
5636 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5637 {
5638 return mono_get_domain_intrinsic (cfg);
5639 }
5640
5641 guint32
5642 mono_arch_get_patch_offset (guint8 *code)
5643 {
5644 /* OP_AOTCONST */
5645 return 8;
5646 }
5647
5648 void
5649 mono_arch_flush_register_windows (void)
5650 {
5651 }
5652
5653 #ifdef MONO_ARCH_HAVE_IMT
5654
5655 #ifndef DISABLE_JIT
5656
5657 void
5658 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5659 {
5660 if (cfg->compile_aot) {
5661 int method_reg = mono_alloc_ireg (cfg);
5662 MonoInst *ins;
5663
5664 call->dynamic_imt_arg = TRUE;
5665
5666 if (imt_arg) {
5667 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5668 } else {
5669 MONO_INST_NEW (cfg, ins, OP_AOTCONST);
5670 ins->dreg = method_reg;
5671 ins->inst_p0 = call->method;
5672 ins->inst_c1 = MONO_PATCH_INFO_METHODCONST;
5673 MONO_ADD_INS (cfg->cbb, ins);
5674
5675 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5676 }
5677 } else if (cfg->generic_context || imt_arg || mono_use_llvm) {
5678
5679 /* Always pass in a register for simplicity */
5680 call->dynamic_imt_arg = TRUE;
5681
5682 cfg->uses_rgctx_reg = TRUE;
5683
5684 if (imt_arg) {
5685 mono_call_inst_add_outarg_reg (cfg, call, imt_arg->dreg, ARMREG_V5, FALSE);
5686 } else {
5687 MonoInst *ins;
5688 int method_reg = mono_alloc_preg (cfg);
5689
5690 MONO_INST_NEW (cfg, ins, OP_PCONST);
5691 ins->inst_p0 = call->method;
5692 ins->dreg = method_reg;
5693 MONO_ADD_INS (cfg->cbb, ins);
5694
5695 mono_call_inst_add_outarg_reg (cfg, call, method_reg, ARMREG_V5, FALSE);
5696 }
5697 }
5698 }
5699
5700 #endif /* DISABLE_JIT */
5701
5702 MonoMethod*
5703 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5704 {
5705 guint32 *code_ptr = (guint32*)code;
5706 code_ptr -= 2;
5707
5708 if (mono_use_llvm)
5709 /* Passed in V5 */
5710 return (MonoMethod*)regs [ARMREG_V5];
5711
5712 /* The IMT value is stored in the code stream right after the LDC instruction. */
5713 if (!IS_LDR_PC (code_ptr [0])) {
5714 g_warning ("invalid code stream, instruction before IMT value is not a LDC in %s() (code %p value 0: 0x%x -1: 0x%x -2: 0x%x)", __FUNCTION__, code, code_ptr [2], code_ptr [1], code_ptr [0]);
5715 g_assert (IS_LDR_PC (code_ptr [0]));
5716 }
5717 if (code_ptr [1] == 0)
5718 /* This is AOTed code, the IMT method is in V5 */
5719 return (MonoMethod*)regs [ARMREG_V5];
5720 else
5721 return (MonoMethod*) code_ptr [1];
5722 }
5723
5724 MonoVTable*
5725 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5726 {
5727 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5728 }
5729
5730 #define ENABLE_WRONG_METHOD_CHECK 0
5731 #define BASE_SIZE (6 * 4)
5732 #define BSEARCH_ENTRY_SIZE (4 * 4)
5733 #define CMP_SIZE (3 * 4)
5734 #define BRANCH_SIZE (1 * 4)
5735 #define CALL_SIZE (2 * 4)
5736 #define WMC_SIZE (5 * 4)
5737 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
5738
5739 static arminstr_t *
5740 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
5741 {
5742 guint32 delta = DISTANCE (target, code);
5743 delta -= 8;
5744 g_assert (delta >= 0 && delta <= 0xFFF);
5745 *target = *target | delta;
5746 *code = value;
5747 return code + 1;
5748 }
5749
5750 gpointer
5751 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5752 gpointer fail_tramp)
5753 {
5754 int size, i, extra_space = 0;
5755 arminstr_t *code, *start, *vtable_target = NULL;
5756 gboolean large_offsets = FALSE;
5757 guint32 **constant_pool_starts;
5758
5759 size = BASE_SIZE;
5760 constant_pool_starts = g_new0 (guint32*, count);
5761
5762 for (i = 0; i < count; ++i) {
5763 MonoIMTCheckItem *item = imt_entries [i];
5764 if (item->is_equals) {
5765 gboolean fail_case = !item->check_target_idx && fail_tramp;
5766
5767 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
5768 item->chunk_size += 32;
5769 large_offsets = TRUE;
5770 }
5771
5772 if (item->check_target_idx || fail_case) {
5773 if (!item->compare_done || fail_case)
5774 item->chunk_size += CMP_SIZE;
5775 item->chunk_size += BRANCH_SIZE;
5776 } else {
5777 #if ENABLE_WRONG_METHOD_CHECK
5778 item->chunk_size += WMC_SIZE;
5779 #endif
5780 }
5781 if (fail_case) {
5782 item->chunk_size += 16;
5783 large_offsets = TRUE;
5784 }
5785 item->chunk_size += CALL_SIZE;
5786 } else {
5787 item->chunk_size += BSEARCH_ENTRY_SIZE;
5788 imt_entries [item->check_target_idx]->compare_done = TRUE;
5789 }
5790 size += item->chunk_size;
5791 }
5792
5793 if (large_offsets)
5794 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
5795
5796 if (fail_tramp)
5797 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5798 else
5799 code = mono_domain_code_reserve (domain, size);
5800 start = code;
5801
5802 #if DEBUG_IMT
5803 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
5804 for (i = 0; i < count; ++i) {
5805 MonoIMTCheckItem *item = imt_entries [i];
5806 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
5807 }
5808 #endif
5809
5810 if (large_offsets)
5811 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5812 else
5813 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
5814 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
5815 vtable_target = code;
5816 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5817
5818 if (mono_use_llvm) {
5819 /* LLVM always passes the IMT method in R5 */
5820 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
5821 } else {
5822 /* R0 == 0 means we are called from AOT code. In this case, V5 contains the IMT method */
5823 ARM_CMP_REG_IMM8 (code, ARMREG_R0, 0);
5824 ARM_MOV_REG_REG_COND (code, ARMREG_R0, ARMREG_V5, ARMCOND_EQ);
5825 }
5826
5827 for (i = 0; i < count; ++i) {
5828 MonoIMTCheckItem *item = imt_entries [i];
5829 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
5830 gint32 vtable_offset;
5831
5832 item->code_target = (guint8*)code;
5833
5834 if (item->is_equals) {
5835 gboolean fail_case = !item->check_target_idx && fail_tramp;
5836
5837 if (item->check_target_idx || fail_case) {
5838 if (!item->compare_done || fail_case) {
5839 imt_method = code;
5840 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5841 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5842 }
5843 item->jmp_code = (guint8*)code;
5844 ARM_B_COND (code, ARMCOND_NE, 0);
5845 } else {
5846 /*Enable the commented code to assert on wrong method*/
5847 #if ENABLE_WRONG_METHOD_CHECK
5848 imt_method = code;
5849 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5850 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5851 ARM_B_COND (code, ARMCOND_NE, 1);
5852
5853 ARM_DBRK (code);
5854 #endif
5855 }
5856
5857 if (item->has_target_code) {
5858 target_code_ins = code;
5859 /* Load target address */
5860 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5861 /* Save it to the fourth slot */
5862 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5863 /* Restore registers and branch */
5864 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5865
5866 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
5867 } else {
5868 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
5869 if (!arm_is_imm12 (vtable_offset)) {
5870 /*
5871 * We need to branch to a computed address but we don't have
5872 * a free register to store it, since IP must contain the
5873 * vtable address. So we push the two values to the stack, and
5874 * load them both using LDM.
5875 */
5876 /* Compute target address */
5877 vtable_offset_ins = code;
5878 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5879 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
5880 /* Save it to the fourth slot */
5881 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5882 /* Restore registers and branch */
5883 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5884
5885 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
5886 } else {
5887 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
5888 if (large_offsets)
5889 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
5890 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
5891 }
5892 }
5893
5894 if (fail_case) {
5895 arm_patch (item->jmp_code, (guchar*)code);
5896
5897 target_code_ins = code;
5898 /* Load target address */
5899 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5900 /* Save it to the fourth slot */
5901 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
5902 /* Restore registers and branch */
5903 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
5904
5905 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
5906 item->jmp_code = NULL;
5907 }
5908
5909 if (imt_method)
5910 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
5911
5912 /*must emit after unconditional branch*/
5913 if (vtable_target) {
5914 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
5915 item->chunk_size += 4;
5916 vtable_target = NULL;
5917 }
5918
5919 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
5920 constant_pool_starts [i] = code;
5921 if (extra_space) {
5922 code += extra_space;
5923 extra_space = 0;
5924 }
5925 } else {
5926 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
5927 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
5928
5929 item->jmp_code = (guint8*)code;
5930 ARM_B_COND (code, ARMCOND_GE, 0);
5931 ++extra_space;
5932 }
5933 }
5934
5935 for (i = 0; i < count; ++i) {
5936 MonoIMTCheckItem *item = imt_entries [i];
5937 if (item->jmp_code) {
5938 if (item->check_target_idx)
5939 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5940 }
5941 if (i > 0 && item->is_equals) {
5942 int j;
5943 arminstr_t *space_start = constant_pool_starts [i];
5944 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
5945 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
5946 }
5947 }
5948 }
5949
5950 #if DEBUG_IMT
5951 {
5952 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5953 mono_disassemble_code (NULL, (guint8*)start, size, buff);
5954 g_free (buff);
5955 }
5956 #endif
5957
5958 g_free (constant_pool_starts);
5959
5960 mono_arch_flush_icache ((guint8*)start, size);
5961 mono_stats.imt_thunks_size += code - start;
5962
5963 g_assert (DISTANCE (start, code) <= size);
5964 return start;
5965 }
5966
5967 #endif
5968
5969 mgreg_t
5970 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5971 {
5972 return ctx->regs [reg];
5973 }
5974
5975 void
5976 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
5977 {
5978 ctx->regs [reg] = val;
5979 }
5980
5981 /*
5982 * mono_arch_get_trampolines:
5983 *
5984 * Return a list of MonoTrampInfo structures describing arch specific trampolines
5985 * for AOT.
5986 */
5987 GSList *
5988 mono_arch_get_trampolines (gboolean aot)
5989 {
5990 return mono_arm_get_exception_trampolines (aot);
5991 }
5992
5993 /*
5994 * mono_arch_set_breakpoint:
5995 *
5996 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5997 * The location should contain code emitted by OP_SEQ_POINT.
5998 */
5999 void
6000 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6001 {
6002 guint8 *code = ip;
6003 guint32 native_offset = ip - (guint8*)ji->code_start;
6004 MonoDebugOptions *opt = mini_get_debug_options ();
6005
6006 if (opt->soft_breakpoints) {
6007 g_assert (!ji->from_aot);
6008 code += 4;
6009 ARM_BLX_REG (code, ARMREG_LR);
6010 mono_arch_flush_icache (code - 4, 4);
6011 } else if (ji->from_aot) {
6012 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6013
6014 g_assert (native_offset % 4 == 0);
6015 g_assert (info->bp_addrs [native_offset / 4] == 0);
6016 info->bp_addrs [native_offset / 4] = bp_trigger_page;
6017 } else {
6018 int dreg = ARMREG_LR;
6019
6020 /* Read from another trigger page */
6021 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
6022 ARM_B (code, 0);
6023 *(int*)code = (int)bp_trigger_page;
6024 code += 4;
6025 ARM_LDR_IMM (code, dreg, dreg, 0);
6026
6027 mono_arch_flush_icache (code - 16, 16);
6028
6029 #if 0
6030 /* This is currently implemented by emitting an SWI instruction, which
6031 * qemu/linux seems to convert to a SIGILL.
6032 */
6033 *(int*)code = (0xef << 24) | 8;
6034 code += 4;
6035 mono_arch_flush_icache (code - 4, 4);
6036 #endif
6037 }
6038 }
6039
6040 /*
6041 * mono_arch_clear_breakpoint:
6042 *
6043 * Clear the breakpoint at IP.
6044 */
6045 void
6046 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6047 {
6048 MonoDebugOptions *opt = mini_get_debug_options ();
6049 guint8 *code = ip;
6050 int i;
6051
6052 if (opt->soft_breakpoints) {
6053 g_assert (!ji->from_aot);
6054 code += 4;
6055 ARM_NOP (code);
6056 mono_arch_flush_icache (code - 4, 4);
6057 } else if (ji->from_aot) {
6058 guint32 native_offset = ip - (guint8*)ji->code_start;
6059 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
6060
6061 g_assert (native_offset % 4 == 0);
6062 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
6063 info->bp_addrs [native_offset / 4] = 0;
6064 } else {
6065 for (i = 0; i < 4; ++i)
6066 ARM_NOP (code);
6067
6068 mono_arch_flush_icache (ip, code - ip);
6069 }
6070 }
6071
6072 /*
6073 * mono_arch_start_single_stepping:
6074 *
6075 * Start single stepping.
6076 */
6077 void
6078 mono_arch_start_single_stepping (void)
6079 {
6080 if (ss_trigger_page)
6081 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6082 else
6083 ss_trigger_var = 1;
6084 }
6085
6086 /*
6087 * mono_arch_stop_single_stepping:
6088 *
6089 * Stop single stepping.
6090 */
6091 void
6092 mono_arch_stop_single_stepping (void)
6093 {
6094 if (ss_trigger_page)
6095 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6096 else
6097 ss_trigger_var = 0;
6098 }
6099
6100 #if __APPLE__
6101 #define DBG_SIGNAL SIGBUS
6102 #else
6103 #define DBG_SIGNAL SIGSEGV
6104 #endif
6105
6106 /*
6107 * mono_arch_is_single_step_event:
6108 *
6109 * Return whenever the machine state in SIGCTX corresponds to a single
6110 * step event.
6111 */
6112 gboolean
6113 mono_arch_is_single_step_event (void *info, void *sigctx)
6114 {
6115 siginfo_t *sinfo = info;
6116
6117 if (!ss_trigger_page)
6118 return FALSE;
6119
6120 /* Sometimes the address is off by 4 */
6121 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
6122 return TRUE;
6123 else
6124 return FALSE;
6125 }
6126
6127 /*
6128 * mono_arch_is_breakpoint_event:
6129 *
6130 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
6131 */
6132 gboolean
6133 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6134 {
6135 siginfo_t *sinfo = info;
6136
6137 if (!ss_trigger_page)
6138 return FALSE;
6139
6140 if (sinfo->si_signo == DBG_SIGNAL) {
6141 /* Sometimes the address is off by 4 */
6142 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
6143 return TRUE;
6144 else
6145 return FALSE;
6146 } else {
6147 return FALSE;
6148 }
6149 }
6150
6151 /*
6152 * mono_arch_skip_breakpoint:
6153 *
6154 * See mini-amd64.c for docs.
6155 */
6156 void
6157 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6158 {
6159 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6160 }
6161
6162 /*
6163 * mono_arch_skip_single_step:
6164 *
6165 * See mini-amd64.c for docs.
6166 */
6167 void
6168 mono_arch_skip_single_step (MonoContext *ctx)
6169 {
6170 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
6171 }
6172
6173 /*
6174 * mono_arch_get_seq_point_info:
6175 *
6176 * See mini-amd64.c for docs.
6177 */
6178 gpointer
6179 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6180 {
6181 SeqPointInfo *info;
6182 MonoJitInfo *ji;
6183
6184 // FIXME: Add a free function
6185
6186 mono_domain_lock (domain);
6187 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
6188 code);
6189 mono_domain_unlock (domain);
6190
6191 if (!info) {
6192 ji = mono_jit_info_table_find (domain, (char*)code);
6193 g_assert (ji);
6194
6195 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
6196
6197 info->ss_trigger_page = ss_trigger_page;
6198 info->bp_trigger_page = bp_trigger_page;
6199
6200 mono_domain_lock (domain);
6201 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
6202 code, info);
6203 mono_domain_unlock (domain);
6204 }
6205
6206 return info;
6207 }
6208
6209 /*
6210 * mono_arch_set_target:
6211 *
6212 * Set the target architecture the JIT backend should generate code for, in the form
6213 * of a GNU target triplet. Only used in AOT mode.
6214 */
6215 void
6216 mono_arch_set_target (char *mtriple)
6217 {
6218 /* The GNU target triple format is not very well documented */
6219 if (strstr (mtriple, "armv7")) {
6220 v6_supported = TRUE;
6221 v7_supported = TRUE;
6222 }
6223 if (strstr (mtriple, "armv6")) {
6224 v6_supported = TRUE;
6225 }
6226 if (strstr (mtriple, "darwin")) {
6227 v5_supported = TRUE;
6228 thumb_supported = TRUE;
6229 darwin = TRUE;
6230 iphone_abi = TRUE;
6231 }
6232 if (strstr (mtriple, "gnueabi"))
6233 eabi_supported = TRUE;
6234 }
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