Public Git Hosting - mesa.git/log

glsl: Catch subscripted calls to undeclared subroutines

generate_array_index fails to check whether the target of a subroutine
call exists in the AST, potentially passing around null ir_rvalue
pointers eventuating in abort/segfault.

Fixes: fd01840c0bd3 ("glsl: add AoA support to subroutines")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100438
(cherry picked from commit f09c2cefdd53cd61562a994294e9d0630868d2da)

i965: Upload invariant state once at the start of the batch on Gen4-5.

We want to emit invariant state at the start of a render batch.  In the
past, this more or less happened: a new batch flagged BRW_NEW_CONTEXT
(because we don't have hardware contexts), which triggered the
brw_invariant_state atom.  So, it would be emitted before any 3D
drawing.  (Technically, there might be some BLT commands in the batch
because Gen4-5 have a single combined render/BLT ring, but that should
be harmless).

With the advent of BLORP, this broke.  The first item in a batch might
be a BLORP operation, which bypasses the normal draw upload path.  So,
we need to ensure invariant state happens first.  To do that, we just
upload it when creating a new batch.  On Gen6+ we'd need to worry about
whether it's a RENDER or BLT batch, but because we have a combined ring,
this approach should work fine on Gen4-5.

Seems to fix GPU hangs when playing hardware accelerated video with
mpv -hwdec=vaapi on Ironlake.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103529
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 8f91aa35a54e127b68415376ef2b577ea8fc30f9)

egl/wayland: Add a fallback when fourcc query isn't supported

When queryImage doesn't support __DRI_IMAGE_ATTRIB_FOURCC wayland clients
will die with a NULL derefence in wl_proxy_add_listener.

Attempt to provide a simple fallback to keep ancient systems working.

Fixes: 6595c699511 ("egl/wayland: Remove more surface specifics from
create_wl_buffer")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103519
Signed-off-by: Derek Foreman <derekf@osg.samsung.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit 0db36caa192b129cb4f22d152f82f38fcf6f06d4)

Squashed with:

egl: fix var type

queryImage() takes an `int*`; compiler is warning about the
signed<->unsigned pointer mismatch.

Fixes: 0db36caa192b129cb4f2 "egl/wayland: Add a fallback when fourcc
query isn't supported"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Derek Foreman <derekf@osg.samsung.com>
(cherry picked from commit ca95d7ad4e1b900eb3d559ed5bda0b96b232961d)

i965: Implement another VF cache invalidate workaround on Gen8+.

...and provide a better citation for the existing one.

v2:
- Apply the workaround to Gen8 too, as intended (caught by Topi).
- Restructure to add bits instead of an extra flush (based on a similar
patch by Rafael Antognolli).

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
(cherry picked from commit 8d48671492412e04c18651a779cabacf30ed0afe)
[Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_pipe_control.c

Squashed with:

i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.

This apparently causes hangs on Broadwell, so let's back it out for now.
I think there are other PIPE_CONTROL workarounds that we're missing.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103787
(cherry picked from commit a01ba366e01b7d1cdfa6b0e6647536b10c0667ef)
[Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_pipe_control.c

i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK

Fixes the following tests on CHV, BXT, and GLK:
KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115

(cherry picked from commit cfcfa0b9cd1b1d563a988b1250950057c4612ac9)

i965/fs: Fix extract_i8/u8 to a 64-bit destination

The MOV instruction can extract bytes to words/double words, and
words/double words to quadwords, but not byte to quadwords.

For unsigned byte to quadword, we can read them as words and AND off the
high byte and extract to quadword in one instruction. For signed bytes,
we need to first sign extend to word and the sign extend that word to a
quadword.

Fixes the following test on CHV, BXT, and GLK:
KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 6ac2d16901927013393f873a34c717ece5014c1a)

i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW

Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 1dc45d75bb3ff3085f7356b8ec658111529ff76d)
[Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_pipe_control.c
src/mesa/drivers/dri/i965/intel_blit.c

i965: Program DWord Length in MI_FLUSH_DW

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 6165fda59b889de035b38d9a1a08ffe0da19e6a6)

Squashed with:

i965: Remove DWord length from MI_FLUSH_DW definition

Fixes: 6165fda59b8 ("i965: Program DWord Length in MI_FLUSH_DW")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 822fd2341db49cbbe813114d2d0fc1b66de4807c)

swr/rast: Faster emulated simd16 permute

Speed up simd16 frontend (default) on avx/avx2 platforms;
fixes performance regression caused by switch to simdlib.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit d8489517a572c7e5c5405ebf510db9d20b1e2591)

swr/rast: Use gather instruction for i32gather_ps on simd16/avx512

Speed up avx512 platforms; fixes performance regression caused
by swithc to simdlib.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 439904847e9c2970494c18e8c47bd6c38c0ed8ab)

radv: Free temporary syncobj after waiting on it.

Otherwise we leak it.

Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 7c255788637b8fdfc31aca5f7891f39a110c5cb2)

radv: Free syncobj with multiple imports.

Otherwise we can leak the old syncobj.

Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 917d3b43f2b206ccf036542aa1c39f1dbdd84f62)

i965: Add stencil buffers to cache set regardless of stencil texturing

We may access them as a texture using blorp regardless of whether or not
stencil texturing is enabled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 6830ba0d3be8df12572622839743c41b4f294825)

r600: fix isoline tess factor component swapping.

As per radeonsi, the tess factor components for isolines
are reversed.

Fixes: tests/spec/arb_tessellation_shader/execution/isoline.shader_test
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit f3f8615d76b20ad66466b172a600e06b9a833729)

intel/tools: Fix detection of enabled shader stages.

We renamed "Function Enable" to "Enable", which broke our detection
of whether shaders are enabled or not. So, we'd see a bunch of HS/DS
packets with program offsets of 0, and think that was a valid TCS/TES.

Fixes: c032cae9ff77e (genxml: Rename "Function Enable" to "Enable".)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 9a0465b3a3a1a6e8beda7a59506c2e1a1aae776f)

i965: Make L3 configuration atom listen for TCS/TES program updates.

The L3 configuration code already considers the TCS and TES programs,
but failed to listen for TCS/TES program changes.

This was somehow missing.

Fixes: e9644cb1f96ccf7e ("i965: Consider tessellation in get_pipeline_state_l3_weights.")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit b8d42cccd053e32ca048645ea7e6f901366e286d)

autotools: Set C++ visibility flags on Intel

These flags are set for C sources, but not C++. This causes symbol
visibility leaks from the C++ parts of the Intel compiler.

Fixes: 700bebb958e93f4d ("i965: Move the back-end compiler to src/intel/compiler")
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 854455498c0370e959c0bb25680641e05faea3e2)

glx/dri3: Fix passing renderType into glXCreateContext

Without this, trying to create a GLX_RGBA_FLOAT_TYPE_ARB context would
fail, because GLX_RGBA_TYPE would be a mismatch with the fbconfig.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit 257edb5b9aedc9fc5d5c13eb2f48a0c11d15456f)

glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)

This is perfectly legal in GL 3.0+.

Fixes piglit/glx-create-context-current-no-framebuffer.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
(cherry picked from commit 033cfb17db85b38bc012d74f30f6c92cddf85216)

nir/spirv: tg4 requires a sampler

Gather operations in both GLSL and SPIR-V require a sampler. Fixes
gathers returning garbage when using separate texture/samplers (on AMD,
was using an invalid sampler descriptor).

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 4122d008466cef47eaa3f958924618060f4e4330)

spirv: Use correct type for sampled images

We should use the result type of the OpSampledImage opcode, rather than
the type of the underlying image/samplers.

This resolves an issue when using separate images and shadow samplers
with glslang. Example:

    layout (...) uniform samplerShadow s0;
    layout (...) uniform texture2D res0;
    ...
    float result = textureLod(sampler2DShadow(res0, s0), uv, 0);

For this, for the combined OpSampledImage, the type of the base image
was being used (which does not have the Depth flag set, whereas the
result type does), therefore it was not being recognised as a shadow
sampler. This led to the wrong LLVM intrinsics being emitted by RADV.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit e9eb3c4753e4f56b03d16d8d6f71d49f1e7b97db)

configure.ac: require xcb* for the omx/va/... when using x11 platform

Targets such as omx and va can work w/o anything X related. Mandate the
xcb* dependencies only when the X11 platform is selected.

Reported-by: Lukas Rusak <lorusak@gmail.com>
Fixes: 63e11ac2b5c ("configure: error out if building VA w/o supported
platform")
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Tested-by: Lukas Rusak <lorusak@gmail.com> (v1)
(cherry picked from commit 85a017230cacd0661570421c8e5b0619e512d33d)

configure.ac: loosen --enable-glvnd check to honour egl

Currently we error out when building GLVND w/o GLX.

That was the original premice before we had EGL. As the commit says,
that error should be reworked to honour both - do so.

v2: Drop noop *);; (Eric)

Reported-by: Lukas Rusak <lorusak@gmail.com>
Fixes: ce562f9e3fa ("EGL: Implement the libglvnd interface for EGL (v3)")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Tested-by: Lukas Rusak <lorusak@gmail.com> (v1)
(cherry picked from commit b4967561c035182b64d3ae0f474d4ef281535ce1)

glsl: Transform fb buffers are only active if a variable uses them

The GL spec will soon be revised to clarify that a buffer binding for
a transform feedback buffer is only required if a variable is actually
defined to use the buffer binding point. Previously a declaration for
the default transform buffer would make it require a binding even if
nothing was declared to use the default buffer.

Affects:
KHR-GL44/45.enhanced_layouts.xfb_stride_of_empty_list
KHR-GL44/45.enhanced_layouts.xfb_stride_of_empty_list_and_api

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 4dc8458cd13154daa48bd97c3f8393daf02aa351)

mesa: rework how we free gl_shader_program_data

When I introduced gl_shader_program_data one of the intentions was to
fix a bug where a failed linking attempt freed data required by a
currently active program. However I seem to have failed to finish
hooking up the final steps required to have the data hang around.

Here we create a fresh instance of gl_shader_program_data every
time we link. gl_program has a reference to gl_shader_program_data
so it will be freed once the program is no longer active.

Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Neil Roberts <nroberts@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102177
(cherry picked from commit 6a72eba755fea15a0d97abb913a6315d9d32e274)

glsl: use the correct parent when allocating program data members

Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 9c33533586476693a197b7179552d140d54f23f2)

glsl: drop cache_fallback

This turned out to be a dead end, it is much easier and less error
prone to just cache the IR used by the drivers backend e.g. TGSI or
NIR.

Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit cf05bb506a075c9e3b8a3c374b928ff0367c49b2)

i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE

This has a bit of a surprising effect:

For the render pipeline, the upload_sampler_state_table atom emits
3DSTATE_BINDING_TABLE_POINTERS_XS.  It tries to avoid this for compute:

   if (GEN_GEN >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) {
      /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
      genX(emit_sampler_state_pointers_xs)(brw, stage_state);
   } ...

However, we were failing to initialize brw->cs.base.stage, so it was
left as 0 (MESA_SHADER_VERTEX), causing this condition to break.  We
then emitted 3DSTATE_SAMPLER_STATE_POINTERS_VS in GPGPU mode, when
trying to upload CS samplers.  Nothing good can come of this.

Found by inspection while debugging a GPU hang.  Jordan believes this
helps the Deus Ex: Mankind Divided benchmark mode's stability when
running with shader cache.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit a16dc04ad51c32e5c7d136e4dd6273d983385d3f)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_context.c

targets/opencl: don't hardcode the icd file install to /etc/...

Use $(sysconfdir) instead of hardcoding /etc.

While the OpenCL spec expects the file in /etc, people building their
stack can override that, esp. !Linux users.

Furthermore this removes a fundamental violation, which results in the
system file being overwritten even as one explicitly sets --prefix
and/or DESTDIR.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-By: Aaron Watry <awatry@gmail.com>
(cherry picked from commit 0cd09585441d15ef1ff49de497008103f0b0e1ac)

intel/fs: Rework zero-length URB write handling

Originally we tried to handle this case based on slots_valid.  However,
there are a number of ways that this can go wrong.  For one, we throw
away any trailing slots which either aren't written or are set to
VARYING_SLOT_PAD.  Second, even if PSIZ is a valid slot, we may not
actually write anything there.  Between the lot of these, it was
possible to end up in a case where we tried to do a regular URB write
but ended up with a length of 1 which is invalid.  This commit moves it
to the end and makes it based on a new boolean flag urb_written.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 7a82ad54bb56cafaeea7f909cd9fc35542c23ba0)

intel/fs: Mark 64-bit values as being contiguous

This isn't often a problem , when we're in a compute shader, we must
push the thread local ID so we decrement the amount of available push
space by 1 and it's no longer even and 64-bit data can, in theory, span
it. By marking those uniforms contiguous, we ensure that they never get
split in half between push and pull constants.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 25f7453c9e6dc7c947b936bdac86680c332362bf)

intel/fs: Fix integer multiplication lowering for src/dst hazards

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit d54f8ec744545673fd78f15ffce3cb4e47d4b5f1)

intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core

The same workaround we need for 64-bit values on little core also takes
care of the Ivy Bridge problem and does so a bit more efficiently so we
can drop that code while we're here.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit fd1bcccc2de9ba6a1ad6171342a155091963c3b9)

intel/eu/reg: Add a subscript() helper

This is similar to the identically named fs_reg helper.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 10e4feed39120072f38274b95e884422f72f360f)

intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all

For some reason, the any/all predicates don't work properly with SIMD32.
In particular, it appears that a SEL with a QtrCtrl of 2H doesn't read
the correct subset of the flag register and you end up getting garbage
in the second half. Work around this by using a pair of 1-wide MOVs and
scattering the result. This fixes the any/all instructions for SIMD32.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 1b8ef49f48ae3634e4903422a9d9c11864c03cb1)

intel/fs: Use an explicit D type for vote any/all/eq intrinsics

The any/all intrinsics return a boolean value so D or UD is the correct
type.  Unfortunately, get_nir_dest has the annoying behavior of
returnning a float type by default.  This causes format conversion which
gives us -1.0f or 0.0f in the register.  If the consumer of the result
does an integer comparison to zero, it will give you the right boolean
value but if we do something more clever based on the 0/~0 assumption
for booleans, this will give the wrong value.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 1f416630079f38110910ba796f70e2b81e9ddbf4)

intel/fs: Use ANY/ALL32 predicates in SIMD32

We have ANY/ALL32 predicates and, for the most part, they work just
fine. (See the next commit for more details.) Also, due to the way
that flag registers are handled in hardware, instruction splitting is
able to split the CMP correctly. Specifically, that hardware looks at
the execution group and knows to shift it's flag usage up correctly so a
2H instruction will write to f0.1 instead of f0.0.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit def013a863558a1f4735d82ef3dfa0f8261fa743)

docs: add sha256 checksums for 17.2.5

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add release notes for 17.2.5

Signed-off-by: Andres Gomez <agomez@igalia.com>

Update version to 17.2.5

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: automake: include git_sha1.h.in in release tarball

fixes: This commit has more than one Fixes tag but the commit it
addresses didn't land in branch.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: added 17.3 nominations.

stable: 17.3 nominations only.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: intel/fs: Alloc pull constants off mem_ctx

stable: This commit addressed earlier commit 8d90e28839 which did not
land in branch.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: etnaviv: don't do resolve-in-place without valid TS

stable: This commit addressed earlier commit 78ade659569 which did not
land in branch.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: i965: fix blorp stage_prog_data->param leak

stable: This commit addressed earlier commit 8d90e28839 which did not
land in branch.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: radv: copy indirect lowering settings from radeonsi

fixes: remove 6ce550453f1 and 059434e1763, which were depending in now
backported 087e010b2b3.

Signed-off-by: Andres Gomez <agomez@igalia.com>

glsl: Allow precision mismatch on dead data with GLSL ES 1.00

Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for
mismatching uniform precision, as required by GLES 3.0 specification and
conformance test-suite.

Several Android applications, including Forge of Empires, have shaders
which violate this rule, on a dead varying that will be eliminated.
The problem affects a big number of applications using Cocos2D engine
and other GLES implementations accept this, this poses a serious
application compatibility issue.

Starting from GLSL ES 3.0, declarations with conflicting precision
qualifiers are explicitly prohibited. However GLSL ES 1.00 does not
clearly specify the behavior, except that

  "Uniforms are defined to behave as if they are using the same storage in
  the vertex and fragment processors and may be implemented this way.
  If uniforms are used in both the vertex and fragment shaders, developers
  should be warned if the precisions are different. Conversion of
  precision should never be implicit."

The word "used" is not clear in this context and might refer to
1) declared (same as GLES 3.x)
2) referred after post-processing, or
3) linked after all optimizations are done.

Looking at existing applications, 2) or 3) seems to be widely adopted.
To avoid compatibility issues, turn the error into a warning if GLSL ES
version is lower than 3.0 and the data is dead in at least one of the
shaders.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97532
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 0886be093fb871b0b6169718277e0f4d18df3ea7)

radv: Disallow indirect outputs for GS on GFX9 as well.

Since it also uses the output vector before writing to memory.

Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit c07d719e8b683e1bf78f187dd17fe4716f4e5e9c)
[Bas Nieuwenhuizen: resolve conflicts]

Conflicts:
src/amd/vulkan/radv_shader.c

radv: Don't use vgpr indexing for outputs on GFX9.

Due to LLVM bugs. Fixes a bunch of dEQP-VK.glsl.indexing.*
tests.

Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 6ce550453f1df64caeb956f215d32da96b89f2b1)
[Bas Nieuwenhuizen: resolve conflicts]

Conflicts:
src/amd/vulkan/radv_shader.c

radv: copy indirect lowering settings from radeonsi

It looks the original indirect mask was probably copied from
ANV.

Sascha Willems demo results:

tessellation ~4000 -> ~4200 fps

V2: continue lowering local indirects due to llvm deficiencies.

(cherry picked from commit 087e010b2b3dd83a539f97203909d6c43b5da87c)
[Bas Nieuwenhuizen: patch is a backport for 17.2 of the cherry-pick above]

radv: add initial copy descriptor support. (v2)

It appears the latest dota2 vulkan uses this,
and we get a hang in VR mode without it.

v2: remove finishme I left in after finishing.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 4bcb48b8319fd8185a326bbd1f77191bddd35506)

radv: free attachments on end command buffer.

If we allocate attachments in the begin command buffer due to the
render pass continue bit, we were leaking them.

Since renderpasses inside a cmd buffer malloc/free these properly,
and set to NULL, we just need to call free at end.

Fixes a memory leak with multithreading demo.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit f0ae06a13c1a60f58de77401f705eaf620b5b822)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/amd/vulkan/radv_cmd_buffer.c

i915g: make gears run again.

We need to validate some structs exist before we dirty the states, and
avoid the problem in some other places.

Fixes: e027935a7 ("st/mesa: don't update unrelated states in non-draw calls such as Clear")
(cherry picked from commit cc69f2385ee5405cd1bef746d3e9006fc5430545)

radv: Don't expose heaps with 0 memory.

It confuses CTS. This pregenerates the heap info into the
physical device, so we can use it for translating contiguous
indices into our "standard" ones.

This also makes the WSI a bit smarter in case the first preferred
heap does not exist.

Reviewed-by: Dave Airlie <airlied@redhat.com>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 806721429afa090380bf39a4958fe4e21c63816c)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/amd/vulkan/radv_device.c
src/amd/vulkan/radv_private.h
src/amd/vulkan/radv_wsi.c

vc4: fix release build

Mesa's DEBUG and assert's NDEBUG are not tied to each other, so we need
to explicitly compile this code out.

Fixes: 3df78928786134874eafa "vc4: Drop reloc_count tracking for debug
asserts on non-debug builds."
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 5d44e35a8f3967b40db153fdcedb9294d44ae5c4)

r600/sb: bail out if prepare_alu_group() doesn't find a proper scheduling

It is possible that the optimizer ends up in an infinite loop in
post_scheduler::schedule_alu(), because post_scheduler::prepare_alu_group()
does not find a proper scheduling. This can be deducted from
pending.count() being larger than zero and not getting smaller.

This patch works around this problem by signalling this failure so that the
optimizers bails out and the un-optimized shader is used.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103142
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 69eee511c631a8372803f175bd6f5a9551230424)

nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARB

Previously the values were calculated by just shifting ~0 by the
invocation ID. This would end up including bits that are higher than
gl_SubGroupSizeARB. The corresponding CTS test effectively requires that
these high bits be zero so it was failing. There is a Piglit test as
well but this appears to checking the wrong values so it passes.

For the two greater-than bitmasks, this patch adds an extra mask with
(~0>>(64-gl_SubGroupSizeARB)) to force these bits to zero.

Fixes: KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680#c3
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Neil Roberts <nroberts@igalia.com>
(cherry picked from commit b697ece10aa041b8653eb184d73dcf5b846729a3)

i965: Check CCS_E compatibility for texture view rendering

Only use CCS_E to render to a texture that is CCS_E-compatible with the
original texture's miptree (linear) format. This prevents render
operations from writing data that can't be decoded with the original
miptree format.

On Gen10, with the new CCS_E-enabled formats handled, this enables the
driver to pass the arb_texture_view-rendering-formats piglit test.

v2. Add a TODO for texturing. (Jason)

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 9e849eb8bb97259136b40dc2b06f42a81cfd3dae)

intel/compiler/gen9: Pixel shader header only workaround

Fixes intermittent GPU hangs on Broxton with an Intel internal
test case.

There are plenty of similar fragment shaders in piglit that do
not use any varyings and any uniforms. According to the
documentation special timing is needed between pipeline stages.
Apparently we just don't hit that with piglit. Even with the
failing test case one doesn't always get the hang.

Moreover, according to the error states the hang happens
significantly later than the execution of the problematic shader.
There are multiple render cycles (primitive submissions) in between.
I've also seen error states where the ACTHD points outside the
batch. Almost as if the hardware writes somewhere that gets used
later on. That would also explain why piglit doesn't suffer from
this - most tests kick off one render cycle and any corruption
is left unseen.

v2 (Ken): Instead of enabling push constants, enable one of the
inputs (PSIZ).
v3 (Ken, Jason): Use LAYER instead making vulkan emit_3dstate_sbe()
happy.

Cc: "17.3 17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
(cherry picked from commit 97e01adfd549c260efd615289938265306d42a05)

mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.

According to the ARB_ES3_1_compatibility specification,
glGetFramebufferAttachmentParameteriv is supposed to accept BACK,
and it behaves exactly like BACK_LEFT.

Fixes a GL error in GFXBench 5 Aztec Ruins.

Cc: "17.3 17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 4f538c3f99b25dc96cd20314ce7785fd4d333be1)

i965: unref push_const_bo in intelDestroyContext

Valgrind shows that leak is caused by gen6_upload_push_constant, add
unref push_const_bo per stage to destructor to fix this (like done for
scratch_bo).

   ==10952== 144 bytes in 1 blocks are definitely lost in loss record 44 of 66
   ==10952==    at 0x4C30A1E: calloc (vg_replace_malloc.c:711)
   ==10952==    by 0x8C02847: bo_alloc_internal.constprop.10 (brw_bufmgr.c:344)
   ==10952==    by 0x8C425C4: intel_upload_space (intel_upload.c:101)
   ==10952==    by 0x8C22ED0: gen6_upload_push_constants (gen6_constant_state.c:154)

v2: remove if conditions, brw_bo_unreference handles NULL (Ken, Emil)

Fixes: 24891d7c05 ("i965: Store per-stage push constant BO pointers.")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 0b131ca427d788ae08426bdeddb8f4bd3c7da202)

i965/miptree: Take an isl_format in render_aux_usage

Not all rendering matches the miptree format.  We allow rendering to
texture views so there are cases where it may not match.  In those
cases, our current scheme of just passing the value of ctx->sRGBEnabled
isn't viable.  Instead, just do what we do for texturing and pass the
view format in directly.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 39c5c12f8fbee9eec26a627f247d1f3ef7d4bf39)
[Andres Gomez: remove code which was trivially modified previously]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_draw.c
src/mesa/drivers/dri/i965/brw_wm_surface_state.c

i965/blorp: Use more temporary isl_format variables

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 78e50185d6f9546f8b09cf281f5e5a17195a7ee5)

i965/blorp: Use blorp_to_isl_format for src_isl_format in blit_miptrees

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 94389943b63bf8e25fecbbdf357ae5da100d2fc9)

spirv: Claim support for the simple memory model

It's rather surprising that we've never actually hit this before.
Aparently, Ian's SPIR-V generator currently claims the Simple when you
don't do anything complex. We really shouldn't assert-fail on it.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 8ab9820d34d3a454e455c99e28ed2b6031b25b0f)

radeon/video: add gfx9 offsets when rejoin the video surface

For CPU access.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit ea3dc75d72c148dabffa71e8657bfd831ad0afe9)

amd/common/gfx9: workaround DCC corruption more conservatively

Fixes KHR-GL45.texture_swizzle.smoke and others on Vega.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102809
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit f9ccfda9bc8166f833fdb64adf1eca5b8ee69251)

ac/surface/gfx9: don't allow DCC for the smallest mipmap levels

This fixes garbage there if we don't flush TC L2 after rendering.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 759526813be137f7f139d6b4e56c5afeb8ba53c9)

st/dri: don't expose modifiers in EGL if the driver doesn't implement them

This unbreaks waffle/gbm (piglit/gbm) which fails initialization.

v2: also don't set queryDmaBufFormats

Reviewed-by: Daniel Stone <daniel@fooishbar.org>
(cherry picked from commit a65db0ad1c3ace58fbc81b6860e28c0a7645257c)

docs: add sha256 checksums for 17.2.4

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add release notes for 17.2.4

Signed-off-by: Andres Gomez <agomez@igalia.com>

Update version to 17.2.4

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: broadcom/vc5: Propagate vc4 aliasing fix to vc5.

extra: Commit is not applicable when ade416d0236 is missing.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: mesa/bufferobj: don't double negate the range

fixes: This commit addressed earlier commit 35ac13ed3 which did not
land in branch.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: radv: Disallow indirect outputs for GS on GFX9 as well.

fixes: Commit is not applicable when 6ce550453f1 is missing.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: radv: Don't use vgpr indexing for outputs on GFX9.

fixes: Commit is not applicable when 087e010b2b3 is missing.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: added 17.3 nominations.

stable: 17.3 nominations only.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: glsl: fix derived cs variables

stable: Commit is too big for stable at this point.

Signed-off-by: Andres Gomez <agomez@igalia.com>

cherry-ignore: configure.ac: rework llvm detection and handling

stable: Commits are too invasive for 17.2.

Signed-off-by: Andres Gomez <agomez@igalia.com>

intel/eu: Use EXECUTE_1 for JMPI

The PRM says "The execution size must be 1."  In 73137997e23ff6c11, the
execution size was set to 1 when it should have been BRW_EXECUTE_1
(which maps to 0).  Later, in dc2d3a7f5c217a7cee9, JMPI was used for
line AA on gen6 and earlier and we started manually stomping the
exeution size to BRW_EXECUTE_1 in the generator.  This commit fixes the
original bug and makes brw_JMPI just do the right thing.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 73137997e23ff6c1145d036315d1a9ad96651281
(cherry picked from commit 562b8d458c2de262019da2c056f75cb9feb5ee54)

anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nir

We currently have a bug where nir_lower_system_values gets called before
nir_lower_var_copies so it will miss any system value uses which come
from a copy_var intrinsic. Moving it to after brw_preprocess_nir fixes
this problem.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 279f8fb69cf68d05287e14f60cf67fc025643bc4)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/intel/vulkan/anv_pipeline.c

intel/fs: Handle flag read/write aliasing in needs_src_copy

In order to implement the ballot intrinsic, we do a MOV from flag
register to some GRF. If that GRF is used in a SEL, cmod propagation
helpfully changes it into a MOV from the flag register with a cmod.
This is perfectly valid but when lower_simd_width comes along, it simply
splits into two instructions which both have conditional modifiers.
This is a problem since we're reading the flag register. This commit
makes us check whether or not flags_written() overlaps with the flag
values that we are reading via the instruction source and, if we have
any interference, will force us to emit a copy of the source.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit fa6e74e33e5bc5f6fba8f9de76b8b059515e708f)

clover: Fix compilation after clang r315871

v2: use a more generic compat function
v3: rename and formatting cleanup

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103388
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a6d38f476beaaf0a9677cfc168172121b5779570)

nir/intrinsics: Set the correct num_indices for load_output

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit c1b84256ccc443a9792893bc780bba970c0dcd4e)

ac/nir: generate correct instruction for atomic min/max on unsigned images

v2: fix silly typo

Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit 27a0b24bf238342031e0709584e4d71ab228f1ec)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c