hw/i386.reference/c07.htm

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   4 <TITLE>80386 Programmer's Reference Manual -- Chapter 07</TITLE>
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  11 <A HREF="s06_05.htm">6.5  Combining Page and Segment Protection</A><BR>
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  16 <H1>Chapter 7  Multitasking</H1>
  17 <P>
  18 To provide efficient, protected multitasking, the 80386 employs several
  19 special data structures. It does not, however, use special instructions to
  20 control multitasking; instead, it interprets ordinary control-transfer
  21 instructions differently when they refer to the special data structures. The
  22 registers and data structures that support multitasking are:
  23 <UL>
  24 <LI>Task state segment
  25 <LI>Task state segment descriptor
  26 <LI>Task register
  27 <LI>Task gate descriptor
  28 </UL>
  29 With these structures the 80386 can rapidly switch execution from one task
  30 to another, saving the context of the original task so that the task can be
  31 restarted later. In addition to the simple task switch, the 80386 offers two
  32 other task-management features:
  33 <OL>
  34 <LI>Interrupts and exceptions can cause task switches (if needed in the
  35       system design). The processor not only switches automatically to the
  36       task that handles the interrupt or exception, but it automatically
  37       switches back to the interrupted task when the interrupt or exception
  38       has been serviced. Interrupt tasks may interrupt lower-priority
  39       interrupt tasks to any depth.
  40
  41 <LI>With each switch to another task, the 80386 can also switch to
  42       another LDT and to another page directory. Thus each task can have a
  43       different logical-to-linear mapping and a different linear-to-physical
  44       mapping. This is yet another protection feature, because tasks can be
  45       isolated and prevented from interfering with one another.
  46 </OL>
  47 <P>
  48 <A HREF="s07_01.htm">7.1  Task State Segment</A><BR>
  49 <A HREF="s07_02.htm">7.2  TSS Descriptor</A><BR>
  50 <A HREF="s07_03.htm">7.3  Task Register</A><BR>
  51 <A HREF="s07_04.htm">7.4  Task Gate Descriptor</A><BR>
  52 <A HREF="s07_05.htm">7.5  Task Switching</A><BR>
  53 <A HREF="s07_06.htm">7.6  Task Linking</A><BR>
  54 <A HREF="s07_07.htm">7.7  Task Address Space</A>
  55 <P>
  56 <HR>
  57 <P>
  58 <B>up:</B> <A HREF="toc.htm">
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  61 <A HREF="s06_05.htm">6.5  Combining Page and Segment Protection</A><BR>
  62 <B>next:</B> <A HREF="s07_01.htm">7.1  Task State Segment</A>
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