From 553aeae9c63f789c969a954983e537244934903a Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Sat, 19 May 2012 13:16:17 +0200 Subject: [PATCH] imx233: fix clkctrl naming Move to a more consistent naming convention like the other devices Change-Id: I4ddbbee27ee9f5ae775c5776592ec7ce02b30948 --- firmware/target/arm/imx233/audioout-imx233.c | 4 +- firmware/target/arm/imx233/clkctrl-imx233.c | 109 +++++++++++---------- firmware/target/arm/imx233/clkctrl-imx233.h | 41 ++++---- firmware/target/arm/imx233/debug-imx233.c | 18 ++-- .../arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c | 8 +- firmware/target/arm/imx233/ssp-imx233.c | 14 +-- firmware/target/arm/imx233/timrot-imx233.c | 2 +- firmware/target/arm/imx233/usb-imx233.c | 4 +- 8 files changed, 101 insertions(+), 99 deletions(-) diff --git a/firmware/target/arm/imx233/audioout-imx233.c b/firmware/target/arm/imx233/audioout-imx233.c index e03de5c861..4e1ff27ad2 100644 --- a/firmware/target/arm/imx233/audioout-imx233.c +++ b/firmware/target/arm/imx233/audioout-imx233.c @@ -30,7 +30,7 @@ void imx233_audioout_preinit(void) /* Enable AUDIOOUT block */ imx233_reset_block(&HW_AUDIOOUT_CTRL); /* Enable digital filter clock */ - imx233_enable_xtal_clock(XTAL_FILT, true); + imx233_clkctrl_enable_xtal(XTAL_FILT, true); /* Enable DAC */ __REG_CLR(HW_AUDIOOUT_ANACLKCTRL) = HW_AUDIOOUT_ANACLKCTRL__CLKGATE; /* Set capless mode */ @@ -76,7 +76,7 @@ void imx233_audioout_close(void) /* Gate off DAC */ __REG_SET(HW_AUDIOOUT_ANACLKCTRL) = HW_AUDIOOUT_ANACLKCTRL__CLKGATE; /* Disable digital filter clock */ - imx233_enable_xtal_clock(XTAL_FILT, false); + imx233_clkctrl_enable_xtal(XTAL_FILT, false); /* will also gate off the module */ __REG_CLR(HW_AUDIOOUT_CTRL) = HW_AUDIOOUT_CTRL__RUN; } diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c index bfa707e3be..064ee8013b 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.c +++ b/firmware/target/arm/imx233/clkctrl-imx233.c @@ -23,7 +23,7 @@ #define __CLK_CLKGATE (1 << 31) #define __CLK_BUSY (1 << 29) -void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable) +void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable) { if(enable) __REG_CLR(HW_CLKCTRL_XTAL) = xtal_clk; @@ -31,12 +31,12 @@ void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable) __REG_SET(HW_CLKCTRL_XTAL) = xtal_clk; } -bool imx233_is_xtal_clock_enable(enum imx233_xtal_clk_t clk) +bool imx233_clkctrl_is_xtal_enable(enum imx233_xtal_clk_t clk) { return HW_CLKCTRL_XTAL & clk; } -void imx233_enable_clock(enum imx233_clock_t clk, bool enable) +void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable) { volatile uint32_t *REG; switch(clk) @@ -60,7 +60,7 @@ void imx233_enable_clock(enum imx233_clock_t clk, bool enable) } } -bool imx233_is_clock_enable(enum imx233_clock_t clk) +bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t clk) { volatile uint32_t *REG; switch(clk) @@ -74,7 +74,7 @@ bool imx233_is_clock_enable(enum imx233_clock_t clk) return !((*REG) & __CLK_CLKGATE); } -void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) +void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div) { /* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */ switch(clk) @@ -101,7 +101,7 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) } } -int imx233_get_clock_divisor(enum imx233_clock_t clk) +int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk) { switch(clk) { @@ -119,7 +119,7 @@ int imx233_get_clock_divisor(enum imx233_clock_t clk) } } -void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) +void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) { /* NOTE: HW_CLKCTRL_FRAC only support byte access ! */ volatile uint8_t *REG; @@ -142,7 +142,7 @@ void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) *REG = HW_CLKCTRL_FRAC_XX__CLKGATEXX;; } -int imx233_get_fractional_divisor(enum imx233_clock_t clk) +int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk) { /* NOTE: HW_CLKCTRL_FRAC only support byte access ! */ volatile uint8_t *REG; @@ -166,7 +166,7 @@ int imx233_get_fractional_divisor(enum imx233_clock_t clk) return *REG & ~HW_CLKCTRL_FRAC_XX__XX_STABLE; } -void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass) +void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass) { uint32_t msk; switch(clk) @@ -184,7 +184,7 @@ void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass) __REG_CLR(HW_CLKCTRL_CLKSEQ) = msk; } -bool imx233_get_bypass_pll(enum imx233_clock_t clk) +bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk) { uint32_t msk; switch(clk) @@ -199,7 +199,7 @@ bool imx233_get_bypass_pll(enum imx233_clock_t clk) return HW_CLKCTRL_CLKSEQ & msk; } -void imx233_enable_usb_pll(bool enable) +void imx233_clkctrl_enable_usb_pll(bool enable) { if(enable) __REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS; @@ -207,23 +207,23 @@ void imx233_enable_usb_pll(bool enable) __REG_CLR(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS; } -bool imx233_is_usb_pll_enable(void) +bool imx233_clkctrl_is_usb_pll_enabled(void) { return HW_CLKCTRL_PLLCTRL0 & HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS; } -void imx233_set_auto_slow_divisor(enum imx233_as_div_t div) +void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div) { __REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__SLOW_DIV_BM; __REG_SET(HW_CLKCTRL_HBUS) = div; } -enum imx233_as_div_t imx233_get_auto_slow_divisor(void) +enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void) { return __XTRACT(HW_CLKCTRL_HBUS, SLOW_DIV); } -void imx233_enable_auto_slow(bool enable) +void imx233_clkctrl_enable_auto_slow(bool enable) { if(enable) __REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE; @@ -231,12 +231,12 @@ void imx233_enable_auto_slow(bool enable) __REG_SET(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE; } -bool imx233_is_auto_slow_enable(void) +bool imx233_clkctrl_is_auto_slow_enabled(void) { return HW_CLKCTRL_HBUS & HW_CLKCTRL_HBUS__AUTO_SLOW_MODE; } -void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable) +void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable) { if(enable) __REG_SET(HW_CLKCTRL_HBUS) = monitor; @@ -244,17 +244,17 @@ void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enab __REG_CLR(HW_CLKCTRL_HBUS) = monitor; } -bool imx233_is_auto_slow_monitor_enable(enum imx233_as_monitor_t monitor) +bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor) { return HW_CLKCTRL_HBUS & monitor; } -unsigned imx233_get_clock_freq(enum imx233_clock_t clk) +unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk) { switch(clk) { case CLK_PLL: /* PLL: 480MHz when enable */ - return imx233_is_clock_enable(CLK_PLL) ? 480000 : 0; + return imx233_clkctrl_is_clock_enabled(CLK_PLL) ? 480000 : 0; case CLK_XTAL: /* crystal: 24MHz */ return 24000; case CLK_CPU: @@ -263,78 +263,78 @@ unsigned imx233_get_clock_freq(enum imx233_clock_t clk) /* In bypass mode: clk_p derived from clk_xtal via int/binfrac divider * otherwise, clk_p derived from clk_cpu via int div and clk_cpu * derived from clk_pll fracdiv */ - if(imx233_get_bypass_pll(CLK_CPU)) + if(imx233_clkctrl_get_bypass_pll(CLK_CPU)) { - ref = imx233_get_clock_freq(CLK_XTAL); + ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); /* Integer divide mode vs fractional divide mode */ if(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__DIV_XTAL_FRAC_EN) return (ref * __XTRACT(HW_CLKCTRL_CPU, DIV_XTAL)) / 32; else - return ref / imx233_get_clock_divisor(CLK_CPU); + return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU); } else { - ref = imx233_get_clock_freq(CLK_PLL); + ref = imx233_clkctrl_get_clock_freq(CLK_PLL); /* fractional divider enable ? */ - if(imx233_get_fractional_divisor(CLK_CPU) != 0) - ref = (ref * 18) / imx233_get_fractional_divisor(CLK_CPU); - return ref / imx233_get_clock_divisor(CLK_CPU); + if(imx233_clkctrl_get_fractional_divisor(CLK_CPU) != 0) + ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_CPU); + return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU); } } case CLK_HBUS: { /* Derived from clk_p via integer/fractional div */ - unsigned ref = imx233_get_clock_freq(CLK_CPU); - if(imx233_get_fractional_divisor(CLK_HBUS) != 0) - ref = (ref * imx233_get_fractional_divisor(CLK_HBUS)) / 32; - if(imx233_get_clock_divisor(CLK_HBUS) != 0) - ref /= imx233_get_clock_divisor(CLK_HBUS); + unsigned ref = imx233_clkctrl_get_clock_freq(CLK_CPU); + if(imx233_clkctrl_get_fractional_divisor(CLK_HBUS) != 0) + ref = (ref * imx233_clkctrl_get_fractional_divisor(CLK_HBUS)) / 32; + if(imx233_clkctrl_get_clock_divisor(CLK_HBUS) != 0) + ref /= imx233_clkctrl_get_clock_divisor(CLK_HBUS); return ref; } case CLK_IO: { /* Derived from clk_pll via fracdiv */ - unsigned ref = imx233_get_clock_freq(CLK_PLL); - if(imx233_get_fractional_divisor(CLK_IO) != 0) - ref = (ref * 18) / imx233_get_fractional_divisor(CLK_IO); + unsigned ref = imx233_clkctrl_get_clock_freq(CLK_PLL); + if(imx233_clkctrl_get_fractional_divisor(CLK_IO) != 0) + ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_IO); return ref; } case CLK_PIX: { unsigned ref; /* Derived from clk_pll or clk_xtal */ - if(!imx233_is_clock_enable(CLK_PIX)) + if(!imx233_clkctrl_is_clock_enabled(CLK_PIX)) ref = 0; - else if(imx233_get_bypass_pll(CLK_PIX)) - ref = imx233_get_clock_freq(CLK_XTAL); + else if(imx233_clkctrl_get_bypass_pll(CLK_PIX)) + ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); else { - ref = imx233_get_clock_freq(CLK_PLL); - if(imx233_get_fractional_divisor(CLK_PIX) != 0) - ref = (ref * 18) / imx233_get_fractional_divisor(CLK_PIX); + ref = imx233_clkctrl_get_clock_freq(CLK_PLL); + if(imx233_clkctrl_get_fractional_divisor(CLK_PIX) != 0) + ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_PIX); } - return ref / imx233_get_clock_divisor(CLK_PIX); + return ref / imx233_clkctrl_get_clock_divisor(CLK_PIX); } case CLK_SSP: { unsigned ref; /* Derived from clk_pll or clk_xtal */ - if(!imx233_is_clock_enable(CLK_SSP)) + if(!imx233_clkctrl_is_clock_enabled(CLK_SSP)) ref = 0; - else if(imx233_get_bypass_pll(CLK_SSP)) - ref = imx233_get_clock_freq(CLK_XTAL); + else if(imx233_clkctrl_get_bypass_pll(CLK_SSP)) + ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); else - ref = imx233_get_clock_freq(CLK_IO); - return ref / imx233_get_clock_divisor(CLK_SSP); + ref = imx233_clkctrl_get_clock_freq(CLK_IO); + return ref / imx233_clkctrl_get_clock_divisor(CLK_SSP); } case CLK_EMI: { unsigned ref; /* Derived from clk_pll or clk_xtal */ - if(imx233_get_bypass_pll(CLK_EMI)) + if(imx233_clkctrl_get_bypass_pll(CLK_EMI)) { - ref = imx233_get_clock_freq(CLK_XTAL); + ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); if(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__CLKGATE) return 0; else @@ -342,14 +342,15 @@ unsigned imx233_get_clock_freq(enum imx233_clock_t clk) } else { - ref = imx233_get_clock_freq(CLK_PLL); - if(imx233_get_fractional_divisor(CLK_EMI) != 0) - ref = (ref * 18) / imx233_get_fractional_divisor(CLK_EMI); - return ref / imx233_get_clock_divisor(CLK_EMI); + ref = imx233_clkctrl_get_clock_freq(CLK_PLL); + if(imx233_clkctrl_get_fractional_divisor(CLK_EMI) != 0) + ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_EMI); + return ref / imx233_clkctrl_get_clock_divisor(CLK_EMI); } } case CLK_XBUS: - return imx233_get_clock_freq(CLK_XTAL) / imx233_get_clock_divisor(CLK_XBUS); + return imx233_clkctrl_get_clock_freq(CLK_XTAL) / + imx233_clkctrl_get_clock_divisor(CLK_XBUS); default: return 0; } diff --git a/firmware/target/arm/imx233/clkctrl-imx233.h b/firmware/target/arm/imx233/clkctrl-imx233.h index ae2e0465a0..d49e8b2802 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.h +++ b/firmware/target/arm/imx233/clkctrl-imx233.h @@ -132,6 +132,7 @@ enum imx233_xtal_clk_t XTAL_FILT = 1 << 30, XTAL_DRI = 1 << 28, XTAL_TIMROT = 1 << 26, + XTAM_PWM = 1 << 29, }; /* Auto-Slow monitoring */ @@ -158,28 +159,28 @@ enum imx233_as_div_t }; /* can use a mask of clocks */ -void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable); -bool imx233_is_xtal_clock_enable(enum imx233_xtal_clk_t clk); +void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable); +void imx233_clkctrl_is_xtal_enabled(enum imx233_xtal_clk_t xtal_clk, bool enable); /* only use it for non-fractional clocks (ie not for IO) */ -void imx233_enable_clock(enum imx233_clock_t clk, bool enable); -bool imx233_is_clock_enable(enum imx233_clock_t cl); -void imx233_set_clock_divisor(enum imx233_clock_t clk, int div); -int imx233_get_clock_divisor(enum imx233_clock_t clk); +void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable); +bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t cl); +void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div); +int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk); /* call with fracdiv=0 to disable it */ -void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv); +void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv); /* 0 means fractional dividor disable */ -int imx233_get_fractional_divisor(enum imx233_clock_t clk); -void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass); -bool imx233_get_bypass_pll(enum imx233_clock_t clk); -void imx233_enable_usb_pll(bool enable); -bool imx233_is_usb_pll_enable(void); -unsigned imx233_get_clock_freq(enum imx233_clock_t clk); - -void imx233_set_auto_slow_divisor(enum imx233_as_div_t div); -enum imx233_as_div_t imx233_get_auto_slow_divisor(void); -void imx233_enable_auto_slow(bool enable); -bool imx233_is_auto_slow_enable(void); -void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable); -bool imx233_is_auto_slow_monitor_enable(enum imx233_as_monitor_t monitor); +int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk); +void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass); +bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk); +void imx233_clkctrl_enable_usb_pll(bool enable); +bool imx233_clkctrl_is_usb_pll_enabled(void); +unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk); + +void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div); +enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void); +void imx233_clkctrl_enable_auto_slow(bool enable); +bool imx233_clkctrl_is_auto_slow_enabled(void); +void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable); +bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor); #endif /* CLKCTRL_IMX233_H */ diff --git a/firmware/target/arm/imx233/debug-imx233.c b/firmware/target/arm/imx233/debug-imx233.c index 59792c17a8..0702fcbebc 100644 --- a/firmware/target/arm/imx233/debug-imx233.c +++ b/firmware/target/arm/imx233/debug-imx233.c @@ -235,19 +235,19 @@ bool dbg_hw_info_clkctrl(void) #define c dbg_clk[i] lcd_putsf(0, i + 1, "%4s", c.name); if(c.has_enable) - lcd_putsf(5, i + 1, "%2d", imx233_is_clock_enable(c.clk)); + lcd_putsf(5, i + 1, "%2d", imx233_clkctrl_is_clock_enabled(c.clk)); if(c.has_bypass) - lcd_putsf(8, i + 1, "%2d", imx233_get_bypass_pll(c.clk)); - if(c.has_idiv && imx233_get_clock_divisor(c.clk) != 0) - lcd_putsf(10, i + 1, "%4d", imx233_get_clock_divisor(c.clk)); - if(c.has_fdiv && imx233_get_fractional_divisor(c.clk) != 0) - lcd_putsf(16, i + 1, "%4d", imx233_get_fractional_divisor(c.clk)); + lcd_putsf(8, i + 1, "%2d", imx233_clkctrl_get_bypass_pll(c.clk)); + if(c.has_idiv && imx233_clkctrl_get_clock_divisor(c.clk) != 0) + lcd_putsf(10, i + 1, "%4d", imx233_clkctrl_get_clock_divisor(c.clk)); + if(c.has_fdiv && imx233_clkctrl_get_fractional_divisor(c.clk) != 0) + lcd_putsf(16, i + 1, "%4d", imx233_clkctrl_get_fractional_divisor(c.clk)); if(c.has_freq) - lcd_putsf(21, i + 1, "%9d", imx233_get_clock_freq(c.clk)); + lcd_putsf(21, i + 1, "%9d", imx233_clkctrl_get_clock_freq(c.clk)); #undef c } int line = ARRAYLEN(dbg_clk) + 1; - lcd_putsf(0, line, "auto slow: %d", imx233_is_auto_slow_enable()); + lcd_putsf(0, line, "auto slow: %d", imx233_clkctrl_is_auto_slow_enabled()); line++; lcd_putsf(0, line, "as monitor: "); int x_off = 12; @@ -255,7 +255,7 @@ bool dbg_hw_info_clkctrl(void) unsigned line_w = lcd_getwidth() / font_get_width(font_get(lcd_getfont()), ' '); for(unsigned i = 0; i < ARRAYLEN(dbg_as_monitor); i++) { - if(!imx233_is_auto_slow_monitor_enable(dbg_as_monitor[i].monitor)) + if(!imx233_clkctrl_is_auto_slow_monitor_enabled(dbg_as_monitor[i].monitor)) continue; if(!first) { diff --git a/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c b/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c index 3913bf6906..39469028a0 100644 --- a/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c +++ b/firmware/target/arm/imx233/sansa-fuzeplus/lcd-fuzeplus.c @@ -157,10 +157,10 @@ static inline uint32_t decode_18_to_16(uint32_t a) static void setup_lcdif_clock(void) { /* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */ - imx233_enable_clock(CLK_PIX, false); - imx233_set_clock_divisor(CLK_PIX, 1); - imx233_set_bypass_pll(CLK_PIX, true); /* use XTAL */ - imx233_enable_clock(CLK_PIX, true); + imx233_clkctrl_enable_clock(CLK_PIX, false); + imx233_clkctrl_set_clock_divisor(CLK_PIX, 1); + imx233_clkctrl_set_bypass_pll(CLK_PIX, true); /* use XTAL */ + imx233_clkctrl_enable_clock(CLK_PIX, true); } static uint32_t i80_read_register(uint32_t data_out) diff --git a/firmware/target/arm/imx233/ssp-imx233.c b/firmware/target/arm/imx233/ssp-imx233.c index cbf537dd07..bdbde9ec93 100644 --- a/firmware/target/arm/imx233/ssp-imx233.c +++ b/firmware/target/arm/imx233/ssp-imx233.c @@ -106,11 +106,11 @@ void imx233_ssp_start(int ssp) /** 2.3.1: the clk_ssp maximum frequency is 102.858 MHz */ /* fracdiv = 18 => clk_io = pll = 480Mhz * intdiv = 5 => clk_ssp = 96Mhz */ - imx233_set_fractional_divisor(CLK_IO, 18); - imx233_enable_clock(CLK_SSP, false); - imx233_set_clock_divisor(CLK_SSP, 5); - imx233_set_bypass_pll(CLK_SSP, false); /* use IO */ - imx233_enable_clock(CLK_SSP, true); + imx233_clkctrl_set_fractional_divisor(CLK_IO, 18); + imx233_clkctrl_enable_clock(CLK_SSP, false); + imx233_clkctrl_set_clock_divisor(CLK_SSP, 5); + imx233_clkctrl_set_bypass_pll(CLK_SSP, false); /* use IO */ + imx233_clkctrl_enable_clock(CLK_SSP, true); } ssp_nr_in_use++; } @@ -128,8 +128,8 @@ void imx233_ssp_stop(int ssp) ssp_nr_in_use--; if(ssp_nr_in_use == 0) { - imx233_enable_clock(CLK_SSP, false); - imx233_set_fractional_divisor(CLK_IO, 0); + imx233_clkctrl_enable_clock(CLK_SSP, false); + imx233_clkctrl_set_fractional_divisor(CLK_IO, 0); } } diff --git a/firmware/target/arm/imx233/timrot-imx233.c b/firmware/target/arm/imx233/timrot-imx233.c index b7cf588cf3..24ed0096ab 100644 --- a/firmware/target/arm/imx233/timrot-imx233.c +++ b/firmware/target/arm/imx233/timrot-imx233.c @@ -75,5 +75,5 @@ void imx233_timrot_init(void) { imx233_reset_block(&HW_TIMROT_ROTCTRL); /* enable xtal path to timrot */ - imx233_enable_xtal_clock(XTAL_TIMROT, true); + imx233_clkctrl_enable_xtal(XTAL_TIMROT, true); } diff --git a/firmware/target/arm/imx233/usb-imx233.c b/firmware/target/arm/imx233/usb-imx233.c index 904f84b948..304018b09b 100644 --- a/firmware/target/arm/imx233/usb-imx233.c +++ b/firmware/target/arm/imx233/usb-imx233.c @@ -69,7 +69,7 @@ void usb_enable(bool on) { if(on) { - imx233_enable_usb_pll(true); + imx233_clkctrl_enable_usb_pll(true); imx233_enable_usb_phy(true); imx233_enable_usb_controller(true); usb_core_init(); @@ -79,6 +79,6 @@ void usb_enable(bool on) usb_core_exit(); imx233_enable_usb_controller(false); imx233_enable_usb_phy(false); - imx233_enable_usb_pll(false); + imx233_clkctrl_enable_usb_pll(false); } } -- 2.11.4.GIT