From 5513c6db56e6de82561bbf90f3f0af12045be6d5 Mon Sep 17 00:00:00 2001 From: Marcin Bukat Date: Thu, 22 Mar 2012 23:45:27 +0100 Subject: [PATCH] rk27xx: implement system_init() For now it contains explicit SDRAM setup, cutting clock for unused modules and turning off unused PLLs. This improves slightly mem throughput as well as saves quite a bit of power. Change-Id: I19a2827ac90a6868856c676fbe1e051c42f0d608 --- firmware/target/arm/rk27xx/system-rk27xx.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/firmware/target/arm/rk27xx/system-rk27xx.c b/firmware/target/arm/rk27xx/system-rk27xx.c index ac423955d6..0e7fca4c06 100644 --- a/firmware/target/arm/rk27xx/system-rk27xx.c +++ b/firmware/target/arm/rk27xx/system-rk27xx.c @@ -117,6 +117,34 @@ void fiq_dummy(void) void system_init(void) { + /* SDRAM tweaks */ + MCSDR_MODE = (2<<4)|3; /* CAS=2, burst=8 */ + MCSDR_T_REF = (125*100) >> 3; /* 125/8 = 15.625 autorefresh interval */ + MCSDR_T_RFC = (64*100) / 1000; /* autorefresh period */ + MCSDR_T_RP = 1; /* precharge period */ + MCSDR_T_RCD = 1; /* active to RD/WR delay */ + + /* turn off clock for unused modules */ + SCU_CLKCFG |= (1<<31) | /* WDT pclk */ + (1<<30) | /* RTC pclk */ + (1<<26) | /* HS_ADC clock */ + (1<<25) | /* HS_ADC HCLK */ + (1<<21) | /* SPI clock */ + (1<<19) | /* UART1 clock */ + (1<<18) | /* UART0 clock */ + (1<<15) | /* VIP clock */ + (1<<14) | /* VIP HCLK */ + (1<<13) | /* LCDC clock */ + (1<<9) | /* NAND HCLK */ + (1<<5) | /* USB host HCLK */ + (1<<1) | /* DSP clock */ + (1<<0); /* OTP clock (dunno what it is */ + + /* turn off DSP pll */ + SCU_PLLCON2 |= (1<<22); + + /* turn off codec pll */ + SCU_PLLCON3 |= (1<<22); return; } @@ -124,6 +152,7 @@ void system_init(void) void system_reboot(void) { /* use Watchdog to reset */ + SCU_CLKCFG &= ~(1<<31); WDTLR = 1; WDTCON = (1<<4) | (1<<3); -- 2.11.4.GIT