?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Fix advanced EQ menu
[maemo-rb.git] / firmware / export / rk27xx.h
blob58b3fe8166ee4343690b30faedfdaf8c5fd34c31
1 /* ARM part only for now */
2 #define AHB_SRAM 0x00000000
3
4 #define ARM_BUS0_BASE 0x18000000
5 #define ARM_BUS1_BASE 0x18400000
6
7 #define FLASH_BANK0 0x10000000
8 #define FLASH_BANK1 0x11000000
9
10 #define USB_NUM_ENDPOINTS 16
11 #define USB_DEVBSS_ATTR
12
13 /* Timers */
14 #define APB0_TIMER (ARM_BUS0_BASE + 0x00000000)
15 #define TMR0LR (*(volatile unsigned long *)(APB0_TIMER + 0x00))
16 #define TMR0CVR (*(volatile unsigned long *)(APB0_TIMER + 0x04))
17 #define TMR0CON (*(volatile unsigned long *)(APB0_TIMER + 0x08))
18
19 #define TMR1LR (*(volatile unsigned long *)(APB0_TIMER + 0x10))
20 #define TMR1CVR (*(volatile unsigned long *)(APB0_TIMER + 0x14))
21 #define TMR1CON (*(volatile unsigned long *)(APB0_TIMER + 0x18))
22
23 #define TMR2LR (*(volatile unsigned long *)(APB0_TIMER + 0x20))
24 #define TMR2CVR (*(volatile unsigned long *)(APB0_TIMER + 0x24))
25 #define TMR2CON (*(volatile unsigned long *)(APB0_TIMER + 0x28))
26
27 /* UART0 */
28 #define APB0_UART0 (ARM_BUS0_BASE + 0x00004000)
29 #define UART0_RBR (*(volatile unsigned long *)(APB0_UART0 + 0x00))
30 #define UART0_THR (*(volatile unsigned long *)(APB0_UART0 + 0x00))
31 #define UART0_DLL (*(volatile unsigned long *)(APB0_UART0 + 0x00))
32 #define UART0_DLH (*(volatile unsigned long *)(APB0_UART0 + 0x04))
33 #define UART0_IER (*(volatile unsigned long *)(APB0_UART0 + 0x04))
34 #define UART0_IIR (*(volatile unsigned long *)(APB0_UART0 + 0x08))
35 #define UART0_FCR (*(volatile unsigned long *)(APB0_UART0 + 0x08))
36 #define UART0_LCR (*(volatile unsigned long *)(APB0_UART0 + 0x0C))
37 #define UART0_MCR (*(volatile unsigned long *)(APB0_UART0 + 0x10))
38 #define UART0_LSR (*(volatile unsigned long *)(APB0_UART0 + 0x14))
39 #define UART0_MSR (*(volatile unsigned long *)(APB0_UART0 + 0x18))
40
41 /* UART1 */
42 #define APB0_UART1 (ARM_BUS0_BASE + 0x00008000)
43 #define UART1_RBR (*(volatile unsigned long *)(APB0_UART1 + 0x00))
44 #define UART1_THR (*(volatile unsigned long *)(APB0_UART1 + 0x00))
45 #define UART1_DLL (*(volatile unsigned long *)(APB0_UART1 + 0x00))
46 #define UART1_DLH (*(volatile unsigned long *)(APB0_UART1 + 0x04))
47 #define UART1_IER (*(volatile unsigned long *)(APB0_UART1 + 0x04))
48 #define UART1_IIR (*(volatile unsigned long *)(APB0_UART1 + 0x08))
49 #define UART1_FCR (*(volatile unsigned long *)(APB0_UART1 + 0x08))
50 #define UART1_LCR (*(volatile unsigned long *)(APB0_UART1 + 0x0C))
51 #define UART1_MCR (*(volatile unsigned long *)(APB0_UART1 + 0x10))
52 #define UART1_LSR (*(volatile unsigned long *)(APB0_UART1 + 0x14))
53 #define UART1_MSR (*(volatile unsigned long *)(APB0_UART1 + 0x18))
54
55 /* GPIO ports A,B,C,D */
56 #define APB0_GPIO0 (ARM_BUS0_BASE + 0x0000C000)
57 #define GPIO_PADR (*(volatile unsigned long *)(APB0_GPIO0 + 0x00))
58 #define GPIO_PACON (*(volatile unsigned long *)(APB0_GPIO0 + 0x04))
59 #define GPIO_PBDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x08))
60 #define GPIO_PBCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x0C))
61 #define GPIO_PCDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x10))
62 #define GPIO_PCCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x14))
63 #define GPIO_PDDR (*(volatile unsigned long *)(APB0_GPIO0 + 0x18))
64 #define GPIO_PDCON (*(volatile unsigned long *)(APB0_GPIO0 + 0x1C))
65 #define GPIO_TEST (*(volatile unsigned long *)(APB0_GPIO0 + 0x20))
66 #define GPIO_IEA (*(volatile unsigned long *)(APB0_GPIO0 + 0x24))
67 #define GPIO_IEB (*(volatile unsigned long *)(APB0_GPIO0 + 0x28))
68 #define GPIO_IEC (*(volatile unsigned long *)(APB0_GPIO0 + 0x2C))
69 #define GPIO_IED (*(volatile unsigned long *)(APB0_GPIO0 + 0x30))
70 #define GPIO_ISA (*(volatile unsigned long *)(APB0_GPIO0 + 0x34))
71 #define GPIO_ISB (*(volatile unsigned long *)(APB0_GPIO0 + 0x38))
72 #define GPIO_ISC (*(volatile unsigned long *)(APB0_GPIO0 + 0x3C))
73 #define GPIO_ISD (*(volatile unsigned long *)(APB0_GPIO0 + 0x40))
74 #define GPIO_IBEA (*(volatile unsigned long *)(APB0_GPIO0 + 0x44))
75 #define GPIO_IBEB (*(volatile unsigned long *)(APB0_GPIO0 + 0x48))
76 #define GPIO_IBEC (*(volatile unsigned long *)(APB0_GPIO0 + 0x4C))
77 #define GPIO_IBED (*(volatile unsigned long *)(APB0_GPIO0 + 0x50))
78 #define GPIO_IEVA (*(volatile unsigned long *)(APB0_GPIO0 + 0x54))
79 #define GPIO_IEVB (*(volatile unsigned long *)(APB0_GPIO0 + 0x58))
80 #define GPIO_IEVC (*(volatile unsigned long *)(APB0_GPIO0 + 0x5C))
81 #define GPIO_IEVD (*(volatile unsigned long *)(APB0_GPIO0 + 0x60))
82 #define GPIO_ICA (*(volatile unsigned long *)(APB0_GPIO0 + 0x64))
83 #define GPIO_ICB (*(volatile unsigned long *)(APB0_GPIO0 + 0x68))
84 #define GPIO_ICC (*(volatile unsigned long *)(APB0_GPIO0 + 0x6C))
85 #define GPIO_ICD (*(volatile unsigned long *)(APB0_GPIO0 + 0x70))
86 #define GPIO_ISR (*(volatile unsigned long *)(APB0_GPIO0 + 0x74))
87
88 /* Watchdog */
89 #define APB0_WDT (ARM_BUS0_BASE + 0x00010000)
90 #define WDTLR (*(volatile unsigned long *)(APB0_WDT + 0x00))
91 #define WDTCVR (*(volatile unsigned long *)(APB0_WDT + 0x04))
92 #define WDTCON (*(volatile unsigned long *)(APB0_WDT + 0x08))
93
94 /* RTC module documentation missing */
95 #define APB0_RTC (ARM_BUS0_BASE + 0x00014000)
96 #define RTC_TIME (*(volatile unsigned long *)(APB0_RTC + 0x00))
97 #define RTC_DATE (*(volatile unsigned long *)(APB0_RTC + 0x04))
98 #define RTC_TALARM (*(volatile unsigned long *)(APB0_RTC + 0x08))
99 #define RTC_DALARM (*(volatile unsigned long *)(APB0_RTC + 0x0C))
100 #define RTC_CTRL (*(volatile unsigned long *)(APB0_RTC + 0x10))
101 #define RTC_RESET (*(volatile unsigned long *)(APB0_RTC + 0x14))
102 #define RTC_PWOFF (*(volatile unsigned long *)(APB0_RTC + 0x18))
103 #define RTC_PWFAIL (*(volatile unsigned long *)(APB0_RTC + 0x1C))
104
105 /* SPI */
106 #define APB0_SPI (ARM_BUS0_BASE + 0x00018000)
107 #define SPI_TXR (*(volatile unsigned long *)(APB0_SPI + 0x00))
108 #define SPI_RXR (*(volatile unsigned long *)(APB0_SPI + 0x00))
109 #define SPI_IER (*(volatile unsigned long *)(APB0_SPI + 0x04))
110 #define SPI_FCR (*(volatile unsigned long *)(APB0_SPI + 0x08))
111 #define SPI_FWCR (*(volatile unsigned long *)(APB0_SPI + 0x0C))
112 #define SPI_DLYCR (*(volatile unsigned long *)(APB0_SPI + 0x10))
113 #define SPI_TXCR (*(volatile unsigned long *)(APB0_SPI + 0x14))
114 #define SPI_RXCR (*(volatile unsigned long *)(APB0_SPI + 0x18))
115 #define SPI_SSCR (*(volatile unsigned long *)(APB0_SPI + 0x1C))
116 #define SPI_ISR (*(volatile unsigned long *)(APB0_SPI + 0x20))
117
118 /* SCU module */
119 #define APB0_SCU (ARM_BUS0_BASE + 0x0001C000)
120 #define SCU_ID (*(volatile unsigned long *)(APB0_SCU + 0x00))
121 #define SCU_REMAP (*(volatile unsigned long *)(APB0_SCU + 0x04))
122 #define SCU_PLLCON1 (*(volatile unsigned long *)(APB0_SCU + 0x08))
123 #define SCU_PLLCON2 (*(volatile unsigned long *)(APB0_SCU + 0x0C))
124 #define SCU_PLLCON3 (*(volatile unsigned long *)(APB0_SCU + 0x10))
125 #define SCU_DIVCON1 (*(volatile unsigned long *)(APB0_SCU + 0x14))
126 #define SCU_CLKCFG (*(volatile unsigned long *)(APB0_SCU + 0x18))
127 #define CLKCFG_OTP (1<<0)
128 #define CLKCFG_DSP (1<<1)
129 #define CLKCFG_SDRAM (1<<2)
130 #define CLKCFG_HDMA (1<<3)
131 #define CLKCFG_DWDMA (1<<4)
132 #define CLKCFG_UHC (1<<5)
133 #define CLKCFG_UDC (1<<6)
134 /* 7 - 8 reserved */
135 #define CLKCFG_NAND (1<<9)
136 #define CLKCFG_A2A (1<<10)
137 #define CLKCFG_SRAM (1<<11)
138 #define CLKCFG_HCLK_LCDC (1<<12)
139 #define CLKCFG_LCDC (1<<13)
140 #define CLKCFG_HCLK_VIP (1<<14)
141 #define CLKCFG_VIP (1<<15)
142 #define CLKCFG_I2S (1<<16)
143 #define CLKCFG_PCLK_I2S (1<<17)
144 #define CLKCFG_UART0 (1<<18)
145 #define CLKCFG_UART1 (1<<19)
146 #define CLKCFG_I2C (1<<20)
147 #define CLKCFG_SPI (1<<21)
148 #define CLKCFG_SD (1<<22)
149 #define CLKCFG_PCLK_LSADC (1<<23)
150 #define CLKCFG_LSADC (1<<24)
151 #define CLKCFG_HCLK_HSADC (1<<25)
152 #define CLKCFG_HSADC (1<<26)
153 #define CLKCFG_GPIO (1<<27)
154 #define CLKCFG_TIMER (1<<28)
155 #define CLKCFG_PWM (1<<29)
156 #define CLKCFG_RTC (1<<30)
157 #define CLKCFG_WDT (1<<31)
158
159 #define SCU_RSTCFG (*(volatile unsigned long *)(APB0_SCU + 0x1C))
160 #define RSTCFG_UHC (1<<0)
161 #define RSTCFG_UDC (1<<1)
162 #define RSTCFG_LCDC (1<<2)
163 #define RSTCFG_VIP (1<<3)
164 #define RSTCFG_DSP_CORE (1<<4)
165 #define RSTCFG_DSP_PERI (1<<5)
166 #define RSTCFG_CODEC (1<<6)
167 #define RSTCFG_LSADC (1<<7)
168 #define RSTCFG_HSADC (1<<8)
169 #define RSTCFG_SD (1<<9)
170 #define RSTCFG_MAILBOX (1<<10)
171 #define RSTCFG_ECT (1<<11)
172 #define RSTCFG_ARM_CORE (1<<12)
173 /* 13 - 31 reserved */
174
175 #define SCU_PWM (*(volatile unsigned long *)(APB0_SCU + 0x20))
176 #define SCU_CPUPD (*(volatile unsigned long *)(APB0_SCU + 0x24))
177 #define SCU_CHIPCFG (*(volatile unsigned long *)(APB0_SCU + 0x28))
178 #define SCU_STATUS (*(volatile unsigned long *)(APB0_SCU + 0x2C))
179 #define SCU_IOMUXA_CON (*(volatile unsigned long *)(APB0_SCU + 0x30))
180 /* 20 - 31 reserved */
181 #define IOMUX_I2S_PAD (1<<19)
182 #define IOMUX_I2S_CODEC (0<<19)
183 #define IOMUX_I2C_PAD (1<<18)
184 #define IOMUX_I2C_CODEC (0<<18)
185 #define IOMUX_GPIO_B7 (2<<16)
186 #define IOMUX_NAND_CS3 (1<<16)
187 #define IOMUX_I2C_SDA (0<<16)
188 #define IOMUX_GPIO_B6 (2<<14)
189 #define IOMUX_NAND_CS2 (1<<14)
190 #define IOMUX_I2C_SCL (0<<14)
191 #define IOMUX_SPI (2<<12)
192 #define IOMUX_SD (1<<12)
193 #define IOMUX_GPIO_B05 (0<<12)
194 #define IOMUX_LCD_VSYNC (1<<11)
195 #define IOMUX_GPIO_A7 (0<<11)
196 #define IOMUX_LCD_DEN (1<<10)
197 #define IOMUX_GPIO_A6 (0<<10)
198 #define IOMUX_NAND_CS1 (1<<9)
199 #define IOMUX_GPIO_A5 (0<<9)
200 #define IOMUX_LCD_D22 (1<<8)
201 #define IOMUX_GPIO_A4 (0<<8)
202 #define IOMUX_UART0_NRTS (2<<6)
203 #define IOMUX_LCD_D20 (1<<6)
204 #define IOMUX_GPIO_A3 (0<<6)
205 #define IOMUX_UART0_NCTS (2<<4)
206 #define IOMUX_LCD_D18 (1<<4)
207 #define IOMUX_GPIO_A2 (0<<4)
208 #define IOMUX_UART0_TXD (2<<2)
209 #define IOMUX_LCD_D17 (1<<2)
210 #define IOMUX_GPIO_A1 (0<<2)
211 #define IOMUX_UART0_RXD (2<<0)
212 #define IOMUX_LCD_D16 (1<<0)
213 #define IOMUX_GPIO_A0 (0<<0)
214
215 #define SCU_IOMUXB_CON (*(volatile unsigned long *)(APB0_SCU + 0x34))
216 /* bits 31 - 23 reserved */
217 #define IOMUX_HADC (1<<22)
218 #define IOMUX_VIP (0<<22)
219 #define IOMUX_SDRAM_CKE (1<<21)
220 #define IOMUX_GPIO_D3 (0<<21)
221 #define IOMUX_UHC_VBUS (1<<20)
222 #define IOMUX_GPIO_F4 (0<<20)
223 #define IOMUX_UHC_OCUR (1<<19)
224 #define IOMUX_GPIO_F3 (0<<19)
225 #define IOMUX_GPIO_F2 (1<<18)
226 #define IOMUX_SDRAM_A12 (0<<18)
227 #define IOMUX_GPIO_F1 (1<<17)
228 #define IOMUX_SDRAM_A11 (0<<17)
229 #define IOMUX_VIP_CLK (1<<16)
230 #define IOMUX_GPIO_F0 (0<<16)
231 #define IOMUX_LCD_D815 (1<<15)
232 #define IOMUX_GPIO_E07 (0<<15)
233 #define IOMUX_PWM3 (1<<14)
234 #define IOMUX_GPIO_D7 (0<<14)
235 #define IOMUX_PWM2 (1<<13)
236 #define IOMUX_GPIO_D6 (0<<13)
237 #define IOMUX_PWM1 (1<<12)
238 #define IOMUX_GPIO_D5 (0<<12)
239 #define IOMUX_PWM0 (1<<11)
240 #define IOMUX_GPIO_D4 (0<<11)
241 #define IOMUX_SD_WPA (1<<10)
242 #define IOMUX_GPIO_D2 (0<<10)
243 #define IOMUX_UART1_RXD (2<<8)
244 #define IOMUX_SD_CDA (1<<8)
245 #define IOMUX_GPIO_D1 (0<<8)
246 #define IOMUX_UART1_TXD (2<<6)
247 #define IOMUX_SD_PCA (1<<6)
248 #define IOMUX_GPIO_D0 (0<<6)
249 #define IOMUX_STMEM_CS1 (1<<5)
250 #define IOMUX_GPIO_C7 (0<<5)
251 #define IOMUX_I2S_CLK (1<<4)
252 #define IOMUX_GPIO_C6 (0<<4)
253 #define IOMUX_I2S_SDO (1<<3)
254 #define IOMUX_GPIO_C5 (0<<3)
255 #define IOMUX_I2S_SDI (1<<2)
256 #define IOMUX_GPIO_C4 (0<<2)
257 #define IOMUX_I2S_LRCK (1<<1)
258 #define IOMUX_GPIO_C3 (0<<1)
259 #define IOMUX_I2S_SCLK (1<<0)
260 #define IOMUX_GPIO_C2 (0<<0)
261
262 #define SCU_GPIOUPCON (*(volatile unsigned long *)(APB0_SCU + 0x38))
263 #define SCU_DIVCON2 (*(volatile unsigned long *)(APB0_SCU + 0x3C))
264
265 /* I2C controller */
266 #define APB0_I2C (ARM_BUS0_BASE + 0x00020000)
267 #define I2C_MTXR (*(volatile unsigned long *)(APB0_I2C + 0x00))
268 #define I2C_MRXR (*(volatile unsigned long *)(APB0_I2C + 0x04))
269 #define I2C_STXR (*(volatile unsigned long *)(APB0_I2C + 0x08))
270 #define I2C_SRXR (*(volatile unsigned long *)(APB0_I2C + 0x0C))
271 #define I2C_SADDR (*(volatile unsigned long *)(APB0_I2C + 0x10))
272 #define I2C_IER (*(volatile unsigned long *)(APB0_I2C + 0x14))
273 #define I2C_ISR (*(volatile unsigned long *)(APB0_I2C + 0x18))
274 #define I2C_LCMR (*(volatile unsigned long *)(APB0_I2C + 0x1C))
275 #define I2C_LSR (*(volatile unsigned long *)(APB0_I2C + 0x20))
276 #define I2C_CONR (*(volatile unsigned long *)(APB0_I2C + 0x24))
277 #define I2C_OPR (*(volatile unsigned long *)(APB0_I2C + 0x28))
278
279 /* SD card controller */
280 #define APB0_SD (ARM_BUS0_BASE + 0x00024000)
281 #define MMU_CTRL (*(volatile unsigned long *)(APB0_SD + 0x00))
282 #define MMU_BIG_ENDIAN (1<<12)
283 #define MMU_DMA_START (1<<11)
284 #define MMU_DMA_WRITE (1<<10)
285 #define MMU_MMU0_BUFI (0<<9)
286 #define MMU_MMU0_BUFII (1<<9)
287 #define MMU_CPU_BUFI (0<<8)
288 #define MMU_CPU_BUFII (1<<8)
289 #define MMU_BUFII_RESET (1<<7)
290 #define MMU_BUFII_END (1<<6)
291 #define MMU_BUFII_BYTE (0<<4)
292 #define MMU_BUFII_HALFWORD (1<<4)
293 #define MMU_BUFII_WORD (3<<4)
294 #define MMU_BUFI_RESET (1<<3)
295 #define MMU_BUFI_END (1<<2)
296 #define MMU_BUFI_BYTE (0<<0)
297 #define MMU_BUFI_HALFWORD (1<<0)
298 #define MMU_BUFI_WORD (3<<0)
299
300 #define MMU_PNRI (*(volatile unsigned long *)(APB0_SD + 0x04))
301 #define CUR_PNRI (*(volatile unsigned long *)(APB0_SD + 0x08))
302 #define MMU_PNRII (*(volatile unsigned long *)(APB0_SD + 0x0C))
303 #define CUR_PNRII (*(volatile unsigned long *)(APB0_SD + 0x10))
304 #define MMU_ADDR (*(volatile unsigned long *)(APB0_SD + 0x14))
305 #define CUR_ADDR (*(volatile unsigned long *)(APB0_SD + 0x18))
306 #define MMU_DATA (*(volatile unsigned long *)(APB0_SD + 0x1C))
307
308 #define SD_CTRL (*(volatile unsigned long *)(APB0_SD + 0x20))
309 #define SD_PWR_CD (1<<13)
310 #define SD_PWR_CPU (0<<13)
311 #define SD_DETECT_CDDAT3 (1<<12)
312 #define SD_DETECT_MECH (0<<12)
313 #define SD_CLOCK_DIS (1<<11)
314 #define SD_CLOCK_EN (0<<11)
315 #define SD_DIV(x) ((x)&0x7ff)
316
317 #define SD_INT (*(volatile unsigned long *)(APB0_SD + 0x24))
318 #define CMD_RES_STAT (1<<6)
319 #define DATA_XFER_STAT (1<<5)
320 #define CD_DETECT_STAT (1<<4)
321 #define CMD_RES_INT_EN (1<<2)
322 #define DATA_XFER_INT_EN (1<<1)
323 #define CD_DETECT_IN_EN (1<<0)
324
325 #define SD_CARD (*(volatile unsigned long *)(APB0_SD + 0x28))
326 #define SD_CARD_SELECT (1<<7)
327 #define SD_CARD_PWR_EN (1<<6)
328 #define SD_CARD_DETECT_INT_EN (1<<5)
329 #define SD_CARD_BSY (1<<2)
330 #define SD_CARD_WRITE_PROTECT (1<<1)
331 #define SD_CARD_DETECT (1<<0)
332
333 #define SD_CMDREST (*(volatile unsigned long *)(APB0_SD + 0x30))
334 #define CMD_XFER_START (1<<13)
335 #define CMD_XFER_END (0<<13)
336 #define RES_XFER_START (1<<12)
337 #define RES_XFER_END (0<<12)
338 #define RES_R1 (0<<9)
339 #define RES_R1b (1<<9)
340 #define RES_R2 (2<<9)
341 #define RES_R3 (3<<9)
342 #define RES_R6 (6<<9)
343 #define CMD_RES_ERROR (1<<8)
344 /* bits 0-5 cmd index */
345
346 #define SD_CMDRES (*(volatile unsigned long *)(APB0_SD + 0x34))
347 #define STAT_CMD_XFER_START (1<<8)
348 #define STAT_RES_XFER_START (1<<7)
349 #define STAT_CMD_RES_ERR (1<<6)
350 #define STAT_CMD_RES_BUS_ERR (1<<5)
351 #define STAT_RES_TIMEOUT_ERR (1<<4)
352 #define STAT_RES_STARTBIT_ERR (1<<3)
353 #define STAT_RES_INDEX_ERR (1<<2)
354 #define STAT_RES_CRC_ERR (1<<1)
355 #define STAT_RES_ENDBIT_ERR (1<<0)
356
357 #define SD_DATAT (*(volatile unsigned long *)(APB0_SD + 0x3C))
358 #define DATA_XFER_START (1<<13)
359 #define DATA_XFER_WRITE (1<<12)
360 #define DATA_XFER_READ (0<<12)
361 #define DATA_BUS_4LINES (1<<11) /* rk2705/6/8 does not support this mode */
362 #define DATA_BUS_1LINE (0<<11)
363 #define DATA_XFER_DMA_EN (1<<10)
364 #define DATA_XFER_DMA_DIS (0<<10)
365 #define DATA_XFER_MULTI (1<<9)
366 #define DATA_XFER_SINGLE (0<<9)
367 #define DATA_XFER_ERR (1<<8)
368 #define DATA_BUS_ERR (1<<7)
369 #define DATA_TIMEOUT_ERR (1<<6)
370 #define DATA_CRC_ERR (1<<5)
371 #define READ_DAT_STARTBIT_ERR (1<<4)
372 #define READ_DAT_ENDBIT_ERR (1<<3)
373 #define WRITE_DAT_NOERR (2<<0)
374 #define WRITE_DAT_CRC_ERR (5<<0)
375 #define WRITE_DAT_NO_RES (7<<0)
376
377 #define SD_CMD (*(volatile unsigned long *)(APB0_SD + 0x40))
378 #define SD_RES3 (*(volatile unsigned long *)(APB0_SD + 0x44))
379 #define SD_RES2 (*(volatile unsigned long *)(APB0_SD + 0x48))
380 #define SD_RES1 (*(volatile unsigned long *)(APB0_SD + 0x4C))
381 #define SD_RES0 (*(volatile unsigned long *)(APB0_SD + 0x50))
382
383 /* I2S controller */
384 #define APB0_I2S (ARM_BUS0_BASE + 0x00028000)
385 #define I2S_OPR (*(volatile unsigned long *)(APB0_I2S + 0x00))
386 #define I2S_TXR (*(volatile unsigned long *)(APB0_I2S + 0x04))
387 #define I2S_RXR (*(volatile unsigned long *)(APB0_I2S + 0x08))
388 #define I2S_TXCTL (*(volatile unsigned long *)(APB0_I2S + 0x0C))
389 #define I2S_RXCTL (*(volatile unsigned long *)(APB0_I2S + 0x10))
390 #define I2S_FIFOSTS (*(volatile unsigned long *)(APB0_I2S + 0x14))
391 #define I2S_IER (*(volatile unsigned long *)(APB0_I2S + 0x18))
392 #define I2S_ISR (*(volatile unsigned long *)(APB0_I2S + 0x1C))
393
394 /* PWM timer */
395 #define APB0_PWM (ARM_BUS0_BASE + 0x0002C000)
396 #define PWMT0_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x00))
397 #define PWMT0_HRC (*(volatile unsigned long *)(APB0_PWM + 0x04))
398 #define PWMT0_LRC (*(volatile unsigned long *)(APB0_PWM + 0x08))
399 #define PWMT0_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x0C))
400 #define PWMT1_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x10))
401 #define PWMT1_HRC (*(volatile unsigned long *)(APB0_PWM + 0x14))
402 #define PWMT1_LRC (*(volatile unsigned long *)(APB0_PWM + 0x18))
403 #define PWMT1_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x1C))
404 #define PWMT2_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x20))
405 #define PWMT2_HRC (*(volatile unsigned long *)(APB0_PWM + 0x24))
406 #define PWMT2_LRC (*(volatile unsigned long *)(APB0_PWM + 0x28))
407 #define PWMT2_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x2C))
408 #define PWMT3_CNTR (*(volatile unsigned long *)(APB0_PWM + 0x30))
409 #define PWMT3_HRC (*(volatile unsigned long *)(APB0_PWM + 0x34))
410 #define PWMT3_LRC (*(volatile unsigned long *)(APB0_PWM + 0x38))
411 #define PWMT3_CTRL (*(volatile unsigned long *)(APB0_PWM + 0x3C))
412
413 /* ADC converter */
414 #define APB0_ADC0 (ARM_BUS0_BASE + 0x00030000)
415 #define ADC_DATA (*(volatile unsigned long *)(APB0_ADC0 + 0x00))
416 #define ADC_STAT (*(volatile unsigned long *)(APB0_ADC0 + 0x04))
417 #define ADC_CTRL (*(volatile unsigned long *)(APB0_ADC0 + 0x08))
418
419 /* 0x18034000 - 0x18038000 reserved */
420
421 /* GPIO ports E,F */
422 #define APB0_GPIO1 (ARM_BUS0_BASE + 0x00038000)
423 #define GPIO_PEDR (*(volatile unsigned long *)(APB0_GPIO1 + 0x00))
424 #define GPIO_PECON (*(volatile unsigned long *)(APB0_GPIO1 + 0x04))
425 #define GPIO_PFDR (*(volatile unsigned long *)(APB0_GPIO1 + 0x08))
426 #define GPIO_PFCON (*(volatile unsigned long *)(APB0_GPIO1 + 0x0C))
427
428 #define GPIO1_TEST (*(volatile unsigned long *)(APB0_GPIO1 + 0x20))
429 #define GPIO_IEE (*(volatile unsigned long *)(APB0_GPIO1 + 0x24))
430 #define GPIO_IEF (*(volatile unsigned long *)(APB0_GPIO1 + 0x28))
431
432 #define GPIO_ISE (*(volatile unsigned long *)(APB0_GPIO1 + 0x34))
433 #define GPIO_ISF (*(volatile unsigned long *)(APB0_GPIO1 + 0x38))
434
435 #define GPIO_IBEE (*(volatile unsigned long *)(APB0_GPIO1 + 0x44))
436 #define GPIO_IBEF (*(volatile unsigned long *)(APB0_GPIO1 + 0x48))
437
438 #define GPIO_IEVE (*(volatile unsigned long *)(APB0_GPIO1 + 0x54))
439 #define GPIO_IEVF (*(volatile unsigned long *)(APB0_GPIO1 + 0x58))
440
441 #define GPIO_ICE (*(volatile unsigned long *)(APB0_GPIO1 + 0x64))
442 #define GPIO_ICF (*(volatile unsigned long *)(APB0_GPIO1 + 0x68))
443
444 #define GPIO1_ISR (*(volatile unsigned long *)(APB0_GPIO1 + 0x74))
445
446
447 /* 0x1803C000 - 0x18080000 reserved */
448
449 /* Interrupt controller */
450 #define AHB0_INTC (ARM_BUS0_BASE + 0x00080000)
451 #define INTC_SCR0 (*(volatile unsigned long *)(AHB0_INTC + 0x00))
452 #define INTC_SCR1 (*(volatile unsigned long *)(AHB0_INTC + 0x04))
453 #define INTC_SCR2 (*(volatile unsigned long *)(AHB0_INTC + 0x08))
454 #define INTC_SCR3 (*(volatile unsigned long *)(AHB0_INTC + 0x0C))
455 #define INTC_SCR4 (*(volatile unsigned long *)(AHB0_INTC + 0x10))
456 #define INTC_SCR5 (*(volatile unsigned long *)(AHB0_INTC + 0x14))
457 #define INTC_SCR6 (*(volatile unsigned long *)(AHB0_INTC + 0x18))
458 #define INTC_SCR7 (*(volatile unsigned long *)(AHB0_INTC + 0x1C))
459 #define INTC_SCR8 (*(volatile unsigned long *)(AHB0_INTC + 0x20))
460 #define INTC_SCR9 (*(volatile unsigned long *)(AHB0_INTC + 0x24))
461 #define INTC_SCR10 (*(volatile unsigned long *)(AHB0_INTC + 0x28))
462 #define INTC_SCR11 (*(volatile unsigned long *)(AHB0_INTC + 0x2C))
463 #define INTC_SCR12 (*(volatile unsigned long *)(AHB0_INTC + 0x30))
464 #define INTC_SCR13 (*(volatile unsigned long *)(AHB0_INTC + 0x34))
465 #define INTC_SCR14 (*(volatile unsigned long *)(AHB0_INTC + 0x38))
466 #define INTC_SCR15 (*(volatile unsigned long *)(AHB0_INTC + 0x3C))
467 #define INTC_SCR16 (*(volatile unsigned long *)(AHB0_INTC + 0x40))
468 #define INTC_SCR17 (*(volatile unsigned long *)(AHB0_INTC + 0x44))
469 #define INTC_SCR18 (*(volatile unsigned long *)(AHB0_INTC + 0x48))
470 #define INTC_SCR19 (*(volatile unsigned long *)(AHB0_INTC + 0x4C))
471 #define INTC_SCR20 (*(volatile unsigned long *)(AHB0_INTC + 0x50))
472 #define INTC_SCR21 (*(volatile unsigned long *)(AHB0_INTC + 0x54))
473 #define INTC_SCR22 (*(volatile unsigned long *)(AHB0_INTC + 0x58))
474 #define INTC_SCR23 (*(volatile unsigned long *)(AHB0_INTC + 0x5C))
475 #define INTC_SCR24 (*(volatile unsigned long *)(AHB0_INTC + 0x60))
476 #define INTC_SCR25 (*(volatile unsigned long *)(AHB0_INTC + 0x64))
477 #define INTC_SCR26 (*(volatile unsigned long *)(AHB0_INTC + 0x68))
478 #define INTC_SCR27 (*(volatile unsigned long *)(AHB0_INTC + 0x6C))
479 #define INTC_SCR28 (*(volatile unsigned long *)(AHB0_INTC + 0x70))
480 #define INTC_SCR29 (*(volatile unsigned long *)(AHB0_INTC + 0x74))
481 #define INTC_SCR30 (*(volatile unsigned long *)(AHB0_INTC + 0x78))
482 #define INTC_SCR31 (*(volatile unsigned long *)(AHB0_INTC + 0x7C))
483
484 #define INTC_ISR (*(volatile unsigned long *)(AHB0_INTC + 0x104))
485 #define INTC_IPR (*(volatile unsigned long *)(AHB0_INTC + 0x108))
486 #define INTC_IMR (*(volatile unsigned long *)(AHB0_INTC + 0x10C))
487
488 #define INTC_IECR (*(volatile unsigned long *)(AHB0_INTC + 0x114))
489 #define INTC_ICCR (*(volatile unsigned long *)(AHB0_INTC + 0x118))
490 #define INTC_ISCR (*(volatile unsigned long *)(AHB0_INTC + 0x11C))
491
492 #define IRQ_ARM_UART0 (1<<0)
493 #define IRQ_ARM_UART1 (1<<1)
494 #define IRQ_ARM_TIMER0 (1<<2)
495 #define IRQ_ARM_TIMER1 (1<<3)
496 #define IRQ_ARM_TIMER2 (1<<4)
497 #define IRQ_ARM_GPIO0 (1<<5)
498 #define IRQ_ARM_SW (1<<6)
499 #define IRQ_ARM_MAILBOX (1<<7)
500 #define IRQ_ARM_RTC (1<<8)
501 #define IRQ_ARM_SCU (1<<9)
502 #define IRQ_ARM_SD (1<<10)
503 #define IRQ_ARM_SPI (1<<11)
504 #define IRQ_ARM_HDMA (1<<12)
505 #define IRQ_ARM_A2A (1<<13)
506 #define IRQ_ARM_I2C (1<<14)
507 #define IRQ_ARM_I2S (1<<15)
508 #define IRQ_ARM_UDC (1<<16)
509 #define IRQ_ARM_UHC (1<<17)
510 #define IRQ_ARM_PWM0 (1<<18)
511 #define IRQ_ARM_PWM1 (1<<19)
512 #define IRQ_ARM_PWM2 (1<<20)
513 #define IRQ_ARM_PWM3 (1<<21)
514 #define IRQ_ARM_ADC (1<<22)
515 #define IRQ_ARM_GPIO1 (1<<23)
516 #define IRQ_ARM_VIP (1<<24)
517 #define IRQ_ARM_DWDMA (1<<25)
518 #define IRQ_ARM_NANDC (1<<26)
519 #define IRQ_ARM_LCDC (1<<27)
520 #define IRQ_ARM_DSP (1<<28)
521 #define IRQ_ARM_SW1 (1<<29)
522 #define IRQ_ARM_SW2 (1<<30)
523 #define IRQ_ARM_SW3 (1<<31)
524
525 #define INTC_TEST (*(volatile unsigned long *)(AHB0_INTC + 0x124))
526
527 /* Bus arbiter module */
528 #define AHB0_ARBITER (ARM_BUS0_BASE + 0x00084000)
529 #define ARB_MODE (*(volatile unsigned long *)(AHB0_ARBITER + 0x00))
530 #define ARB_PRIO1 (*(volatile unsigned long *)(AHB0_ARBITER + 0x04))
531 #define ARB_PRIO2 (*(volatile unsigned long *)(AHB0_ARBITER + 0x08))
532 #define ARB_PRIO3 (*(volatile unsigned long *)(AHB0_ARBITER + 0x0C))
533 #define ARB_PRIO4 (*(volatile unsigned long *)(AHB0_ARBITER + 0x10))
534 #define ARB_PRIO5 (*(volatile unsigned long *)(AHB0_ARBITER + 0x14))
535 #define ARB_PRIO6 (*(volatile unsigned long *)(AHB0_ARBITER + 0x18))
536 #define ARB_PRIO7 (*(volatile unsigned long *)(AHB0_ARBITER + 0x1C))
537 #define ARB_PRIO8 (*(volatile unsigned long *)(AHB0_ARBITER + 0x20))
538 #define ARB_PRIO9 (*(volatile unsigned long *)(AHB0_ARBITER + 0x24))
539 #define ARB_PRIO10 (*(volatile unsigned long *)(AHB0_ARBITER + 0x28))
540 #define ARB_PRIO11 (*(volatile unsigned long *)(AHB0_ARBITER + 0x2C))
541 #define ARB_PRIO12 (*(volatile unsigned long *)(AHB0_ARBITER + 0x30))
542 #define ARB_PRIO13 (*(volatile unsigned long *)(AHB0_ARBITER + 0x34))
543 #define ARB_PRIO14 (*(volatile unsigned long *)(AHB0_ARBITER + 0x38))
544 #define ARB_PRIO15 (*(volatile unsigned long *)(AHB0_ARBITER + 0x3C))
545
546 /* Interprocessor communication module */
547 #define AHB0_CPU_MAILBOX (ARM_BUS0_BASE + 0x00088000)
548 #define MAILBOX_ID (*(volatile unsigned long *)(AHB0_CPU_MAILBOX + 0x00))
549 #define H2C_STA (*(volatile unsigned long *)(AHB0_CPU_MAILBOX + 0x10))
550 #define H2C0_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x20))
551 #define H2C0_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x24))
552 #define H2C1_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x28))
553 #define H2C1_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x2C))
554 #define H2C2_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x30))
555 #define H2C2_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x24))
556 #define H2C3_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x38))
557 #define H2C3_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x3C))
558
559 #define C2H_STA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x40))
560 #define C2H0_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x50))
561 #define C2H0_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x54))
562 #define C2H1_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x58))
563 #define C2H1_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x5C))
564 #define C2H2_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x60))
565 #define C2H2_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x64))
566 #define C2H3_DATA (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x68))
567 #define C2H3_CMD (*(volatile unsigned long *)(AHB0_CPU_MAILBOC + 0x6C))
568
569 /* Debug module */
570 #define AHB0_CPU_DEBUGIF (ARM_BUS0_BASE + 0x0008C000)
571
572 /* AHB DMA */
573 #define AHB0_HDMA (ARM_BUS0_BASE + 0x00090000)
574 #define HDMA_CON0 (*(volatile unsigned long *)(AHB0_HDMA + 0x00))
575 #define HDMA_CON1 (*(volatile unsigned long *)(AHB0_HDMA + 0x04))
576 #define HDMA_ISRC0 (*(volatile unsigned long *)(AHB0_HDMA + 0x08))
577 #define HDMA_IDST0 (*(volatile unsigned long *)(AHB0_HDMA + 0x0C))
578 #define HDMA_ICNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x10))
579 #define HDMA_ISRC1 (*(volatile unsigned long *)(AHB0_HDMA + 0x14))
580 #define HDMA_IDST1 (*(volatile unsigned long *)(AHB0_HDMA + 0x18))
581 #define HDMA_ICNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x1C))
582 #define HDMA_CSRC0 (*(volatile unsigned long *)(AHB0_HDMA + 0x20))
583 #define HDMA_CDST0 (*(volatile unsigned long *)(AHB0_HDMA + 0x24))
584 #define HDMA_CCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x28))
585 #define HDMA_CSRC1 (*(volatile unsigned long *)(AHB0_HDMA + 0x2C))
586 #define HDMA_CDST1 (*(volatile unsigned long *)(AHB0_HDMA + 0x30))
587 #define HDMA_CCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x34))
588 #define HDMA_ISR (*(volatile unsigned long *)(AHB0_HDMA + 0x38))
589 #define HDMA_DSR (*(volatile unsigned long *)(AHB0_HDMA + 0x3C))
590 #define HDMA_ISCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x40))
591 #define HDMA_IPNCNTD0 (*(volatile unsigned long *)(AHB0_HDMA + 0x44))
592 #define HDMA_IADDR_BS0 (*(volatile unsigned long *)(AHB0_HDMA + 0x48))
593 #define HDMA_ISCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x4C))
594 #define HDMA_IPNCNTD1 (*(volatile unsigned long *)(AHB0_HDMA + 0x50))
595 #define HDMA_IADDR_BS1 (*(volatile unsigned long *)(AHB0_HDMA + 0x54))
596 #define HDMA_CSCNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x58))
597 #define HDMA_CPNCNTD0 (*(volatile unsigned long *)(AHB0_HDMA + 0x5C))
598 #define HDMA_CADDR_BS0 (*(volatile unsigned long *)(AHB0_HDMA + 0x60))
599 #define HDMA_CSCNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x64))
600 #define HDMA_CPNCNTD1 (*(volatile unsigned long *)(AHB0_HDMA + 0x68))
601 #define HDMA_CADDR_BS1 (*(volatile unsigned long *)(AHB0_HDMA + 0x6C))
602 #define HDMA_PACNT0 (*(volatile unsigned long *)(AHB0_HDMA + 0x70))
603 #define HDMA_PACNT1 (*(volatile unsigned long *)(AHB0_HDMA + 0x74))
604
605 /* AHB-to-AHB bridge controller */
606 #define AHB0_A2A_DMA (ARM_BUS0_BASE + 0x00094000)
607 #define A2A_CON0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x00))
608 #define A2A_ISRC0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x04))
609 #define A2A_IDST0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x08))
610 #define A2A_ICNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x0C))
611 #define A2A_CSRC0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x10))
612 #define A2A_CDST0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x14))
613 #define A2A_CCNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x18))
614 #define A2A_CON1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x1C))
615 #define A2A_ISRC1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x20))
616 #define A2A_IDST1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x24))
617 #define A2A_ICNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x28))
618 #define A2A_CSRC1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x2C))
619 #define A2A_CDST1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x30))
620 #define A2A_CCNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x34))
621 #define A2A_INT_STS (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x38))
622 #define A2A_DMA_STS (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x3C))
623 #define A2A_ERR_ADR0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x40))
624 #define A2A_ERR_OP0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x44))
625 #define A2A_ERR_ADR1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x48))
626 #define A2A_ERR_OP1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x4C))
627 #define A2A_LCNT0 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x50))
628 #define A2A_LCNT1 (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x54))
629 #define A2A_DOMAIN (*(volatile unsigned long *)(AHB0_A2A_DMA + 0x58))
630
631 /* 0x18098000 - 0x180A000 reserved */
632
633 /* USB device controller */
634 #define AHB0_UDC (ARM_BUS0_BASE + 0x000A0000)
635 #define PHY_TEST_EN (*(volatile unsigned long *)(AHB0_UDC + 0x00))
636 #define PHY_TEST (*(volatile unsigned long *)(AHB0_UDC + 0x04))
637 #define DEV_CTL (*(volatile unsigned long *)(AHB0_UDC + 0x08))
638 #define DEV_RMTWKP (1<<2)
639 #define DEV_SELF_PWR (1<<3)
640 #define DEV_SOFT_CN (1<<4)
641 #define DEV_RESUME (1<<5)
642 #define DEV_PHY16BIT (1<<6)
643 #define SOFT_POR (1<<7)
644 #define CSR_DONE (1<<8)
645
646 #define DEV_INFO (*(volatile unsigned long *)(AHB0_UDC + 0x10))
647 #define DEV_EN (1<<7)
648 #define VBUS_STS (1<<20)
649 #define DEV_SPEED (3<<21)
650
651 #define EN_INT (*(volatile unsigned long *)(AHB0_UDC + 0x14))
652 #define EN_SOF_INTR (1<<0)
653 #define EN_SETUP_INTR (1<<1)
654 #define EN_IN0_INTR (1<<2)
655 #define EN_OUT0_INTR (1<<3)
656 #define EN_USBRST_INTR (1<<4)
657 #define EN_RESUME_INTR (1<<5)
658 #define EN_SUSP_INTR (1<<6)
659 /* bit 7 reserved */
660 #define EN_BOUT1_INTR (1<<8)
661 #define EN_BIN2_INTR (1<<9)
662 #define EN_IIN3_INTR (1<<10)
663 #define EN_BOUT4_INTR (1<<11)
664 #define EN_BIN5_INTR (1<<12)
665 #define EN_IIN6_INTR (1<<13)
666 #define EN_BOUT7_INTR (1<<14)
667 #define EN_BIN8_INTR (1<<15)
668 #define EN_IIN9_INTR (1<<16)
669 #define EN_BOUT10_INTR (1<<17)
670 #define EN_BIN11_INTR (1<<18)
671 #define EN_IIN12_INTR (1<<19)
672 #define EN_BOUT13_INTR (1<<20)
673 #define EN_BIN14_INTR (1<<21)
674 #define EN_IIN15_INTR (1<<22)
675 /* bits 23-26 TEST */
676 /* bits 27-31 reserved */
677
678 #define INT2FLAG (*(volatile unsigned long *)(AHB0_UDC + 0x18))
679 #define SOF_INTR (1<<0)
680 #define SETUP_INTR (1<<1)
681 #define IN0_INTR (1<<2)
682 #define OUT0_INTR (1<<3)
683 #define USBRST_INTR (1<<4)
684 #define RESUME_INTR (1<<5)
685 #define SUSP_INTR (1<<6)
686 #define CONN_INTR (1<<7) /* marked as reserved in DS */
687 #define BOUT1_INTR (1<<8)
688 #define BIN2_INTR (1<<9)
689 #define IIN3_INTR (1<<10)
690 #define BOUT4_INTR (1<<11)
691 #define BIN5_INTR (1<<12)
692 #define IIN6_INTR (1<<13)
693 #define BOUT7_INTR (1<<14)
694 #define BIN8_INTR (1<<15)
695 #define IIN9_INTR (1<<16)
696 #define BOUT10_INTR (1<<17)
697 #define BIN11_INTR (1<<18)
698 #define IIN12_INTR (1<<19)
699 #define BOUT13_INTR (1<<20)
700 #define BIN14_INTR (1<<21)
701 #define IIN15_INTR (1<<22)
702 /* bits 23-26 TEST */
703 /* bits 27-31 reserved */
704
705 #define INTCON (*(volatile unsigned long *)(AHB0_UDC + 0x1C))
706 #define UDC_INTEN (1<<0)
707 #define UDC_INTEDGE_TRIG (1<<1)
708 #define UDC_INTHIGH_ACT (1<<2)
709
710 #define SETUP1 (*(volatile unsigned long *)(AHB0_UDC + 0x20))
711 #define SETUP2 (*(volatile unsigned long *)(AHB0_UDC + 0x24))
712 #define AHBCON (*(volatile unsigned long *)(AHB0_UDC + 0x28))
713 #define RX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x30))
714 #define RX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x34))
715 #define RX0DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x38))
716 #define RX0DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x3C))
717 #define TX0STAT (*(volatile unsigned long *)(AHB0_UDC + 0x40))
718 #define TX0CON (*(volatile unsigned long *)(AHB0_UDC + 0x44))
719 #define TX0BUF (*(volatile unsigned long *)(AHB0_UDC + 0x48))
720 #define TX0DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x4C))
721 #define TX0DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x50))
722 #define RX1STAT (*(volatile unsigned long *)(AHB0_UDC + 0x54))
723 #define RX1CON (*(volatile unsigned long *)(AHB0_UDC + 0x58))
724 #define RX1DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x5C))
725 #define RX1DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x60))
726 #define TX2STAT (*(volatile unsigned long *)(AHB0_UDC + 0x64))
727 #define TX2CON (*(volatile unsigned long *)(AHB0_UDC + 0x68))
728 #define TX2BUF (*(volatile unsigned long *)(AHB0_UDC + 0x6C))
729 #define TX2DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x70))
730 #define TX2DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x74))
731 #define TX3STAT (*(volatile unsigned long *)(AHB0_UDC + 0x78))
732 #define TX3CON (*(volatile unsigned long *)(AHB0_UDC + 0x7C))
733 #define TX3BUF (*(volatile unsigned long *)(AHB0_UDC + 0x80))
734 #define TX3DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x84))
735 #define TX3DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x88))
736 #define RX4STAT (*(volatile unsigned long *)(AHB0_UDC + 0x8C))
737 #define RX4CON (*(volatile unsigned long *)(AHB0_UDC + 0x90))
738 #define RX4DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x94))
739 #define RX4DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x98))
740 #define TX5STAT (*(volatile unsigned long *)(AHB0_UDC + 0x9C))
741 #define TX5CON (*(volatile unsigned long *)(AHB0_UDC + 0xA0))
742 #define TX5BUF (*(volatile unsigned long *)(AHB0_UDC + 0xA4))
743 #define TX5DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xA8))
744 #define TX5DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xAC))
745 #define TX6STAT (*(volatile unsigned long *)(AHB0_UDC + 0xB0))
746 #define TX6CON (*(volatile unsigned long *)(AHB0_UDC + 0xB4))
747 #define TX6BUF (*(volatile unsigned long *)(AHB0_UDC + 0xB8))
748 #define TX6DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xBC))
749 #define TX6DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xC0))
750 #define RX7STAT (*(volatile unsigned long *)(AHB0_UDC + 0xC4))
751 #define RX7CON (*(volatile unsigned long *)(AHB0_UDC + 0xC8))
752 #define RX7DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0xCC))
753 #define RX7DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0xD0))
754 #define TX8STAT (*(volatile unsigned long *)(AHB0_UDC + 0xD4))
755 #define TX8CON (*(volatile unsigned long *)(AHB0_UDC + 0xD8))
756 #define TX8BUF (*(volatile unsigned long *)(AHB0_UDC + 0xDC))
757 #define TX8DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xE0))
758 #define TX8DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xE4))
759 #define TX9STAT (*(volatile unsigned long *)(AHB0_UDC + 0xE8))
760 #define TX9CON (*(volatile unsigned long *)(AHB0_UDC + 0xEC))
761 #define TX9BUF (*(volatile unsigned long *)(AHB0_UDC + 0xF0))
762 #define TX9DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0xF4))
763 #define TX9DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0xF8))
764 #define RX10STAT (*(volatile unsigned long *)(AHB0_UDC + 0xFC))
765 #define RX10CON (*(volatile unsigned long *)(AHB0_UDC + 0x100))
766 #define RX10DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x104))
767 #define RX10DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x108))
768 #define TX11STAT (*(volatile unsigned long *)(AHB0_UDC + 0x10C))
769 #define TX11CON (*(volatile unsigned long *)(AHB0_UDC + 0x110))
770 #define TX11BUF (*(volatile unsigned long *)(AHB0_UDC + 0x114))
771 #define TX11DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x118))
772 #define TX11DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x11C))
773 #define TX12STAT (*(volatile unsigned long *)(AHB0_UDC + 0x120))
774 #define TX12CON (*(volatile unsigned long *)(AHB0_UDC + 0x124))
775 #define TX12BUF (*(volatile unsigned long *)(AHB0_UDC + 0x128))
776 #define TX12DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x12C))
777 #define TX12DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x130))
778 #define RX13STAT (*(volatile unsigned long *)(AHB0_UDC + 0x134))
779 #define RX13CON (*(volatile unsigned long *)(AHB0_UDC + 0x138))
780 #define RX13DMACTLO (*(volatile unsigned long *)(AHB0_UDC + 0x13C))
781 #define RX13DMAOUTLMADDR (*(volatile unsigned long *)(AHB0_UDC + 0x140))
782 #define TX14STAT (*(volatile unsigned long *)(AHB0_UDC + 0x144))
783 #define TX14CON (*(volatile unsigned long *)(AHB0_UDC + 0x148))
784 #define TX14BUF (*(volatile unsigned long *)(AHB0_UDC + 0x14C))
785 #define TX14DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x150))
786 #define TX14DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x154))
787 #define TX15STAT (*(volatile unsigned long *)(AHB0_UDC + 0x158))
788 #define TX15CON (*(volatile unsigned long *)(AHB0_UDC + 0x15C))
789 #define TX15BUF (*(volatile unsigned long *)(AHB0_UDC + 0x160))
790 #define TX15DMAINCTL (*(volatile unsigned long *)(AHB0_UDC + 0x164))
791 #define TX15DMALM_IADDR (*(volatile unsigned long *)(AHB0_UDC + 0x168))
792
793 /* RXnSTAT bits */
794 /* bits 10:0 RXLEN */
795 /* bits 15:11 reserved */
796 #define RXVOID (1<<16)
797 #define RXERR (1<<17)
798 #define RXACK (1<<18)
799 #define RXCFINT (1<<19) /* reserved for EP0 */
800 /* bits 23:20 reserved */
801 #define RXFULL (1<<24)
802 #define RXOVF (1<<25)
803 /* bits 31:26 reserved */
804
805 /* RXnCON bits */
806 #define RXFFRC (1<<0)
807 #define RXCLR (1<<1)
808 #define RXSTALL (1<<2)
809 #define RXNAK (1<<3)
810 #define RXEPEN (1<<4)
811 #define RXVOIDINTEN (1<<5)
812 #define RXERRINTEN (1<<6)
813 #define RXACKINTEN (1<<7)
814 /* bits 31:8 reserved for EP0 */
815 /* bits 31:14 reserved for others */
816
817 /* TxnSTAT */
818 /* bits 10:0 TXLEN */
819 /* bits 15:11 reserved */
820 #define TXVOID (1<<16)
821 #define TXERR (1<<17)
822 #define TXACK (1<<18)
823 #define TXDMADN (1<<19) /* reserved for EP0 */
824 #define TXCFINT (1<<20) /* reserved for EP0 */
825 /* bits 31:21 reserved */
826
827 /* TXnCON bits */
828 #define TXCLR (1<<0)
829 #define TXSTALL (1<<1)
830 #define TXNAK (1<<2)
831 #define TXEPEN (1<<3) /* reserved for EP0 */
832 #define TXVOIDINTEN (1<<4)
833 #define TXERRINTEN (1<<5)
834 #define TXACKINTEN (1<<6)
835 #define TXDMADNEN (1<<7) /* reserved for EP0 */
836 /* bits 31:8 reserved */
837
838 /* TXnBUF bits */
839 #define TXFULL (1<<0)
840 #define TXURF (1<<1)
841 #define TXDS0 (1<<2) /* reserved for EP0 */
842 #define TXDS1 (1<<3) /* reserved for EP0 */
843 /* bits 31:4 reserved */
844
845 /* DMA bits */
846 #define DMA_START (1<<0)
847 /* bits 31:1 reserved */
848
849 /* USB host controller */
850 #define AHB0_UHC (ARM_BUS0_BASE + 0x000A4000)
851 /* documentation missing */
852
853 /* 0x180A8000 - 0x180B0000 reserved */
854
855 /* Static/SDRAM memory controller */
856 #define AHB0_SDRSTMC (ARM_BUS0_BASE + 0x000B0000)
857 #define MCSDR_MODE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x100))
858 #define MCSDR_ADDMAP (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x104))
859 #define MCSDR_ADDCFG (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x108))
860 #define MCSDR_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x10C))
861 #define MCSDR_T_REF (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x110))
862 #define MCSDR_T_RFC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x114))
863 #define MCSDR_T_MRD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x118))
864 #define MCSDR_T_RP (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x120))
865 #define MCSDR_T_RCD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x124))
866
867 #define MCST0_T_CEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x200))
868 #define MCST0_T_CE2WE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x204))
869 #define MCST0_WEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x208))
870 #define MCST0_T_WE2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x20C))
871 #define MCST0_T_CEWDR (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x210))
872 #define MCST0_T_CE2RD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x214))
873 #define MCST0_T_RDWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x218))
874 #define MCST0_T_RD2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x21C))
875 #define MCST0_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x220))
876
877 #define MCST1_T_CEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x300))
878 #define MCST1_T_CE2WE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x304))
879 #define MCST1_WEWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x308))
880 #define MCST1_T_WE2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x30C))
881 #define MCST1_T_CEWDR (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x310))
882 #define MCST1_T_CE2RD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x314))
883 #define MCST1_T_RDWD (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x318))
884 #define MCST1_T_RD2CE (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x31C))
885 #define MCST1_BASIC (*(volatile unsigned long *)(AHB0_SDRSTMC + 0x320))
886
887 /* 0x180B4000 - 0x180C000 reserved */
888
889 /* VIP - video input processor */
890 #define AHB0_VIP (ARM_BUS0_BASE + 0x000C0000)
891
892 /* 0x180C4000 - 0x180E8000 reserved */
893
894 /* NAND flash controller */
895 #define AHB0_NANDC (ARM_BUS0_BASE + 0x000E8000)
896
897 #define FMCTL (*(volatile unsigned long *)(AHB0_NANDC))
898 #define FM_RDY (1<<5) /* status of line R/B# */
899 #define FM_PROTECT (1<<4) /* WP# line (active low) */
900 /* bits 0-3 are chip selects */
901
902 #define FMWAIT (*(volatile unsigned long *)(AHB0_NANDC + 0x04))
903 #define FLCTL (*(volatile unsigned long *)(AHB0_NANDC + 0x08))
904 #define FL_RDY (1<<12)
905 #define FL_COR_EN (1<<11)
906 #define FL_INT_EN (1<<10)
907 #define FL_XFER_EN (1<<9)
908 #define FL_INTCLR_EN (1<<8)
909 /* bits 3-7 unknown */
910 #define FL_START (1<<2)
911 #define FL_WR (1<<1)
912 #define FL_RST (1<<0)
913
914 #define BCHCTL (*(volatile unsigned long *)(AHB0_NANDC + 0x0C))
915 /* bit 13 is used but unknown */
916 /* bit 12 is used but unknown */
917 #define BCH_WR (1<<1)
918 #define BCH_RST (1<<0)
919
920 #define BCHST (*(volatile unsigned long *)(AHB0_NANDC + 0xD0))
921 /* bit 2 ERR ?? */
922 /* bit 0 ?? */
923
924 #define FLASH_DATA(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x200 + (n<<9)))
925 #define FLASH_ADDR(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x204 + (n<<9)))
926 #define FLASH_CMD(n) (*(volatile unsigned char *)(AHB0_NANDC + 0x208 + (n<<9)))
927
928 #define PAGE_BUF (*(volatile unsigned char *)(AHB0_NANDC + 0xA00))
929 #define SPARE_BUF (*(volatile unsigned char *)(AHB0_NANDC + 0x1200))
930
931 #define AHB0_ROM (ARM_BUS0_BASE + 0x000EC000)
932 #define AHB0_ES3 (ARM_BUS0_BASE + 0x000F4000)
933 #define AHB0_ES4 (ARM_BUS0_BASE + 0x000F8000)
934 #define AHB0_ES5 (ARM_BUS0_BASE + 0x000FC000)
935 #define AHB0_ES6 (ARM_BUS0_BASE + 0x00100000)
936 #define AHB0_EMD_SRAM (ARM_BUS0_BASE + 0x00200000)
937
938 /* 0x18204000 - 0x1840000 reserved */
939
940 /* 0x18400000 - 0x18484000 reserved*/
941
942 #define AHB1_ARBITER 0x18484000
943 /* 0x18488000 - 0x186E8000 reserved*/
944
945 /* LCD controller */
946 #define AHB1_LCDC 0x186E8000
947 #define LCDC_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x00))
948 /* bits 14-31 reserved */
949 #define ALPHA24B (1<<13)
950 #define UVBUFEXCH (1<<12)
951 #define ALPHA(x) (((x)&0x07)<<9)
952 #define Y_MIX (1<<8)
953 #define LCDC_MCU (1<<7)
954 #define RGB24B (1<<6)
955 #define START_EVEN (1<<5)
956 #define EVEN_EN (1<<4)
957 #define RGB_DUMMY(x) (((x)&0x03)<<2)
958 #define LCDC_EN (1<<1)
959 #define LCDC_STOP (1<<0)
960 #define MCU_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x04))
961
962 #define ALPHA_BASE(x) (((x)&0x3f)<<8)
963 #define MCU_CTRL_FIFO_EN (1<<6)
964 #define MCU_CTRL_RS_HIGH (1<<5)
965 #define MCU_CTRL_BUFF_WRITE (1<<2)
966 #define MCU_CTRL_BUFF_START (1<<1)
967 #define MCU_CTRL_BYPASS (1<<0)
968
969 #define HOR_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x08))
970 #define VERT_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x0C))
971 #define HOR_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x10))
972 #define VERT_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x14))
973 #define HOR_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x18))
974 #define VERT_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x1C))
975 #define HOR_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x20))
976 #define VERT_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x24))
977 #define LINE0_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x28))
978 #define LINE_ALPHA_EN (1<<14)
979 #define LINE_SCALE_EN (1<<13)
980 #define LINE_GBR (1<<12)
981 #define LINE_RGB (0<<12)
982 #define LINE_YUV_SRC (1<<11)
983 #define LINE_RGB_SRC (0<<11)
984 /* bits 0-10 Y_BASE */
985
986 #define LINE0_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x2C))
987 #define LINE1_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x30))
988 #define LINE1_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x34))
989 #define LINE2_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x38))
990 #define LINE2_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x3C))
991 #define LINE3_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x40))
992 #define LINE3_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x44))
993 #define START_X (*(volatile unsigned long *)(AHB1_LCDC + 0x48))
994 #define START_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x4C))
995 #define DELTA_X (*(volatile unsigned long *)(AHB1_LCDC + 0x50))
996 #define DELTA_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x54))
997 #define LCDC_INTR_MASK (*(volatile unsigned long *)(AHB1_LCDC + 0x58))
998 #define INTR_MASK_LINE (1<<3)
999 #define INTR_MASK_EVENLINE (0<<3)
1000 #define INTR_MASK_BUFF (1<<2)
1001 #define INTR_MASK_VERT (1<<1)
1002 #define INTR_MASK_HOR (1<<0)
1003
1004 #define ALPHA_ALX (*(volatile unsigned long *)(AHB1_LCDC + 0x5C))
1005 #define ALPHA_ATY (*(volatile unsigned long *)(AHB1_LCDC + 0x60))
1006 #define ALPHA_ARX (*(volatile unsigned long *)(AHB1_LCDC + 0x64))
1007 #define ALPHA_ABY (*(volatile unsigned long *)(AHB1_LCDC + 0x68))
1008
1009 #define ALPHA_BLX (*(volatile unsigned long *)(AHB1_LCDC + 0x6C))
1010 #define ALPHA_BTY (*(volatile unsigned long *)(AHB1_LCDC + 0x70))
1011 #define ALPHA_BRX (*(volatile unsigned long *)(AHB1_LCDC + 0x74))
1012 #define ALPHA_BBY (*(volatile unsigned long *)(AHB1_LCDC + 0x78))
1013
1014 #define LCDC_STA (*(volatile unsigned long *)(AHB1_LCDC + 0x7C))
1015 #define LCDC_MCU_IDLE (1<<12)
1016
1017 #define LCD_COMMAND (*(volatile unsigned long *)(AHB1_LCDC + 0x1000))
1018 #define LCD_DATA (*(volatile unsigned long *)(AHB1_LCDC + 0x1004))
1019
1020 #define LCD_BUFF ((volatile void *)(AHB1_LCDC + 0x2000))
1021 /* High speed ADC interface */
1022 #define AHB1_HS_ADC 0x186EC000
1023 #define HSADC_DATA (*(volatile unsigned long *)(AHB1_HS_ADC + 0x00))
1024 #define HSADC_CTRL (*(volatile unsigned long *)(AHB1_HS_ADC + 0x04))
1025 #define HSADC_IER (*(volatile unsigned long *)(AHB1_HS_ADC + 0x08))
1026 #define HSADC_ISR (*(volatile unsigned long *)(AHB1_HS_ADC + 0x0C))
1027
1028 /* AHB-to-AHB DMA controller */
1029 #define AHB1_DWDMA 0x186F0000
1030 #define DWDMA_SAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x00 + 0x58*n))
1031 #define DWDMA_DAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x08 + 0x58*n))
1032 #define DWDMA_LLP(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x10 + 0x58*n))
1033 #define DWDMA_CTL_L(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x18 + 0x58*n))
1034 #define CTLL_LLP_SRC_EN (1<<28)
1035 #define CTLL_LLP_DST_EN (1<<27)
1036 #define CTLL_SMS_M2 (1<<25)
1037 #define CTLL_SMS_M1 (0<<25)
1038 #define CTLL_DMS_M2 (1<<23)
1039 #define CTLL_DMS_M1 (0<<23)
1040 #define CTLL_FC_PER2PER (3<<20)
1041 #define CTLL_FC_PER2MEM (2<<20)
1042 #define CTLL_FC_MEM2PER (1<<20)
1043 #define CTLL_FC_MEM2MEM (0<<20)
1044 /* bit 19 reserved */
1045 #define CTLL_DST_SCATTER_EN (1<<18)
1046 #define CTLL_SRC_GATHER_EN (1<<17)
1047 #define CTLL_SRC_MSIZE_32 (4<<14)
1048 #define CTLL_SRC_MSIZE_16 (3<<14)
1049 #define CTLL_SRC_MSIZE_8 (2<<14)
1050 #define CTLL_SRC_MSIZE_4 (1<<14)
1051 #define CTLL_SRC_MSIZE_1 (0<<14)
1052 #define CTLL_DST_MSIZE_32 (4<<11)
1053 #define CTLL_DST_MSIZE_16 (3<<11)
1054 #define CTLL_DST_MSIZE_8 (2<<11)
1055 #define CTLL_DST_MSIZE_4 (1<<11)
1056 #define CTLL_DST_MSIZE_1 (0<<11)
1057 #define CTLL_SINC_NO (2<<9)
1058 #define CTLL_SINC_DEC (1<<9)
1059 #define CTLL_SINC_INC (0<<9)
1060 #define CTLL_DINC_NO (2<<7)
1061 #define CTLL_DINC_DEC (1<<7)
1062 #define CTLL_DINC_INC (0<<7)
1063 #define CTLL_SRC_TR_WIDTH_32 (2<<4)
1064 #define CTLL_SRC_TR_WIDTH_16 (1<<4)
1065 #define CTLL_SRC_TR_WIDTH_8 (0<<4)
1066 #define CTLL_DST_TR_WIDTH_32 (2<<1)
1067 #define CTLL_DST_TR_WIDTH_16 (1<<1)
1068 #define CTLL_DST_TR_WIDTH_8 (0<<1)
1069 #define CTLL_INT_EN (1<<0)
1070
1071 #define DWDMA_CTL_H(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x1C + 0x58*n))
1072 #define DWDMA_SSTAT(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x20 + 0x58*n))
1073 #define DWDMA_DSTAT(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x28 + 0x58*n))
1074 #define DWDMA_SSTATAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x30 + 0x58*n))
1075 #define DWDMA_DSTATAR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x38 + 0x58*n))
1076 #define DWDMA_CFG_L(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x40 + 0x58*n))
1077 #define CFGL_RELOAD_DST (1<<31)
1078 #define CFGL_RELOAD_SRC (1<<30)
1079 #define CFGL_MAX_ABRST(n) ((n)<<20)
1080 #define CFGL_SRC_HS_POL_LOW (1<<19)
1081 #define CFGL_DST_HS_POL_LOW (1<<18)
1082 #define CFGL_LOCK_B (1<<17)
1083 #define CFGL_LOCK_CH (1<<16)
1084 #define CFGL_LOCK_B_L(n) (((n)&0x03)<<14)
1085 #define CFGL_LOCK_CH_L(n) (((n)&0x03)<<12)
1086 #define CFGL_HS_SEL_SRC (1<<11)
1087 #define CFGL_HS_SEL_DST (1<<10)
1088 #define CFGL_FIFO_EMPTY (1<<9)
1089 #define CFGL_CH_SUSP (1<<8)
1090 #define CFGL_CH_PRIOR(n) (((n) & 0x03)<<5)
1091 /* bits 0-4 reserved */
1092 #define DWDMA_CFG_H(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x44 + 0x58*n))
1093 #define CFGH_DST_PER(n) (((n)&0x0F)<<11)
1094 #define CFGH_SRC_PER(n) (((n)&0x0F)<<7)
1095 #define CFGH_SRC_UPD_EN (1<<6)
1096 #define CFGH_DST_UPD_EN (1<<5)
1097 #define CFGH_PROTCTL(n) (((n)&0x07)<<2)
1098 #define CFGH_FIFO_MODE (1<<1)
1099 #define CFGH_FC_MODE (1<<0)
1100
1101 #define DWDMA_SGR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x48 + 0x58*n))
1102 #define DWDMA_DSR(n) (*(volatile unsigned long *)(AHB1_DWDMA + 0x50 + 0x58*n))
1103
1104 #define DWDMA_RAW_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2C0))
1105 #define DWDMA_RAW_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x2C8))
1106 #define DWDMA_RAW_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2D0))
1107 #define DWDMA_RAW_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2D8))
1108 #define DWDMA_RAW_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2E0))
1109
1110 #define DWDMA_STATUS_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x2E8))
1111 #define DWDMA_STATUS_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x2F0))
1112 #define DWDMA_STATUS_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x2F8))
1113 #define DWDMA_STATUS_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x300))
1114 #define DWDMA_STATUS_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x308))
1115
1116 #define DWDMA_MASK_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x310))
1117 #define DWDMA_MASK_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x318))
1118 #define DWDMA_MASK_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x320))
1119 #define DWDMA_MASK_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x328))
1120 #define DWDMA_MASK_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x330))
1121
1122 #define DWDMA_CLEAR_TFR (*(volatile unsigned long *)(AHB1_DWDMA + 0x338))
1123 #define DWDMA_CLEAR_BLOCK (*(volatile unsigned long *)(AHB1_DWDMA + 0x340))
1124 #define DWDMA_CLEAR_SRCTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x348))
1125 #define DWDMA_CLEAR_DSTTRAN (*(volatile unsigned long *)(AHB1_DWDMA + 0x350))
1126 #define DWDMA_CLEAR_ERR (*(volatile unsigned long *)(AHB1_DWDMA + 0x358))
1127
1128 #define DWDMA_STATUS_INT (*(volatile unsigned long *)(AHB1_DWDMA + 0x360))
1129
1130 #define DWDMA_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x368))
1131 #define DWDMA_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x370))
1132 #define DWDMA_S_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x378))
1133 #define DWDMA_S_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x380))
1134 #define DWDMA_L_REQ_SRC (*(volatile unsigned long *)(AHB1_DWDMA + 0x388))
1135 #define DWDMA_L_REQ_DST (*(volatile unsigned long *)(AHB1_DWDMA + 0x390))
1136
1137 #define DWDMA_DMA_CFG (*(volatile unsigned long *)(AHB1_DWDMA + 0x398))
1138 #define GLOB_EN (1<<0)
1139 #define DWDMA_DMA_CHEN (*(volatile unsigned long *)(AHB1_DWDMA + 0x3A0))
1140 #define DMACHEN_CH0 (0x101<<0)
1141 #define DMACHEN_CH1 (0x101<<1)
1142 #define DMACHEN_CH2 (0x101<<2)
1143 #define DMACHEN_CH3 (0x101<<3)
1144
1145 /* ARM7 cache controller */
1146 #define ARM_CACHE_CTRL 0xEFFF0000
1147 #define DEVID (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x00))
1148 #define CACHEOP (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x04))
1149 #define CACHELKDN (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x08))
1150
1151 #define MEMMAPA (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x10))
1152 #define MEMMAPB (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x14))
1153 #define MEMMAPC (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x18))
1154 #define MEMMAPD (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x1C))
1155 #define PFCNTRA_CTRL (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x20))
1156 #define PFCNTRA (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x24))
1157 #define PFCNTRB_CTRL (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x28))
1158 #define PFCNTRB (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x2C))
1159
1160 /* Timer frequency */
1161 #define TIMER_FREQ 50000000
thomasjfox's rockbox modifications (mameo port)