From f11f9f180fc9968aa67a86ccd9c870b383104bf4 Mon Sep 17 00:00:00 2001 From: Bruno Cardoso Lopes Date: Wed, 23 Jun 2010 19:50:39 +0000 Subject: [PATCH] Fix a tblgen bug. Given the pattern below as an example: list Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1, (mem_frag addr:$src2))))]; The right reference resolving should lead to: list Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1, (mem_frag addr:$src2))))]; But was yielding: list Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1, (mem_frag addr:$src2))))]; Fix this by passing the right name when creating a new DagInit node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106670 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/TableGen/usevalname.td | 24 ++++++++++++++++++++++++ utils/TableGen/Record.cpp | 2 +- 2 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 test/TableGen/usevalname.td diff --git a/test/TableGen/usevalname.td b/test/TableGen/usevalname.td new file mode 100644 index 0000000000..1b31c8f150 --- /dev/null +++ b/test/TableGen/usevalname.td @@ -0,0 +1,24 @@ +// RUN: tblgen %s | FileCheck %s +// XFAIL: vg_leak + +class Instr pat> { + list Pattern = pat; +} + +class Reg { + int a = 3; +} + +def VR128 : Reg; +def mem_frag; +def set; +def addr; +def shufp : Reg; + +multiclass shuffle { + def rri : Instr<[(set RC:$dst, (shufp:$src3 + RC:$src1, RC:$src2))]>; +} + +// CHECK: shufp:src3 +defm ADD : shuffle; diff --git a/utils/TableGen/Record.cpp b/utils/TableGen/Record.cpp index 5a69edb615..d2cf379907 100644 --- a/utils/TableGen/Record.cpp +++ b/utils/TableGen/Record.cpp @@ -1262,7 +1262,7 @@ Init *DagInit::resolveReferences(Record &R, const RecordVal *RV) { Init *Op = Val->resolveReferences(R, RV); if (Args != NewArgs || Op != Val) - return new DagInit(Op, "", NewArgs, ArgNames); + return new DagInit(Op, ValName, NewArgs, ArgNames); return this; } -- 2.11.4.GIT