| commit | c399770b5cd8e6a6536435b055acaac06dcd9935 | |
| author | David Green <david.green@arm.com> | |
| Tue, 17 Sep 2019 15:23:09 +0000 (17 15:23 +0000) | ||
| committer | David Green <david.green@arm.com> | |
| Tue, 17 Sep 2019 15:23:09 +0000 (17 15:23 +0000) | ||
| tree | 03041ebefade4d8177a51205d6664b9c59091b6f | treesnapshot (tar.gz zip) |
| parent | 407502440cfafa6a250e4c0ab2118993e5c2f6f5 | commitdiff |
[ARM] Reserve an emergency spill slot for fp16 addressing modes that need it
Similar to D67327, but this time for the FP16 VLDR and VSTR instructions that
use the AddrMode5FP16 addressing mode. We need to reserve an emergency spill
slot for instructions that will be out of range to use sp directly.
AddrMode5FP16 is 8 bits with a scale of 2.
Differential Revision: https://reviews.llvm.org/D67483
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372132 91177308-0d34-0410-b5e6-96231b3b80d8
Similar to D67327, but this time for the FP16 VLDR and VSTR instructions that
use the AddrMode5FP16 addressing mode. We need to reserve an emergency spill
slot for instructions that will be out of range to use sp directly.
AddrMode5FP16 is 8 bits with a scale of 2.
Differential Revision: https://reviews.llvm.org/D67483
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372132 91177308-0d34-0410-b5e6-96231b3b80d8
| lib/Target/ARM/ARMFrameLowering.cpp | diffblobblamehistory | |
| test/CodeGen/Thumb2/fp16-stacksplot.mir | [new file with mode: 0644] | blob |