| commit | 59654524ceb87432eb2578db74a7c83dcdafa59b | |
| author | David Green <david.green@arm.com> | |
| Tue, 17 Sep 2019 12:58:51 +0000 (17 12:58 +0000) | ||
| committer | David Green <david.green@arm.com> | |
| Tue, 17 Sep 2019 12:58:51 +0000 (17 12:58 +0000) | ||
| tree | 751cfba9a32b2f899e221aa649bc0fe1c1aa59fb | treesnapshot (tar.gz zip) |
| parent | 1d7df59e12cfeefba37ee56341a39704e708c9f0 | commitdiff |
[ARM] Fix for MVE load/store stack accesses
MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices.
Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used.
Differential Revision: https://reviews.llvm.org/D67327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372114 91177308-0d34-0410-b5e6-96231b3b80d8
MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices.
Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used.
Differential Revision: https://reviews.llvm.org/D67327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372114 91177308-0d34-0410-b5e6-96231b3b80d8
| lib/Target/ARM/ARMFrameLowering.cpp | diffblobblamehistory | |
| test/CodeGen/Thumb2/mve-stacksplot.mir | [new file with mode: 0644] | blob |