2 * Set up the interrupt priorities
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
11 * Licensed under the GPL-2
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
19 #include <linux/ipipe.h>
22 #include <linux/kgdb.h>
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
27 #include <asm/irq_handler.h>
29 #include <asm/bfin5xx_spi.h>
30 #include <asm/bfin_sport.h>
31 #include <asm/bfin_can.h>
33 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
36 # define BF537_GENERIC_ERROR_INT_DEMUX
37 # define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
38 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
39 # define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
40 # define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
41 # define UART_ERR_MASK (0x6) /* UART_IIR */
42 # define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
44 # undef BF537_GENERIC_ERROR_INT_DEMUX
49 * - we have separated the physical Hardware interrupt from the
50 * levels that the LINUX kernel sees (see the description in irq.h)
55 /* Initialize this to an actual value to force it into the .data
56 * section so that we know it is properly initialized at entry into
57 * the kernel but before bss is initialized to zero (which is where
58 * it would live otherwise). The 0x1f magic represents the IRQs we
59 * cannot actually mask out in hardware.
61 unsigned long bfin_irq_flags
= 0x1f;
62 EXPORT_SYMBOL(bfin_irq_flags
);
65 /* The number of spurious interrupts */
66 atomic_t num_spurious
;
69 unsigned long bfin_sic_iwr
[3]; /* Up to 3 SIC_IWRx registers */
74 /* irq number for request_irq, available in mach-bf5xx/irq.h */
76 /* corresponding bit in the SIC_ISR register */
78 } ivg_table
[NR_PERI_INTS
];
81 /* position of first irq in ivg_table for given ivg */
84 } ivg7_13
[IVG13
- IVG7
+ 1];
88 * Search SIC_IAR and fill tables with the irqvalues
89 * and their positions in the SIC_ISR register.
91 static void __init
search_IAR(void)
93 unsigned ivg
, irq_pos
= 0;
94 for (ivg
= 0; ivg
<= IVG13
- IVG7
; ivg
++) {
97 ivg7_13
[ivg
].istop
= ivg7_13
[ivg
].ifirst
= &ivg_table
[irq_pos
];
99 for (irqN
= 0; irqN
< NR_PERI_INTS
; irqN
+= 4) {
101 u32 iar
= bfin_read32((unsigned long *)SIC_IAR0
+
102 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
103 defined(CONFIG_BF538) || defined(CONFIG_BF539)
104 ((irqN
% 32) >> 3) + ((irqN
/ 32) * ((SIC_IAR4
- SIC_IAR0
) / 4))
110 for (irqn
= irqN
; irqn
< irqN
+ 4; ++irqn
) {
111 int iar_shift
= (irqn
& 7) * 4;
112 if (ivg
== (0xf & (iar
>> iar_shift
))) {
113 ivg_table
[irq_pos
].irqno
= IVG7
+ irqn
;
114 ivg_table
[irq_pos
].isrflag
= 1 << (irqn
% 32);
115 ivg7_13
[ivg
].istop
++;
124 * This is for core internal IRQs
127 static void bfin_ack_noop(unsigned int irq
)
129 /* Dummy function. */
132 static void bfin_core_mask_irq(unsigned int irq
)
134 bfin_irq_flags
&= ~(1 << irq
);
135 if (!irqs_disabled_hw())
136 local_irq_enable_hw();
139 static void bfin_core_unmask_irq(unsigned int irq
)
141 bfin_irq_flags
|= 1 << irq
;
143 * If interrupts are enabled, IMASK must contain the same value
144 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
145 * are currently disabled we need not do anything; one of the
146 * callers will take care of setting IMASK to the proper value
147 * when reenabling interrupts.
148 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
151 if (!irqs_disabled_hw())
152 local_irq_enable_hw();
156 static void bfin_internal_mask_irq(unsigned int irq
)
161 local_irq_save_hw(flags
);
162 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
163 ~(1 << SIC_SYSIRQ(irq
)));
165 unsigned mask_bank
, mask_bit
;
166 local_irq_save_hw(flags
);
167 mask_bank
= SIC_SYSIRQ(irq
) / 32;
168 mask_bit
= SIC_SYSIRQ(irq
) % 32;
169 bfin_write_SIC_IMASK(mask_bank
, bfin_read_SIC_IMASK(mask_bank
) &
172 bfin_write_SICB_IMASK(mask_bank
, bfin_read_SICB_IMASK(mask_bank
) &
176 local_irq_restore_hw(flags
);
180 static void bfin_internal_unmask_irq_affinity(unsigned int irq
,
181 const struct cpumask
*affinity
)
183 static void bfin_internal_unmask_irq(unsigned int irq
)
189 local_irq_save_hw(flags
);
190 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
191 (1 << SIC_SYSIRQ(irq
)));
193 unsigned mask_bank
, mask_bit
;
194 local_irq_save_hw(flags
);
195 mask_bank
= SIC_SYSIRQ(irq
) / 32;
196 mask_bit
= SIC_SYSIRQ(irq
) % 32;
198 if (cpumask_test_cpu(0, affinity
))
200 bfin_write_SIC_IMASK(mask_bank
,
201 bfin_read_SIC_IMASK(mask_bank
) |
204 if (cpumask_test_cpu(1, affinity
))
205 bfin_write_SICB_IMASK(mask_bank
,
206 bfin_read_SICB_IMASK(mask_bank
) |
210 local_irq_restore_hw(flags
);
214 static void bfin_internal_unmask_irq(unsigned int irq
)
216 struct irq_desc
*desc
= irq_to_desc(irq
);
217 bfin_internal_unmask_irq_affinity(irq
, desc
->affinity
);
220 static int bfin_internal_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
222 bfin_internal_mask_irq(irq
);
223 bfin_internal_unmask_irq_affinity(irq
, mask
);
230 int bfin_internal_set_wake(unsigned int irq
, unsigned int state
)
232 u32 bank
, bit
, wakeup
= 0;
234 bank
= SIC_SYSIRQ(irq
) / 32;
235 bit
= SIC_SYSIRQ(irq
) % 32;
267 local_irq_save_hw(flags
);
270 bfin_sic_iwr
[bank
] |= (1 << bit
);
274 bfin_sic_iwr
[bank
] &= ~(1 << bit
);
275 vr_wakeup
&= ~wakeup
;
278 local_irq_restore_hw(flags
);
284 static struct irq_chip bfin_core_irqchip
= {
286 .ack
= bfin_ack_noop
,
287 .mask
= bfin_core_mask_irq
,
288 .unmask
= bfin_core_unmask_irq
,
291 static struct irq_chip bfin_internal_irqchip
= {
293 .ack
= bfin_ack_noop
,
294 .mask
= bfin_internal_mask_irq
,
295 .unmask
= bfin_internal_unmask_irq
,
296 .mask_ack
= bfin_internal_mask_irq
,
297 .disable
= bfin_internal_mask_irq
,
298 .enable
= bfin_internal_unmask_irq
,
300 .set_affinity
= bfin_internal_set_affinity
,
303 .set_wake
= bfin_internal_set_wake
,
307 static void bfin_handle_irq(unsigned irq
)
310 struct pt_regs regs
; /* Contents not used. */
311 ipipe_trace_irq_entry(irq
);
312 __ipipe_handle_irq(irq
, ®s
);
313 ipipe_trace_irq_exit(irq
);
314 #else /* !CONFIG_IPIPE */
315 struct irq_desc
*desc
= irq_desc
+ irq
;
316 desc
->handle_irq(irq
, desc
);
317 #endif /* !CONFIG_IPIPE */
320 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
321 static int error_int_mask
;
323 static void bfin_generic_error_mask_irq(unsigned int irq
)
325 error_int_mask
&= ~(1L << (irq
- IRQ_PPI_ERROR
));
327 bfin_internal_mask_irq(IRQ_GENERIC_ERROR
);
330 static void bfin_generic_error_unmask_irq(unsigned int irq
)
332 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR
);
333 error_int_mask
|= 1L << (irq
- IRQ_PPI_ERROR
);
336 static struct irq_chip bfin_generic_error_irqchip
= {
338 .ack
= bfin_ack_noop
,
339 .mask_ack
= bfin_generic_error_mask_irq
,
340 .mask
= bfin_generic_error_mask_irq
,
341 .unmask
= bfin_generic_error_unmask_irq
,
344 static void bfin_demux_error_irq(unsigned int int_err_irq
,
345 struct irq_desc
*inta_desc
)
349 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
350 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK
)
354 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK
)
355 irq
= IRQ_SPORT0_ERROR
;
356 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK
)
357 irq
= IRQ_SPORT1_ERROR
;
358 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK
)
360 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK
)
362 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK
)
364 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK
) == UART_ERR_MASK
)
365 irq
= IRQ_UART0_ERROR
;
366 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK
) == UART_ERR_MASK
)
367 irq
= IRQ_UART1_ERROR
;
370 if (error_int_mask
& (1L << (irq
- IRQ_PPI_ERROR
)))
371 bfin_handle_irq(irq
);
376 bfin_write_PPI_STATUS(PPI_ERR_MASK
);
378 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
380 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK
);
383 case IRQ_SPORT0_ERROR
:
384 bfin_write_SPORT0_STAT(SPORT_ERR_MASK
);
387 case IRQ_SPORT1_ERROR
:
388 bfin_write_SPORT1_STAT(SPORT_ERR_MASK
);
392 bfin_write_CAN_GIS(CAN_ERR_MASK
);
396 bfin_write_SPI_STAT(SPI_ERR_MASK
);
404 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
409 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
410 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
411 __func__
, __FILE__
, __LINE__
);
414 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
416 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
417 static int mac_stat_int_mask
;
419 static void bfin_mac_status_ack_irq(unsigned int irq
)
423 bfin_write_EMAC_MMC_TIRQS(
424 bfin_read_EMAC_MMC_TIRQE() &
425 bfin_read_EMAC_MMC_TIRQS());
426 bfin_write_EMAC_MMC_RIRQS(
427 bfin_read_EMAC_MMC_RIRQE() &
428 bfin_read_EMAC_MMC_RIRQS());
430 case IRQ_MAC_RXFSINT
:
431 bfin_write_EMAC_RX_STKY(
432 bfin_read_EMAC_RX_IRQE() &
433 bfin_read_EMAC_RX_STKY());
435 case IRQ_MAC_TXFSINT
:
436 bfin_write_EMAC_TX_STKY(
437 bfin_read_EMAC_TX_IRQE() &
438 bfin_read_EMAC_TX_STKY());
440 case IRQ_MAC_WAKEDET
:
441 bfin_write_EMAC_WKUP_CTL(
442 bfin_read_EMAC_WKUP_CTL() | MPKS
| RWKS
);
445 /* These bits are W1C */
446 bfin_write_EMAC_SYSTAT(1L << (irq
- IRQ_MAC_PHYINT
));
451 static void bfin_mac_status_mask_irq(unsigned int irq
)
453 mac_stat_int_mask
&= ~(1L << (irq
- IRQ_MAC_PHYINT
));
454 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
457 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE
);
463 if (!mac_stat_int_mask
)
464 bfin_internal_mask_irq(IRQ_MAC_ERROR
);
466 bfin_mac_status_ack_irq(irq
);
469 static void bfin_mac_status_unmask_irq(unsigned int irq
)
471 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
474 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE
);
480 if (!mac_stat_int_mask
)
481 bfin_internal_unmask_irq(IRQ_MAC_ERROR
);
483 mac_stat_int_mask
|= 1L << (irq
- IRQ_MAC_PHYINT
);
487 int bfin_mac_status_set_wake(unsigned int irq
, unsigned int state
)
489 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
490 return bfin_internal_set_wake(IRQ_GENERIC_ERROR
, state
);
492 return bfin_internal_set_wake(IRQ_MAC_ERROR
, state
);
497 static struct irq_chip bfin_mac_status_irqchip
= {
499 .ack
= bfin_ack_noop
,
500 .mask_ack
= bfin_mac_status_mask_irq
,
501 .mask
= bfin_mac_status_mask_irq
,
502 .unmask
= bfin_mac_status_unmask_irq
,
504 .set_wake
= bfin_mac_status_set_wake
,
508 static void bfin_demux_mac_status_irq(unsigned int int_err_irq
,
509 struct irq_desc
*inta_desc
)
512 u32 status
= bfin_read_EMAC_SYSTAT();
514 for (i
= 0; i
< (IRQ_MAC_STMDONE
- IRQ_MAC_PHYINT
); i
++)
515 if (status
& (1L << i
)) {
516 irq
= IRQ_MAC_PHYINT
+ i
;
521 if (mac_stat_int_mask
& (1L << (irq
- IRQ_MAC_PHYINT
))) {
522 bfin_handle_irq(irq
);
524 bfin_mac_status_ack_irq(irq
);
526 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
531 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
532 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
533 __func__
, __FILE__
, __LINE__
);
537 static inline void bfin_set_irq_handler(unsigned irq
, irq_flow_handler_t handle
)
540 _set_irq_handler(irq
, handle_level_irq
);
542 struct irq_desc
*desc
= irq_desc
+ irq
;
543 /* May not call generic set_irq_handler() due to spinlock
545 desc
->handle_irq
= handle
;
549 static DECLARE_BITMAP(gpio_enabled
, MAX_BLACKFIN_GPIOS
);
550 extern void bfin_gpio_irq_prepare(unsigned gpio
);
552 #if !defined(CONFIG_BF54x)
554 static void bfin_gpio_ack_irq(unsigned int irq
)
556 /* AFAIK ack_irq in case mask_ack is provided
557 * get's only called for edge sense irqs
559 set_gpio_data(irq_to_gpio(irq
), 0);
562 static void bfin_gpio_mask_ack_irq(unsigned int irq
)
564 struct irq_desc
*desc
= irq_desc
+ irq
;
565 u32 gpionr
= irq_to_gpio(irq
);
567 if (desc
->handle_irq
== handle_edge_irq
)
568 set_gpio_data(gpionr
, 0);
570 set_gpio_maska(gpionr
, 0);
573 static void bfin_gpio_mask_irq(unsigned int irq
)
575 set_gpio_maska(irq_to_gpio(irq
), 0);
578 static void bfin_gpio_unmask_irq(unsigned int irq
)
580 set_gpio_maska(irq_to_gpio(irq
), 1);
583 static unsigned int bfin_gpio_irq_startup(unsigned int irq
)
585 u32 gpionr
= irq_to_gpio(irq
);
587 if (__test_and_set_bit(gpionr
, gpio_enabled
))
588 bfin_gpio_irq_prepare(gpionr
);
590 bfin_gpio_unmask_irq(irq
);
595 static void bfin_gpio_irq_shutdown(unsigned int irq
)
597 u32 gpionr
= irq_to_gpio(irq
);
599 bfin_gpio_mask_irq(irq
);
600 __clear_bit(gpionr
, gpio_enabled
);
601 bfin_gpio_irq_free(gpionr
);
604 static int bfin_gpio_irq_type(unsigned int irq
, unsigned int type
)
608 u32 gpionr
= irq_to_gpio(irq
);
610 if (type
== IRQ_TYPE_PROBE
) {
611 /* only probe unenabled GPIO interrupt lines */
612 if (test_bit(gpionr
, gpio_enabled
))
614 type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
617 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
|
618 IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
)) {
620 snprintf(buf
, 16, "gpio-irq%d", irq
);
621 ret
= bfin_gpio_irq_request(gpionr
, buf
);
625 if (__test_and_set_bit(gpionr
, gpio_enabled
))
626 bfin_gpio_irq_prepare(gpionr
);
629 __clear_bit(gpionr
, gpio_enabled
);
633 set_gpio_inen(gpionr
, 0);
634 set_gpio_dir(gpionr
, 0);
636 if ((type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
637 == (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
638 set_gpio_both(gpionr
, 1);
640 set_gpio_both(gpionr
, 0);
642 if ((type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_LEVEL_LOW
)))
643 set_gpio_polar(gpionr
, 1); /* low or falling edge denoted by one */
645 set_gpio_polar(gpionr
, 0); /* high or rising edge denoted by zero */
647 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
)) {
648 set_gpio_edge(gpionr
, 1);
649 set_gpio_inen(gpionr
, 1);
650 set_gpio_data(gpionr
, 0);
653 set_gpio_edge(gpionr
, 0);
654 set_gpio_inen(gpionr
, 1);
657 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
658 bfin_set_irq_handler(irq
, handle_edge_irq
);
660 bfin_set_irq_handler(irq
, handle_level_irq
);
666 int bfin_gpio_set_wake(unsigned int irq
, unsigned int state
)
668 return gpio_pm_wakeup_ctrl(irq_to_gpio(irq
), state
);
672 static void bfin_demux_gpio_irq(unsigned int inta_irq
,
673 struct irq_desc
*desc
)
675 unsigned int i
, gpio
, mask
, irq
, search
= 0;
678 #if defined(CONFIG_BF53x)
683 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
688 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
692 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
702 #elif defined(CONFIG_BF561)
719 for (i
= 0; i
< MAX_BLACKFIN_GPIOS
; i
+= GPIO_BANKSIZE
) {
722 mask
= get_gpiop_data(i
) & get_gpiop_maska(i
);
726 bfin_handle_irq(irq
);
732 gpio
= irq_to_gpio(irq
);
733 mask
= get_gpiop_data(gpio
) & get_gpiop_maska(gpio
);
737 bfin_handle_irq(irq
);
745 #else /* CONFIG_BF54x */
747 #define NR_PINT_SYS_IRQS 4
748 #define NR_PINT_BITS 32
750 #define IRQ_NOT_AVAIL 0xFF
752 #define PINT_2_BANK(x) ((x) >> 5)
753 #define PINT_2_BIT(x) ((x) & 0x1F)
754 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
756 static unsigned char irq2pint_lut
[NR_PINTS
];
757 static unsigned char pint2irq_lut
[NR_PINT_SYS_IRQS
* NR_PINT_BITS
];
760 unsigned int mask_set
;
761 unsigned int mask_clear
;
762 unsigned int request
;
764 unsigned int edge_set
;
765 unsigned int edge_clear
;
766 unsigned int invert_set
;
767 unsigned int invert_clear
;
768 unsigned int pinstate
;
772 static struct pin_int_t
*pint
[NR_PINT_SYS_IRQS
] = {
773 (struct pin_int_t
*)PINT0_MASK_SET
,
774 (struct pin_int_t
*)PINT1_MASK_SET
,
775 (struct pin_int_t
*)PINT2_MASK_SET
,
776 (struct pin_int_t
*)PINT3_MASK_SET
,
779 inline unsigned int get_irq_base(u32 bank
, u8 bmap
)
781 unsigned int irq_base
;
783 if (bank
< 2) { /*PA-PB */
784 irq_base
= IRQ_PA0
+ bmap
* 16;
786 irq_base
= IRQ_PC0
+ bmap
* 16;
792 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
793 void init_pint_lut(void)
795 u16 bank
, bit
, irq_base
, bit_pos
;
799 memset(irq2pint_lut
, IRQ_NOT_AVAIL
, sizeof(irq2pint_lut
));
801 for (bank
= 0; bank
< NR_PINT_SYS_IRQS
; bank
++) {
803 pint_assign
= pint
[bank
]->assign
;
805 for (bit
= 0; bit
< NR_PINT_BITS
; bit
++) {
807 bmap
= (pint_assign
>> ((bit
/ 8) * 8)) & 0xFF;
809 irq_base
= get_irq_base(bank
, bmap
);
811 irq_base
+= (bit
% 8) + ((bit
/ 8) & 1 ? 8 : 0);
812 bit_pos
= bit
+ bank
* NR_PINT_BITS
;
814 pint2irq_lut
[bit_pos
] = irq_base
- SYS_IRQS
;
815 irq2pint_lut
[irq_base
- SYS_IRQS
] = bit_pos
;
820 static void bfin_gpio_ack_irq(unsigned int irq
)
822 struct irq_desc
*desc
= irq_desc
+ irq
;
823 u32 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
824 u32 pintbit
= PINT_BIT(pint_val
);
825 u32 bank
= PINT_2_BANK(pint_val
);
827 if ((desc
->status
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
) {
828 if (pint
[bank
]->invert_set
& pintbit
)
829 pint
[bank
]->invert_clear
= pintbit
;
831 pint
[bank
]->invert_set
= pintbit
;
833 pint
[bank
]->request
= pintbit
;
837 static void bfin_gpio_mask_ack_irq(unsigned int irq
)
839 struct irq_desc
*desc
= irq_desc
+ irq
;
840 u32 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
841 u32 pintbit
= PINT_BIT(pint_val
);
842 u32 bank
= PINT_2_BANK(pint_val
);
844 if ((desc
->status
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
) {
845 if (pint
[bank
]->invert_set
& pintbit
)
846 pint
[bank
]->invert_clear
= pintbit
;
848 pint
[bank
]->invert_set
= pintbit
;
851 pint
[bank
]->request
= pintbit
;
852 pint
[bank
]->mask_clear
= pintbit
;
855 static void bfin_gpio_mask_irq(unsigned int irq
)
857 u32 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
859 pint
[PINT_2_BANK(pint_val
)]->mask_clear
= PINT_BIT(pint_val
);
862 static void bfin_gpio_unmask_irq(unsigned int irq
)
864 u32 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
865 u32 pintbit
= PINT_BIT(pint_val
);
866 u32 bank
= PINT_2_BANK(pint_val
);
868 pint
[bank
]->request
= pintbit
;
869 pint
[bank
]->mask_set
= pintbit
;
872 static unsigned int bfin_gpio_irq_startup(unsigned int irq
)
874 u32 gpionr
= irq_to_gpio(irq
);
875 u32 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
877 if (pint_val
== IRQ_NOT_AVAIL
) {
879 "GPIO IRQ %d :Not in PINT Assign table "
880 "Reconfigure Interrupt to Port Assignemt\n", irq
);
884 if (__test_and_set_bit(gpionr
, gpio_enabled
))
885 bfin_gpio_irq_prepare(gpionr
);
887 bfin_gpio_unmask_irq(irq
);
892 static void bfin_gpio_irq_shutdown(unsigned int irq
)
894 u32 gpionr
= irq_to_gpio(irq
);
896 bfin_gpio_mask_irq(irq
);
897 __clear_bit(gpionr
, gpio_enabled
);
898 bfin_gpio_irq_free(gpionr
);
901 static int bfin_gpio_irq_type(unsigned int irq
, unsigned int type
)
905 u32 gpionr
= irq_to_gpio(irq
);
906 u32 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
907 u32 pintbit
= PINT_BIT(pint_val
);
908 u32 bank
= PINT_2_BANK(pint_val
);
910 if (pint_val
== IRQ_NOT_AVAIL
)
913 if (type
== IRQ_TYPE_PROBE
) {
914 /* only probe unenabled GPIO interrupt lines */
915 if (test_bit(gpionr
, gpio_enabled
))
917 type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
920 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
|
921 IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
)) {
923 snprintf(buf
, 16, "gpio-irq%d", irq
);
924 ret
= bfin_gpio_irq_request(gpionr
, buf
);
928 if (__test_and_set_bit(gpionr
, gpio_enabled
))
929 bfin_gpio_irq_prepare(gpionr
);
932 __clear_bit(gpionr
, gpio_enabled
);
936 if ((type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_LEVEL_LOW
)))
937 pint
[bank
]->invert_set
= pintbit
; /* low or falling edge denoted by one */
939 pint
[bank
]->invert_clear
= pintbit
; /* high or rising edge denoted by zero */
941 if ((type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
))
942 == (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
)) {
943 if (gpio_get_value(gpionr
))
944 pint
[bank
]->invert_set
= pintbit
;
946 pint
[bank
]->invert_clear
= pintbit
;
949 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
)) {
950 pint
[bank
]->edge_set
= pintbit
;
951 bfin_set_irq_handler(irq
, handle_edge_irq
);
953 pint
[bank
]->edge_clear
= pintbit
;
954 bfin_set_irq_handler(irq
, handle_level_irq
);
961 u32 pint_saved_masks
[NR_PINT_SYS_IRQS
];
962 u32 pint_wakeup_masks
[NR_PINT_SYS_IRQS
];
964 int bfin_gpio_set_wake(unsigned int irq
, unsigned int state
)
967 u32 pint_val
= irq2pint_lut
[irq
- SYS_IRQS
];
968 u32 bank
= PINT_2_BANK(pint_val
);
969 u32 pintbit
= PINT_BIT(pint_val
);
973 pint_irq
= IRQ_PINT0
;
976 pint_irq
= IRQ_PINT2
;
979 pint_irq
= IRQ_PINT3
;
982 pint_irq
= IRQ_PINT1
;
988 bfin_internal_set_wake(pint_irq
, state
);
991 pint_wakeup_masks
[bank
] |= pintbit
;
993 pint_wakeup_masks
[bank
] &= ~pintbit
;
998 u32
bfin_pm_setup(void)
1002 for (i
= 0; i
< NR_PINT_SYS_IRQS
; i
++) {
1003 val
= pint
[i
]->mask_clear
;
1004 pint_saved_masks
[i
] = val
;
1005 if (val
^ pint_wakeup_masks
[i
]) {
1006 pint
[i
]->mask_clear
= val
;
1007 pint
[i
]->mask_set
= pint_wakeup_masks
[i
];
1014 void bfin_pm_restore(void)
1018 for (i
= 0; i
< NR_PINT_SYS_IRQS
; i
++) {
1019 val
= pint_saved_masks
[i
];
1020 if (val
^ pint_wakeup_masks
[i
]) {
1021 pint
[i
]->mask_clear
= pint
[i
]->mask_clear
;
1022 pint
[i
]->mask_set
= val
;
1028 static void bfin_demux_gpio_irq(unsigned int inta_irq
,
1029 struct irq_desc
*desc
)
1051 pint_val
= bank
* NR_PINT_BITS
;
1053 request
= pint
[bank
]->request
;
1057 irq
= pint2irq_lut
[pint_val
] + SYS_IRQS
;
1058 bfin_handle_irq(irq
);
1067 static struct irq_chip bfin_gpio_irqchip
= {
1069 .ack
= bfin_gpio_ack_irq
,
1070 .mask
= bfin_gpio_mask_irq
,
1071 .mask_ack
= bfin_gpio_mask_ack_irq
,
1072 .unmask
= bfin_gpio_unmask_irq
,
1073 .disable
= bfin_gpio_mask_irq
,
1074 .enable
= bfin_gpio_unmask_irq
,
1075 .set_type
= bfin_gpio_irq_type
,
1076 .startup
= bfin_gpio_irq_startup
,
1077 .shutdown
= bfin_gpio_irq_shutdown
,
1079 .set_wake
= bfin_gpio_set_wake
,
1083 void __cpuinit
init_exception_vectors(void)
1085 /* cannot program in software:
1086 * evt0 - emulation (jtag)
1089 bfin_write_EVT2(evt_nmi
);
1090 bfin_write_EVT3(trap
);
1091 bfin_write_EVT5(evt_ivhw
);
1092 bfin_write_EVT6(evt_timer
);
1093 bfin_write_EVT7(evt_evt7
);
1094 bfin_write_EVT8(evt_evt8
);
1095 bfin_write_EVT9(evt_evt9
);
1096 bfin_write_EVT10(evt_evt10
);
1097 bfin_write_EVT11(evt_evt11
);
1098 bfin_write_EVT12(evt_evt12
);
1099 bfin_write_EVT13(evt_evt13
);
1100 bfin_write_EVT14(evt_evt14
);
1101 bfin_write_EVT15(evt_system_call
);
1106 * This function should be called during kernel startup to initialize
1107 * the BFin IRQ handling routines.
1110 int __init
init_arch_irq(void)
1113 unsigned long ilat
= 0;
1114 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1115 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1116 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1117 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL
);
1118 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL
);
1119 # ifdef CONFIG_BF54x
1120 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL
);
1123 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL
);
1124 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL
);
1127 bfin_write_SIC_IMASK(SIC_UNMASK_ALL
);
1130 local_irq_disable();
1132 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1133 /* Clear EMAC Interrupt Status bits so we can demux it later */
1134 bfin_write_EMAC_SYSTAT(-1);
1138 # ifdef CONFIG_PINTx_REASSIGN
1139 pint
[0]->assign
= CONFIG_PINT0_ASSIGN
;
1140 pint
[1]->assign
= CONFIG_PINT1_ASSIGN
;
1141 pint
[2]->assign
= CONFIG_PINT2_ASSIGN
;
1142 pint
[3]->assign
= CONFIG_PINT3_ASSIGN
;
1144 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1148 for (irq
= 0; irq
<= SYS_IRQS
; irq
++) {
1149 if (irq
<= IRQ_CORETMR
)
1150 set_irq_chip(irq
, &bfin_core_irqchip
);
1152 set_irq_chip(irq
, &bfin_internal_irqchip
);
1155 #if defined(CONFIG_BF53x)
1157 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1160 #elif defined(CONFIG_BF54x)
1165 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1166 case IRQ_PORTF_INTA
:
1167 case IRQ_PORTG_INTA
:
1168 case IRQ_PORTH_INTA
:
1169 #elif defined(CONFIG_BF561)
1170 case IRQ_PROG0_INTA
:
1171 case IRQ_PROG1_INTA
:
1172 case IRQ_PROG2_INTA
:
1173 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1174 case IRQ_PORTF_INTA
:
1176 set_irq_chained_handler(irq
,
1177 bfin_demux_gpio_irq
);
1179 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1180 case IRQ_GENERIC_ERROR
:
1181 set_irq_chained_handler(irq
, bfin_demux_error_irq
);
1184 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1186 set_irq_chained_handler(irq
, bfin_demux_mac_status_irq
);
1192 set_irq_handler(irq
, handle_percpu_irq
);
1196 #ifdef CONFIG_TICKSOURCE_CORETMR
1199 set_irq_handler(irq
, handle_percpu_irq
);
1202 set_irq_handler(irq
, handle_simple_irq
);
1207 #ifdef CONFIG_TICKSOURCE_GPTMR0
1209 set_irq_handler(irq
, handle_simple_irq
);
1215 set_irq_handler(irq
, handle_level_irq
);
1217 #else /* !CONFIG_IPIPE */
1219 set_irq_handler(irq
, handle_simple_irq
);
1221 #endif /* !CONFIG_IPIPE */
1225 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1226 for (irq
= IRQ_PPI_ERROR
; irq
<= IRQ_UART1_ERROR
; irq
++)
1227 set_irq_chip_and_handler(irq
, &bfin_generic_error_irqchip
,
1229 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1230 set_irq_chained_handler(IRQ_MAC_ERROR
, bfin_demux_mac_status_irq
);
1234 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1235 for (irq
= IRQ_MAC_PHYINT
; irq
<= IRQ_MAC_STMDONE
; irq
++)
1236 set_irq_chip_and_handler(irq
, &bfin_mac_status_irqchip
,
1239 /* if configured as edge, then will be changed to do_edge_IRQ */
1240 for (irq
= GPIO_IRQ_BASE
;
1241 irq
< (GPIO_IRQ_BASE
+ MAX_BLACKFIN_GPIOS
); irq
++)
1242 set_irq_chip_and_handler(irq
, &bfin_gpio_irqchip
,
1245 bfin_write_IMASK(0);
1247 ilat
= bfin_read_ILAT();
1249 bfin_write_ILAT(ilat
);
1252 printk(KERN_INFO
"Configuring Blackfin Priority Driven Interrupts\n");
1253 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1254 * local_irq_enable()
1257 /* Therefore it's better to setup IARs before interrupts enabled */
1260 /* Enable interrupts IVG7-15 */
1261 bfin_irq_flags
|= IMASK_IVG15
|
1262 IMASK_IVG14
| IMASK_IVG13
| IMASK_IVG12
| IMASK_IVG11
|
1263 IMASK_IVG10
| IMASK_IVG9
| IMASK_IVG8
| IMASK_IVG7
| IMASK_IVGHW
;
1265 /* This implicitly covers ANOMALY_05000171
1266 * Boot-ROM code modifies SICA_IWRx wakeup registers
1269 bfin_write_SIC_IWR0(IWR_DISABLE_ALL
);
1271 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1272 * will screw up the bootrom as it relies on MDMA0/1 waking it
1273 * up from IDLE instructions. See this report for more info:
1274 * http://blackfin.uclinux.org/gf/tracker/4323
1276 if (ANOMALY_05000435
)
1277 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1279 bfin_write_SIC_IWR1(IWR_DISABLE_ALL
);
1282 bfin_write_SIC_IWR2(IWR_DISABLE_ALL
);
1285 bfin_write_SIC_IWR(IWR_DISABLE_ALL
);
1291 #ifdef CONFIG_DO_IRQ_L1
1292 __attribute__((l1_text
))
1294 void do_irq(int vec
, struct pt_regs
*fp
)
1296 if (vec
== EVT_IVTMR_P
) {
1299 struct ivgx
*ivg
= ivg7_13
[vec
- IVG7
].ifirst
;
1300 struct ivgx
*ivg_stop
= ivg7_13
[vec
- IVG7
].istop
;
1301 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1302 unsigned long sic_status
[3];
1304 if (smp_processor_id()) {
1306 /* This will be optimized out in UP mode. */
1307 sic_status
[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1308 sic_status
[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1311 sic_status
[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1312 sic_status
[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1315 sic_status
[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1318 if (ivg
>= ivg_stop
) {
1319 atomic_inc(&num_spurious
);
1322 if (sic_status
[(ivg
->irqno
- IVG7
) / 32] & ivg
->isrflag
)
1326 unsigned long sic_status
;
1328 sic_status
= bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1331 if (ivg
>= ivg_stop
) {
1332 atomic_inc(&num_spurious
);
1334 } else if (sic_status
& ivg
->isrflag
)
1340 asm_do_IRQ(vec
, fp
);
1345 int __ipipe_get_irq_priority(unsigned irq
)
1349 if (irq
<= IRQ_CORETMR
)
1352 for (ient
= 0; ient
< NR_PERI_INTS
; ient
++) {
1353 struct ivgx
*ivg
= ivg_table
+ ient
;
1354 if (ivg
->irqno
== irq
) {
1355 for (prio
= 0; prio
<= IVG13
-IVG7
; prio
++) {
1356 if (ivg7_13
[prio
].ifirst
<= ivg
&&
1357 ivg7_13
[prio
].istop
> ivg
)
1366 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1367 #ifdef CONFIG_DO_IRQ_L1
1368 __attribute__((l1_text
))
1370 asmlinkage
int __ipipe_grab_irq(int vec
, struct pt_regs
*regs
)
1372 struct ipipe_percpu_domain_data
*p
= ipipe_root_cpudom_ptr();
1373 struct ipipe_domain
*this_domain
= __ipipe_current_domain
;
1374 struct ivgx
*ivg_stop
= ivg7_13
[vec
-IVG7
].istop
;
1375 struct ivgx
*ivg
= ivg7_13
[vec
-IVG7
].ifirst
;
1378 if (likely(vec
== EVT_IVTMR_P
))
1381 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1382 unsigned long sic_status
[3];
1384 sic_status
[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1385 sic_status
[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1387 sic_status
[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1390 if (ivg
>= ivg_stop
) {
1391 atomic_inc(&num_spurious
);
1394 if (sic_status
[(ivg
->irqno
- IVG7
) / 32] & ivg
->isrflag
)
1398 unsigned long sic_status
;
1400 sic_status
= bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1403 if (ivg
>= ivg_stop
) {
1404 atomic_inc(&num_spurious
);
1406 } else if (sic_status
& ivg
->isrflag
)
1413 if (irq
== IRQ_SYSTMR
) {
1414 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1415 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1417 /* This is basically what we need from the register frame. */
1418 __raw_get_cpu_var(__ipipe_tick_regs
).ipend
= regs
->ipend
;
1419 __raw_get_cpu_var(__ipipe_tick_regs
).pc
= regs
->pc
;
1420 if (this_domain
!= ipipe_root_domain
)
1421 __raw_get_cpu_var(__ipipe_tick_regs
).ipend
&= ~0x10;
1423 __raw_get_cpu_var(__ipipe_tick_regs
).ipend
|= 0x10;
1426 if (this_domain
== ipipe_root_domain
) {
1427 s
= __test_and_set_bit(IPIPE_SYNCDEFER_FLAG
, &p
->status
);
1431 ipipe_trace_irq_entry(irq
);
1432 __ipipe_handle_irq(irq
, regs
);
1433 ipipe_trace_irq_exit(irq
);
1435 if (this_domain
== ipipe_root_domain
) {
1436 set_thread_flag(TIF_IRQ_SYNC
);
1438 __clear_bit(IPIPE_SYNCDEFER_FLAG
, &p
->status
);
1439 return !test_bit(IPIPE_STALL_FLAG
, &p
->status
);
1446 #endif /* CONFIG_IPIPE */