| commit | 44eeab67416711db9b84610ef18c99a60415dff8 | |
| author | Ralf Baechle <ralf@linux-mips.org> | |
| Fri, 19 Jun 2009 14:01:44 +0000 (19 15:01 +0100) | ||
| committer | Ralf Baechle <ralf@linux-mips.org> | |
| Wed, 24 Jun 2009 17:34:39 +0000 (24 18:34 +0100) | ||
| tree | e9beb9000be5cd9c17bbb7bc05cd3db1c4cb3f09 | treesnapshot (tar.gz zip) |
| parent | 631330f5847b3f8a7ea67d689e9f7c56833ccaa6 | commitdiff |
MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled. A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled. A local
flush is not needed either because we didn't change any mappings. So
just delete the code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled. A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled. A local
flush is not needed either because we didn't change any mappings. So
just delete the code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| arch/mips/power/hibernate.S | diffblobblamehistory |