arch/powerpc/platforms/85xx/mpc85xx_cds.c

   1 /*
   2  * MPC85xx setup and early boot code plus other random bits.
   3  *
   4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5  *
   6  * Copyright 2005 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/major.h>
  22 #include <linux/console.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/initrd.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/fsl_devices.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/page.h>
  33 #include <asm/atomic.h>
  34 #include <asm/time.h>
  35 #include <asm/io.h>
  36 #include <asm/machdep.h>
  37 #include <asm/ipic.h>
  38 #include <asm/pci-bridge.h>
  39 #include <asm/mpc85xx.h>
  40 #include <asm/irq.h>
  41 #include <mm/mmu_decl.h>
  42 #include <asm/prom.h>
  43 #include <asm/udbg.h>
  44 #include <asm/mpic.h>
  45 #include <asm/i8259.h>
  46
  47 #include <sysdev/fsl_soc.h>
  48 #include <sysdev/fsl_pci.h>
  49 #include "mpc85xx.h"
  50
  51 static int cds_pci_slot = 2;
  52 static volatile u8 *cadmus;
  53
  54 #ifdef CONFIG_PCI
  55
  56 #define ARCADIA_HOST_BRIDGE_IDSEL       17
  57 #define ARCADIA_2ND_BRIDGE_IDSEL        3
  58
  59 static int mpc85xx_exclude_device(struct pci_controller *hose,
  60                                   u_char bus, u_char devfn)
  61 {
  62         /* We explicitly do not go past the Tundra 320 Bridge */
  63         if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  64                 return PCIBIOS_DEVICE_NOT_FOUND;
  65         if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  66                 return PCIBIOS_DEVICE_NOT_FOUND;
  67         else
  68                 return PCIBIOS_SUCCESSFUL;
  69 }
  70
  71 static void mpc85xx_cds_restart(char *cmd)
  72 {
  73         struct pci_dev *dev;
  74         u_char tmp;
  75
  76         if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
  77                                         NULL))) {
  78
  79                 /* Use the VIA Super Southbridge to force a PCI reset */
  80                 pci_read_config_byte(dev, 0x47, &tmp);
  81                 pci_write_config_byte(dev, 0x47, tmp | 1);
  82
  83                 /* Flush the outbound PCI write queues */
  84                 pci_read_config_byte(dev, 0x47, &tmp);
  85
  86                 /*
  87                  *  At this point, the harware reset should have triggered.
  88                  *  However, if it doesn't work for some mysterious reason,
  89                  *  just fall through to the default reset below.
  90                  */
  91
  92                 pci_dev_put(dev);
  93         }
  94
  95         /*
  96          *  If we can't find the VIA chip (maybe the P2P bridge is disabled)
  97          *  or the VIA chip reset didn't work, just use the default reset.
  98          */
  99         mpc85xx_restart(NULL);
 100 }
 101
 102 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
 103 {
 104         u_char c;
 105         if (dev->vendor == PCI_VENDOR_ID_VIA) {
 106                 switch (dev->device) {
 107                 case PCI_DEVICE_ID_VIA_82C586_1:
 108                         /*
 109                          * U-Boot does not set the enable bits
 110                          * for the IDE device. Force them on here.
 111                          */
 112                         pci_read_config_byte(dev, 0x40, &c);
 113                         c |= 0x03; /* IDE: Chip Enable Bits */
 114                         pci_write_config_byte(dev, 0x40, c);
 115
 116                         /*
 117                          * Since only primary interface works, force the
 118                          * IDE function to standard primary IDE interrupt
 119                          * w/ 8259 offset
 120                          */
 121                         dev->irq = 14;
 122                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 123                         break;
 124                 /*
 125                  * Force legacy USB interrupt routing
 126                  */
 127                 case PCI_DEVICE_ID_VIA_82C586_2:
 128                 /* There are two USB controllers.
 129                  * Identify them by functon number
 130                  */
 131                         if (PCI_FUNC(dev->devfn) == 3)
 132                                 dev->irq = 11;
 133                         else
 134                                 dev->irq = 10;
 135                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 136                 default:
 137                         break;
 138                 }
 139         }
 140 }
 141
 142 static void __devinit skip_fake_bridge(struct pci_dev *dev)
 143 {
 144         /* Make it an error to skip the fake bridge
 145          * in pci_setup_device() in probe.c */
 146         dev->hdr_type = 0x7f;
 147 }
 148 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
 149 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
 150 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
 151
 152 #ifdef CONFIG_PPC_I8259
 153 static void mpc85xx_8259_cascade_handler(unsigned int irq,
 154                                          struct irq_desc *desc)
 155 {
 156         unsigned int cascade_irq = i8259_irq();
 157
 158         if (cascade_irq != NO_IRQ)
 159                 /* handle an interrupt from the 8259 */
 160                 generic_handle_irq(cascade_irq);
 161
 162         /* check for any interrupts from the shared IRQ line */
 163         handle_fasteoi_irq(irq, desc);
 164 }
 165
 166 static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
 167 {
 168         return IRQ_HANDLED;
 169 }
 170
 171 static struct irqaction mpc85xxcds_8259_irqaction = {
 172         .handler = mpc85xx_8259_cascade_action,
 173         .flags = IRQF_SHARED,
 174         .mask = CPU_MASK_NONE,
 175         .name = "8259 cascade",
 176 };
 177 #endif /* PPC_I8259 */
 178 #endif /* CONFIG_PCI */
 179
 180 static void __init mpc85xx_cds_pic_init(void)
 181 {
 182         struct mpic *mpic;
 183         struct resource r;
 184         struct device_node *np = NULL;
 185
 186         np = of_find_node_by_type(np, "open-pic");
 187
 188         if (np == NULL) {
 189                 printk(KERN_ERR "Could not find open-pic node\n");
 190                 return;
 191         }
 192
 193         if (of_address_to_resource(np, 0, &r)) {
 194                 printk(KERN_ERR "Failed to map mpic register space\n");
 195                 of_node_put(np);
 196                 return;
 197         }
 198
 199         mpic = mpic_alloc(np, r.start,
 200                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 201                         0, 256, " OpenPIC  ");
 202         BUG_ON(mpic == NULL);
 203
 204         /* Return the mpic node */
 205         of_node_put(np);
 206
 207         mpic_init(mpic);
 208 }
 209
 210 #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
 211 static int mpc85xx_cds_8259_attach(void)
 212 {
 213         int ret;
 214         struct device_node *np = NULL;
 215         struct device_node *cascade_node = NULL;
 216         int cascade_irq;
 217
 218         if (!machine_is(mpc85xx_cds))
 219                 return 0;
 220
 221         /* Initialize the i8259 controller */
 222         for_each_node_by_type(np, "interrupt-controller")
 223                 if (of_device_is_compatible(np, "chrp,iic")) {
 224                         cascade_node = np;
 225                         break;
 226                 }
 227
 228         if (cascade_node == NULL) {
 229                 printk(KERN_DEBUG "Could not find i8259 PIC\n");
 230                 return -ENODEV;
 231         }
 232
 233         cascade_irq = irq_of_parse_and_map(cascade_node, 0);
 234         if (cascade_irq == NO_IRQ) {
 235                 printk(KERN_ERR "Failed to map cascade interrupt\n");
 236                 return -ENXIO;
 237         }
 238
 239         i8259_init(cascade_node, 0);
 240         of_node_put(cascade_node);
 241
 242         /*
 243          *  Hook the interrupt to make sure desc->action is never NULL.
 244          *  This is required to ensure that the interrupt does not get
 245          *  disabled when the last user of the shared IRQ line frees their
 246          *  interrupt.
 247          */
 248         if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
 249                 printk(KERN_ERR "Failed to setup cascade interrupt\n");
 250                 return ret;
 251         }
 252
 253         /* Success. Connect our low-level cascade handler. */
 254         set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler);
 255
 256         return 0;
 257 }
 258
 259 device_initcall(mpc85xx_cds_8259_attach);
 260
 261 #endif /* CONFIG_PPC_I8259 */
 262
 263 /*
 264  * Setup the architecture
 265  */
 266 static void __init mpc85xx_cds_setup_arch(void)
 267 {
 268 #ifdef CONFIG_PCI
 269         struct device_node *np;
 270 #endif
 271
 272         if (ppc_md.progress)
 273                 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
 274
 275         cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
 276         cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
 277
 278         if (ppc_md.progress) {
 279                 char buf[40];
 280                 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
 281                                 cadmus[CM_VER], cds_pci_slot);
 282                 ppc_md.progress(buf, 0);
 283         }
 284
 285 #ifdef CONFIG_PCI
 286         for_each_node_by_type(np, "pci") {
 287                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 288                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
 289                         struct resource rsrc;
 290                         of_address_to_resource(np, 0, &rsrc);
 291                         if ((rsrc.start & 0xfffff) == 0x8000)
 292                                 fsl_add_bridge(np, 1);
 293                         else
 294                                 fsl_add_bridge(np, 0);
 295                 }
 296         }
 297
 298         ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
 299         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 300 #endif
 301 }
 302
 303 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
 304 {
 305         uint pvid, svid, phid1;
 306         uint memsize = total_memory;
 307
 308         pvid = mfspr(SPRN_PVR);
 309         svid = mfspr(SPRN_SVR);
 310
 311         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 312         seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
 313         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 314         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 315
 316         /* Display cpu Pll setting */
 317         phid1 = mfspr(SPRN_HID1);
 318         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 319
 320         /* Display the amount of memory */
 321         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 322 }
 323
 324
 325 /*
 326  * Called very early, device-tree isn't unflattened
 327  */
 328 static int __init mpc85xx_cds_probe(void)
 329 {
 330         unsigned long root = of_get_flat_dt_root();
 331
 332         return of_flat_dt_is_compatible(root, "MPC85xxCDS");
 333 }
 334
 335 define_machine(mpc85xx_cds) {
 336         .name           = "MPC85xx CDS",
 337         .probe          = mpc85xx_cds_probe,
 338         .setup_arch     = mpc85xx_cds_setup_arch,
 339         .init_IRQ       = mpc85xx_cds_pic_init,
 340         .show_cpuinfo   = mpc85xx_cds_show_cpuinfo,
 341         .get_irq        = mpic_get_irq,
 342 #ifdef CONFIG_PCI
 343         .restart        = mpc85xx_cds_restart,
 344         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 345 #else
 346         .restart        = mpc85xx_restart,
 347 #endif
 348         .calibrate_decr = generic_calibrate_decr,
 349         .progress       = udbg_progress,
 350 };