include/asm-arm/cacheflush.h

   1 /*
   2  *  linux/include/asm-arm/cacheflush.h
   3  *
   4  *  Copyright (C) 1999-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASMARM_CACHEFLUSH_H
  11 #define _ASMARM_CACHEFLUSH_H
  12
  13 #include <linux/sched.h>
  14 #include <linux/mm.h>
  15
  16 #include <asm/glue.h>
  17 #include <asm/shmparam.h>
  18
  19 #define CACHE_COLOUR(vaddr)     ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
  20
  21 /*
  22  *      Cache Model
  23  *      ===========
  24  */
  25 #undef _CACHE
  26 #undef MULTI_CACHE
  27
  28 #if defined(CONFIG_CPU_CACHE_V3)
  29 # ifdef _CACHE
  30 #  define MULTI_CACHE 1
  31 # else
  32 #  define _CACHE v3
  33 # endif
  34 #endif
  35
  36 #if defined(CONFIG_CPU_CACHE_V4)
  37 # ifdef _CACHE
  38 #  define MULTI_CACHE 1
  39 # else
  40 #  define _CACHE v4
  41 # endif
  42 #endif
  43
  44 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
  45     defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
  46 # define MULTI_CACHE 1
  47 #endif
  48
  49 #if defined(CONFIG_CPU_ARM926T)
  50 # ifdef _CACHE
  51 #  define MULTI_CACHE 1
  52 # else
  53 #  define _CACHE arm926
  54 # endif
  55 #endif
  56
  57 #if defined(CONFIG_CPU_ARM940T)
  58 # ifdef _CACHE
  59 #  define MULTI_CACHE 1
  60 # else
  61 #  define _CACHE arm940
  62 # endif
  63 #endif
  64
  65 #if defined(CONFIG_CPU_ARM946E)
  66 # ifdef _CACHE
  67 #  define MULTI_CACHE 1
  68 # else
  69 #  define _CACHE arm946
  70 # endif
  71 #endif
  72
  73 #if defined(CONFIG_CPU_CACHE_V4WB)
  74 # ifdef _CACHE
  75 #  define MULTI_CACHE 1
  76 # else
  77 #  define _CACHE v4wb
  78 # endif
  79 #endif
  80
  81 #if defined(CONFIG_CPU_XSCALE)
  82 # ifdef _CACHE
  83 #  define MULTI_CACHE 1
  84 # else
  85 #  define _CACHE xscale
  86 # endif
  87 #endif
  88
  89 #if defined(CONFIG_CPU_XSC3)
  90 # ifdef _CACHE
  91 #  define MULTI_CACHE 1
  92 # else
  93 #  define _CACHE xsc3
  94 # endif
  95 #endif
  96
  97 #if defined(CONFIG_CPU_V6)
  98 //# ifdef _CACHE
  99 #  define MULTI_CACHE 1
 100 //# else
 101 //#  define _CACHE v6
 102 //# endif
 103 #endif
 104
 105 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 106 #error Unknown cache maintainence model
 107 #endif
 108
 109 /*
 110  * This flag is used to indicate that the page pointed to by a pte
 111  * is dirty and requires cleaning before returning it to the user.
 112  */
 113 #define PG_dcache_dirty PG_arch_1
 114
 115 /*
 116  *      MM Cache Management
 117  *      ===================
 118  *
 119  *      The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
 120  *      implement these methods.
 121  *
 122  *      Start addresses are inclusive and end addresses are exclusive;
 123  *      start addresses should be rounded down, end addresses up.
 124  *
 125  *      See Documentation/cachetlb.txt for more information.
 126  *      Please note that the implementation of these, and the required
 127  *      effects are cache-type (VIVT/VIPT/PIPT) specific.
 128  *
 129  *      flush_cache_kern_all()
 130  *
 131  *              Unconditionally clean and invalidate the entire cache.
 132  *
 133  *      flush_cache_user_mm(mm)
 134  *
 135  *              Clean and invalidate all user space cache entries
 136  *              before a change of page tables.
 137  *
 138  *      flush_cache_user_range(start, end, flags)
 139  *
 140  *              Clean and invalidate a range of cache entries in the
 141  *              specified address space before a change of page tables.
 142  *              - start - user start address (inclusive, page aligned)
 143  *              - end   - user end address   (exclusive, page aligned)
 144  *              - flags - vma->vm_flags field
 145  *
 146  *      coherent_kern_range(start, end)
 147  *
 148  *              Ensure coherency between the Icache and the Dcache in the
 149  *              region described by start, end.  If you have non-snooping
 150  *              Harvard caches, you need to implement this function.
 151  *              - start  - virtual start address
 152  *              - end    - virtual end address
 153  *
 154  *      DMA Cache Coherency
 155  *      ===================
 156  *
 157  *      dma_inv_range(start, end)
 158  *
 159  *              Invalidate (discard) the specified virtual address range.
 160  *              May not write back any entries.  If 'start' or 'end'
 161  *              are not cache line aligned, those lines must be written
 162  *              back.
 163  *              - start  - virtual start address
 164  *              - end    - virtual end address
 165  *
 166  *      dma_clean_range(start, end)
 167  *
 168  *              Clean (write back) the specified virtual address range.
 169  *              - start  - virtual start address
 170  *              - end    - virtual end address
 171  *
 172  *      dma_flush_range(start, end)
 173  *
 174  *              Clean and invalidate the specified virtual address range.
 175  *              - start  - virtual start address
 176  *              - end    - virtual end address
 177  */
 178
 179 struct cpu_cache_fns {
 180         void (*flush_kern_all)(void);
 181         void (*flush_user_all)(void);
 182         void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
 183
 184         void (*coherent_kern_range)(unsigned long, unsigned long);
 185         void (*coherent_user_range)(unsigned long, unsigned long);
 186         void (*flush_kern_dcache_page)(void *);
 187
 188         void (*dma_inv_range)(unsigned long, unsigned long);
 189         void (*dma_clean_range)(unsigned long, unsigned long);
 190         void (*dma_flush_range)(unsigned long, unsigned long);
 191 };
 192
 193 /*
 194  * Select the calling method
 195  */
 196 #ifdef MULTI_CACHE
 197
 198 extern struct cpu_cache_fns cpu_cache;
 199
 200 #define __cpuc_flush_kern_all           cpu_cache.flush_kern_all
 201 #define __cpuc_flush_user_all           cpu_cache.flush_user_all
 202 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
 203 #define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
 204 #define __cpuc_coherent_user_range      cpu_cache.coherent_user_range
 205 #define __cpuc_flush_dcache_page        cpu_cache.flush_kern_dcache_page
 206
 207 /*
 208  * These are private to the dma-mapping API.  Do not use directly.
 209  * Their sole purpose is to ensure that data held in the cache
 210  * is visible to DMA, or data written by DMA to system memory is
 211  * visible to the CPU.
 212  */
 213 #define dmac_inv_range                  cpu_cache.dma_inv_range
 214 #define dmac_clean_range                cpu_cache.dma_clean_range
 215 #define dmac_flush_range                cpu_cache.dma_flush_range
 216
 217 #else
 218
 219 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
 220 #define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
 221 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
 222 #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
 223 #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
 224 #define __cpuc_flush_dcache_page        __glue(_CACHE,_flush_kern_dcache_page)
 225
 226 extern void __cpuc_flush_kern_all(void);
 227 extern void __cpuc_flush_user_all(void);
 228 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 229 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
 230 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
 231 extern void __cpuc_flush_dcache_page(void *);
 232
 233 /*
 234  * These are private to the dma-mapping API.  Do not use directly.
 235  * Their sole purpose is to ensure that data held in the cache
 236  * is visible to DMA, or data written by DMA to system memory is
 237  * visible to the CPU.
 238  */
 239 #define dmac_inv_range                  __glue(_CACHE,_dma_inv_range)
 240 #define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
 241 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 242
 243 extern void dmac_inv_range(unsigned long, unsigned long);
 244 extern void dmac_clean_range(unsigned long, unsigned long);
 245 extern void dmac_flush_range(unsigned long, unsigned long);
 246
 247 #endif
 248
 249 /*
 250  * flush_cache_vmap() is used when creating mappings (eg, via vmap,
 251  * vmalloc, ioremap etc) in kernel space for pages.  Since the
 252  * direct-mappings of these pages may contain cached data, we need
 253  * to do a full cache flush to ensure that writebacks don't corrupt
 254  * data placed into these pages via the new mappings.
 255  */
 256 #define flush_cache_vmap(start, end)            flush_cache_all()
 257 #define flush_cache_vunmap(start, end)          flush_cache_all()
 258
 259 /*
 260  * Copy user data from/to a page which is mapped into a different
 261  * processes address space.  Really, we want to allow our "user
 262  * space" model to handle this.
 263  */
 264 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
 265         do {                                                    \
 266                 memcpy(dst, src, len);                          \
 267                 flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
 268         } while (0)
 269
 270 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 271         do {                                                    \
 272                 memcpy(dst, src, len);                          \
 273         } while (0)
 274
 275 /*
 276  * Convert calls to our calling convention.
 277  */
 278 #define flush_cache_all()               __cpuc_flush_kern_all()
 279 #ifndef CONFIG_CPU_CACHE_VIPT
 280 static inline void flush_cache_mm(struct mm_struct *mm)
 281 {
 282         if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
 283                 __cpuc_flush_user_all();
 284 }
 285
 286 static inline void
 287 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 288 {
 289         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
 290                 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
 291                                         vma->vm_flags);
 292 }
 293
 294 static inline void
 295 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
 296 {
 297         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
 298                 unsigned long addr = user_addr & PAGE_MASK;
 299                 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
 300         }
 301 }
 302
 303 static inline void
 304 flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 305                          unsigned long uaddr, void *kaddr,
 306                          unsigned long len, int write)
 307 {
 308         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
 309                 unsigned long addr = (unsigned long)kaddr;
 310                 __cpuc_coherent_kern_range(addr, addr + len);
 311         }
 312 }
 313 #else
 314 extern void flush_cache_mm(struct mm_struct *mm);
 315 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 316 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
 317 extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 318                                 unsigned long uaddr, void *kaddr,
 319                                 unsigned long len, int write);
 320 #endif
 321
 322 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
 323
 324 /*
 325  * flush_cache_user_range is used when we want to ensure that the
 326  * Harvard caches are synchronised for the user space address range.
 327  * This is used for the ARM private sys_cacheflush system call.
 328  */
 329 #define flush_cache_user_range(vma,start,end) \
 330         __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
 331
 332 /*
 333  * Perform necessary cache operations to ensure that data previously
 334  * stored within this range of addresses can be executed by the CPU.
 335  */
 336 #define flush_icache_range(s,e)         __cpuc_coherent_kern_range(s,e)
 337
 338 /*
 339  * Perform necessary cache operations to ensure that the TLB will
 340  * see data written in the specified area.
 341  */
 342 #define clean_dcache_area(start,size)   cpu_dcache_clean_area(start, size)
 343
 344 /*
 345  * flush_dcache_page is used when the kernel has written to the page
 346  * cache page at virtual address page->virtual.
 347  *
 348  * If this page isn't mapped (ie, page_mapping == NULL), or it might
 349  * have userspace mappings, then we _must_ always clean + invalidate
 350  * the dcache entries associated with the kernel mapping.
 351  *
 352  * Otherwise we can defer the operation, and clean the cache when we are
 353  * about to change to user space.  This is the same method as used on SPARC64.
 354  * See update_mmu_cache for the user space part.
 355  */
 356 extern void flush_dcache_page(struct page *);
 357
 358 extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
 359
 360 #define ARCH_HAS_FLUSH_ANON_PAGE
 361 static inline void flush_anon_page(struct vm_area_struct *vma,
 362                          struct page *page, unsigned long vmaddr)
 363 {
 364         extern void __flush_anon_page(struct vm_area_struct *vma,
 365                                 struct page *, unsigned long);
 366         if (PageAnon(page))
 367                 __flush_anon_page(vma, page, vmaddr);
 368 }
 369
 370 #define flush_dcache_mmap_lock(mapping) \
 371         write_lock_irq(&(mapping)->tree_lock)
 372 #define flush_dcache_mmap_unlock(mapping) \
 373         write_unlock_irq(&(mapping)->tree_lock)
 374
 375 #define flush_icache_user_range(vma,page,addr,len) \
 376         flush_dcache_page(page)
 377
 378 /*
 379  * We don't appear to need to do anything here.  In fact, if we did, we'd
 380  * duplicate cache flushing elsewhere performed by flush_dcache_page().
 381  */
 382 #define flush_icache_page(vma,page)     do { } while (0)
 383
 384 #define __cacheid_present(val)          (val != read_cpuid(CPUID_ID))
 385 #define __cacheid_vivt(val)             ((val & (15 << 25)) != (14 << 25))
 386 #define __cacheid_vipt(val)             ((val & (15 << 25)) == (14 << 25))
 387 #define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
 388 #define __cacheid_vipt_aliasing(val)    ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
 389
 390 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
 391
 392 #define cache_is_vivt()                 1
 393 #define cache_is_vipt()                 0
 394 #define cache_is_vipt_nonaliasing()     0
 395 #define cache_is_vipt_aliasing()        0
 396
 397 #elif defined(CONFIG_CPU_CACHE_VIPT)
 398
 399 #define cache_is_vivt()                 0
 400 #define cache_is_vipt()                 1
 401 #define cache_is_vipt_nonaliasing()                                     \
 402         ({                                                              \
 403                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 404                 __cacheid_vipt_nonaliasing(__val);                      \
 405         })
 406
 407 #define cache_is_vipt_aliasing()                                        \
 408         ({                                                              \
 409                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 410                 __cacheid_vipt_aliasing(__val);                         \
 411         })
 412
 413 #else
 414
 415 #define cache_is_vivt()                                                 \
 416         ({                                                              \
 417                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 418                 (!__cacheid_present(__val)) || __cacheid_vivt(__val);   \
 419         })
 420
 421 #define cache_is_vipt()                                                 \
 422         ({                                                              \
 423                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 424                 __cacheid_present(__val) && __cacheid_vipt(__val);      \
 425         })
 426
 427 #define cache_is_vipt_nonaliasing()                                     \
 428         ({                                                              \
 429                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 430                 __cacheid_present(__val) &&                             \
 431                  __cacheid_vipt_nonaliasing(__val);                     \
 432         })
 433
 434 #define cache_is_vipt_aliasing()                                        \
 435         ({                                                              \
 436                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 437                 __cacheid_present(__val) &&                             \
 438                  __cacheid_vipt_aliasing(__val);                        \
 439         })
 440
 441 #endif
 442
 443 #endif