2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.03"
53 PDC_PKT_SUBMIT
= 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK
= 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE
= 0x41, /* TBG mode */
56 PDC_FLASH_CTL
= 0x44, /* Flash control register */
57 PDC_PCI_CTL
= 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL
= 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT
= 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR
= 0x6C, /* SATA Plug control/status reg */
61 PDC_SLEW_CTL
= 0x470, /* slew rate control reg */
63 PDC_ERR_MASK
= (1<<19) | (1<<20) | (1<<21) | (1<<22) |
64 (1<<8) | (1<<9) | (1<<10),
66 board_2037x
= 0, /* FastTrak S150 TX2plus */
67 board_20319
= 1, /* FastTrak S150 TX4 */
68 board_20619
= 2, /* FastTrak TX4000 */
70 PDC_HAS_PATA
= (1 << 1), /* PDC20375 has PATA */
72 PDC_RESET
= (1 << 11), /* HDMA reset */
74 PDC_COMMON_FLAGS
= ATA_FLAG_NO_LEGACY
| ATA_FLAG_SRST
|
75 ATA_FLAG_MMIO
| ATA_FLAG_NO_ATAPI
,
79 struct pdc_port_priv
{
84 static u32
pdc_sata_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
85 static void pdc_sata_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
86 static int pdc_ata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
87 static irqreturn_t
pdc_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
88 static void pdc_eng_timeout(struct ata_port
*ap
);
89 static int pdc_port_start(struct ata_port
*ap
);
90 static void pdc_port_stop(struct ata_port
*ap
);
91 static void pdc_pata_phy_reset(struct ata_port
*ap
);
92 static void pdc_sata_phy_reset(struct ata_port
*ap
);
93 static void pdc_qc_prep(struct ata_queued_cmd
*qc
);
94 static void pdc_tf_load_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
);
95 static void pdc_exec_command_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
);
96 static void pdc_irq_clear(struct ata_port
*ap
);
97 static int pdc_qc_issue_prot(struct ata_queued_cmd
*qc
);
100 static struct scsi_host_template pdc_ata_sht
= {
101 .module
= THIS_MODULE
,
103 .ioctl
= ata_scsi_ioctl
,
104 .queuecommand
= ata_scsi_queuecmd
,
105 .eh_strategy_handler
= ata_scsi_error
,
106 .can_queue
= ATA_DEF_QUEUE
,
107 .this_id
= ATA_SHT_THIS_ID
,
108 .sg_tablesize
= LIBATA_MAX_PRD
,
109 .max_sectors
= ATA_MAX_SECTORS
,
110 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
111 .emulated
= ATA_SHT_EMULATED
,
112 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
113 .proc_name
= DRV_NAME
,
114 .dma_boundary
= ATA_DMA_BOUNDARY
,
115 .slave_configure
= ata_scsi_slave_config
,
116 .bios_param
= ata_std_bios_param
,
119 static const struct ata_port_operations pdc_sata_ops
= {
120 .port_disable
= ata_port_disable
,
121 .tf_load
= pdc_tf_load_mmio
,
122 .tf_read
= ata_tf_read
,
123 .check_status
= ata_check_status
,
124 .exec_command
= pdc_exec_command_mmio
,
125 .dev_select
= ata_std_dev_select
,
127 .phy_reset
= pdc_sata_phy_reset
,
129 .qc_prep
= pdc_qc_prep
,
130 .qc_issue
= pdc_qc_issue_prot
,
131 .eng_timeout
= pdc_eng_timeout
,
132 .irq_handler
= pdc_interrupt
,
133 .irq_clear
= pdc_irq_clear
,
135 .scr_read
= pdc_sata_scr_read
,
136 .scr_write
= pdc_sata_scr_write
,
137 .port_start
= pdc_port_start
,
138 .port_stop
= pdc_port_stop
,
139 .host_stop
= ata_pci_host_stop
,
142 static const struct ata_port_operations pdc_pata_ops
= {
143 .port_disable
= ata_port_disable
,
144 .tf_load
= pdc_tf_load_mmio
,
145 .tf_read
= ata_tf_read
,
146 .check_status
= ata_check_status
,
147 .exec_command
= pdc_exec_command_mmio
,
148 .dev_select
= ata_std_dev_select
,
150 .phy_reset
= pdc_pata_phy_reset
,
152 .qc_prep
= pdc_qc_prep
,
153 .qc_issue
= pdc_qc_issue_prot
,
154 .eng_timeout
= pdc_eng_timeout
,
155 .irq_handler
= pdc_interrupt
,
156 .irq_clear
= pdc_irq_clear
,
158 .port_start
= pdc_port_start
,
159 .port_stop
= pdc_port_stop
,
160 .host_stop
= ata_pci_host_stop
,
163 static const struct ata_port_info pdc_port_info
[] = {
167 .host_flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
,
168 .pio_mask
= 0x1f, /* pio0-4 */
169 .mwdma_mask
= 0x07, /* mwdma0-2 */
170 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
171 .port_ops
= &pdc_sata_ops
,
177 .host_flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
,
178 .pio_mask
= 0x1f, /* pio0-4 */
179 .mwdma_mask
= 0x07, /* mwdma0-2 */
180 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
181 .port_ops
= &pdc_sata_ops
,
187 .host_flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SLAVE_POSS
,
188 .pio_mask
= 0x1f, /* pio0-4 */
189 .mwdma_mask
= 0x07, /* mwdma0-2 */
190 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
191 .port_ops
= &pdc_pata_ops
,
195 static const struct pci_device_id pdc_ata_pci_tbl
[] = {
196 { PCI_VENDOR_ID_PROMISE
, 0x3371, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
198 { PCI_VENDOR_ID_PROMISE
, 0x3570, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
200 { PCI_VENDOR_ID_PROMISE
, 0x3571, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
202 { PCI_VENDOR_ID_PROMISE
, 0x3373, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
204 { PCI_VENDOR_ID_PROMISE
, 0x3375, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
206 { PCI_VENDOR_ID_PROMISE
, 0x3376, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
208 { PCI_VENDOR_ID_PROMISE
, 0x3574, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
210 { PCI_VENDOR_ID_PROMISE
, 0x3d75, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
212 { PCI_VENDOR_ID_PROMISE
, 0x3d73, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
215 { PCI_VENDOR_ID_PROMISE
, 0x3318, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
217 { PCI_VENDOR_ID_PROMISE
, 0x3319, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
219 { PCI_VENDOR_ID_PROMISE
, 0x3519, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
221 { PCI_VENDOR_ID_PROMISE
, 0x3d17, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
223 { PCI_VENDOR_ID_PROMISE
, 0x3d18, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
226 { PCI_VENDOR_ID_PROMISE
, 0x6629, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
229 { } /* terminate list */
233 static struct pci_driver pdc_ata_pci_driver
= {
235 .id_table
= pdc_ata_pci_tbl
,
236 .probe
= pdc_ata_init_one
,
237 .remove
= ata_pci_remove_one
,
241 static int pdc_port_start(struct ata_port
*ap
)
243 struct device
*dev
= ap
->host_set
->dev
;
244 struct pdc_port_priv
*pp
;
247 rc
= ata_port_start(ap
);
251 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
256 memset(pp
, 0, sizeof(*pp
));
258 pp
->pkt
= dma_alloc_coherent(dev
, 128, &pp
->pkt_dma
, GFP_KERNEL
);
264 ap
->private_data
= pp
;
276 static void pdc_port_stop(struct ata_port
*ap
)
278 struct device
*dev
= ap
->host_set
->dev
;
279 struct pdc_port_priv
*pp
= ap
->private_data
;
281 ap
->private_data
= NULL
;
282 dma_free_coherent(dev
, 128, pp
->pkt
, pp
->pkt_dma
);
288 static void pdc_reset_port(struct ata_port
*ap
)
290 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_CTLSTAT
;
294 for (i
= 11; i
> 0; i
--) {
307 readl(mmio
); /* flush */
310 static void pdc_sata_phy_reset(struct ata_port
*ap
)
316 static void pdc_pata_phy_reset(struct ata_port
*ap
)
318 /* FIXME: add cable detect. Don't assume 40-pin cable */
319 ap
->cbl
= ATA_CBL_PATA40
;
320 ap
->udma_mask
&= ATA_UDMA_MASK_40C
;
327 static u32
pdc_sata_scr_read (struct ata_port
*ap
, unsigned int sc_reg
)
329 if (sc_reg
> SCR_CONTROL
)
331 return readl((void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
335 static void pdc_sata_scr_write (struct ata_port
*ap
, unsigned int sc_reg
,
338 if (sc_reg
> SCR_CONTROL
)
340 writel(val
, (void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
343 static void pdc_qc_prep(struct ata_queued_cmd
*qc
)
345 struct pdc_port_priv
*pp
= qc
->ap
->private_data
;
350 switch (qc
->tf
.protocol
) {
355 case ATA_PROT_NODATA
:
356 i
= pdc_pkt_header(&qc
->tf
, qc
->ap
->prd_dma
,
357 qc
->dev
->devno
, pp
->pkt
);
359 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
360 i
= pdc_prep_lba48(&qc
->tf
, pp
->pkt
, i
);
362 i
= pdc_prep_lba28(&qc
->tf
, pp
->pkt
, i
);
364 pdc_pkt_footer(&qc
->tf
, pp
->pkt
, i
);
372 static void pdc_eng_timeout(struct ata_port
*ap
)
374 struct ata_host_set
*host_set
= ap
->host_set
;
376 struct ata_queued_cmd
*qc
;
381 spin_lock_irqsave(&host_set
->lock
, flags
);
383 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
385 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
390 /* hack alert! We cannot use the supplied completion
391 * function from inside the ->eh_strategy_handler() thread.
392 * libata is the only user of ->eh_strategy_handler() in
393 * any kernel, so the default scsi_done() assumes it is
394 * not being called from the SCSI EH.
396 qc
->scsidone
= scsi_finish_command
;
398 switch (qc
->tf
.protocol
) {
400 case ATA_PROT_NODATA
:
401 printk(KERN_ERR
"ata%u: command timeout\n", ap
->id
);
402 drv_stat
= ata_wait_idle(ap
);
403 qc
->err_mask
|= __ac_err_mask(drv_stat
);
408 drv_stat
= ata_busy_wait(ap
, ATA_BUSY
| ATA_DRQ
, 1000);
410 printk(KERN_ERR
"ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
411 ap
->id
, qc
->tf
.command
, drv_stat
);
413 qc
->err_mask
|= ac_err_mask(drv_stat
);
419 spin_unlock_irqrestore(&host_set
->lock
, flags
);
423 static inline unsigned int pdc_host_intr( struct ata_port
*ap
,
424 struct ata_queued_cmd
*qc
)
426 unsigned int handled
= 0;
428 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_GLOBAL_CTL
;
431 if (tmp
& PDC_ERR_MASK
) {
432 qc
->err_mask
|= AC_ERR_DEV
;
436 switch (qc
->tf
.protocol
) {
438 case ATA_PROT_NODATA
:
439 qc
->err_mask
|= ac_err_mask(ata_wait_idle(ap
));
445 ap
->stats
.idle_irq
++;
452 static void pdc_irq_clear(struct ata_port
*ap
)
454 struct ata_host_set
*host_set
= ap
->host_set
;
455 void __iomem
*mmio
= host_set
->mmio_base
;
457 readl(mmio
+ PDC_INT_SEQMASK
);
460 static irqreturn_t
pdc_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
462 struct ata_host_set
*host_set
= dev_instance
;
466 unsigned int handled
= 0;
467 void __iomem
*mmio_base
;
471 if (!host_set
|| !host_set
->mmio_base
) {
472 VPRINTK("QUICK EXIT\n");
476 mmio_base
= host_set
->mmio_base
;
478 /* reading should also clear interrupts */
479 mask
= readl(mmio_base
+ PDC_INT_SEQMASK
);
481 if (mask
== 0xffffffff) {
482 VPRINTK("QUICK EXIT 2\n");
485 mask
&= 0xffff; /* only 16 tags possible */
487 VPRINTK("QUICK EXIT 3\n");
491 spin_lock(&host_set
->lock
);
493 writel(mask
, mmio_base
+ PDC_INT_SEQMASK
);
495 for (i
= 0; i
< host_set
->n_ports
; i
++) {
496 VPRINTK("port %u\n", i
);
497 ap
= host_set
->ports
[i
];
498 tmp
= mask
& (1 << (i
+ 1));
500 !(ap
->flags
& (ATA_FLAG_PORT_DISABLED
| ATA_FLAG_NOINTR
))) {
501 struct ata_queued_cmd
*qc
;
503 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
504 if (qc
&& (!(qc
->tf
.ctl
& ATA_NIEN
)))
505 handled
+= pdc_host_intr(ap
, qc
);
509 spin_unlock(&host_set
->lock
);
513 return IRQ_RETVAL(handled
);
516 static inline void pdc_packet_start(struct ata_queued_cmd
*qc
)
518 struct ata_port
*ap
= qc
->ap
;
519 struct pdc_port_priv
*pp
= ap
->private_data
;
520 unsigned int port_no
= ap
->port_no
;
521 u8 seq
= (u8
) (port_no
+ 1);
523 VPRINTK("ENTER, ap %p\n", ap
);
525 writel(0x00000001, ap
->host_set
->mmio_base
+ (seq
* 4));
526 readl(ap
->host_set
->mmio_base
+ (seq
* 4)); /* flush */
529 wmb(); /* flush PRD, pkt writes */
530 writel(pp
->pkt_dma
, (void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
531 readl((void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
); /* flush */
534 static int pdc_qc_issue_prot(struct ata_queued_cmd
*qc
)
536 switch (qc
->tf
.protocol
) {
538 case ATA_PROT_NODATA
:
539 pdc_packet_start(qc
);
542 case ATA_PROT_ATAPI_DMA
:
550 return ata_qc_issue_prot(qc
);
553 static void pdc_tf_load_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
555 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
556 tf
->protocol
== ATA_PROT_NODATA
);
561 static void pdc_exec_command_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
563 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
564 tf
->protocol
== ATA_PROT_NODATA
);
565 ata_exec_command(ap
, tf
);
569 static void pdc_ata_setup_port(struct ata_ioports
*port
, unsigned long base
)
571 port
->cmd_addr
= base
;
572 port
->data_addr
= base
;
574 port
->error_addr
= base
+ 0x4;
575 port
->nsect_addr
= base
+ 0x8;
576 port
->lbal_addr
= base
+ 0xc;
577 port
->lbam_addr
= base
+ 0x10;
578 port
->lbah_addr
= base
+ 0x14;
579 port
->device_addr
= base
+ 0x18;
581 port
->status_addr
= base
+ 0x1c;
582 port
->altstatus_addr
=
583 port
->ctl_addr
= base
+ 0x38;
587 static void pdc_host_init(unsigned int chip_id
, struct ata_probe_ent
*pe
)
589 void __iomem
*mmio
= pe
->mmio_base
;
593 * Except for the hotplug stuff, this is voodoo from the
594 * Promise driver. Label this entire section
595 * "TODO: figure out why we do this"
598 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
599 tmp
= readl(mmio
+ PDC_FLASH_CTL
);
600 tmp
|= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
601 writel(tmp
, mmio
+ PDC_FLASH_CTL
);
603 /* clear plug/unplug flags for all ports */
604 tmp
= readl(mmio
+ PDC_SATA_PLUG_CSR
);
605 writel(tmp
| 0xff, mmio
+ PDC_SATA_PLUG_CSR
);
607 /* mask plug/unplug ints */
608 tmp
= readl(mmio
+ PDC_SATA_PLUG_CSR
);
609 writel(tmp
| 0xff0000, mmio
+ PDC_SATA_PLUG_CSR
);
611 /* reduce TBG clock to 133 Mhz. */
612 tmp
= readl(mmio
+ PDC_TBG_MODE
);
613 tmp
&= ~0x30000; /* clear bit 17, 16*/
614 tmp
|= 0x10000; /* set bit 17:16 = 0:1 */
615 writel(tmp
, mmio
+ PDC_TBG_MODE
);
617 readl(mmio
+ PDC_TBG_MODE
); /* flush */
620 /* adjust slew rate control register. */
621 tmp
= readl(mmio
+ PDC_SLEW_CTL
);
622 tmp
&= 0xFFFFF03F; /* clear bit 11 ~ 6 */
623 tmp
|= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
624 writel(tmp
, mmio
+ PDC_SLEW_CTL
);
627 static int pdc_ata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
629 static int printed_version
;
630 struct ata_probe_ent
*probe_ent
= NULL
;
632 void __iomem
*mmio_base
;
633 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
634 int pci_dev_busy
= 0;
637 if (!printed_version
++)
638 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
641 * If this driver happens to only be useful on Apple's K2, then
642 * we should check that here as it has a normal Serverworks ID
644 rc
= pci_enable_device(pdev
);
648 rc
= pci_request_regions(pdev
, DRV_NAME
);
654 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
656 goto err_out_regions
;
657 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
659 goto err_out_regions
;
661 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
662 if (probe_ent
== NULL
) {
664 goto err_out_regions
;
667 memset(probe_ent
, 0, sizeof(*probe_ent
));
668 probe_ent
->dev
= pci_dev_to_dev(pdev
);
669 INIT_LIST_HEAD(&probe_ent
->node
);
671 mmio_base
= pci_iomap(pdev
, 3, 0);
672 if (mmio_base
== NULL
) {
674 goto err_out_free_ent
;
676 base
= (unsigned long) mmio_base
;
678 probe_ent
->sht
= pdc_port_info
[board_idx
].sht
;
679 probe_ent
->host_flags
= pdc_port_info
[board_idx
].host_flags
;
680 probe_ent
->pio_mask
= pdc_port_info
[board_idx
].pio_mask
;
681 probe_ent
->mwdma_mask
= pdc_port_info
[board_idx
].mwdma_mask
;
682 probe_ent
->udma_mask
= pdc_port_info
[board_idx
].udma_mask
;
683 probe_ent
->port_ops
= pdc_port_info
[board_idx
].port_ops
;
685 probe_ent
->irq
= pdev
->irq
;
686 probe_ent
->irq_flags
= SA_SHIRQ
;
687 probe_ent
->mmio_base
= mmio_base
;
689 pdc_ata_setup_port(&probe_ent
->port
[0], base
+ 0x200);
690 pdc_ata_setup_port(&probe_ent
->port
[1], base
+ 0x280);
692 probe_ent
->port
[0].scr_addr
= base
+ 0x400;
693 probe_ent
->port
[1].scr_addr
= base
+ 0x500;
695 /* notice 4-port boards */
698 probe_ent
->n_ports
= 4;
700 pdc_ata_setup_port(&probe_ent
->port
[2], base
+ 0x300);
701 pdc_ata_setup_port(&probe_ent
->port
[3], base
+ 0x380);
703 probe_ent
->port
[2].scr_addr
= base
+ 0x600;
704 probe_ent
->port
[3].scr_addr
= base
+ 0x700;
707 probe_ent
->n_ports
= 2;
710 probe_ent
->n_ports
= 4;
712 pdc_ata_setup_port(&probe_ent
->port
[2], base
+ 0x300);
713 pdc_ata_setup_port(&probe_ent
->port
[3], base
+ 0x380);
715 probe_ent
->port
[2].scr_addr
= base
+ 0x600;
716 probe_ent
->port
[3].scr_addr
= base
+ 0x700;
723 pci_set_master(pdev
);
725 /* initialize adapter */
726 pdc_host_init(board_idx
, probe_ent
);
728 /* FIXME: check ata_device_add return value */
729 ata_device_add(probe_ent
);
737 pci_release_regions(pdev
);
740 pci_disable_device(pdev
);
745 static int __init
pdc_ata_init(void)
747 return pci_module_init(&pdc_ata_pci_driver
);
751 static void __exit
pdc_ata_exit(void)
753 pci_unregister_driver(&pdc_ata_pci_driver
);
757 MODULE_AUTHOR("Jeff Garzik");
758 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
759 MODULE_LICENSE("GPL");
760 MODULE_DEVICE_TABLE(pci
, pdc_ata_pci_tbl
);
761 MODULE_VERSION(DRV_VERSION
);
763 module_init(pdc_ata_init
);
764 module_exit(pdc_ata_exit
);