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Merge branch 'x86/uaccess' into core/percpu
[linux-2.6/mini2440.git] / arch / x86 / kernel / io_apic.c
blobc0498daf01c32cc939316035c7ed45a6e6e77997
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/cpu.h>
50 #include <asm/desc.h>
51 #include <asm/proto.h>
52 #include <asm/acpi.h>
53 #include <asm/dma.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
56 #include <asm/nmi.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
64
65 #include <mach_ipi.h>
66 #include <mach_apic.h>
67 #include <mach_apicdef.h>
68
69 #define __apicdebuginit(type) static type __init
70
71 /*
72 * Is the SiS APIC rmw bug present ?
73 * -1 = don't know, 0 = no, 1 = yes
74 */
75 int sis_apic_bug = -1;
76
77 static DEFINE_SPINLOCK(ioapic_lock);
78 static DEFINE_SPINLOCK(vector_lock);
79
80 /*
81 * # of IRQ routing registers
82 */
83 int nr_ioapic_registers[MAX_IO_APICS];
84
85 /* I/O APIC entries */
86 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
87 int nr_ioapics;
88
89 /* MP IRQ source entries */
90 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
91
92 /* # of MP IRQ source entries */
93 int mp_irq_entries;
94
95 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
96 int mp_bus_id_to_type[MAX_MP_BUSSES];
97 #endif
98
99 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100
101 int skip_ioapic_setup;
102
103 static int __init parse_noapic(char *str)
104 {
105 /* disable IO-APIC */
106 disable_ioapic_setup();
107 return 0;
108 }
109 early_param("noapic", parse_noapic);
110
111 struct irq_pin_list;
112
113 /*
114 * This is performance-critical, we want to do it O(1)
115 *
116 * the indexing order of this array favors 1:1 mappings
117 * between pins and IRQs.
118 */
119
120 struct irq_pin_list {
121 int apic, pin;
122 struct irq_pin_list *next;
123 };
124
125 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
126 {
127 struct irq_pin_list *pin;
128 int node;
129
130 node = cpu_to_node(cpu);
131
132 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
133
134 return pin;
135 }
136
137 struct irq_cfg {
138 struct irq_pin_list *irq_2_pin;
139 cpumask_var_t domain;
140 cpumask_var_t old_domain;
141 unsigned move_cleanup_count;
142 u8 vector;
143 u8 move_in_progress : 1;
144 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
145 u8 move_desc_pending : 1;
146 #endif
147 };
148
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx[] = {
152 #else
153 static struct irq_cfg irq_cfgx[NR_IRQS] = {
154 #endif
155 [0] = { .vector = IRQ0_VECTOR, },
156 [1] = { .vector = IRQ1_VECTOR, },
157 [2] = { .vector = IRQ2_VECTOR, },
158 [3] = { .vector = IRQ3_VECTOR, },
159 [4] = { .vector = IRQ4_VECTOR, },
160 [5] = { .vector = IRQ5_VECTOR, },
161 [6] = { .vector = IRQ6_VECTOR, },
162 [7] = { .vector = IRQ7_VECTOR, },
163 [8] = { .vector = IRQ8_VECTOR, },
164 [9] = { .vector = IRQ9_VECTOR, },
165 [10] = { .vector = IRQ10_VECTOR, },
166 [11] = { .vector = IRQ11_VECTOR, },
167 [12] = { .vector = IRQ12_VECTOR, },
168 [13] = { .vector = IRQ13_VECTOR, },
169 [14] = { .vector = IRQ14_VECTOR, },
170 [15] = { .vector = IRQ15_VECTOR, },
171 };
172
173 int __init arch_early_irq_init(void)
174 {
175 struct irq_cfg *cfg;
176 struct irq_desc *desc;
177 int count;
178 int i;
179
180 cfg = irq_cfgx;
181 count = ARRAY_SIZE(irq_cfgx);
182
183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
186 alloc_bootmem_cpumask_var(&cfg[i].domain);
187 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
188 if (i < NR_IRQS_LEGACY)
189 cpumask_setall(cfg[i].domain);
190 }
191
192 return 0;
193 }
194
195 #ifdef CONFIG_SPARSE_IRQ
196 static struct irq_cfg *irq_cfg(unsigned int irq)
197 {
198 struct irq_cfg *cfg = NULL;
199 struct irq_desc *desc;
200
201 desc = irq_to_desc(irq);
202 if (desc)
203 cfg = desc->chip_data;
204
205 return cfg;
206 }
207
208 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
209 {
210 struct irq_cfg *cfg;
211 int node;
212
213 node = cpu_to_node(cpu);
214
215 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
216 if (cfg) {
217 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
218 kfree(cfg);
219 cfg = NULL;
220 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
221 GFP_ATOMIC, node)) {
222 free_cpumask_var(cfg->domain);
223 kfree(cfg);
224 cfg = NULL;
225 } else {
226 cpumask_clear(cfg->domain);
227 cpumask_clear(cfg->old_domain);
228 }
229 }
230
231 return cfg;
232 }
233
234 int arch_init_chip_data(struct irq_desc *desc, int cpu)
235 {
236 struct irq_cfg *cfg;
237
238 cfg = desc->chip_data;
239 if (!cfg) {
240 desc->chip_data = get_one_free_irq_cfg(cpu);
241 if (!desc->chip_data) {
242 printk(KERN_ERR "can not alloc irq_cfg\n");
243 BUG_ON(1);
244 }
245 }
246
247 return 0;
248 }
249
250 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
251
252 static void
253 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
254 {
255 struct irq_pin_list *old_entry, *head, *tail, *entry;
256
257 cfg->irq_2_pin = NULL;
258 old_entry = old_cfg->irq_2_pin;
259 if (!old_entry)
260 return;
261
262 entry = get_one_free_irq_2_pin(cpu);
263 if (!entry)
264 return;
265
266 entry->apic = old_entry->apic;
267 entry->pin = old_entry->pin;
268 head = entry;
269 tail = entry;
270 old_entry = old_entry->next;
271 while (old_entry) {
272 entry = get_one_free_irq_2_pin(cpu);
273 if (!entry) {
274 entry = head;
275 while (entry) {
276 head = entry->next;
277 kfree(entry);
278 entry = head;
279 }
280 /* still use the old one */
281 return;
282 }
283 entry->apic = old_entry->apic;
284 entry->pin = old_entry->pin;
285 tail->next = entry;
286 tail = entry;
287 old_entry = old_entry->next;
288 }
289
290 tail->next = NULL;
291 cfg->irq_2_pin = head;
292 }
293
294 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
295 {
296 struct irq_pin_list *entry, *next;
297
298 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
299 return;
300
301 entry = old_cfg->irq_2_pin;
302
303 while (entry) {
304 next = entry->next;
305 kfree(entry);
306 entry = next;
307 }
308 old_cfg->irq_2_pin = NULL;
309 }
310
311 void arch_init_copy_chip_data(struct irq_desc *old_desc,
312 struct irq_desc *desc, int cpu)
313 {
314 struct irq_cfg *cfg;
315 struct irq_cfg *old_cfg;
316
317 cfg = get_one_free_irq_cfg(cpu);
318
319 if (!cfg)
320 return;
321
322 desc->chip_data = cfg;
323
324 old_cfg = old_desc->chip_data;
325
326 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
327
328 init_copy_irq_2_pin(old_cfg, cfg, cpu);
329 }
330
331 static void free_irq_cfg(struct irq_cfg *old_cfg)
332 {
333 kfree(old_cfg);
334 }
335
336 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
337 {
338 struct irq_cfg *old_cfg, *cfg;
339
340 old_cfg = old_desc->chip_data;
341 cfg = desc->chip_data;
342
343 if (old_cfg == cfg)
344 return;
345
346 if (old_cfg) {
347 free_irq_2_pin(old_cfg, cfg);
348 free_irq_cfg(old_cfg);
349 old_desc->chip_data = NULL;
350 }
351 }
352
353 static void
354 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
355 {
356 struct irq_cfg *cfg = desc->chip_data;
357
358 if (!cfg->move_in_progress) {
359 /* it means that domain is not changed */
360 if (!cpumask_intersects(desc->affinity, mask))
361 cfg->move_desc_pending = 1;
362 }
363 }
364 #endif
365
366 #else
367 static struct irq_cfg *irq_cfg(unsigned int irq)
368 {
369 return irq < nr_irqs ? irq_cfgx + irq : NULL;
370 }
371
372 #endif
373
374 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
375 static inline void
376 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
377 {
378 }
379 #endif
380
381 struct io_apic {
382 unsigned int index;
383 unsigned int unused[3];
384 unsigned int data;
385 };
386
387 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
388 {
389 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
390 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
391 }
392
393 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
394 {
395 struct io_apic __iomem *io_apic = io_apic_base(apic);
396 writel(reg, &io_apic->index);
397 return readl(&io_apic->data);
398 }
399
400 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
401 {
402 struct io_apic __iomem *io_apic = io_apic_base(apic);
403 writel(reg, &io_apic->index);
404 writel(value, &io_apic->data);
405 }
406
407 /*
408 * Re-write a value: to be used for read-modify-write
409 * cycles where the read already set up the index register.
410 *
411 * Older SiS APIC requires we rewrite the index register
412 */
413 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
414 {
415 struct io_apic __iomem *io_apic = io_apic_base(apic);
416
417 if (sis_apic_bug)
418 writel(reg, &io_apic->index);
419 writel(value, &io_apic->data);
420 }
421
422 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
423 {
424 struct irq_pin_list *entry;
425 unsigned long flags;
426
427 spin_lock_irqsave(&ioapic_lock, flags);
428 entry = cfg->irq_2_pin;
429 for (;;) {
430 unsigned int reg;
431 int pin;
432
433 if (!entry)
434 break;
435 pin = entry->pin;
436 reg = io_apic_read(entry->apic, 0x10 + pin*2);
437 /* Is the remote IRR bit set? */
438 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
439 spin_unlock_irqrestore(&ioapic_lock, flags);
440 return true;
441 }
442 if (!entry->next)
443 break;
444 entry = entry->next;
445 }
446 spin_unlock_irqrestore(&ioapic_lock, flags);
447
448 return false;
449 }
450
451 union entry_union {
452 struct { u32 w1, w2; };
453 struct IO_APIC_route_entry entry;
454 };
455
456 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
457 {
458 union entry_union eu;
459 unsigned long flags;
460 spin_lock_irqsave(&ioapic_lock, flags);
461 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
462 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
463 spin_unlock_irqrestore(&ioapic_lock, flags);
464 return eu.entry;
465 }
466
467 /*
468 * When we write a new IO APIC routing entry, we need to write the high
469 * word first! If the mask bit in the low word is clear, we will enable
470 * the interrupt, and we need to make sure the entry is fully populated
471 * before that happens.
472 */
473 static void
474 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
475 {
476 union entry_union eu;
477 eu.entry = e;
478 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
479 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
480 }
481
482 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
483 {
484 unsigned long flags;
485 spin_lock_irqsave(&ioapic_lock, flags);
486 __ioapic_write_entry(apic, pin, e);
487 spin_unlock_irqrestore(&ioapic_lock, flags);
488 }
489
490 /*
491 * When we mask an IO APIC routing entry, we need to write the low
492 * word first, in order to set the mask bit before we change the
493 * high bits!
494 */
495 static void ioapic_mask_entry(int apic, int pin)
496 {
497 unsigned long flags;
498 union entry_union eu = { .entry.mask = 1 };
499
500 spin_lock_irqsave(&ioapic_lock, flags);
501 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
502 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
503 spin_unlock_irqrestore(&ioapic_lock, flags);
504 }
505
506 #ifdef CONFIG_SMP
507 static void send_cleanup_vector(struct irq_cfg *cfg)
508 {
509 cpumask_var_t cleanup_mask;
510
511 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
512 unsigned int i;
513 cfg->move_cleanup_count = 0;
514 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
515 cfg->move_cleanup_count++;
516 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
517 send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
518 } else {
519 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
520 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
521 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
522 free_cpumask_var(cleanup_mask);
523 }
524 cfg->move_in_progress = 0;
525 }
526
527 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
528 {
529 int apic, pin;
530 struct irq_pin_list *entry;
531 u8 vector = cfg->vector;
532
533 entry = cfg->irq_2_pin;
534 for (;;) {
535 unsigned int reg;
536
537 if (!entry)
538 break;
539
540 apic = entry->apic;
541 pin = entry->pin;
542 #ifdef CONFIG_INTR_REMAP
543 /*
544 * With interrupt-remapping, destination information comes
545 * from interrupt-remapping table entry.
546 */
547 if (!irq_remapped(irq))
548 io_apic_write(apic, 0x11 + pin*2, dest);
549 #else
550 io_apic_write(apic, 0x11 + pin*2, dest);
551 #endif
552 reg = io_apic_read(apic, 0x10 + pin*2);
553 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
554 reg |= vector;
555 io_apic_modify(apic, 0x10 + pin*2, reg);
556 if (!entry->next)
557 break;
558 entry = entry->next;
559 }
560 }
561
562 static int
563 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
564
565 /*
566 * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid
567 * of that, or returns BAD_APICID and leaves desc->affinity untouched.
568 */
569 static unsigned int
570 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
571 {
572 struct irq_cfg *cfg;
573 unsigned int irq;
574
575 if (!cpumask_intersects(mask, cpu_online_mask))
576 return BAD_APICID;
577
578 irq = desc->irq;
579 cfg = desc->chip_data;
580 if (assign_irq_vector(irq, cfg, mask))
581 return BAD_APICID;
582
583 cpumask_and(desc->affinity, cfg->domain, mask);
584 set_extra_move_desc(desc, mask);
585 return cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
586 }
587
588 static void
589 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
590 {
591 struct irq_cfg *cfg;
592 unsigned long flags;
593 unsigned int dest;
594 unsigned int irq;
595
596 irq = desc->irq;
597 cfg = desc->chip_data;
598
599 spin_lock_irqsave(&ioapic_lock, flags);
600 dest = set_desc_affinity(desc, mask);
601 if (dest != BAD_APICID) {
602 /* Only the high 8 bits are valid. */
603 dest = SET_APIC_LOGICAL_ID(dest);
604 __target_IO_APIC_irq(irq, dest, cfg);
605 }
606 spin_unlock_irqrestore(&ioapic_lock, flags);
607 }
608
609 static void
610 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
611 {
612 struct irq_desc *desc;
613
614 desc = irq_to_desc(irq);
615
616 set_ioapic_affinity_irq_desc(desc, mask);
617 }
618 #endif /* CONFIG_SMP */
619
620 /*
621 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
622 * shared ISA-space IRQs, so we have to support them. We are super
623 * fast in the common case, and fast for shared ISA-space IRQs.
624 */
625 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
626 {
627 struct irq_pin_list *entry;
628
629 entry = cfg->irq_2_pin;
630 if (!entry) {
631 entry = get_one_free_irq_2_pin(cpu);
632 if (!entry) {
633 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
634 apic, pin);
635 return;
636 }
637 cfg->irq_2_pin = entry;
638 entry->apic = apic;
639 entry->pin = pin;
640 return;
641 }
642
643 while (entry->next) {
644 /* not again, please */
645 if (entry->apic == apic && entry->pin == pin)
646 return;
647
648 entry = entry->next;
649 }
650
651 entry->next = get_one_free_irq_2_pin(cpu);
652 entry = entry->next;
653 entry->apic = apic;
654 entry->pin = pin;
655 }
656
657 /*
658 * Reroute an IRQ to a different pin.
659 */
660 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
661 int oldapic, int oldpin,
662 int newapic, int newpin)
663 {
664 struct irq_pin_list *entry = cfg->irq_2_pin;
665 int replaced = 0;
666
667 while (entry) {
668 if (entry->apic == oldapic && entry->pin == oldpin) {
669 entry->apic = newapic;
670 entry->pin = newpin;
671 replaced = 1;
672 /* every one is different, right? */
673 break;
674 }
675 entry = entry->next;
676 }
677
678 /* why? call replace before add? */
679 if (!replaced)
680 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
681 }
682
683 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
684 int mask_and, int mask_or,
685 void (*final)(struct irq_pin_list *entry))
686 {
687 int pin;
688 struct irq_pin_list *entry;
689
690 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
691 unsigned int reg;
692 pin = entry->pin;
693 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
694 reg &= mask_and;
695 reg |= mask_or;
696 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
697 if (final)
698 final(entry);
699 }
700 }
701
702 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
703 {
704 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
705 }
706
707 #ifdef CONFIG_X86_64
708 static void io_apic_sync(struct irq_pin_list *entry)
709 {
710 /*
711 * Synchronize the IO-APIC and the CPU by doing
712 * a dummy read from the IO-APIC
713 */
714 struct io_apic __iomem *io_apic;
715 io_apic = io_apic_base(entry->apic);
716 readl(&io_apic->data);
717 }
718
719 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
720 {
721 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
722 }
723 #else /* CONFIG_X86_32 */
724 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
725 {
726 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
727 }
728
729 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
730 {
731 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
732 IO_APIC_REDIR_MASKED, NULL);
733 }
734
735 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
736 {
737 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
738 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
739 }
740 #endif /* CONFIG_X86_32 */
741
742 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
743 {
744 struct irq_cfg *cfg = desc->chip_data;
745 unsigned long flags;
746
747 BUG_ON(!cfg);
748
749 spin_lock_irqsave(&ioapic_lock, flags);
750 __mask_IO_APIC_irq(cfg);
751 spin_unlock_irqrestore(&ioapic_lock, flags);
752 }
753
754 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
755 {
756 struct irq_cfg *cfg = desc->chip_data;
757 unsigned long flags;
758
759 spin_lock_irqsave(&ioapic_lock, flags);
760 __unmask_IO_APIC_irq(cfg);
761 spin_unlock_irqrestore(&ioapic_lock, flags);
762 }
763
764 static void mask_IO_APIC_irq(unsigned int irq)
765 {
766 struct irq_desc *desc = irq_to_desc(irq);
767
768 mask_IO_APIC_irq_desc(desc);
769 }
770 static void unmask_IO_APIC_irq(unsigned int irq)
771 {
772 struct irq_desc *desc = irq_to_desc(irq);
773
774 unmask_IO_APIC_irq_desc(desc);
775 }
776
777 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
778 {
779 struct IO_APIC_route_entry entry;
780
781 /* Check delivery_mode to be sure we're not clearing an SMI pin */
782 entry = ioapic_read_entry(apic, pin);
783 if (entry.delivery_mode == dest_SMI)
784 return;
785 /*
786 * Disable it in the IO-APIC irq-routing table:
787 */
788 ioapic_mask_entry(apic, pin);
789 }
790
791 static void clear_IO_APIC (void)
792 {
793 int apic, pin;
794
795 for (apic = 0; apic < nr_ioapics; apic++)
796 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
797 clear_IO_APIC_pin(apic, pin);
798 }
799
800 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
801 void send_IPI_self(int vector)
802 {
803 unsigned int cfg;
804
805 /*
806 * Wait for idle.
807 */
808 apic_wait_icr_idle();
809 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
810 /*
811 * Send the IPI. The write to APIC_ICR fires this off.
812 */
813 apic_write(APIC_ICR, cfg);
814 }
815 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
816
817 #ifdef CONFIG_X86_32
818 /*
819 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
820 * specific CPU-side IRQs.
821 */
822
823 #define MAX_PIRQS 8
824 static int pirq_entries [MAX_PIRQS];
825 static int pirqs_enabled;
826
827 static int __init ioapic_pirq_setup(char *str)
828 {
829 int i, max;
830 int ints[MAX_PIRQS+1];
831
832 get_options(str, ARRAY_SIZE(ints), ints);
833
834 for (i = 0; i < MAX_PIRQS; i++)
835 pirq_entries[i] = -1;
836
837 pirqs_enabled = 1;
838 apic_printk(APIC_VERBOSE, KERN_INFO
839 "PIRQ redirection, working around broken MP-BIOS.\n");
840 max = MAX_PIRQS;
841 if (ints[0] < MAX_PIRQS)
842 max = ints[0];
843
844 for (i = 0; i < max; i++) {
845 apic_printk(APIC_VERBOSE, KERN_DEBUG
846 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
847 /*
848 * PIRQs are mapped upside down, usually.
849 */
850 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
851 }
852 return 1;
853 }
854
855 __setup("pirq=", ioapic_pirq_setup);
856 #endif /* CONFIG_X86_32 */
857
858 #ifdef CONFIG_INTR_REMAP
859 /* I/O APIC RTE contents at the OS boot up */
860 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
861
862 /*
863 * Saves and masks all the unmasked IO-APIC RTE's
864 */
865 int save_mask_IO_APIC_setup(void)
866 {
867 union IO_APIC_reg_01 reg_01;
868 unsigned long flags;
869 int apic, pin;
870
871 /*
872 * The number of IO-APIC IRQ registers (== #pins):
873 */
874 for (apic = 0; apic < nr_ioapics; apic++) {
875 spin_lock_irqsave(&ioapic_lock, flags);
876 reg_01.raw = io_apic_read(apic, 1);
877 spin_unlock_irqrestore(&ioapic_lock, flags);
878 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
879 }
880
881 for (apic = 0; apic < nr_ioapics; apic++) {
882 early_ioapic_entries[apic] =
883 kzalloc(sizeof(struct IO_APIC_route_entry) *
884 nr_ioapic_registers[apic], GFP_KERNEL);
885 if (!early_ioapic_entries[apic])
886 goto nomem;
887 }
888
889 for (apic = 0; apic < nr_ioapics; apic++)
890 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
891 struct IO_APIC_route_entry entry;
892
893 entry = early_ioapic_entries[apic][pin] =
894 ioapic_read_entry(apic, pin);
895 if (!entry.mask) {
896 entry.mask = 1;
897 ioapic_write_entry(apic, pin, entry);
898 }
899 }
900
901 return 0;
902
903 nomem:
904 while (apic >= 0)
905 kfree(early_ioapic_entries[apic--]);
906 memset(early_ioapic_entries, 0,
907 ARRAY_SIZE(early_ioapic_entries));
908
909 return -ENOMEM;
910 }
911
912 void restore_IO_APIC_setup(void)
913 {
914 int apic, pin;
915
916 for (apic = 0; apic < nr_ioapics; apic++) {
917 if (!early_ioapic_entries[apic])
918 break;
919 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
920 ioapic_write_entry(apic, pin,
921 early_ioapic_entries[apic][pin]);
922 kfree(early_ioapic_entries[apic]);
923 early_ioapic_entries[apic] = NULL;
924 }
925 }
926
927 void reinit_intr_remapped_IO_APIC(int intr_remapping)
928 {
929 /*
930 * for now plain restore of previous settings.
931 * TBD: In the case of OS enabling interrupt-remapping,
932 * IO-APIC RTE's need to be setup to point to interrupt-remapping
933 * table entries. for now, do a plain restore, and wait for
934 * the setup_IO_APIC_irqs() to do proper initialization.
935 */
936 restore_IO_APIC_setup();
937 }
938 #endif
939
940 /*
941 * Find the IRQ entry number of a certain pin.
942 */
943 static int find_irq_entry(int apic, int pin, int type)
944 {
945 int i;
946
947 for (i = 0; i < mp_irq_entries; i++)
948 if (mp_irqs[i].irqtype == type &&
949 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
950 mp_irqs[i].dstapic == MP_APIC_ALL) &&
951 mp_irqs[i].dstirq == pin)
952 return i;
953
954 return -1;
955 }
956
957 /*
958 * Find the pin to which IRQ[irq] (ISA) is connected
959 */
960 static int __init find_isa_irq_pin(int irq, int type)
961 {
962 int i;
963
964 for (i = 0; i < mp_irq_entries; i++) {
965 int lbus = mp_irqs[i].srcbus;
966
967 if (test_bit(lbus, mp_bus_not_pci) &&
968 (mp_irqs[i].irqtype == type) &&
969 (mp_irqs[i].srcbusirq == irq))
970
971 return mp_irqs[i].dstirq;
972 }
973 return -1;
974 }
975
976 static int __init find_isa_irq_apic(int irq, int type)
977 {
978 int i;
979
980 for (i = 0; i < mp_irq_entries; i++) {
981 int lbus = mp_irqs[i].srcbus;
982
983 if (test_bit(lbus, mp_bus_not_pci) &&
984 (mp_irqs[i].irqtype == type) &&
985 (mp_irqs[i].srcbusirq == irq))
986 break;
987 }
988 if (i < mp_irq_entries) {
989 int apic;
990 for(apic = 0; apic < nr_ioapics; apic++) {
991 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
992 return apic;
993 }
994 }
995
996 return -1;
997 }
998
999 /*
1000 * Find a specific PCI IRQ entry.
1001 * Not an __init, possibly needed by modules
1002 */
1003 static int pin_2_irq(int idx, int apic, int pin);
1004
1005 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1006 {
1007 int apic, i, best_guess = -1;
1008
1009 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1010 bus, slot, pin);
1011 if (test_bit(bus, mp_bus_not_pci)) {
1012 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1013 return -1;
1014 }
1015 for (i = 0; i < mp_irq_entries; i++) {
1016 int lbus = mp_irqs[i].srcbus;
1017
1018 for (apic = 0; apic < nr_ioapics; apic++)
1019 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1020 mp_irqs[i].dstapic == MP_APIC_ALL)
1021 break;
1022
1023 if (!test_bit(lbus, mp_bus_not_pci) &&
1024 !mp_irqs[i].irqtype &&
1025 (bus == lbus) &&
1026 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1027 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1028
1029 if (!(apic || IO_APIC_IRQ(irq)))
1030 continue;
1031
1032 if (pin == (mp_irqs[i].srcbusirq & 3))
1033 return irq;
1034 /*
1035 * Use the first all-but-pin matching entry as a
1036 * best-guess fuzzy result for broken mptables.
1037 */
1038 if (best_guess < 0)
1039 best_guess = irq;
1040 }
1041 }
1042 return best_guess;
1043 }
1044
1045 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1046
1047 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1048 /*
1049 * EISA Edge/Level control register, ELCR
1050 */
1051 static int EISA_ELCR(unsigned int irq)
1052 {
1053 if (irq < NR_IRQS_LEGACY) {
1054 unsigned int port = 0x4d0 + (irq >> 3);
1055 return (inb(port) >> (irq & 7)) & 1;
1056 }
1057 apic_printk(APIC_VERBOSE, KERN_INFO
1058 "Broken MPtable reports ISA irq %d\n", irq);
1059 return 0;
1060 }
1061
1062 #endif
1063
1064 /* ISA interrupts are always polarity zero edge triggered,
1065 * when listed as conforming in the MP table. */
1066
1067 #define default_ISA_trigger(idx) (0)
1068 #define default_ISA_polarity(idx) (0)
1069
1070 /* EISA interrupts are always polarity zero and can be edge or level
1071 * trigger depending on the ELCR value. If an interrupt is listed as
1072 * EISA conforming in the MP table, that means its trigger type must
1073 * be read in from the ELCR */
1074
1075 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
1076 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1077
1078 /* PCI interrupts are always polarity one level triggered,
1079 * when listed as conforming in the MP table. */
1080
1081 #define default_PCI_trigger(idx) (1)
1082 #define default_PCI_polarity(idx) (1)
1083
1084 /* MCA interrupts are always polarity zero level triggered,
1085 * when listed as conforming in the MP table. */
1086
1087 #define default_MCA_trigger(idx) (1)
1088 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1089
1090 static int MPBIOS_polarity(int idx)
1091 {
1092 int bus = mp_irqs[idx].srcbus;
1093 int polarity;
1094
1095 /*
1096 * Determine IRQ line polarity (high active or low active):
1097 */
1098 switch (mp_irqs[idx].irqflag & 3)
1099 {
1100 case 0: /* conforms, ie. bus-type dependent polarity */
1101 if (test_bit(bus, mp_bus_not_pci))
1102 polarity = default_ISA_polarity(idx);
1103 else
1104 polarity = default_PCI_polarity(idx);
1105 break;
1106 case 1: /* high active */
1107 {
1108 polarity = 0;
1109 break;
1110 }
1111 case 2: /* reserved */
1112 {
1113 printk(KERN_WARNING "broken BIOS!!\n");
1114 polarity = 1;
1115 break;
1116 }
1117 case 3: /* low active */
1118 {
1119 polarity = 1;
1120 break;
1121 }
1122 default: /* invalid */
1123 {
1124 printk(KERN_WARNING "broken BIOS!!\n");
1125 polarity = 1;
1126 break;
1127 }
1128 }
1129 return polarity;
1130 }
1131
1132 static int MPBIOS_trigger(int idx)
1133 {
1134 int bus = mp_irqs[idx].srcbus;
1135 int trigger;
1136
1137 /*
1138 * Determine IRQ trigger mode (edge or level sensitive):
1139 */
1140 switch ((mp_irqs[idx].irqflag>>2) & 3)
1141 {
1142 case 0: /* conforms, ie. bus-type dependent */
1143 if (test_bit(bus, mp_bus_not_pci))
1144 trigger = default_ISA_trigger(idx);
1145 else
1146 trigger = default_PCI_trigger(idx);
1147 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1148 switch (mp_bus_id_to_type[bus]) {
1149 case MP_BUS_ISA: /* ISA pin */
1150 {
1151 /* set before the switch */
1152 break;
1153 }
1154 case MP_BUS_EISA: /* EISA pin */
1155 {
1156 trigger = default_EISA_trigger(idx);
1157 break;
1158 }
1159 case MP_BUS_PCI: /* PCI pin */
1160 {
1161 /* set before the switch */
1162 break;
1163 }
1164 case MP_BUS_MCA: /* MCA pin */
1165 {
1166 trigger = default_MCA_trigger(idx);
1167 break;
1168 }
1169 default:
1170 {
1171 printk(KERN_WARNING "broken BIOS!!\n");
1172 trigger = 1;
1173 break;
1174 }
1175 }
1176 #endif
1177 break;
1178 case 1: /* edge */
1179 {
1180 trigger = 0;
1181 break;
1182 }
1183 case 2: /* reserved */
1184 {
1185 printk(KERN_WARNING "broken BIOS!!\n");
1186 trigger = 1;
1187 break;
1188 }
1189 case 3: /* level */
1190 {
1191 trigger = 1;
1192 break;
1193 }
1194 default: /* invalid */
1195 {
1196 printk(KERN_WARNING "broken BIOS!!\n");
1197 trigger = 0;
1198 break;
1199 }
1200 }
1201 return trigger;
1202 }
1203
1204 static inline int irq_polarity(int idx)
1205 {
1206 return MPBIOS_polarity(idx);
1207 }
1208
1209 static inline int irq_trigger(int idx)
1210 {
1211 return MPBIOS_trigger(idx);
1212 }
1213
1214 int (*ioapic_renumber_irq)(int ioapic, int irq);
1215 static int pin_2_irq(int idx, int apic, int pin)
1216 {
1217 int irq, i;
1218 int bus = mp_irqs[idx].srcbus;
1219
1220 /*
1221 * Debugging check, we are in big trouble if this message pops up!
1222 */
1223 if (mp_irqs[idx].dstirq != pin)
1224 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1225
1226 if (test_bit(bus, mp_bus_not_pci)) {
1227 irq = mp_irqs[idx].srcbusirq;
1228 } else {
1229 /*
1230 * PCI IRQs are mapped in order
1231 */
1232 i = irq = 0;
1233 while (i < apic)
1234 irq += nr_ioapic_registers[i++];
1235 irq += pin;
1236 /*
1237 * For MPS mode, so far only needed by ES7000 platform
1238 */
1239 if (ioapic_renumber_irq)
1240 irq = ioapic_renumber_irq(apic, irq);
1241 }
1242
1243 #ifdef CONFIG_X86_32
1244 /*
1245 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1246 */
1247 if ((pin >= 16) && (pin <= 23)) {
1248 if (pirq_entries[pin-16] != -1) {
1249 if (!pirq_entries[pin-16]) {
1250 apic_printk(APIC_VERBOSE, KERN_DEBUG
1251 "disabling PIRQ%d\n", pin-16);
1252 } else {
1253 irq = pirq_entries[pin-16];
1254 apic_printk(APIC_VERBOSE, KERN_DEBUG
1255 "using PIRQ%d -> IRQ %d\n",
1256 pin-16, irq);
1257 }
1258 }
1259 }
1260 #endif
1261
1262 return irq;
1263 }
1264
1265 void lock_vector_lock(void)
1266 {
1267 /* Used to the online set of cpus does not change
1268 * during assign_irq_vector.
1269 */
1270 spin_lock(&vector_lock);
1271 }
1272
1273 void unlock_vector_lock(void)
1274 {
1275 spin_unlock(&vector_lock);
1276 }
1277
1278 static int
1279 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1280 {
1281 /*
1282 * NOTE! The local APIC isn't very good at handling
1283 * multiple interrupts at the same interrupt level.
1284 * As the interrupt level is determined by taking the
1285 * vector number and shifting that right by 4, we
1286 * want to spread these out a bit so that they don't
1287 * all fall in the same interrupt level.
1288 *
1289 * Also, we've got to be careful not to trash gate
1290 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1291 */
1292 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1293 unsigned int old_vector;
1294 int cpu, err;
1295 cpumask_var_t tmp_mask;
1296
1297 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1298 return -EBUSY;
1299
1300 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1301 return -ENOMEM;
1302
1303 old_vector = cfg->vector;
1304 if (old_vector) {
1305 cpumask_and(tmp_mask, mask, cpu_online_mask);
1306 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1307 if (!cpumask_empty(tmp_mask)) {
1308 free_cpumask_var(tmp_mask);
1309 return 0;
1310 }
1311 }
1312
1313 /* Only try and allocate irqs on cpus that are present */
1314 err = -ENOSPC;
1315 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1316 int new_cpu;
1317 int vector, offset;
1318
1319 vector_allocation_domain(cpu, tmp_mask);
1320
1321 vector = current_vector;
1322 offset = current_offset;
1323 next:
1324 vector += 8;
1325 if (vector >= first_system_vector) {
1326 /* If out of vectors on large boxen, must share them. */
1327 offset = (offset + 1) % 8;
1328 vector = FIRST_DEVICE_VECTOR + offset;
1329 }
1330 if (unlikely(current_vector == vector))
1331 continue;
1332
1333 if (test_bit(vector, used_vectors))
1334 goto next;
1335
1336 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1337 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1338 goto next;
1339 /* Found one! */
1340 current_vector = vector;
1341 current_offset = offset;
1342 if (old_vector) {
1343 cfg->move_in_progress = 1;
1344 cpumask_copy(cfg->old_domain, cfg->domain);
1345 }
1346 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1347 per_cpu(vector_irq, new_cpu)[vector] = irq;
1348 cfg->vector = vector;
1349 cpumask_copy(cfg->domain, tmp_mask);
1350 err = 0;
1351 break;
1352 }
1353 free_cpumask_var(tmp_mask);
1354 return err;
1355 }
1356
1357 static int
1358 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1359 {
1360 int err;
1361 unsigned long flags;
1362
1363 spin_lock_irqsave(&vector_lock, flags);
1364 err = __assign_irq_vector(irq, cfg, mask);
1365 spin_unlock_irqrestore(&vector_lock, flags);
1366 return err;
1367 }
1368
1369 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1370 {
1371 int cpu, vector;
1372
1373 BUG_ON(!cfg->vector);
1374
1375 vector = cfg->vector;
1376 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1377 per_cpu(vector_irq, cpu)[vector] = -1;
1378
1379 cfg->vector = 0;
1380 cpumask_clear(cfg->domain);
1381
1382 if (likely(!cfg->move_in_progress))
1383 return;
1384 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1385 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1386 vector++) {
1387 if (per_cpu(vector_irq, cpu)[vector] != irq)
1388 continue;
1389 per_cpu(vector_irq, cpu)[vector] = -1;
1390 break;
1391 }
1392 }
1393 cfg->move_in_progress = 0;
1394 }
1395
1396 void __setup_vector_irq(int cpu)
1397 {
1398 /* Initialize vector_irq on a new cpu */
1399 /* This function must be called with vector_lock held */
1400 int irq, vector;
1401 struct irq_cfg *cfg;
1402 struct irq_desc *desc;
1403
1404 /* Mark the inuse vectors */
1405 for_each_irq_desc(irq, desc) {
1406 cfg = desc->chip_data;
1407 if (!cpumask_test_cpu(cpu, cfg->domain))
1408 continue;
1409 vector = cfg->vector;
1410 per_cpu(vector_irq, cpu)[vector] = irq;
1411 }
1412 /* Mark the free vectors */
1413 for (vector = 0; vector < NR_VECTORS; ++vector) {
1414 irq = per_cpu(vector_irq, cpu)[vector];
1415 if (irq < 0)
1416 continue;
1417
1418 cfg = irq_cfg(irq);
1419 if (!cpumask_test_cpu(cpu, cfg->domain))
1420 per_cpu(vector_irq, cpu)[vector] = -1;
1421 }
1422 }
1423
1424 static struct irq_chip ioapic_chip;
1425 #ifdef CONFIG_INTR_REMAP
1426 static struct irq_chip ir_ioapic_chip;
1427 #endif
1428
1429 #define IOAPIC_AUTO -1
1430 #define IOAPIC_EDGE 0
1431 #define IOAPIC_LEVEL 1
1432
1433 #ifdef CONFIG_X86_32
1434 static inline int IO_APIC_irq_trigger(int irq)
1435 {
1436 int apic, idx, pin;
1437
1438 for (apic = 0; apic < nr_ioapics; apic++) {
1439 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1440 idx = find_irq_entry(apic, pin, mp_INT);
1441 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1442 return irq_trigger(idx);
1443 }
1444 }
1445 /*
1446 * nonexistent IRQs are edge default
1447 */
1448 return 0;
1449 }
1450 #else
1451 static inline int IO_APIC_irq_trigger(int irq)
1452 {
1453 return 1;
1454 }
1455 #endif
1456
1457 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1458 {
1459
1460 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1461 trigger == IOAPIC_LEVEL)
1462 desc->status |= IRQ_LEVEL;
1463 else
1464 desc->status &= ~IRQ_LEVEL;
1465
1466 #ifdef CONFIG_INTR_REMAP
1467 if (irq_remapped(irq)) {
1468 desc->status |= IRQ_MOVE_PCNTXT;
1469 if (trigger)
1470 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1471 handle_fasteoi_irq,
1472 "fasteoi");
1473 else
1474 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1475 handle_edge_irq, "edge");
1476 return;
1477 }
1478 #endif
1479 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1480 trigger == IOAPIC_LEVEL)
1481 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1482 handle_fasteoi_irq,
1483 "fasteoi");
1484 else
1485 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1486 handle_edge_irq, "edge");
1487 }
1488
1489 static int setup_ioapic_entry(int apic, int irq,
1490 struct IO_APIC_route_entry *entry,
1491 unsigned int destination, int trigger,
1492 int polarity, int vector)
1493 {
1494 /*
1495 * add it to the IO-APIC irq-routing table:
1496 */
1497 memset(entry,0,sizeof(*entry));
1498
1499 #ifdef CONFIG_INTR_REMAP
1500 if (intr_remapping_enabled) {
1501 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1502 struct irte irte;
1503 struct IR_IO_APIC_route_entry *ir_entry =
1504 (struct IR_IO_APIC_route_entry *) entry;
1505 int index;
1506
1507 if (!iommu)
1508 panic("No mapping iommu for ioapic %d\n", apic);
1509
1510 index = alloc_irte(iommu, irq, 1);
1511 if (index < 0)
1512 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1513
1514 memset(&irte, 0, sizeof(irte));
1515
1516 irte.present = 1;
1517 irte.dst_mode = INT_DEST_MODE;
1518 irte.trigger_mode = trigger;
1519 irte.dlvry_mode = INT_DELIVERY_MODE;
1520 irte.vector = vector;
1521 irte.dest_id = IRTE_DEST(destination);
1522
1523 modify_irte(irq, &irte);
1524
1525 ir_entry->index2 = (index >> 15) & 0x1;
1526 ir_entry->zero = 0;
1527 ir_entry->format = 1;
1528 ir_entry->index = (index & 0x7fff);
1529 } else
1530 #endif
1531 {
1532 entry->delivery_mode = INT_DELIVERY_MODE;
1533 entry->dest_mode = INT_DEST_MODE;
1534 entry->dest = destination;
1535 }
1536
1537 entry->mask = 0; /* enable IRQ */
1538 entry->trigger = trigger;
1539 entry->polarity = polarity;
1540 entry->vector = vector;
1541
1542 /* Mask level triggered irqs.
1543 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1544 */
1545 if (trigger)
1546 entry->mask = 1;
1547 return 0;
1548 }
1549
1550 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc,
1551 int trigger, int polarity)
1552 {
1553 struct irq_cfg *cfg;
1554 struct IO_APIC_route_entry entry;
1555 unsigned int dest;
1556
1557 if (!IO_APIC_IRQ(irq))
1558 return;
1559
1560 cfg = desc->chip_data;
1561
1562 if (assign_irq_vector(irq, cfg, TARGET_CPUS))
1563 return;
1564
1565 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
1566
1567 apic_printk(APIC_VERBOSE,KERN_DEBUG
1568 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1569 "IRQ %d Mode:%i Active:%i)\n",
1570 apic, mp_ioapics[apic].apicid, pin, cfg->vector,
1571 irq, trigger, polarity);
1572
1573
1574 if (setup_ioapic_entry(mp_ioapics[apic].apicid, irq, &entry,
1575 dest, trigger, polarity, cfg->vector)) {
1576 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1577 mp_ioapics[apic].apicid, pin);
1578 __clear_irq_vector(irq, cfg);
1579 return;
1580 }
1581
1582 ioapic_register_intr(irq, desc, trigger);
1583 if (irq < NR_IRQS_LEGACY)
1584 disable_8259A_irq(irq);
1585
1586 ioapic_write_entry(apic, pin, entry);
1587 }
1588
1589 static void __init setup_IO_APIC_irqs(void)
1590 {
1591 int apic, pin, idx, irq;
1592 int notcon = 0;
1593 struct irq_desc *desc;
1594 struct irq_cfg *cfg;
1595 int cpu = boot_cpu_id;
1596
1597 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1598
1599 for (apic = 0; apic < nr_ioapics; apic++) {
1600 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1601
1602 idx = find_irq_entry(apic, pin, mp_INT);
1603 if (idx == -1) {
1604 if (!notcon) {
1605 notcon = 1;
1606 apic_printk(APIC_VERBOSE,
1607 KERN_DEBUG " %d-%d",
1608 mp_ioapics[apic].apicid, pin);
1609 } else
1610 apic_printk(APIC_VERBOSE, " %d-%d",
1611 mp_ioapics[apic].apicid, pin);
1612 continue;
1613 }
1614 if (notcon) {
1615 apic_printk(APIC_VERBOSE,
1616 " (apicid-pin) not connected\n");
1617 notcon = 0;
1618 }
1619
1620 irq = pin_2_irq(idx, apic, pin);
1621 #ifdef CONFIG_X86_32
1622 if (multi_timer_check(apic, irq))
1623 continue;
1624 #endif
1625 desc = irq_to_desc_alloc_cpu(irq, cpu);
1626 if (!desc) {
1627 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1628 continue;
1629 }
1630 cfg = desc->chip_data;
1631 add_pin_to_irq_cpu(cfg, cpu, apic, pin);
1632
1633 setup_IO_APIC_irq(apic, pin, irq, desc,
1634 irq_trigger(idx), irq_polarity(idx));
1635 }
1636 }
1637
1638 if (notcon)
1639 apic_printk(APIC_VERBOSE,
1640 " (apicid-pin) not connected\n");
1641 }
1642
1643 /*
1644 * Set up the timer pin, possibly with the 8259A-master behind.
1645 */
1646 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1647 int vector)
1648 {
1649 struct IO_APIC_route_entry entry;
1650
1651 #ifdef CONFIG_INTR_REMAP
1652 if (intr_remapping_enabled)
1653 return;
1654 #endif
1655
1656 memset(&entry, 0, sizeof(entry));
1657
1658 /*
1659 * We use logical delivery to get the timer IRQ
1660 * to the first CPU.
1661 */
1662 entry.dest_mode = INT_DEST_MODE;
1663 entry.mask = 1; /* mask IRQ now */
1664 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1665 entry.delivery_mode = INT_DELIVERY_MODE;
1666 entry.polarity = 0;
1667 entry.trigger = 0;
1668 entry.vector = vector;
1669
1670 /*
1671 * The timer IRQ doesn't have to know that behind the
1672 * scene we may have a 8259A-master in AEOI mode ...
1673 */
1674 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1675
1676 /*
1677 * Add it to the IO-APIC irq-routing table:
1678 */
1679 ioapic_write_entry(apic, pin, entry);
1680 }
1681
1682
1683 __apicdebuginit(void) print_IO_APIC(void)
1684 {
1685 int apic, i;
1686 union IO_APIC_reg_00 reg_00;
1687 union IO_APIC_reg_01 reg_01;
1688 union IO_APIC_reg_02 reg_02;
1689 union IO_APIC_reg_03 reg_03;
1690 unsigned long flags;
1691 struct irq_cfg *cfg;
1692 struct irq_desc *desc;
1693 unsigned int irq;
1694
1695 if (apic_verbosity == APIC_QUIET)
1696 return;
1697
1698 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1699 for (i = 0; i < nr_ioapics; i++)
1700 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1701 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1702
1703 /*
1704 * We are a bit conservative about what we expect. We have to
1705 * know about every hardware change ASAP.
1706 */
1707 printk(KERN_INFO "testing the IO APIC.......................\n");
1708
1709 for (apic = 0; apic < nr_ioapics; apic++) {
1710
1711 spin_lock_irqsave(&ioapic_lock, flags);
1712 reg_00.raw = io_apic_read(apic, 0);
1713 reg_01.raw = io_apic_read(apic, 1);
1714 if (reg_01.bits.version >= 0x10)
1715 reg_02.raw = io_apic_read(apic, 2);
1716 if (reg_01.bits.version >= 0x20)
1717 reg_03.raw = io_apic_read(apic, 3);
1718 spin_unlock_irqrestore(&ioapic_lock, flags);
1719
1720 printk("\n");
1721 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1722 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1723 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1724 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1725 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1726
1727 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1728 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1729
1730 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1731 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1732
1733 /*
1734 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1735 * but the value of reg_02 is read as the previous read register
1736 * value, so ignore it if reg_02 == reg_01.
1737 */
1738 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1739 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1740 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1741 }
1742
1743 /*
1744 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1745 * or reg_03, but the value of reg_0[23] is read as the previous read
1746 * register value, so ignore it if reg_03 == reg_0[12].
1747 */
1748 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1749 reg_03.raw != reg_01.raw) {
1750 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1751 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1752 }
1753
1754 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1755
1756 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1757 " Stat Dmod Deli Vect: \n");
1758
1759 for (i = 0; i <= reg_01.bits.entries; i++) {
1760 struct IO_APIC_route_entry entry;
1761
1762 entry = ioapic_read_entry(apic, i);
1763
1764 printk(KERN_DEBUG " %02x %03X ",
1765 i,
1766 entry.dest
1767 );
1768
1769 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1770 entry.mask,
1771 entry.trigger,
1772 entry.irr,
1773 entry.polarity,
1774 entry.delivery_status,
1775 entry.dest_mode,
1776 entry.delivery_mode,
1777 entry.vector
1778 );
1779 }
1780 }
1781 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1782 for_each_irq_desc(irq, desc) {
1783 struct irq_pin_list *entry;
1784
1785 cfg = desc->chip_data;
1786 entry = cfg->irq_2_pin;
1787 if (!entry)
1788 continue;
1789 printk(KERN_DEBUG "IRQ%d ", irq);
1790 for (;;) {
1791 printk("-> %d:%d", entry->apic, entry->pin);
1792 if (!entry->next)
1793 break;
1794 entry = entry->next;
1795 }
1796 printk("\n");
1797 }
1798
1799 printk(KERN_INFO ".................................... done.\n");
1800
1801 return;
1802 }
1803
1804 __apicdebuginit(void) print_APIC_bitfield(int base)
1805 {
1806 unsigned int v;
1807 int i, j;
1808
1809 if (apic_verbosity == APIC_QUIET)
1810 return;
1811
1812 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1813 for (i = 0; i < 8; i++) {
1814 v = apic_read(base + i*0x10);
1815 for (j = 0; j < 32; j++) {
1816 if (v & (1<<j))
1817 printk("1");
1818 else
1819 printk("0");
1820 }
1821 printk("\n");
1822 }
1823 }
1824
1825 __apicdebuginit(void) print_local_APIC(void *dummy)
1826 {
1827 unsigned int v, ver, maxlvt;
1828 u64 icr;
1829
1830 if (apic_verbosity == APIC_QUIET)
1831 return;
1832
1833 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1834 smp_processor_id(), hard_smp_processor_id());
1835 v = apic_read(APIC_ID);
1836 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1837 v = apic_read(APIC_LVR);
1838 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1839 ver = GET_APIC_VERSION(v);
1840 maxlvt = lapic_get_maxlvt();
1841
1842 v = apic_read(APIC_TASKPRI);
1843 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1844
1845 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1846 if (!APIC_XAPIC(ver)) {
1847 v = apic_read(APIC_ARBPRI);
1848 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1849 v & APIC_ARBPRI_MASK);
1850 }
1851 v = apic_read(APIC_PROCPRI);
1852 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1853 }
1854
1855 /*
1856 * Remote read supported only in the 82489DX and local APIC for
1857 * Pentium processors.
1858 */
1859 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1860 v = apic_read(APIC_RRR);
1861 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1862 }
1863
1864 v = apic_read(APIC_LDR);
1865 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1866 if (!x2apic_enabled()) {
1867 v = apic_read(APIC_DFR);
1868 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1869 }
1870 v = apic_read(APIC_SPIV);
1871 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1872
1873 printk(KERN_DEBUG "... APIC ISR field:\n");
1874 print_APIC_bitfield(APIC_ISR);
1875 printk(KERN_DEBUG "... APIC TMR field:\n");
1876 print_APIC_bitfield(APIC_TMR);
1877 printk(KERN_DEBUG "... APIC IRR field:\n");
1878 print_APIC_bitfield(APIC_IRR);
1879
1880 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1881 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1882 apic_write(APIC_ESR, 0);
1883
1884 v = apic_read(APIC_ESR);
1885 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1886 }
1887
1888 icr = apic_icr_read();
1889 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1890 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1891
1892 v = apic_read(APIC_LVTT);
1893 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1894
1895 if (maxlvt > 3) { /* PC is LVT#4. */
1896 v = apic_read(APIC_LVTPC);
1897 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1898 }
1899 v = apic_read(APIC_LVT0);
1900 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1901 v = apic_read(APIC_LVT1);
1902 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1903
1904 if (maxlvt > 2) { /* ERR is LVT#3. */
1905 v = apic_read(APIC_LVTERR);
1906 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1907 }
1908
1909 v = apic_read(APIC_TMICT);
1910 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1911 v = apic_read(APIC_TMCCT);
1912 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1913 v = apic_read(APIC_TDCR);
1914 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1915 printk("\n");
1916 }
1917
1918 __apicdebuginit(void) print_all_local_APICs(void)
1919 {
1920 int cpu;
1921
1922 preempt_disable();
1923 for_each_online_cpu(cpu)
1924 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1925 preempt_enable();
1926 }
1927
1928 __apicdebuginit(void) print_PIC(void)
1929 {
1930 unsigned int v;
1931 unsigned long flags;
1932
1933 if (apic_verbosity == APIC_QUIET)
1934 return;
1935
1936 printk(KERN_DEBUG "\nprinting PIC contents\n");
1937
1938 spin_lock_irqsave(&i8259A_lock, flags);
1939
1940 v = inb(0xa1) << 8 | inb(0x21);
1941 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1942
1943 v = inb(0xa0) << 8 | inb(0x20);
1944 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1945
1946 outb(0x0b,0xa0);
1947 outb(0x0b,0x20);
1948 v = inb(0xa0) << 8 | inb(0x20);
1949 outb(0x0a,0xa0);
1950 outb(0x0a,0x20);
1951
1952 spin_unlock_irqrestore(&i8259A_lock, flags);
1953
1954 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1955
1956 v = inb(0x4d1) << 8 | inb(0x4d0);
1957 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1958 }
1959
1960 __apicdebuginit(int) print_all_ICs(void)
1961 {
1962 print_PIC();
1963 print_all_local_APICs();
1964 print_IO_APIC();
1965
1966 return 0;
1967 }
1968
1969 fs_initcall(print_all_ICs);
1970
1971
1972 /* Where if anywhere is the i8259 connect in external int mode */
1973 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1974
1975 void __init enable_IO_APIC(void)
1976 {
1977 union IO_APIC_reg_01 reg_01;
1978 int i8259_apic, i8259_pin;
1979 int apic;
1980 unsigned long flags;
1981
1982 #ifdef CONFIG_X86_32
1983 int i;
1984 if (!pirqs_enabled)
1985 for (i = 0; i < MAX_PIRQS; i++)
1986 pirq_entries[i] = -1;
1987 #endif
1988
1989 /*
1990 * The number of IO-APIC IRQ registers (== #pins):
1991 */
1992 for (apic = 0; apic < nr_ioapics; apic++) {
1993 spin_lock_irqsave(&ioapic_lock, flags);
1994 reg_01.raw = io_apic_read(apic, 1);
1995 spin_unlock_irqrestore(&ioapic_lock, flags);
1996 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1997 }
1998 for(apic = 0; apic < nr_ioapics; apic++) {
1999 int pin;
2000 /* See if any of the pins is in ExtINT mode */
2001 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2002 struct IO_APIC_route_entry entry;
2003 entry = ioapic_read_entry(apic, pin);
2004
2005 /* If the interrupt line is enabled and in ExtInt mode
2006 * I have found the pin where the i8259 is connected.
2007 */
2008 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2009 ioapic_i8259.apic = apic;
2010 ioapic_i8259.pin = pin;
2011 goto found_i8259;
2012 }
2013 }
2014 }
2015 found_i8259:
2016 /* Look to see what if the MP table has reported the ExtINT */
2017 /* If we could not find the appropriate pin by looking at the ioapic
2018 * the i8259 probably is not connected the ioapic but give the
2019 * mptable a chance anyway.
2020 */
2021 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2022 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2023 /* Trust the MP table if nothing is setup in the hardware */
2024 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2025 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2026 ioapic_i8259.pin = i8259_pin;
2027 ioapic_i8259.apic = i8259_apic;
2028 }
2029 /* Complain if the MP table and the hardware disagree */
2030 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2031 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2032 {
2033 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2034 }
2035
2036 /*
2037 * Do not trust the IO-APIC being empty at bootup
2038 */
2039 clear_IO_APIC();
2040 }
2041
2042 /*
2043 * Not an __init, needed by the reboot code
2044 */
2045 void disable_IO_APIC(void)
2046 {
2047 /*
2048 * Clear the IO-APIC before rebooting:
2049 */
2050 clear_IO_APIC();
2051
2052 /*
2053 * If the i8259 is routed through an IOAPIC
2054 * Put that IOAPIC in virtual wire mode
2055 * so legacy interrupts can be delivered.
2056 */
2057 if (ioapic_i8259.pin != -1) {
2058 struct IO_APIC_route_entry entry;
2059
2060 memset(&entry, 0, sizeof(entry));
2061 entry.mask = 0; /* Enabled */
2062 entry.trigger = 0; /* Edge */
2063 entry.irr = 0;
2064 entry.polarity = 0; /* High */
2065 entry.delivery_status = 0;
2066 entry.dest_mode = 0; /* Physical */
2067 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2068 entry.vector = 0;
2069 entry.dest = read_apic_id();
2070
2071 /*
2072 * Add it to the IO-APIC irq-routing table:
2073 */
2074 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2075 }
2076
2077 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2078 }
2079
2080 #ifdef CONFIG_X86_32
2081 /*
2082 * function to set the IO-APIC physical IDs based on the
2083 * values stored in the MPC table.
2084 *
2085 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2086 */
2087
2088 static void __init setup_ioapic_ids_from_mpc(void)
2089 {
2090 union IO_APIC_reg_00 reg_00;
2091 physid_mask_t phys_id_present_map;
2092 int apic;
2093 int i;
2094 unsigned char old_id;
2095 unsigned long flags;
2096
2097 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2098 return;
2099
2100 /*
2101 * Don't check I/O APIC IDs for xAPIC systems. They have
2102 * no meaning without the serial APIC bus.
2103 */
2104 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2105 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2106 return;
2107 /*
2108 * This is broken; anything with a real cpu count has to
2109 * circumvent this idiocy regardless.
2110 */
2111 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
2112
2113 /*
2114 * Set the IOAPIC ID to the value stored in the MPC table.
2115 */
2116 for (apic = 0; apic < nr_ioapics; apic++) {
2117
2118 /* Read the register 0 value */
2119 spin_lock_irqsave(&ioapic_lock, flags);
2120 reg_00.raw = io_apic_read(apic, 0);
2121 spin_unlock_irqrestore(&ioapic_lock, flags);
2122
2123 old_id = mp_ioapics[apic].apicid;
2124
2125 if (mp_ioapics[apic].apicid >= get_physical_broadcast()) {
2126 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2127 apic, mp_ioapics[apic].apicid);
2128 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2129 reg_00.bits.ID);
2130 mp_ioapics[apic].apicid = reg_00.bits.ID;
2131 }
2132
2133 /*
2134 * Sanity check, is the ID really free? Every APIC in a
2135 * system must have a unique ID or we get lots of nice
2136 * 'stuck on smp_invalidate_needed IPI wait' messages.
2137 */
2138 if (check_apicid_used(phys_id_present_map,
2139 mp_ioapics[apic].apicid)) {
2140 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2141 apic, mp_ioapics[apic].apicid);
2142 for (i = 0; i < get_physical_broadcast(); i++)
2143 if (!physid_isset(i, phys_id_present_map))
2144 break;
2145 if (i >= get_physical_broadcast())
2146 panic("Max APIC ID exceeded!\n");
2147 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2148 i);
2149 physid_set(i, phys_id_present_map);
2150 mp_ioapics[apic].apicid = i;
2151 } else {
2152 physid_mask_t tmp;
2153 tmp = apicid_to_cpu_present(mp_ioapics[apic].apicid);
2154 apic_printk(APIC_VERBOSE, "Setting %d in the "
2155 "phys_id_present_map\n",
2156 mp_ioapics[apic].apicid);
2157 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2158 }
2159
2160
2161 /*
2162 * We need to adjust the IRQ routing table
2163 * if the ID changed.
2164 */
2165 if (old_id != mp_ioapics[apic].apicid)
2166 for (i = 0; i < mp_irq_entries; i++)
2167 if (mp_irqs[i].dstapic == old_id)
2168 mp_irqs[i].dstapic
2169 = mp_ioapics[apic].apicid;
2170
2171 /*
2172 * Read the right value from the MPC table and
2173 * write it into the ID register.
2174 */
2175 apic_printk(APIC_VERBOSE, KERN_INFO
2176 "...changing IO-APIC physical APIC ID to %d ...",
2177 mp_ioapics[apic].apicid);
2178
2179 reg_00.bits.ID = mp_ioapics[apic].apicid;
2180 spin_lock_irqsave(&ioapic_lock, flags);
2181 io_apic_write(apic, 0, reg_00.raw);
2182 spin_unlock_irqrestore(&ioapic_lock, flags);
2183
2184 /*
2185 * Sanity check
2186 */
2187 spin_lock_irqsave(&ioapic_lock, flags);
2188 reg_00.raw = io_apic_read(apic, 0);
2189 spin_unlock_irqrestore(&ioapic_lock, flags);
2190 if (reg_00.bits.ID != mp_ioapics[apic].apicid)
2191 printk("could not set ID!\n");
2192 else
2193 apic_printk(APIC_VERBOSE, " ok.\n");
2194 }
2195 }
2196 #endif
2197
2198 int no_timer_check __initdata;
2199
2200 static int __init notimercheck(char *s)
2201 {
2202 no_timer_check = 1;
2203 return 1;
2204 }
2205 __setup("no_timer_check", notimercheck);
2206
2207 /*
2208 * There is a nasty bug in some older SMP boards, their mptable lies
2209 * about the timer IRQ. We do the following to work around the situation:
2210 *
2211 * - timer IRQ defaults to IO-APIC IRQ
2212 * - if this function detects that timer IRQs are defunct, then we fall
2213 * back to ISA timer IRQs
2214 */
2215 static int __init timer_irq_works(void)
2216 {
2217 unsigned long t1 = jiffies;
2218 unsigned long flags;
2219
2220 if (no_timer_check)
2221 return 1;
2222
2223 local_save_flags(flags);
2224 local_irq_enable();
2225 /* Let ten ticks pass... */
2226 mdelay((10 * 1000) / HZ);
2227 local_irq_restore(flags);
2228
2229 /*
2230 * Expect a few ticks at least, to be sure some possible
2231 * glue logic does not lock up after one or two first
2232 * ticks in a non-ExtINT mode. Also the local APIC
2233 * might have cached one ExtINT interrupt. Finally, at
2234 * least one tick may be lost due to delays.
2235 */
2236
2237 /* jiffies wrap? */
2238 if (time_after(jiffies, t1 + 4))
2239 return 1;
2240 return 0;
2241 }
2242
2243 /*
2244 * In the SMP+IOAPIC case it might happen that there are an unspecified
2245 * number of pending IRQ events unhandled. These cases are very rare,
2246 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2247 * better to do it this way as thus we do not have to be aware of
2248 * 'pending' interrupts in the IRQ path, except at this point.
2249 */
2250 /*
2251 * Edge triggered needs to resend any interrupt
2252 * that was delayed but this is now handled in the device
2253 * independent code.
2254 */
2255
2256 /*
2257 * Starting up a edge-triggered IO-APIC interrupt is
2258 * nasty - we need to make sure that we get the edge.
2259 * If it is already asserted for some reason, we need
2260 * return 1 to indicate that is was pending.
2261 *
2262 * This is not complete - we should be able to fake
2263 * an edge even if it isn't on the 8259A...
2264 */
2265
2266 static unsigned int startup_ioapic_irq(unsigned int irq)
2267 {
2268 int was_pending = 0;
2269 unsigned long flags;
2270 struct irq_cfg *cfg;
2271
2272 spin_lock_irqsave(&ioapic_lock, flags);
2273 if (irq < NR_IRQS_LEGACY) {
2274 disable_8259A_irq(irq);
2275 if (i8259A_irq_pending(irq))
2276 was_pending = 1;
2277 }
2278 cfg = irq_cfg(irq);
2279 __unmask_IO_APIC_irq(cfg);
2280 spin_unlock_irqrestore(&ioapic_lock, flags);
2281
2282 return was_pending;
2283 }
2284
2285 #ifdef CONFIG_X86_64
2286 static int ioapic_retrigger_irq(unsigned int irq)
2287 {
2288
2289 struct irq_cfg *cfg = irq_cfg(irq);
2290 unsigned long flags;
2291
2292 spin_lock_irqsave(&vector_lock, flags);
2293 send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2294 spin_unlock_irqrestore(&vector_lock, flags);
2295
2296 return 1;
2297 }
2298 #else
2299 static int ioapic_retrigger_irq(unsigned int irq)
2300 {
2301 send_IPI_self(irq_cfg(irq)->vector);
2302
2303 return 1;
2304 }
2305 #endif
2306
2307 /*
2308 * Level and edge triggered IO-APIC interrupts need different handling,
2309 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2310 * handled with the level-triggered descriptor, but that one has slightly
2311 * more overhead. Level-triggered interrupts cannot be handled with the
2312 * edge-triggered handler, without risking IRQ storms and other ugly
2313 * races.
2314 */
2315
2316 #ifdef CONFIG_SMP
2317
2318 #ifdef CONFIG_INTR_REMAP
2319 static void ir_irq_migration(struct work_struct *work);
2320
2321 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2322
2323 /*
2324 * Migrate the IO-APIC irq in the presence of intr-remapping.
2325 *
2326 * For edge triggered, irq migration is a simple atomic update(of vector
2327 * and cpu destination) of IRTE and flush the hardware cache.
2328 *
2329 * For level triggered, we need to modify the io-apic RTE aswell with the update
2330 * vector information, along with modifying IRTE with vector and destination.
2331 * So irq migration for level triggered is little bit more complex compared to
2332 * edge triggered migration. But the good news is, we use the same algorithm
2333 * for level triggered migration as we have today, only difference being,
2334 * we now initiate the irq migration from process context instead of the
2335 * interrupt context.
2336 *
2337 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2338 * suppression) to the IO-APIC, level triggered irq migration will also be
2339 * as simple as edge triggered migration and we can do the irq migration
2340 * with a simple atomic update to IO-APIC RTE.
2341 */
2342 static void
2343 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2344 {
2345 struct irq_cfg *cfg;
2346 struct irte irte;
2347 int modify_ioapic_rte;
2348 unsigned int dest;
2349 unsigned long flags;
2350 unsigned int irq;
2351
2352 if (!cpumask_intersects(mask, cpu_online_mask))
2353 return;
2354
2355 irq = desc->irq;
2356 if (get_irte(irq, &irte))
2357 return;
2358
2359 cfg = desc->chip_data;
2360 if (assign_irq_vector(irq, cfg, mask))
2361 return;
2362
2363 set_extra_move_desc(desc, mask);
2364
2365 dest = cpu_mask_to_apicid_and(cfg->domain, mask);
2366
2367 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2368 if (modify_ioapic_rte) {
2369 spin_lock_irqsave(&ioapic_lock, flags);
2370 __target_IO_APIC_irq(irq, dest, cfg);
2371 spin_unlock_irqrestore(&ioapic_lock, flags);
2372 }
2373
2374 irte.vector = cfg->vector;
2375 irte.dest_id = IRTE_DEST(dest);
2376
2377 /*
2378 * Modified the IRTE and flushes the Interrupt entry cache.
2379 */
2380 modify_irte(irq, &irte);
2381
2382 if (cfg->move_in_progress)
2383 send_cleanup_vector(cfg);
2384
2385 cpumask_copy(desc->affinity, mask);
2386 }
2387
2388 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2389 {
2390 int ret = -1;
2391 struct irq_cfg *cfg = desc->chip_data;
2392
2393 mask_IO_APIC_irq_desc(desc);
2394
2395 if (io_apic_level_ack_pending(cfg)) {
2396 /*
2397 * Interrupt in progress. Migrating irq now will change the
2398 * vector information in the IO-APIC RTE and that will confuse
2399 * the EOI broadcast performed by cpu.
2400 * So, delay the irq migration to the next instance.
2401 */
2402 schedule_delayed_work(&ir_migration_work, 1);
2403 goto unmask;
2404 }
2405
2406 /* everthing is clear. we have right of way */
2407 migrate_ioapic_irq_desc(desc, desc->pending_mask);
2408
2409 ret = 0;
2410 desc->status &= ~IRQ_MOVE_PENDING;
2411 cpumask_clear(desc->pending_mask);
2412
2413 unmask:
2414 unmask_IO_APIC_irq_desc(desc);
2415
2416 return ret;
2417 }
2418
2419 static void ir_irq_migration(struct work_struct *work)
2420 {
2421 unsigned int irq;
2422 struct irq_desc *desc;
2423
2424 for_each_irq_desc(irq, desc) {
2425 if (desc->status & IRQ_MOVE_PENDING) {
2426 unsigned long flags;
2427
2428 spin_lock_irqsave(&desc->lock, flags);
2429 if (!desc->chip->set_affinity ||
2430 !(desc->status & IRQ_MOVE_PENDING)) {
2431 desc->status &= ~IRQ_MOVE_PENDING;
2432 spin_unlock_irqrestore(&desc->lock, flags);
2433 continue;
2434 }
2435
2436 desc->chip->set_affinity(irq, desc->pending_mask);
2437 spin_unlock_irqrestore(&desc->lock, flags);
2438 }
2439 }
2440 }
2441
2442 /*
2443 * Migrates the IRQ destination in the process context.
2444 */
2445 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2446 const struct cpumask *mask)
2447 {
2448 if (desc->status & IRQ_LEVEL) {
2449 desc->status |= IRQ_MOVE_PENDING;
2450 cpumask_copy(desc->pending_mask, mask);
2451 migrate_irq_remapped_level_desc(desc);
2452 return;
2453 }
2454
2455 migrate_ioapic_irq_desc(desc, mask);
2456 }
2457 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2458 const struct cpumask *mask)
2459 {
2460 struct irq_desc *desc = irq_to_desc(irq);
2461
2462 set_ir_ioapic_affinity_irq_desc(desc, mask);
2463 }
2464 #endif
2465
2466 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2467 {
2468 unsigned vector, me;
2469
2470 ack_APIC_irq();
2471 exit_idle();
2472 irq_enter();
2473
2474 me = smp_processor_id();
2475 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2476 unsigned int irq;
2477 struct irq_desc *desc;
2478 struct irq_cfg *cfg;
2479 irq = __get_cpu_var(vector_irq)[vector];
2480
2481 if (irq == -1)
2482 continue;
2483
2484 desc = irq_to_desc(irq);
2485 if (!desc)
2486 continue;
2487
2488 cfg = irq_cfg(irq);
2489 spin_lock(&desc->lock);
2490 if (!cfg->move_cleanup_count)
2491 goto unlock;
2492
2493 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2494 goto unlock;
2495
2496 __get_cpu_var(vector_irq)[vector] = -1;
2497 cfg->move_cleanup_count--;
2498 unlock:
2499 spin_unlock(&desc->lock);
2500 }
2501
2502 irq_exit();
2503 }
2504
2505 static void irq_complete_move(struct irq_desc **descp)
2506 {
2507 struct irq_desc *desc = *descp;
2508 struct irq_cfg *cfg = desc->chip_data;
2509 unsigned vector, me;
2510
2511 if (likely(!cfg->move_in_progress)) {
2512 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2513 if (likely(!cfg->move_desc_pending))
2514 return;
2515
2516 /* domain has not changed, but affinity did */
2517 me = smp_processor_id();
2518 if (cpumask_test_cpu(me, desc->affinity)) {
2519 *descp = desc = move_irq_desc(desc, me);
2520 /* get the new one */
2521 cfg = desc->chip_data;
2522 cfg->move_desc_pending = 0;
2523 }
2524 #endif
2525 return;
2526 }
2527
2528 vector = ~get_irq_regs()->orig_ax;
2529 me = smp_processor_id();
2530
2531 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2532 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2533 *descp = desc = move_irq_desc(desc, me);
2534 /* get the new one */
2535 cfg = desc->chip_data;
2536 #endif
2537 send_cleanup_vector(cfg);
2538 }
2539 }
2540 #else
2541 static inline void irq_complete_move(struct irq_desc **descp) {}
2542 #endif
2543
2544 #ifdef CONFIG_INTR_REMAP
2545 static void ack_x2apic_level(unsigned int irq)
2546 {
2547 ack_x2APIC_irq();
2548 }
2549
2550 static void ack_x2apic_edge(unsigned int irq)
2551 {
2552 ack_x2APIC_irq();
2553 }
2554
2555 #endif
2556
2557 static void ack_apic_edge(unsigned int irq)
2558 {
2559 struct irq_desc *desc = irq_to_desc(irq);
2560
2561 irq_complete_move(&desc);
2562 move_native_irq(irq);
2563 ack_APIC_irq();
2564 }
2565
2566 atomic_t irq_mis_count;
2567
2568 static void ack_apic_level(unsigned int irq)
2569 {
2570 struct irq_desc *desc = irq_to_desc(irq);
2571
2572 #ifdef CONFIG_X86_32
2573 unsigned long v;
2574 int i;
2575 #endif
2576 struct irq_cfg *cfg;
2577 int do_unmask_irq = 0;
2578
2579 irq_complete_move(&desc);
2580 #ifdef CONFIG_GENERIC_PENDING_IRQ
2581 /* If we are moving the irq we need to mask it */
2582 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2583 do_unmask_irq = 1;
2584 mask_IO_APIC_irq_desc(desc);
2585 }
2586 #endif
2587
2588 #ifdef CONFIG_X86_32
2589 /*
2590 * It appears there is an erratum which affects at least version 0x11
2591 * of I/O APIC (that's the 82093AA and cores integrated into various
2592 * chipsets). Under certain conditions a level-triggered interrupt is
2593 * erroneously delivered as edge-triggered one but the respective IRR
2594 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2595 * message but it will never arrive and further interrupts are blocked
2596 * from the source. The exact reason is so far unknown, but the
2597 * phenomenon was observed when two consecutive interrupt requests
2598 * from a given source get delivered to the same CPU and the source is
2599 * temporarily disabled in between.
2600 *
2601 * A workaround is to simulate an EOI message manually. We achieve it
2602 * by setting the trigger mode to edge and then to level when the edge
2603 * trigger mode gets detected in the TMR of a local APIC for a
2604 * level-triggered interrupt. We mask the source for the time of the
2605 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2606 * The idea is from Manfred Spraul. --macro
2607 */
2608 cfg = desc->chip_data;
2609 i = cfg->vector;
2610
2611 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2612 #endif
2613
2614 /*
2615 * We must acknowledge the irq before we move it or the acknowledge will
2616 * not propagate properly.
2617 */
2618 ack_APIC_irq();
2619
2620 /* Now we can move and renable the irq */
2621 if (unlikely(do_unmask_irq)) {
2622 /* Only migrate the irq if the ack has been received.
2623 *
2624 * On rare occasions the broadcast level triggered ack gets
2625 * delayed going to ioapics, and if we reprogram the
2626 * vector while Remote IRR is still set the irq will never
2627 * fire again.
2628 *
2629 * To prevent this scenario we read the Remote IRR bit
2630 * of the ioapic. This has two effects.
2631 * - On any sane system the read of the ioapic will
2632 * flush writes (and acks) going to the ioapic from
2633 * this cpu.
2634 * - We get to see if the ACK has actually been delivered.
2635 *
2636 * Based on failed experiments of reprogramming the
2637 * ioapic entry from outside of irq context starting
2638 * with masking the ioapic entry and then polling until
2639 * Remote IRR was clear before reprogramming the
2640 * ioapic I don't trust the Remote IRR bit to be
2641 * completey accurate.
2642 *
2643 * However there appears to be no other way to plug
2644 * this race, so if the Remote IRR bit is not
2645 * accurate and is causing problems then it is a hardware bug
2646 * and you can go talk to the chipset vendor about it.
2647 */
2648 cfg = desc->chip_data;
2649 if (!io_apic_level_ack_pending(cfg))
2650 move_masked_irq(irq);
2651 unmask_IO_APIC_irq_desc(desc);
2652 }
2653
2654 #ifdef CONFIG_X86_32
2655 if (!(v & (1 << (i & 0x1f)))) {
2656 atomic_inc(&irq_mis_count);
2657 spin_lock(&ioapic_lock);
2658 __mask_and_edge_IO_APIC_irq(cfg);
2659 __unmask_and_level_IO_APIC_irq(cfg);
2660 spin_unlock(&ioapic_lock);
2661 }
2662 #endif
2663 }
2664
2665 static struct irq_chip ioapic_chip __read_mostly = {
2666 .name = "IO-APIC",
2667 .startup = startup_ioapic_irq,
2668 .mask = mask_IO_APIC_irq,
2669 .unmask = unmask_IO_APIC_irq,
2670 .ack = ack_apic_edge,
2671 .eoi = ack_apic_level,
2672 #ifdef CONFIG_SMP
2673 .set_affinity = set_ioapic_affinity_irq,
2674 #endif
2675 .retrigger = ioapic_retrigger_irq,
2676 };
2677
2678 #ifdef CONFIG_INTR_REMAP
2679 static struct irq_chip ir_ioapic_chip __read_mostly = {
2680 .name = "IR-IO-APIC",
2681 .startup = startup_ioapic_irq,
2682 .mask = mask_IO_APIC_irq,
2683 .unmask = unmask_IO_APIC_irq,
2684 .ack = ack_x2apic_edge,
2685 .eoi = ack_x2apic_level,
2686 #ifdef CONFIG_SMP
2687 .set_affinity = set_ir_ioapic_affinity_irq,
2688 #endif
2689 .retrigger = ioapic_retrigger_irq,
2690 };
2691 #endif
2692
2693 static inline void init_IO_APIC_traps(void)
2694 {
2695 int irq;
2696 struct irq_desc *desc;
2697 struct irq_cfg *cfg;
2698
2699 /*
2700 * NOTE! The local APIC isn't very good at handling
2701 * multiple interrupts at the same interrupt level.
2702 * As the interrupt level is determined by taking the
2703 * vector number and shifting that right by 4, we
2704 * want to spread these out a bit so that they don't
2705 * all fall in the same interrupt level.
2706 *
2707 * Also, we've got to be careful not to trash gate
2708 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2709 */
2710 for_each_irq_desc(irq, desc) {
2711 cfg = desc->chip_data;
2712 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2713 /*
2714 * Hmm.. We don't have an entry for this,
2715 * so default to an old-fashioned 8259
2716 * interrupt if we can..
2717 */
2718 if (irq < NR_IRQS_LEGACY)
2719 make_8259A_irq(irq);
2720 else
2721 /* Strange. Oh, well.. */
2722 desc->chip = &no_irq_chip;
2723 }
2724 }
2725 }
2726
2727 /*
2728 * The local APIC irq-chip implementation:
2729 */
2730
2731 static void mask_lapic_irq(unsigned int irq)
2732 {
2733 unsigned long v;
2734
2735 v = apic_read(APIC_LVT0);
2736 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2737 }
2738
2739 static void unmask_lapic_irq(unsigned int irq)
2740 {
2741 unsigned long v;
2742
2743 v = apic_read(APIC_LVT0);
2744 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2745 }
2746
2747 static void ack_lapic_irq(unsigned int irq)
2748 {
2749 ack_APIC_irq();
2750 }
2751
2752 static struct irq_chip lapic_chip __read_mostly = {
2753 .name = "local-APIC",
2754 .mask = mask_lapic_irq,
2755 .unmask = unmask_lapic_irq,
2756 .ack = ack_lapic_irq,
2757 };
2758
2759 static void lapic_register_intr(int irq, struct irq_desc *desc)
2760 {
2761 desc->status &= ~IRQ_LEVEL;
2762 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2763 "edge");
2764 }
2765
2766 static void __init setup_nmi(void)
2767 {
2768 /*
2769 * Dirty trick to enable the NMI watchdog ...
2770 * We put the 8259A master into AEOI mode and
2771 * unmask on all local APICs LVT0 as NMI.
2772 *
2773 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2774 * is from Maciej W. Rozycki - so we do not have to EOI from
2775 * the NMI handler or the timer interrupt.
2776 */
2777 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2778
2779 enable_NMI_through_LVT0();
2780
2781 apic_printk(APIC_VERBOSE, " done.\n");
2782 }
2783
2784 /*
2785 * This looks a bit hackish but it's about the only one way of sending
2786 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2787 * not support the ExtINT mode, unfortunately. We need to send these
2788 * cycles as some i82489DX-based boards have glue logic that keeps the
2789 * 8259A interrupt line asserted until INTA. --macro
2790 */
2791 static inline void __init unlock_ExtINT_logic(void)
2792 {
2793 int apic, pin, i;
2794 struct IO_APIC_route_entry entry0, entry1;
2795 unsigned char save_control, save_freq_select;
2796
2797 pin = find_isa_irq_pin(8, mp_INT);
2798 if (pin == -1) {
2799 WARN_ON_ONCE(1);
2800 return;
2801 }
2802 apic = find_isa_irq_apic(8, mp_INT);
2803 if (apic == -1) {
2804 WARN_ON_ONCE(1);
2805 return;
2806 }
2807
2808 entry0 = ioapic_read_entry(apic, pin);
2809 clear_IO_APIC_pin(apic, pin);
2810
2811 memset(&entry1, 0, sizeof(entry1));
2812
2813 entry1.dest_mode = 0; /* physical delivery */
2814 entry1.mask = 0; /* unmask IRQ now */
2815 entry1.dest = hard_smp_processor_id();
2816 entry1.delivery_mode = dest_ExtINT;
2817 entry1.polarity = entry0.polarity;
2818 entry1.trigger = 0;
2819 entry1.vector = 0;
2820
2821 ioapic_write_entry(apic, pin, entry1);
2822
2823 save_control = CMOS_READ(RTC_CONTROL);
2824 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2825 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2826 RTC_FREQ_SELECT);
2827 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2828
2829 i = 100;
2830 while (i-- > 0) {
2831 mdelay(10);
2832 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2833 i -= 10;
2834 }
2835
2836 CMOS_WRITE(save_control, RTC_CONTROL);
2837 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2838 clear_IO_APIC_pin(apic, pin);
2839
2840 ioapic_write_entry(apic, pin, entry0);
2841 }
2842
2843 static int disable_timer_pin_1 __initdata;
2844 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2845 static int __init disable_timer_pin_setup(char *arg)
2846 {
2847 disable_timer_pin_1 = 1;
2848 return 0;
2849 }
2850 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2851
2852 int timer_through_8259 __initdata;
2853
2854 /*
2855 * This code may look a bit paranoid, but it's supposed to cooperate with
2856 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2857 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2858 * fanatically on his truly buggy board.
2859 *
2860 * FIXME: really need to revamp this for all platforms.
2861 */
2862 static inline void __init check_timer(void)
2863 {
2864 struct irq_desc *desc = irq_to_desc(0);
2865 struct irq_cfg *cfg = desc->chip_data;
2866 int cpu = boot_cpu_id;
2867 int apic1, pin1, apic2, pin2;
2868 unsigned long flags;
2869 unsigned int ver;
2870 int no_pin1 = 0;
2871
2872 local_irq_save(flags);
2873
2874 ver = apic_read(APIC_LVR);
2875 ver = GET_APIC_VERSION(ver);
2876
2877 /*
2878 * get/set the timer IRQ vector:
2879 */
2880 disable_8259A_irq(0);
2881 assign_irq_vector(0, cfg, TARGET_CPUS);
2882
2883 /*
2884 * As IRQ0 is to be enabled in the 8259A, the virtual
2885 * wire has to be disabled in the local APIC. Also
2886 * timer interrupts need to be acknowledged manually in
2887 * the 8259A for the i82489DX when using the NMI
2888 * watchdog as that APIC treats NMIs as level-triggered.
2889 * The AEOI mode will finish them in the 8259A
2890 * automatically.
2891 */
2892 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2893 init_8259A(1);
2894 #ifdef CONFIG_X86_32
2895 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2896 #endif
2897
2898 pin1 = find_isa_irq_pin(0, mp_INT);
2899 apic1 = find_isa_irq_apic(0, mp_INT);
2900 pin2 = ioapic_i8259.pin;
2901 apic2 = ioapic_i8259.apic;
2902
2903 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2904 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2905 cfg->vector, apic1, pin1, apic2, pin2);
2906
2907 /*
2908 * Some BIOS writers are clueless and report the ExtINTA
2909 * I/O APIC input from the cascaded 8259A as the timer
2910 * interrupt input. So just in case, if only one pin
2911 * was found above, try it both directly and through the
2912 * 8259A.
2913 */
2914 if (pin1 == -1) {
2915 #ifdef CONFIG_INTR_REMAP
2916 if (intr_remapping_enabled)
2917 panic("BIOS bug: timer not connected to IO-APIC");
2918 #endif
2919 pin1 = pin2;
2920 apic1 = apic2;
2921 no_pin1 = 1;
2922 } else if (pin2 == -1) {
2923 pin2 = pin1;
2924 apic2 = apic1;
2925 }
2926
2927 if (pin1 != -1) {
2928 /*
2929 * Ok, does IRQ0 through the IOAPIC work?
2930 */
2931 if (no_pin1) {
2932 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2933 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2934 }
2935 unmask_IO_APIC_irq_desc(desc);
2936 if (timer_irq_works()) {
2937 if (nmi_watchdog == NMI_IO_APIC) {
2938 setup_nmi();
2939 enable_8259A_irq(0);
2940 }
2941 if (disable_timer_pin_1 > 0)
2942 clear_IO_APIC_pin(0, pin1);
2943 goto out;
2944 }
2945 #ifdef CONFIG_INTR_REMAP
2946 if (intr_remapping_enabled)
2947 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2948 #endif
2949 clear_IO_APIC_pin(apic1, pin1);
2950 if (!no_pin1)
2951 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2952 "8254 timer not connected to IO-APIC\n");
2953
2954 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2955 "(IRQ0) through the 8259A ...\n");
2956 apic_printk(APIC_QUIET, KERN_INFO
2957 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2958 /*
2959 * legacy devices should be connected to IO APIC #0
2960 */
2961 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2962 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2963 unmask_IO_APIC_irq_desc(desc);
2964 enable_8259A_irq(0);
2965 if (timer_irq_works()) {
2966 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2967 timer_through_8259 = 1;
2968 if (nmi_watchdog == NMI_IO_APIC) {
2969 disable_8259A_irq(0);
2970 setup_nmi();
2971 enable_8259A_irq(0);
2972 }
2973 goto out;
2974 }
2975 /*
2976 * Cleanup, just in case ...
2977 */
2978 disable_8259A_irq(0);
2979 clear_IO_APIC_pin(apic2, pin2);
2980 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2981 }
2982
2983 if (nmi_watchdog == NMI_IO_APIC) {
2984 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2985 "through the IO-APIC - disabling NMI Watchdog!\n");
2986 nmi_watchdog = NMI_NONE;
2987 }
2988 #ifdef CONFIG_X86_32
2989 timer_ack = 0;
2990 #endif
2991
2992 apic_printk(APIC_QUIET, KERN_INFO
2993 "...trying to set up timer as Virtual Wire IRQ...\n");
2994
2995 lapic_register_intr(0, desc);
2996 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2997 enable_8259A_irq(0);
2998
2999 if (timer_irq_works()) {
3000 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3001 goto out;
3002 }
3003 disable_8259A_irq(0);
3004 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3005 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3006
3007 apic_printk(APIC_QUIET, KERN_INFO
3008 "...trying to set up timer as ExtINT IRQ...\n");
3009
3010 init_8259A(0);
3011 make_8259A_irq(0);
3012 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3013
3014 unlock_ExtINT_logic();
3015
3016 if (timer_irq_works()) {
3017 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3018 goto out;
3019 }
3020 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3021 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3022 "report. Then try booting with the 'noapic' option.\n");
3023 out:
3024 local_irq_restore(flags);
3025 }
3026
3027 /*
3028 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3029 * to devices. However there may be an I/O APIC pin available for
3030 * this interrupt regardless. The pin may be left unconnected, but
3031 * typically it will be reused as an ExtINT cascade interrupt for
3032 * the master 8259A. In the MPS case such a pin will normally be
3033 * reported as an ExtINT interrupt in the MP table. With ACPI
3034 * there is no provision for ExtINT interrupts, and in the absence
3035 * of an override it would be treated as an ordinary ISA I/O APIC
3036 * interrupt, that is edge-triggered and unmasked by default. We
3037 * used to do this, but it caused problems on some systems because
3038 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3039 * the same ExtINT cascade interrupt to drive the local APIC of the
3040 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3041 * the I/O APIC in all cases now. No actual device should request
3042 * it anyway. --macro
3043 */
3044 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3045
3046 void __init setup_IO_APIC(void)
3047 {
3048
3049 #ifdef CONFIG_X86_32
3050 enable_IO_APIC();
3051 #else
3052 /*
3053 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3054 */
3055 #endif
3056
3057 io_apic_irqs = ~PIC_IRQS;
3058
3059 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3060 /*
3061 * Set up IO-APIC IRQ routing.
3062 */
3063 #ifdef CONFIG_X86_32
3064 if (!acpi_ioapic)
3065 setup_ioapic_ids_from_mpc();
3066 #endif
3067 sync_Arb_IDs();
3068 setup_IO_APIC_irqs();
3069 init_IO_APIC_traps();
3070 check_timer();
3071 }
3072
3073 /*
3074 * Called after all the initialization is done. If we didnt find any
3075 * APIC bugs then we can allow the modify fast path
3076 */
3077
3078 static int __init io_apic_bug_finalize(void)
3079 {
3080 if (sis_apic_bug == -1)
3081 sis_apic_bug = 0;
3082 return 0;
3083 }
3084
3085 late_initcall(io_apic_bug_finalize);
3086
3087 struct sysfs_ioapic_data {
3088 struct sys_device dev;
3089 struct IO_APIC_route_entry entry[0];
3090 };
3091 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3092
3093 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3094 {
3095 struct IO_APIC_route_entry *entry;
3096 struct sysfs_ioapic_data *data;
3097 int i;
3098
3099 data = container_of(dev, struct sysfs_ioapic_data, dev);
3100 entry = data->entry;
3101 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3102 *entry = ioapic_read_entry(dev->id, i);
3103
3104 return 0;
3105 }
3106
3107 static int ioapic_resume(struct sys_device *dev)
3108 {
3109 struct IO_APIC_route_entry *entry;
3110 struct sysfs_ioapic_data *data;
3111 unsigned long flags;
3112 union IO_APIC_reg_00 reg_00;
3113 int i;
3114
3115 data = container_of(dev, struct sysfs_ioapic_data, dev);
3116 entry = data->entry;
3117
3118 spin_lock_irqsave(&ioapic_lock, flags);
3119 reg_00.raw = io_apic_read(dev->id, 0);
3120 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3121 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3122 io_apic_write(dev->id, 0, reg_00.raw);
3123 }
3124 spin_unlock_irqrestore(&ioapic_lock, flags);
3125 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3126 ioapic_write_entry(dev->id, i, entry[i]);
3127
3128 return 0;
3129 }
3130
3131 static struct sysdev_class ioapic_sysdev_class = {
3132 .name = "ioapic",
3133 .suspend = ioapic_suspend,
3134 .resume = ioapic_resume,
3135 };
3136
3137 static int __init ioapic_init_sysfs(void)
3138 {
3139 struct sys_device * dev;
3140 int i, size, error;
3141
3142 error = sysdev_class_register(&ioapic_sysdev_class);
3143 if (error)
3144 return error;
3145
3146 for (i = 0; i < nr_ioapics; i++ ) {
3147 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3148 * sizeof(struct IO_APIC_route_entry);
3149 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3150 if (!mp_ioapic_data[i]) {
3151 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3152 continue;
3153 }
3154 dev = &mp_ioapic_data[i]->dev;
3155 dev->id = i;
3156 dev->cls = &ioapic_sysdev_class;
3157 error = sysdev_register(dev);
3158 if (error) {
3159 kfree(mp_ioapic_data[i]);
3160 mp_ioapic_data[i] = NULL;
3161 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3162 continue;
3163 }
3164 }
3165
3166 return 0;
3167 }
3168
3169 device_initcall(ioapic_init_sysfs);
3170
3171 /*
3172 * Dynamic irq allocate and deallocation
3173 */
3174 unsigned int create_irq_nr(unsigned int irq_want)
3175 {
3176 /* Allocate an unused irq */
3177 unsigned int irq;
3178 unsigned int new;
3179 unsigned long flags;
3180 struct irq_cfg *cfg_new = NULL;
3181 int cpu = boot_cpu_id;
3182 struct irq_desc *desc_new = NULL;
3183
3184 irq = 0;
3185 spin_lock_irqsave(&vector_lock, flags);
3186 for (new = irq_want; new < nr_irqs; new++) {
3187 if (platform_legacy_irq(new))
3188 continue;
3189
3190 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3191 if (!desc_new) {
3192 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3193 continue;
3194 }
3195 cfg_new = desc_new->chip_data;
3196
3197 if (cfg_new->vector != 0)
3198 continue;
3199 if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0)
3200 irq = new;
3201 break;
3202 }
3203 spin_unlock_irqrestore(&vector_lock, flags);
3204
3205 if (irq > 0) {
3206 dynamic_irq_init(irq);
3207 /* restore it, in case dynamic_irq_init clear it */
3208 if (desc_new)
3209 desc_new->chip_data = cfg_new;
3210 }
3211 return irq;
3212 }
3213
3214 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3215 int create_irq(void)
3216 {
3217 unsigned int irq_want;
3218 int irq;
3219
3220 irq_want = nr_irqs_gsi;
3221 irq = create_irq_nr(irq_want);
3222
3223 if (irq == 0)
3224 irq = -1;
3225
3226 return irq;
3227 }
3228
3229 void destroy_irq(unsigned int irq)
3230 {
3231 unsigned long flags;
3232 struct irq_cfg *cfg;
3233 struct irq_desc *desc;
3234
3235 /* store it, in case dynamic_irq_cleanup clear it */
3236 desc = irq_to_desc(irq);
3237 cfg = desc->chip_data;
3238 dynamic_irq_cleanup(irq);
3239 /* connect back irq_cfg */
3240 if (desc)
3241 desc->chip_data = cfg;
3242
3243 #ifdef CONFIG_INTR_REMAP
3244 free_irte(irq);
3245 #endif
3246 spin_lock_irqsave(&vector_lock, flags);
3247 __clear_irq_vector(irq, cfg);
3248 spin_unlock_irqrestore(&vector_lock, flags);
3249 }
3250
3251 /*
3252 * MSI message composition
3253 */
3254 #ifdef CONFIG_PCI_MSI
3255 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3256 {
3257 struct irq_cfg *cfg;
3258 int err;
3259 unsigned dest;
3260
3261 if (disable_apic)
3262 return -ENXIO;
3263
3264 cfg = irq_cfg(irq);
3265 err = assign_irq_vector(irq, cfg, TARGET_CPUS);
3266 if (err)
3267 return err;
3268
3269 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
3270
3271 #ifdef CONFIG_INTR_REMAP
3272 if (irq_remapped(irq)) {
3273 struct irte irte;
3274 int ir_index;
3275 u16 sub_handle;
3276
3277 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3278 BUG_ON(ir_index == -1);
3279
3280 memset (&irte, 0, sizeof(irte));
3281
3282 irte.present = 1;
3283 irte.dst_mode = INT_DEST_MODE;
3284 irte.trigger_mode = 0; /* edge */
3285 irte.dlvry_mode = INT_DELIVERY_MODE;
3286 irte.vector = cfg->vector;
3287 irte.dest_id = IRTE_DEST(dest);
3288
3289 modify_irte(irq, &irte);
3290
3291 msg->address_hi = MSI_ADDR_BASE_HI;
3292 msg->data = sub_handle;
3293 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3294 MSI_ADDR_IR_SHV |
3295 MSI_ADDR_IR_INDEX1(ir_index) |
3296 MSI_ADDR_IR_INDEX2(ir_index);
3297 } else
3298 #endif
3299 {
3300 msg->address_hi = MSI_ADDR_BASE_HI;
3301 msg->address_lo =
3302 MSI_ADDR_BASE_LO |
3303 ((INT_DEST_MODE == 0) ?
3304 MSI_ADDR_DEST_MODE_PHYSICAL:
3305 MSI_ADDR_DEST_MODE_LOGICAL) |
3306 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3307 MSI_ADDR_REDIRECTION_CPU:
3308 MSI_ADDR_REDIRECTION_LOWPRI) |
3309 MSI_ADDR_DEST_ID(dest);
3310
3311 msg->data =
3312 MSI_DATA_TRIGGER_EDGE |
3313 MSI_DATA_LEVEL_ASSERT |
3314 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3315 MSI_DATA_DELIVERY_FIXED:
3316 MSI_DATA_DELIVERY_LOWPRI) |
3317 MSI_DATA_VECTOR(cfg->vector);
3318 }
3319 return err;
3320 }
3321
3322 #ifdef CONFIG_SMP
3323 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3324 {
3325 struct irq_desc *desc = irq_to_desc(irq);
3326 struct irq_cfg *cfg;
3327 struct msi_msg msg;
3328 unsigned int dest;
3329
3330 dest = set_desc_affinity(desc, mask);
3331 if (dest == BAD_APICID)
3332 return;
3333
3334 cfg = desc->chip_data;
3335
3336 read_msi_msg_desc(desc, &msg);
3337
3338 msg.data &= ~MSI_DATA_VECTOR_MASK;
3339 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3340 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3341 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3342
3343 write_msi_msg_desc(desc, &msg);
3344 }
3345 #ifdef CONFIG_INTR_REMAP
3346 /*
3347 * Migrate the MSI irq to another cpumask. This migration is
3348 * done in the process context using interrupt-remapping hardware.
3349 */
3350 static void
3351 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3352 {
3353 struct irq_desc *desc = irq_to_desc(irq);
3354 struct irq_cfg *cfg = desc->chip_data;
3355 unsigned int dest;
3356 struct irte irte;
3357
3358 if (get_irte(irq, &irte))
3359 return;
3360
3361 dest = set_desc_affinity(desc, mask);
3362 if (dest == BAD_APICID)
3363 return;
3364
3365 irte.vector = cfg->vector;
3366 irte.dest_id = IRTE_DEST(dest);
3367
3368 /*
3369 * atomically update the IRTE with the new destination and vector.
3370 */
3371 modify_irte(irq, &irte);
3372
3373 /*
3374 * After this point, all the interrupts will start arriving
3375 * at the new destination. So, time to cleanup the previous
3376 * vector allocation.
3377 */
3378 if (cfg->move_in_progress)
3379 send_cleanup_vector(cfg);
3380 }
3381
3382 #endif
3383 #endif /* CONFIG_SMP */
3384
3385 /*
3386 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3387 * which implement the MSI or MSI-X Capability Structure.
3388 */
3389 static struct irq_chip msi_chip = {
3390 .name = "PCI-MSI",
3391 .unmask = unmask_msi_irq,
3392 .mask = mask_msi_irq,
3393 .ack = ack_apic_edge,
3394 #ifdef CONFIG_SMP
3395 .set_affinity = set_msi_irq_affinity,
3396 #endif
3397 .retrigger = ioapic_retrigger_irq,
3398 };
3399
3400 #ifdef CONFIG_INTR_REMAP
3401 static struct irq_chip msi_ir_chip = {
3402 .name = "IR-PCI-MSI",
3403 .unmask = unmask_msi_irq,
3404 .mask = mask_msi_irq,
3405 .ack = ack_x2apic_edge,
3406 #ifdef CONFIG_SMP
3407 .set_affinity = ir_set_msi_irq_affinity,
3408 #endif
3409 .retrigger = ioapic_retrigger_irq,
3410 };
3411
3412 /*
3413 * Map the PCI dev to the corresponding remapping hardware unit
3414 * and allocate 'nvec' consecutive interrupt-remapping table entries
3415 * in it.
3416 */
3417 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3418 {
3419 struct intel_iommu *iommu;
3420 int index;
3421
3422 iommu = map_dev_to_ir(dev);
3423 if (!iommu) {
3424 printk(KERN_ERR
3425 "Unable to map PCI %s to iommu\n", pci_name(dev));
3426 return -ENOENT;
3427 }
3428
3429 index = alloc_irte(iommu, irq, nvec);
3430 if (index < 0) {
3431 printk(KERN_ERR
3432 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3433 pci_name(dev));
3434 return -ENOSPC;
3435 }
3436 return index;
3437 }
3438 #endif
3439
3440 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3441 {
3442 int ret;
3443 struct msi_msg msg;
3444
3445 ret = msi_compose_msg(dev, irq, &msg);
3446 if (ret < 0)
3447 return ret;
3448
3449 set_irq_msi(irq, msidesc);
3450 write_msi_msg(irq, &msg);
3451
3452 #ifdef CONFIG_INTR_REMAP
3453 if (irq_remapped(irq)) {
3454 struct irq_desc *desc = irq_to_desc(irq);
3455 /*
3456 * irq migration in process context
3457 */
3458 desc->status |= IRQ_MOVE_PCNTXT;
3459 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3460 } else
3461 #endif
3462 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3463
3464 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3465
3466 return 0;
3467 }
3468
3469 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3470 {
3471 unsigned int irq;
3472 int ret, sub_handle;
3473 struct msi_desc *msidesc;
3474 unsigned int irq_want;
3475
3476 #ifdef CONFIG_INTR_REMAP
3477 struct intel_iommu *iommu = 0;
3478 int index = 0;
3479 #endif
3480
3481 irq_want = nr_irqs_gsi;
3482 sub_handle = 0;
3483 list_for_each_entry(msidesc, &dev->msi_list, list) {
3484 irq = create_irq_nr(irq_want);
3485 irq_want++;
3486 if (irq == 0)
3487 return -1;
3488 #ifdef CONFIG_INTR_REMAP
3489 if (!intr_remapping_enabled)
3490 goto no_ir;
3491
3492 if (!sub_handle) {
3493 /*
3494 * allocate the consecutive block of IRTE's
3495 * for 'nvec'
3496 */
3497 index = msi_alloc_irte(dev, irq, nvec);
3498 if (index < 0) {
3499 ret = index;
3500 goto error;
3501 }
3502 } else {
3503 iommu = map_dev_to_ir(dev);
3504 if (!iommu) {
3505 ret = -ENOENT;
3506 goto error;
3507 }
3508 /*
3509 * setup the mapping between the irq and the IRTE
3510 * base index, the sub_handle pointing to the
3511 * appropriate interrupt remap table entry.
3512 */
3513 set_irte_irq(irq, iommu, index, sub_handle);
3514 }
3515 no_ir:
3516 #endif
3517 ret = setup_msi_irq(dev, msidesc, irq);
3518 if (ret < 0)
3519 goto error;
3520 sub_handle++;
3521 }
3522 return 0;
3523
3524 error:
3525 destroy_irq(irq);
3526 return ret;
3527 }
3528
3529 void arch_teardown_msi_irq(unsigned int irq)
3530 {
3531 destroy_irq(irq);
3532 }
3533
3534 #ifdef CONFIG_DMAR
3535 #ifdef CONFIG_SMP
3536 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3537 {
3538 struct irq_desc *desc = irq_to_desc(irq);
3539 struct irq_cfg *cfg;
3540 struct msi_msg msg;
3541 unsigned int dest;
3542
3543 dest = set_desc_affinity(desc, mask);
3544 if (dest == BAD_APICID)
3545 return;
3546
3547 cfg = desc->chip_data;
3548
3549 dmar_msi_read(irq, &msg);
3550
3551 msg.data &= ~MSI_DATA_VECTOR_MASK;
3552 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3553 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3554 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3555
3556 dmar_msi_write(irq, &msg);
3557 }
3558
3559 #endif /* CONFIG_SMP */
3560
3561 struct irq_chip dmar_msi_type = {
3562 .name = "DMAR_MSI",
3563 .unmask = dmar_msi_unmask,
3564 .mask = dmar_msi_mask,
3565 .ack = ack_apic_edge,
3566 #ifdef CONFIG_SMP
3567 .set_affinity = dmar_msi_set_affinity,
3568 #endif
3569 .retrigger = ioapic_retrigger_irq,
3570 };
3571
3572 int arch_setup_dmar_msi(unsigned int irq)
3573 {
3574 int ret;
3575 struct msi_msg msg;
3576
3577 ret = msi_compose_msg(NULL, irq, &msg);
3578 if (ret < 0)
3579 return ret;
3580 dmar_msi_write(irq, &msg);
3581 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3582 "edge");
3583 return 0;
3584 }
3585 #endif
3586
3587 #ifdef CONFIG_HPET_TIMER
3588
3589 #ifdef CONFIG_SMP
3590 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3591 {
3592 struct irq_desc *desc = irq_to_desc(irq);
3593 struct irq_cfg *cfg;
3594 struct msi_msg msg;
3595 unsigned int dest;
3596
3597 dest = set_desc_affinity(desc, mask);
3598 if (dest == BAD_APICID)
3599 return;
3600
3601 cfg = desc->chip_data;
3602
3603 hpet_msi_read(irq, &msg);
3604
3605 msg.data &= ~MSI_DATA_VECTOR_MASK;
3606 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3607 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3608 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3609
3610 hpet_msi_write(irq, &msg);
3611 }
3612
3613 #endif /* CONFIG_SMP */
3614
3615 struct irq_chip hpet_msi_type = {
3616 .name = "HPET_MSI",
3617 .unmask = hpet_msi_unmask,
3618 .mask = hpet_msi_mask,
3619 .ack = ack_apic_edge,
3620 #ifdef CONFIG_SMP
3621 .set_affinity = hpet_msi_set_affinity,
3622 #endif
3623 .retrigger = ioapic_retrigger_irq,
3624 };
3625
3626 int arch_setup_hpet_msi(unsigned int irq)
3627 {
3628 int ret;
3629 struct msi_msg msg;
3630
3631 ret = msi_compose_msg(NULL, irq, &msg);
3632 if (ret < 0)
3633 return ret;
3634
3635 hpet_msi_write(irq, &msg);
3636 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3637 "edge");
3638
3639 return 0;
3640 }
3641 #endif
3642
3643 #endif /* CONFIG_PCI_MSI */
3644 /*
3645 * Hypertransport interrupt support
3646 */
3647 #ifdef CONFIG_HT_IRQ
3648
3649 #ifdef CONFIG_SMP
3650
3651 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3652 {
3653 struct ht_irq_msg msg;
3654 fetch_ht_irq_msg(irq, &msg);
3655
3656 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3657 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3658
3659 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3660 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3661
3662 write_ht_irq_msg(irq, &msg);
3663 }
3664
3665 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3666 {
3667 struct irq_desc *desc = irq_to_desc(irq);
3668 struct irq_cfg *cfg;
3669 unsigned int dest;
3670
3671 dest = set_desc_affinity(desc, mask);
3672 if (dest == BAD_APICID)
3673 return;
3674
3675 cfg = desc->chip_data;
3676
3677 target_ht_irq(irq, dest, cfg->vector);
3678 }
3679
3680 #endif
3681
3682 static struct irq_chip ht_irq_chip = {
3683 .name = "PCI-HT",
3684 .mask = mask_ht_irq,
3685 .unmask = unmask_ht_irq,
3686 .ack = ack_apic_edge,
3687 #ifdef CONFIG_SMP
3688 .set_affinity = set_ht_irq_affinity,
3689 #endif
3690 .retrigger = ioapic_retrigger_irq,
3691 };
3692
3693 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3694 {
3695 struct irq_cfg *cfg;
3696 int err;
3697
3698 if (disable_apic)
3699 return -ENXIO;
3700
3701 cfg = irq_cfg(irq);
3702 err = assign_irq_vector(irq, cfg, TARGET_CPUS);
3703 if (!err) {
3704 struct ht_irq_msg msg;
3705 unsigned dest;
3706
3707 dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
3708
3709 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3710
3711 msg.address_lo =
3712 HT_IRQ_LOW_BASE |
3713 HT_IRQ_LOW_DEST_ID(dest) |
3714 HT_IRQ_LOW_VECTOR(cfg->vector) |
3715 ((INT_DEST_MODE == 0) ?
3716 HT_IRQ_LOW_DM_PHYSICAL :
3717 HT_IRQ_LOW_DM_LOGICAL) |
3718 HT_IRQ_LOW_RQEOI_EDGE |
3719 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3720 HT_IRQ_LOW_MT_FIXED :
3721 HT_IRQ_LOW_MT_ARBITRATED) |
3722 HT_IRQ_LOW_IRQ_MASKED;
3723
3724 write_ht_irq_msg(irq, &msg);
3725
3726 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3727 handle_edge_irq, "edge");
3728
3729 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3730 }
3731 return err;
3732 }
3733 #endif /* CONFIG_HT_IRQ */
3734
3735 #ifdef CONFIG_X86_UV
3736 /*
3737 * Re-target the irq to the specified CPU and enable the specified MMR located
3738 * on the specified blade to allow the sending of MSIs to the specified CPU.
3739 */
3740 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3741 unsigned long mmr_offset)
3742 {
3743 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3744 struct irq_cfg *cfg;
3745 int mmr_pnode;
3746 unsigned long mmr_value;
3747 struct uv_IO_APIC_route_entry *entry;
3748 unsigned long flags;
3749 int err;
3750
3751 cfg = irq_cfg(irq);
3752
3753 err = assign_irq_vector(irq, cfg, eligible_cpu);
3754 if (err != 0)
3755 return err;
3756
3757 spin_lock_irqsave(&vector_lock, flags);
3758 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3759 irq_name);
3760 spin_unlock_irqrestore(&vector_lock, flags);
3761
3762 mmr_value = 0;
3763 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3764 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3765
3766 entry->vector = cfg->vector;
3767 entry->delivery_mode = INT_DELIVERY_MODE;
3768 entry->dest_mode = INT_DEST_MODE;
3769 entry->polarity = 0;
3770 entry->trigger = 0;
3771 entry->mask = 0;
3772 entry->dest = cpu_mask_to_apicid(eligible_cpu);
3773
3774 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3775 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3776
3777 return irq;
3778 }
3779
3780 /*
3781 * Disable the specified MMR located on the specified blade so that MSIs are
3782 * longer allowed to be sent.
3783 */
3784 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3785 {
3786 unsigned long mmr_value;
3787 struct uv_IO_APIC_route_entry *entry;
3788 int mmr_pnode;
3789
3790 mmr_value = 0;
3791 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3792 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3793
3794 entry->mask = 1;
3795
3796 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3797 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3798 }
3799 #endif /* CONFIG_X86_64 */
3800
3801 int __init io_apic_get_redir_entries (int ioapic)
3802 {
3803 union IO_APIC_reg_01 reg_01;
3804 unsigned long flags;
3805
3806 spin_lock_irqsave(&ioapic_lock, flags);
3807 reg_01.raw = io_apic_read(ioapic, 1);
3808 spin_unlock_irqrestore(&ioapic_lock, flags);
3809
3810 return reg_01.bits.entries;
3811 }
3812
3813 void __init probe_nr_irqs_gsi(void)
3814 {
3815 int idx;
3816 int nr = 0;
3817
3818 for (idx = 0; idx < nr_ioapics; idx++)
3819 nr += io_apic_get_redir_entries(idx) + 1;
3820
3821 if (nr > nr_irqs_gsi)
3822 nr_irqs_gsi = nr;
3823 }
3824
3825 #ifdef CONFIG_SPARSE_IRQ
3826 int __init arch_probe_nr_irqs(void)
3827 {
3828 int nr;
3829
3830 nr = ((8 * nr_cpu_ids) > (32 * nr_ioapics) ?
3831 (NR_VECTORS + (8 * nr_cpu_ids)) :
3832 (NR_VECTORS + (32 * nr_ioapics)));
3833
3834 if (nr < nr_irqs && nr > nr_irqs_gsi)
3835 nr_irqs = nr;
3836
3837 return 0;
3838 }
3839 #endif
3840
3841 /* --------------------------------------------------------------------------
3842 ACPI-based IOAPIC Configuration
3843 -------------------------------------------------------------------------- */
3844
3845 #ifdef CONFIG_ACPI
3846
3847 #ifdef CONFIG_X86_32
3848 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3849 {
3850 union IO_APIC_reg_00 reg_00;
3851 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3852 physid_mask_t tmp;
3853 unsigned long flags;
3854 int i = 0;
3855
3856 /*
3857 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3858 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3859 * supports up to 16 on one shared APIC bus.
3860 *
3861 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3862 * advantage of new APIC bus architecture.
3863 */
3864
3865 if (physids_empty(apic_id_map))
3866 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3867
3868 spin_lock_irqsave(&ioapic_lock, flags);
3869 reg_00.raw = io_apic_read(ioapic, 0);
3870 spin_unlock_irqrestore(&ioapic_lock, flags);
3871
3872 if (apic_id >= get_physical_broadcast()) {
3873 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3874 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3875 apic_id = reg_00.bits.ID;
3876 }
3877
3878 /*
3879 * Every APIC in a system must have a unique ID or we get lots of nice
3880 * 'stuck on smp_invalidate_needed IPI wait' messages.
3881 */
3882 if (check_apicid_used(apic_id_map, apic_id)) {
3883
3884 for (i = 0; i < get_physical_broadcast(); i++) {
3885 if (!check_apicid_used(apic_id_map, i))
3886 break;
3887 }
3888
3889 if (i == get_physical_broadcast())
3890 panic("Max apic_id exceeded!\n");
3891
3892 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3893 "trying %d\n", ioapic, apic_id, i);
3894
3895 apic_id = i;
3896 }
3897
3898 tmp = apicid_to_cpu_present(apic_id);
3899 physids_or(apic_id_map, apic_id_map, tmp);
3900
3901 if (reg_00.bits.ID != apic_id) {
3902 reg_00.bits.ID = apic_id;
3903
3904 spin_lock_irqsave(&ioapic_lock, flags);
3905 io_apic_write(ioapic, 0, reg_00.raw);
3906 reg_00.raw = io_apic_read(ioapic, 0);
3907 spin_unlock_irqrestore(&ioapic_lock, flags);
3908
3909 /* Sanity check */
3910 if (reg_00.bits.ID != apic_id) {
3911 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3912 return -1;
3913 }
3914 }
3915
3916 apic_printk(APIC_VERBOSE, KERN_INFO
3917 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3918
3919 return apic_id;
3920 }
3921
3922 int __init io_apic_get_version(int ioapic)
3923 {
3924 union IO_APIC_reg_01 reg_01;
3925 unsigned long flags;
3926
3927 spin_lock_irqsave(&ioapic_lock, flags);
3928 reg_01.raw = io_apic_read(ioapic, 1);
3929 spin_unlock_irqrestore(&ioapic_lock, flags);
3930
3931 return reg_01.bits.version;
3932 }
3933 #endif
3934
3935 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3936 {
3937 struct irq_desc *desc;
3938 struct irq_cfg *cfg;
3939 int cpu = boot_cpu_id;
3940
3941 if (!IO_APIC_IRQ(irq)) {
3942 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3943 ioapic);
3944 return -EINVAL;
3945 }
3946
3947 desc = irq_to_desc_alloc_cpu(irq, cpu);
3948 if (!desc) {
3949 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3950 return 0;
3951 }
3952
3953 /*
3954 * IRQs < 16 are already in the irq_2_pin[] map
3955 */
3956 if (irq >= NR_IRQS_LEGACY) {
3957 cfg = desc->chip_data;
3958 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3959 }
3960
3961 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3962
3963 return 0;
3964 }
3965
3966
3967 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3968 {
3969 int i;
3970
3971 if (skip_ioapic_setup)
3972 return -1;
3973
3974 for (i = 0; i < mp_irq_entries; i++)
3975 if (mp_irqs[i].irqtype == mp_INT &&
3976 mp_irqs[i].srcbusirq == bus_irq)
3977 break;
3978 if (i >= mp_irq_entries)
3979 return -1;
3980
3981 *trigger = irq_trigger(i);
3982 *polarity = irq_polarity(i);
3983 return 0;
3984 }
3985
3986 #endif /* CONFIG_ACPI */
3987
3988 /*
3989 * This function currently is only a helper for the i386 smp boot process where
3990 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3991 * so mask in all cases should simply be TARGET_CPUS
3992 */
3993 #ifdef CONFIG_SMP
3994 void __init setup_ioapic_dest(void)
3995 {
3996 int pin, ioapic, irq, irq_entry;
3997 struct irq_desc *desc;
3998 struct irq_cfg *cfg;
3999 const struct cpumask *mask;
4000
4001 if (skip_ioapic_setup == 1)
4002 return;
4003
4004 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4005 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4006 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4007 if (irq_entry == -1)
4008 continue;
4009 irq = pin_2_irq(irq_entry, ioapic, pin);
4010
4011 /* setup_IO_APIC_irqs could fail to get vector for some device
4012 * when you have too many devices, because at that time only boot
4013 * cpu is online.
4014 */
4015 desc = irq_to_desc(irq);
4016 cfg = desc->chip_data;
4017 if (!cfg->vector) {
4018 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4019 irq_trigger(irq_entry),
4020 irq_polarity(irq_entry));
4021 continue;
4022
4023 }
4024
4025 /*
4026 * Honour affinities which have been set in early boot
4027 */
4028 if (desc->status &
4029 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4030 mask = desc->affinity;
4031 else
4032 mask = TARGET_CPUS;
4033
4034 #ifdef CONFIG_INTR_REMAP
4035 if (intr_remapping_enabled)
4036 set_ir_ioapic_affinity_irq_desc(desc, mask);
4037 else
4038 #endif
4039 set_ioapic_affinity_irq_desc(desc, mask);
4040 }
4041
4042 }
4043 }
4044 #endif
4045
4046 #define IOAPIC_RESOURCE_NAME_SIZE 11
4047
4048 static struct resource *ioapic_resources;
4049
4050 static struct resource * __init ioapic_setup_resources(void)
4051 {
4052 unsigned long n;
4053 struct resource *res;
4054 char *mem;
4055 int i;
4056
4057 if (nr_ioapics <= 0)
4058 return NULL;
4059
4060 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4061 n *= nr_ioapics;
4062
4063 mem = alloc_bootmem(n);
4064 res = (void *)mem;
4065
4066 if (mem != NULL) {
4067 mem += sizeof(struct resource) * nr_ioapics;
4068
4069 for (i = 0; i < nr_ioapics; i++) {
4070 res[i].name = mem;
4071 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4072 sprintf(mem, "IOAPIC %u", i);
4073 mem += IOAPIC_RESOURCE_NAME_SIZE;
4074 }
4075 }
4076
4077 ioapic_resources = res;
4078
4079 return res;
4080 }
4081
4082 void __init ioapic_init_mappings(void)
4083 {
4084 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4085 struct resource *ioapic_res;
4086 int i;
4087
4088 ioapic_res = ioapic_setup_resources();
4089 for (i = 0; i < nr_ioapics; i++) {
4090 if (smp_found_config) {
4091 ioapic_phys = mp_ioapics[i].apicaddr;
4092 #ifdef CONFIG_X86_32
4093 if (!ioapic_phys) {
4094 printk(KERN_ERR
4095 "WARNING: bogus zero IO-APIC "
4096 "address found in MPTABLE, "
4097 "disabling IO/APIC support!\n");
4098 smp_found_config = 0;
4099 skip_ioapic_setup = 1;
4100 goto fake_ioapic_page;
4101 }
4102 #endif
4103 } else {
4104 #ifdef CONFIG_X86_32
4105 fake_ioapic_page:
4106 #endif
4107 ioapic_phys = (unsigned long)
4108 alloc_bootmem_pages(PAGE_SIZE);
4109 ioapic_phys = __pa(ioapic_phys);
4110 }
4111 set_fixmap_nocache(idx, ioapic_phys);
4112 apic_printk(APIC_VERBOSE,
4113 "mapped IOAPIC to %08lx (%08lx)\n",
4114 __fix_to_virt(idx), ioapic_phys);
4115 idx++;
4116
4117 if (ioapic_res != NULL) {
4118 ioapic_res->start = ioapic_phys;
4119 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4120 ioapic_res++;
4121 }
4122 }
4123 }
4124
4125 static int __init ioapic_insert_resources(void)
4126 {
4127 int i;
4128 struct resource *r = ioapic_resources;
4129
4130 if (!r) {
4131 printk(KERN_ERR
4132 "IO APIC resources could be not be allocated.\n");
4133 return -1;
4134 }
4135
4136 for (i = 0; i < nr_ioapics; i++) {
4137 insert_resource(&iomem_resource, r);
4138 r++;
4139 }
4140
4141 return 0;
4142 }
4143
4144 /* Insert the IO APIC resources after PCI initialization has occured to handle
4145 * IO APICS that are mapped in on a BAR in PCI space. */
4146 late_initcall(ioapic_insert_resources);
Support for the Chinese Samsung S3C2440 based development boards