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e1000e: increase swflag acquisition timeout for ICHx/PCH
[linux-2.6/mini2440.git] / drivers / net / e1000e / ich8lan.c
blobfb2222d60a793104551e6176617dcf658a1a41db
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 */
56
57 #include <linux/netdevice.h>
58 #include <linux/ethtool.h>
59 #include <linux/delay.h>
60 #include <linux/pci.h>
61
62 #include "e1000.h"
63
64 #define ICH_FLASH_GFPREG 0x0000
65 #define ICH_FLASH_HSFSTS 0x0004
66 #define ICH_FLASH_HSFCTL 0x0006
67 #define ICH_FLASH_FADDR 0x0008
68 #define ICH_FLASH_FDATA0 0x0010
69 #define ICH_FLASH_PR0 0x0074
70
71 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
72 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
73 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
74 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
75 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
76
77 #define ICH_CYCLE_READ 0
78 #define ICH_CYCLE_WRITE 2
79 #define ICH_CYCLE_ERASE 3
80
81 #define FLASH_GFPREG_BASE_MASK 0x1FFF
82 #define FLASH_SECTOR_ADDR_SHIFT 12
83
84 #define ICH_FLASH_SEG_SIZE_256 256
85 #define ICH_FLASH_SEG_SIZE_4K 4096
86 #define ICH_FLASH_SEG_SIZE_8K 8192
87 #define ICH_FLASH_SEG_SIZE_64K 65536
88
89
90 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
91
92 #define E1000_ICH_MNG_IAMT_MODE 0x2
93
94 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
95 (ID_LED_DEF1_OFF2 << 8) | \
96 (ID_LED_DEF1_ON2 << 4) | \
97 (ID_LED_DEF1_DEF2))
98
99 #define E1000_ICH_NVM_SIG_WORD 0x13
100 #define E1000_ICH_NVM_SIG_MASK 0xC000
101 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
102 #define E1000_ICH_NVM_SIG_VALUE 0x80
103
104 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
105
106 #define E1000_FEXTNVM_SW_CONFIG 1
107 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
108
109 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
110
111 #define E1000_ICH_RAR_ENTRIES 7
112
113 #define PHY_PAGE_SHIFT 5
114 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
115 ((reg) & MAX_PHY_REG_ADDRESS))
116 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
117 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
118
119 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
120 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
121 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
122
123 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
124
125 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
126
127 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
128 /* Offset 04h HSFSTS */
129 union ich8_hws_flash_status {
130 struct ich8_hsfsts {
131 u16 flcdone :1; /* bit 0 Flash Cycle Done */
132 u16 flcerr :1; /* bit 1 Flash Cycle Error */
133 u16 dael :1; /* bit 2 Direct Access error Log */
134 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
135 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
136 u16 reserved1 :2; /* bit 13:6 Reserved */
137 u16 reserved2 :6; /* bit 13:6 Reserved */
138 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
139 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
140 } hsf_status;
141 u16 regval;
142 };
143
144 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
145 /* Offset 06h FLCTL */
146 union ich8_hws_flash_ctrl {
147 struct ich8_hsflctl {
148 u16 flcgo :1; /* 0 Flash Cycle Go */
149 u16 flcycle :2; /* 2:1 Flash Cycle */
150 u16 reserved :5; /* 7:3 Reserved */
151 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
152 u16 flockdn :6; /* 15:10 Reserved */
153 } hsf_ctrl;
154 u16 regval;
155 };
156
157 /* ICH Flash Region Access Permissions */
158 union ich8_hws_flash_regacc {
159 struct ich8_flracc {
160 u32 grra :8; /* 0:7 GbE region Read Access */
161 u32 grwa :8; /* 8:15 GbE region Write Access */
162 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
163 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
164 } hsf_flregacc;
165 u16 regval;
166 };
167
168 /* ICH Flash Protected Region */
169 union ich8_flash_protected_range {
170 struct ich8_pr {
171 u32 base:13; /* 0:12 Protected Range Base */
172 u32 reserved1:2; /* 13:14 Reserved */
173 u32 rpe:1; /* 15 Read Protection Enable */
174 u32 limit:13; /* 16:28 Protected Range Limit */
175 u32 reserved2:2; /* 29:30 Reserved */
176 u32 wpe:1; /* 31 Write Protection Enable */
177 } range;
178 u32 regval;
179 };
180
181 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
182 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
183 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
184 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
185 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
186 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
187 u32 offset, u8 byte);
188 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
189 u8 *data);
190 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
191 u16 *data);
192 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
193 u8 size, u16 *data);
194 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
195 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
196 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
197 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
198 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
199 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
200 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
201 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
202 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
203 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
204 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
205
206 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
207 {
208 return readw(hw->flash_address + reg);
209 }
210
211 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
212 {
213 return readl(hw->flash_address + reg);
214 }
215
216 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
217 {
218 writew(val, hw->flash_address + reg);
219 }
220
221 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
222 {
223 writel(val, hw->flash_address + reg);
224 }
225
226 #define er16flash(reg) __er16flash(hw, (reg))
227 #define er32flash(reg) __er32flash(hw, (reg))
228 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
229 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
230
231 /**
232 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
233 * @hw: pointer to the HW structure
234 *
235 * Initialize family-specific PHY parameters and function pointers.
236 **/
237 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
238 {
239 struct e1000_phy_info *phy = &hw->phy;
240 s32 ret_val = 0;
241
242 phy->addr = 1;
243 phy->reset_delay_us = 100;
244
245 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
246 phy->ops.read_phy_reg = e1000_read_phy_reg_hv;
247 phy->ops.write_phy_reg = e1000_write_phy_reg_hv;
248 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
249
250 phy->id = e1000_phy_unknown;
251 e1000e_get_phy_id(hw);
252 phy->type = e1000e_get_phy_type_from_id(phy->id);
253
254 if (phy->type == e1000_phy_82577) {
255 phy->ops.check_polarity = e1000_check_polarity_82577;
256 phy->ops.force_speed_duplex =
257 e1000_phy_force_speed_duplex_82577;
258 phy->ops.get_cable_length = e1000_get_cable_length_82577;
259 phy->ops.get_phy_info = e1000_get_phy_info_82577;
260 phy->ops.commit_phy = e1000e_phy_sw_reset;
261 }
262
263 return ret_val;
264 }
265
266 /**
267 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
268 * @hw: pointer to the HW structure
269 *
270 * Initialize family-specific PHY parameters and function pointers.
271 **/
272 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
273 {
274 struct e1000_phy_info *phy = &hw->phy;
275 s32 ret_val;
276 u16 i = 0;
277
278 phy->addr = 1;
279 phy->reset_delay_us = 100;
280
281 /*
282 * We may need to do this twice - once for IGP and if that fails,
283 * we'll set BM func pointers and try again
284 */
285 ret_val = e1000e_determine_phy_address(hw);
286 if (ret_val) {
287 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
288 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
289 ret_val = e1000e_determine_phy_address(hw);
290 if (ret_val)
291 return ret_val;
292 }
293
294 phy->id = 0;
295 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
296 (i++ < 100)) {
297 msleep(1);
298 ret_val = e1000e_get_phy_id(hw);
299 if (ret_val)
300 return ret_val;
301 }
302
303 /* Verify phy id */
304 switch (phy->id) {
305 case IGP03E1000_E_PHY_ID:
306 phy->type = e1000_phy_igp_3;
307 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
308 break;
309 case IFE_E_PHY_ID:
310 case IFE_PLUS_E_PHY_ID:
311 case IFE_C_E_PHY_ID:
312 phy->type = e1000_phy_ife;
313 phy->autoneg_mask = E1000_ALL_NOT_GIG;
314 break;
315 case BME1000_E_PHY_ID:
316 phy->type = e1000_phy_bm;
317 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
318 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
319 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
320 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
321 break;
322 default:
323 return -E1000_ERR_PHY;
324 break;
325 }
326
327 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
328
329 return 0;
330 }
331
332 /**
333 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
334 * @hw: pointer to the HW structure
335 *
336 * Initialize family-specific NVM parameters and function
337 * pointers.
338 **/
339 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
340 {
341 struct e1000_nvm_info *nvm = &hw->nvm;
342 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
343 u32 gfpreg, sector_base_addr, sector_end_addr;
344 u16 i;
345
346 /* Can't read flash registers if the register set isn't mapped. */
347 if (!hw->flash_address) {
348 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
349 return -E1000_ERR_CONFIG;
350 }
351
352 nvm->type = e1000_nvm_flash_sw;
353
354 gfpreg = er32flash(ICH_FLASH_GFPREG);
355
356 /*
357 * sector_X_addr is a "sector"-aligned address (4096 bytes)
358 * Add 1 to sector_end_addr since this sector is included in
359 * the overall size.
360 */
361 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
362 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
363
364 /* flash_base_addr is byte-aligned */
365 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
366
367 /*
368 * find total size of the NVM, then cut in half since the total
369 * size represents two separate NVM banks.
370 */
371 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
372 << FLASH_SECTOR_ADDR_SHIFT;
373 nvm->flash_bank_size /= 2;
374 /* Adjust to word count */
375 nvm->flash_bank_size /= sizeof(u16);
376
377 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
378
379 /* Clear shadow ram */
380 for (i = 0; i < nvm->word_size; i++) {
381 dev_spec->shadow_ram[i].modified = 0;
382 dev_spec->shadow_ram[i].value = 0xFFFF;
383 }
384
385 return 0;
386 }
387
388 /**
389 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
390 * @hw: pointer to the HW structure
391 *
392 * Initialize family-specific MAC parameters and function
393 * pointers.
394 **/
395 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
396 {
397 struct e1000_hw *hw = &adapter->hw;
398 struct e1000_mac_info *mac = &hw->mac;
399
400 /* Set media type function pointer */
401 hw->phy.media_type = e1000_media_type_copper;
402
403 /* Set mta register count */
404 mac->mta_reg_count = 32;
405 /* Set rar entry count */
406 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
407 if (mac->type == e1000_ich8lan)
408 mac->rar_entry_count--;
409 /* Set if manageability features are enabled. */
410 mac->arc_subsystem_valid = 1;
411
412 /* LED operations */
413 switch (mac->type) {
414 case e1000_ich8lan:
415 case e1000_ich9lan:
416 case e1000_ich10lan:
417 /* ID LED init */
418 mac->ops.id_led_init = e1000e_id_led_init;
419 /* setup LED */
420 mac->ops.setup_led = e1000e_setup_led_generic;
421 /* cleanup LED */
422 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
423 /* turn on/off LED */
424 mac->ops.led_on = e1000_led_on_ich8lan;
425 mac->ops.led_off = e1000_led_off_ich8lan;
426 break;
427 case e1000_pchlan:
428 /* ID LED init */
429 mac->ops.id_led_init = e1000_id_led_init_pchlan;
430 /* setup LED */
431 mac->ops.setup_led = e1000_setup_led_pchlan;
432 /* cleanup LED */
433 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
434 /* turn on/off LED */
435 mac->ops.led_on = e1000_led_on_pchlan;
436 mac->ops.led_off = e1000_led_off_pchlan;
437 break;
438 default:
439 break;
440 }
441
442 /* Enable PCS Lock-loss workaround for ICH8 */
443 if (mac->type == e1000_ich8lan)
444 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
445
446 return 0;
447 }
448
449 /**
450 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
451 * @hw: pointer to the HW structure
452 *
453 * Checks to see of the link status of the hardware has changed. If a
454 * change in link status has been detected, then we read the PHY registers
455 * to get the current speed/duplex if link exists.
456 **/
457 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
458 {
459 struct e1000_mac_info *mac = &hw->mac;
460 s32 ret_val;
461 bool link;
462
463 /*
464 * We only want to go out to the PHY registers to see if Auto-Neg
465 * has completed and/or if our link status has changed. The
466 * get_link_status flag is set upon receiving a Link Status
467 * Change or Rx Sequence Error interrupt.
468 */
469 if (!mac->get_link_status) {
470 ret_val = 0;
471 goto out;
472 }
473
474 if (hw->mac.type == e1000_pchlan) {
475 ret_val = e1000e_write_kmrn_reg(hw,
476 E1000_KMRNCTRLSTA_K1_CONFIG,
477 E1000_KMRNCTRLSTA_K1_ENABLE);
478 if (ret_val)
479 goto out;
480 }
481
482 /*
483 * First we want to see if the MII Status Register reports
484 * link. If so, then we want to get the current speed/duplex
485 * of the PHY.
486 */
487 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
488 if (ret_val)
489 goto out;
490
491 if (!link)
492 goto out; /* No link detected */
493
494 mac->get_link_status = false;
495
496 if (hw->phy.type == e1000_phy_82578) {
497 ret_val = e1000_link_stall_workaround_hv(hw);
498 if (ret_val)
499 goto out;
500 }
501
502 /*
503 * Check if there was DownShift, must be checked
504 * immediately after link-up
505 */
506 e1000e_check_downshift(hw);
507
508 /*
509 * If we are forcing speed/duplex, then we simply return since
510 * we have already determined whether we have link or not.
511 */
512 if (!mac->autoneg) {
513 ret_val = -E1000_ERR_CONFIG;
514 goto out;
515 }
516
517 /*
518 * Auto-Neg is enabled. Auto Speed Detection takes care
519 * of MAC speed/duplex configuration. So we only need to
520 * configure Collision Distance in the MAC.
521 */
522 e1000e_config_collision_dist(hw);
523
524 /*
525 * Configure Flow Control now that Auto-Neg has completed.
526 * First, we need to restore the desired flow control
527 * settings because we may have had to re-autoneg with a
528 * different link partner.
529 */
530 ret_val = e1000e_config_fc_after_link_up(hw);
531 if (ret_val)
532 hw_dbg(hw, "Error configuring flow control\n");
533
534 out:
535 return ret_val;
536 }
537
538 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
539 {
540 struct e1000_hw *hw = &adapter->hw;
541 s32 rc;
542
543 rc = e1000_init_mac_params_ich8lan(adapter);
544 if (rc)
545 return rc;
546
547 rc = e1000_init_nvm_params_ich8lan(hw);
548 if (rc)
549 return rc;
550
551 if (hw->mac.type == e1000_pchlan)
552 rc = e1000_init_phy_params_pchlan(hw);
553 else
554 rc = e1000_init_phy_params_ich8lan(hw);
555 if (rc)
556 return rc;
557
558 if (adapter->hw.phy.type == e1000_phy_ife) {
559 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
560 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
561 }
562
563 if ((adapter->hw.mac.type == e1000_ich8lan) &&
564 (adapter->hw.phy.type == e1000_phy_igp_3))
565 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
566
567 return 0;
568 }
569
570 static DEFINE_MUTEX(nvm_mutex);
571
572 /**
573 * e1000_acquire_swflag_ich8lan - Acquire software control flag
574 * @hw: pointer to the HW structure
575 *
576 * Acquires the software control flag for performing NVM and PHY
577 * operations. This is a function pointer entry point only called by
578 * read/write routines for the PHY and NVM parts.
579 **/
580 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
581 {
582 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
583 s32 ret_val = 0;
584
585 might_sleep();
586
587 mutex_lock(&nvm_mutex);
588
589 while (timeout) {
590 extcnf_ctrl = er32(EXTCNF_CTRL);
591 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
592 break;
593
594 mdelay(1);
595 timeout--;
596 }
597
598 if (!timeout) {
599 hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n");
600 ret_val = -E1000_ERR_CONFIG;
601 goto out;
602 }
603
604 timeout = SW_FLAG_TIMEOUT;
605
606 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
607 ew32(EXTCNF_CTRL, extcnf_ctrl);
608
609 while (timeout) {
610 extcnf_ctrl = er32(EXTCNF_CTRL);
611 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
612 break;
613
614 mdelay(1);
615 timeout--;
616 }
617
618 if (!timeout) {
619 hw_dbg(hw, "Failed to acquire the semaphore.\n");
620 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
621 ew32(EXTCNF_CTRL, extcnf_ctrl);
622 ret_val = -E1000_ERR_CONFIG;
623 goto out;
624 }
625
626 out:
627 if (ret_val)
628 mutex_unlock(&nvm_mutex);
629
630 return ret_val;
631 }
632
633 /**
634 * e1000_release_swflag_ich8lan - Release software control flag
635 * @hw: pointer to the HW structure
636 *
637 * Releases the software control flag for performing NVM and PHY operations.
638 * This is a function pointer entry point only called by read/write
639 * routines for the PHY and NVM parts.
640 **/
641 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
642 {
643 u32 extcnf_ctrl;
644
645 extcnf_ctrl = er32(EXTCNF_CTRL);
646 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
647 ew32(EXTCNF_CTRL, extcnf_ctrl);
648
649 mutex_unlock(&nvm_mutex);
650 }
651
652 /**
653 * e1000_check_mng_mode_ich8lan - Checks management mode
654 * @hw: pointer to the HW structure
655 *
656 * This checks if the adapter has manageability enabled.
657 * This is a function pointer entry point only called by read/write
658 * routines for the PHY and NVM parts.
659 **/
660 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
661 {
662 u32 fwsm = er32(FWSM);
663
664 return (fwsm & E1000_FWSM_MODE_MASK) ==
665 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
666 }
667
668 /**
669 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
670 * @hw: pointer to the HW structure
671 *
672 * Checks if firmware is blocking the reset of the PHY.
673 * This is a function pointer entry point only called by
674 * reset routines.
675 **/
676 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
677 {
678 u32 fwsm;
679
680 fwsm = er32(FWSM);
681
682 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
683 }
684
685 /**
686 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
687 * @hw: pointer to the HW structure
688 *
689 * Forces the speed and duplex settings of the PHY.
690 * This is a function pointer entry point only called by
691 * PHY setup routines.
692 **/
693 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
694 {
695 struct e1000_phy_info *phy = &hw->phy;
696 s32 ret_val;
697 u16 data;
698 bool link;
699
700 if (phy->type != e1000_phy_ife) {
701 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
702 return ret_val;
703 }
704
705 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
706 if (ret_val)
707 return ret_val;
708
709 e1000e_phy_force_speed_duplex_setup(hw, &data);
710
711 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
712 if (ret_val)
713 return ret_val;
714
715 /* Disable MDI-X support for 10/100 */
716 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
717 if (ret_val)
718 return ret_val;
719
720 data &= ~IFE_PMC_AUTO_MDIX;
721 data &= ~IFE_PMC_FORCE_MDIX;
722
723 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
724 if (ret_val)
725 return ret_val;
726
727 hw_dbg(hw, "IFE PMC: %X\n", data);
728
729 udelay(1);
730
731 if (phy->autoneg_wait_to_complete) {
732 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
733
734 ret_val = e1000e_phy_has_link_generic(hw,
735 PHY_FORCE_LIMIT,
736 100000,
737 &link);
738 if (ret_val)
739 return ret_val;
740
741 if (!link)
742 hw_dbg(hw, "Link taking longer than expected.\n");
743
744 /* Try once more */
745 ret_val = e1000e_phy_has_link_generic(hw,
746 PHY_FORCE_LIMIT,
747 100000,
748 &link);
749 if (ret_val)
750 return ret_val;
751 }
752
753 return 0;
754 }
755
756 /**
757 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
758 * done after every PHY reset.
759 **/
760 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
761 {
762 s32 ret_val = 0;
763
764 if (hw->mac.type != e1000_pchlan)
765 return ret_val;
766
767 if (((hw->phy.type == e1000_phy_82577) &&
768 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
769 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
770 /* Disable generation of early preamble */
771 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
772 if (ret_val)
773 return ret_val;
774
775 /* Preamble tuning for SSC */
776 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
777 if (ret_val)
778 return ret_val;
779 }
780
781 if (hw->phy.type == e1000_phy_82578) {
782 /*
783 * Return registers to default by doing a soft reset then
784 * writing 0x3140 to the control register.
785 */
786 if (hw->phy.revision < 2) {
787 e1000e_phy_sw_reset(hw);
788 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
789 }
790 }
791
792 /* Select page 0 */
793 ret_val = hw->phy.ops.acquire_phy(hw);
794 if (ret_val)
795 return ret_val;
796 hw->phy.addr = 1;
797 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
798 hw->phy.ops.release_phy(hw);
799
800 return ret_val;
801 }
802
803 /**
804 * e1000_lan_init_done_ich8lan - Check for PHY config completion
805 * @hw: pointer to the HW structure
806 *
807 * Check the appropriate indication the MAC has finished configuring the
808 * PHY after a software reset.
809 **/
810 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
811 {
812 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
813
814 /* Wait for basic configuration completes before proceeding */
815 do {
816 data = er32(STATUS);
817 data &= E1000_STATUS_LAN_INIT_DONE;
818 udelay(100);
819 } while ((!data) && --loop);
820
821 /*
822 * If basic configuration is incomplete before the above loop
823 * count reaches 0, loading the configuration from NVM will
824 * leave the PHY in a bad state possibly resulting in no link.
825 */
826 if (loop == 0)
827 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
828
829 /* Clear the Init Done bit for the next init event */
830 data = er32(STATUS);
831 data &= ~E1000_STATUS_LAN_INIT_DONE;
832 ew32(STATUS, data);
833 }
834
835 /**
836 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
837 * @hw: pointer to the HW structure
838 *
839 * Resets the PHY
840 * This is a function pointer entry point called by drivers
841 * or other shared routines.
842 **/
843 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
844 {
845 struct e1000_phy_info *phy = &hw->phy;
846 u32 i;
847 u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
848 s32 ret_val;
849 u16 reg, word_addr, reg_data, reg_addr, phy_page = 0;
850
851 ret_val = e1000e_phy_hw_reset_generic(hw);
852 if (ret_val)
853 return ret_val;
854
855 /* Allow time for h/w to get to a quiescent state after reset */
856 mdelay(10);
857
858 if (hw->mac.type == e1000_pchlan) {
859 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
860 if (ret_val)
861 return ret_val;
862 }
863
864 /* Dummy read to clear the phy wakeup bit after lcd reset */
865 if (hw->mac.type == e1000_pchlan)
866 e1e_rphy(hw, BM_WUC, &reg);
867
868 /*
869 * Initialize the PHY from the NVM on ICH platforms. This
870 * is needed due to an issue where the NVM configuration is
871 * not properly autoloaded after power transitions.
872 * Therefore, after each PHY reset, we will load the
873 * configuration data out of the NVM manually.
874 */
875 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
876 struct e1000_adapter *adapter = hw->adapter;
877
878 /* Check if SW needs configure the PHY */
879 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
880 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
881 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
882 else
883 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
884
885 data = er32(FEXTNVM);
886 if (!(data & sw_cfg_mask))
887 return 0;
888
889 /* Wait for basic configuration completes before proceeding */
890 e1000_lan_init_done_ich8lan(hw);
891
892 /*
893 * Make sure HW does not configure LCD from PHY
894 * extended configuration before SW configuration
895 */
896 data = er32(EXTCNF_CTRL);
897 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
898 return 0;
899
900 cnf_size = er32(EXTCNF_SIZE);
901 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
902 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
903 if (!cnf_size)
904 return 0;
905
906 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
907 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
908
909 /* Configure LCD from extended configuration region. */
910
911 /* cnf_base_addr is in DWORD */
912 word_addr = (u16)(cnf_base_addr << 1);
913
914 for (i = 0; i < cnf_size; i++) {
915 ret_val = e1000_read_nvm(hw,
916 (word_addr + i * 2),
917 1,
918 &reg_data);
919 if (ret_val)
920 return ret_val;
921
922 ret_val = e1000_read_nvm(hw,
923 (word_addr + i * 2 + 1),
924 1,
925 &reg_addr);
926 if (ret_val)
927 return ret_val;
928
929 /* Save off the PHY page for future writes. */
930 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
931 phy_page = reg_data;
932 continue;
933 }
934
935 reg_addr |= phy_page;
936
937 ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
938 if (ret_val)
939 return ret_val;
940 }
941 }
942
943 return 0;
944 }
945
946 /**
947 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
948 * @hw: pointer to the HW structure
949 *
950 * Populates "phy" structure with various feature states.
951 * This function is only called by other family-specific
952 * routines.
953 **/
954 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
955 {
956 struct e1000_phy_info *phy = &hw->phy;
957 s32 ret_val;
958 u16 data;
959 bool link;
960
961 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
962 if (ret_val)
963 return ret_val;
964
965 if (!link) {
966 hw_dbg(hw, "Phy info is only valid if link is up\n");
967 return -E1000_ERR_CONFIG;
968 }
969
970 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
971 if (ret_val)
972 return ret_val;
973 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
974
975 if (phy->polarity_correction) {
976 ret_val = phy->ops.check_polarity(hw);
977 if (ret_val)
978 return ret_val;
979 } else {
980 /* Polarity is forced */
981 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
982 ? e1000_rev_polarity_reversed
983 : e1000_rev_polarity_normal;
984 }
985
986 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
987 if (ret_val)
988 return ret_val;
989
990 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
991
992 /* The following parameters are undefined for 10/100 operation. */
993 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
994 phy->local_rx = e1000_1000t_rx_status_undefined;
995 phy->remote_rx = e1000_1000t_rx_status_undefined;
996
997 return 0;
998 }
999
1000 /**
1001 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1002 * @hw: pointer to the HW structure
1003 *
1004 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
1005 * This is a function pointer entry point called by drivers
1006 * or other shared routines.
1007 **/
1008 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1009 {
1010 switch (hw->phy.type) {
1011 case e1000_phy_ife:
1012 return e1000_get_phy_info_ife_ich8lan(hw);
1013 break;
1014 case e1000_phy_igp_3:
1015 case e1000_phy_bm:
1016 case e1000_phy_82578:
1017 case e1000_phy_82577:
1018 return e1000e_get_phy_info_igp(hw);
1019 break;
1020 default:
1021 break;
1022 }
1023
1024 return -E1000_ERR_PHY_TYPE;
1025 }
1026
1027 /**
1028 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1029 * @hw: pointer to the HW structure
1030 *
1031 * Polarity is determined on the polarity reversal feature being enabled.
1032 * This function is only called by other family-specific
1033 * routines.
1034 **/
1035 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1036 {
1037 struct e1000_phy_info *phy = &hw->phy;
1038 s32 ret_val;
1039 u16 phy_data, offset, mask;
1040
1041 /*
1042 * Polarity is determined based on the reversal feature being enabled.
1043 */
1044 if (phy->polarity_correction) {
1045 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1046 mask = IFE_PESC_POLARITY_REVERSED;
1047 } else {
1048 offset = IFE_PHY_SPECIAL_CONTROL;
1049 mask = IFE_PSC_FORCE_POLARITY;
1050 }
1051
1052 ret_val = e1e_rphy(hw, offset, &phy_data);
1053
1054 if (!ret_val)
1055 phy->cable_polarity = (phy_data & mask)
1056 ? e1000_rev_polarity_reversed
1057 : e1000_rev_polarity_normal;
1058
1059 return ret_val;
1060 }
1061
1062 /**
1063 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1064 * @hw: pointer to the HW structure
1065 * @active: TRUE to enable LPLU, FALSE to disable
1066 *
1067 * Sets the LPLU D0 state according to the active flag. When
1068 * activating LPLU this function also disables smart speed
1069 * and vice versa. LPLU will not be activated unless the
1070 * device autonegotiation advertisement meets standards of
1071 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1072 * This is a function pointer entry point only called by
1073 * PHY setup routines.
1074 **/
1075 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1076 {
1077 struct e1000_phy_info *phy = &hw->phy;
1078 u32 phy_ctrl;
1079 s32 ret_val = 0;
1080 u16 data;
1081
1082 if (phy->type == e1000_phy_ife)
1083 return ret_val;
1084
1085 phy_ctrl = er32(PHY_CTRL);
1086
1087 if (active) {
1088 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1089 ew32(PHY_CTRL, phy_ctrl);
1090
1091 if (phy->type != e1000_phy_igp_3)
1092 return 0;
1093
1094 /*
1095 * Call gig speed drop workaround on LPLU before accessing
1096 * any PHY registers
1097 */
1098 if (hw->mac.type == e1000_ich8lan)
1099 e1000e_gig_downshift_workaround_ich8lan(hw);
1100
1101 /* When LPLU is enabled, we should disable SmartSpeed */
1102 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1103 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1104 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1105 if (ret_val)
1106 return ret_val;
1107 } else {
1108 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1109 ew32(PHY_CTRL, phy_ctrl);
1110
1111 if (phy->type != e1000_phy_igp_3)
1112 return 0;
1113
1114 /*
1115 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1116 * during Dx states where the power conservation is most
1117 * important. During driver activity we should enable
1118 * SmartSpeed, so performance is maintained.
1119 */
1120 if (phy->smart_speed == e1000_smart_speed_on) {
1121 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1122 &data);
1123 if (ret_val)
1124 return ret_val;
1125
1126 data |= IGP01E1000_PSCFR_SMART_SPEED;
1127 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1128 data);
1129 if (ret_val)
1130 return ret_val;
1131 } else if (phy->smart_speed == e1000_smart_speed_off) {
1132 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1133 &data);
1134 if (ret_val)
1135 return ret_val;
1136
1137 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1138 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1139 data);
1140 if (ret_val)
1141 return ret_val;
1142 }
1143 }
1144
1145 return 0;
1146 }
1147
1148 /**
1149 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1150 * @hw: pointer to the HW structure
1151 * @active: TRUE to enable LPLU, FALSE to disable
1152 *
1153 * Sets the LPLU D3 state according to the active flag. When
1154 * activating LPLU this function also disables smart speed
1155 * and vice versa. LPLU will not be activated unless the
1156 * device autonegotiation advertisement meets standards of
1157 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1158 * This is a function pointer entry point only called by
1159 * PHY setup routines.
1160 **/
1161 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1162 {
1163 struct e1000_phy_info *phy = &hw->phy;
1164 u32 phy_ctrl;
1165 s32 ret_val;
1166 u16 data;
1167
1168 phy_ctrl = er32(PHY_CTRL);
1169
1170 if (!active) {
1171 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1172 ew32(PHY_CTRL, phy_ctrl);
1173
1174 if (phy->type != e1000_phy_igp_3)
1175 return 0;
1176
1177 /*
1178 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1179 * during Dx states where the power conservation is most
1180 * important. During driver activity we should enable
1181 * SmartSpeed, so performance is maintained.
1182 */
1183 if (phy->smart_speed == e1000_smart_speed_on) {
1184 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1185 &data);
1186 if (ret_val)
1187 return ret_val;
1188
1189 data |= IGP01E1000_PSCFR_SMART_SPEED;
1190 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1191 data);
1192 if (ret_val)
1193 return ret_val;
1194 } else if (phy->smart_speed == e1000_smart_speed_off) {
1195 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1196 &data);
1197 if (ret_val)
1198 return ret_val;
1199
1200 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1201 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1202 data);
1203 if (ret_val)
1204 return ret_val;
1205 }
1206 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1207 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1208 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1209 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1210 ew32(PHY_CTRL, phy_ctrl);
1211
1212 if (phy->type != e1000_phy_igp_3)
1213 return 0;
1214
1215 /*
1216 * Call gig speed drop workaround on LPLU before accessing
1217 * any PHY registers
1218 */
1219 if (hw->mac.type == e1000_ich8lan)
1220 e1000e_gig_downshift_workaround_ich8lan(hw);
1221
1222 /* When LPLU is enabled, we should disable SmartSpeed */
1223 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1224 if (ret_val)
1225 return ret_val;
1226
1227 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1228 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1229 }
1230
1231 return 0;
1232 }
1233
1234 /**
1235 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1236 * @hw: pointer to the HW structure
1237 * @bank: pointer to the variable that returns the active bank
1238 *
1239 * Reads signature byte from the NVM using the flash access registers.
1240 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1241 **/
1242 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1243 {
1244 u32 eecd;
1245 struct e1000_nvm_info *nvm = &hw->nvm;
1246 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1247 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1248 u8 sig_byte = 0;
1249 s32 ret_val = 0;
1250
1251 switch (hw->mac.type) {
1252 case e1000_ich8lan:
1253 case e1000_ich9lan:
1254 eecd = er32(EECD);
1255 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1256 E1000_EECD_SEC1VAL_VALID_MASK) {
1257 if (eecd & E1000_EECD_SEC1VAL)
1258 *bank = 1;
1259 else
1260 *bank = 0;
1261
1262 return 0;
1263 }
1264 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
1265 "reading flash signature\n");
1266 /* fall-thru */
1267 default:
1268 /* set bank to 0 in case flash read fails */
1269 *bank = 0;
1270
1271 /* Check bank 0 */
1272 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1273 &sig_byte);
1274 if (ret_val)
1275 return ret_val;
1276 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1277 E1000_ICH_NVM_SIG_VALUE) {
1278 *bank = 0;
1279 return 0;
1280 }
1281
1282 /* Check bank 1 */
1283 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1284 bank1_offset,
1285 &sig_byte);
1286 if (ret_val)
1287 return ret_val;
1288 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1289 E1000_ICH_NVM_SIG_VALUE) {
1290 *bank = 1;
1291 return 0;
1292 }
1293
1294 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1295 return -E1000_ERR_NVM;
1296 }
1297
1298 return 0;
1299 }
1300
1301 /**
1302 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1303 * @hw: pointer to the HW structure
1304 * @offset: The offset (in bytes) of the word(s) to read.
1305 * @words: Size of data to read in words
1306 * @data: Pointer to the word(s) to read at offset.
1307 *
1308 * Reads a word(s) from the NVM using the flash access registers.
1309 **/
1310 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1311 u16 *data)
1312 {
1313 struct e1000_nvm_info *nvm = &hw->nvm;
1314 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1315 u32 act_offset;
1316 s32 ret_val = 0;
1317 u32 bank = 0;
1318 u16 i, word;
1319
1320 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1321 (words == 0)) {
1322 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1323 return -E1000_ERR_NVM;
1324 }
1325
1326 ret_val = e1000_acquire_swflag_ich8lan(hw);
1327 if (ret_val)
1328 goto out;
1329
1330 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1331 if (ret_val) {
1332 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
1333 bank = 0;
1334 }
1335
1336 act_offset = (bank) ? nvm->flash_bank_size : 0;
1337 act_offset += offset;
1338
1339 ret_val = 0;
1340 for (i = 0; i < words; i++) {
1341 if ((dev_spec->shadow_ram) &&
1342 (dev_spec->shadow_ram[offset+i].modified)) {
1343 data[i] = dev_spec->shadow_ram[offset+i].value;
1344 } else {
1345 ret_val = e1000_read_flash_word_ich8lan(hw,
1346 act_offset + i,
1347 &word);
1348 if (ret_val)
1349 break;
1350 data[i] = word;
1351 }
1352 }
1353
1354 e1000_release_swflag_ich8lan(hw);
1355
1356 out:
1357 if (ret_val)
1358 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1359
1360 return ret_val;
1361 }
1362
1363 /**
1364 * e1000_flash_cycle_init_ich8lan - Initialize flash
1365 * @hw: pointer to the HW structure
1366 *
1367 * This function does initial flash setup so that a new read/write/erase cycle
1368 * can be started.
1369 **/
1370 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1371 {
1372 union ich8_hws_flash_status hsfsts;
1373 s32 ret_val = -E1000_ERR_NVM;
1374 s32 i = 0;
1375
1376 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1377
1378 /* Check if the flash descriptor is valid */
1379 if (hsfsts.hsf_status.fldesvalid == 0) {
1380 hw_dbg(hw, "Flash descriptor invalid. "
1381 "SW Sequencing must be used.");
1382 return -E1000_ERR_NVM;
1383 }
1384
1385 /* Clear FCERR and DAEL in hw status by writing 1 */
1386 hsfsts.hsf_status.flcerr = 1;
1387 hsfsts.hsf_status.dael = 1;
1388
1389 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1390
1391 /*
1392 * Either we should have a hardware SPI cycle in progress
1393 * bit to check against, in order to start a new cycle or
1394 * FDONE bit should be changed in the hardware so that it
1395 * is 1 after hardware reset, which can then be used as an
1396 * indication whether a cycle is in progress or has been
1397 * completed.
1398 */
1399
1400 if (hsfsts.hsf_status.flcinprog == 0) {
1401 /*
1402 * There is no cycle running at present,
1403 * so we can start a cycle
1404 * Begin by setting Flash Cycle Done.
1405 */
1406 hsfsts.hsf_status.flcdone = 1;
1407 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1408 ret_val = 0;
1409 } else {
1410 /*
1411 * otherwise poll for sometime so the current
1412 * cycle has a chance to end before giving up.
1413 */
1414 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1415 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1416 if (hsfsts.hsf_status.flcinprog == 0) {
1417 ret_val = 0;
1418 break;
1419 }
1420 udelay(1);
1421 }
1422 if (ret_val == 0) {
1423 /*
1424 * Successful in waiting for previous cycle to timeout,
1425 * now set the Flash Cycle Done.
1426 */
1427 hsfsts.hsf_status.flcdone = 1;
1428 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1429 } else {
1430 hw_dbg(hw, "Flash controller busy, cannot get access");
1431 }
1432 }
1433
1434 return ret_val;
1435 }
1436
1437 /**
1438 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1439 * @hw: pointer to the HW structure
1440 * @timeout: maximum time to wait for completion
1441 *
1442 * This function starts a flash cycle and waits for its completion.
1443 **/
1444 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1445 {
1446 union ich8_hws_flash_ctrl hsflctl;
1447 union ich8_hws_flash_status hsfsts;
1448 s32 ret_val = -E1000_ERR_NVM;
1449 u32 i = 0;
1450
1451 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1452 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1453 hsflctl.hsf_ctrl.flcgo = 1;
1454 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1455
1456 /* wait till FDONE bit is set to 1 */
1457 do {
1458 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1459 if (hsfsts.hsf_status.flcdone == 1)
1460 break;
1461 udelay(1);
1462 } while (i++ < timeout);
1463
1464 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1465 return 0;
1466
1467 return ret_val;
1468 }
1469
1470 /**
1471 * e1000_read_flash_word_ich8lan - Read word from flash
1472 * @hw: pointer to the HW structure
1473 * @offset: offset to data location
1474 * @data: pointer to the location for storing the data
1475 *
1476 * Reads the flash word at offset into data. Offset is converted
1477 * to bytes before read.
1478 **/
1479 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1480 u16 *data)
1481 {
1482 /* Must convert offset into bytes. */
1483 offset <<= 1;
1484
1485 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1486 }
1487
1488 /**
1489 * e1000_read_flash_byte_ich8lan - Read byte from flash
1490 * @hw: pointer to the HW structure
1491 * @offset: The offset of the byte to read.
1492 * @data: Pointer to a byte to store the value read.
1493 *
1494 * Reads a single byte from the NVM using the flash access registers.
1495 **/
1496 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1497 u8 *data)
1498 {
1499 s32 ret_val;
1500 u16 word = 0;
1501
1502 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1503 if (ret_val)
1504 return ret_val;
1505
1506 *data = (u8)word;
1507
1508 return 0;
1509 }
1510
1511 /**
1512 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1513 * @hw: pointer to the HW structure
1514 * @offset: The offset (in bytes) of the byte or word to read.
1515 * @size: Size of data to read, 1=byte 2=word
1516 * @data: Pointer to the word to store the value read.
1517 *
1518 * Reads a byte or word from the NVM using the flash access registers.
1519 **/
1520 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1521 u8 size, u16 *data)
1522 {
1523 union ich8_hws_flash_status hsfsts;
1524 union ich8_hws_flash_ctrl hsflctl;
1525 u32 flash_linear_addr;
1526 u32 flash_data = 0;
1527 s32 ret_val = -E1000_ERR_NVM;
1528 u8 count = 0;
1529
1530 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1531 return -E1000_ERR_NVM;
1532
1533 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1534 hw->nvm.flash_base_addr;
1535
1536 do {
1537 udelay(1);
1538 /* Steps */
1539 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1540 if (ret_val != 0)
1541 break;
1542
1543 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1544 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1545 hsflctl.hsf_ctrl.fldbcount = size - 1;
1546 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1547 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1548
1549 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1550
1551 ret_val = e1000_flash_cycle_ich8lan(hw,
1552 ICH_FLASH_READ_COMMAND_TIMEOUT);
1553
1554 /*
1555 * Check if FCERR is set to 1, if set to 1, clear it
1556 * and try the whole sequence a few more times, else
1557 * read in (shift in) the Flash Data0, the order is
1558 * least significant byte first msb to lsb
1559 */
1560 if (ret_val == 0) {
1561 flash_data = er32flash(ICH_FLASH_FDATA0);
1562 if (size == 1) {
1563 *data = (u8)(flash_data & 0x000000FF);
1564 } else if (size == 2) {
1565 *data = (u16)(flash_data & 0x0000FFFF);
1566 }
1567 break;
1568 } else {
1569 /*
1570 * If we've gotten here, then things are probably
1571 * completely hosed, but if the error condition is
1572 * detected, it won't hurt to give it another try...
1573 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1574 */
1575 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1576 if (hsfsts.hsf_status.flcerr == 1) {
1577 /* Repeat for some time before giving up. */
1578 continue;
1579 } else if (hsfsts.hsf_status.flcdone == 0) {
1580 hw_dbg(hw, "Timeout error - flash cycle "
1581 "did not complete.");
1582 break;
1583 }
1584 }
1585 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1586
1587 return ret_val;
1588 }
1589
1590 /**
1591 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1592 * @hw: pointer to the HW structure
1593 * @offset: The offset (in bytes) of the word(s) to write.
1594 * @words: Size of data to write in words
1595 * @data: Pointer to the word(s) to write at offset.
1596 *
1597 * Writes a byte or word to the NVM using the flash access registers.
1598 **/
1599 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1600 u16 *data)
1601 {
1602 struct e1000_nvm_info *nvm = &hw->nvm;
1603 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1604 u16 i;
1605
1606 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1607 (words == 0)) {
1608 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1609 return -E1000_ERR_NVM;
1610 }
1611
1612 for (i = 0; i < words; i++) {
1613 dev_spec->shadow_ram[offset+i].modified = 1;
1614 dev_spec->shadow_ram[offset+i].value = data[i];
1615 }
1616
1617 return 0;
1618 }
1619
1620 /**
1621 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1622 * @hw: pointer to the HW structure
1623 *
1624 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1625 * which writes the checksum to the shadow ram. The changes in the shadow
1626 * ram are then committed to the EEPROM by processing each bank at a time
1627 * checking for the modified bit and writing only the pending changes.
1628 * After a successful commit, the shadow ram is cleared and is ready for
1629 * future writes.
1630 **/
1631 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1632 {
1633 struct e1000_nvm_info *nvm = &hw->nvm;
1634 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1635 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1636 s32 ret_val;
1637 u16 data;
1638
1639 ret_val = e1000e_update_nvm_checksum_generic(hw);
1640 if (ret_val)
1641 goto out;
1642
1643 if (nvm->type != e1000_nvm_flash_sw)
1644 goto out;
1645
1646 ret_val = e1000_acquire_swflag_ich8lan(hw);
1647 if (ret_val)
1648 goto out;
1649
1650 /*
1651 * We're writing to the opposite bank so if we're on bank 1,
1652 * write to bank 0 etc. We also need to erase the segment that
1653 * is going to be written
1654 */
1655 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1656 if (ret_val) {
1657 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
1658 bank = 0;
1659 }
1660
1661 if (bank == 0) {
1662 new_bank_offset = nvm->flash_bank_size;
1663 old_bank_offset = 0;
1664 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1665 if (ret_val) {
1666 e1000_release_swflag_ich8lan(hw);
1667 goto out;
1668 }
1669 } else {
1670 old_bank_offset = nvm->flash_bank_size;
1671 new_bank_offset = 0;
1672 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1673 if (ret_val) {
1674 e1000_release_swflag_ich8lan(hw);
1675 goto out;
1676 }
1677 }
1678
1679 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1680 /*
1681 * Determine whether to write the value stored
1682 * in the other NVM bank or a modified value stored
1683 * in the shadow RAM
1684 */
1685 if (dev_spec->shadow_ram[i].modified) {
1686 data = dev_spec->shadow_ram[i].value;
1687 } else {
1688 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1689 old_bank_offset,
1690 &data);
1691 if (ret_val)
1692 break;
1693 }
1694
1695 /*
1696 * If the word is 0x13, then make sure the signature bits
1697 * (15:14) are 11b until the commit has completed.
1698 * This will allow us to write 10b which indicates the
1699 * signature is valid. We want to do this after the write
1700 * has completed so that we don't mark the segment valid
1701 * while the write is still in progress
1702 */
1703 if (i == E1000_ICH_NVM_SIG_WORD)
1704 data |= E1000_ICH_NVM_SIG_MASK;
1705
1706 /* Convert offset to bytes. */
1707 act_offset = (i + new_bank_offset) << 1;
1708
1709 udelay(100);
1710 /* Write the bytes to the new bank. */
1711 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1712 act_offset,
1713 (u8)data);
1714 if (ret_val)
1715 break;
1716
1717 udelay(100);
1718 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1719 act_offset + 1,
1720 (u8)(data >> 8));
1721 if (ret_val)
1722 break;
1723 }
1724
1725 /*
1726 * Don't bother writing the segment valid bits if sector
1727 * programming failed.
1728 */
1729 if (ret_val) {
1730 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1731 hw_dbg(hw, "Flash commit failed.\n");
1732 e1000_release_swflag_ich8lan(hw);
1733 goto out;
1734 }
1735
1736 /*
1737 * Finally validate the new segment by setting bit 15:14
1738 * to 10b in word 0x13 , this can be done without an
1739 * erase as well since these bits are 11 to start with
1740 * and we need to change bit 14 to 0b
1741 */
1742 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1743 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1744 if (ret_val) {
1745 e1000_release_swflag_ich8lan(hw);
1746 goto out;
1747 }
1748 data &= 0xBFFF;
1749 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1750 act_offset * 2 + 1,
1751 (u8)(data >> 8));
1752 if (ret_val) {
1753 e1000_release_swflag_ich8lan(hw);
1754 goto out;
1755 }
1756
1757 /*
1758 * And invalidate the previously valid segment by setting
1759 * its signature word (0x13) high_byte to 0b. This can be
1760 * done without an erase because flash erase sets all bits
1761 * to 1's. We can write 1's to 0's without an erase
1762 */
1763 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1764 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1765 if (ret_val) {
1766 e1000_release_swflag_ich8lan(hw);
1767 goto out;
1768 }
1769
1770 /* Great! Everything worked, we can now clear the cached entries. */
1771 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1772 dev_spec->shadow_ram[i].modified = 0;
1773 dev_spec->shadow_ram[i].value = 0xFFFF;
1774 }
1775
1776 e1000_release_swflag_ich8lan(hw);
1777
1778 /*
1779 * Reload the EEPROM, or else modifications will not appear
1780 * until after the next adapter reset.
1781 */
1782 e1000e_reload_nvm(hw);
1783 msleep(10);
1784
1785 out:
1786 if (ret_val)
1787 hw_dbg(hw, "NVM update error: %d\n", ret_val);
1788
1789 return ret_val;
1790 }
1791
1792 /**
1793 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1794 * @hw: pointer to the HW structure
1795 *
1796 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1797 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1798 * calculated, in which case we need to calculate the checksum and set bit 6.
1799 **/
1800 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1801 {
1802 s32 ret_val;
1803 u16 data;
1804
1805 /*
1806 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1807 * needs to be fixed. This bit is an indication that the NVM
1808 * was prepared by OEM software and did not calculate the
1809 * checksum...a likely scenario.
1810 */
1811 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1812 if (ret_val)
1813 return ret_val;
1814
1815 if ((data & 0x40) == 0) {
1816 data |= 0x40;
1817 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1818 if (ret_val)
1819 return ret_val;
1820 ret_val = e1000e_update_nvm_checksum(hw);
1821 if (ret_val)
1822 return ret_val;
1823 }
1824
1825 return e1000e_validate_nvm_checksum_generic(hw);
1826 }
1827
1828 /**
1829 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1830 * @hw: pointer to the HW structure
1831 *
1832 * To prevent malicious write/erase of the NVM, set it to be read-only
1833 * so that the hardware ignores all write/erase cycles of the NVM via
1834 * the flash control registers. The shadow-ram copy of the NVM will
1835 * still be updated, however any updates to this copy will not stick
1836 * across driver reloads.
1837 **/
1838 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1839 {
1840 union ich8_flash_protected_range pr0;
1841 union ich8_hws_flash_status hsfsts;
1842 u32 gfpreg;
1843 s32 ret_val;
1844
1845 ret_val = e1000_acquire_swflag_ich8lan(hw);
1846 if (ret_val)
1847 return;
1848
1849 gfpreg = er32flash(ICH_FLASH_GFPREG);
1850
1851 /* Write-protect GbE Sector of NVM */
1852 pr0.regval = er32flash(ICH_FLASH_PR0);
1853 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1854 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1855 pr0.range.wpe = true;
1856 ew32flash(ICH_FLASH_PR0, pr0.regval);
1857
1858 /*
1859 * Lock down a subset of GbE Flash Control Registers, e.g.
1860 * PR0 to prevent the write-protection from being lifted.
1861 * Once FLOCKDN is set, the registers protected by it cannot
1862 * be written until FLOCKDN is cleared by a hardware reset.
1863 */
1864 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1865 hsfsts.hsf_status.flockdn = true;
1866 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1867
1868 e1000_release_swflag_ich8lan(hw);
1869 }
1870
1871 /**
1872 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1873 * @hw: pointer to the HW structure
1874 * @offset: The offset (in bytes) of the byte/word to read.
1875 * @size: Size of data to read, 1=byte 2=word
1876 * @data: The byte(s) to write to the NVM.
1877 *
1878 * Writes one/two bytes to the NVM using the flash access registers.
1879 **/
1880 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1881 u8 size, u16 data)
1882 {
1883 union ich8_hws_flash_status hsfsts;
1884 union ich8_hws_flash_ctrl hsflctl;
1885 u32 flash_linear_addr;
1886 u32 flash_data = 0;
1887 s32 ret_val;
1888 u8 count = 0;
1889
1890 if (size < 1 || size > 2 || data > size * 0xff ||
1891 offset > ICH_FLASH_LINEAR_ADDR_MASK)
1892 return -E1000_ERR_NVM;
1893
1894 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1895 hw->nvm.flash_base_addr;
1896
1897 do {
1898 udelay(1);
1899 /* Steps */
1900 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1901 if (ret_val)
1902 break;
1903
1904 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1905 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1906 hsflctl.hsf_ctrl.fldbcount = size -1;
1907 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1908 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1909
1910 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1911
1912 if (size == 1)
1913 flash_data = (u32)data & 0x00FF;
1914 else
1915 flash_data = (u32)data;
1916
1917 ew32flash(ICH_FLASH_FDATA0, flash_data);
1918
1919 /*
1920 * check if FCERR is set to 1 , if set to 1, clear it
1921 * and try the whole sequence a few more times else done
1922 */
1923 ret_val = e1000_flash_cycle_ich8lan(hw,
1924 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1925 if (!ret_val)
1926 break;
1927
1928 /*
1929 * If we're here, then things are most likely
1930 * completely hosed, but if the error condition
1931 * is detected, it won't hurt to give it another
1932 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1933 */
1934 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1935 if (hsfsts.hsf_status.flcerr == 1)
1936 /* Repeat for some time before giving up. */
1937 continue;
1938 if (hsfsts.hsf_status.flcdone == 0) {
1939 hw_dbg(hw, "Timeout error - flash cycle "
1940 "did not complete.");
1941 break;
1942 }
1943 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1944
1945 return ret_val;
1946 }
1947
1948 /**
1949 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1950 * @hw: pointer to the HW structure
1951 * @offset: The index of the byte to read.
1952 * @data: The byte to write to the NVM.
1953 *
1954 * Writes a single byte to the NVM using the flash access registers.
1955 **/
1956 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1957 u8 data)
1958 {
1959 u16 word = (u16)data;
1960
1961 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1962 }
1963
1964 /**
1965 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1966 * @hw: pointer to the HW structure
1967 * @offset: The offset of the byte to write.
1968 * @byte: The byte to write to the NVM.
1969 *
1970 * Writes a single byte to the NVM using the flash access registers.
1971 * Goes through a retry algorithm before giving up.
1972 **/
1973 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1974 u32 offset, u8 byte)
1975 {
1976 s32 ret_val;
1977 u16 program_retries;
1978
1979 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1980 if (!ret_val)
1981 return ret_val;
1982
1983 for (program_retries = 0; program_retries < 100; program_retries++) {
1984 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1985 udelay(100);
1986 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1987 if (!ret_val)
1988 break;
1989 }
1990 if (program_retries == 100)
1991 return -E1000_ERR_NVM;
1992
1993 return 0;
1994 }
1995
1996 /**
1997 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1998 * @hw: pointer to the HW structure
1999 * @bank: 0 for first bank, 1 for second bank, etc.
2000 *
2001 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2002 * bank N is 4096 * N + flash_reg_addr.
2003 **/
2004 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2005 {
2006 struct e1000_nvm_info *nvm = &hw->nvm;
2007 union ich8_hws_flash_status hsfsts;
2008 union ich8_hws_flash_ctrl hsflctl;
2009 u32 flash_linear_addr;
2010 /* bank size is in 16bit words - adjust to bytes */
2011 u32 flash_bank_size = nvm->flash_bank_size * 2;
2012 s32 ret_val;
2013 s32 count = 0;
2014 s32 iteration;
2015 s32 sector_size;
2016 s32 j;
2017
2018 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2019
2020 /*
2021 * Determine HW Sector size: Read BERASE bits of hw flash status
2022 * register
2023 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2024 * consecutive sectors. The start index for the nth Hw sector
2025 * can be calculated as = bank * 4096 + n * 256
2026 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2027 * The start index for the nth Hw sector can be calculated
2028 * as = bank * 4096
2029 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2030 * (ich9 only, otherwise error condition)
2031 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2032 */
2033 switch (hsfsts.hsf_status.berasesz) {
2034 case 0:
2035 /* Hw sector size 256 */
2036 sector_size = ICH_FLASH_SEG_SIZE_256;
2037 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2038 break;
2039 case 1:
2040 sector_size = ICH_FLASH_SEG_SIZE_4K;
2041 iteration = 1;
2042 break;
2043 case 2:
2044 sector_size = ICH_FLASH_SEG_SIZE_8K;
2045 iteration = 1;
2046 break;
2047 case 3:
2048 sector_size = ICH_FLASH_SEG_SIZE_64K;
2049 iteration = 1;
2050 break;
2051 default:
2052 return -E1000_ERR_NVM;
2053 }
2054
2055 /* Start with the base address, then add the sector offset. */
2056 flash_linear_addr = hw->nvm.flash_base_addr;
2057 flash_linear_addr += (bank) ? flash_bank_size : 0;
2058
2059 for (j = 0; j < iteration ; j++) {
2060 do {
2061 /* Steps */
2062 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2063 if (ret_val)
2064 return ret_val;
2065
2066 /*
2067 * Write a value 11 (block Erase) in Flash
2068 * Cycle field in hw flash control
2069 */
2070 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2071 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2072 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2073
2074 /*
2075 * Write the last 24 bits of an index within the
2076 * block into Flash Linear address field in Flash
2077 * Address.
2078 */
2079 flash_linear_addr += (j * sector_size);
2080 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2081
2082 ret_val = e1000_flash_cycle_ich8lan(hw,
2083 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2084 if (ret_val == 0)
2085 break;
2086
2087 /*
2088 * Check if FCERR is set to 1. If 1,
2089 * clear it and try the whole sequence
2090 * a few more times else Done
2091 */
2092 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2093 if (hsfsts.hsf_status.flcerr == 1)
2094 /* repeat for some time before giving up */
2095 continue;
2096 else if (hsfsts.hsf_status.flcdone == 0)
2097 return ret_val;
2098 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2099 }
2100
2101 return 0;
2102 }
2103
2104 /**
2105 * e1000_valid_led_default_ich8lan - Set the default LED settings
2106 * @hw: pointer to the HW structure
2107 * @data: Pointer to the LED settings
2108 *
2109 * Reads the LED default settings from the NVM to data. If the NVM LED
2110 * settings is all 0's or F's, set the LED default to a valid LED default
2111 * setting.
2112 **/
2113 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2114 {
2115 s32 ret_val;
2116
2117 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2118 if (ret_val) {
2119 hw_dbg(hw, "NVM Read Error\n");
2120 return ret_val;
2121 }
2122
2123 if (*data == ID_LED_RESERVED_0000 ||
2124 *data == ID_LED_RESERVED_FFFF)
2125 *data = ID_LED_DEFAULT_ICH8LAN;
2126
2127 return 0;
2128 }
2129
2130 /**
2131 * e1000_id_led_init_pchlan - store LED configurations
2132 * @hw: pointer to the HW structure
2133 *
2134 * PCH does not control LEDs via the LEDCTL register, rather it uses
2135 * the PHY LED configuration register.
2136 *
2137 * PCH also does not have an "always on" or "always off" mode which
2138 * complicates the ID feature. Instead of using the "on" mode to indicate
2139 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2140 * use "link_up" mode. The LEDs will still ID on request if there is no
2141 * link based on logic in e1000_led_[on|off]_pchlan().
2142 **/
2143 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2144 {
2145 struct e1000_mac_info *mac = &hw->mac;
2146 s32 ret_val;
2147 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2148 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2149 u16 data, i, temp, shift;
2150
2151 /* Get default ID LED modes */
2152 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2153 if (ret_val)
2154 goto out;
2155
2156 mac->ledctl_default = er32(LEDCTL);
2157 mac->ledctl_mode1 = mac->ledctl_default;
2158 mac->ledctl_mode2 = mac->ledctl_default;
2159
2160 for (i = 0; i < 4; i++) {
2161 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2162 shift = (i * 5);
2163 switch (temp) {
2164 case ID_LED_ON1_DEF2:
2165 case ID_LED_ON1_ON2:
2166 case ID_LED_ON1_OFF2:
2167 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2168 mac->ledctl_mode1 |= (ledctl_on << shift);
2169 break;
2170 case ID_LED_OFF1_DEF2:
2171 case ID_LED_OFF1_ON2:
2172 case ID_LED_OFF1_OFF2:
2173 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2174 mac->ledctl_mode1 |= (ledctl_off << shift);
2175 break;
2176 default:
2177 /* Do nothing */
2178 break;
2179 }
2180 switch (temp) {
2181 case ID_LED_DEF1_ON2:
2182 case ID_LED_ON1_ON2:
2183 case ID_LED_OFF1_ON2:
2184 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2185 mac->ledctl_mode2 |= (ledctl_on << shift);
2186 break;
2187 case ID_LED_DEF1_OFF2:
2188 case ID_LED_ON1_OFF2:
2189 case ID_LED_OFF1_OFF2:
2190 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2191 mac->ledctl_mode2 |= (ledctl_off << shift);
2192 break;
2193 default:
2194 /* Do nothing */
2195 break;
2196 }
2197 }
2198
2199 out:
2200 return ret_val;
2201 }
2202
2203 /**
2204 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2205 * @hw: pointer to the HW structure
2206 *
2207 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2208 * register, so the the bus width is hard coded.
2209 **/
2210 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2211 {
2212 struct e1000_bus_info *bus = &hw->bus;
2213 s32 ret_val;
2214
2215 ret_val = e1000e_get_bus_info_pcie(hw);
2216
2217 /*
2218 * ICH devices are "PCI Express"-ish. They have
2219 * a configuration space, but do not contain
2220 * PCI Express Capability registers, so bus width
2221 * must be hardcoded.
2222 */
2223 if (bus->width == e1000_bus_width_unknown)
2224 bus->width = e1000_bus_width_pcie_x1;
2225
2226 return ret_val;
2227 }
2228
2229 /**
2230 * e1000_reset_hw_ich8lan - Reset the hardware
2231 * @hw: pointer to the HW structure
2232 *
2233 * Does a full reset of the hardware which includes a reset of the PHY and
2234 * MAC.
2235 **/
2236 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2237 {
2238 u16 reg;
2239 u32 ctrl, icr, kab;
2240 s32 ret_val;
2241
2242 /*
2243 * Prevent the PCI-E bus from sticking if there is no TLP connection
2244 * on the last TLP read/write transaction when MAC is reset.
2245 */
2246 ret_val = e1000e_disable_pcie_master(hw);
2247 if (ret_val) {
2248 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
2249 }
2250
2251 hw_dbg(hw, "Masking off all interrupts\n");
2252 ew32(IMC, 0xffffffff);
2253
2254 /*
2255 * Disable the Transmit and Receive units. Then delay to allow
2256 * any pending transactions to complete before we hit the MAC
2257 * with the global reset.
2258 */
2259 ew32(RCTL, 0);
2260 ew32(TCTL, E1000_TCTL_PSP);
2261 e1e_flush();
2262
2263 msleep(10);
2264
2265 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2266 if (hw->mac.type == e1000_ich8lan) {
2267 /* Set Tx and Rx buffer allocation to 8k apiece. */
2268 ew32(PBA, E1000_PBA_8K);
2269 /* Set Packet Buffer Size to 16k. */
2270 ew32(PBS, E1000_PBS_16K);
2271 }
2272
2273 ctrl = er32(CTRL);
2274
2275 if (!e1000_check_reset_block(hw)) {
2276 /* Clear PHY Reset Asserted bit */
2277 if (hw->mac.type >= e1000_pchlan) {
2278 u32 status = er32(STATUS);
2279 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2280 }
2281
2282 /*
2283 * PHY HW reset requires MAC CORE reset at the same
2284 * time to make sure the interface between MAC and the
2285 * external PHY is reset.
2286 */
2287 ctrl |= E1000_CTRL_PHY_RST;
2288 }
2289 ret_val = e1000_acquire_swflag_ich8lan(hw);
2290 /* Whether or not the swflag was acquired, we need to reset the part */
2291 hw_dbg(hw, "Issuing a global reset to ich8lan\n");
2292 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2293 msleep(20);
2294
2295 if (!ret_val)
2296 e1000_release_swflag_ich8lan(hw);
2297
2298 if (ctrl & E1000_CTRL_PHY_RST)
2299 ret_val = hw->phy.ops.get_cfg_done(hw);
2300
2301 if (hw->mac.type >= e1000_ich10lan) {
2302 e1000_lan_init_done_ich8lan(hw);
2303 } else {
2304 ret_val = e1000e_get_auto_rd_done(hw);
2305 if (ret_val) {
2306 /*
2307 * When auto config read does not complete, do not
2308 * return with an error. This can happen in situations
2309 * where there is no eeprom and prevents getting link.
2310 */
2311 hw_dbg(hw, "Auto Read Done did not complete\n");
2312 }
2313 }
2314 /* Dummy read to clear the phy wakeup bit after lcd reset */
2315 if (hw->mac.type == e1000_pchlan)
2316 e1e_rphy(hw, BM_WUC, &reg);
2317
2318 /*
2319 * For PCH, this write will make sure that any noise
2320 * will be detected as a CRC error and be dropped rather than show up
2321 * as a bad packet to the DMA engine.
2322 */
2323 if (hw->mac.type == e1000_pchlan)
2324 ew32(CRC_OFFSET, 0x65656565);
2325
2326 ew32(IMC, 0xffffffff);
2327 icr = er32(ICR);
2328
2329 kab = er32(KABGTXD);
2330 kab |= E1000_KABGTXD_BGSQLBIAS;
2331 ew32(KABGTXD, kab);
2332
2333 if (hw->mac.type == e1000_pchlan)
2334 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2335
2336 return ret_val;
2337 }
2338
2339 /**
2340 * e1000_init_hw_ich8lan - Initialize the hardware
2341 * @hw: pointer to the HW structure
2342 *
2343 * Prepares the hardware for transmit and receive by doing the following:
2344 * - initialize hardware bits
2345 * - initialize LED identification
2346 * - setup receive address registers
2347 * - setup flow control
2348 * - setup transmit descriptors
2349 * - clear statistics
2350 **/
2351 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2352 {
2353 struct e1000_mac_info *mac = &hw->mac;
2354 u32 ctrl_ext, txdctl, snoop;
2355 s32 ret_val;
2356 u16 i;
2357
2358 e1000_initialize_hw_bits_ich8lan(hw);
2359
2360 /* Initialize identification LED */
2361 ret_val = mac->ops.id_led_init(hw);
2362 if (ret_val) {
2363 hw_dbg(hw, "Error initializing identification LED\n");
2364 return ret_val;
2365 }
2366
2367 /* Setup the receive address. */
2368 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2369
2370 /* Zero out the Multicast HASH table */
2371 hw_dbg(hw, "Zeroing the MTA\n");
2372 for (i = 0; i < mac->mta_reg_count; i++)
2373 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2374
2375 /*
2376 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2377 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2378 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2379 */
2380 if (hw->phy.type == e1000_phy_82578) {
2381 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2382 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2383 if (ret_val)
2384 return ret_val;
2385 }
2386
2387 /* Setup link and flow control */
2388 ret_val = e1000_setup_link_ich8lan(hw);
2389
2390 /* Set the transmit descriptor write-back policy for both queues */
2391 txdctl = er32(TXDCTL(0));
2392 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2393 E1000_TXDCTL_FULL_TX_DESC_WB;
2394 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2395 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2396 ew32(TXDCTL(0), txdctl);
2397 txdctl = er32(TXDCTL(1));
2398 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2399 E1000_TXDCTL_FULL_TX_DESC_WB;
2400 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2401 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2402 ew32(TXDCTL(1), txdctl);
2403
2404 /*
2405 * ICH8 has opposite polarity of no_snoop bits.
2406 * By default, we should use snoop behavior.
2407 */
2408 if (mac->type == e1000_ich8lan)
2409 snoop = PCIE_ICH8_SNOOP_ALL;
2410 else
2411 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2412 e1000e_set_pcie_no_snoop(hw, snoop);
2413
2414 ctrl_ext = er32(CTRL_EXT);
2415 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2416 ew32(CTRL_EXT, ctrl_ext);
2417
2418 /*
2419 * Clear all of the statistics registers (clear on read). It is
2420 * important that we do this after we have tried to establish link
2421 * because the symbol error count will increment wildly if there
2422 * is no link.
2423 */
2424 e1000_clear_hw_cntrs_ich8lan(hw);
2425
2426 return 0;
2427 }
2428 /**
2429 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2430 * @hw: pointer to the HW structure
2431 *
2432 * Sets/Clears required hardware bits necessary for correctly setting up the
2433 * hardware for transmit and receive.
2434 **/
2435 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2436 {
2437 u32 reg;
2438
2439 /* Extended Device Control */
2440 reg = er32(CTRL_EXT);
2441 reg |= (1 << 22);
2442 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2443 if (hw->mac.type >= e1000_pchlan)
2444 reg |= E1000_CTRL_EXT_PHYPDEN;
2445 ew32(CTRL_EXT, reg);
2446
2447 /* Transmit Descriptor Control 0 */
2448 reg = er32(TXDCTL(0));
2449 reg |= (1 << 22);
2450 ew32(TXDCTL(0), reg);
2451
2452 /* Transmit Descriptor Control 1 */
2453 reg = er32(TXDCTL(1));
2454 reg |= (1 << 22);
2455 ew32(TXDCTL(1), reg);
2456
2457 /* Transmit Arbitration Control 0 */
2458 reg = er32(TARC(0));
2459 if (hw->mac.type == e1000_ich8lan)
2460 reg |= (1 << 28) | (1 << 29);
2461 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2462 ew32(TARC(0), reg);
2463
2464 /* Transmit Arbitration Control 1 */
2465 reg = er32(TARC(1));
2466 if (er32(TCTL) & E1000_TCTL_MULR)
2467 reg &= ~(1 << 28);
2468 else
2469 reg |= (1 << 28);
2470 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2471 ew32(TARC(1), reg);
2472
2473 /* Device Status */
2474 if (hw->mac.type == e1000_ich8lan) {
2475 reg = er32(STATUS);
2476 reg &= ~(1 << 31);
2477 ew32(STATUS, reg);
2478 }
2479 }
2480
2481 /**
2482 * e1000_setup_link_ich8lan - Setup flow control and link settings
2483 * @hw: pointer to the HW structure
2484 *
2485 * Determines which flow control settings to use, then configures flow
2486 * control. Calls the appropriate media-specific link configuration
2487 * function. Assuming the adapter has a valid link partner, a valid link
2488 * should be established. Assumes the hardware has previously been reset
2489 * and the transmitter and receiver are not enabled.
2490 **/
2491 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2492 {
2493 s32 ret_val;
2494
2495 if (e1000_check_reset_block(hw))
2496 return 0;
2497
2498 /*
2499 * ICH parts do not have a word in the NVM to determine
2500 * the default flow control setting, so we explicitly
2501 * set it to full.
2502 */
2503 if (hw->fc.requested_mode == e1000_fc_default) {
2504 /* Workaround h/w hang when Tx flow control enabled */
2505 if (hw->mac.type == e1000_pchlan)
2506 hw->fc.requested_mode = e1000_fc_rx_pause;
2507 else
2508 hw->fc.requested_mode = e1000_fc_full;
2509 }
2510
2511 /*
2512 * Save off the requested flow control mode for use later. Depending
2513 * on the link partner's capabilities, we may or may not use this mode.
2514 */
2515 hw->fc.current_mode = hw->fc.requested_mode;
2516
2517 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2518 hw->fc.current_mode);
2519
2520 /* Continue to configure the copper link. */
2521 ret_val = e1000_setup_copper_link_ich8lan(hw);
2522 if (ret_val)
2523 return ret_val;
2524
2525 ew32(FCTTV, hw->fc.pause_time);
2526 if ((hw->phy.type == e1000_phy_82578) ||
2527 (hw->phy.type == e1000_phy_82577)) {
2528 ret_val = hw->phy.ops.write_phy_reg(hw,
2529 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2530 hw->fc.pause_time);
2531 if (ret_val)
2532 return ret_val;
2533 }
2534
2535 return e1000e_set_fc_watermarks(hw);
2536 }
2537
2538 /**
2539 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2540 * @hw: pointer to the HW structure
2541 *
2542 * Configures the kumeran interface to the PHY to wait the appropriate time
2543 * when polling the PHY, then call the generic setup_copper_link to finish
2544 * configuring the copper link.
2545 **/
2546 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2547 {
2548 u32 ctrl;
2549 s32 ret_val;
2550 u16 reg_data;
2551
2552 ctrl = er32(CTRL);
2553 ctrl |= E1000_CTRL_SLU;
2554 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2555 ew32(CTRL, ctrl);
2556
2557 /*
2558 * Set the mac to wait the maximum time between each iteration
2559 * and increase the max iterations when polling the phy;
2560 * this fixes erroneous timeouts at 10Mbps.
2561 */
2562 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2563 if (ret_val)
2564 return ret_val;
2565 ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2566 if (ret_val)
2567 return ret_val;
2568 reg_data |= 0x3F;
2569 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2570 if (ret_val)
2571 return ret_val;
2572
2573 switch (hw->phy.type) {
2574 case e1000_phy_igp_3:
2575 ret_val = e1000e_copper_link_setup_igp(hw);
2576 if (ret_val)
2577 return ret_val;
2578 break;
2579 case e1000_phy_bm:
2580 case e1000_phy_82578:
2581 ret_val = e1000e_copper_link_setup_m88(hw);
2582 if (ret_val)
2583 return ret_val;
2584 break;
2585 case e1000_phy_82577:
2586 ret_val = e1000_copper_link_setup_82577(hw);
2587 if (ret_val)
2588 return ret_val;
2589 break;
2590 case e1000_phy_ife:
2591 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2592 &reg_data);
2593 if (ret_val)
2594 return ret_val;
2595
2596 reg_data &= ~IFE_PMC_AUTO_MDIX;
2597
2598 switch (hw->phy.mdix) {
2599 case 1:
2600 reg_data &= ~IFE_PMC_FORCE_MDIX;
2601 break;
2602 case 2:
2603 reg_data |= IFE_PMC_FORCE_MDIX;
2604 break;
2605 case 0:
2606 default:
2607 reg_data |= IFE_PMC_AUTO_MDIX;
2608 break;
2609 }
2610 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2611 reg_data);
2612 if (ret_val)
2613 return ret_val;
2614 break;
2615 default:
2616 break;
2617 }
2618 return e1000e_setup_copper_link(hw);
2619 }
2620
2621 /**
2622 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2623 * @hw: pointer to the HW structure
2624 * @speed: pointer to store current link speed
2625 * @duplex: pointer to store the current link duplex
2626 *
2627 * Calls the generic get_speed_and_duplex to retrieve the current link
2628 * information and then calls the Kumeran lock loss workaround for links at
2629 * gigabit speeds.
2630 **/
2631 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2632 u16 *duplex)
2633 {
2634 s32 ret_val;
2635
2636 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2637 if (ret_val)
2638 return ret_val;
2639
2640 if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) {
2641 ret_val = e1000e_write_kmrn_reg(hw,
2642 E1000_KMRNCTRLSTA_K1_CONFIG,
2643 E1000_KMRNCTRLSTA_K1_DISABLE);
2644 if (ret_val)
2645 return ret_val;
2646 }
2647
2648 if ((hw->mac.type == e1000_ich8lan) &&
2649 (hw->phy.type == e1000_phy_igp_3) &&
2650 (*speed == SPEED_1000)) {
2651 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2652 }
2653
2654 return ret_val;
2655 }
2656
2657 /**
2658 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2659 * @hw: pointer to the HW structure
2660 *
2661 * Work-around for 82566 Kumeran PCS lock loss:
2662 * On link status change (i.e. PCI reset, speed change) and link is up and
2663 * speed is gigabit-
2664 * 0) if workaround is optionally disabled do nothing
2665 * 1) wait 1ms for Kumeran link to come up
2666 * 2) check Kumeran Diagnostic register PCS lock loss bit
2667 * 3) if not set the link is locked (all is good), otherwise...
2668 * 4) reset the PHY
2669 * 5) repeat up to 10 times
2670 * Note: this is only called for IGP3 copper when speed is 1gb.
2671 **/
2672 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2673 {
2674 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2675 u32 phy_ctrl;
2676 s32 ret_val;
2677 u16 i, data;
2678 bool link;
2679
2680 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2681 return 0;
2682
2683 /*
2684 * Make sure link is up before proceeding. If not just return.
2685 * Attempting this while link is negotiating fouled up link
2686 * stability
2687 */
2688 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2689 if (!link)
2690 return 0;
2691
2692 for (i = 0; i < 10; i++) {
2693 /* read once to clear */
2694 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2695 if (ret_val)
2696 return ret_val;
2697 /* and again to get new status */
2698 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2699 if (ret_val)
2700 return ret_val;
2701
2702 /* check for PCS lock */
2703 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2704 return 0;
2705
2706 /* Issue PHY reset */
2707 e1000_phy_hw_reset(hw);
2708 mdelay(5);
2709 }
2710 /* Disable GigE link negotiation */
2711 phy_ctrl = er32(PHY_CTRL);
2712 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2713 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2714 ew32(PHY_CTRL, phy_ctrl);
2715
2716 /*
2717 * Call gig speed drop workaround on Gig disable before accessing
2718 * any PHY registers
2719 */
2720 e1000e_gig_downshift_workaround_ich8lan(hw);
2721
2722 /* unable to acquire PCS lock */
2723 return -E1000_ERR_PHY;
2724 }
2725
2726 /**
2727 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2728 * @hw: pointer to the HW structure
2729 * @state: boolean value used to set the current Kumeran workaround state
2730 *
2731 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2732 * /disabled - FALSE).
2733 **/
2734 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2735 bool state)
2736 {
2737 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2738
2739 if (hw->mac.type != e1000_ich8lan) {
2740 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2741 return;
2742 }
2743
2744 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2745 }
2746
2747 /**
2748 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2749 * @hw: pointer to the HW structure
2750 *
2751 * Workaround for 82566 power-down on D3 entry:
2752 * 1) disable gigabit link
2753 * 2) write VR power-down enable
2754 * 3) read it back
2755 * Continue if successful, else issue LCD reset and repeat
2756 **/
2757 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2758 {
2759 u32 reg;
2760 u16 data;
2761 u8 retry = 0;
2762
2763 if (hw->phy.type != e1000_phy_igp_3)
2764 return;
2765
2766 /* Try the workaround twice (if needed) */
2767 do {
2768 /* Disable link */
2769 reg = er32(PHY_CTRL);
2770 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2771 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2772 ew32(PHY_CTRL, reg);
2773
2774 /*
2775 * Call gig speed drop workaround on Gig disable before
2776 * accessing any PHY registers
2777 */
2778 if (hw->mac.type == e1000_ich8lan)
2779 e1000e_gig_downshift_workaround_ich8lan(hw);
2780
2781 /* Write VR power-down enable */
2782 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2783 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2784 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2785
2786 /* Read it back and test */
2787 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2788 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2789 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2790 break;
2791
2792 /* Issue PHY reset and repeat at most one more time */
2793 reg = er32(CTRL);
2794 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2795 retry++;
2796 } while (retry);
2797 }
2798
2799 /**
2800 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2801 * @hw: pointer to the HW structure
2802 *
2803 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2804 * LPLU, Gig disable, MDIC PHY reset):
2805 * 1) Set Kumeran Near-end loopback
2806 * 2) Clear Kumeran Near-end loopback
2807 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2808 **/
2809 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2810 {
2811 s32 ret_val;
2812 u16 reg_data;
2813
2814 if ((hw->mac.type != e1000_ich8lan) ||
2815 (hw->phy.type != e1000_phy_igp_3))
2816 return;
2817
2818 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2819 &reg_data);
2820 if (ret_val)
2821 return;
2822 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2823 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2824 reg_data);
2825 if (ret_val)
2826 return;
2827 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2828 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2829 reg_data);
2830 }
2831
2832 /**
2833 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2834 * @hw: pointer to the HW structure
2835 *
2836 * During S0 to Sx transition, it is possible the link remains at gig
2837 * instead of negotiating to a lower speed. Before going to Sx, set
2838 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2839 * to a lower speed.
2840 *
2841 * Should only be called for applicable parts.
2842 **/
2843 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2844 {
2845 u32 phy_ctrl;
2846
2847 switch (hw->mac.type) {
2848 case e1000_ich9lan:
2849 case e1000_ich10lan:
2850 case e1000_pchlan:
2851 phy_ctrl = er32(PHY_CTRL);
2852 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2853 E1000_PHY_CTRL_GBE_DISABLE;
2854 ew32(PHY_CTRL, phy_ctrl);
2855
2856 if (hw->mac.type == e1000_pchlan)
2857 e1000_phy_hw_reset_ich8lan(hw);
2858 default:
2859 break;
2860 }
2861
2862 return;
2863 }
2864
2865 /**
2866 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2867 * @hw: pointer to the HW structure
2868 *
2869 * Return the LED back to the default configuration.
2870 **/
2871 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2872 {
2873 if (hw->phy.type == e1000_phy_ife)
2874 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2875
2876 ew32(LEDCTL, hw->mac.ledctl_default);
2877 return 0;
2878 }
2879
2880 /**
2881 * e1000_led_on_ich8lan - Turn LEDs on
2882 * @hw: pointer to the HW structure
2883 *
2884 * Turn on the LEDs.
2885 **/
2886 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2887 {
2888 if (hw->phy.type == e1000_phy_ife)
2889 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2890 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2891
2892 ew32(LEDCTL, hw->mac.ledctl_mode2);
2893 return 0;
2894 }
2895
2896 /**
2897 * e1000_led_off_ich8lan - Turn LEDs off
2898 * @hw: pointer to the HW structure
2899 *
2900 * Turn off the LEDs.
2901 **/
2902 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2903 {
2904 if (hw->phy.type == e1000_phy_ife)
2905 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2906 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2907
2908 ew32(LEDCTL, hw->mac.ledctl_mode1);
2909 return 0;
2910 }
2911
2912 /**
2913 * e1000_setup_led_pchlan - Configures SW controllable LED
2914 * @hw: pointer to the HW structure
2915 *
2916 * This prepares the SW controllable LED for use.
2917 **/
2918 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
2919 {
2920 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2921 (u16)hw->mac.ledctl_mode1);
2922 }
2923
2924 /**
2925 * e1000_cleanup_led_pchlan - Restore the default LED operation
2926 * @hw: pointer to the HW structure
2927 *
2928 * Return the LED back to the default configuration.
2929 **/
2930 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
2931 {
2932 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2933 (u16)hw->mac.ledctl_default);
2934 }
2935
2936 /**
2937 * e1000_led_on_pchlan - Turn LEDs on
2938 * @hw: pointer to the HW structure
2939 *
2940 * Turn on the LEDs.
2941 **/
2942 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
2943 {
2944 u16 data = (u16)hw->mac.ledctl_mode2;
2945 u32 i, led;
2946
2947 /*
2948 * If no link, then turn LED on by setting the invert bit
2949 * for each LED that's mode is "link_up" in ledctl_mode2.
2950 */
2951 if (!(er32(STATUS) & E1000_STATUS_LU)) {
2952 for (i = 0; i < 3; i++) {
2953 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2954 if ((led & E1000_PHY_LED0_MODE_MASK) !=
2955 E1000_LEDCTL_MODE_LINK_UP)
2956 continue;
2957 if (led & E1000_PHY_LED0_IVRT)
2958 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2959 else
2960 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2961 }
2962 }
2963
2964 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
2965 }
2966
2967 /**
2968 * e1000_led_off_pchlan - Turn LEDs off
2969 * @hw: pointer to the HW structure
2970 *
2971 * Turn off the LEDs.
2972 **/
2973 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
2974 {
2975 u16 data = (u16)hw->mac.ledctl_mode1;
2976 u32 i, led;
2977
2978 /*
2979 * If no link, then turn LED off by clearing the invert bit
2980 * for each LED that's mode is "link_up" in ledctl_mode1.
2981 */
2982 if (!(er32(STATUS) & E1000_STATUS_LU)) {
2983 for (i = 0; i < 3; i++) {
2984 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2985 if ((led & E1000_PHY_LED0_MODE_MASK) !=
2986 E1000_LEDCTL_MODE_LINK_UP)
2987 continue;
2988 if (led & E1000_PHY_LED0_IVRT)
2989 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2990 else
2991 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2992 }
2993 }
2994
2995 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
2996 }
2997
2998 /**
2999 * e1000_get_cfg_done_ich8lan - Read config done bit
3000 * @hw: pointer to the HW structure
3001 *
3002 * Read the management control register for the config done bit for
3003 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3004 * to read the config done bit, so an error is *ONLY* logged and returns
3005 * 0. If we were to return with error, EEPROM-less silicon
3006 * would not be able to be reset or change link.
3007 **/
3008 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3009 {
3010 u32 bank = 0;
3011
3012 if (hw->mac.type >= e1000_pchlan) {
3013 u32 status = er32(STATUS);
3014
3015 if (status & E1000_STATUS_PHYRA)
3016 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3017 else
3018 hw_dbg(hw,
3019 "PHY Reset Asserted not set - needs delay\n");
3020 }
3021
3022 e1000e_get_cfg_done(hw);
3023
3024 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3025 if ((hw->mac.type != e1000_ich10lan) &&
3026 (hw->mac.type != e1000_pchlan)) {
3027 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3028 (hw->phy.type == e1000_phy_igp_3)) {
3029 e1000e_phy_init_script_igp3(hw);
3030 }
3031 } else {
3032 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3033 /* Maybe we should do a basic PHY config */
3034 hw_dbg(hw, "EEPROM not present\n");
3035 return -E1000_ERR_CONFIG;
3036 }
3037 }
3038
3039 return 0;
3040 }
3041
3042 /**
3043 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3044 * @hw: pointer to the HW structure
3045 *
3046 * Clears hardware counters specific to the silicon family and calls
3047 * clear_hw_cntrs_generic to clear all general purpose counters.
3048 **/
3049 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3050 {
3051 u32 temp;
3052 u16 phy_data;
3053
3054 e1000e_clear_hw_cntrs_base(hw);
3055
3056 temp = er32(ALGNERRC);
3057 temp = er32(RXERRC);
3058 temp = er32(TNCRS);
3059 temp = er32(CEXTERR);
3060 temp = er32(TSCTC);
3061 temp = er32(TSCTFC);
3062
3063 temp = er32(MGTPRC);
3064 temp = er32(MGTPDC);
3065 temp = er32(MGTPTC);
3066
3067 temp = er32(IAC);
3068 temp = er32(ICRXOC);
3069
3070 /* Clear PHY statistics registers */
3071 if ((hw->phy.type == e1000_phy_82578) ||
3072 (hw->phy.type == e1000_phy_82577)) {
3073 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
3074 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
3075 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
3076 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
3077 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
3078 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
3079 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
3080 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
3081 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
3082 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
3083 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
3084 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
3085 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
3086 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
3087 }
3088 }
3089
3090 static struct e1000_mac_operations ich8_mac_ops = {
3091 .id_led_init = e1000e_id_led_init,
3092 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3093 .check_for_link = e1000_check_for_copper_link_ich8lan,
3094 /* cleanup_led dependent on mac type */
3095 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3096 .get_bus_info = e1000_get_bus_info_ich8lan,
3097 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3098 /* led_on dependent on mac type */
3099 /* led_off dependent on mac type */
3100 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3101 .reset_hw = e1000_reset_hw_ich8lan,
3102 .init_hw = e1000_init_hw_ich8lan,
3103 .setup_link = e1000_setup_link_ich8lan,
3104 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3105 /* id_led_init dependent on mac type */
3106 };
3107
3108 static struct e1000_phy_operations ich8_phy_ops = {
3109 .acquire_phy = e1000_acquire_swflag_ich8lan,
3110 .check_reset_block = e1000_check_reset_block_ich8lan,
3111 .commit_phy = NULL,
3112 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
3113 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3114 .get_cable_length = e1000e_get_cable_length_igp_2,
3115 .get_phy_info = e1000_get_phy_info_ich8lan,
3116 .read_phy_reg = e1000e_read_phy_reg_igp,
3117 .release_phy = e1000_release_swflag_ich8lan,
3118 .reset_phy = e1000_phy_hw_reset_ich8lan,
3119 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3120 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3121 .write_phy_reg = e1000e_write_phy_reg_igp,
3122 };
3123
3124 static struct e1000_nvm_operations ich8_nvm_ops = {
3125 .acquire_nvm = e1000_acquire_swflag_ich8lan,
3126 .read_nvm = e1000_read_nvm_ich8lan,
3127 .release_nvm = e1000_release_swflag_ich8lan,
3128 .update_nvm = e1000_update_nvm_checksum_ich8lan,
3129 .valid_led_default = e1000_valid_led_default_ich8lan,
3130 .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
3131 .write_nvm = e1000_write_nvm_ich8lan,
3132 };
3133
3134 struct e1000_info e1000_ich8_info = {
3135 .mac = e1000_ich8lan,
3136 .flags = FLAG_HAS_WOL
3137 | FLAG_IS_ICH
3138 | FLAG_RX_CSUM_ENABLED
3139 | FLAG_HAS_CTRLEXT_ON_LOAD
3140 | FLAG_HAS_AMT
3141 | FLAG_HAS_FLASH
3142 | FLAG_APME_IN_WUC,
3143 .pba = 8,
3144 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3145 .get_variants = e1000_get_variants_ich8lan,
3146 .mac_ops = &ich8_mac_ops,
3147 .phy_ops = &ich8_phy_ops,
3148 .nvm_ops = &ich8_nvm_ops,
3149 };
3150
3151 struct e1000_info e1000_ich9_info = {
3152 .mac = e1000_ich9lan,
3153 .flags = FLAG_HAS_JUMBO_FRAMES
3154 | FLAG_IS_ICH
3155 | FLAG_HAS_WOL
3156 | FLAG_RX_CSUM_ENABLED
3157 | FLAG_HAS_CTRLEXT_ON_LOAD
3158 | FLAG_HAS_AMT
3159 | FLAG_HAS_ERT
3160 | FLAG_HAS_FLASH
3161 | FLAG_APME_IN_WUC,
3162 .pba = 10,
3163 .max_hw_frame_size = DEFAULT_JUMBO,
3164 .get_variants = e1000_get_variants_ich8lan,
3165 .mac_ops = &ich8_mac_ops,
3166 .phy_ops = &ich8_phy_ops,
3167 .nvm_ops = &ich8_nvm_ops,
3168 };
3169
3170 struct e1000_info e1000_ich10_info = {
3171 .mac = e1000_ich10lan,
3172 .flags = FLAG_HAS_JUMBO_FRAMES
3173 | FLAG_IS_ICH
3174 | FLAG_HAS_WOL
3175 | FLAG_RX_CSUM_ENABLED
3176 | FLAG_HAS_CTRLEXT_ON_LOAD
3177 | FLAG_HAS_AMT
3178 | FLAG_HAS_ERT
3179 | FLAG_HAS_FLASH
3180 | FLAG_APME_IN_WUC,
3181 .pba = 10,
3182 .max_hw_frame_size = DEFAULT_JUMBO,
3183 .get_variants = e1000_get_variants_ich8lan,
3184 .mac_ops = &ich8_mac_ops,
3185 .phy_ops = &ich8_phy_ops,
3186 .nvm_ops = &ich8_nvm_ops,
3187 };
3188
3189 struct e1000_info e1000_pch_info = {
3190 .mac = e1000_pchlan,
3191 .flags = FLAG_IS_ICH
3192 | FLAG_HAS_WOL
3193 | FLAG_RX_CSUM_ENABLED
3194 | FLAG_HAS_CTRLEXT_ON_LOAD
3195 | FLAG_HAS_AMT
3196 | FLAG_HAS_FLASH
3197 | FLAG_HAS_JUMBO_FRAMES
3198 | FLAG_APME_IN_WUC,
3199 .pba = 26,
3200 .max_hw_frame_size = 4096,
3201 .get_variants = e1000_get_variants_ich8lan,
3202 .mac_ops = &ich8_mac_ops,
3203 .phy_ops = &ich8_phy_ops,
3204 .nvm_ops = &ich8_nvm_ops,
3205 };
Support for the Chinese Samsung S3C2440 based development boards