2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
45 #include <asm/proto.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
53 #include <mach_apic.h>
58 unsigned move_cleanup_count
;
60 u8 move_in_progress
: 1;
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 struct irq_cfg irq_cfg
[NR_IRQS
] __read_mostly
= {
65 [0] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
66 [1] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
67 [2] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
68 [3] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
69 [4] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
70 [5] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
71 [6] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
72 [7] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
73 [8] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
74 [9] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
75 [10] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
76 [11] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
77 [12] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
78 [13] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
79 [14] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
80 [15] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
83 static int assign_irq_vector(int irq
, cpumask_t mask
);
85 #define __apicdebuginit __init
87 int sis_apic_bug
; /* not actually supported, dummy for compile */
89 static int no_timer_check
;
91 static int disable_timer_pin_1 __initdata
;
93 int timer_over_8254 __initdata
= 1;
95 /* Where if anywhere is the i8259 connect in external int mode */
96 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
98 static DEFINE_SPINLOCK(ioapic_lock
);
99 DEFINE_SPINLOCK(vector_lock
);
102 * # of IRQ routing registers
104 int nr_ioapic_registers
[MAX_IO_APICS
];
106 /* I/O APIC entries */
107 struct mpc_config_ioapic mp_ioapics
[MAX_IO_APICS
];
110 /* MP IRQ source entries */
111 struct mpc_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
113 /* # of MP IRQ source entries */
117 * Rough estimation of how many shared IRQs there are, can
118 * be changed anytime.
120 #define MAX_PLUS_SHARED_IRQS NR_IRQS
121 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
124 * This is performance-critical, we want to do it O(1)
126 * the indexing order of this array favors 1:1 mappings
127 * between pins and IRQs.
130 static struct irq_pin_list
{
131 short apic
, pin
, next
;
132 } irq_2_pin
[PIN_MAP_SIZE
];
136 unsigned int unused
[3];
140 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
142 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
143 + (mp_ioapics
[idx
].mpc_apicaddr
& ~PAGE_MASK
);
146 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
148 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
149 writel(reg
, &io_apic
->index
);
150 return readl(&io_apic
->data
);
153 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
155 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
156 writel(reg
, &io_apic
->index
);
157 writel(value
, &io_apic
->data
);
161 * Re-write a value: to be used for read-modify-write
162 * cycles where the read already set up the index register.
164 static inline void io_apic_modify(unsigned int apic
, unsigned int value
)
166 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
167 writel(value
, &io_apic
->data
);
170 static int io_apic_level_ack_pending(unsigned int irq
)
172 struct irq_pin_list
*entry
;
176 spin_lock_irqsave(&ioapic_lock
, flags
);
177 entry
= irq_2_pin
+ irq
;
185 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
186 /* Is the remote IRR bit set? */
187 pending
|= (reg
>> 14) & 1;
190 entry
= irq_2_pin
+ entry
->next
;
192 spin_unlock_irqrestore(&ioapic_lock
, flags
);
197 * Synchronize the IO-APIC and the CPU by doing
198 * a dummy read from the IO-APIC
200 static inline void io_apic_sync(unsigned int apic
)
202 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
203 readl(&io_apic
->data
);
206 #define __DO_ACTION(R, ACTION, FINAL) \
210 struct irq_pin_list *entry = irq_2_pin + irq; \
212 BUG_ON(irq >= NR_IRQS); \
218 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
220 io_apic_modify(entry->apic, reg); \
224 entry = irq_2_pin + entry->next; \
229 struct { u32 w1
, w2
; };
230 struct IO_APIC_route_entry entry
;
233 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
235 union entry_union eu
;
237 spin_lock_irqsave(&ioapic_lock
, flags
);
238 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
239 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
240 spin_unlock_irqrestore(&ioapic_lock
, flags
);
245 * When we write a new IO APIC routing entry, we need to write the high
246 * word first! If the mask bit in the low word is clear, we will enable
247 * the interrupt, and we need to make sure the entry is fully populated
248 * before that happens.
251 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
253 union entry_union eu
;
255 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
256 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
259 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
262 spin_lock_irqsave(&ioapic_lock
, flags
);
263 __ioapic_write_entry(apic
, pin
, e
);
264 spin_unlock_irqrestore(&ioapic_lock
, flags
);
268 * When we mask an IO APIC routing entry, we need to write the low
269 * word first, in order to set the mask bit before we change the
272 static void ioapic_mask_entry(int apic
, int pin
)
275 union entry_union eu
= { .entry
.mask
= 1 };
277 spin_lock_irqsave(&ioapic_lock
, flags
);
278 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
279 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
280 spin_unlock_irqrestore(&ioapic_lock
, flags
);
284 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
287 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
289 BUG_ON(irq
>= NR_IRQS
);
296 io_apic_write(apic
, 0x11 + pin
*2, dest
);
297 reg
= io_apic_read(apic
, 0x10 + pin
*2);
300 io_apic_modify(apic
, reg
);
303 entry
= irq_2_pin
+ entry
->next
;
307 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
309 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
314 cpus_and(tmp
, mask
, cpu_online_map
);
318 if (assign_irq_vector(irq
, mask
))
321 cpus_and(tmp
, cfg
->domain
, mask
);
322 dest
= cpu_mask_to_apicid(tmp
);
325 * Only the high 8 bits are valid.
327 dest
= SET_APIC_LOGICAL_ID(dest
);
329 spin_lock_irqsave(&ioapic_lock
, flags
);
330 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
331 irq_desc
[irq
].affinity
= mask
;
332 spin_unlock_irqrestore(&ioapic_lock
, flags
);
337 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
338 * shared ISA-space IRQs, so we have to support them. We are super
339 * fast in the common case, and fast for shared ISA-space IRQs.
341 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
343 static int first_free_entry
= NR_IRQS
;
344 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
346 BUG_ON(irq
>= NR_IRQS
);
348 entry
= irq_2_pin
+ entry
->next
;
350 if (entry
->pin
!= -1) {
351 entry
->next
= first_free_entry
;
352 entry
= irq_2_pin
+ entry
->next
;
353 if (++first_free_entry
>= PIN_MAP_SIZE
)
354 panic("io_apic.c: ran out of irq_2_pin entries!");
361 #define DO_ACTION(name,R,ACTION, FINAL) \
363 static void name##_IO_APIC_irq (unsigned int irq) \
364 __DO_ACTION(R, ACTION, FINAL)
366 DO_ACTION( __mask
, 0, |= 0x00010000, io_apic_sync(entry
->apic
) )
368 DO_ACTION( __unmask
, 0, &= 0xfffeffff, )
371 static void mask_IO_APIC_irq (unsigned int irq
)
375 spin_lock_irqsave(&ioapic_lock
, flags
);
376 __mask_IO_APIC_irq(irq
);
377 spin_unlock_irqrestore(&ioapic_lock
, flags
);
380 static void unmask_IO_APIC_irq (unsigned int irq
)
384 spin_lock_irqsave(&ioapic_lock
, flags
);
385 __unmask_IO_APIC_irq(irq
);
386 spin_unlock_irqrestore(&ioapic_lock
, flags
);
389 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
391 struct IO_APIC_route_entry entry
;
393 /* Check delivery_mode to be sure we're not clearing an SMI pin */
394 entry
= ioapic_read_entry(apic
, pin
);
395 if (entry
.delivery_mode
== dest_SMI
)
398 * Disable it in the IO-APIC irq-routing table:
400 ioapic_mask_entry(apic
, pin
);
403 static void clear_IO_APIC (void)
407 for (apic
= 0; apic
< nr_ioapics
; apic
++)
408 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
409 clear_IO_APIC_pin(apic
, pin
);
412 int skip_ioapic_setup
;
415 static int __init
parse_noapic(char *str
)
417 disable_ioapic_setup();
420 early_param("noapic", parse_noapic
);
422 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
423 static int __init
disable_timer_pin_setup(char *arg
)
425 disable_timer_pin_1
= 1;
428 __setup("disable_timer_pin_1", disable_timer_pin_setup
);
430 static int __init
setup_disable_8254_timer(char *s
)
432 timer_over_8254
= -1;
435 static int __init
setup_enable_8254_timer(char *s
)
441 __setup("disable_8254_timer", setup_disable_8254_timer
);
442 __setup("enable_8254_timer", setup_enable_8254_timer
);
446 * Find the IRQ entry number of a certain pin.
448 static int find_irq_entry(int apic
, int pin
, int type
)
452 for (i
= 0; i
< mp_irq_entries
; i
++)
453 if (mp_irqs
[i
].mpc_irqtype
== type
&&
454 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
455 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
456 mp_irqs
[i
].mpc_dstirq
== pin
)
463 * Find the pin to which IRQ[irq] (ISA) is connected
465 static int __init
find_isa_irq_pin(int irq
, int type
)
469 for (i
= 0; i
< mp_irq_entries
; i
++) {
470 int lbus
= mp_irqs
[i
].mpc_srcbus
;
472 if (test_bit(lbus
, mp_bus_not_pci
) &&
473 (mp_irqs
[i
].mpc_irqtype
== type
) &&
474 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
476 return mp_irqs
[i
].mpc_dstirq
;
481 static int __init
find_isa_irq_apic(int irq
, int type
)
485 for (i
= 0; i
< mp_irq_entries
; i
++) {
486 int lbus
= mp_irqs
[i
].mpc_srcbus
;
488 if (test_bit(lbus
, mp_bus_not_pci
) &&
489 (mp_irqs
[i
].mpc_irqtype
== type
) &&
490 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
493 if (i
< mp_irq_entries
) {
495 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
496 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
505 * Find a specific PCI IRQ entry.
506 * Not an __init, possibly needed by modules
508 static int pin_2_irq(int idx
, int apic
, int pin
);
510 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
512 int apic
, i
, best_guess
= -1;
514 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
516 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
517 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
520 for (i
= 0; i
< mp_irq_entries
; i
++) {
521 int lbus
= mp_irqs
[i
].mpc_srcbus
;
523 for (apic
= 0; apic
< nr_ioapics
; apic
++)
524 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
525 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
528 if (!test_bit(lbus
, mp_bus_not_pci
) &&
529 !mp_irqs
[i
].mpc_irqtype
&&
531 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
532 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
534 if (!(apic
|| IO_APIC_IRQ(irq
)))
537 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
540 * Use the first all-but-pin matching entry as a
541 * best-guess fuzzy result for broken mptables.
547 BUG_ON(best_guess
>= NR_IRQS
);
551 /* ISA interrupts are always polarity zero edge triggered,
552 * when listed as conforming in the MP table. */
554 #define default_ISA_trigger(idx) (0)
555 #define default_ISA_polarity(idx) (0)
557 /* PCI interrupts are always polarity one level triggered,
558 * when listed as conforming in the MP table. */
560 #define default_PCI_trigger(idx) (1)
561 #define default_PCI_polarity(idx) (1)
563 static int MPBIOS_polarity(int idx
)
565 int bus
= mp_irqs
[idx
].mpc_srcbus
;
569 * Determine IRQ line polarity (high active or low active):
571 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
573 case 0: /* conforms, ie. bus-type dependent polarity */
574 if (test_bit(bus
, mp_bus_not_pci
))
575 polarity
= default_ISA_polarity(idx
);
577 polarity
= default_PCI_polarity(idx
);
579 case 1: /* high active */
584 case 2: /* reserved */
586 printk(KERN_WARNING
"broken BIOS!!\n");
590 case 3: /* low active */
595 default: /* invalid */
597 printk(KERN_WARNING
"broken BIOS!!\n");
605 static int MPBIOS_trigger(int idx
)
607 int bus
= mp_irqs
[idx
].mpc_srcbus
;
611 * Determine IRQ trigger mode (edge or level sensitive):
613 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
615 case 0: /* conforms, ie. bus-type dependent */
616 if (test_bit(bus
, mp_bus_not_pci
))
617 trigger
= default_ISA_trigger(idx
);
619 trigger
= default_PCI_trigger(idx
);
626 case 2: /* reserved */
628 printk(KERN_WARNING
"broken BIOS!!\n");
637 default: /* invalid */
639 printk(KERN_WARNING
"broken BIOS!!\n");
647 static inline int irq_polarity(int idx
)
649 return MPBIOS_polarity(idx
);
652 static inline int irq_trigger(int idx
)
654 return MPBIOS_trigger(idx
);
657 static int pin_2_irq(int idx
, int apic
, int pin
)
660 int bus
= mp_irqs
[idx
].mpc_srcbus
;
663 * Debugging check, we are in big trouble if this message pops up!
665 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
666 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
668 if (test_bit(bus
, mp_bus_not_pci
)) {
669 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
672 * PCI IRQs are mapped in order
676 irq
+= nr_ioapic_registers
[i
++];
679 BUG_ON(irq
>= NR_IRQS
);
683 static int __assign_irq_vector(int irq
, cpumask_t mask
)
686 * NOTE! The local APIC isn't very good at handling
687 * multiple interrupts at the same interrupt level.
688 * As the interrupt level is determined by taking the
689 * vector number and shifting that right by 4, we
690 * want to spread these out a bit so that they don't
691 * all fall in the same interrupt level.
693 * Also, we've got to be careful not to trash gate
694 * 0x80, because int 0x80 is hm, kind of importantish. ;)
696 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
697 unsigned int old_vector
;
701 BUG_ON((unsigned)irq
>= NR_IRQS
);
704 /* Only try and allocate irqs on cpus that are present */
705 cpus_and(mask
, mask
, cpu_online_map
);
707 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
710 old_vector
= cfg
->vector
;
713 cpus_and(tmp
, cfg
->domain
, mask
);
714 if (!cpus_empty(tmp
))
718 for_each_cpu_mask(cpu
, mask
) {
719 cpumask_t domain
, new_mask
;
723 domain
= vector_allocation_domain(cpu
);
724 cpus_and(new_mask
, domain
, cpu_online_map
);
726 vector
= current_vector
;
727 offset
= current_offset
;
730 if (vector
>= FIRST_SYSTEM_VECTOR
) {
731 /* If we run out of vectors on large boxen, must share them. */
732 offset
= (offset
+ 1) % 8;
733 vector
= FIRST_DEVICE_VECTOR
+ offset
;
735 if (unlikely(current_vector
== vector
))
737 if (vector
== IA32_SYSCALL_VECTOR
)
739 for_each_cpu_mask(new_cpu
, new_mask
)
740 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
743 current_vector
= vector
;
744 current_offset
= offset
;
746 cfg
->move_in_progress
= 1;
747 cfg
->old_domain
= cfg
->domain
;
749 for_each_cpu_mask(new_cpu
, new_mask
)
750 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
751 cfg
->vector
= vector
;
752 cfg
->domain
= domain
;
758 static int assign_irq_vector(int irq
, cpumask_t mask
)
763 spin_lock_irqsave(&vector_lock
, flags
);
764 err
= __assign_irq_vector(irq
, mask
);
765 spin_unlock_irqrestore(&vector_lock
, flags
);
769 static void __clear_irq_vector(int irq
)
775 BUG_ON((unsigned)irq
>= NR_IRQS
);
777 BUG_ON(!cfg
->vector
);
779 vector
= cfg
->vector
;
780 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
781 for_each_cpu_mask(cpu
, mask
)
782 per_cpu(vector_irq
, cpu
)[vector
] = -1;
785 cfg
->domain
= CPU_MASK_NONE
;
788 void __setup_vector_irq(int cpu
)
790 /* Initialize vector_irq on a new cpu */
791 /* This function must be called with vector_lock held */
794 /* Mark the inuse vectors */
795 for (irq
= 0; irq
< NR_IRQS
; ++irq
) {
796 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
798 vector
= irq_cfg
[irq
].vector
;
799 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
801 /* Mark the free vectors */
802 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
803 irq
= per_cpu(vector_irq
, cpu
)[vector
];
806 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
807 per_cpu(vector_irq
, cpu
)[vector
] = -1;
812 static struct irq_chip ioapic_chip
;
814 static void ioapic_register_intr(int irq
, unsigned long trigger
)
817 irq_desc
[irq
].status
|= IRQ_LEVEL
;
818 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
819 handle_fasteoi_irq
, "fasteoi");
821 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
822 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
823 handle_edge_irq
, "edge");
827 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
828 int trigger
, int polarity
)
830 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
831 struct IO_APIC_route_entry entry
;
834 if (!IO_APIC_IRQ(irq
))
838 if (assign_irq_vector(irq
, mask
))
841 cpus_and(mask
, cfg
->domain
, mask
);
843 apic_printk(APIC_VERBOSE
,KERN_DEBUG
844 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
845 "IRQ %d Mode:%i Active:%i)\n",
846 apic
, mp_ioapics
[apic
].mpc_apicid
, pin
, cfg
->vector
,
847 irq
, trigger
, polarity
);
850 * add it to the IO-APIC irq-routing table:
852 memset(&entry
,0,sizeof(entry
));
854 entry
.delivery_mode
= INT_DELIVERY_MODE
;
855 entry
.dest_mode
= INT_DEST_MODE
;
856 entry
.dest
= cpu_mask_to_apicid(mask
);
857 entry
.mask
= 0; /* enable IRQ */
858 entry
.trigger
= trigger
;
859 entry
.polarity
= polarity
;
860 entry
.vector
= cfg
->vector
;
862 /* Mask level triggered irqs.
863 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
868 ioapic_register_intr(irq
, trigger
);
870 disable_8259A_irq(irq
);
872 ioapic_write_entry(apic
, pin
, entry
);
875 static void __init
setup_IO_APIC_irqs(void)
877 int apic
, pin
, idx
, irq
, first_notcon
= 1;
879 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
881 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
882 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
884 idx
= find_irq_entry(apic
,pin
,mp_INT
);
887 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
890 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
894 apic_printk(APIC_VERBOSE
, " not connected.\n");
898 irq
= pin_2_irq(idx
, apic
, pin
);
899 add_pin_to_irq(irq
, apic
, pin
);
901 setup_IO_APIC_irq(apic
, pin
, irq
,
902 irq_trigger(idx
), irq_polarity(idx
));
907 apic_printk(APIC_VERBOSE
, " not connected.\n");
911 * Set up the 8259A-master output pin as broadcast to all
914 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
916 struct IO_APIC_route_entry entry
;
919 memset(&entry
,0,sizeof(entry
));
921 disable_8259A_irq(0);
924 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
927 * We use logical delivery to get the timer IRQ
930 entry
.dest_mode
= INT_DEST_MODE
;
931 entry
.mask
= 0; /* unmask IRQ now */
932 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
933 entry
.delivery_mode
= INT_DELIVERY_MODE
;
936 entry
.vector
= vector
;
939 * The timer IRQ doesn't have to know that behind the
940 * scene we have a 8259A-master in AEOI mode ...
942 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
945 * Add it to the IO-APIC irq-routing table:
947 spin_lock_irqsave(&ioapic_lock
, flags
);
948 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
949 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
950 spin_unlock_irqrestore(&ioapic_lock
, flags
);
955 void __apicdebuginit
print_IO_APIC(void)
958 union IO_APIC_reg_00 reg_00
;
959 union IO_APIC_reg_01 reg_01
;
960 union IO_APIC_reg_02 reg_02
;
963 if (apic_verbosity
== APIC_QUIET
)
966 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
967 for (i
= 0; i
< nr_ioapics
; i
++)
968 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
969 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
972 * We are a bit conservative about what we expect. We have to
973 * know about every hardware change ASAP.
975 printk(KERN_INFO
"testing the IO APIC.......................\n");
977 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
979 spin_lock_irqsave(&ioapic_lock
, flags
);
980 reg_00
.raw
= io_apic_read(apic
, 0);
981 reg_01
.raw
= io_apic_read(apic
, 1);
982 if (reg_01
.bits
.version
>= 0x10)
983 reg_02
.raw
= io_apic_read(apic
, 2);
984 spin_unlock_irqrestore(&ioapic_lock
, flags
);
987 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
988 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
989 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
991 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
992 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
994 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
995 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
997 if (reg_01
.bits
.version
>= 0x10) {
998 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
999 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1002 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1004 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1005 " Stat Dmod Deli Vect: \n");
1007 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1008 struct IO_APIC_route_entry entry
;
1010 entry
= ioapic_read_entry(apic
, i
);
1012 printk(KERN_DEBUG
" %02x %03X ",
1017 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1022 entry
.delivery_status
,
1024 entry
.delivery_mode
,
1029 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1030 for (i
= 0; i
< NR_IRQS
; i
++) {
1031 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1034 printk(KERN_DEBUG
"IRQ%d ", i
);
1036 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1039 entry
= irq_2_pin
+ entry
->next
;
1044 printk(KERN_INFO
".................................... done.\n");
1051 static __apicdebuginit
void print_APIC_bitfield (int base
)
1056 if (apic_verbosity
== APIC_QUIET
)
1059 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1060 for (i
= 0; i
< 8; i
++) {
1061 v
= apic_read(base
+ i
*0x10);
1062 for (j
= 0; j
< 32; j
++) {
1072 void __apicdebuginit
print_local_APIC(void * dummy
)
1074 unsigned int v
, ver
, maxlvt
;
1076 if (apic_verbosity
== APIC_QUIET
)
1079 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1080 smp_processor_id(), hard_smp_processor_id());
1081 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(read_apic_id()));
1082 v
= apic_read(APIC_LVR
);
1083 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1084 ver
= GET_APIC_VERSION(v
);
1085 maxlvt
= lapic_get_maxlvt();
1087 v
= apic_read(APIC_TASKPRI
);
1088 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1090 v
= apic_read(APIC_ARBPRI
);
1091 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1092 v
& APIC_ARBPRI_MASK
);
1093 v
= apic_read(APIC_PROCPRI
);
1094 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1096 v
= apic_read(APIC_EOI
);
1097 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1098 v
= apic_read(APIC_RRR
);
1099 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1100 v
= apic_read(APIC_LDR
);
1101 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1102 v
= apic_read(APIC_DFR
);
1103 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1104 v
= apic_read(APIC_SPIV
);
1105 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1107 printk(KERN_DEBUG
"... APIC ISR field:\n");
1108 print_APIC_bitfield(APIC_ISR
);
1109 printk(KERN_DEBUG
"... APIC TMR field:\n");
1110 print_APIC_bitfield(APIC_TMR
);
1111 printk(KERN_DEBUG
"... APIC IRR field:\n");
1112 print_APIC_bitfield(APIC_IRR
);
1114 v
= apic_read(APIC_ESR
);
1115 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1117 v
= apic_read(APIC_ICR
);
1118 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1119 v
= apic_read(APIC_ICR2
);
1120 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1122 v
= apic_read(APIC_LVTT
);
1123 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1125 if (maxlvt
> 3) { /* PC is LVT#4. */
1126 v
= apic_read(APIC_LVTPC
);
1127 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1129 v
= apic_read(APIC_LVT0
);
1130 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1131 v
= apic_read(APIC_LVT1
);
1132 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1134 if (maxlvt
> 2) { /* ERR is LVT#3. */
1135 v
= apic_read(APIC_LVTERR
);
1136 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1139 v
= apic_read(APIC_TMICT
);
1140 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1141 v
= apic_read(APIC_TMCCT
);
1142 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1143 v
= apic_read(APIC_TDCR
);
1144 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1148 void print_all_local_APICs (void)
1150 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1153 void __apicdebuginit
print_PIC(void)
1156 unsigned long flags
;
1158 if (apic_verbosity
== APIC_QUIET
)
1161 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1163 spin_lock_irqsave(&i8259A_lock
, flags
);
1165 v
= inb(0xa1) << 8 | inb(0x21);
1166 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1168 v
= inb(0xa0) << 8 | inb(0x20);
1169 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1173 v
= inb(0xa0) << 8 | inb(0x20);
1177 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1179 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1181 v
= inb(0x4d1) << 8 | inb(0x4d0);
1182 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1187 void __init
enable_IO_APIC(void)
1189 union IO_APIC_reg_01 reg_01
;
1190 int i8259_apic
, i8259_pin
;
1192 unsigned long flags
;
1194 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1195 irq_2_pin
[i
].pin
= -1;
1196 irq_2_pin
[i
].next
= 0;
1200 * The number of IO-APIC IRQ registers (== #pins):
1202 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1203 spin_lock_irqsave(&ioapic_lock
, flags
);
1204 reg_01
.raw
= io_apic_read(apic
, 1);
1205 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1206 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1208 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1210 /* See if any of the pins is in ExtINT mode */
1211 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1212 struct IO_APIC_route_entry entry
;
1213 entry
= ioapic_read_entry(apic
, pin
);
1215 /* If the interrupt line is enabled and in ExtInt mode
1216 * I have found the pin where the i8259 is connected.
1218 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1219 ioapic_i8259
.apic
= apic
;
1220 ioapic_i8259
.pin
= pin
;
1226 /* Look to see what if the MP table has reported the ExtINT */
1227 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1228 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1229 /* Trust the MP table if nothing is setup in the hardware */
1230 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1231 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1232 ioapic_i8259
.pin
= i8259_pin
;
1233 ioapic_i8259
.apic
= i8259_apic
;
1235 /* Complain if the MP table and the hardware disagree */
1236 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1237 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1239 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1243 * Do not trust the IO-APIC being empty at bootup
1249 * Not an __init, needed by the reboot code
1251 void disable_IO_APIC(void)
1254 * Clear the IO-APIC before rebooting:
1259 * If the i8259 is routed through an IOAPIC
1260 * Put that IOAPIC in virtual wire mode
1261 * so legacy interrupts can be delivered.
1263 if (ioapic_i8259
.pin
!= -1) {
1264 struct IO_APIC_route_entry entry
;
1266 memset(&entry
, 0, sizeof(entry
));
1267 entry
.mask
= 0; /* Enabled */
1268 entry
.trigger
= 0; /* Edge */
1270 entry
.polarity
= 0; /* High */
1271 entry
.delivery_status
= 0;
1272 entry
.dest_mode
= 0; /* Physical */
1273 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1275 entry
.dest
= GET_APIC_ID(read_apic_id());
1278 * Add it to the IO-APIC irq-routing table:
1280 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1283 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1287 * There is a nasty bug in some older SMP boards, their mptable lies
1288 * about the timer IRQ. We do the following to work around the situation:
1290 * - timer IRQ defaults to IO-APIC IRQ
1291 * - if this function detects that timer IRQs are defunct, then we fall
1292 * back to ISA timer IRQs
1294 static int __init
timer_irq_works(void)
1296 unsigned long t1
= jiffies
;
1297 unsigned long flags
;
1299 local_save_flags(flags
);
1301 /* Let ten ticks pass... */
1302 mdelay((10 * 1000) / HZ
);
1303 local_irq_restore(flags
);
1306 * Expect a few ticks at least, to be sure some possible
1307 * glue logic does not lock up after one or two first
1308 * ticks in a non-ExtINT mode. Also the local APIC
1309 * might have cached one ExtINT interrupt. Finally, at
1310 * least one tick may be lost due to delays.
1314 if (time_after(jiffies
, t1
+ 4))
1320 * In the SMP+IOAPIC case it might happen that there are an unspecified
1321 * number of pending IRQ events unhandled. These cases are very rare,
1322 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1323 * better to do it this way as thus we do not have to be aware of
1324 * 'pending' interrupts in the IRQ path, except at this point.
1327 * Edge triggered needs to resend any interrupt
1328 * that was delayed but this is now handled in the device
1333 * Starting up a edge-triggered IO-APIC interrupt is
1334 * nasty - we need to make sure that we get the edge.
1335 * If it is already asserted for some reason, we need
1336 * return 1 to indicate that is was pending.
1338 * This is not complete - we should be able to fake
1339 * an edge even if it isn't on the 8259A...
1342 static unsigned int startup_ioapic_irq(unsigned int irq
)
1344 int was_pending
= 0;
1345 unsigned long flags
;
1347 spin_lock_irqsave(&ioapic_lock
, flags
);
1349 disable_8259A_irq(irq
);
1350 if (i8259A_irq_pending(irq
))
1353 __unmask_IO_APIC_irq(irq
);
1354 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1359 static int ioapic_retrigger_irq(unsigned int irq
)
1361 struct irq_cfg
*cfg
= &irq_cfg
[irq
];
1363 unsigned long flags
;
1365 spin_lock_irqsave(&vector_lock
, flags
);
1367 cpu_set(first_cpu(cfg
->domain
), mask
);
1369 send_IPI_mask(mask
, cfg
->vector
);
1370 spin_unlock_irqrestore(&vector_lock
, flags
);
1376 * Level and edge triggered IO-APIC interrupts need different handling,
1377 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1378 * handled with the level-triggered descriptor, but that one has slightly
1379 * more overhead. Level-triggered interrupts cannot be handled with the
1380 * edge-triggered handler, without risking IRQ storms and other ugly
1385 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1387 unsigned vector
, me
;
1392 me
= smp_processor_id();
1393 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1395 struct irq_desc
*desc
;
1396 struct irq_cfg
*cfg
;
1397 irq
= __get_cpu_var(vector_irq
)[vector
];
1401 desc
= irq_desc
+ irq
;
1402 cfg
= irq_cfg
+ irq
;
1403 spin_lock(&desc
->lock
);
1404 if (!cfg
->move_cleanup_count
)
1407 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1410 __get_cpu_var(vector_irq
)[vector
] = -1;
1411 cfg
->move_cleanup_count
--;
1413 spin_unlock(&desc
->lock
);
1419 static void irq_complete_move(unsigned int irq
)
1421 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1422 unsigned vector
, me
;
1424 if (likely(!cfg
->move_in_progress
))
1427 vector
= ~get_irq_regs()->orig_ax
;
1428 me
= smp_processor_id();
1429 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1430 cpumask_t cleanup_mask
;
1432 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1433 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1434 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1435 cfg
->move_in_progress
= 0;
1439 static inline void irq_complete_move(unsigned int irq
) {}
1442 static void ack_apic_edge(unsigned int irq
)
1444 irq_complete_move(irq
);
1445 move_native_irq(irq
);
1449 static void ack_apic_level(unsigned int irq
)
1451 int do_unmask_irq
= 0;
1453 irq_complete_move(irq
);
1454 #ifdef CONFIG_GENERIC_PENDING_IRQ
1455 /* If we are moving the irq we need to mask it */
1456 if (unlikely(irq_desc
[irq
].status
& IRQ_MOVE_PENDING
)) {
1458 mask_IO_APIC_irq(irq
);
1463 * We must acknowledge the irq before we move it or the acknowledge will
1464 * not propagate properly.
1468 /* Now we can move and renable the irq */
1469 if (unlikely(do_unmask_irq
)) {
1470 /* Only migrate the irq if the ack has been received.
1472 * On rare occasions the broadcast level triggered ack gets
1473 * delayed going to ioapics, and if we reprogram the
1474 * vector while Remote IRR is still set the irq will never
1477 * To prevent this scenario we read the Remote IRR bit
1478 * of the ioapic. This has two effects.
1479 * - On any sane system the read of the ioapic will
1480 * flush writes (and acks) going to the ioapic from
1482 * - We get to see if the ACK has actually been delivered.
1484 * Based on failed experiments of reprogramming the
1485 * ioapic entry from outside of irq context starting
1486 * with masking the ioapic entry and then polling until
1487 * Remote IRR was clear before reprogramming the
1488 * ioapic I don't trust the Remote IRR bit to be
1489 * completey accurate.
1491 * However there appears to be no other way to plug
1492 * this race, so if the Remote IRR bit is not
1493 * accurate and is causing problems then it is a hardware bug
1494 * and you can go talk to the chipset vendor about it.
1496 if (!io_apic_level_ack_pending(irq
))
1497 move_masked_irq(irq
);
1498 unmask_IO_APIC_irq(irq
);
1502 static struct irq_chip ioapic_chip __read_mostly
= {
1504 .startup
= startup_ioapic_irq
,
1505 .mask
= mask_IO_APIC_irq
,
1506 .unmask
= unmask_IO_APIC_irq
,
1507 .ack
= ack_apic_edge
,
1508 .eoi
= ack_apic_level
,
1510 .set_affinity
= set_ioapic_affinity_irq
,
1512 .retrigger
= ioapic_retrigger_irq
,
1515 static inline void init_IO_APIC_traps(void)
1520 * NOTE! The local APIC isn't very good at handling
1521 * multiple interrupts at the same interrupt level.
1522 * As the interrupt level is determined by taking the
1523 * vector number and shifting that right by 4, we
1524 * want to spread these out a bit so that they don't
1525 * all fall in the same interrupt level.
1527 * Also, we've got to be careful not to trash gate
1528 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1530 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1532 if (IO_APIC_IRQ(tmp
) && !irq_cfg
[tmp
].vector
) {
1534 * Hmm.. We don't have an entry for this,
1535 * so default to an old-fashioned 8259
1536 * interrupt if we can..
1539 make_8259A_irq(irq
);
1541 /* Strange. Oh, well.. */
1542 irq_desc
[irq
].chip
= &no_irq_chip
;
1547 static void enable_lapic_irq (unsigned int irq
)
1551 v
= apic_read(APIC_LVT0
);
1552 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1555 static void disable_lapic_irq (unsigned int irq
)
1559 v
= apic_read(APIC_LVT0
);
1560 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1563 static void ack_lapic_irq (unsigned int irq
)
1568 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
1570 static struct hw_interrupt_type lapic_irq_type __read_mostly
= {
1571 .name
= "local-APIC",
1572 .typename
= "local-APIC-edge",
1573 .startup
= NULL
, /* startup_irq() not used for IRQ0 */
1574 .shutdown
= NULL
, /* shutdown_irq() not used for IRQ0 */
1575 .enable
= enable_lapic_irq
,
1576 .disable
= disable_lapic_irq
,
1577 .ack
= ack_lapic_irq
,
1578 .end
= end_lapic_irq
,
1581 static void __init
setup_nmi(void)
1584 * Dirty trick to enable the NMI watchdog ...
1585 * We put the 8259A master into AEOI mode and
1586 * unmask on all local APICs LVT0 as NMI.
1588 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1589 * is from Maciej W. Rozycki - so we do not have to EOI from
1590 * the NMI handler or the timer interrupt.
1592 printk(KERN_INFO
"activating NMI Watchdog ...");
1594 enable_NMI_through_LVT0();
1600 * This looks a bit hackish but it's about the only one way of sending
1601 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1602 * not support the ExtINT mode, unfortunately. We need to send these
1603 * cycles as some i82489DX-based boards have glue logic that keeps the
1604 * 8259A interrupt line asserted until INTA. --macro
1606 static inline void unlock_ExtINT_logic(void)
1609 struct IO_APIC_route_entry entry0
, entry1
;
1610 unsigned char save_control
, save_freq_select
;
1611 unsigned long flags
;
1613 pin
= find_isa_irq_pin(8, mp_INT
);
1614 apic
= find_isa_irq_apic(8, mp_INT
);
1618 spin_lock_irqsave(&ioapic_lock
, flags
);
1619 *(((int *)&entry0
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
1620 *(((int *)&entry0
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
1621 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1622 clear_IO_APIC_pin(apic
, pin
);
1624 memset(&entry1
, 0, sizeof(entry1
));
1626 entry1
.dest_mode
= 0; /* physical delivery */
1627 entry1
.mask
= 0; /* unmask IRQ now */
1628 entry1
.dest
= hard_smp_processor_id();
1629 entry1
.delivery_mode
= dest_ExtINT
;
1630 entry1
.polarity
= entry0
.polarity
;
1634 spin_lock_irqsave(&ioapic_lock
, flags
);
1635 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
1636 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
1637 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1639 save_control
= CMOS_READ(RTC_CONTROL
);
1640 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1641 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1643 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1648 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1652 CMOS_WRITE(save_control
, RTC_CONTROL
);
1653 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1654 clear_IO_APIC_pin(apic
, pin
);
1656 spin_lock_irqsave(&ioapic_lock
, flags
);
1657 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
1658 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
1659 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1663 * This code may look a bit paranoid, but it's supposed to cooperate with
1664 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1665 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1666 * fanatically on his truly buggy board.
1668 * FIXME: really need to revamp this for modern platforms only.
1670 static inline void __init
check_timer(void)
1672 struct irq_cfg
*cfg
= irq_cfg
+ 0;
1673 int apic1
, pin1
, apic2
, pin2
;
1674 unsigned long flags
;
1676 local_irq_save(flags
);
1679 * get/set the timer IRQ vector:
1681 disable_8259A_irq(0);
1682 assign_irq_vector(0, TARGET_CPUS
);
1685 * Subtle, code in do_timer_interrupt() expects an AEOI
1686 * mode for the 8259A whenever interrupts are routed
1687 * through I/O APICs. Also IRQ0 has to be enabled in
1688 * the 8259A which implies the virtual wire has to be
1689 * disabled in the local APIC.
1691 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1693 if (timer_over_8254
> 0)
1694 enable_8259A_irq(0);
1696 pin1
= find_isa_irq_pin(0, mp_INT
);
1697 apic1
= find_isa_irq_apic(0, mp_INT
);
1698 pin2
= ioapic_i8259
.pin
;
1699 apic2
= ioapic_i8259
.apic
;
1701 apic_printk(APIC_VERBOSE
,KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1702 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
1706 * Ok, does IRQ0 through the IOAPIC work?
1708 unmask_IO_APIC_irq(0);
1709 if (!no_timer_check
&& timer_irq_works()) {
1710 nmi_watchdog_default();
1711 if (nmi_watchdog
== NMI_IO_APIC
) {
1712 disable_8259A_irq(0);
1714 enable_8259A_irq(0);
1716 if (disable_timer_pin_1
> 0)
1717 clear_IO_APIC_pin(0, pin1
);
1720 clear_IO_APIC_pin(apic1
, pin1
);
1721 apic_printk(APIC_QUIET
,KERN_ERR
"..MP-BIOS bug: 8254 timer not "
1722 "connected to IO-APIC\n");
1725 apic_printk(APIC_VERBOSE
,KERN_INFO
"...trying to set up timer (IRQ0) "
1726 "through the 8259A ... ");
1728 apic_printk(APIC_VERBOSE
,"\n..... (found apic %d pin %d) ...",
1731 * legacy devices should be connected to IO APIC #0
1733 setup_ExtINT_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
1734 if (timer_irq_works()) {
1735 apic_printk(APIC_VERBOSE
," works.\n");
1736 nmi_watchdog_default();
1737 if (nmi_watchdog
== NMI_IO_APIC
) {
1743 * Cleanup, just in case ...
1745 clear_IO_APIC_pin(apic2
, pin2
);
1747 apic_printk(APIC_VERBOSE
," failed.\n");
1749 if (nmi_watchdog
== NMI_IO_APIC
) {
1750 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1754 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
1756 disable_8259A_irq(0);
1757 irq_desc
[0].chip
= &lapic_irq_type
;
1758 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
1759 enable_8259A_irq(0);
1761 if (timer_irq_works()) {
1762 apic_printk(APIC_VERBOSE
," works.\n");
1765 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
1766 apic_printk(APIC_VERBOSE
," failed.\n");
1768 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
1772 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1774 unlock_ExtINT_logic();
1776 if (timer_irq_works()) {
1777 apic_printk(APIC_VERBOSE
," works.\n");
1780 apic_printk(APIC_VERBOSE
," failed :(.\n");
1781 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1783 local_irq_restore(flags
);
1786 static int __init
notimercheck(char *s
)
1791 __setup("no_timer_check", notimercheck
);
1795 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1796 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1797 * Linux doesn't really care, as it's not actually used
1798 * for any interrupt handling anyway.
1800 #define PIC_IRQS (1<<2)
1802 void __init
setup_IO_APIC(void)
1806 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1810 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
1812 io_apic_irqs
= ~PIC_IRQS
;
1814 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
1817 setup_IO_APIC_irqs();
1818 init_IO_APIC_traps();
1824 struct sysfs_ioapic_data
{
1825 struct sys_device dev
;
1826 struct IO_APIC_route_entry entry
[0];
1828 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
1830 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1832 struct IO_APIC_route_entry
*entry
;
1833 struct sysfs_ioapic_data
*data
;
1836 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
1837 entry
= data
->entry
;
1838 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
1839 *entry
= ioapic_read_entry(dev
->id
, i
);
1844 static int ioapic_resume(struct sys_device
*dev
)
1846 struct IO_APIC_route_entry
*entry
;
1847 struct sysfs_ioapic_data
*data
;
1848 unsigned long flags
;
1849 union IO_APIC_reg_00 reg_00
;
1852 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
1853 entry
= data
->entry
;
1855 spin_lock_irqsave(&ioapic_lock
, flags
);
1856 reg_00
.raw
= io_apic_read(dev
->id
, 0);
1857 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
1858 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
1859 io_apic_write(dev
->id
, 0, reg_00
.raw
);
1861 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1862 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
1863 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
1868 static struct sysdev_class ioapic_sysdev_class
= {
1870 .suspend
= ioapic_suspend
,
1871 .resume
= ioapic_resume
,
1874 static int __init
ioapic_init_sysfs(void)
1876 struct sys_device
* dev
;
1879 error
= sysdev_class_register(&ioapic_sysdev_class
);
1883 for (i
= 0; i
< nr_ioapics
; i
++ ) {
1884 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
1885 * sizeof(struct IO_APIC_route_entry
);
1886 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
1887 if (!mp_ioapic_data
[i
]) {
1888 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
1891 dev
= &mp_ioapic_data
[i
]->dev
;
1893 dev
->cls
= &ioapic_sysdev_class
;
1894 error
= sysdev_register(dev
);
1896 kfree(mp_ioapic_data
[i
]);
1897 mp_ioapic_data
[i
] = NULL
;
1898 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
1906 device_initcall(ioapic_init_sysfs
);
1909 * Dynamic irq allocate and deallocation
1911 int create_irq(void)
1913 /* Allocate an unused irq */
1916 unsigned long flags
;
1919 spin_lock_irqsave(&vector_lock
, flags
);
1920 for (new = (NR_IRQS
- 1); new >= 0; new--) {
1921 if (platform_legacy_irq(new))
1923 if (irq_cfg
[new].vector
!= 0)
1925 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
1929 spin_unlock_irqrestore(&vector_lock
, flags
);
1932 dynamic_irq_init(irq
);
1937 void destroy_irq(unsigned int irq
)
1939 unsigned long flags
;
1941 dynamic_irq_cleanup(irq
);
1943 spin_lock_irqsave(&vector_lock
, flags
);
1944 __clear_irq_vector(irq
);
1945 spin_unlock_irqrestore(&vector_lock
, flags
);
1949 * MSI message composition
1951 #ifdef CONFIG_PCI_MSI
1952 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
1954 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1960 err
= assign_irq_vector(irq
, tmp
);
1962 cpus_and(tmp
, cfg
->domain
, tmp
);
1963 dest
= cpu_mask_to_apicid(tmp
);
1965 msg
->address_hi
= MSI_ADDR_BASE_HI
;
1968 ((INT_DEST_MODE
== 0) ?
1969 MSI_ADDR_DEST_MODE_PHYSICAL
:
1970 MSI_ADDR_DEST_MODE_LOGICAL
) |
1971 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
1972 MSI_ADDR_REDIRECTION_CPU
:
1973 MSI_ADDR_REDIRECTION_LOWPRI
) |
1974 MSI_ADDR_DEST_ID(dest
);
1977 MSI_DATA_TRIGGER_EDGE
|
1978 MSI_DATA_LEVEL_ASSERT
|
1979 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
1980 MSI_DATA_DELIVERY_FIXED
:
1981 MSI_DATA_DELIVERY_LOWPRI
) |
1982 MSI_DATA_VECTOR(cfg
->vector
);
1988 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
1990 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1995 cpus_and(tmp
, mask
, cpu_online_map
);
1996 if (cpus_empty(tmp
))
1999 if (assign_irq_vector(irq
, mask
))
2002 cpus_and(tmp
, cfg
->domain
, mask
);
2003 dest
= cpu_mask_to_apicid(tmp
);
2005 read_msi_msg(irq
, &msg
);
2007 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2008 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2009 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2010 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2012 write_msi_msg(irq
, &msg
);
2013 irq_desc
[irq
].affinity
= mask
;
2015 #endif /* CONFIG_SMP */
2018 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2019 * which implement the MSI or MSI-X Capability Structure.
2021 static struct irq_chip msi_chip
= {
2023 .unmask
= unmask_msi_irq
,
2024 .mask
= mask_msi_irq
,
2025 .ack
= ack_apic_edge
,
2027 .set_affinity
= set_msi_irq_affinity
,
2029 .retrigger
= ioapic_retrigger_irq
,
2032 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2040 ret
= msi_compose_msg(dev
, irq
, &msg
);
2046 set_irq_msi(irq
, desc
);
2047 write_msi_msg(irq
, &msg
);
2049 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2054 void arch_teardown_msi_irq(unsigned int irq
)
2061 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
2063 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2068 cpus_and(tmp
, mask
, cpu_online_map
);
2069 if (cpus_empty(tmp
))
2072 if (assign_irq_vector(irq
, mask
))
2075 cpus_and(tmp
, cfg
->domain
, mask
);
2076 dest
= cpu_mask_to_apicid(tmp
);
2078 dmar_msi_read(irq
, &msg
);
2080 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2081 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2082 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2083 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2085 dmar_msi_write(irq
, &msg
);
2086 irq_desc
[irq
].affinity
= mask
;
2088 #endif /* CONFIG_SMP */
2090 struct irq_chip dmar_msi_type
= {
2092 .unmask
= dmar_msi_unmask
,
2093 .mask
= dmar_msi_mask
,
2094 .ack
= ack_apic_edge
,
2096 .set_affinity
= dmar_msi_set_affinity
,
2098 .retrigger
= ioapic_retrigger_irq
,
2101 int arch_setup_dmar_msi(unsigned int irq
)
2106 ret
= msi_compose_msg(NULL
, irq
, &msg
);
2109 dmar_msi_write(irq
, &msg
);
2110 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
2116 #endif /* CONFIG_PCI_MSI */
2118 * Hypertransport interrupt support
2120 #ifdef CONFIG_HT_IRQ
2124 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
2126 struct ht_irq_msg msg
;
2127 fetch_ht_irq_msg(irq
, &msg
);
2129 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
2130 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2132 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
2133 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2135 write_ht_irq_msg(irq
, &msg
);
2138 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2140 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2144 cpus_and(tmp
, mask
, cpu_online_map
);
2145 if (cpus_empty(tmp
))
2148 if (assign_irq_vector(irq
, mask
))
2151 cpus_and(tmp
, cfg
->domain
, mask
);
2152 dest
= cpu_mask_to_apicid(tmp
);
2154 target_ht_irq(irq
, dest
, cfg
->vector
);
2155 irq_desc
[irq
].affinity
= mask
;
2159 static struct irq_chip ht_irq_chip
= {
2161 .mask
= mask_ht_irq
,
2162 .unmask
= unmask_ht_irq
,
2163 .ack
= ack_apic_edge
,
2165 .set_affinity
= set_ht_irq_affinity
,
2167 .retrigger
= ioapic_retrigger_irq
,
2170 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2172 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2177 err
= assign_irq_vector(irq
, tmp
);
2179 struct ht_irq_msg msg
;
2182 cpus_and(tmp
, cfg
->domain
, tmp
);
2183 dest
= cpu_mask_to_apicid(tmp
);
2185 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2189 HT_IRQ_LOW_DEST_ID(dest
) |
2190 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
2191 ((INT_DEST_MODE
== 0) ?
2192 HT_IRQ_LOW_DM_PHYSICAL
:
2193 HT_IRQ_LOW_DM_LOGICAL
) |
2194 HT_IRQ_LOW_RQEOI_EDGE
|
2195 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2196 HT_IRQ_LOW_MT_FIXED
:
2197 HT_IRQ_LOW_MT_ARBITRATED
) |
2198 HT_IRQ_LOW_IRQ_MASKED
;
2200 write_ht_irq_msg(irq
, &msg
);
2202 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2203 handle_edge_irq
, "edge");
2207 #endif /* CONFIG_HT_IRQ */
2209 /* --------------------------------------------------------------------------
2210 ACPI-based IOAPIC Configuration
2211 -------------------------------------------------------------------------- */
2215 #define IO_APIC_MAX_ID 0xFE
2217 int __init
io_apic_get_redir_entries (int ioapic
)
2219 union IO_APIC_reg_01 reg_01
;
2220 unsigned long flags
;
2222 spin_lock_irqsave(&ioapic_lock
, flags
);
2223 reg_01
.raw
= io_apic_read(ioapic
, 1);
2224 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2226 return reg_01
.bits
.entries
;
2230 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2232 if (!IO_APIC_IRQ(irq
)) {
2233 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2239 * IRQs < 16 are already in the irq_2_pin[] map
2242 add_pin_to_irq(irq
, ioapic
, pin
);
2244 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
2250 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2254 if (skip_ioapic_setup
)
2257 for (i
= 0; i
< mp_irq_entries
; i
++)
2258 if (mp_irqs
[i
].mpc_irqtype
== mp_INT
&&
2259 mp_irqs
[i
].mpc_srcbusirq
== bus_irq
)
2261 if (i
>= mp_irq_entries
)
2264 *trigger
= irq_trigger(i
);
2265 *polarity
= irq_polarity(i
);
2269 #endif /* CONFIG_ACPI */
2272 * This function currently is only a helper for the i386 smp boot process where
2273 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2274 * so mask in all cases should simply be TARGET_CPUS
2277 void __init
setup_ioapic_dest(void)
2279 int pin
, ioapic
, irq
, irq_entry
;
2281 if (skip_ioapic_setup
== 1)
2284 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2285 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2286 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2287 if (irq_entry
== -1)
2289 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2291 /* setup_IO_APIC_irqs could fail to get vector for some device
2292 * when you have too many devices, because at that time only boot
2295 if (!irq_cfg
[irq
].vector
)
2296 setup_IO_APIC_irq(ioapic
, pin
, irq
,
2297 irq_trigger(irq_entry
),
2298 irq_polarity(irq_entry
));
2300 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
2307 #define IOAPIC_RESOURCE_NAME_SIZE 11
2309 static struct resource
*ioapic_resources
;
2311 static struct resource
* __init
ioapic_setup_resources(void)
2314 struct resource
*res
;
2318 if (nr_ioapics
<= 0)
2321 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
2324 mem
= alloc_bootmem(n
);
2329 mem
+= sizeof(struct resource
) * nr_ioapics
;
2331 for (i
= 0; i
< nr_ioapics
; i
++) {
2333 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
2334 sprintf(mem
, "IOAPIC %u", i
);
2335 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
2339 ioapic_resources
= res
;
2344 void __init
ioapic_init_mappings(void)
2346 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2347 struct resource
*ioapic_res
;
2350 ioapic_res
= ioapic_setup_resources();
2351 for (i
= 0; i
< nr_ioapics
; i
++) {
2352 if (smp_found_config
) {
2353 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
2355 ioapic_phys
= (unsigned long)
2356 alloc_bootmem_pages(PAGE_SIZE
);
2357 ioapic_phys
= __pa(ioapic_phys
);
2359 set_fixmap_nocache(idx
, ioapic_phys
);
2360 apic_printk(APIC_VERBOSE
,
2361 "mapped IOAPIC to %016lx (%016lx)\n",
2362 __fix_to_virt(idx
), ioapic_phys
);
2365 if (ioapic_res
!= NULL
) {
2366 ioapic_res
->start
= ioapic_phys
;
2367 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
2373 static int __init
ioapic_insert_resources(void)
2376 struct resource
*r
= ioapic_resources
;
2380 "IO APIC resources could be not be allocated.\n");
2384 for (i
= 0; i
< nr_ioapics
; i
++) {
2385 insert_resource(&iomem_resource
, r
);
2392 /* Insert the IO APIC resources after PCI initialization has occured to handle
2393 * IO APICS that are mapped in on a BAR in PCI space. */
2394 late_initcall(ioapic_insert_resources
);