arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c

   1 /*
   2  * (C) 2004  Sebastian Witt <se.witt@gmx.net>
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *  Based upon reverse engineered information
   6  *
   7  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/cpufreq.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17
  18 #define NFORCE2_XTAL 25
  19 #define NFORCE2_BOOTFSB 0x48
  20 #define NFORCE2_PLLENABLE 0xa8
  21 #define NFORCE2_PLLREG 0xa4
  22 #define NFORCE2_PLLADR 0xa0
  23 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)
  24
  25 #define NFORCE2_MIN_FSB 50
  26 #define NFORCE2_SAFE_DISTANCE 50
  27
  28 /* Delay in ms between FSB changes */
  29 //#define NFORCE2_DELAY 10
  30
  31 /* nforce2_chipset:
  32  * FSB is changed using the chipset
  33  */
  34 static struct pci_dev *nforce2_chipset_dev;
  35
  36 /* fid:
  37  * multiplier * 10
  38  */
  39 static int fid = 0;
  40
  41 /* min_fsb, max_fsb:
  42  * minimum and maximum FSB (= FSB at boot time)
  43  */
  44 static int min_fsb = 0;
  45 static int max_fsb = 0;
  46
  47 MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
  48 MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
  49 MODULE_LICENSE("GPL");
  50
  51 module_param(fid, int, 0444);
  52 module_param(min_fsb, int, 0444);
  53
  54 MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
  55 MODULE_PARM_DESC(min_fsb,
  56                  "Minimum FSB to use, if not defined: current FSB - 50");
  57
  58 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
  59
  60 /**
  61  * nforce2_calc_fsb - calculate FSB
  62  * @pll: PLL value
  63  *
  64  *   Calculates FSB from PLL value
  65  */
  66 static int nforce2_calc_fsb(int pll)
  67 {
  68         unsigned char mul, div;
  69
  70         mul = (pll >> 8) & 0xff;
  71         div = pll & 0xff;
  72
  73         if (div > 0)
  74                 return NFORCE2_XTAL * mul / div;
  75
  76         return 0;
  77 }
  78
  79 /**
  80  * nforce2_calc_pll - calculate PLL value
  81  * @fsb: FSB
  82  *
  83  *   Calculate PLL value for given FSB
  84  */
  85 static int nforce2_calc_pll(unsigned int fsb)
  86 {
  87         unsigned char xmul, xdiv;
  88         unsigned char mul = 0, div = 0;
  89         int tried = 0;
  90
  91         /* Try to calculate multiplier and divider up to 4 times */
  92         while (((mul == 0) || (div == 0)) && (tried <= 3)) {
  93                 for (xdiv = 1; xdiv <= 0x80; xdiv++)
  94                         for (xmul = 1; xmul <= 0xfe; xmul++)
  95                                 if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
  96                                     fsb + tried) {
  97                                         mul = xmul;
  98                                         div = xdiv;
  99                                 }
 100                 tried++;
 101         }
 102
 103         if ((mul == 0) || (div == 0))
 104                 return -1;
 105
 106         return NFORCE2_PLL(mul, div);
 107 }
 108
 109 /**
 110  * nforce2_write_pll - write PLL value to chipset
 111  * @pll: PLL value
 112  *
 113  *   Writes new FSB PLL value to chipset
 114  */
 115 static void nforce2_write_pll(int pll)
 116 {
 117         int temp;
 118
 119         /* Set the pll addr. to 0x00 */
 120         temp = 0x00;
 121         pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
 122
 123         /* Now write the value in all 64 registers */
 124         for (temp = 0; temp <= 0x3f; temp++)
 125                 pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, pll);
 126
 127         return;
 128 }
 129
 130 /**
 131  * nforce2_fsb_read - Read FSB
 132  *
 133  *   Read FSB from chipset
 134  *   If bootfsb != 0, return FSB at boot-time
 135  */
 136 static unsigned int nforce2_fsb_read(int bootfsb)
 137 {
 138         struct pci_dev *nforce2_sub5;
 139         u32 fsb, temp = 0;
 140
 141         /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
 142         nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
 143                                                 0x01EF,PCI_ANY_ID,PCI_ANY_ID,NULL);
 144         if (!nforce2_sub5)
 145                 return 0;
 146
 147         pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
 148         fsb /= 1000000;
 149
 150         /* Check if PLL register is already set */
 151         pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
 152
 153         if(bootfsb || !temp)
 154                 return fsb;
 155
 156         /* Use PLL register FSB value */
 157         pci_read_config_dword(nforce2_chipset_dev,NFORCE2_PLLREG, &temp);
 158         fsb = nforce2_calc_fsb(temp);
 159
 160         return fsb;
 161 }
 162
 163 /**
 164  * nforce2_set_fsb - set new FSB
 165  * @fsb: New FSB
 166  *
 167  *   Sets new FSB
 168  */
 169 static int nforce2_set_fsb(unsigned int fsb)
 170 {
 171         u32 temp = 0;
 172         unsigned int tfsb;
 173         int diff;
 174         int pll = 0;
 175
 176         if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
 177                 printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
 178                 return -EINVAL;
 179         }
 180
 181         tfsb = nforce2_fsb_read(0);
 182         if (!tfsb) {
 183                 printk(KERN_ERR "cpufreq: Error while reading the FSB\n");
 184                 return -EINVAL;
 185         }
 186
 187         /* First write? Then set actual value */
 188         pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
 189         if (!temp) {
 190                 pll = nforce2_calc_pll(tfsb);
 191
 192                 if (pll < 0)
 193                         return -EINVAL;
 194
 195                 nforce2_write_pll(pll);
 196         }
 197
 198         /* Enable write access */
 199         temp = 0x01;
 200         pci_write_config_byte(nforce2_chipset_dev, NFORCE2_PLLENABLE, (u8)temp);
 201
 202         diff = tfsb - fsb;
 203
 204         if (!diff)
 205                 return 0;
 206
 207         while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
 208                 if (diff < 0)
 209                         tfsb++;
 210                 else
 211                         tfsb--;
 212
 213                 /* Calculate the PLL reg. value */
 214                 if ((pll = nforce2_calc_pll(tfsb)) == -1)
 215                         return -EINVAL;
 216
 217                 nforce2_write_pll(pll);
 218 #ifdef NFORCE2_DELAY
 219                 mdelay(NFORCE2_DELAY);
 220 #endif
 221         }
 222
 223         temp = 0x40;
 224         pci_write_config_byte(nforce2_chipset_dev, NFORCE2_PLLADR, (u8)temp);
 225
 226         return 0;
 227 }
 228
 229 /**
 230  * nforce2_get - get the CPU frequency
 231  * @cpu: CPU number
 232  *
 233  * Returns the CPU frequency
 234  */
 235 static unsigned int nforce2_get(unsigned int cpu)
 236 {
 237         if (cpu)
 238                 return 0;
 239         return nforce2_fsb_read(0) * fid * 100;
 240 }
 241
 242 /**
 243  * nforce2_target - set a new CPUFreq policy
 244  * @policy: new policy
 245  * @target_freq: the target frequency
 246  * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 247  *
 248  * Sets a new CPUFreq policy.
 249  */
 250 static int nforce2_target(struct cpufreq_policy *policy,
 251                           unsigned int target_freq, unsigned int relation)
 252 {
 253 //        unsigned long         flags;
 254         struct cpufreq_freqs freqs;
 255         unsigned int target_fsb;
 256
 257         if ((target_freq > policy->max) || (target_freq < policy->min))
 258                 return -EINVAL;
 259
 260         target_fsb = target_freq / (fid * 100);
 261
 262         freqs.old = nforce2_get(policy->cpu);
 263         freqs.new = target_fsb * fid * 100;
 264         freqs.cpu = 0;          /* Only one CPU on nForce2 plattforms */
 265
 266         if (freqs.old == freqs.new)
 267                 return 0;
 268
 269         dprintk(KERN_INFO "cpufreq: Old CPU frequency %d kHz, new %d kHz\n",
 270                freqs.old, freqs.new);
 271
 272         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 273
 274         /* Disable IRQs */
 275         //local_irq_save(flags);
 276
 277         if (nforce2_set_fsb(target_fsb) < 0)
 278                 printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n",
 279                        target_fsb);
 280         else
 281                 dprintk(KERN_INFO "cpufreq: Changed FSB successfully to %d\n",
 282                        target_fsb);
 283
 284         /* Enable IRQs */
 285         //local_irq_restore(flags);
 286
 287         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 288
 289         return 0;
 290 }
 291
 292 /**
 293  * nforce2_verify - verifies a new CPUFreq policy
 294  * @policy: new policy
 295  */
 296 static int nforce2_verify(struct cpufreq_policy *policy)
 297 {
 298         unsigned int fsb_pol_max;
 299
 300         fsb_pol_max = policy->max / (fid * 100);
 301
 302         if (policy->min < (fsb_pol_max * fid * 100))
 303                 policy->max = (fsb_pol_max + 1) * fid * 100;
 304
 305         cpufreq_verify_within_limits(policy,
 306                                      policy->cpuinfo.min_freq,
 307                                      policy->cpuinfo.max_freq);
 308         return 0;
 309 }
 310
 311 static int nforce2_cpu_init(struct cpufreq_policy *policy)
 312 {
 313         unsigned int fsb;
 314         unsigned int rfid;
 315
 316         /* capability check */
 317         if (policy->cpu != 0)
 318                 return -ENODEV;
 319
 320         /* Get current FSB */
 321         fsb = nforce2_fsb_read(0);
 322
 323         if (!fsb)
 324                 return -EIO;
 325
 326         /* FIX: Get FID from CPU */
 327         if (!fid) {
 328                 if (!cpu_khz) {
 329                         printk(KERN_WARNING
 330                                "cpufreq: cpu_khz not set, can't calculate multiplier!\n");
 331                         return -ENODEV;
 332                 }
 333
 334                 fid = cpu_khz / (fsb * 100);
 335                 rfid = fid % 5;
 336
 337                 if (rfid) {
 338                         if (rfid > 2)
 339                                 fid += 5 - rfid;
 340                         else
 341                                 fid -= rfid;
 342                 }
 343         }
 344
 345         printk(KERN_INFO "cpufreq: FSB currently at %i MHz, FID %d.%d\n", fsb,
 346                fid / 10, fid % 10);
 347
 348         /* Set maximum FSB to FSB at boot time */
 349         max_fsb = nforce2_fsb_read(1);
 350
 351         if(!max_fsb)
 352                 return -EIO;
 353
 354         if (!min_fsb)
 355                 min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;
 356
 357         if (min_fsb < NFORCE2_MIN_FSB)
 358                 min_fsb = NFORCE2_MIN_FSB;
 359
 360         /* cpuinfo and default policy values */
 361         policy->cpuinfo.min_freq = min_fsb * fid * 100;
 362         policy->cpuinfo.max_freq = max_fsb * fid * 100;
 363         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
 364         policy->cur = nforce2_get(policy->cpu);
 365         policy->min = policy->cpuinfo.min_freq;
 366         policy->max = policy->cpuinfo.max_freq;
 367         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 368
 369         return 0;
 370 }
 371
 372 static int nforce2_cpu_exit(struct cpufreq_policy *policy)
 373 {
 374         return 0;
 375 }
 376
 377 static struct cpufreq_driver nforce2_driver = {
 378         .name = "nforce2",
 379         .verify = nforce2_verify,
 380         .target = nforce2_target,
 381         .get = nforce2_get,
 382         .init = nforce2_cpu_init,
 383         .exit = nforce2_cpu_exit,
 384         .owner = THIS_MODULE,
 385 };
 386
 387 /**
 388  * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
 389  *
 390  * Detects nForce2 A2 and C1 stepping
 391  *
 392  */
 393 static unsigned int nforce2_detect_chipset(void)
 394 {
 395         u8 revision;
 396
 397         nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
 398                                         PCI_DEVICE_ID_NVIDIA_NFORCE2,
 399                                         PCI_ANY_ID, PCI_ANY_ID, NULL);
 400
 401         if (nforce2_chipset_dev == NULL)
 402                 return -ENODEV;
 403
 404         pci_read_config_byte(nforce2_chipset_dev, PCI_REVISION_ID, &revision);
 405
 406         printk(KERN_INFO "cpufreq: Detected nForce2 chipset revision %X\n",
 407                revision);
 408         printk(KERN_INFO
 409                "cpufreq: FSB changing is maybe unstable and can lead to crashes and data loss.\n");
 410
 411         return 0;
 412 }
 413
 414 /**
 415  * nforce2_init - initializes the nForce2 CPUFreq driver
 416  *
 417  * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
 418  * devices, -EINVAL on problems during initiatization, and zero on
 419  * success.
 420  */
 421 static int __init nforce2_init(void)
 422 {
 423         /* TODO: do we need to detect the processor? */
 424
 425         /* detect chipset */
 426         if (nforce2_detect_chipset()) {
 427                 printk(KERN_ERR "cpufreq: No nForce2 chipset.\n");
 428                 return -ENODEV;
 429         }
 430
 431         return cpufreq_register_driver(&nforce2_driver);
 432 }
 433
 434 /**
 435  * nforce2_exit - unregisters cpufreq module
 436  *
 437  *   Unregisters nForce2 FSB change support.
 438  */
 439 static void __exit nforce2_exit(void)
 440 {
 441         cpufreq_unregister_driver(&nforce2_driver);
 442 }
 443
 444 module_init(nforce2_init);
 445 module_exit(nforce2_exit);
 446