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ixgbe: disable flow control by default
[linux-2.6/mini2440.git] / drivers / net / ixgbe / ixgbe_main.c
blobcba7a38bf6bb4e7b287561bb5d25f1b8ae8dbb3a
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43
44 #include "ixgbe.h"
45 #include "ixgbe_common.h"
46
47 char ixgbe_driver_name[] = "ixgbe";
48 static const char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
50
51 #define DRV_VERSION "1.3.18-k4"
52 const char ixgbe_driver_version[] = DRV_VERSION;
53 static const char ixgbe_copyright[] =
54 "Copyright (c) 1999-2007 Intel Corporation.";
55
56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
57 [board_82598] = &ixgbe_82598_info,
58 };
59
60 /* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68 static struct pci_device_id ixgbe_pci_tbl[] = {
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
70 board_82598 },
71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
72 board_82598 },
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
74 board_82598 },
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
76 board_82598 },
77
78 /* required last entry */
79 {0, }
80 };
81 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
82
83 #ifdef CONFIG_DCA
84 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
85 void *p);
86 static struct notifier_block dca_notifier = {
87 .notifier_call = ixgbe_notify_dca,
88 .next = NULL,
89 .priority = 0
90 };
91 #endif
92
93 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
94 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
95 MODULE_LICENSE("GPL");
96 MODULE_VERSION(DRV_VERSION);
97
98 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
99
100 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
101 {
102 u32 ctrl_ext;
103
104 /* Let firmware take over control of h/w */
105 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
107 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
108 }
109
110 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
111 {
112 u32 ctrl_ext;
113
114 /* Let firmware know the driver has taken over */
115 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
117 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
118 }
119
120 #ifdef DEBUG
121 /**
122 * ixgbe_get_hw_dev_name - return device name string
123 * used by hardware layer to print debugging information
124 **/
125 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
126 {
127 struct ixgbe_adapter *adapter = hw->back;
128 struct net_device *netdev = adapter->netdev;
129 return netdev->name;
130 }
131 #endif
132
133 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
134 u8 msix_vector)
135 {
136 u32 ivar, index;
137
138 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
139 index = (int_alloc_entry >> 2) & 0x1F;
140 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
141 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
142 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
144 }
145
146 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
147 struct ixgbe_tx_buffer
148 *tx_buffer_info)
149 {
150 if (tx_buffer_info->dma) {
151 pci_unmap_page(adapter->pdev,
152 tx_buffer_info->dma,
153 tx_buffer_info->length, PCI_DMA_TODEVICE);
154 tx_buffer_info->dma = 0;
155 }
156 if (tx_buffer_info->skb) {
157 dev_kfree_skb_any(tx_buffer_info->skb);
158 tx_buffer_info->skb = NULL;
159 }
160 /* tx_buffer_info must be completely set up in the transmit path */
161 }
162
163 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
164 struct ixgbe_ring *tx_ring,
165 unsigned int eop,
166 union ixgbe_adv_tx_desc *eop_desc)
167 {
168 /* Detect a transmit hang in hardware, this serializes the
169 * check with the clearing of time_stamp and movement of i */
170 adapter->detect_tx_hung = false;
171 if (tx_ring->tx_buffer_info[eop].dma &&
172 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
173 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
174 /* detected Tx unit hang */
175 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
176 " TDH <%x>\n"
177 " TDT <%x>\n"
178 " next_to_use <%x>\n"
179 " next_to_clean <%x>\n"
180 "tx_buffer_info[next_to_clean]\n"
181 " time_stamp <%lx>\n"
182 " next_to_watch <%x>\n"
183 " jiffies <%lx>\n"
184 " next_to_watch.status <%x>\n",
185 readl(adapter->hw.hw_addr + tx_ring->head),
186 readl(adapter->hw.hw_addr + tx_ring->tail),
187 tx_ring->next_to_use,
188 tx_ring->next_to_clean,
189 tx_ring->tx_buffer_info[eop].time_stamp,
190 eop, jiffies, eop_desc->wb.status);
191 return true;
192 }
193
194 return false;
195 }
196
197 #define IXGBE_MAX_TXD_PWR 14
198 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
199
200 /* Tx Descriptors needed, worst case */
201 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
202 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
203 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
204 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
205
206 /**
207 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
208 * @adapter: board private structure
209 **/
210 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
211 struct ixgbe_ring *tx_ring)
212 {
213 struct net_device *netdev = adapter->netdev;
214 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
215 struct ixgbe_tx_buffer *tx_buffer_info;
216 unsigned int i, eop;
217 bool cleaned = false;
218 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
219
220 i = tx_ring->next_to_clean;
221 eop = tx_ring->tx_buffer_info[i].next_to_watch;
222 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
223 while (eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) {
224 cleaned = false;
225 while (!cleaned) {
226 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
227 tx_buffer_info = &tx_ring->tx_buffer_info[i];
228 cleaned = (i == eop);
229
230 tx_ring->stats.bytes += tx_buffer_info->length;
231 if (cleaned) {
232 struct sk_buff *skb = tx_buffer_info->skb;
233 unsigned int segs, bytecount;
234 segs = skb_shinfo(skb)->gso_segs ?: 1;
235 /* multiply data chunks by size of headers */
236 bytecount = ((segs - 1) * skb_headlen(skb)) +
237 skb->len;
238 total_tx_packets += segs;
239 total_tx_bytes += bytecount;
240 }
241 ixgbe_unmap_and_free_tx_resource(adapter,
242 tx_buffer_info);
243 tx_desc->wb.status = 0;
244
245 i++;
246 if (i == tx_ring->count)
247 i = 0;
248 }
249
250 tx_ring->stats.packets++;
251
252 eop = tx_ring->tx_buffer_info[i].next_to_watch;
253 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
254
255 /* weight of a sort for tx, avoid endless transmit cleanup */
256 if (total_tx_packets >= tx_ring->work_limit)
257 break;
258 }
259
260 tx_ring->next_to_clean = i;
261
262 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
263 if (total_tx_packets && netif_carrier_ok(netdev) &&
264 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
265 /* Make sure that anybody stopping the queue after this
266 * sees the new next_to_clean.
267 */
268 smp_mb();
269 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
270 !test_bit(__IXGBE_DOWN, &adapter->state)) {
271 netif_wake_subqueue(netdev, tx_ring->queue_index);
272 adapter->restart_queue++;
273 }
274 }
275
276 if (adapter->detect_tx_hung)
277 if (ixgbe_check_tx_hang(adapter, tx_ring, eop, eop_desc))
278 netif_stop_subqueue(netdev, tx_ring->queue_index);
279
280 if (total_tx_packets >= tx_ring->work_limit)
281 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->eims_value);
282
283 tx_ring->total_bytes += total_tx_bytes;
284 tx_ring->total_packets += total_tx_packets;
285 adapter->net_stats.tx_bytes += total_tx_bytes;
286 adapter->net_stats.tx_packets += total_tx_packets;
287 cleaned = total_tx_packets ? true : false;
288 return cleaned;
289 }
290
291 #ifdef CONFIG_DCA
292 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
293 struct ixgbe_ring *rx_ring)
294 {
295 u32 rxctrl;
296 int cpu = get_cpu();
297 int q = rx_ring - adapter->rx_ring;
298
299 if (rx_ring->cpu != cpu) {
300 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
301 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
302 rxctrl |= dca_get_tag(cpu);
303 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
304 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
305 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
306 rx_ring->cpu = cpu;
307 }
308 put_cpu();
309 }
310
311 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
312 struct ixgbe_ring *tx_ring)
313 {
314 u32 txctrl;
315 int cpu = get_cpu();
316 int q = tx_ring - adapter->tx_ring;
317
318 if (tx_ring->cpu != cpu) {
319 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
320 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
321 txctrl |= dca_get_tag(cpu);
322 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
323 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
324 tx_ring->cpu = cpu;
325 }
326 put_cpu();
327 }
328
329 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
330 {
331 int i;
332
333 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
334 return;
335
336 for (i = 0; i < adapter->num_tx_queues; i++) {
337 adapter->tx_ring[i].cpu = -1;
338 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
339 }
340 for (i = 0; i < adapter->num_rx_queues; i++) {
341 adapter->rx_ring[i].cpu = -1;
342 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
343 }
344 }
345
346 static int __ixgbe_notify_dca(struct device *dev, void *data)
347 {
348 struct net_device *netdev = dev_get_drvdata(dev);
349 struct ixgbe_adapter *adapter = netdev_priv(netdev);
350 unsigned long event = *(unsigned long *)data;
351
352 switch (event) {
353 case DCA_PROVIDER_ADD:
354 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
355 /* Always use CB2 mode, difference is masked
356 * in the CB driver. */
357 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
358 if (dca_add_requester(dev) == 0) {
359 ixgbe_setup_dca(adapter);
360 break;
361 }
362 /* Fall Through since DCA is disabled. */
363 case DCA_PROVIDER_REMOVE:
364 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
365 dca_remove_requester(dev);
366 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
368 }
369 break;
370 }
371
372 return 0;
373 }
374
375 #endif /* CONFIG_DCA */
376 /**
377 * ixgbe_receive_skb - Send a completed packet up the stack
378 * @adapter: board private structure
379 * @skb: packet to send up
380 * @status: hardware indication of status of receive
381 * @rx_ring: rx descriptor ring (for a specific queue) to setup
382 * @rx_desc: rx descriptor
383 **/
384 static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
385 struct sk_buff *skb, u8 status,
386 struct ixgbe_ring *ring,
387 union ixgbe_adv_rx_desc *rx_desc)
388 {
389 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
390 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
391
392 if (adapter->netdev->features & NETIF_F_LRO &&
393 skb->ip_summed == CHECKSUM_UNNECESSARY) {
394 if (adapter->vlgrp && is_vlan)
395 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
396 adapter->vlgrp, tag,
397 rx_desc);
398 else
399 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
400 ring->lro_used = true;
401 } else {
402 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
403 if (adapter->vlgrp && is_vlan)
404 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
405 else
406 netif_receive_skb(skb);
407 } else {
408 if (adapter->vlgrp && is_vlan)
409 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
410 else
411 netif_rx(skb);
412 }
413 }
414 }
415
416 /**
417 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
418 * @adapter: address of board private structure
419 * @status_err: hardware indication of status of receive
420 * @skb: skb currently being received and modified
421 **/
422 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
423 u32 status_err, struct sk_buff *skb)
424 {
425 skb->ip_summed = CHECKSUM_NONE;
426
427 /* Rx csum disabled */
428 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
429 return;
430
431 /* if IP and error */
432 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
433 (status_err & IXGBE_RXDADV_ERR_IPE)) {
434 adapter->hw_csum_rx_error++;
435 return;
436 }
437
438 if (!(status_err & IXGBE_RXD_STAT_L4CS))
439 return;
440
441 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
442 adapter->hw_csum_rx_error++;
443 return;
444 }
445
446 /* It must be a TCP or UDP packet with a valid checksum */
447 skb->ip_summed = CHECKSUM_UNNECESSARY;
448 adapter->hw_csum_rx_good++;
449 }
450
451 /**
452 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
453 * @adapter: address of board private structure
454 **/
455 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
456 struct ixgbe_ring *rx_ring,
457 int cleaned_count)
458 {
459 struct net_device *netdev = adapter->netdev;
460 struct pci_dev *pdev = adapter->pdev;
461 union ixgbe_adv_rx_desc *rx_desc;
462 struct ixgbe_rx_buffer *bi;
463 unsigned int i;
464 unsigned int bufsz = adapter->rx_buf_len + NET_IP_ALIGN;
465
466 i = rx_ring->next_to_use;
467 bi = &rx_ring->rx_buffer_info[i];
468
469 while (cleaned_count--) {
470 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
471
472 if (!bi->page &&
473 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
474 bi->page = alloc_page(GFP_ATOMIC);
475 if (!bi->page) {
476 adapter->alloc_rx_page_failed++;
477 goto no_buffers;
478 }
479 bi->page_dma = pci_map_page(pdev, bi->page, 0,
480 PAGE_SIZE,
481 PCI_DMA_FROMDEVICE);
482 }
483
484 if (!bi->skb) {
485 struct sk_buff *skb = netdev_alloc_skb(netdev, bufsz);
486
487 if (!skb) {
488 adapter->alloc_rx_buff_failed++;
489 goto no_buffers;
490 }
491
492 /*
493 * Make buffer alignment 2 beyond a 16 byte boundary
494 * this will result in a 16 byte aligned IP header after
495 * the 14 byte MAC header is removed
496 */
497 skb_reserve(skb, NET_IP_ALIGN);
498
499 bi->skb = skb;
500 bi->dma = pci_map_single(pdev, skb->data, bufsz,
501 PCI_DMA_FROMDEVICE);
502 }
503 /* Refresh the desc even if buffer_addrs didn't change because
504 * each write-back erases this info. */
505 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
506 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
507 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
508 } else {
509 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
510 }
511
512 i++;
513 if (i == rx_ring->count)
514 i = 0;
515 bi = &rx_ring->rx_buffer_info[i];
516 }
517 no_buffers:
518 if (rx_ring->next_to_use != i) {
519 rx_ring->next_to_use = i;
520 if (i-- == 0)
521 i = (rx_ring->count - 1);
522
523 /*
524 * Force memory writes to complete before letting h/w
525 * know there are new descriptors to fetch. (Only
526 * applicable for weak-ordered memory model archs,
527 * such as IA-64).
528 */
529 wmb();
530 writel(i, adapter->hw.hw_addr + rx_ring->tail);
531 }
532 }
533
534 static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
535 struct ixgbe_ring *rx_ring,
536 int *work_done, int work_to_do)
537 {
538 struct net_device *netdev = adapter->netdev;
539 struct pci_dev *pdev = adapter->pdev;
540 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
541 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
542 struct sk_buff *skb;
543 unsigned int i;
544 u32 upper_len, len, staterr;
545 u16 hdr_info;
546 bool cleaned = false;
547 int cleaned_count = 0;
548 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
549
550 i = rx_ring->next_to_clean;
551 upper_len = 0;
552 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
553 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
554 rx_buffer_info = &rx_ring->rx_buffer_info[i];
555
556 while (staterr & IXGBE_RXD_STAT_DD) {
557 if (*work_done >= work_to_do)
558 break;
559 (*work_done)++;
560
561 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
562 hdr_info =
563 le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info);
564 len =
565 ((hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
566 IXGBE_RXDADV_HDRBUFLEN_SHIFT);
567 if (hdr_info & IXGBE_RXDADV_SPH)
568 adapter->rx_hdr_split++;
569 if (len > IXGBE_RX_HDR_SIZE)
570 len = IXGBE_RX_HDR_SIZE;
571 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
572 } else
573 len = le16_to_cpu(rx_desc->wb.upper.length);
574
575 cleaned = true;
576 skb = rx_buffer_info->skb;
577 prefetch(skb->data - NET_IP_ALIGN);
578 rx_buffer_info->skb = NULL;
579
580 if (len && !skb_shinfo(skb)->nr_frags) {
581 pci_unmap_single(pdev, rx_buffer_info->dma,
582 adapter->rx_buf_len + NET_IP_ALIGN,
583 PCI_DMA_FROMDEVICE);
584 skb_put(skb, len);
585 }
586
587 if (upper_len) {
588 pci_unmap_page(pdev, rx_buffer_info->page_dma,
589 PAGE_SIZE, PCI_DMA_FROMDEVICE);
590 rx_buffer_info->page_dma = 0;
591 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
592 rx_buffer_info->page, 0, upper_len);
593 rx_buffer_info->page = NULL;
594
595 skb->len += upper_len;
596 skb->data_len += upper_len;
597 skb->truesize += upper_len;
598 }
599
600 i++;
601 if (i == rx_ring->count)
602 i = 0;
603 next_buffer = &rx_ring->rx_buffer_info[i];
604
605 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
606 prefetch(next_rxd);
607
608 cleaned_count++;
609 if (staterr & IXGBE_RXD_STAT_EOP) {
610 rx_ring->stats.packets++;
611 rx_ring->stats.bytes += skb->len;
612 } else {
613 rx_buffer_info->skb = next_buffer->skb;
614 rx_buffer_info->dma = next_buffer->dma;
615 next_buffer->skb = skb;
616 adapter->non_eop_descs++;
617 goto next_desc;
618 }
619
620 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
621 dev_kfree_skb_irq(skb);
622 goto next_desc;
623 }
624
625 ixgbe_rx_checksum(adapter, staterr, skb);
626
627 /* probably a little skewed due to removing CRC */
628 total_rx_bytes += skb->len;
629 total_rx_packets++;
630
631 skb->protocol = eth_type_trans(skb, netdev);
632 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
633 netdev->last_rx = jiffies;
634
635 next_desc:
636 rx_desc->wb.upper.status_error = 0;
637
638 /* return some buffers to hardware, one at a time is too slow */
639 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
640 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
641 cleaned_count = 0;
642 }
643
644 /* use prefetched values */
645 rx_desc = next_rxd;
646 rx_buffer_info = next_buffer;
647
648 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
649 }
650
651 if (rx_ring->lro_used) {
652 lro_flush_all(&rx_ring->lro_mgr);
653 rx_ring->lro_used = false;
654 }
655
656 rx_ring->next_to_clean = i;
657 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
658
659 if (cleaned_count)
660 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
661
662 rx_ring->total_packets += total_rx_packets;
663 rx_ring->total_bytes += total_rx_bytes;
664 adapter->net_stats.rx_bytes += total_rx_bytes;
665 adapter->net_stats.rx_packets += total_rx_packets;
666
667 return cleaned;
668 }
669
670 static int ixgbe_clean_rxonly(struct napi_struct *, int);
671 /**
672 * ixgbe_configure_msix - Configure MSI-X hardware
673 * @adapter: board private structure
674 *
675 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
676 * interrupts.
677 **/
678 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
679 {
680 struct ixgbe_q_vector *q_vector;
681 int i, j, q_vectors, v_idx, r_idx;
682 u32 mask;
683
684 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
685
686 /* Populate the IVAR table and set the ITR values to the
687 * corresponding register.
688 */
689 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
690 q_vector = &adapter->q_vector[v_idx];
691 /* XXX for_each_bit(...) */
692 r_idx = find_first_bit(q_vector->rxr_idx,
693 adapter->num_rx_queues);
694
695 for (i = 0; i < q_vector->rxr_count; i++) {
696 j = adapter->rx_ring[r_idx].reg_idx;
697 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
698 r_idx = find_next_bit(q_vector->rxr_idx,
699 adapter->num_rx_queues,
700 r_idx + 1);
701 }
702 r_idx = find_first_bit(q_vector->txr_idx,
703 adapter->num_tx_queues);
704
705 for (i = 0; i < q_vector->txr_count; i++) {
706 j = adapter->tx_ring[r_idx].reg_idx;
707 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
708 r_idx = find_next_bit(q_vector->txr_idx,
709 adapter->num_tx_queues,
710 r_idx + 1);
711 }
712
713 /* if this is a tx only vector use half the irq (tx) rate */
714 if (q_vector->txr_count && !q_vector->rxr_count)
715 q_vector->eitr = adapter->tx_eitr;
716 else
717 /* rx only or mixed */
718 q_vector->eitr = adapter->rx_eitr;
719
720 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
721 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
722 }
723
724 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
725 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
726
727 /* set up to autoclear timer, lsc, and the vectors */
728 mask = IXGBE_EIMS_ENABLE_MASK;
729 mask &= ~IXGBE_EIMS_OTHER;
730 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
731 }
732
733 enum latency_range {
734 lowest_latency = 0,
735 low_latency = 1,
736 bulk_latency = 2,
737 latency_invalid = 255
738 };
739
740 /**
741 * ixgbe_update_itr - update the dynamic ITR value based on statistics
742 * @adapter: pointer to adapter
743 * @eitr: eitr setting (ints per sec) to give last timeslice
744 * @itr_setting: current throttle rate in ints/second
745 * @packets: the number of packets during this measurement interval
746 * @bytes: the number of bytes during this measurement interval
747 *
748 * Stores a new ITR value based on packets and byte
749 * counts during the last interrupt. The advantage of per interrupt
750 * computation is faster updates and more accurate ITR for the current
751 * traffic pattern. Constants in this function were computed
752 * based on theoretical maximum wire speed and thresholds were set based
753 * on testing data as well as attempting to minimize response time
754 * while increasing bulk throughput.
755 * this functionality is controlled by the InterruptThrottleRate module
756 * parameter (see ixgbe_param.c)
757 **/
758 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
759 u32 eitr, u8 itr_setting,
760 int packets, int bytes)
761 {
762 unsigned int retval = itr_setting;
763 u32 timepassed_us;
764 u64 bytes_perint;
765
766 if (packets == 0)
767 goto update_itr_done;
768
769
770 /* simple throttlerate management
771 * 0-20MB/s lowest (100000 ints/s)
772 * 20-100MB/s low (20000 ints/s)
773 * 100-1249MB/s bulk (8000 ints/s)
774 */
775 /* what was last interrupt timeslice? */
776 timepassed_us = 1000000/eitr;
777 bytes_perint = bytes / timepassed_us; /* bytes/usec */
778
779 switch (itr_setting) {
780 case lowest_latency:
781 if (bytes_perint > adapter->eitr_low)
782 retval = low_latency;
783 break;
784 case low_latency:
785 if (bytes_perint > adapter->eitr_high)
786 retval = bulk_latency;
787 else if (bytes_perint <= adapter->eitr_low)
788 retval = lowest_latency;
789 break;
790 case bulk_latency:
791 if (bytes_perint <= adapter->eitr_high)
792 retval = low_latency;
793 break;
794 }
795
796 update_itr_done:
797 return retval;
798 }
799
800 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
801 {
802 struct ixgbe_adapter *adapter = q_vector->adapter;
803 struct ixgbe_hw *hw = &adapter->hw;
804 u32 new_itr;
805 u8 current_itr, ret_itr;
806 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
807 sizeof(struct ixgbe_q_vector);
808 struct ixgbe_ring *rx_ring, *tx_ring;
809
810 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
811 for (i = 0; i < q_vector->txr_count; i++) {
812 tx_ring = &(adapter->tx_ring[r_idx]);
813 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
814 q_vector->tx_eitr,
815 tx_ring->total_packets,
816 tx_ring->total_bytes);
817 /* if the result for this queue would decrease interrupt
818 * rate for this vector then use that result */
819 q_vector->tx_eitr = ((q_vector->tx_eitr > ret_itr) ?
820 q_vector->tx_eitr - 1 : ret_itr);
821 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
822 r_idx + 1);
823 }
824
825 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
826 for (i = 0; i < q_vector->rxr_count; i++) {
827 rx_ring = &(adapter->rx_ring[r_idx]);
828 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
829 q_vector->rx_eitr,
830 rx_ring->total_packets,
831 rx_ring->total_bytes);
832 /* if the result for this queue would decrease interrupt
833 * rate for this vector then use that result */
834 q_vector->rx_eitr = ((q_vector->rx_eitr > ret_itr) ?
835 q_vector->rx_eitr - 1 : ret_itr);
836 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
837 r_idx + 1);
838 }
839
840 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
841
842 switch (current_itr) {
843 /* counts and packets in update_itr are dependent on these numbers */
844 case lowest_latency:
845 new_itr = 100000;
846 break;
847 case low_latency:
848 new_itr = 20000; /* aka hwitr = ~200 */
849 break;
850 case bulk_latency:
851 default:
852 new_itr = 8000;
853 break;
854 }
855
856 if (new_itr != q_vector->eitr) {
857 u32 itr_reg;
858 /* do an exponential smoothing */
859 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
860 q_vector->eitr = new_itr;
861 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
862 /* must write high and low 16 bits to reset counter */
863 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
864 itr_reg);
865 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
866 }
867
868 return;
869 }
870
871 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
872 {
873 struct net_device *netdev = data;
874 struct ixgbe_adapter *adapter = netdev_priv(netdev);
875 struct ixgbe_hw *hw = &adapter->hw;
876 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
877
878 if (eicr & IXGBE_EICR_LSC) {
879 adapter->lsc_int++;
880 if (!test_bit(__IXGBE_DOWN, &adapter->state))
881 mod_timer(&adapter->watchdog_timer, jiffies);
882 }
883
884 if (!test_bit(__IXGBE_DOWN, &adapter->state))
885 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
886
887 return IRQ_HANDLED;
888 }
889
890 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
891 {
892 struct ixgbe_q_vector *q_vector = data;
893 struct ixgbe_adapter *adapter = q_vector->adapter;
894 struct ixgbe_ring *tx_ring;
895 int i, r_idx;
896
897 if (!q_vector->txr_count)
898 return IRQ_HANDLED;
899
900 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
901 for (i = 0; i < q_vector->txr_count; i++) {
902 tx_ring = &(adapter->tx_ring[r_idx]);
903 #ifdef CONFIG_DCA
904 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
905 ixgbe_update_tx_dca(adapter, tx_ring);
906 #endif
907 tx_ring->total_bytes = 0;
908 tx_ring->total_packets = 0;
909 ixgbe_clean_tx_irq(adapter, tx_ring);
910 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
911 r_idx + 1);
912 }
913
914 return IRQ_HANDLED;
915 }
916
917 /**
918 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
919 * @irq: unused
920 * @data: pointer to our q_vector struct for this interrupt vector
921 **/
922 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
923 {
924 struct ixgbe_q_vector *q_vector = data;
925 struct ixgbe_adapter *adapter = q_vector->adapter;
926 struct ixgbe_ring *rx_ring;
927 int r_idx;
928
929 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
930 if (!q_vector->rxr_count)
931 return IRQ_HANDLED;
932
933 rx_ring = &(adapter->rx_ring[r_idx]);
934 /* disable interrupts on this vector only */
935 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
936 rx_ring->total_bytes = 0;
937 rx_ring->total_packets = 0;
938 netif_rx_schedule(adapter->netdev, &q_vector->napi);
939
940 return IRQ_HANDLED;
941 }
942
943 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
944 {
945 ixgbe_msix_clean_rx(irq, data);
946 ixgbe_msix_clean_tx(irq, data);
947
948 return IRQ_HANDLED;
949 }
950
951 /**
952 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
953 * @napi: napi struct with our devices info in it
954 * @budget: amount of work driver is allowed to do this pass, in packets
955 *
956 **/
957 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
958 {
959 struct ixgbe_q_vector *q_vector =
960 container_of(napi, struct ixgbe_q_vector, napi);
961 struct ixgbe_adapter *adapter = q_vector->adapter;
962 struct ixgbe_ring *rx_ring;
963 int work_done = 0;
964 long r_idx;
965
966 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
967 rx_ring = &(adapter->rx_ring[r_idx]);
968 #ifdef CONFIG_DCA
969 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
970 ixgbe_update_rx_dca(adapter, rx_ring);
971 #endif
972
973 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
974
975 /* If all Rx work done, exit the polling mode */
976 if (work_done < budget) {
977 netif_rx_complete(adapter->netdev, napi);
978 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
979 ixgbe_set_itr_msix(q_vector);
980 if (!test_bit(__IXGBE_DOWN, &adapter->state))
981 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
982 }
983
984 return work_done;
985 }
986
987 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
988 int r_idx)
989 {
990 a->q_vector[v_idx].adapter = a;
991 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
992 a->q_vector[v_idx].rxr_count++;
993 a->rx_ring[r_idx].v_idx = 1 << v_idx;
994 }
995
996 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
997 int r_idx)
998 {
999 a->q_vector[v_idx].adapter = a;
1000 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1001 a->q_vector[v_idx].txr_count++;
1002 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1003 }
1004
1005 /**
1006 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1007 * @adapter: board private structure to initialize
1008 * @vectors: allotted vector count for descriptor rings
1009 *
1010 * This function maps descriptor rings to the queue-specific vectors
1011 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1012 * one vector per ring/queue, but on a constrained vector budget, we
1013 * group the rings as "efficiently" as possible. You would add new
1014 * mapping configurations in here.
1015 **/
1016 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1017 int vectors)
1018 {
1019 int v_start = 0;
1020 int rxr_idx = 0, txr_idx = 0;
1021 int rxr_remaining = adapter->num_rx_queues;
1022 int txr_remaining = adapter->num_tx_queues;
1023 int i, j;
1024 int rqpv, tqpv;
1025 int err = 0;
1026
1027 /* No mapping required if MSI-X is disabled. */
1028 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1029 goto out;
1030
1031 /*
1032 * The ideal configuration...
1033 * We have enough vectors to map one per queue.
1034 */
1035 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1036 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1037 map_vector_to_rxq(adapter, v_start, rxr_idx);
1038
1039 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1040 map_vector_to_txq(adapter, v_start, txr_idx);
1041
1042 goto out;
1043 }
1044
1045 /*
1046 * If we don't have enough vectors for a 1-to-1
1047 * mapping, we'll have to group them so there are
1048 * multiple queues per vector.
1049 */
1050 /* Re-adjusting *qpv takes care of the remainder. */
1051 for (i = v_start; i < vectors; i++) {
1052 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1053 for (j = 0; j < rqpv; j++) {
1054 map_vector_to_rxq(adapter, i, rxr_idx);
1055 rxr_idx++;
1056 rxr_remaining--;
1057 }
1058 }
1059 for (i = v_start; i < vectors; i++) {
1060 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1061 for (j = 0; j < tqpv; j++) {
1062 map_vector_to_txq(adapter, i, txr_idx);
1063 txr_idx++;
1064 txr_remaining--;
1065 }
1066 }
1067
1068 out:
1069 return err;
1070 }
1071
1072 /**
1073 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1074 * @adapter: board private structure
1075 *
1076 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1077 * interrupts from the kernel.
1078 **/
1079 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1080 {
1081 struct net_device *netdev = adapter->netdev;
1082 irqreturn_t (*handler)(int, void *);
1083 int i, vector, q_vectors, err;
1084
1085 /* Decrement for Other and TCP Timer vectors */
1086 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1087
1088 /* Map the Tx/Rx rings to the vectors we were allotted. */
1089 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1090 if (err)
1091 goto out;
1092
1093 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1094 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1095 &ixgbe_msix_clean_many)
1096 for (vector = 0; vector < q_vectors; vector++) {
1097 handler = SET_HANDLER(&adapter->q_vector[vector]);
1098 sprintf(adapter->name[vector], "%s:v%d-%s",
1099 netdev->name, vector,
1100 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1101 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
1102 err = request_irq(adapter->msix_entries[vector].vector,
1103 handler, 0, adapter->name[vector],
1104 &(adapter->q_vector[vector]));
1105 if (err) {
1106 DPRINTK(PROBE, ERR,
1107 "request_irq failed for MSIX interrupt "
1108 "Error: %d\n", err);
1109 goto free_queue_irqs;
1110 }
1111 }
1112
1113 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1114 err = request_irq(adapter->msix_entries[vector].vector,
1115 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1116 if (err) {
1117 DPRINTK(PROBE, ERR,
1118 "request_irq for msix_lsc failed: %d\n", err);
1119 goto free_queue_irqs;
1120 }
1121
1122 return 0;
1123
1124 free_queue_irqs:
1125 for (i = vector - 1; i >= 0; i--)
1126 free_irq(adapter->msix_entries[--vector].vector,
1127 &(adapter->q_vector[i]));
1128 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1129 pci_disable_msix(adapter->pdev);
1130 kfree(adapter->msix_entries);
1131 adapter->msix_entries = NULL;
1132 out:
1133 return err;
1134 }
1135
1136 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1137 {
1138 struct ixgbe_hw *hw = &adapter->hw;
1139 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1140 u8 current_itr;
1141 u32 new_itr = q_vector->eitr;
1142 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1143 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1144
1145 q_vector->tx_eitr = ixgbe_update_itr(adapter, new_itr,
1146 q_vector->tx_eitr,
1147 tx_ring->total_packets,
1148 tx_ring->total_bytes);
1149 q_vector->rx_eitr = ixgbe_update_itr(adapter, new_itr,
1150 q_vector->rx_eitr,
1151 rx_ring->total_packets,
1152 rx_ring->total_bytes);
1153
1154 current_itr = max(q_vector->rx_eitr, q_vector->tx_eitr);
1155
1156 switch (current_itr) {
1157 /* counts and packets in update_itr are dependent on these numbers */
1158 case lowest_latency:
1159 new_itr = 100000;
1160 break;
1161 case low_latency:
1162 new_itr = 20000; /* aka hwitr = ~200 */
1163 break;
1164 case bulk_latency:
1165 new_itr = 8000;
1166 break;
1167 default:
1168 break;
1169 }
1170
1171 if (new_itr != q_vector->eitr) {
1172 u32 itr_reg;
1173 /* do an exponential smoothing */
1174 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1175 q_vector->eitr = new_itr;
1176 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1177 /* must write high and low 16 bits to reset counter */
1178 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1179 }
1180
1181 return;
1182 }
1183
1184 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1185
1186 /**
1187 * ixgbe_intr - legacy mode Interrupt Handler
1188 * @irq: interrupt number
1189 * @data: pointer to a network interface device structure
1190 * @pt_regs: CPU registers structure
1191 **/
1192 static irqreturn_t ixgbe_intr(int irq, void *data)
1193 {
1194 struct net_device *netdev = data;
1195 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1196 struct ixgbe_hw *hw = &adapter->hw;
1197 u32 eicr;
1198
1199
1200 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1201 * therefore no explict interrupt disable is necessary */
1202 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1203 if (!eicr)
1204 return IRQ_NONE; /* Not our interrupt */
1205
1206 if (eicr & IXGBE_EICR_LSC) {
1207 adapter->lsc_int++;
1208 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1209 mod_timer(&adapter->watchdog_timer, jiffies);
1210 }
1211
1212
1213 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
1214 adapter->tx_ring[0].total_packets = 0;
1215 adapter->tx_ring[0].total_bytes = 0;
1216 adapter->rx_ring[0].total_packets = 0;
1217 adapter->rx_ring[0].total_bytes = 0;
1218 /* would disable interrupts here but EIAM disabled it */
1219 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
1220 }
1221
1222 return IRQ_HANDLED;
1223 }
1224
1225 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1226 {
1227 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1228
1229 for (i = 0; i < q_vectors; i++) {
1230 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1231 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1232 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1233 q_vector->rxr_count = 0;
1234 q_vector->txr_count = 0;
1235 }
1236 }
1237
1238 /**
1239 * ixgbe_request_irq - initialize interrupts
1240 * @adapter: board private structure
1241 *
1242 * Attempts to configure interrupts using the best available
1243 * capabilities of the hardware and kernel.
1244 **/
1245 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1246 {
1247 struct net_device *netdev = adapter->netdev;
1248 int err;
1249
1250 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1251 err = ixgbe_request_msix_irqs(adapter);
1252 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1253 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1254 netdev->name, netdev);
1255 } else {
1256 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1257 netdev->name, netdev);
1258 }
1259
1260 if (err)
1261 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1262
1263 return err;
1264 }
1265
1266 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1267 {
1268 struct net_device *netdev = adapter->netdev;
1269
1270 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1271 int i, q_vectors;
1272
1273 q_vectors = adapter->num_msix_vectors;
1274
1275 i = q_vectors - 1;
1276 free_irq(adapter->msix_entries[i].vector, netdev);
1277
1278 i--;
1279 for (; i >= 0; i--) {
1280 free_irq(adapter->msix_entries[i].vector,
1281 &(adapter->q_vector[i]));
1282 }
1283
1284 ixgbe_reset_q_vectors(adapter);
1285 } else {
1286 free_irq(adapter->pdev->irq, netdev);
1287 }
1288 }
1289
1290 /**
1291 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1292 * @adapter: board private structure
1293 **/
1294 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1295 {
1296 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1297 IXGBE_WRITE_FLUSH(&adapter->hw);
1298 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1299 int i;
1300 for (i = 0; i < adapter->num_msix_vectors; i++)
1301 synchronize_irq(adapter->msix_entries[i].vector);
1302 } else {
1303 synchronize_irq(adapter->pdev->irq);
1304 }
1305 }
1306
1307 /**
1308 * ixgbe_irq_enable - Enable default interrupt generation settings
1309 * @adapter: board private structure
1310 **/
1311 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1312 {
1313 u32 mask;
1314 mask = IXGBE_EIMS_ENABLE_MASK;
1315 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1316 IXGBE_WRITE_FLUSH(&adapter->hw);
1317 }
1318
1319 /**
1320 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1321 *
1322 **/
1323 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1324 {
1325 struct ixgbe_hw *hw = &adapter->hw;
1326
1327 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1328 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr));
1329
1330 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
1331 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1332
1333 map_vector_to_rxq(adapter, 0, 0);
1334 map_vector_to_txq(adapter, 0, 0);
1335
1336 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1337 }
1338
1339 /**
1340 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1341 * @adapter: board private structure
1342 *
1343 * Configure the Tx unit of the MAC after a reset.
1344 **/
1345 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1346 {
1347 u64 tdba;
1348 struct ixgbe_hw *hw = &adapter->hw;
1349 u32 i, j, tdlen, txctrl;
1350
1351 /* Setup the HW Tx Head and Tail descriptor pointers */
1352 for (i = 0; i < adapter->num_tx_queues; i++) {
1353 j = adapter->tx_ring[i].reg_idx;
1354 tdba = adapter->tx_ring[i].dma;
1355 tdlen = adapter->tx_ring[i].count *
1356 sizeof(union ixgbe_adv_tx_desc);
1357 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1358 (tdba & DMA_32BIT_MASK));
1359 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1360 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1361 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1362 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1363 adapter->tx_ring[i].head = IXGBE_TDH(j);
1364 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1365 /* Disable Tx Head Writeback RO bit, since this hoses
1366 * bookkeeping if things aren't delivered in order.
1367 */
1368 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1369 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1370 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), txctrl);
1371 }
1372 }
1373
1374 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1375 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1376
1377 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1378 /**
1379 * ixgbe_get_skb_hdr - helper function for LRO header processing
1380 * @skb: pointer to sk_buff to be added to LRO packet
1381 * @iphdr: pointer to tcp header structure
1382 * @tcph: pointer to tcp header structure
1383 * @hdr_flags: pointer to header flags
1384 * @priv: private data
1385 **/
1386 static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1387 u64 *hdr_flags, void *priv)
1388 {
1389 union ixgbe_adv_rx_desc *rx_desc = priv;
1390
1391 /* Verify that this is a valid IPv4 TCP packet */
1392 if (!(rx_desc->wb.lower.lo_dword.pkt_info &
1393 (IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP)))
1394 return -1;
1395
1396 /* Set network headers */
1397 skb_reset_network_header(skb);
1398 skb_set_transport_header(skb, ip_hdrlen(skb));
1399 *iphdr = ip_hdr(skb);
1400 *tcph = tcp_hdr(skb);
1401 *hdr_flags = LRO_IPV4 | LRO_TCP;
1402 return 0;
1403 }
1404
1405 /**
1406 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1407 * @adapter: board private structure
1408 *
1409 * Configure the Rx unit of the MAC after a reset.
1410 **/
1411 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1412 {
1413 u64 rdba;
1414 struct ixgbe_hw *hw = &adapter->hw;
1415 struct net_device *netdev = adapter->netdev;
1416 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1417 int i, j;
1418 u32 rdlen, rxctrl, rxcsum;
1419 u32 random[10];
1420 u32 fctrl, hlreg0;
1421 u32 pages;
1422 u32 reta = 0, mrqc, srrctl;
1423
1424 /* Decide whether to use packet split mode or not */
1425 if (netdev->mtu > ETH_DATA_LEN)
1426 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1427 else
1428 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1429
1430 /* Set the RX buffer length according to the mode */
1431 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1432 adapter->rx_buf_len = IXGBE_RX_HDR_SIZE;
1433 } else {
1434 if (netdev->mtu <= ETH_DATA_LEN)
1435 adapter->rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1436 else
1437 adapter->rx_buf_len = ALIGN(max_frame, 1024);
1438 }
1439
1440 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1441 fctrl |= IXGBE_FCTRL_BAM;
1442 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1443 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1444
1445 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1446 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1447 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1448 else
1449 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1450 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1451
1452 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1453
1454 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(0));
1455 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1456 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1457
1458 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1459 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1460 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1461 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1462 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1463 IXGBE_SRRCTL_BSIZEHDR_MASK);
1464 } else {
1465 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1466
1467 if (adapter->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1468 srrctl |=
1469 IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1470 else
1471 srrctl |=
1472 adapter->rx_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1473 }
1474 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(0), srrctl);
1475
1476 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1477 /* disable receives while setting up the descriptors */
1478 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1479 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1480
1481 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1482 * the Base and Length of the Rx Descriptor Ring */
1483 for (i = 0; i < adapter->num_rx_queues; i++) {
1484 rdba = adapter->rx_ring[i].dma;
1485 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i), (rdba & DMA_32BIT_MASK));
1486 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(i), (rdba >> 32));
1487 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(i), rdlen);
1488 IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
1489 IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
1490 adapter->rx_ring[i].head = IXGBE_RDH(i);
1491 adapter->rx_ring[i].tail = IXGBE_RDT(i);
1492 }
1493
1494 /* Intitial LRO Settings */
1495 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1496 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1497 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1498 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1499 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1500 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1501 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1502 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1503 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1504
1505 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1506 /* Fill out redirection table */
1507 for (i = 0, j = 0; i < 128; i++, j++) {
1508 if (j == adapter->ring_feature[RING_F_RSS].indices)
1509 j = 0;
1510 /* reta = 4-byte sliding window of
1511 * 0x00..(indices-1)(indices-1)00..etc. */
1512 reta = (reta << 8) | (j * 0x11);
1513 if ((i & 3) == 3)
1514 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1515 }
1516
1517 /* Fill out hash function seeds */
1518 /* XXX use a random constant here to glue certain flows */
1519 get_random_bytes(&random[0], 40);
1520 for (i = 0; i < 10; i++)
1521 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), random[i]);
1522
1523 mrqc = IXGBE_MRQC_RSSEN
1524 /* Perform hash on these packet types */
1525 | IXGBE_MRQC_RSS_FIELD_IPV4
1526 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1527 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1528 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1529 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1530 | IXGBE_MRQC_RSS_FIELD_IPV6
1531 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1532 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1533 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1534 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1535 }
1536
1537 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1538
1539 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1540 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1541 /* Disable indicating checksum in descriptor, enables
1542 * RSS hash */
1543 rxcsum |= IXGBE_RXCSUM_PCSD;
1544 }
1545 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1546 /* Enable IPv4 payload checksum for UDP fragments
1547 * if PCSD is not set */
1548 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1549 }
1550
1551 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1552 }
1553
1554 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1555 struct vlan_group *grp)
1556 {
1557 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1558 u32 ctrl;
1559
1560 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1561 ixgbe_irq_disable(adapter);
1562 adapter->vlgrp = grp;
1563
1564 if (grp) {
1565 /* enable VLAN tag insert/strip */
1566 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1567 ctrl |= IXGBE_VLNCTRL_VME;
1568 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1570 }
1571
1572 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1573 ixgbe_irq_enable(adapter);
1574 }
1575
1576 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1577 {
1578 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1579
1580 /* add VID to filter table */
1581 ixgbe_set_vfta(&adapter->hw, vid, 0, true);
1582 }
1583
1584 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1585 {
1586 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1587
1588 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1589 ixgbe_irq_disable(adapter);
1590
1591 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1592
1593 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1594 ixgbe_irq_enable(adapter);
1595
1596 /* remove VID from filter table */
1597 ixgbe_set_vfta(&adapter->hw, vid, 0, false);
1598 }
1599
1600 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1601 {
1602 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1603
1604 if (adapter->vlgrp) {
1605 u16 vid;
1606 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1607 if (!vlan_group_get_device(adapter->vlgrp, vid))
1608 continue;
1609 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1610 }
1611 }
1612 }
1613
1614 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1615 {
1616 struct dev_mc_list *mc_ptr;
1617 u8 *addr = *mc_addr_ptr;
1618 *vmdq = 0;
1619
1620 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1621 if (mc_ptr->next)
1622 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1623 else
1624 *mc_addr_ptr = NULL;
1625
1626 return addr;
1627 }
1628
1629 /**
1630 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1631 * @netdev: network interface device structure
1632 *
1633 * The set_rx_method entry point is called whenever the unicast/multicast
1634 * address list or the network interface flags are updated. This routine is
1635 * responsible for configuring the hardware for proper unicast, multicast and
1636 * promiscuous mode.
1637 **/
1638 static void ixgbe_set_rx_mode(struct net_device *netdev)
1639 {
1640 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1641 struct ixgbe_hw *hw = &adapter->hw;
1642 u32 fctrl, vlnctrl;
1643 u8 *addr_list = NULL;
1644 int addr_count = 0;
1645
1646 /* Check for Promiscuous and All Multicast modes */
1647
1648 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1649 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1650
1651 if (netdev->flags & IFF_PROMISC) {
1652 hw->addr_ctrl.user_set_promisc = 1;
1653 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1654 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1655 } else {
1656 if (netdev->flags & IFF_ALLMULTI) {
1657 fctrl |= IXGBE_FCTRL_MPE;
1658 fctrl &= ~IXGBE_FCTRL_UPE;
1659 } else {
1660 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1661 }
1662 vlnctrl |= IXGBE_VLNCTRL_VFE;
1663 hw->addr_ctrl.user_set_promisc = 0;
1664 }
1665
1666 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1667 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1668
1669 /* reprogram secondary unicast list */
1670 addr_count = netdev->uc_count;
1671 if (addr_count)
1672 addr_list = netdev->uc_list->dmi_addr;
1673 ixgbe_update_uc_addr_list(hw, addr_list, addr_count,
1674 ixgbe_addr_list_itr);
1675
1676 /* reprogram multicast list */
1677 addr_count = netdev->mc_count;
1678 if (addr_count)
1679 addr_list = netdev->mc_list->dmi_addr;
1680 ixgbe_update_mc_addr_list(hw, addr_list, addr_count,
1681 ixgbe_addr_list_itr);
1682 }
1683
1684 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1685 {
1686 int q_idx;
1687 struct ixgbe_q_vector *q_vector;
1688 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1689
1690 /* legacy and MSI only use one vector */
1691 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1692 q_vectors = 1;
1693
1694 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1695 q_vector = &adapter->q_vector[q_idx];
1696 if (!q_vector->rxr_count)
1697 continue;
1698 napi_enable(&q_vector->napi);
1699 }
1700 }
1701
1702 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1703 {
1704 int q_idx;
1705 struct ixgbe_q_vector *q_vector;
1706 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1707
1708 /* legacy and MSI only use one vector */
1709 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1710 q_vectors = 1;
1711
1712 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1713 q_vector = &adapter->q_vector[q_idx];
1714 if (!q_vector->rxr_count)
1715 continue;
1716 napi_disable(&q_vector->napi);
1717 }
1718 }
1719
1720 static void ixgbe_configure(struct ixgbe_adapter *adapter)
1721 {
1722 struct net_device *netdev = adapter->netdev;
1723 int i;
1724
1725 ixgbe_set_rx_mode(netdev);
1726
1727 ixgbe_restore_vlan(adapter);
1728
1729 ixgbe_configure_tx(adapter);
1730 ixgbe_configure_rx(adapter);
1731 for (i = 0; i < adapter->num_rx_queues; i++)
1732 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1733 (adapter->rx_ring[i].count - 1));
1734 }
1735
1736 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1737 {
1738 struct net_device *netdev = adapter->netdev;
1739 struct ixgbe_hw *hw = &adapter->hw;
1740 int i, j = 0;
1741 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1742 u32 txdctl, rxdctl, mhadd;
1743 u32 gpie;
1744
1745 ixgbe_get_hw_control(adapter);
1746
1747 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1748 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
1749 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1750 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1751 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1752 } else {
1753 /* MSI only */
1754 gpie = 0;
1755 }
1756 /* XXX: to interrupt immediately for EICS writes, enable this */
1757 /* gpie |= IXGBE_GPIE_EIMEN; */
1758 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
1759 }
1760
1761 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1762 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1763 * specifically only auto mask tx and rx interrupts */
1764 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1765 }
1766
1767 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
1768 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1769 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1770 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1771
1772 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1773 }
1774
1775 for (i = 0; i < adapter->num_tx_queues; i++) {
1776 j = adapter->tx_ring[i].reg_idx;
1777 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
1778 txdctl |= IXGBE_TXDCTL_ENABLE;
1779 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1780 }
1781
1782 for (i = 0; i < adapter->num_rx_queues; i++) {
1783 j = adapter->rx_ring[i].reg_idx;
1784 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1785 /* enable PTHRESH=32 descriptors (half the internal cache)
1786 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1787 * this also removes a pesky rx_no_buffer_count increment */
1788 rxdctl |= 0x0020;
1789 rxdctl |= IXGBE_RXDCTL_ENABLE;
1790 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
1791 }
1792 /* enable all receives */
1793 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1794 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1795 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1796
1797 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1798 ixgbe_configure_msix(adapter);
1799 else
1800 ixgbe_configure_msi_and_legacy(adapter);
1801
1802 clear_bit(__IXGBE_DOWN, &adapter->state);
1803 ixgbe_napi_enable_all(adapter);
1804
1805 /* clear any pending interrupts, may auto mask */
1806 IXGBE_READ_REG(hw, IXGBE_EICR);
1807
1808 ixgbe_irq_enable(adapter);
1809
1810 /* bring the link up in the watchdog, this could race with our first
1811 * link up interrupt but shouldn't be a problem */
1812 mod_timer(&adapter->watchdog_timer, jiffies);
1813 return 0;
1814 }
1815
1816 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1817 {
1818 WARN_ON(in_interrupt());
1819 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1820 msleep(1);
1821 ixgbe_down(adapter);
1822 ixgbe_up(adapter);
1823 clear_bit(__IXGBE_RESETTING, &adapter->state);
1824 }
1825
1826 int ixgbe_up(struct ixgbe_adapter *adapter)
1827 {
1828 /* hardware has been reset, we need to reload some things */
1829 ixgbe_configure(adapter);
1830
1831 return ixgbe_up_complete(adapter);
1832 }
1833
1834 void ixgbe_reset(struct ixgbe_adapter *adapter)
1835 {
1836 if (ixgbe_init_hw(&adapter->hw))
1837 DPRINTK(PROBE, ERR, "Hardware Error\n");
1838
1839 /* reprogram the RAR[0] in case user changed it. */
1840 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
1841
1842 }
1843
1844 #ifdef CONFIG_PM
1845 static int ixgbe_resume(struct pci_dev *pdev)
1846 {
1847 struct net_device *netdev = pci_get_drvdata(pdev);
1848 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1849 u32 err;
1850
1851 pci_set_power_state(pdev, PCI_D0);
1852 pci_restore_state(pdev);
1853 err = pci_enable_device(pdev);
1854 if (err) {
1855 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
1856 "suspend\n");
1857 return err;
1858 }
1859 pci_set_master(pdev);
1860
1861 pci_enable_wake(pdev, PCI_D3hot, 0);
1862 pci_enable_wake(pdev, PCI_D3cold, 0);
1863
1864 if (netif_running(netdev)) {
1865 err = ixgbe_request_irq(adapter);
1866 if (err)
1867 return err;
1868 }
1869
1870 ixgbe_reset(adapter);
1871
1872 if (netif_running(netdev))
1873 ixgbe_up(adapter);
1874
1875 netif_device_attach(netdev);
1876
1877 return 0;
1878 }
1879 #endif
1880
1881 /**
1882 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
1883 * @adapter: board private structure
1884 * @rx_ring: ring to free buffers from
1885 **/
1886 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
1887 struct ixgbe_ring *rx_ring)
1888 {
1889 struct pci_dev *pdev = adapter->pdev;
1890 unsigned long size;
1891 unsigned int i;
1892
1893 /* Free all the Rx ring sk_buffs */
1894
1895 for (i = 0; i < rx_ring->count; i++) {
1896 struct ixgbe_rx_buffer *rx_buffer_info;
1897
1898 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1899 if (rx_buffer_info->dma) {
1900 pci_unmap_single(pdev, rx_buffer_info->dma,
1901 adapter->rx_buf_len,
1902 PCI_DMA_FROMDEVICE);
1903 rx_buffer_info->dma = 0;
1904 }
1905 if (rx_buffer_info->skb) {
1906 dev_kfree_skb(rx_buffer_info->skb);
1907 rx_buffer_info->skb = NULL;
1908 }
1909 if (!rx_buffer_info->page)
1910 continue;
1911 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE,
1912 PCI_DMA_FROMDEVICE);
1913 rx_buffer_info->page_dma = 0;
1914
1915 put_page(rx_buffer_info->page);
1916 rx_buffer_info->page = NULL;
1917 }
1918
1919 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1920 memset(rx_ring->rx_buffer_info, 0, size);
1921
1922 /* Zero out the descriptor ring */
1923 memset(rx_ring->desc, 0, rx_ring->size);
1924
1925 rx_ring->next_to_clean = 0;
1926 rx_ring->next_to_use = 0;
1927
1928 writel(0, adapter->hw.hw_addr + rx_ring->head);
1929 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1930 }
1931
1932 /**
1933 * ixgbe_clean_tx_ring - Free Tx Buffers
1934 * @adapter: board private structure
1935 * @tx_ring: ring to be cleaned
1936 **/
1937 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
1938 struct ixgbe_ring *tx_ring)
1939 {
1940 struct ixgbe_tx_buffer *tx_buffer_info;
1941 unsigned long size;
1942 unsigned int i;
1943
1944 /* Free all the Tx ring sk_buffs */
1945
1946 for (i = 0; i < tx_ring->count; i++) {
1947 tx_buffer_info = &tx_ring->tx_buffer_info[i];
1948 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1949 }
1950
1951 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
1952 memset(tx_ring->tx_buffer_info, 0, size);
1953
1954 /* Zero out the descriptor ring */
1955 memset(tx_ring->desc, 0, tx_ring->size);
1956
1957 tx_ring->next_to_use = 0;
1958 tx_ring->next_to_clean = 0;
1959
1960 writel(0, adapter->hw.hw_addr + tx_ring->head);
1961 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1962 }
1963
1964 /**
1965 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
1966 * @adapter: board private structure
1967 **/
1968 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
1969 {
1970 int i;
1971
1972 for (i = 0; i < adapter->num_rx_queues; i++)
1973 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1974 }
1975
1976 /**
1977 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
1978 * @adapter: board private structure
1979 **/
1980 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
1981 {
1982 int i;
1983
1984 for (i = 0; i < adapter->num_tx_queues; i++)
1985 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1986 }
1987
1988 void ixgbe_down(struct ixgbe_adapter *adapter)
1989 {
1990 struct net_device *netdev = adapter->netdev;
1991 u32 rxctrl;
1992
1993 /* signal that we are down to the interrupt handler */
1994 set_bit(__IXGBE_DOWN, &adapter->state);
1995
1996 /* disable receives */
1997 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1998 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL,
1999 rxctrl & ~IXGBE_RXCTRL_RXEN);
2000
2001 netif_tx_disable(netdev);
2002
2003 /* disable transmits in the hardware */
2004
2005 /* flush both disables */
2006 IXGBE_WRITE_FLUSH(&adapter->hw);
2007 msleep(10);
2008
2009 ixgbe_irq_disable(adapter);
2010
2011 ixgbe_napi_disable_all(adapter);
2012 del_timer_sync(&adapter->watchdog_timer);
2013
2014 netif_carrier_off(netdev);
2015 netif_tx_stop_all_queues(netdev);
2016
2017 if (!pci_channel_offline(adapter->pdev))
2018 ixgbe_reset(adapter);
2019 ixgbe_clean_all_tx_rings(adapter);
2020 ixgbe_clean_all_rx_rings(adapter);
2021
2022 }
2023
2024 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
2025 {
2026 struct net_device *netdev = pci_get_drvdata(pdev);
2027 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2028 #ifdef CONFIG_PM
2029 int retval = 0;
2030 #endif
2031
2032 netif_device_detach(netdev);
2033
2034 if (netif_running(netdev)) {
2035 ixgbe_down(adapter);
2036 ixgbe_free_irq(adapter);
2037 }
2038
2039 #ifdef CONFIG_PM
2040 retval = pci_save_state(pdev);
2041 if (retval)
2042 return retval;
2043 #endif
2044
2045 pci_enable_wake(pdev, PCI_D3hot, 0);
2046 pci_enable_wake(pdev, PCI_D3cold, 0);
2047
2048 ixgbe_release_hw_control(adapter);
2049
2050 pci_disable_device(pdev);
2051
2052 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2053
2054 return 0;
2055 }
2056
2057 static void ixgbe_shutdown(struct pci_dev *pdev)
2058 {
2059 ixgbe_suspend(pdev, PMSG_SUSPEND);
2060 }
2061
2062 /**
2063 * ixgbe_poll - NAPI Rx polling callback
2064 * @napi: structure for representing this polling device
2065 * @budget: how many packets driver is allowed to clean
2066 *
2067 * This function is used for legacy and MSI, NAPI mode
2068 **/
2069 static int ixgbe_poll(struct napi_struct *napi, int budget)
2070 {
2071 struct ixgbe_q_vector *q_vector = container_of(napi,
2072 struct ixgbe_q_vector, napi);
2073 struct ixgbe_adapter *adapter = q_vector->adapter;
2074 int tx_cleaned = 0, work_done = 0;
2075
2076 #ifdef CONFIG_DCA
2077 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2078 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2079 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2080 }
2081 #endif
2082
2083 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2084 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
2085
2086 if (tx_cleaned)
2087 work_done = budget;
2088
2089 /* If budget not fully consumed, exit the polling mode */
2090 if (work_done < budget) {
2091 netif_rx_complete(adapter->netdev, napi);
2092 if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
2093 ixgbe_set_itr(adapter);
2094 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2095 ixgbe_irq_enable(adapter);
2096 }
2097
2098 return work_done;
2099 }
2100
2101 /**
2102 * ixgbe_tx_timeout - Respond to a Tx Hang
2103 * @netdev: network interface device structure
2104 **/
2105 static void ixgbe_tx_timeout(struct net_device *netdev)
2106 {
2107 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2108
2109 /* Do the reset outside of interrupt context */
2110 schedule_work(&adapter->reset_task);
2111 }
2112
2113 static void ixgbe_reset_task(struct work_struct *work)
2114 {
2115 struct ixgbe_adapter *adapter;
2116 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2117
2118 adapter->tx_timeout_count++;
2119
2120 ixgbe_reinit_locked(adapter);
2121 }
2122
2123 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2124 int vectors)
2125 {
2126 int err, vector_threshold;
2127
2128 /* We'll want at least 3 (vector_threshold):
2129 * 1) TxQ[0] Cleanup
2130 * 2) RxQ[0] Cleanup
2131 * 3) Other (Link Status Change, etc.)
2132 * 4) TCP Timer (optional)
2133 */
2134 vector_threshold = MIN_MSIX_COUNT;
2135
2136 /* The more we get, the more we will assign to Tx/Rx Cleanup
2137 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2138 * Right now, we simply care about how many we'll get; we'll
2139 * set them up later while requesting irq's.
2140 */
2141 while (vectors >= vector_threshold) {
2142 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2143 vectors);
2144 if (!err) /* Success in acquiring all requested vectors. */
2145 break;
2146 else if (err < 0)
2147 vectors = 0; /* Nasty failure, quit now */
2148 else /* err == number of vectors we should try again with */
2149 vectors = err;
2150 }
2151
2152 if (vectors < vector_threshold) {
2153 /* Can't allocate enough MSI-X interrupts? Oh well.
2154 * This just means we'll go with either a single MSI
2155 * vector or fall back to legacy interrupts.
2156 */
2157 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2158 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2159 kfree(adapter->msix_entries);
2160 adapter->msix_entries = NULL;
2161 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2162 adapter->num_tx_queues = 1;
2163 adapter->num_rx_queues = 1;
2164 } else {
2165 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2166 adapter->num_msix_vectors = vectors;
2167 }
2168 }
2169
2170 static void __devinit ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2171 {
2172 int nrq, ntq;
2173 int feature_mask = 0, rss_i, rss_m;
2174
2175 /* Number of supported queues */
2176 switch (adapter->hw.mac.type) {
2177 case ixgbe_mac_82598EB:
2178 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2179 rss_m = 0;
2180 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2181
2182 switch (adapter->flags & feature_mask) {
2183 case (IXGBE_FLAG_RSS_ENABLED):
2184 rss_m = 0xF;
2185 nrq = rss_i;
2186 ntq = rss_i;
2187 break;
2188 case 0:
2189 default:
2190 rss_i = 0;
2191 rss_m = 0;
2192 nrq = 1;
2193 ntq = 1;
2194 break;
2195 }
2196
2197 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2198 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2199 break;
2200 default:
2201 nrq = 1;
2202 ntq = 1;
2203 break;
2204 }
2205
2206 adapter->num_rx_queues = nrq;
2207 adapter->num_tx_queues = ntq;
2208 }
2209
2210 /**
2211 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2212 * @adapter: board private structure to initialize
2213 *
2214 * Once we know the feature-set enabled for the device, we'll cache
2215 * the register offset the descriptor ring is assigned to.
2216 **/
2217 static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2218 {
2219 /* TODO: Remove all uses of the indices in the cases where multiple
2220 * features are OR'd together, if the feature set makes sense.
2221 */
2222 int feature_mask = 0, rss_i;
2223 int i, txr_idx, rxr_idx;
2224
2225 /* Number of supported queues */
2226 switch (adapter->hw.mac.type) {
2227 case ixgbe_mac_82598EB:
2228 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2229 txr_idx = 0;
2230 rxr_idx = 0;
2231 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2232 switch (adapter->flags & feature_mask) {
2233 case (IXGBE_FLAG_RSS_ENABLED):
2234 for (i = 0; i < adapter->num_rx_queues; i++)
2235 adapter->rx_ring[i].reg_idx = i;
2236 for (i = 0; i < adapter->num_tx_queues; i++)
2237 adapter->tx_ring[i].reg_idx = i;
2238 break;
2239 case 0:
2240 default:
2241 break;
2242 }
2243 break;
2244 default:
2245 break;
2246 }
2247 }
2248
2249 /**
2250 * ixgbe_alloc_queues - Allocate memory for all rings
2251 * @adapter: board private structure to initialize
2252 *
2253 * We allocate one ring per queue at run-time since we don't know the
2254 * number of queues at compile-time. The polling_netdev array is
2255 * intended for Multiqueue, but should work fine with a single queue.
2256 **/
2257 static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2258 {
2259 int i;
2260
2261 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2262 sizeof(struct ixgbe_ring), GFP_KERNEL);
2263 if (!adapter->tx_ring)
2264 goto err_tx_ring_allocation;
2265
2266 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2267 sizeof(struct ixgbe_ring), GFP_KERNEL);
2268 if (!adapter->rx_ring)
2269 goto err_rx_ring_allocation;
2270
2271 for (i = 0; i < adapter->num_tx_queues; i++) {
2272 adapter->tx_ring[i].count = IXGBE_DEFAULT_TXD;
2273 adapter->tx_ring[i].queue_index = i;
2274 }
2275 for (i = 0; i < adapter->num_rx_queues; i++) {
2276 adapter->rx_ring[i].count = IXGBE_DEFAULT_RXD;
2277 adapter->rx_ring[i].queue_index = i;
2278 }
2279
2280 ixgbe_cache_ring_register(adapter);
2281
2282 return 0;
2283
2284 err_rx_ring_allocation:
2285 kfree(adapter->tx_ring);
2286 err_tx_ring_allocation:
2287 return -ENOMEM;
2288 }
2289
2290 /**
2291 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2292 * @adapter: board private structure to initialize
2293 *
2294 * Attempt to configure the interrupts using the best available
2295 * capabilities of the hardware and the kernel.
2296 **/
2297 static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
2298 *adapter)
2299 {
2300 int err = 0;
2301 int vector, v_budget;
2302
2303 /*
2304 * It's easy to be greedy for MSI-X vectors, but it really
2305 * doesn't do us much good if we have a lot more vectors
2306 * than CPU's. So let's be conservative and only ask for
2307 * (roughly) twice the number of vectors as there are CPU's.
2308 */
2309 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2310 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2311
2312 /*
2313 * At the same time, hardware can only support a maximum of
2314 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2315 * we can easily reach upwards of 64 Rx descriptor queues and
2316 * 32 Tx queues. Thus, we cap it off in those rare cases where
2317 * the cpu count also exceeds our vector limit.
2318 */
2319 v_budget = min(v_budget, MAX_MSIX_COUNT);
2320
2321 /* A failure in MSI-X entry allocation isn't fatal, but it does
2322 * mean we disable MSI-X capabilities of the adapter. */
2323 adapter->msix_entries = kcalloc(v_budget,
2324 sizeof(struct msix_entry), GFP_KERNEL);
2325 if (!adapter->msix_entries) {
2326 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2327 ixgbe_set_num_queues(adapter);
2328 kfree(adapter->tx_ring);
2329 kfree(adapter->rx_ring);
2330 err = ixgbe_alloc_queues(adapter);
2331 if (err) {
2332 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2333 "for queues\n");
2334 goto out;
2335 }
2336
2337 goto try_msi;
2338 }
2339
2340 for (vector = 0; vector < v_budget; vector++)
2341 adapter->msix_entries[vector].entry = vector;
2342
2343 ixgbe_acquire_msix_vectors(adapter, v_budget);
2344
2345 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2346 goto out;
2347
2348 try_msi:
2349 err = pci_enable_msi(adapter->pdev);
2350 if (!err) {
2351 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2352 } else {
2353 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2354 "falling back to legacy. Error: %d\n", err);
2355 /* reset err */
2356 err = 0;
2357 }
2358
2359 out:
2360 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2361 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2362
2363 return err;
2364 }
2365
2366 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2367 {
2368 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2369 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2370 pci_disable_msix(adapter->pdev);
2371 kfree(adapter->msix_entries);
2372 adapter->msix_entries = NULL;
2373 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2374 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2375 pci_disable_msi(adapter->pdev);
2376 }
2377 return;
2378 }
2379
2380 /**
2381 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2382 * @adapter: board private structure to initialize
2383 *
2384 * We determine which interrupt scheme to use based on...
2385 * - Kernel support (MSI, MSI-X)
2386 * - which can be user-defined (via MODULE_PARAM)
2387 * - Hardware queue count (num_*_queues)
2388 * - defined by miscellaneous hardware support/features (RSS, etc.)
2389 **/
2390 static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2391 {
2392 int err;
2393
2394 /* Number of supported queues */
2395 ixgbe_set_num_queues(adapter);
2396
2397 err = ixgbe_alloc_queues(adapter);
2398 if (err) {
2399 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2400 goto err_alloc_queues;
2401 }
2402
2403 err = ixgbe_set_interrupt_capability(adapter);
2404 if (err) {
2405 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2406 goto err_set_interrupt;
2407 }
2408
2409 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2410 "Tx Queue count = %u\n",
2411 (adapter->num_rx_queues > 1) ? "Enabled" :
2412 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2413
2414 set_bit(__IXGBE_DOWN, &adapter->state);
2415
2416 return 0;
2417
2418 err_set_interrupt:
2419 kfree(adapter->tx_ring);
2420 kfree(adapter->rx_ring);
2421 err_alloc_queues:
2422 return err;
2423 }
2424
2425 /**
2426 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2427 * @adapter: board private structure to initialize
2428 *
2429 * ixgbe_sw_init initializes the Adapter private data structure.
2430 * Fields are initialized based on PCI device information and
2431 * OS network device settings (MTU size).
2432 **/
2433 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2434 {
2435 struct ixgbe_hw *hw = &adapter->hw;
2436 struct pci_dev *pdev = adapter->pdev;
2437 unsigned int rss;
2438
2439 /* Set capability flags */
2440 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2441 adapter->ring_feature[RING_F_RSS].indices = rss;
2442 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2443
2444 /* Enable Dynamic interrupt throttling by default */
2445 adapter->rx_eitr = 1;
2446 adapter->tx_eitr = 1;
2447
2448 /* default flow control settings */
2449 hw->fc.original_type = ixgbe_fc_none;
2450 hw->fc.type = ixgbe_fc_none;
2451 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2452 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2453 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2454 hw->fc.send_xon = true;
2455
2456 /* select 10G link by default */
2457 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2458 if (hw->mac.ops.reset(hw)) {
2459 dev_err(&pdev->dev, "HW Init failed\n");
2460 return -EIO;
2461 }
2462 if (hw->mac.ops.setup_link_speed(hw, IXGBE_LINK_SPEED_10GB_FULL, true,
2463 false)) {
2464 dev_err(&pdev->dev, "Link Speed setup failed\n");
2465 return -EIO;
2466 }
2467
2468 /* initialize eeprom parameters */
2469 if (ixgbe_init_eeprom(hw)) {
2470 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2471 return -EIO;
2472 }
2473
2474 /* enable rx csum by default */
2475 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2476
2477 set_bit(__IXGBE_DOWN, &adapter->state);
2478
2479 return 0;
2480 }
2481
2482 /**
2483 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2484 * @adapter: board private structure
2485 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2486 *
2487 * Return 0 on success, negative on failure
2488 **/
2489 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2490 struct ixgbe_ring *tx_ring)
2491 {
2492 struct pci_dev *pdev = adapter->pdev;
2493 int size;
2494
2495 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2496 tx_ring->tx_buffer_info = vmalloc(size);
2497 if (!tx_ring->tx_buffer_info) {
2498 DPRINTK(PROBE, ERR,
2499 "Unable to allocate memory for the transmit descriptor ring\n");
2500 return -ENOMEM;
2501 }
2502 memset(tx_ring->tx_buffer_info, 0, size);
2503
2504 /* round up to nearest 4K */
2505 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
2506 tx_ring->size = ALIGN(tx_ring->size, 4096);
2507
2508 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2509 &tx_ring->dma);
2510 if (!tx_ring->desc) {
2511 vfree(tx_ring->tx_buffer_info);
2512 DPRINTK(PROBE, ERR,
2513 "Memory allocation failed for the tx desc ring\n");
2514 return -ENOMEM;
2515 }
2516
2517 tx_ring->next_to_use = 0;
2518 tx_ring->next_to_clean = 0;
2519 tx_ring->work_limit = tx_ring->count;
2520
2521 return 0;
2522 }
2523
2524 /**
2525 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2526 * @adapter: board private structure
2527 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2528 *
2529 * Returns 0 on success, negative on failure
2530 **/
2531 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2532 struct ixgbe_ring *rx_ring)
2533 {
2534 struct pci_dev *pdev = adapter->pdev;
2535 int size;
2536
2537 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
2538 rx_ring->lro_mgr.lro_arr = vmalloc(size);
2539 if (!rx_ring->lro_mgr.lro_arr)
2540 return -ENOMEM;
2541 memset(rx_ring->lro_mgr.lro_arr, 0, size);
2542
2543 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2544 rx_ring->rx_buffer_info = vmalloc(size);
2545 if (!rx_ring->rx_buffer_info) {
2546 DPRINTK(PROBE, ERR,
2547 "vmalloc allocation failed for the rx desc ring\n");
2548 goto alloc_failed;
2549 }
2550 memset(rx_ring->rx_buffer_info, 0, size);
2551
2552 /* Round up to nearest 4K */
2553 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2554 rx_ring->size = ALIGN(rx_ring->size, 4096);
2555
2556 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
2557
2558 if (!rx_ring->desc) {
2559 DPRINTK(PROBE, ERR,
2560 "Memory allocation failed for the rx desc ring\n");
2561 vfree(rx_ring->rx_buffer_info);
2562 goto alloc_failed;
2563 }
2564
2565 rx_ring->next_to_clean = 0;
2566 rx_ring->next_to_use = 0;
2567
2568 return 0;
2569
2570 alloc_failed:
2571 vfree(rx_ring->lro_mgr.lro_arr);
2572 rx_ring->lro_mgr.lro_arr = NULL;
2573 return -ENOMEM;
2574 }
2575
2576 /**
2577 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2578 * @adapter: board private structure
2579 * @tx_ring: Tx descriptor ring for a specific queue
2580 *
2581 * Free all transmit software resources
2582 **/
2583 static void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2584 struct ixgbe_ring *tx_ring)
2585 {
2586 struct pci_dev *pdev = adapter->pdev;
2587
2588 ixgbe_clean_tx_ring(adapter, tx_ring);
2589
2590 vfree(tx_ring->tx_buffer_info);
2591 tx_ring->tx_buffer_info = NULL;
2592
2593 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2594
2595 tx_ring->desc = NULL;
2596 }
2597
2598 /**
2599 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2600 * @adapter: board private structure
2601 *
2602 * Free all transmit software resources
2603 **/
2604 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2605 {
2606 int i;
2607
2608 for (i = 0; i < adapter->num_tx_queues; i++)
2609 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2610 }
2611
2612 /**
2613 * ixgbe_free_rx_resources - Free Rx Resources
2614 * @adapter: board private structure
2615 * @rx_ring: ring to clean the resources from
2616 *
2617 * Free all receive software resources
2618 **/
2619 static void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2620 struct ixgbe_ring *rx_ring)
2621 {
2622 struct pci_dev *pdev = adapter->pdev;
2623
2624 vfree(rx_ring->lro_mgr.lro_arr);
2625 rx_ring->lro_mgr.lro_arr = NULL;
2626
2627 ixgbe_clean_rx_ring(adapter, rx_ring);
2628
2629 vfree(rx_ring->rx_buffer_info);
2630 rx_ring->rx_buffer_info = NULL;
2631
2632 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2633
2634 rx_ring->desc = NULL;
2635 }
2636
2637 /**
2638 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2639 * @adapter: board private structure
2640 *
2641 * Free all receive software resources
2642 **/
2643 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2644 {
2645 int i;
2646
2647 for (i = 0; i < adapter->num_rx_queues; i++)
2648 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2649 }
2650
2651 /**
2652 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2653 * @adapter: board private structure
2654 *
2655 * If this function returns with an error, then it's possible one or
2656 * more of the rings is populated (while the rest are not). It is the
2657 * callers duty to clean those orphaned rings.
2658 *
2659 * Return 0 on success, negative on failure
2660 **/
2661 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2662 {
2663 int i, err = 0;
2664
2665 for (i = 0; i < adapter->num_tx_queues; i++) {
2666 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2667 if (err) {
2668 DPRINTK(PROBE, ERR,
2669 "Allocation for Tx Queue %u failed\n", i);
2670 break;
2671 }
2672 }
2673
2674 return err;
2675 }
2676
2677 /**
2678 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2679 * @adapter: board private structure
2680 *
2681 * If this function returns with an error, then it's possible one or
2682 * more of the rings is populated (while the rest are not). It is the
2683 * callers duty to clean those orphaned rings.
2684 *
2685 * Return 0 on success, negative on failure
2686 **/
2687
2688 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2689 {
2690 int i, err = 0;
2691
2692 for (i = 0; i < adapter->num_rx_queues; i++) {
2693 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2694 if (err) {
2695 DPRINTK(PROBE, ERR,
2696 "Allocation for Rx Queue %u failed\n", i);
2697 break;
2698 }
2699 }
2700
2701 return err;
2702 }
2703
2704 /**
2705 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2706 * @netdev: network interface device structure
2707 * @new_mtu: new value for maximum frame size
2708 *
2709 * Returns 0 on success, negative on failure
2710 **/
2711 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2712 {
2713 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2714 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2715
2716 if ((max_frame < (ETH_ZLEN + ETH_FCS_LEN)) ||
2717 (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
2718 return -EINVAL;
2719
2720 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
2721 netdev->mtu, new_mtu);
2722 /* must set new MTU before calling down or up */
2723 netdev->mtu = new_mtu;
2724
2725 if (netif_running(netdev))
2726 ixgbe_reinit_locked(adapter);
2727
2728 return 0;
2729 }
2730
2731 /**
2732 * ixgbe_open - Called when a network interface is made active
2733 * @netdev: network interface device structure
2734 *
2735 * Returns 0 on success, negative value on failure
2736 *
2737 * The open entry point is called when a network interface is made
2738 * active by the system (IFF_UP). At this point all resources needed
2739 * for transmit and receive operations are allocated, the interrupt
2740 * handler is registered with the OS, the watchdog timer is started,
2741 * and the stack is notified that the interface is ready.
2742 **/
2743 static int ixgbe_open(struct net_device *netdev)
2744 {
2745 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2746 int err;
2747
2748 /* disallow open during test */
2749 if (test_bit(__IXGBE_TESTING, &adapter->state))
2750 return -EBUSY;
2751
2752 /* allocate transmit descriptors */
2753 err = ixgbe_setup_all_tx_resources(adapter);
2754 if (err)
2755 goto err_setup_tx;
2756
2757 /* allocate receive descriptors */
2758 err = ixgbe_setup_all_rx_resources(adapter);
2759 if (err)
2760 goto err_setup_rx;
2761
2762 ixgbe_configure(adapter);
2763
2764 err = ixgbe_request_irq(adapter);
2765 if (err)
2766 goto err_req_irq;
2767
2768 err = ixgbe_up_complete(adapter);
2769 if (err)
2770 goto err_up;
2771
2772 netif_tx_start_all_queues(netdev);
2773
2774 return 0;
2775
2776 err_up:
2777 ixgbe_release_hw_control(adapter);
2778 ixgbe_free_irq(adapter);
2779 err_req_irq:
2780 ixgbe_free_all_rx_resources(adapter);
2781 err_setup_rx:
2782 ixgbe_free_all_tx_resources(adapter);
2783 err_setup_tx:
2784 ixgbe_reset(adapter);
2785
2786 return err;
2787 }
2788
2789 /**
2790 * ixgbe_close - Disables a network interface
2791 * @netdev: network interface device structure
2792 *
2793 * Returns 0, this is not allowed to fail
2794 *
2795 * The close entry point is called when an interface is de-activated
2796 * by the OS. The hardware is still under the drivers control, but
2797 * needs to be disabled. A global MAC reset is issued to stop the
2798 * hardware, and all transmit and receive resources are freed.
2799 **/
2800 static int ixgbe_close(struct net_device *netdev)
2801 {
2802 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2803
2804 ixgbe_down(adapter);
2805 ixgbe_free_irq(adapter);
2806
2807 ixgbe_free_all_tx_resources(adapter);
2808 ixgbe_free_all_rx_resources(adapter);
2809
2810 ixgbe_release_hw_control(adapter);
2811
2812 return 0;
2813 }
2814
2815 /**
2816 * ixgbe_update_stats - Update the board statistics counters.
2817 * @adapter: board private structure
2818 **/
2819 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
2820 {
2821 struct ixgbe_hw *hw = &adapter->hw;
2822 u64 total_mpc = 0;
2823 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
2824
2825 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2826 for (i = 0; i < 8; i++) {
2827 /* for packet buffers not used, the register should read 0 */
2828 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2829 missed_rx += mpc;
2830 adapter->stats.mpc[i] += mpc;
2831 total_mpc += adapter->stats.mpc[i];
2832 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2833 }
2834 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2835 /* work around hardware counting issue */
2836 adapter->stats.gprc -= missed_rx;
2837
2838 /* 82598 hardware only has a 32 bit counter in the high register */
2839 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2840 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2841 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2842 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2843 adapter->stats.bprc += bprc;
2844 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2845 adapter->stats.mprc -= bprc;
2846 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2847 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2848 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2849 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2850 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2851 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2852 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2853 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2854 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2855 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2856 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2857 adapter->stats.lxontxc += lxon;
2858 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2859 adapter->stats.lxofftxc += lxoff;
2860 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2861 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2862 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2863 /*
2864 * 82598 errata - tx of flow control packets is included in tx counters
2865 */
2866 xon_off_tot = lxon + lxoff;
2867 adapter->stats.gptc -= xon_off_tot;
2868 adapter->stats.mptc -= xon_off_tot;
2869 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
2870 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2871 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2872 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2873 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2874 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2875 adapter->stats.ptc64 -= xon_off_tot;
2876 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2877 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2878 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2879 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2880 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2881 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2882
2883 /* Fill out the OS statistics structure */
2884 adapter->net_stats.multicast = adapter->stats.mprc;
2885
2886 /* Rx Errors */
2887 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
2888 adapter->stats.rlec;
2889 adapter->net_stats.rx_dropped = 0;
2890 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2891 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
2892 adapter->net_stats.rx_missed_errors = total_mpc;
2893 }
2894
2895 /**
2896 * ixgbe_watchdog - Timer Call-back
2897 * @data: pointer to adapter cast into an unsigned long
2898 **/
2899 static void ixgbe_watchdog(unsigned long data)
2900 {
2901 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2902 struct net_device *netdev = adapter->netdev;
2903 bool link_up;
2904 u32 link_speed = 0;
2905
2906 adapter->hw.mac.ops.check_link(&adapter->hw, &(link_speed), &link_up);
2907
2908 if (link_up) {
2909 if (!netif_carrier_ok(netdev)) {
2910 u32 frctl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2911 u32 rmcs = IXGBE_READ_REG(&adapter->hw, IXGBE_RMCS);
2912 #define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
2913 #define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
2914 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
2915 "Flow Control: %s\n",
2916 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
2917 "10 Gbps" :
2918 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
2919 "1 Gbps" : "unknown speed")),
2920 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
2921 (FLOW_RX ? "RX" :
2922 (FLOW_TX ? "TX" : "None"))));
2923
2924 netif_carrier_on(netdev);
2925 netif_tx_wake_all_queues(netdev);
2926 } else {
2927 /* Force detection of hung controller */
2928 adapter->detect_tx_hung = true;
2929 }
2930 } else {
2931 if (netif_carrier_ok(netdev)) {
2932 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2933 netif_carrier_off(netdev);
2934 netif_tx_stop_all_queues(netdev);
2935 }
2936 }
2937
2938 ixgbe_update_stats(adapter);
2939
2940 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2941 /* Cause software interrupt to ensure rx rings are cleaned */
2942 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2943 u32 eics =
2944 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
2945 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, eics);
2946 } else {
2947 /* for legacy and MSI interrupts don't set any bits that
2948 * are enabled for EIAM, because this operation would
2949 * set *both* EIMS and EICS for any bit in EIAM */
2950 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
2951 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
2952 }
2953 /* Reset the timer */
2954 mod_timer(&adapter->watchdog_timer,
2955 round_jiffies(jiffies + 2 * HZ));
2956 }
2957 }
2958
2959 static int ixgbe_tso(struct ixgbe_adapter *adapter,
2960 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
2961 u32 tx_flags, u8 *hdr_len)
2962 {
2963 struct ixgbe_adv_tx_context_desc *context_desc;
2964 unsigned int i;
2965 int err;
2966 struct ixgbe_tx_buffer *tx_buffer_info;
2967 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2968 u32 mss_l4len_idx = 0, l4len;
2969
2970 if (skb_is_gso(skb)) {
2971 if (skb_header_cloned(skb)) {
2972 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2973 if (err)
2974 return err;
2975 }
2976 l4len = tcp_hdrlen(skb);
2977 *hdr_len += l4len;
2978
2979 if (skb->protocol == htons(ETH_P_IP)) {
2980 struct iphdr *iph = ip_hdr(skb);
2981 iph->tot_len = 0;
2982 iph->check = 0;
2983 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2984 iph->daddr, 0,
2985 IPPROTO_TCP,
2986 0);
2987 adapter->hw_tso_ctxt++;
2988 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2989 ipv6_hdr(skb)->payload_len = 0;
2990 tcp_hdr(skb)->check =
2991 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2992 &ipv6_hdr(skb)->daddr,
2993 0, IPPROTO_TCP, 0);
2994 adapter->hw_tso6_ctxt++;
2995 }
2996
2997 i = tx_ring->next_to_use;
2998
2999 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3000 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3001
3002 /* VLAN MACLEN IPLEN */
3003 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3004 vlan_macip_lens |=
3005 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3006 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3007 IXGBE_ADVTXD_MACLEN_SHIFT);
3008 *hdr_len += skb_network_offset(skb);
3009 vlan_macip_lens |=
3010 (skb_transport_header(skb) - skb_network_header(skb));
3011 *hdr_len +=
3012 (skb_transport_header(skb) - skb_network_header(skb));
3013 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3014 context_desc->seqnum_seed = 0;
3015
3016 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3017 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3018 IXGBE_ADVTXD_DTYP_CTXT);
3019
3020 if (skb->protocol == htons(ETH_P_IP))
3021 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3022 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3023 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3024
3025 /* MSS L4LEN IDX */
3026 mss_l4len_idx |=
3027 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3028 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3029 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3030
3031 tx_buffer_info->time_stamp = jiffies;
3032 tx_buffer_info->next_to_watch = i;
3033
3034 i++;
3035 if (i == tx_ring->count)
3036 i = 0;
3037 tx_ring->next_to_use = i;
3038
3039 return true;
3040 }
3041 return false;
3042 }
3043
3044 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3045 struct ixgbe_ring *tx_ring,
3046 struct sk_buff *skb, u32 tx_flags)
3047 {
3048 struct ixgbe_adv_tx_context_desc *context_desc;
3049 unsigned int i;
3050 struct ixgbe_tx_buffer *tx_buffer_info;
3051 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3052
3053 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3054 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3055 i = tx_ring->next_to_use;
3056 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3057 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3058
3059 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3060 vlan_macip_lens |=
3061 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3062 vlan_macip_lens |= (skb_network_offset(skb) <<
3063 IXGBE_ADVTXD_MACLEN_SHIFT);
3064 if (skb->ip_summed == CHECKSUM_PARTIAL)
3065 vlan_macip_lens |= (skb_transport_header(skb) -
3066 skb_network_header(skb));
3067
3068 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3069 context_desc->seqnum_seed = 0;
3070
3071 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3072 IXGBE_ADVTXD_DTYP_CTXT);
3073
3074 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3075 switch (skb->protocol) {
3076 case __constant_htons(ETH_P_IP):
3077 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3078 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3079 type_tucmd_mlhl |=
3080 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3081 break;
3082
3083 case __constant_htons(ETH_P_IPV6):
3084 /* XXX what about other V6 headers?? */
3085 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3086 type_tucmd_mlhl |=
3087 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3088 break;
3089
3090 default:
3091 if (unlikely(net_ratelimit())) {
3092 DPRINTK(PROBE, WARNING,
3093 "partial checksum but proto=%x!\n",
3094 skb->protocol);
3095 }
3096 break;
3097 }
3098 }
3099
3100 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3101 context_desc->mss_l4len_idx = 0;
3102
3103 tx_buffer_info->time_stamp = jiffies;
3104 tx_buffer_info->next_to_watch = i;
3105 adapter->hw_csum_tx_good++;
3106 i++;
3107 if (i == tx_ring->count)
3108 i = 0;
3109 tx_ring->next_to_use = i;
3110
3111 return true;
3112 }
3113 return false;
3114 }
3115
3116 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3117 struct ixgbe_ring *tx_ring,
3118 struct sk_buff *skb, unsigned int first)
3119 {
3120 struct ixgbe_tx_buffer *tx_buffer_info;
3121 unsigned int len = skb->len;
3122 unsigned int offset = 0, size, count = 0, i;
3123 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3124 unsigned int f;
3125
3126 len -= skb->data_len;
3127
3128 i = tx_ring->next_to_use;
3129
3130 while (len) {
3131 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3132 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3133
3134 tx_buffer_info->length = size;
3135 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3136 skb->data + offset,
3137 size, PCI_DMA_TODEVICE);
3138 tx_buffer_info->time_stamp = jiffies;
3139 tx_buffer_info->next_to_watch = i;
3140
3141 len -= size;
3142 offset += size;
3143 count++;
3144 i++;
3145 if (i == tx_ring->count)
3146 i = 0;
3147 }
3148
3149 for (f = 0; f < nr_frags; f++) {
3150 struct skb_frag_struct *frag;
3151
3152 frag = &skb_shinfo(skb)->frags[f];
3153 len = frag->size;
3154 offset = frag->page_offset;
3155
3156 while (len) {
3157 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3158 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3159
3160 tx_buffer_info->length = size;
3161 tx_buffer_info->dma = pci_map_page(adapter->pdev,
3162 frag->page,
3163 offset,
3164 size, PCI_DMA_TODEVICE);
3165 tx_buffer_info->time_stamp = jiffies;
3166 tx_buffer_info->next_to_watch = i;
3167
3168 len -= size;
3169 offset += size;
3170 count++;
3171 i++;
3172 if (i == tx_ring->count)
3173 i = 0;
3174 }
3175 }
3176 if (i == 0)
3177 i = tx_ring->count - 1;
3178 else
3179 i = i - 1;
3180 tx_ring->tx_buffer_info[i].skb = skb;
3181 tx_ring->tx_buffer_info[first].next_to_watch = i;
3182
3183 return count;
3184 }
3185
3186 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3187 struct ixgbe_ring *tx_ring,
3188 int tx_flags, int count, u32 paylen, u8 hdr_len)
3189 {
3190 union ixgbe_adv_tx_desc *tx_desc = NULL;
3191 struct ixgbe_tx_buffer *tx_buffer_info;
3192 u32 olinfo_status = 0, cmd_type_len = 0;
3193 unsigned int i;
3194 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3195
3196 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3197
3198 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3199
3200 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3201 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3202
3203 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3204 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3205
3206 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3207 IXGBE_ADVTXD_POPTS_SHIFT;
3208
3209 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3210 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3211 IXGBE_ADVTXD_POPTS_SHIFT;
3212
3213 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3214 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3215 IXGBE_ADVTXD_POPTS_SHIFT;
3216
3217 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3218
3219 i = tx_ring->next_to_use;
3220 while (count--) {
3221 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3222 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3223 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3224 tx_desc->read.cmd_type_len =
3225 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3226 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3227
3228 i++;
3229 if (i == tx_ring->count)
3230 i = 0;
3231 }
3232
3233 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3234
3235 /*
3236 * Force memory writes to complete before letting h/w
3237 * know there are new descriptors to fetch. (Only
3238 * applicable for weak-ordered memory model archs,
3239 * such as IA-64).
3240 */
3241 wmb();
3242
3243 tx_ring->next_to_use = i;
3244 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3245 }
3246
3247 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3248 struct ixgbe_ring *tx_ring, int size)
3249 {
3250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3251
3252 netif_stop_subqueue(netdev, tx_ring->queue_index);
3253 /* Herbert's original patch had:
3254 * smp_mb__after_netif_stop_queue();
3255 * but since that doesn't exist yet, just open code it. */
3256 smp_mb();
3257
3258 /* We need to check again in a case another CPU has just
3259 * made room available. */
3260 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3261 return -EBUSY;
3262
3263 /* A reprieve! - use start_queue because it doesn't call schedule */
3264 netif_wake_subqueue(netdev, tx_ring->queue_index);
3265 ++adapter->restart_queue;
3266 return 0;
3267 }
3268
3269 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3270 struct ixgbe_ring *tx_ring, int size)
3271 {
3272 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3273 return 0;
3274 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3275 }
3276
3277
3278 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3279 {
3280 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3281 struct ixgbe_ring *tx_ring;
3282 unsigned int len = skb->len;
3283 unsigned int first;
3284 unsigned int tx_flags = 0;
3285 u8 hdr_len = 0;
3286 int r_idx = 0, tso;
3287 unsigned int mss = 0;
3288 int count = 0;
3289 unsigned int f;
3290 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3291 len -= skb->data_len;
3292 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
3293 tx_ring = &adapter->tx_ring[r_idx];
3294
3295
3296 if (skb->len <= 0) {
3297 dev_kfree_skb(skb);
3298 return NETDEV_TX_OK;
3299 }
3300 mss = skb_shinfo(skb)->gso_size;
3301
3302 if (mss)
3303 count++;
3304 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3305 count++;
3306
3307 count += TXD_USE_COUNT(len);
3308 for (f = 0; f < nr_frags; f++)
3309 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3310
3311 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
3312 adapter->tx_busy++;
3313 return NETDEV_TX_BUSY;
3314 }
3315 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3316 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3317 tx_flags |= (vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT);
3318 }
3319
3320 if (skb->protocol == htons(ETH_P_IP))
3321 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3322 first = tx_ring->next_to_use;
3323 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3324 if (tso < 0) {
3325 dev_kfree_skb_any(skb);
3326 return NETDEV_TX_OK;
3327 }
3328
3329 if (tso)
3330 tx_flags |= IXGBE_TX_FLAGS_TSO;
3331 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3332 (skb->ip_summed == CHECKSUM_PARTIAL))
3333 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3334
3335 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3336 ixgbe_tx_map(adapter, tx_ring, skb, first),
3337 skb->len, hdr_len);
3338
3339 netdev->trans_start = jiffies;
3340
3341 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
3342
3343 return NETDEV_TX_OK;
3344 }
3345
3346 /**
3347 * ixgbe_get_stats - Get System Network Statistics
3348 * @netdev: network interface device structure
3349 *
3350 * Returns the address of the device statistics structure.
3351 * The statistics are actually updated from the timer callback.
3352 **/
3353 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3354 {
3355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3356
3357 /* only return the current stats */
3358 return &adapter->net_stats;
3359 }
3360
3361 /**
3362 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3363 * @netdev: network interface device structure
3364 * @p: pointer to an address structure
3365 *
3366 * Returns 0 on success, negative on failure
3367 **/
3368 static int ixgbe_set_mac(struct net_device *netdev, void *p)
3369 {
3370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3371 struct sockaddr *addr = p;
3372
3373 if (!is_valid_ether_addr(addr->sa_data))
3374 return -EADDRNOTAVAIL;
3375
3376 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3377 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3378
3379 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
3380
3381 return 0;
3382 }
3383
3384 #ifdef CONFIG_NET_POLL_CONTROLLER
3385 /*
3386 * Polling 'interrupt' - used by things like netconsole to send skbs
3387 * without having to re-enable interrupts. It's not called while
3388 * the interrupt routine is executing.
3389 */
3390 static void ixgbe_netpoll(struct net_device *netdev)
3391 {
3392 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3393
3394 disable_irq(adapter->pdev->irq);
3395 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3396 ixgbe_intr(adapter->pdev->irq, netdev);
3397 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3398 enable_irq(adapter->pdev->irq);
3399 }
3400 #endif
3401
3402 /**
3403 * ixgbe_napi_add_all - prep napi structs for use
3404 * @adapter: private struct
3405 * helper function to napi_add each possible q_vector->napi
3406 */
3407 static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3408 {
3409 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3410 int (*poll)(struct napi_struct *, int);
3411
3412 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3413 poll = &ixgbe_clean_rxonly;
3414 } else {
3415 poll = &ixgbe_poll;
3416 /* only one q_vector for legacy modes */
3417 q_vectors = 1;
3418 }
3419
3420 for (i = 0; i < q_vectors; i++) {
3421 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
3422 netif_napi_add(adapter->netdev, &q_vector->napi,
3423 (*poll), 64);
3424 }
3425 }
3426
3427 /**
3428 * ixgbe_probe - Device Initialization Routine
3429 * @pdev: PCI device information struct
3430 * @ent: entry in ixgbe_pci_tbl
3431 *
3432 * Returns 0 on success, negative on failure
3433 *
3434 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3435 * The OS initialization, configuring of the adapter private structure,
3436 * and a hardware reset occur.
3437 **/
3438 static int __devinit ixgbe_probe(struct pci_dev *pdev,
3439 const struct pci_device_id *ent)
3440 {
3441 struct net_device *netdev;
3442 struct ixgbe_adapter *adapter = NULL;
3443 struct ixgbe_hw *hw;
3444 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3445 unsigned long mmio_start, mmio_len;
3446 static int cards_found;
3447 int i, err, pci_using_dac;
3448 u16 link_status, link_speed, link_width;
3449 u32 part_num;
3450
3451 err = pci_enable_device(pdev);
3452 if (err)
3453 return err;
3454
3455 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3456 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3457 pci_using_dac = 1;
3458 } else {
3459 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3460 if (err) {
3461 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3462 if (err) {
3463 dev_err(&pdev->dev, "No usable DMA "
3464 "configuration, aborting\n");
3465 goto err_dma;
3466 }
3467 }
3468 pci_using_dac = 0;
3469 }
3470
3471 err = pci_request_regions(pdev, ixgbe_driver_name);
3472 if (err) {
3473 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3474 goto err_pci_reg;
3475 }
3476
3477 pci_set_master(pdev);
3478 pci_save_state(pdev);
3479
3480 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
3481 if (!netdev) {
3482 err = -ENOMEM;
3483 goto err_alloc_etherdev;
3484 }
3485
3486 SET_NETDEV_DEV(netdev, &pdev->dev);
3487
3488 pci_set_drvdata(pdev, netdev);
3489 adapter = netdev_priv(netdev);
3490
3491 adapter->netdev = netdev;
3492 adapter->pdev = pdev;
3493 hw = &adapter->hw;
3494 hw->back = adapter;
3495 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3496
3497 mmio_start = pci_resource_start(pdev, 0);
3498 mmio_len = pci_resource_len(pdev, 0);
3499
3500 hw->hw_addr = ioremap(mmio_start, mmio_len);
3501 if (!hw->hw_addr) {
3502 err = -EIO;
3503 goto err_ioremap;
3504 }
3505
3506 for (i = 1; i <= 5; i++) {
3507 if (pci_resource_len(pdev, i) == 0)
3508 continue;
3509 }
3510
3511 netdev->open = &ixgbe_open;
3512 netdev->stop = &ixgbe_close;
3513 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3514 netdev->get_stats = &ixgbe_get_stats;
3515 netdev->set_rx_mode = &ixgbe_set_rx_mode;
3516 netdev->set_multicast_list = &ixgbe_set_rx_mode;
3517 netdev->set_mac_address = &ixgbe_set_mac;
3518 netdev->change_mtu = &ixgbe_change_mtu;
3519 ixgbe_set_ethtool_ops(netdev);
3520 netdev->tx_timeout = &ixgbe_tx_timeout;
3521 netdev->watchdog_timeo = 5 * HZ;
3522 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3523 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3524 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3525 #ifdef CONFIG_NET_POLL_CONTROLLER
3526 netdev->poll_controller = ixgbe_netpoll;
3527 #endif
3528 strcpy(netdev->name, pci_name(pdev));
3529
3530 netdev->mem_start = mmio_start;
3531 netdev->mem_end = mmio_start + mmio_len;
3532
3533 adapter->bd_number = cards_found;
3534
3535 /* PCI config space info */
3536 hw->vendor_id = pdev->vendor;
3537 hw->device_id = pdev->device;
3538 hw->revision_id = pdev->revision;
3539 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3540 hw->subsystem_device_id = pdev->subsystem_device;
3541
3542 /* Setup hw api */
3543 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
3544 hw->mac.type = ii->mac;
3545
3546 err = ii->get_invariants(hw);
3547 if (err)
3548 goto err_hw_init;
3549
3550 /* setup the private structure */
3551 err = ixgbe_sw_init(adapter);
3552 if (err)
3553 goto err_sw_init;
3554
3555 netdev->features = NETIF_F_SG |
3556 NETIF_F_HW_CSUM |
3557 NETIF_F_HW_VLAN_TX |
3558 NETIF_F_HW_VLAN_RX |
3559 NETIF_F_HW_VLAN_FILTER;
3560
3561 netdev->features |= NETIF_F_LRO;
3562 netdev->features |= NETIF_F_TSO;
3563 netdev->features |= NETIF_F_TSO6;
3564
3565 netdev->vlan_features |= NETIF_F_TSO;
3566 netdev->vlan_features |= NETIF_F_TSO6;
3567 netdev->vlan_features |= NETIF_F_HW_CSUM;
3568 netdev->vlan_features |= NETIF_F_SG;
3569
3570 if (pci_using_dac)
3571 netdev->features |= NETIF_F_HIGHDMA;
3572
3573 /* make sure the EEPROM is good */
3574 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
3575 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3576 err = -EIO;
3577 goto err_eeprom;
3578 }
3579
3580 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3581 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3582
3583 if (ixgbe_validate_mac_addr(netdev->dev_addr)) {
3584 err = -EIO;
3585 goto err_eeprom;
3586 }
3587
3588 init_timer(&adapter->watchdog_timer);
3589 adapter->watchdog_timer.function = &ixgbe_watchdog;
3590 adapter->watchdog_timer.data = (unsigned long)adapter;
3591
3592 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
3593
3594 err = ixgbe_init_interrupt_scheme(adapter);
3595 if (err)
3596 goto err_sw_init;
3597
3598 /* print bus type/speed/width info */
3599 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3600 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3601 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3602 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
3603 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3604 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3605 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3606 "Unknown"),
3607 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3608 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3609 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3610 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3611 "Unknown"),
3612 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3613 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
3614 ixgbe_read_part_num(hw, &part_num);
3615 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
3616 hw->mac.type, hw->phy.type,
3617 (part_num >> 8), (part_num & 0xff));
3618
3619 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3620 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
3621 "this card is not sufficient for optimal "
3622 "performance.\n");
3623 dev_warn(&pdev->dev, "For optimal performance a x8 "
3624 "PCI-Express slot is required.\n");
3625 }
3626
3627 /* reset the hardware with the new settings */
3628 ixgbe_start_hw(hw);
3629
3630 netif_carrier_off(netdev);
3631 netif_tx_stop_all_queues(netdev);
3632
3633 ixgbe_napi_add_all(adapter);
3634
3635 strcpy(netdev->name, "eth%d");
3636 err = register_netdev(netdev);
3637 if (err)
3638 goto err_register;
3639
3640 #ifdef CONFIG_DCA
3641 if (dca_add_requester(&pdev->dev) == 0) {
3642 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3643 /* always use CB2 mode, difference is masked
3644 * in the CB driver */
3645 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3646 ixgbe_setup_dca(adapter);
3647 }
3648 #endif
3649
3650 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3651 cards_found++;
3652 return 0;
3653
3654 err_register:
3655 ixgbe_release_hw_control(adapter);
3656 err_hw_init:
3657 err_sw_init:
3658 ixgbe_reset_interrupt_capability(adapter);
3659 err_eeprom:
3660 iounmap(hw->hw_addr);
3661 err_ioremap:
3662 free_netdev(netdev);
3663 err_alloc_etherdev:
3664 pci_release_regions(pdev);
3665 err_pci_reg:
3666 err_dma:
3667 pci_disable_device(pdev);
3668 return err;
3669 }
3670
3671 /**
3672 * ixgbe_remove - Device Removal Routine
3673 * @pdev: PCI device information struct
3674 *
3675 * ixgbe_remove is called by the PCI subsystem to alert the driver
3676 * that it should release a PCI device. The could be caused by a
3677 * Hot-Plug event, or because the driver is going to be removed from
3678 * memory.
3679 **/
3680 static void __devexit ixgbe_remove(struct pci_dev *pdev)
3681 {
3682 struct net_device *netdev = pci_get_drvdata(pdev);
3683 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3684
3685 set_bit(__IXGBE_DOWN, &adapter->state);
3686 del_timer_sync(&adapter->watchdog_timer);
3687
3688 flush_scheduled_work();
3689
3690 #ifdef CONFIG_DCA
3691 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3692 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
3693 dca_remove_requester(&pdev->dev);
3694 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
3695 }
3696
3697 #endif
3698 unregister_netdev(netdev);
3699
3700 ixgbe_reset_interrupt_capability(adapter);
3701
3702 ixgbe_release_hw_control(adapter);
3703
3704 iounmap(adapter->hw.hw_addr);
3705 pci_release_regions(pdev);
3706
3707 DPRINTK(PROBE, INFO, "complete\n");
3708 kfree(adapter->tx_ring);
3709 kfree(adapter->rx_ring);
3710
3711 free_netdev(netdev);
3712
3713 pci_disable_device(pdev);
3714 }
3715
3716 /**
3717 * ixgbe_io_error_detected - called when PCI error is detected
3718 * @pdev: Pointer to PCI device
3719 * @state: The current pci connection state
3720 *
3721 * This function is called after a PCI bus error affecting
3722 * this device has been detected.
3723 */
3724 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
3725 pci_channel_state_t state)
3726 {
3727 struct net_device *netdev = pci_get_drvdata(pdev);
3728 struct ixgbe_adapter *adapter = netdev->priv;
3729
3730 netif_device_detach(netdev);
3731
3732 if (netif_running(netdev))
3733 ixgbe_down(adapter);
3734 pci_disable_device(pdev);
3735
3736 /* Request a slot slot reset. */
3737 return PCI_ERS_RESULT_NEED_RESET;
3738 }
3739
3740 /**
3741 * ixgbe_io_slot_reset - called after the pci bus has been reset.
3742 * @pdev: Pointer to PCI device
3743 *
3744 * Restart the card from scratch, as if from a cold-boot.
3745 */
3746 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
3747 {
3748 struct net_device *netdev = pci_get_drvdata(pdev);
3749 struct ixgbe_adapter *adapter = netdev->priv;
3750
3751 if (pci_enable_device(pdev)) {
3752 DPRINTK(PROBE, ERR,
3753 "Cannot re-enable PCI device after reset.\n");
3754 return PCI_ERS_RESULT_DISCONNECT;
3755 }
3756 pci_set_master(pdev);
3757 pci_restore_state(pdev);
3758
3759 pci_enable_wake(pdev, PCI_D3hot, 0);
3760 pci_enable_wake(pdev, PCI_D3cold, 0);
3761
3762 ixgbe_reset(adapter);
3763
3764 return PCI_ERS_RESULT_RECOVERED;
3765 }
3766
3767 /**
3768 * ixgbe_io_resume - called when traffic can start flowing again.
3769 * @pdev: Pointer to PCI device
3770 *
3771 * This callback is called when the error recovery driver tells us that
3772 * its OK to resume normal operation.
3773 */
3774 static void ixgbe_io_resume(struct pci_dev *pdev)
3775 {
3776 struct net_device *netdev = pci_get_drvdata(pdev);
3777 struct ixgbe_adapter *adapter = netdev->priv;
3778
3779 if (netif_running(netdev)) {
3780 if (ixgbe_up(adapter)) {
3781 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
3782 return;
3783 }
3784 }
3785
3786 netif_device_attach(netdev);
3787
3788 }
3789
3790 static struct pci_error_handlers ixgbe_err_handler = {
3791 .error_detected = ixgbe_io_error_detected,
3792 .slot_reset = ixgbe_io_slot_reset,
3793 .resume = ixgbe_io_resume,
3794 };
3795
3796 static struct pci_driver ixgbe_driver = {
3797 .name = ixgbe_driver_name,
3798 .id_table = ixgbe_pci_tbl,
3799 .probe = ixgbe_probe,
3800 .remove = __devexit_p(ixgbe_remove),
3801 #ifdef CONFIG_PM
3802 .suspend = ixgbe_suspend,
3803 .resume = ixgbe_resume,
3804 #endif
3805 .shutdown = ixgbe_shutdown,
3806 .err_handler = &ixgbe_err_handler
3807 };
3808
3809 /**
3810 * ixgbe_init_module - Driver Registration Routine
3811 *
3812 * ixgbe_init_module is the first routine called when the driver is
3813 * loaded. All it does is register with the PCI subsystem.
3814 **/
3815 static int __init ixgbe_init_module(void)
3816 {
3817 int ret;
3818 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
3819 ixgbe_driver_string, ixgbe_driver_version);
3820
3821 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
3822
3823 #ifdef CONFIG_DCA
3824 dca_register_notify(&dca_notifier);
3825
3826 #endif
3827 ret = pci_register_driver(&ixgbe_driver);
3828 return ret;
3829 }
3830 module_init(ixgbe_init_module);
3831
3832 /**
3833 * ixgbe_exit_module - Driver Exit Cleanup Routine
3834 *
3835 * ixgbe_exit_module is called just before the driver is removed
3836 * from memory.
3837 **/
3838 static void __exit ixgbe_exit_module(void)
3839 {
3840 #ifdef CONFIG_DCA
3841 dca_unregister_notify(&dca_notifier);
3842 #endif
3843 pci_unregister_driver(&ixgbe_driver);
3844 }
3845
3846 #ifdef CONFIG_DCA
3847 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
3848 void *p)
3849 {
3850 int ret_val;
3851
3852 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
3853 __ixgbe_notify_dca);
3854
3855 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3856 }
3857 #endif /* CONFIG_DCA */
3858
3859 module_exit(ixgbe_exit_module);
3860
3861 /* ixgbe_main.c */
Support for the Chinese Samsung S3C2440 based development boards