2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
26 #include <asm/iommu.h>
27 #include <asm/amd_iommu_types.h>
28 #include <asm/amd_iommu.h>
30 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
32 #define EXIT_LOOP_COUNT 10000000
34 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
37 * general struct to manage commands send to an IOMMU
43 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
44 struct unity_map_entry
*e
);
46 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
47 static int iommu_has_npcache(struct amd_iommu
*iommu
)
49 return iommu
->cap
& IOMMU_CAP_NPCACHE
;
52 /****************************************************************************
54 * IOMMU command queuing functions
56 ****************************************************************************/
59 * Writes the command to the IOMMUs command buffer and informs the
60 * hardware about the new command. Must be called with iommu->lock held.
62 static int __iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
67 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
68 target
= (iommu
->cmd_buf
+ tail
);
69 memcpy_toio(target
, cmd
, sizeof(*cmd
));
70 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
71 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
74 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
80 * General queuing function for commands. Takes iommu->lock and calls
81 * __iommu_queue_command().
83 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
88 spin_lock_irqsave(&iommu
->lock
, flags
);
89 ret
= __iommu_queue_command(iommu
, cmd
);
90 spin_unlock_irqrestore(&iommu
->lock
, flags
);
96 * This function is called whenever we need to ensure that the IOMMU has
97 * completed execution of all commands we sent. It sends a
98 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
99 * us about that by writing a value to a physical address we pass with
102 static int iommu_completion_wait(struct amd_iommu
*iommu
)
105 struct iommu_cmd cmd
;
106 volatile u64 ready
= 0;
107 unsigned long ready_phys
= virt_to_phys(&ready
);
110 memset(&cmd
, 0, sizeof(cmd
));
111 cmd
.data
[0] = LOW_U32(ready_phys
) | CMD_COMPL_WAIT_STORE_MASK
;
112 cmd
.data
[1] = upper_32_bits(ready_phys
);
113 cmd
.data
[2] = 1; /* value written to 'ready' */
114 CMD_SET_TYPE(&cmd
, CMD_COMPL_WAIT
);
116 iommu
->need_sync
= 0;
118 ret
= iommu_queue_command(iommu
, &cmd
);
123 while (!ready
&& (i
< EXIT_LOOP_COUNT
)) {
128 if (unlikely((i
== EXIT_LOOP_COUNT
) && printk_ratelimit()))
129 printk(KERN_WARNING
"AMD IOMMU: Completion wait loop failed\n");
135 * Command send function for invalidating a device table entry
137 static int iommu_queue_inv_dev_entry(struct amd_iommu
*iommu
, u16 devid
)
139 struct iommu_cmd cmd
;
141 BUG_ON(iommu
== NULL
);
143 memset(&cmd
, 0, sizeof(cmd
));
144 CMD_SET_TYPE(&cmd
, CMD_INV_DEV_ENTRY
);
147 iommu
->need_sync
= 1;
149 return iommu_queue_command(iommu
, &cmd
);
153 * Generic command send function for invalidaing TLB entries
155 static int iommu_queue_inv_iommu_pages(struct amd_iommu
*iommu
,
156 u64 address
, u16 domid
, int pde
, int s
)
158 struct iommu_cmd cmd
;
160 memset(&cmd
, 0, sizeof(cmd
));
161 address
&= PAGE_MASK
;
162 CMD_SET_TYPE(&cmd
, CMD_INV_IOMMU_PAGES
);
163 cmd
.data
[1] |= domid
;
164 cmd
.data
[2] = LOW_U32(address
);
165 cmd
.data
[3] = upper_32_bits(address
);
166 if (s
) /* size bit - we flush more than one 4kb page */
167 cmd
.data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
168 if (pde
) /* PDE bit - we wan't flush everything not only the PTEs */
169 cmd
.data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
171 iommu
->need_sync
= 1;
173 return iommu_queue_command(iommu
, &cmd
);
177 * TLB invalidation function which is called from the mapping functions.
178 * It invalidates a single PTE if the range to flush is within a single
179 * page. Otherwise it flushes the whole TLB of the IOMMU.
181 static int iommu_flush_pages(struct amd_iommu
*iommu
, u16 domid
,
182 u64 address
, size_t size
)
185 unsigned pages
= iommu_num_pages(address
, size
);
187 address
&= PAGE_MASK
;
191 * If we have to flush more than one page, flush all
192 * TLB entries for this domain
194 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
198 iommu_queue_inv_iommu_pages(iommu
, address
, domid
, 0, s
);
203 /****************************************************************************
205 * The functions below are used the create the page table mappings for
206 * unity mapped regions.
208 ****************************************************************************/
211 * Generic mapping functions. It maps a physical address into a DMA
212 * address space. It allocates the page table pages if necessary.
213 * In the future it can be extended to a generic mapping function
214 * supporting all features of AMD IOMMU page tables like level skipping
215 * and full 64 bit address spaces.
217 static int iommu_map(struct protection_domain
*dom
,
218 unsigned long bus_addr
,
219 unsigned long phys_addr
,
222 u64 __pte
, *pte
, *page
;
224 bus_addr
= PAGE_ALIGN(bus_addr
);
225 phys_addr
= PAGE_ALIGN(bus_addr
);
227 /* only support 512GB address spaces for now */
228 if (bus_addr
> IOMMU_MAP_SIZE_L3
|| !(prot
& IOMMU_PROT_MASK
))
231 pte
= &dom
->pt_root
[IOMMU_PTE_L2_INDEX(bus_addr
)];
233 if (!IOMMU_PTE_PRESENT(*pte
)) {
234 page
= (u64
*)get_zeroed_page(GFP_KERNEL
);
237 *pte
= IOMMU_L2_PDE(virt_to_phys(page
));
240 pte
= IOMMU_PTE_PAGE(*pte
);
241 pte
= &pte
[IOMMU_PTE_L1_INDEX(bus_addr
)];
243 if (!IOMMU_PTE_PRESENT(*pte
)) {
244 page
= (u64
*)get_zeroed_page(GFP_KERNEL
);
247 *pte
= IOMMU_L1_PDE(virt_to_phys(page
));
250 pte
= IOMMU_PTE_PAGE(*pte
);
251 pte
= &pte
[IOMMU_PTE_L0_INDEX(bus_addr
)];
253 if (IOMMU_PTE_PRESENT(*pte
))
256 __pte
= phys_addr
| IOMMU_PTE_P
;
257 if (prot
& IOMMU_PROT_IR
)
258 __pte
|= IOMMU_PTE_IR
;
259 if (prot
& IOMMU_PROT_IW
)
260 __pte
|= IOMMU_PTE_IW
;
268 * This function checks if a specific unity mapping entry is needed for
269 * this specific IOMMU.
271 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
272 struct unity_map_entry
*entry
)
276 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
277 bdf
= amd_iommu_alias_table
[i
];
278 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
286 * Init the unity mappings for a specific IOMMU in the system
288 * Basically iterates over all unity mapping entries and applies them to
289 * the default domain DMA of that IOMMU if necessary.
291 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
293 struct unity_map_entry
*entry
;
296 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
297 if (!iommu_for_unity_map(iommu
, entry
))
299 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
308 * This function actually applies the mapping to the page table of the
311 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
312 struct unity_map_entry
*e
)
317 for (addr
= e
->address_start
; addr
< e
->address_end
;
319 ret
= iommu_map(&dma_dom
->domain
, addr
, addr
, e
->prot
);
323 * if unity mapping is in aperture range mark the page
324 * as allocated in the aperture
326 if (addr
< dma_dom
->aperture_size
)
327 __set_bit(addr
>> PAGE_SHIFT
, dma_dom
->bitmap
);
334 * Inits the unity mappings required for a specific device
336 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
339 struct unity_map_entry
*e
;
342 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
343 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
345 ret
= dma_ops_unity_map(dma_dom
, e
);
353 /****************************************************************************
355 * The next functions belong to the address allocator for the dma_ops
356 * interface functions. They work like the allocators in the other IOMMU
357 * drivers. Its basically a bitmap which marks the allocated pages in
358 * the aperture. Maybe it could be enhanced in the future to a more
359 * efficient allocator.
361 ****************************************************************************/
362 static unsigned long dma_mask_to_pages(unsigned long mask
)
364 return (mask
>> PAGE_SHIFT
) +
365 (PAGE_ALIGN(mask
& ~PAGE_MASK
) >> PAGE_SHIFT
);
369 * The address allocator core function.
371 * called with domain->lock held
373 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
374 struct dma_ops_domain
*dom
,
377 unsigned long limit
= dma_mask_to_pages(*dev
->dma_mask
);
378 unsigned long address
;
379 unsigned long size
= dom
->aperture_size
>> PAGE_SHIFT
;
380 unsigned long boundary_size
;
382 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
383 PAGE_SIZE
) >> PAGE_SHIFT
;
384 limit
= limit
< size
? limit
: size
;
386 if (dom
->next_bit
>= limit
)
389 address
= iommu_area_alloc(dom
->bitmap
, limit
, dom
->next_bit
, pages
,
390 0 , boundary_size
, 0);
392 address
= iommu_area_alloc(dom
->bitmap
, limit
, 0, pages
,
393 0, boundary_size
, 0);
395 if (likely(address
!= -1)) {
396 dom
->next_bit
= address
+ pages
;
397 address
<<= PAGE_SHIFT
;
399 address
= bad_dma_address
;
401 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
407 * The address free function.
409 * called with domain->lock held
411 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
412 unsigned long address
,
415 address
>>= PAGE_SHIFT
;
416 iommu_area_free(dom
->bitmap
, address
, pages
);
419 /****************************************************************************
421 * The next functions belong to the domain allocation. A domain is
422 * allocated for every IOMMU as the default domain. If device isolation
423 * is enabled, every device get its own domain. The most important thing
424 * about domains is the page table mapping the DMA address space they
427 ****************************************************************************/
429 static u16
domain_id_alloc(void)
434 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
435 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
437 if (id
> 0 && id
< MAX_DOMAIN_ID
)
438 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
441 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
447 * Used to reserve address ranges in the aperture (e.g. for exclusion
450 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
451 unsigned long start_page
,
454 unsigned int last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
456 if (start_page
+ pages
> last_page
)
457 pages
= last_page
- start_page
;
459 set_bit_string(dom
->bitmap
, start_page
, pages
);
462 static void dma_ops_free_pagetable(struct dma_ops_domain
*dma_dom
)
467 p1
= dma_dom
->domain
.pt_root
;
472 for (i
= 0; i
< 512; ++i
) {
473 if (!IOMMU_PTE_PRESENT(p1
[i
]))
476 p2
= IOMMU_PTE_PAGE(p1
[i
]);
477 for (j
= 0; j
< 512; ++i
) {
478 if (!IOMMU_PTE_PRESENT(p2
[j
]))
480 p3
= IOMMU_PTE_PAGE(p2
[j
]);
481 free_page((unsigned long)p3
);
484 free_page((unsigned long)p2
);
487 free_page((unsigned long)p1
);
491 * Free a domain, only used if something went wrong in the
492 * allocation path and we need to free an already allocated page table
494 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
499 dma_ops_free_pagetable(dom
);
501 kfree(dom
->pte_pages
);
509 * Allocates a new protection domain usable for the dma_ops functions.
510 * It also intializes the page table and the address allocator data
511 * structures required for the dma_ops interface
513 static struct dma_ops_domain
*dma_ops_domain_alloc(struct amd_iommu
*iommu
,
516 struct dma_ops_domain
*dma_dom
;
517 unsigned i
, num_pte_pages
;
522 * Currently the DMA aperture must be between 32 MB and 1GB in size
524 if ((order
< 25) || (order
> 30))
527 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
531 spin_lock_init(&dma_dom
->domain
.lock
);
533 dma_dom
->domain
.id
= domain_id_alloc();
534 if (dma_dom
->domain
.id
== 0)
536 dma_dom
->domain
.mode
= PAGE_MODE_3_LEVEL
;
537 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
538 dma_dom
->domain
.priv
= dma_dom
;
539 if (!dma_dom
->domain
.pt_root
)
541 dma_dom
->aperture_size
= (1ULL << order
);
542 dma_dom
->bitmap
= kzalloc(dma_dom
->aperture_size
/ (PAGE_SIZE
* 8),
544 if (!dma_dom
->bitmap
)
547 * mark the first page as allocated so we never return 0 as
548 * a valid dma-address. So we can use 0 as error value
550 dma_dom
->bitmap
[0] = 1;
551 dma_dom
->next_bit
= 0;
553 /* Intialize the exclusion range if necessary */
554 if (iommu
->exclusion_start
&&
555 iommu
->exclusion_start
< dma_dom
->aperture_size
) {
556 unsigned long startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
557 int pages
= iommu_num_pages(iommu
->exclusion_start
,
558 iommu
->exclusion_length
);
559 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
563 * At the last step, build the page tables so we don't need to
564 * allocate page table pages in the dma_ops mapping/unmapping
567 num_pte_pages
= dma_dom
->aperture_size
/ (PAGE_SIZE
* 512);
568 dma_dom
->pte_pages
= kzalloc(num_pte_pages
* sizeof(void *),
570 if (!dma_dom
->pte_pages
)
573 l2_pde
= (u64
*)get_zeroed_page(GFP_KERNEL
);
577 dma_dom
->domain
.pt_root
[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde
));
579 for (i
= 0; i
< num_pte_pages
; ++i
) {
580 dma_dom
->pte_pages
[i
] = (u64
*)get_zeroed_page(GFP_KERNEL
);
581 if (!dma_dom
->pte_pages
[i
])
583 address
= virt_to_phys(dma_dom
->pte_pages
[i
]);
584 l2_pde
[i
] = IOMMU_L1_PDE(address
);
590 dma_ops_domain_free(dma_dom
);
596 * Find out the protection domain structure for a given PCI device. This
597 * will give us the pointer to the page table root for example.
599 static struct protection_domain
*domain_for_device(u16 devid
)
601 struct protection_domain
*dom
;
604 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
605 dom
= amd_iommu_pd_table
[devid
];
606 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
612 * If a device is not yet associated with a domain, this function does
613 * assigns it visible for the hardware
615 static void set_device_domain(struct amd_iommu
*iommu
,
616 struct protection_domain
*domain
,
621 u64 pte_root
= virt_to_phys(domain
->pt_root
);
623 pte_root
|= (domain
->mode
& 0x07) << 9;
624 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| 2;
626 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
627 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
628 amd_iommu_dev_table
[devid
].data
[1] = pte_root
>> 32;
629 amd_iommu_dev_table
[devid
].data
[2] = domain
->id
;
631 amd_iommu_pd_table
[devid
] = domain
;
632 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
634 iommu_queue_inv_dev_entry(iommu
, devid
);
636 iommu
->need_sync
= 1;
639 /*****************************************************************************
641 * The next functions belong to the dma_ops mapping/unmapping code.
643 *****************************************************************************/
646 * In the dma_ops path we only have the struct device. This function
647 * finds the corresponding IOMMU, the protection domain and the
648 * requestor id for a given device.
649 * If the device is not yet associated with a domain this is also done
652 static int get_device_resources(struct device
*dev
,
653 struct amd_iommu
**iommu
,
654 struct protection_domain
**domain
,
657 struct dma_ops_domain
*dma_dom
;
658 struct pci_dev
*pcidev
;
661 BUG_ON(!dev
|| dev
->bus
!= &pci_bus_type
|| !dev
->dma_mask
);
663 pcidev
= to_pci_dev(dev
);
664 _bdf
= calc_devid(pcidev
->bus
->number
, pcidev
->devfn
);
666 /* device not translated by any IOMMU in the system? */
667 if (_bdf
> amd_iommu_last_bdf
) {
674 *bdf
= amd_iommu_alias_table
[_bdf
];
676 *iommu
= amd_iommu_rlookup_table
[*bdf
];
679 dma_dom
= (*iommu
)->default_dom
;
680 *domain
= domain_for_device(*bdf
);
681 if (*domain
== NULL
) {
682 *domain
= &dma_dom
->domain
;
683 set_device_domain(*iommu
, *domain
, *bdf
);
684 printk(KERN_INFO
"AMD IOMMU: Using protection domain %d for "
685 "device ", (*domain
)->id
);
686 print_devid(_bdf
, 1);
693 * This is the generic map function. It maps one 4kb page at paddr to
694 * the given address in the DMA address space for the domain.
696 static dma_addr_t
dma_ops_domain_map(struct amd_iommu
*iommu
,
697 struct dma_ops_domain
*dom
,
698 unsigned long address
,
704 WARN_ON(address
> dom
->aperture_size
);
708 pte
= dom
->pte_pages
[IOMMU_PTE_L1_INDEX(address
)];
709 pte
+= IOMMU_PTE_L0_INDEX(address
);
711 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
713 if (direction
== DMA_TO_DEVICE
)
714 __pte
|= IOMMU_PTE_IR
;
715 else if (direction
== DMA_FROM_DEVICE
)
716 __pte
|= IOMMU_PTE_IW
;
717 else if (direction
== DMA_BIDIRECTIONAL
)
718 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
724 return (dma_addr_t
)address
;
728 * The generic unmapping function for on page in the DMA address space.
730 static void dma_ops_domain_unmap(struct amd_iommu
*iommu
,
731 struct dma_ops_domain
*dom
,
732 unsigned long address
)
736 if (address
>= dom
->aperture_size
)
739 WARN_ON(address
& 0xfffULL
|| address
> dom
->aperture_size
);
741 pte
= dom
->pte_pages
[IOMMU_PTE_L1_INDEX(address
)];
742 pte
+= IOMMU_PTE_L0_INDEX(address
);
750 * This function contains common code for mapping of a physically
751 * contiguous memory region into DMA address space. It is uses by all
752 * mapping functions provided by this IOMMU driver.
753 * Must be called with the domain lock held.
755 static dma_addr_t
__map_single(struct device
*dev
,
756 struct amd_iommu
*iommu
,
757 struct dma_ops_domain
*dma_dom
,
762 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
763 dma_addr_t address
, start
;
767 pages
= iommu_num_pages(paddr
, size
);
770 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
);
771 if (unlikely(address
== bad_dma_address
))
775 for (i
= 0; i
< pages
; ++i
) {
776 dma_ops_domain_map(iommu
, dma_dom
, start
, paddr
, dir
);
787 * Does the reverse of the __map_single function. Must be called with
788 * the domain lock held too
790 static void __unmap_single(struct amd_iommu
*iommu
,
791 struct dma_ops_domain
*dma_dom
,
799 if ((dma_addr
== 0) || (dma_addr
+ size
> dma_dom
->aperture_size
))
802 pages
= iommu_num_pages(dma_addr
, size
);
803 dma_addr
&= PAGE_MASK
;
806 for (i
= 0; i
< pages
; ++i
) {
807 dma_ops_domain_unmap(iommu
, dma_dom
, start
);
811 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
815 * The exported map_single function for dma_ops.
817 static dma_addr_t
map_single(struct device
*dev
, phys_addr_t paddr
,
818 size_t size
, int dir
)
821 struct amd_iommu
*iommu
;
822 struct protection_domain
*domain
;
826 get_device_resources(dev
, &iommu
, &domain
, &devid
);
828 if (iommu
== NULL
|| domain
== NULL
)
829 /* device not handled by any AMD IOMMU */
830 return (dma_addr_t
)paddr
;
832 spin_lock_irqsave(&domain
->lock
, flags
);
833 addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
, size
, dir
);
834 if (addr
== bad_dma_address
)
837 if (iommu_has_npcache(iommu
))
838 iommu_flush_pages(iommu
, domain
->id
, addr
, size
);
840 if (iommu
->need_sync
)
841 iommu_completion_wait(iommu
);
844 spin_unlock_irqrestore(&domain
->lock
, flags
);
850 * The exported unmap_single function for dma_ops.
852 static void unmap_single(struct device
*dev
, dma_addr_t dma_addr
,
853 size_t size
, int dir
)
856 struct amd_iommu
*iommu
;
857 struct protection_domain
*domain
;
860 if (!get_device_resources(dev
, &iommu
, &domain
, &devid
))
861 /* device not handled by any AMD IOMMU */
864 spin_lock_irqsave(&domain
->lock
, flags
);
866 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, dir
);
868 iommu_flush_pages(iommu
, domain
->id
, dma_addr
, size
);
870 if (iommu
->need_sync
)
871 iommu_completion_wait(iommu
);
873 spin_unlock_irqrestore(&domain
->lock
, flags
);
877 * This is a special map_sg function which is used if we should map a
878 * device which is not handled by an AMD IOMMU in the system.
880 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
883 struct scatterlist
*s
;
886 for_each_sg(sglist
, s
, nelems
, i
) {
887 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
888 s
->dma_length
= s
->length
;
895 * The exported map_sg function for dma_ops (handles scatter-gather
898 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
902 struct amd_iommu
*iommu
;
903 struct protection_domain
*domain
;
906 struct scatterlist
*s
;
908 int mapped_elems
= 0;
910 get_device_resources(dev
, &iommu
, &domain
, &devid
);
912 if (!iommu
|| !domain
)
913 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
915 spin_lock_irqsave(&domain
->lock
, flags
);
917 for_each_sg(sglist
, s
, nelems
, i
) {
920 s
->dma_address
= __map_single(dev
, iommu
, domain
->priv
,
921 paddr
, s
->length
, dir
);
923 if (s
->dma_address
) {
924 s
->dma_length
= s
->length
;
928 if (iommu_has_npcache(iommu
))
929 iommu_flush_pages(iommu
, domain
->id
, s
->dma_address
,
933 if (iommu
->need_sync
)
934 iommu_completion_wait(iommu
);
937 spin_unlock_irqrestore(&domain
->lock
, flags
);
941 for_each_sg(sglist
, s
, mapped_elems
, i
) {
943 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
945 s
->dma_address
= s
->dma_length
= 0;
954 * The exported map_sg function for dma_ops (handles scatter-gather
957 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
961 struct amd_iommu
*iommu
;
962 struct protection_domain
*domain
;
963 struct scatterlist
*s
;
967 if (!get_device_resources(dev
, &iommu
, &domain
, &devid
))
970 spin_lock_irqsave(&domain
->lock
, flags
);
972 for_each_sg(sglist
, s
, nelems
, i
) {
973 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
975 iommu_flush_pages(iommu
, domain
->id
, s
->dma_address
,
977 s
->dma_address
= s
->dma_length
= 0;
980 if (iommu
->need_sync
)
981 iommu_completion_wait(iommu
);
983 spin_unlock_irqrestore(&domain
->lock
, flags
);
987 * The exported alloc_coherent function for dma_ops.
989 static void *alloc_coherent(struct device
*dev
, size_t size
,
990 dma_addr_t
*dma_addr
, gfp_t flag
)
994 struct amd_iommu
*iommu
;
995 struct protection_domain
*domain
;
999 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
1003 memset(virt_addr
, 0, size
);
1004 paddr
= virt_to_phys(virt_addr
);
1006 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1008 if (!iommu
|| !domain
) {
1009 *dma_addr
= (dma_addr_t
)paddr
;
1013 spin_lock_irqsave(&domain
->lock
, flags
);
1015 *dma_addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
,
1016 size
, DMA_BIDIRECTIONAL
);
1018 if (*dma_addr
== bad_dma_address
) {
1019 free_pages((unsigned long)virt_addr
, get_order(size
));
1024 if (iommu_has_npcache(iommu
))
1025 iommu_flush_pages(iommu
, domain
->id
, *dma_addr
, size
);
1027 if (iommu
->need_sync
)
1028 iommu_completion_wait(iommu
);
1031 spin_unlock_irqrestore(&domain
->lock
, flags
);
1037 * The exported free_coherent function for dma_ops.
1038 * FIXME: fix the generic x86 DMA layer so that it actually calls that
1041 static void free_coherent(struct device
*dev
, size_t size
,
1042 void *virt_addr
, dma_addr_t dma_addr
)
1044 unsigned long flags
;
1045 struct amd_iommu
*iommu
;
1046 struct protection_domain
*domain
;
1049 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1051 if (!iommu
|| !domain
)
1054 spin_lock_irqsave(&domain
->lock
, flags
);
1056 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
1057 iommu_flush_pages(iommu
, domain
->id
, dma_addr
, size
);
1059 if (iommu
->need_sync
)
1060 iommu_completion_wait(iommu
);
1062 spin_unlock_irqrestore(&domain
->lock
, flags
);
1065 free_pages((unsigned long)virt_addr
, get_order(size
));
1069 * The function for pre-allocating protection domains.
1071 * If the driver core informs the DMA layer if a driver grabs a device
1072 * we don't need to preallocate the protection domains anymore.
1073 * For now we have to.
1075 void prealloc_protection_domains(void)
1077 struct pci_dev
*dev
= NULL
;
1078 struct dma_ops_domain
*dma_dom
;
1079 struct amd_iommu
*iommu
;
1080 int order
= amd_iommu_aperture_order
;
1083 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
1084 devid
= (dev
->bus
->number
<< 8) | dev
->devfn
;
1085 if (devid
> amd_iommu_last_bdf
)
1087 devid
= amd_iommu_alias_table
[devid
];
1088 if (domain_for_device(devid
))
1090 iommu
= amd_iommu_rlookup_table
[devid
];
1093 dma_dom
= dma_ops_domain_alloc(iommu
, order
);
1096 init_unity_mappings_for_device(dma_dom
, devid
);
1097 set_device_domain(iommu
, &dma_dom
->domain
, devid
);
1098 printk(KERN_INFO
"AMD IOMMU: Allocated domain %d for device ",
1099 dma_dom
->domain
.id
);
1100 print_devid(devid
, 1);
1104 static struct dma_mapping_ops amd_iommu_dma_ops
= {
1105 .alloc_coherent
= alloc_coherent
,
1106 .free_coherent
= free_coherent
,
1107 .map_single
= map_single
,
1108 .unmap_single
= unmap_single
,
1110 .unmap_sg
= unmap_sg
,
1114 * The function which clues the AMD IOMMU driver into dma_ops.
1116 int __init
amd_iommu_init_dma_ops(void)
1118 struct amd_iommu
*iommu
;
1119 int order
= amd_iommu_aperture_order
;
1123 * first allocate a default protection domain for every IOMMU we
1124 * found in the system. Devices not assigned to any other
1125 * protection domain will be assigned to the default one.
1127 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
1128 iommu
->default_dom
= dma_ops_domain_alloc(iommu
, order
);
1129 if (iommu
->default_dom
== NULL
)
1131 ret
= iommu_init_unity_mappings(iommu
);
1137 * If device isolation is enabled, pre-allocate the protection
1138 * domains for each device.
1140 if (amd_iommu_isolate
)
1141 prealloc_protection_domains();
1145 bad_dma_address
= 0;
1146 #ifdef CONFIG_GART_IOMMU
1147 gart_iommu_aperture_disabled
= 1;
1148 gart_iommu_aperture
= 0;
1151 /* Make the driver finally visible to the drivers */
1152 dma_ops
= &amd_iommu_dma_ops
;
1158 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
1159 if (iommu
->default_dom
)
1160 dma_ops_domain_free(iommu
->default_dom
);