1 #include <linux/config.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/slab.h>
8 #include <linux/random.h>
9 #include <linux/smp_lock.h>
10 #include <linux/init.h>
11 #include <linux/kernel_stat.h>
12 #include <linux/sysdev.h>
13 #include <linux/bitops.h>
15 #include <asm/8253pit.h>
16 #include <asm/atomic.h>
17 #include <asm/system.h>
19 #include <asm/timer.h>
20 #include <asm/pgtable.h>
21 #include <asm/delay.h>
24 #include <asm/arch_hooks.h>
25 #include <asm/i8259.h>
30 * This is the 'legacy' 8259A Programmable Interrupt Controller,
31 * present in the majority of PC/AT boxes.
32 * plus some generic x86 specific things if generic specifics makes
34 * this file should become arch/i386/kernel/irq.c when the old irq.c
35 * moves to arch independent land
38 DEFINE_SPINLOCK(i8259A_lock
);
40 static void end_8259A_irq (unsigned int irq
)
42 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
|IRQ_INPROGRESS
)) &&
44 enable_8259A_irq(irq
);
47 #define shutdown_8259A_irq disable_8259A_irq
49 static void mask_and_ack_8259A(unsigned int);
51 unsigned int startup_8259A_irq(unsigned int irq
)
53 enable_8259A_irq(irq
);
54 return 0; /* never anything pending */
57 static struct hw_interrupt_type i8259A_irq_type
= {
59 .startup
= startup_8259A_irq
,
60 .shutdown
= shutdown_8259A_irq
,
61 .enable
= enable_8259A_irq
,
62 .disable
= disable_8259A_irq
,
63 .ack
= mask_and_ack_8259A
,
68 * 8259A PIC functions to handle ISA devices:
72 * This contains the irq mask for both 8259A irq controllers,
74 unsigned int cached_irq_mask
= 0xffff;
77 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
78 * boards the timer interrupt is not really connected to any IO-APIC pin,
79 * it's fed to the master 8259A's IR0 line only.
81 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
82 * this 'mixed mode' IRQ handling costs nothing because it's only used
85 unsigned long io_apic_irqs
;
87 void disable_8259A_irq(unsigned int irq
)
89 unsigned int mask
= 1 << irq
;
92 spin_lock_irqsave(&i8259A_lock
, flags
);
93 cached_irq_mask
|= mask
;
95 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
97 outb(cached_master_mask
, PIC_MASTER_IMR
);
98 spin_unlock_irqrestore(&i8259A_lock
, flags
);
101 void enable_8259A_irq(unsigned int irq
)
103 unsigned int mask
= ~(1 << irq
);
106 spin_lock_irqsave(&i8259A_lock
, flags
);
107 cached_irq_mask
&= mask
;
109 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
111 outb(cached_master_mask
, PIC_MASTER_IMR
);
112 spin_unlock_irqrestore(&i8259A_lock
, flags
);
115 int i8259A_irq_pending(unsigned int irq
)
117 unsigned int mask
= 1<<irq
;
121 spin_lock_irqsave(&i8259A_lock
, flags
);
123 ret
= inb(PIC_MASTER_CMD
) & mask
;
125 ret
= inb(PIC_SLAVE_CMD
) & (mask
>> 8);
126 spin_unlock_irqrestore(&i8259A_lock
, flags
);
131 void make_8259A_irq(unsigned int irq
)
133 disable_irq_nosync(irq
);
134 io_apic_irqs
&= ~(1<<irq
);
135 irq_desc
[irq
].handler
= &i8259A_irq_type
;
140 * This function assumes to be called rarely. Switching between
141 * 8259A registers is slow.
142 * This has to be protected by the irq controller spinlock
143 * before being called.
145 static inline int i8259A_irq_real(unsigned int irq
)
148 int irqmask
= 1<<irq
;
151 outb(0x0B,PIC_MASTER_CMD
); /* ISR register */
152 value
= inb(PIC_MASTER_CMD
) & irqmask
;
153 outb(0x0A,PIC_MASTER_CMD
); /* back to the IRR register */
156 outb(0x0B,PIC_SLAVE_CMD
); /* ISR register */
157 value
= inb(PIC_SLAVE_CMD
) & (irqmask
>> 8);
158 outb(0x0A,PIC_SLAVE_CMD
); /* back to the IRR register */
163 * Careful! The 8259A is a fragile beast, it pretty
164 * much _has_ to be done exactly like this (mask it
165 * first, _then_ send the EOI, and the order of EOI
166 * to the two 8259s is important!
168 static void mask_and_ack_8259A(unsigned int irq
)
170 unsigned int irqmask
= 1 << irq
;
173 spin_lock_irqsave(&i8259A_lock
, flags
);
175 * Lightweight spurious IRQ detection. We do not want
176 * to overdo spurious IRQ handling - it's usually a sign
177 * of hardware problems, so we only do the checks we can
178 * do without slowing down good hardware unnecesserily.
180 * Note that IRQ7 and IRQ15 (the two spurious IRQs
181 * usually resulting from the 8259A-1|2 PICs) occur
182 * even if the IRQ is masked in the 8259A. Thus we
183 * can check spurious 8259A IRQs without doing the
184 * quite slow i8259A_irq_real() call for every IRQ.
185 * This does not cover 100% of spurious interrupts,
186 * but should be enough to warn the user that there
187 * is something bad going on ...
189 if (cached_irq_mask
& irqmask
)
190 goto spurious_8259A_irq
;
191 cached_irq_mask
|= irqmask
;
195 inb(PIC_SLAVE_IMR
); /* DUMMY - (do we need this?) */
196 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
197 outb(0x60+(irq
&7),PIC_SLAVE_CMD
);/* 'Specific EOI' to slave */
198 outb(0x60+PIC_CASCADE_IR
,PIC_MASTER_CMD
); /* 'Specific EOI' to master-IRQ2 */
200 inb(PIC_MASTER_IMR
); /* DUMMY - (do we need this?) */
201 outb(cached_master_mask
, PIC_MASTER_IMR
);
202 outb(0x60+irq
,PIC_MASTER_CMD
); /* 'Specific EOI to master */
204 spin_unlock_irqrestore(&i8259A_lock
, flags
);
209 * this is the slow path - should happen rarely.
211 if (i8259A_irq_real(irq
))
213 * oops, the IRQ _is_ in service according to the
214 * 8259A - not spurious, go handle it.
216 goto handle_real_irq
;
219 static int spurious_irq_mask
;
221 * At this point we can be sure the IRQ is spurious,
222 * lets ACK and report it. [once per IRQ]
224 if (!(spurious_irq_mask
& irqmask
)) {
225 printk(KERN_DEBUG
"spurious 8259A interrupt: IRQ%d.\n", irq
);
226 spurious_irq_mask
|= irqmask
;
228 atomic_inc(&irq_err_count
);
230 * Theoretically we do not have to handle this IRQ,
231 * but in Linux this does not cause problems and is
234 goto handle_real_irq
;
238 static char irq_trigger
[2];
240 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
242 static void restore_ELCR(char *trigger
)
244 outb(trigger
[0], 0x4d0);
245 outb(trigger
[1], 0x4d1);
248 static void save_ELCR(char *trigger
)
250 /* IRQ 0,1,2,8,13 are marked as reserved */
251 trigger
[0] = inb(0x4d0) & 0xF8;
252 trigger
[1] = inb(0x4d1) & 0xDE;
255 static int i8259A_resume(struct sys_device
*dev
)
258 restore_ELCR(irq_trigger
);
262 static int i8259A_suspend(struct sys_device
*dev
, pm_message_t state
)
264 save_ELCR(irq_trigger
);
268 static int i8259A_shutdown(struct sys_device
*dev
)
270 /* Put the i8259A into a quiescent state that
271 * the kernel initialization code can get it
274 outb(0xff, 0x21); /* mask all of 8259A-1 */
275 outb(0xff, 0xA1); /* mask all of 8259A-1 */
279 static struct sysdev_class i8259_sysdev_class
= {
280 set_kset_name("i8259"),
281 .suspend
= i8259A_suspend
,
282 .resume
= i8259A_resume
,
283 .shutdown
= i8259A_shutdown
,
286 static struct sys_device device_i8259A
= {
288 .cls
= &i8259_sysdev_class
,
291 static int __init
i8259A_init_sysfs(void)
293 int error
= sysdev_class_register(&i8259_sysdev_class
);
295 error
= sysdev_register(&device_i8259A
);
299 device_initcall(i8259A_init_sysfs
);
301 void init_8259A(int auto_eoi
)
305 spin_lock_irqsave(&i8259A_lock
, flags
);
307 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
308 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-2 */
311 * outb_p - this has to work on a wide range of PC hardware.
313 outb_p(0x11, PIC_MASTER_CMD
); /* ICW1: select 8259A-1 init */
314 outb_p(0x20 + 0, PIC_MASTER_IMR
); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
315 outb_p(1U << PIC_CASCADE_IR
, PIC_MASTER_IMR
); /* 8259A-1 (the master) has a slave on IR2 */
316 if (auto_eoi
) /* master does Auto EOI */
317 outb_p(MASTER_ICW4_DEFAULT
| PIC_ICW4_AEOI
, PIC_MASTER_IMR
);
318 else /* master expects normal EOI */
319 outb_p(MASTER_ICW4_DEFAULT
, PIC_MASTER_IMR
);
321 outb_p(0x11, PIC_SLAVE_CMD
); /* ICW1: select 8259A-2 init */
322 outb_p(0x20 + 8, PIC_SLAVE_IMR
); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
323 outb_p(PIC_CASCADE_IR
, PIC_SLAVE_IMR
); /* 8259A-2 is a slave on master's IR2 */
324 outb_p(SLAVE_ICW4_DEFAULT
, PIC_SLAVE_IMR
); /* (slave's support for AEOI in flat mode is to be investigated) */
327 * in AEOI mode we just have to mask the interrupt
330 i8259A_irq_type
.ack
= disable_8259A_irq
;
332 i8259A_irq_type
.ack
= mask_and_ack_8259A
;
334 udelay(100); /* wait for 8259A to initialize */
336 outb(cached_master_mask
, PIC_MASTER_IMR
); /* restore master IRQ mask */
337 outb(cached_slave_mask
, PIC_SLAVE_IMR
); /* restore slave IRQ mask */
339 spin_unlock_irqrestore(&i8259A_lock
, flags
);
343 * Note that on a 486, we don't want to do a SIGFPE on an irq13
344 * as the irq is unreliable, and exception 16 works correctly
345 * (ie as explained in the intel literature). On a 386, you
346 * can't use exception 16 due to bad IBM design, so we have to
347 * rely on the less exact irq13.
349 * Careful.. Not only is IRQ13 unreliable, but it is also
350 * leads to races. IBM designers who came up with it should
355 static irqreturn_t
math_error_irq(int cpl
, void *dev_id
, struct pt_regs
*regs
)
357 extern void math_error(void __user
*);
359 if (ignore_fpu_irq
|| !boot_cpu_data
.hard_math
)
361 math_error((void __user
*)regs
->eip
);
366 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
367 * so allow interrupt sharing.
369 static struct irqaction fpu_irq
= { math_error_irq
, 0, CPU_MASK_NONE
, "fpu", NULL
, NULL
};
371 void __init
init_ISA_irqs (void)
375 #ifdef CONFIG_X86_LOCAL_APIC
380 for (i
= 0; i
< NR_IRQS
; i
++) {
381 irq_desc
[i
].status
= IRQ_DISABLED
;
382 irq_desc
[i
].action
= NULL
;
383 irq_desc
[i
].depth
= 1;
387 * 16 old-style INTA-cycle interrupts:
389 irq_desc
[i
].handler
= &i8259A_irq_type
;
392 * 'high' PCI IRQs filled in on demand
394 irq_desc
[i
].handler
= &no_irq_type
;
399 void __init
init_IRQ(void)
403 /* all the set up before the call gates are initialised */
404 pre_intr_init_hook();
407 * Cover the whole vector space, no vector can escape
408 * us. (some of these will be overridden and become
409 * 'special' SMP interrupts)
411 for (i
= 0; i
< (NR_VECTORS
- FIRST_EXTERNAL_VECTOR
); i
++) {
412 int vector
= FIRST_EXTERNAL_VECTOR
+ i
;
415 if (vector
!= SYSCALL_VECTOR
)
416 set_intr_gate(vector
, interrupt
[i
]);
419 /* setup after call gates are initialised (usually add in
420 * the architecture specific gates)
425 * Set the clock to HZ Hz, we already have a valid
431 * External FPU? Set up irq13 if so, for
432 * original braindamaged IBM FERR coupling.
434 if (boot_cpu_data
.hard_math
&& !cpu_has_fpu
)
435 setup_irq(FPU_IRQ
, &fpu_irq
);
437 irq_ctx_init(smp_processor_id());