2 Copyright-c Realtek Semiconductor Corp. All rights reserved.
12 ---------- --------------- -------------------------------
13 2008-05-14 amy create version 0 porting from windows code.
20 #include "r8192U_dm.h"
21 //#include "r8190_rtl8256.h"
22 #include "r819xU_cmdpkt.h"
23 #include "r8192S_hw.h"
24 #include "r8192S_phy.h"
25 #include "r8192S_phyreg.h"
28 #include "r8192U_dm.h"
29 #include "r8192U_hw.h"
30 #include "r819xU_phy.h"
31 #include "r819xU_phyreg.h"
32 #include "r8190_rtl8256.h"
33 #include "r819xU_cmdpkt.h"
36 /*---------------------------Define Local Constant---------------------------*/
38 // Indicate different AP vendor for IOT issue.
41 typedef enum _HT_IOT_PEER
43 HT_IOT_PEER_UNKNOWN
= 0,
44 HT_IOT_PEER_REALTEK
= 1,
45 HT_IOT_PEER_BROADCOM
= 2,
46 HT_IOT_PEER_RALINK
= 3,
47 HT_IOT_PEER_ATHEROS
= 4,
48 HT_IOT_PEER_CISCO
= 5,
50 }HT_IOT_PEER_E
, *PHTIOT_PEER_E
;
54 static u32 edca_setting_DL
[HT_IOT_PEER_MAX
] =
55 // UNKNOWN REALTEK_90 /*REALTEK_92SE*/ BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP
56 { 0xa44f, 0x5ea44f, 0x5ea44f, 0xa44f, 0xa44f, 0xa44f, 0xa630, 0xa42b, 0x5e4322, 0x5e4322};
57 static u32 edca_setting_UL
[HT_IOT_PEER_MAX
] =
58 // UNKNOWN REALTEK /*REALTEK_92SE*/ BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP
59 { 0x5ea44f, 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea422, 0x5e4322, 0x3ea44f, 0x5ea42b, 0x5e4322, 0x5e4322};
63 static u32 edca_setting_DL
[HT_IOT_PEER_MAX
] =
64 { 0x5e4322, 0x5e4322, 0x5ea44f, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f};
65 static u32 edca_setting_UL
[HT_IOT_PEER_MAX
] =
66 { 0x5e4322, 0xa44f, 0x5ea44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f};
71 #define RTK_UL_EDCA 0xa44f
72 #define RTK_DL_EDCA 0x5e4322
73 /*---------------------------Define Local Constant---------------------------*/
76 /*------------------------Define global variable-----------------------------*/
79 // Store current shoftware write register content for MAC PHY.
80 u8 dm_shadow
[16][256] = {{0}};
81 // For Dynamic Rx Path Selection by Signal Strength
82 DRxPathSel DM_RxPathSelTable
;
83 /*------------------------Define global variable-----------------------------*/
86 /*------------------------Define local variable------------------------------*/
87 /*------------------------Define local variable------------------------------*/
90 /*--------------------Define export function prototype-----------------------*/
92 static void dm_CheckProtection(struct net_device
*dev
);
94 extern void init_hal_dm(struct net_device
*dev
);
95 extern void deinit_hal_dm(struct net_device
*dev
);
97 extern void hal_dm_watchdog(struct net_device
*dev
);
100 extern void init_rate_adaptive(struct net_device
*dev
);
101 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
102 extern void dm_txpower_trackingcallback(struct work_struct
*work
);
104 extern void dm_txpower_trackingcallback(struct net_device
*dev
);
107 extern void dm_cck_txpower_adjust(struct net_device
*dev
,bool binch14
);
108 extern void dm_restore_dynamic_mechanism_state(struct net_device
*dev
);
109 extern void dm_backup_dynamic_mechanism_state(struct net_device
*dev
);
110 extern void dm_change_dynamic_initgain_thresh(struct net_device
*dev
,
113 extern void DM_ChangeFsyncSetting(struct net_device
*dev
,
116 extern void dm_force_tx_fw_info(struct net_device
*dev
,
119 extern void dm_init_edca_turbo(struct net_device
*dev
);
120 extern void dm_rf_operation_test_callback(unsigned long data
);
121 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
122 extern void dm_rf_pathcheck_workitemcallback(struct work_struct
*work
);
124 extern void dm_rf_pathcheck_workitemcallback(struct net_device
*dev
);
126 extern void dm_fsync_timer_callback(unsigned long data
);
128 extern bool dm_check_lbus_status(struct net_device
*dev
);
130 extern void dm_check_fsync(struct net_device
*dev
);
131 extern void dm_shadow_init(struct net_device
*dev
);
134 /*--------------------Define export function prototype-----------------------*/
137 /*---------------------Define local function prototype-----------------------*/
138 // DM --> Rate Adaptive
139 static void dm_check_rate_adaptive(struct net_device
*dev
);
141 // DM --> Bandwidth switch
142 static void dm_init_bandwidth_autoswitch(struct net_device
*dev
);
143 static void dm_bandwidth_autoswitch( struct net_device
*dev
);
145 // DM --> TX power control
146 //static void dm_initialize_txpower_tracking(struct net_device *dev);
148 static void dm_check_txpower_tracking(struct net_device
*dev
);
152 //static void dm_txpower_reset_recovery(struct net_device *dev);
155 // DM --> BB init gain restore
157 static void dm_bb_initialgain_restore(struct net_device
*dev
);
160 // DM --> BB init gain backup
161 static void dm_bb_initialgain_backup(struct net_device
*dev
);
163 // DM --> Dynamic Init Gain by RSSI
164 static void dm_dig_init(struct net_device
*dev
);
165 static void dm_ctrl_initgain_byrssi(struct net_device
*dev
);
166 static void dm_ctrl_initgain_byrssi_highpwr(struct net_device
*dev
);
167 static void dm_ctrl_initgain_byrssi_by_driverrssi( struct net_device
*dev
);
168 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device
*dev
);
169 static void dm_initial_gain(struct net_device
*dev
);
170 static void dm_pd_th(struct net_device
*dev
);
171 static void dm_cs_ratio(struct net_device
*dev
);
173 static void dm_init_ctstoself(struct net_device
*dev
);
174 // DM --> EDCA turboe mode control
175 static void dm_check_edca_turbo(struct net_device
*dev
);
177 // DM --> HW RF control
178 static void dm_check_rfctrl_gpio(struct net_device
*dev
);
181 //static void dm_gpio_change_rf(struct net_device *dev);
184 static void dm_check_pbc_gpio(struct net_device
*dev
);
187 // DM --> Check current RX RF path state
188 static void dm_check_rx_path_selection(struct net_device
*dev
);
189 static void dm_init_rxpath_selection(struct net_device
*dev
);
190 static void dm_rxpath_sel_byrssi(struct net_device
*dev
);
193 // DM --> Fsync for broadcom ap
194 static void dm_init_fsync(struct net_device
*dev
);
195 static void dm_deInit_fsync(struct net_device
*dev
);
197 //Added by vivi, 20080522
198 static void dm_check_txrateandretrycount(struct net_device
*dev
);
200 /*---------------------Define local function prototype-----------------------*/
202 /*---------------------Define of Tx Power Control For Near/Far Range --------*/ //Add by Jacken 2008/02/18
203 static void dm_init_dynamic_txpower(struct net_device
*dev
);
204 static void dm_dynamic_txpower(struct net_device
*dev
);
207 // DM --> For rate adaptive and DIG, we must send RSSI to firmware
208 static void dm_send_rssi_tofw(struct net_device
*dev
);
209 static void dm_ctstoself(struct net_device
*dev
);
210 /*---------------------------Define function prototype------------------------*/
211 //================================================================================
212 // HW Dynamic mechanism interface.
213 //================================================================================
215 static void dm_CheckAggrPolicy(struct net_device
*dev
)
217 struct r8192_priv
*priv
= ieee80211_priv(dev
);
218 PRT_HIGH_THROUGHPUT pHTInfo
= priv
->ieee80211
->pHTInfo
;
221 bool bAmsduEnable
= false;
223 static u8 lastTxOkCnt
= 0;
224 static u8 lastRxOkCnt
= 0;
228 // Determine if A-MSDU policy.
229 if(priv
->ieee80211
->pHTInfo
->IOTAction
& HT_IOT_ACT_HYBRID_AGGREGATION
)
231 if(read_nic_byte(dev
, INIMCS_SEL
) > DESC92S_RATE54M
)
234 else if(priv
->ieee80211
->pHTInfo
->IOTAction
& HT_IOT_ACT_AMSDU_ENABLE
)
236 if(read_nic_byte(dev
, INIMCS_SEL
) > DESC92S_RATE54M
)
238 curTxOkCnt
= priv
->stats
.txbytesunicast
- lastTxOkCnt
;
239 curRxOkCnt
= priv
->stats
.rxbytesunicast
- lastRxOkCnt
;
241 if(curRxOkCnt
<= 4*curTxOkCnt
)
247 // Do not need to switch aggregation policy.
252 if(bAmsduEnable
&& !pHTInfo
->bCurrent_AMSDU_Support
)
254 pHTInfo
->bCurrent_AMSDU_Support
= true;
256 else if(!bAmsduEnable
&& pHTInfo
->bCurrent_AMSDU_Support
)
259 //PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
260 for(QueueId
= 0; QueueId
< MAX_TX_QUEUE
; QueueId
++)
262 while(!RTIsListEmpty(&dev
->TcbAggrQueue
[QueueId
]))
264 pTcb
= (PRT_TCB
)RTRemoveHeadList(&dev
->TcbAggrQueue
[QueueId
]);
265 dev
->TcbCountInAggrQueue
[QueueId
]--;
266 PreTransmitTCB(dev
, pTcb
);
269 //PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
270 pHTInfo
->bCurrent_AMSDU_Support
= false;
274 // Determine A-MPDU policy
275 if(priv
->ieee80211
->pHTInfo
->IOTAction
& HT_IOT_ACT_AMSDU_ENABLE
)
278 pHTInfo
->bCurrentAMPDUEnable
= true;
281 // Update local static variables.
282 lastTxOkCnt
= priv
->stats
.txbytesunicast
;
283 lastRxOkCnt
= priv
->stats
.rxbytesunicast
;
288 // Prepare SW resource for HW dynamic mechanism.
291 // This function is only invoked at driver intialization once.
295 init_hal_dm(struct net_device
*dev
)
297 struct r8192_priv
*priv
= ieee80211_priv(dev
);
299 // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism.
300 priv
->undecorated_smoothed_pwdb
= -1;
302 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
303 dm_init_dynamic_txpower(dev
);
304 init_rate_adaptive(dev
);
306 dm_initialize_txpower_tracking(dev
);
308 //dm_initialize_txpower_tracking(dev);
311 dm_init_edca_turbo(dev
);
312 dm_init_bandwidth_autoswitch(dev
);
314 dm_init_rxpath_selection(dev
);
315 dm_init_ctstoself(dev
);
319 extern void deinit_hal_dm(struct net_device
*dev
)
322 dm_deInit_fsync(dev
);
327 #ifdef USB_RX_AGGREGATION_SUPPORT
328 void dm_CheckRxAggregation(struct net_device
*dev
) {
329 struct r8192_priv
*priv
= ieee80211_priv((struct net_device
*)dev
);
330 PRT_HIGH_THROUGHPUT pHTInfo
= priv
->ieee80211
->pHTInfo
;
331 static unsigned long lastTxOkCnt
= 0;
332 static unsigned long lastRxOkCnt
= 0;
333 unsigned long curTxOkCnt
= 0;
334 unsigned long curRxOkCnt
= 0;
337 if (pHalData->bForcedUsbRxAggr) {
338 if (pHalData->ForcedUsbRxAggrInfo == 0) {
339 if (pHalData->bCurrentRxAggrEnable) {
340 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
343 if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) {
344 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE);
352 if (priv
->bForcedUsbRxAggr
) {
353 if (priv
->ForcedUsbRxAggrInfo
== 0) {
354 if (priv
->bCurrentRxAggrEnable
) {
355 //Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
356 write_nic_dword(dev
, 0x1a8, 0);
357 priv
->bCurrentRxAggrEnable
= false;
360 if (!priv
->bCurrentRxAggrEnable
|| (priv
->ForcedUsbRxAggrInfo
!= priv
->LastUsbRxAggrInfoSetting
)) {
362 ulValue
= (pHTInfo
->UsbRxFwAggrEn
<<24) | (pHTInfo
->UsbRxFwAggrPageNum
<<16) |
363 (pHTInfo
->UsbRxFwAggrPacketNum
<<8) | (pHTInfo
->UsbRxFwAggrTimeout
);
365 * If usb rx firmware aggregation is enabled,
366 * when anyone of three threshold conditions above is reached,
367 * firmware will send aggregated packet to driver.
369 write_nic_dword(dev
, 0x1a8, ulValue
);
370 priv
->bCurrentRxAggrEnable
= true;
376 if((priv
->ieee80211
->mode
& WIRELESS_MODE_B
) || (priv
->ieee80211
->mode
& WIRELESS_MODE_G
))
378 if (priv
->bCurrentRxAggrEnable
)
380 RT_TRACE(COMP_RECV
, "dm_CheckRxAggregation() : Disable Rx Aggregation!!\n");
381 write_nic_dword(dev
, 0x1a8, 0);
382 priv
->bCurrentRxAggrEnable
= false;
388 curTxOkCnt
= priv
->stats
.txbytesunicast
- lastTxOkCnt
;
389 curRxOkCnt
= priv
->stats
.rxbytesunicast
- lastRxOkCnt
;
391 if((curTxOkCnt
+ curRxOkCnt
) < 15000000) {
395 if(curTxOkCnt
> 4*curRxOkCnt
) {
396 if (priv
->bCurrentRxAggrEnable
) {
397 write_nic_dword(dev
, 0x1a8, 0);
398 priv
->bCurrentRxAggrEnable
= false;
401 if (!priv
->bCurrentRxAggrEnable
&& !pHTInfo
->bCurrentRT2RTAggregation
) {
403 ulValue
= (pHTInfo
->UsbRxFwAggrEn
<<24) | (pHTInfo
->UsbRxFwAggrPageNum
<<16) |
404 (pHTInfo
->UsbRxFwAggrPacketNum
<<8) | (pHTInfo
->UsbRxFwAggrTimeout
);
406 * If usb rx firmware aggregation is enabled,
407 * when anyone of three threshold conditions above is reached,
408 * firmware will send aggregated packet to driver.
410 write_nic_dword(dev
, 0x1a8, ulValue
);
411 priv
->bCurrentRxAggrEnable
= true;
415 lastTxOkCnt
= priv
->stats
.txbytesunicast
;
416 lastRxOkCnt
= priv
->stats
.rxbytesunicast
;
417 } // dm_CheckEdcaTurbo
423 extern void hal_dm_watchdog(struct net_device
*dev
)
425 struct r8192_priv
*priv
= ieee80211_priv(dev
);
431 dm_check_rfctrl_gpio(dev
);
433 // Add by hpfan 2008-03-11
434 dm_check_pbc_gpio(dev
);
435 dm_check_txrateandretrycount(dev
); //moved by tynli
436 dm_check_edca_turbo(dev
);
438 dm_CheckAggrPolicy(dev
);
441 dm_CheckProtection(dev
);
444 // ====================================================
445 // If any dynamic mechanism is ready, put it above this return;
446 // ====================================================
447 //if (IS_HARDWARE_TYPE_8192S(dev))
450 #ifdef USB_RX_AGGREGATION_SUPPORT
451 dm_CheckRxAggregation(dev
);
454 if(Adapter
->MgntInfo
.mActingAsAp
)
456 AP_dm_CheckRateAdaptive(dev
);
462 dm_check_rate_adaptive(dev
);
464 dm_dynamic_txpower(dev
);
466 dm_check_txpower_tracking(dev
);
467 dm_ctrl_initgain_byrssi(dev
);//LZM TMP 090302
469 dm_bandwidth_autoswitch(dev
);
471 dm_check_rx_path_selection(dev
);//LZM TMP 090302
474 dm_send_rssi_tofw(dev
);
480 extern void hal_dm_watchdog(struct net_device
*dev
)
482 //struct r8192_priv *priv = ieee80211_priv(dev);
484 //static u8 previous_bssid[6] ={0};
486 /*Add by amy 2008/05/15 ,porting from windows code.*/
487 dm_check_rate_adaptive(dev
);
488 dm_dynamic_txpower(dev
);
489 dm_check_txrateandretrycount(dev
);
490 dm_check_txpower_tracking(dev
);
491 dm_ctrl_initgain_byrssi(dev
);
492 dm_check_edca_turbo(dev
);
493 dm_bandwidth_autoswitch(dev
);
494 dm_check_rfctrl_gpio(dev
);
495 dm_check_rx_path_selection(dev
);
498 // Add by amy 2008-05-15 porting from windows code.
499 dm_check_pbc_gpio(dev
);
500 dm_send_rssi_tofw(dev
);
502 #ifdef USB_RX_AGGREGATION_SUPPORT
503 dm_CheckRxAggregation(dev
);
509 * Decide Rate Adaptive Set according to distance (signal strength)
510 * 01/11/2008 MHC Modify input arguments and RATR table level.
511 * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call
512 * the function after making sure RF_Type.
514 extern void init_rate_adaptive(struct net_device
* dev
)
517 struct r8192_priv
*priv
= ieee80211_priv(dev
);
518 prate_adaptive pra
= (prate_adaptive
)&priv
->rate_adaptive
;
520 pra
->ratr_state
= DM_RATR_STA_MAX
;
521 pra
->high2low_rssi_thresh_for_ra
= RateAdaptiveTH_High
;
522 pra
->low2high_rssi_thresh_for_ra20M
= RateAdaptiveTH_Low_20M
+5;
523 pra
->low2high_rssi_thresh_for_ra40M
= RateAdaptiveTH_Low_40M
+5;
525 pra
->high_rssi_thresh_for_ra
= RateAdaptiveTH_High
+5;
526 pra
->low_rssi_thresh_for_ra20M
= RateAdaptiveTH_Low_20M
;
527 pra
->low_rssi_thresh_for_ra40M
= RateAdaptiveTH_Low_40M
;
529 if(priv
->CustomerID
== RT_CID_819x_Netcore
)
530 pra
->ping_rssi_enable
= 1;
532 pra
->ping_rssi_enable
= 0;
533 pra
->ping_rssi_thresh_for_ra
= 15;
536 if (priv
->rf_type
== RF_2T4R
)
538 // 07/10/08 MH Modify for RA smooth scheme.
539 /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/
540 pra
->upper_rssi_threshold_ratr
= 0x8f0f0000;
541 pra
->middle_rssi_threshold_ratr
= 0x8f0ff000;
542 pra
->low_rssi_threshold_ratr
= 0x8f0ff001;
543 pra
->low_rssi_threshold_ratr_40M
= 0x8f0ff005;
544 pra
->low_rssi_threshold_ratr_20M
= 0x8f0ff001;
545 pra
->ping_rssi_ratr
= 0x0000000d;//cosa add for test
547 else if (priv
->rf_type
== RF_1T2R
)
549 pra
->upper_rssi_threshold_ratr
= 0x000f0000;
550 pra
->middle_rssi_threshold_ratr
= 0x000ff000;
551 pra
->low_rssi_threshold_ratr
= 0x000ff001;
552 pra
->low_rssi_threshold_ratr_40M
= 0x000ff005;
553 pra
->low_rssi_threshold_ratr_20M
= 0x000ff001;
554 pra
->ping_rssi_ratr
= 0x0000000d;//cosa add for test
557 } // InitRateAdaptive
560 /*-----------------------------------------------------------------------------
561 * Function: dm_check_rate_adaptive()
573 * 05/26/08 amy Create version 0 proting from windows code.
575 *---------------------------------------------------------------------------*/
576 static void dm_check_rate_adaptive(struct net_device
* dev
)
578 struct r8192_priv
*priv
= ieee80211_priv(dev
);
579 PRT_HIGH_THROUGHPUT pHTInfo
= priv
->ieee80211
->pHTInfo
;
580 prate_adaptive pra
= (prate_adaptive
)&priv
->rate_adaptive
;
581 u32 currentRATR
, targetRATR
= 0;
582 u32 LowRSSIThreshForRA
= 0, HighRSSIThreshForRA
= 0;
583 bool bshort_gi_enabled
= false;
584 static u8 ping_rssi_state
=0;
589 RT_TRACE(COMP_RATE
, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
593 if(pra
->rate_adaptive_disabled
)//this variable is set by ioctl.
596 // TODO: Only 11n mode is implemented currently,
597 if( !(priv
->ieee80211
->mode
== WIRELESS_MODE_N_24G
||
598 priv
->ieee80211
->mode
== WIRELESS_MODE_N_5G
))
601 if( priv
->ieee80211
->state
== IEEE80211_LINKED
)
603 // RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");
606 // Check whether Short GI is enabled
608 bshort_gi_enabled
= (pHTInfo
->bCurTxBW40MHz
&& pHTInfo
->bCurShortGI40MHz
) ||
609 (!pHTInfo
->bCurTxBW40MHz
&& pHTInfo
->bCurShortGI20MHz
);
612 pra
->upper_rssi_threshold_ratr
=
613 (pra
->upper_rssi_threshold_ratr
& (~BIT31
)) | ((bshort_gi_enabled
)? BIT31
:0) ;
615 pra
->middle_rssi_threshold_ratr
=
616 (pra
->middle_rssi_threshold_ratr
& (~BIT31
)) | ((bshort_gi_enabled
)? BIT31
:0) ;
618 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
620 pra
->low_rssi_threshold_ratr
=
621 (pra
->low_rssi_threshold_ratr_40M
& (~BIT31
)) | ((bshort_gi_enabled
)? BIT31
:0) ;
625 pra
->low_rssi_threshold_ratr
=
626 (pra
->low_rssi_threshold_ratr_20M
& (~BIT31
)) | ((bshort_gi_enabled
)? BIT31
:0) ;
629 pra
->ping_rssi_ratr
=
630 (pra
->ping_rssi_ratr
& (~BIT31
)) | ((bshort_gi_enabled
)? BIT31
:0) ;
632 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
633 time to link with AP. We will not change upper/lower threshold. If
634 STA stay in high or low level, we must change two different threshold
635 to prevent jumping frequently. */
636 if (pra
->ratr_state
== DM_RATR_STA_HIGH
)
638 HighRSSIThreshForRA
= pra
->high2low_rssi_thresh_for_ra
;
639 LowRSSIThreshForRA
= (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)?
640 (pra
->low_rssi_thresh_for_ra40M
):(pra
->low_rssi_thresh_for_ra20M
);
642 else if (pra
->ratr_state
== DM_RATR_STA_LOW
)
644 HighRSSIThreshForRA
= pra
->high_rssi_thresh_for_ra
;
645 LowRSSIThreshForRA
= (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)?
646 (pra
->low2high_rssi_thresh_for_ra40M
):(pra
->low2high_rssi_thresh_for_ra20M
);
650 HighRSSIThreshForRA
= pra
->high_rssi_thresh_for_ra
;
651 LowRSSIThreshForRA
= (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)?
652 (pra
->low_rssi_thresh_for_ra40M
):(pra
->low_rssi_thresh_for_ra20M
);
655 //DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);
656 if(priv
->undecorated_smoothed_pwdb
>= (long)HighRSSIThreshForRA
)
658 //DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);
659 pra
->ratr_state
= DM_RATR_STA_HIGH
;
660 targetRATR
= pra
->upper_rssi_threshold_ratr
;
661 }else if(priv
->undecorated_smoothed_pwdb
>= (long)LowRSSIThreshForRA
)
663 //DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);
664 pra
->ratr_state
= DM_RATR_STA_MIDDLE
;
665 targetRATR
= pra
->middle_rssi_threshold_ratr
;
668 //DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);
669 pra
->ratr_state
= DM_RATR_STA_LOW
;
670 targetRATR
= pra
->low_rssi_threshold_ratr
;
674 if(pra
->ping_rssi_enable
)
676 //pHalData->UndecoratedSmoothedPWDB = 19;
677 if(priv
->undecorated_smoothed_pwdb
< (long)(pra
->ping_rssi_thresh_for_ra
+5))
679 if( (priv
->undecorated_smoothed_pwdb
< (long)pra
->ping_rssi_thresh_for_ra
) ||
682 //DbgPrint("TestRSSI = %d, set RATR to 0x%x \n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);
683 pra
->ratr_state
= DM_RATR_STA_LOW
;
684 targetRATR
= pra
->ping_rssi_ratr
;
688 // DbgPrint("TestRSSI is between the range. \n");
692 //DbgPrint("TestRSSI Recover to 0x%x \n", targetRATR);
699 // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
700 if(priv
->ieee80211
->GetHalfNmodeSupportByAPsHandler(dev
))
701 targetRATR
&= 0xf00fffff;
705 // Check whether updating of RATR0 is required
707 currentRATR
= read_nic_dword(dev
, RATR0
);
708 if( targetRATR
!= currentRATR
)
711 ratr_value
= targetRATR
;
712 RT_TRACE(COMP_RATE
,"currentRATR = %x, targetRATR = %x\n", currentRATR
, targetRATR
);
713 if(priv
->rf_type
== RF_1T2R
)
715 ratr_value
&= ~(RATE_ALL_OFDM_2SS
);
717 write_nic_dword(dev
, RATR0
, ratr_value
);
718 write_nic_byte(dev
, UFWP
, 1);
720 pra
->last_ratr
= targetRATR
;
726 pra
->ratr_state
= DM_RATR_STA_MAX
;
729 } // dm_CheckRateAdaptive
732 static void dm_init_bandwidth_autoswitch(struct net_device
* dev
)
734 struct r8192_priv
*priv
= ieee80211_priv(dev
);
736 priv
->ieee80211
->bandwidth_auto_switch
.threshold_20Mhzto40Mhz
= BW_AUTO_SWITCH_LOW_HIGH
;
737 priv
->ieee80211
->bandwidth_auto_switch
.threshold_40Mhzto20Mhz
= BW_AUTO_SWITCH_HIGH_LOW
;
738 priv
->ieee80211
->bandwidth_auto_switch
.bforced_tx20Mhz
= false;
739 priv
->ieee80211
->bandwidth_auto_switch
.bautoswitch_enable
= false;
741 } // dm_init_bandwidth_autoswitch
744 static void dm_bandwidth_autoswitch(struct net_device
* dev
)
746 struct r8192_priv
*priv
= ieee80211_priv(dev
);
748 if(priv
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20
||!priv
->ieee80211
->bandwidth_auto_switch
.bautoswitch_enable
){
751 if(priv
->ieee80211
->bandwidth_auto_switch
.bforced_tx20Mhz
== false){//If send packets in 40 Mhz in 20/40
752 if(priv
->undecorated_smoothed_pwdb
<= priv
->ieee80211
->bandwidth_auto_switch
.threshold_40Mhzto20Mhz
)
753 priv
->ieee80211
->bandwidth_auto_switch
.bforced_tx20Mhz
= true;
754 }else{//in force send packets in 20 Mhz in 20/40
755 if(priv
->undecorated_smoothed_pwdb
>= priv
->ieee80211
->bandwidth_auto_switch
.threshold_20Mhzto40Mhz
)
756 priv
->ieee80211
->bandwidth_auto_switch
.bforced_tx20Mhz
= false;
760 } // dm_BandwidthAutoSwitch
762 //OFDM default at 0db, index=6.
763 static u32 OFDMSwingTable
[OFDM_Table_Length
] = {
764 0x7f8001fe, // 0, +6db
765 0x71c001c7, // 1, +5db
766 0x65400195, // 2, +4db
767 0x5a400169, // 3, +3db
768 0x50800142, // 4, +2db
769 0x47c0011f, // 5, +1db
770 0x40000100, // 6, +0db ===> default, upper for higher temprature, lower for low temprature
771 0x390000e4, // 7, -1db
772 0x32c000cb, // 8, -2db
773 0x2d4000b5, // 9, -3db
774 0x288000a2, // 10, -4db
775 0x24000090, // 11, -5db
776 0x20000080, // 12, -6db
777 0x1c800072, // 13, -7db
778 0x19800066, // 14, -8db
779 0x26c0005b, // 15, -9db
780 0x24400051, // 16, -10db
781 0x12000048, // 17, -11db
782 0x10000040 // 18, -12db
785 static u8 CCKSwingTable_Ch1_Ch13
[CCK_Table_length
][8] = {
786 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0db ===> CCK40M default
787 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 1, -1db
788 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 2, -2db
789 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 3, -3db
790 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 4, -4db
791 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 5, -5db
792 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 6, -6db ===> CCK20M default
793 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 7, -7db
794 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 8, -8db
795 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 9, -9db
796 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 10, -10db
797 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} // 11, -11db
800 static u8 CCKSwingTable_Ch14
[CCK_Table_length
][8] = {
801 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0db ===> CCK40M default
802 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 1, -1db
803 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 2, -2db
804 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 3, -3db
805 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 4, -4db
806 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 5, -5db
807 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 6, -6db ===> CCK20M default
808 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 7, -7db
809 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 8, -8db
810 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 9, -9db
811 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db
812 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db
815 static void dm_TXPowerTrackingCallback_TSSI(struct net_device
* dev
)
817 struct r8192_priv
*priv
= ieee80211_priv(dev
);
818 bool bHighpowerstate
, viviflag
= FALSE
;
820 u8 powerlevelOFDM24G
;
821 int i
=0, j
= 0, k
= 0;
822 u8 RF_Type
, tmp_report
[5]={0, 0, 0, 0, 0};
825 u16 Avg_TSSI_Meas
, TSSI_13dBm
, Avg_TSSI_Meas_from_driver
=0;
826 //RT_STATUS rtStatus = RT_STATUS_SUCCESS;
828 bool rtStatus
= true;
832 write_nic_byte(dev
, 0x1ba, 0);
834 priv
->ieee80211
->bdynamic_txpower_enable
= false;
835 bHighpowerstate
= priv
->bDynamicTxHighPower
;
837 powerlevelOFDM24G
= (u8
)(priv
->Pwr_Track
>>24);
838 RF_Type
= priv
->rf_type
;
839 Value
= (RF_Type
<<8) | powerlevelOFDM24G
;
841 RT_TRACE(COMP_POWER_TRACKING
, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G
);
843 for(j
= 0; j
<=30; j
++)
846 tx_cmd
.Op
= TXCMD_SET_TX_PWR_TRACKING
;
848 tx_cmd
.Value
= Value
;
850 rtStatus
= SendTxCommandPacket(dev
, &tx_cmd
, 12);
851 if (rtStatus
== false)
853 RT_TRACE(COMP_POWER_TRACKING
, "Set configuration with tx cmd queue fail!\n");
856 cmpk_message_handle_tx(dev
, (u8
*)&tx_cmd
,
857 DESC_PACKET_TYPE_INIT
, sizeof(DCMD_TXCMD_T
));
860 //DbgPrint("hi, vivi, strange\n");
861 for(i
= 0;i
<= 30; i
++)
863 Pwr_Flag
= read_nic_byte(dev
, 0x1ba);
871 Avg_TSSI_Meas
= read_nic_word(dev
, 0x1bc);
873 Avg_TSSI_Meas
= read_nic_word(dev
, 0x13c);
875 if(Avg_TSSI_Meas
== 0)
877 write_nic_byte(dev
, 0x1ba, 0);
881 for(k
= 0;k
< 5; k
++)
884 tmp_report
[k
] = read_nic_byte(dev
, 0x1d8+k
);
887 tmp_report
[k
] = read_nic_byte(dev
, 0x134+k
);
889 tmp_report
[k
] = read_nic_byte(dev
, 0x13e);
891 RT_TRACE(COMP_POWER_TRACKING
, "TSSI_report_value = %d\n", tmp_report
[k
]);
894 //check if the report value is right
895 for(k
= 0;k
< 5; k
++)
897 if(tmp_report
[k
] <= 20)
905 write_nic_byte(dev
, 0x1ba, 0);
907 RT_TRACE(COMP_POWER_TRACKING
, "we filted this data\n");
908 for(k
= 0;k
< 5; k
++)
913 for(k
= 0;k
< 5; k
++)
915 Avg_TSSI_Meas_from_driver
+= tmp_report
[k
];
918 Avg_TSSI_Meas_from_driver
= Avg_TSSI_Meas_from_driver
*100/5;
919 RT_TRACE(COMP_POWER_TRACKING
, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver
);
920 TSSI_13dBm
= priv
->TSSI_13dBm
;
921 RT_TRACE(COMP_POWER_TRACKING
, "TSSI_13dBm = %d\n", TSSI_13dBm
);
923 //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)
924 // For MacOS-compatible
925 if(Avg_TSSI_Meas_from_driver
> TSSI_13dBm
)
926 delta
= Avg_TSSI_Meas_from_driver
- TSSI_13dBm
;
928 delta
= TSSI_13dBm
- Avg_TSSI_Meas_from_driver
;
930 if(delta
<= E_FOR_TX_POWER_TRACK
)
932 priv
->ieee80211
->bdynamic_txpower_enable
= TRUE
;
933 write_nic_byte(dev
, 0x1ba, 0);
934 RT_TRACE(COMP_POWER_TRACKING
, "tx power track is done\n");
935 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfa_txpowertrackingindex = %d\n", priv
->rfa_txpowertrackingindex
);
936 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfa_txpowertrackingindex_real = %d\n", priv
->rfa_txpowertrackingindex_real
);
938 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfc_txpowertrackingindex = %d\n", priv
->rfc_txpowertrackingindex
);
939 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfc_txpowertrackingindex_real = %d\n", priv
->rfc_txpowertrackingindex_real
);
941 RT_TRACE(COMP_POWER_TRACKING
, "priv->cck_present_attentuation_difference = %d\n", priv
->cck_present_attentuation_difference
);
942 RT_TRACE(COMP_POWER_TRACKING
, "priv->cck_present_attentuation = %d\n", priv
->cck_present_attentuation
);
947 if(Avg_TSSI_Meas_from_driver
< TSSI_13dBm
- E_FOR_TX_POWER_TRACK
)
949 if((priv
->rfa_txpowertrackingindex
> 0)
951 &&(priv
->rfc_txpowertrackingindex
> 0)
955 priv
->rfa_txpowertrackingindex
--;
956 if(priv
->rfa_txpowertrackingindex_real
> 4)
958 priv
->rfa_txpowertrackingindex_real
--;
959 rtl8192_setBBreg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfa_txpowertrackingindex_real
].txbbgain_value
);
962 priv
->rfc_txpowertrackingindex
--;
963 if(priv
->rfc_txpowertrackingindex_real
> 4)
965 priv
->rfc_txpowertrackingindex_real
--;
966 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex_real
].txbbgain_value
);
973 if((priv
->rfa_txpowertrackingindex
< 36)
975 &&(priv
->rfc_txpowertrackingindex
< 36)
979 priv
->rfa_txpowertrackingindex
++;
980 priv
->rfa_txpowertrackingindex_real
++;
981 rtl8192_setBBreg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfa_txpowertrackingindex_real
].txbbgain_value
);
984 priv
->rfc_txpowertrackingindex
++;
985 priv
->rfc_txpowertrackingindex_real
++;
986 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex_real
].txbbgain_value
);
990 priv
->cck_present_attentuation_difference
991 = priv
->rfa_txpowertrackingindex
- priv
->rfa_txpowertracking_default
;
993 if(priv
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20
)
994 priv
->cck_present_attentuation
995 = priv
->cck_present_attentuation_20Mdefault
+ priv
->cck_present_attentuation_difference
;
997 priv
->cck_present_attentuation
998 = priv
->cck_present_attentuation_40Mdefault
+ priv
->cck_present_attentuation_difference
;
1000 if(priv
->cck_present_attentuation
> -1&&priv
->cck_present_attentuation
<23)
1002 if(priv
->ieee80211
->current_network
.channel
== 14 && !priv
->bcck_in_ch14
)
1004 priv
->bcck_in_ch14
= TRUE
;
1005 dm_cck_txpower_adjust(dev
,priv
->bcck_in_ch14
);
1007 else if(priv
->ieee80211
->current_network
.channel
!= 14 && priv
->bcck_in_ch14
)
1009 priv
->bcck_in_ch14
= FALSE
;
1010 dm_cck_txpower_adjust(dev
,priv
->bcck_in_ch14
);
1013 dm_cck_txpower_adjust(dev
,priv
->bcck_in_ch14
);
1015 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfa_txpowertrackingindex = %d\n", priv
->rfa_txpowertrackingindex
);
1016 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfa_txpowertrackingindex_real = %d\n", priv
->rfa_txpowertrackingindex_real
);
1018 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfc_txpowertrackingindex = %d\n", priv
->rfc_txpowertrackingindex
);
1019 RT_TRACE(COMP_POWER_TRACKING
, "priv->rfc_txpowertrackingindex_real = %d\n", priv
->rfc_txpowertrackingindex_real
);
1021 RT_TRACE(COMP_POWER_TRACKING
, "priv->cck_present_attentuation_difference = %d\n", priv
->cck_present_attentuation_difference
);
1022 RT_TRACE(COMP_POWER_TRACKING
, "priv->cck_present_attentuation = %d\n", priv
->cck_present_attentuation
);
1024 if (priv
->cck_present_attentuation_difference
<= -12||priv
->cck_present_attentuation_difference
>= 24)
1026 priv
->ieee80211
->bdynamic_txpower_enable
= TRUE
;
1027 write_nic_byte(dev
, 0x1ba, 0);
1028 RT_TRACE(COMP_POWER_TRACKING
, "tx power track--->limited\n");
1034 write_nic_byte(dev
, 0x1ba, 0);
1035 Avg_TSSI_Meas_from_driver
= 0;
1036 for(k
= 0;k
< 5; k
++)
1041 priv
->ieee80211
->bdynamic_txpower_enable
= TRUE
;
1042 write_nic_byte(dev
, 0x1ba, 0);
1045 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device
* dev
)
1047 #define ThermalMeterVal 9
1048 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1049 u32 tmpRegA
, TempCCk
;
1050 u8 tmpOFDMindex
, tmpCCKindex
, tmpCCK20Mindex
, tmpCCK40Mindex
, tmpval
;
1051 int i
=0, CCKSwingNeedUpdate
=0;
1053 if(!priv
->btxpower_trackingInit
)
1055 //Query OFDM default setting
1056 tmpRegA
= rtl8192_QueryBBReg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
);
1057 for(i
=0; i
<OFDM_Table_Length
; i
++) //find the index
1059 if(tmpRegA
== OFDMSwingTable
[i
])
1061 priv
->OFDM_index
= (u8
)i
;
1062 RT_TRACE(COMP_POWER_TRACKING
, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
1063 rOFDM0_XATxIQImbalance
, tmpRegA
, priv
->OFDM_index
);
1067 //Query CCK default setting From 0xa22
1068 TempCCk
= rtl8192_QueryBBReg(dev
, rCCK0_TxFilter1
, bMaskByte2
);
1069 for(i
=0 ; i
<CCK_Table_length
; i
++)
1071 if(TempCCk
== (u32
)CCKSwingTable_Ch1_Ch13
[i
][0])
1073 priv
->CCK_index
=(u8
) i
;
1074 RT_TRACE(COMP_POWER_TRACKING
, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
1075 rCCK0_TxFilter1
, TempCCk
, priv
->CCK_index
);
1079 priv
->btxpower_trackingInit
= TRUE
;
1080 //pHalData->TXPowercount = 0;
1084 //==========================
1085 // this is only for test, should be masked
1089 //UINT32 start_rf, end_rf;
1092 //UINT32 reg_addr_end;
1094 //start_rf = RF90_PATH_A;
1095 //end_rf = RF90_PATH_B;//RF90_PATH_MAX;
1097 //reg_addr_end = 0x2F;
1099 for (curr_addr
= 0; curr_addr
< 0x2d; curr_addr
++)
1101 reg_value
= PHY_QueryRFReg( Adapter
, (RF90_RADIO_PATH_E
)RF90_PATH_A
,
1102 curr_addr
, bMaskDWord
);
1105 pHalData
->TXPowercount
= 0;
1109 //==========================
1111 // read and filter out unreasonable value
1112 tmpRegA
= rtl8192_phy_QueryRFReg(dev
, RF90_PATH_A
, 0x12, 0x078); // 0x12: RF Reg[10:7]
1113 RT_TRACE(COMP_POWER_TRACKING
, "Readback ThermalMeterA = %d \n", tmpRegA
);
1114 if(tmpRegA
< 3 || tmpRegA
> 13)
1116 if(tmpRegA
>= 12) // if over 12, TP will be bad when high temprature
1118 RT_TRACE(COMP_POWER_TRACKING
, "Valid ThermalMeterA = %d \n", tmpRegA
);
1119 priv
->ThermalMeter
[0] = ThermalMeterVal
; //We use fixed value by Bryant's suggestion
1120 priv
->ThermalMeter
[1] = ThermalMeterVal
; //We use fixed value by Bryant's suggestion
1122 //Get current RF-A temprature index
1123 if(priv
->ThermalMeter
[0] >= (u8
)tmpRegA
) //lower temprature
1125 tmpOFDMindex
= tmpCCK20Mindex
= 6+(priv
->ThermalMeter
[0]-(u8
)tmpRegA
);
1126 tmpCCK40Mindex
= tmpCCK20Mindex
- 6;
1127 if(tmpOFDMindex
>= OFDM_Table_Length
)
1128 tmpOFDMindex
= OFDM_Table_Length
-1;
1129 if(tmpCCK20Mindex
>= CCK_Table_length
)
1130 tmpCCK20Mindex
= CCK_Table_length
-1;
1131 if(tmpCCK40Mindex
>= CCK_Table_length
)
1132 tmpCCK40Mindex
= CCK_Table_length
-1;
1136 tmpval
= ((u8
)tmpRegA
- priv
->ThermalMeter
[0]);
1137 if(tmpval
>= 6) // higher temprature
1138 tmpOFDMindex
= tmpCCK20Mindex
= 0; // max to +6dB
1140 tmpOFDMindex
= tmpCCK20Mindex
= 6 - tmpval
;
1143 //DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
1144 //((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
1145 //tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);
1146 if(priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
) //40M
1147 tmpCCKindex
= tmpCCK40Mindex
;
1149 tmpCCKindex
= tmpCCK20Mindex
;
1151 if(priv
->ieee80211
->current_network
.channel
== 14 && !priv
->bcck_in_ch14
)
1153 priv
->bcck_in_ch14
= TRUE
;
1154 CCKSwingNeedUpdate
= 1;
1156 else if(priv
->ieee80211
->current_network
.channel
!= 14 && priv
->bcck_in_ch14
)
1158 priv
->bcck_in_ch14
= FALSE
;
1159 CCKSwingNeedUpdate
= 1;
1162 if(priv
->CCK_index
!= tmpCCKindex
)
1164 priv
->CCK_index
= tmpCCKindex
;
1165 CCKSwingNeedUpdate
= 1;
1168 if(CCKSwingNeedUpdate
)
1170 //DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);
1171 dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1173 if(priv
->OFDM_index
!= tmpOFDMindex
)
1175 priv
->OFDM_index
= tmpOFDMindex
;
1176 rtl8192_setBBreg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
, OFDMSwingTable
[priv
->OFDM_index
]);
1177 RT_TRACE(COMP_POWER_TRACKING
, "Update OFDMSwing[%d] = 0x%x\n",
1178 priv
->OFDM_index
, OFDMSwingTable
[priv
->OFDM_index
]);
1180 priv
->txpower_count
= 0;
1183 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
1184 extern void dm_txpower_trackingcallback(struct work_struct
*work
)
1186 struct delayed_work
*dwork
= container_of(work
,struct delayed_work
,work
);
1187 struct r8192_priv
*priv
= container_of(dwork
,struct r8192_priv
,txpower_tracking_wq
);
1188 struct net_device
*dev
= priv
->ieee80211
->dev
;
1190 extern void dm_txpower_trackingcallback(struct net_device
*dev
)
1192 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1196 dm_TXPowerTrackingCallback_TSSI(dev
);
1198 if(priv
->bDcut
== TRUE
)
1199 dm_TXPowerTrackingCallback_TSSI(dev
);
1201 dm_TXPowerTrackingCallback_ThermalMeter(dev
);
1206 static void dm_InitializeTXPowerTracking_TSSI(struct net_device
*dev
)
1209 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1211 //Initial the Tx BB index and mapping value
1212 priv
->txbbgain_table
[0].txbb_iq_amplifygain
= 12;
1213 priv
->txbbgain_table
[0].txbbgain_value
=0x7f8001fe;
1214 priv
->txbbgain_table
[1].txbb_iq_amplifygain
= 11;
1215 priv
->txbbgain_table
[1].txbbgain_value
=0x788001e2;
1216 priv
->txbbgain_table
[2].txbb_iq_amplifygain
= 10;
1217 priv
->txbbgain_table
[2].txbbgain_value
=0x71c001c7;
1218 priv
->txbbgain_table
[3].txbb_iq_amplifygain
= 9;
1219 priv
->txbbgain_table
[3].txbbgain_value
=0x6b8001ae;
1220 priv
->txbbgain_table
[4].txbb_iq_amplifygain
= 8;
1221 priv
->txbbgain_table
[4].txbbgain_value
=0x65400195;
1222 priv
->txbbgain_table
[5].txbb_iq_amplifygain
= 7;
1223 priv
->txbbgain_table
[5].txbbgain_value
=0x5fc0017f;
1224 priv
->txbbgain_table
[6].txbb_iq_amplifygain
= 6;
1225 priv
->txbbgain_table
[6].txbbgain_value
=0x5a400169;
1226 priv
->txbbgain_table
[7].txbb_iq_amplifygain
= 5;
1227 priv
->txbbgain_table
[7].txbbgain_value
=0x55400155;
1228 priv
->txbbgain_table
[8].txbb_iq_amplifygain
= 4;
1229 priv
->txbbgain_table
[8].txbbgain_value
=0x50800142;
1230 priv
->txbbgain_table
[9].txbb_iq_amplifygain
= 3;
1231 priv
->txbbgain_table
[9].txbbgain_value
=0x4c000130;
1232 priv
->txbbgain_table
[10].txbb_iq_amplifygain
= 2;
1233 priv
->txbbgain_table
[10].txbbgain_value
=0x47c0011f;
1234 priv
->txbbgain_table
[11].txbb_iq_amplifygain
= 1;
1235 priv
->txbbgain_table
[11].txbbgain_value
=0x43c0010f;
1236 priv
->txbbgain_table
[12].txbb_iq_amplifygain
= 0;
1237 priv
->txbbgain_table
[12].txbbgain_value
=0x40000100;
1238 priv
->txbbgain_table
[13].txbb_iq_amplifygain
= -1;
1239 priv
->txbbgain_table
[13].txbbgain_value
=0x3c8000f2;
1240 priv
->txbbgain_table
[14].txbb_iq_amplifygain
= -2;
1241 priv
->txbbgain_table
[14].txbbgain_value
=0x390000e4;
1242 priv
->txbbgain_table
[15].txbb_iq_amplifygain
= -3;
1243 priv
->txbbgain_table
[15].txbbgain_value
=0x35c000d7;
1244 priv
->txbbgain_table
[16].txbb_iq_amplifygain
= -4;
1245 priv
->txbbgain_table
[16].txbbgain_value
=0x32c000cb;
1246 priv
->txbbgain_table
[17].txbb_iq_amplifygain
= -5;
1247 priv
->txbbgain_table
[17].txbbgain_value
=0x300000c0;
1248 priv
->txbbgain_table
[18].txbb_iq_amplifygain
= -6;
1249 priv
->txbbgain_table
[18].txbbgain_value
=0x2d4000b5;
1250 priv
->txbbgain_table
[19].txbb_iq_amplifygain
= -7;
1251 priv
->txbbgain_table
[19].txbbgain_value
=0x2ac000ab;
1252 priv
->txbbgain_table
[20].txbb_iq_amplifygain
= -8;
1253 priv
->txbbgain_table
[20].txbbgain_value
=0x288000a2;
1254 priv
->txbbgain_table
[21].txbb_iq_amplifygain
= -9;
1255 priv
->txbbgain_table
[21].txbbgain_value
=0x26000098;
1256 priv
->txbbgain_table
[22].txbb_iq_amplifygain
= -10;
1257 priv
->txbbgain_table
[22].txbbgain_value
=0x24000090;
1258 priv
->txbbgain_table
[23].txbb_iq_amplifygain
= -11;
1259 priv
->txbbgain_table
[23].txbbgain_value
=0x22000088;
1260 priv
->txbbgain_table
[24].txbb_iq_amplifygain
= -12;
1261 priv
->txbbgain_table
[24].txbbgain_value
=0x20000080;
1262 priv
->txbbgain_table
[25].txbb_iq_amplifygain
= -13;
1263 priv
->txbbgain_table
[25].txbbgain_value
=0x1a00006c;
1264 priv
->txbbgain_table
[26].txbb_iq_amplifygain
= -14;
1265 priv
->txbbgain_table
[26].txbbgain_value
=0x1c800072;
1266 priv
->txbbgain_table
[27].txbb_iq_amplifygain
= -15;
1267 priv
->txbbgain_table
[27].txbbgain_value
=0x18000060;
1268 priv
->txbbgain_table
[28].txbb_iq_amplifygain
= -16;
1269 priv
->txbbgain_table
[28].txbbgain_value
=0x19800066;
1270 priv
->txbbgain_table
[29].txbb_iq_amplifygain
= -17;
1271 priv
->txbbgain_table
[29].txbbgain_value
=0x15800056;
1272 priv
->txbbgain_table
[30].txbb_iq_amplifygain
= -18;
1273 priv
->txbbgain_table
[30].txbbgain_value
=0x26c0005b;
1274 priv
->txbbgain_table
[31].txbb_iq_amplifygain
= -19;
1275 priv
->txbbgain_table
[31].txbbgain_value
=0x14400051;
1276 priv
->txbbgain_table
[32].txbb_iq_amplifygain
= -20;
1277 priv
->txbbgain_table
[32].txbbgain_value
=0x24400051;
1278 priv
->txbbgain_table
[33].txbb_iq_amplifygain
= -21;
1279 priv
->txbbgain_table
[33].txbbgain_value
=0x1300004c;
1280 priv
->txbbgain_table
[34].txbb_iq_amplifygain
= -22;
1281 priv
->txbbgain_table
[34].txbbgain_value
=0x12000048;
1282 priv
->txbbgain_table
[35].txbb_iq_amplifygain
= -23;
1283 priv
->txbbgain_table
[35].txbbgain_value
=0x11000044;
1284 priv
->txbbgain_table
[36].txbb_iq_amplifygain
= -24;
1285 priv
->txbbgain_table
[36].txbbgain_value
=0x10000040;
1287 //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1288 //This Table is for CH1~CH13
1289 priv
->cck_txbbgain_table
[0].ccktxbb_valuearray
[0] = 0x36;
1290 priv
->cck_txbbgain_table
[0].ccktxbb_valuearray
[1] = 0x35;
1291 priv
->cck_txbbgain_table
[0].ccktxbb_valuearray
[2] = 0x2e;
1292 priv
->cck_txbbgain_table
[0].ccktxbb_valuearray
[3] = 0x25;
1293 priv
->cck_txbbgain_table
[0].ccktxbb_valuearray
[4] = 0x1c;
1294 priv
->cck_txbbgain_table
[0].ccktxbb_valuearray
[5] = 0x12;
1295 priv
->cck_txbbgain_table
[0].ccktxbb_valuearray
[6] = 0x09;
1296 priv
->cck_txbbgain_table
[0].ccktxbb_valuearray
[7] = 0x04;
1298 priv
->cck_txbbgain_table
[1].ccktxbb_valuearray
[0] = 0x33;
1299 priv
->cck_txbbgain_table
[1].ccktxbb_valuearray
[1] = 0x32;
1300 priv
->cck_txbbgain_table
[1].ccktxbb_valuearray
[2] = 0x2b;
1301 priv
->cck_txbbgain_table
[1].ccktxbb_valuearray
[3] = 0x23;
1302 priv
->cck_txbbgain_table
[1].ccktxbb_valuearray
[4] = 0x1a;
1303 priv
->cck_txbbgain_table
[1].ccktxbb_valuearray
[5] = 0x11;
1304 priv
->cck_txbbgain_table
[1].ccktxbb_valuearray
[6] = 0x08;
1305 priv
->cck_txbbgain_table
[1].ccktxbb_valuearray
[7] = 0x04;
1307 priv
->cck_txbbgain_table
[2].ccktxbb_valuearray
[0] = 0x30;
1308 priv
->cck_txbbgain_table
[2].ccktxbb_valuearray
[1] = 0x2f;
1309 priv
->cck_txbbgain_table
[2].ccktxbb_valuearray
[2] = 0x29;
1310 priv
->cck_txbbgain_table
[2].ccktxbb_valuearray
[3] = 0x21;
1311 priv
->cck_txbbgain_table
[2].ccktxbb_valuearray
[4] = 0x19;
1312 priv
->cck_txbbgain_table
[2].ccktxbb_valuearray
[5] = 0x10;
1313 priv
->cck_txbbgain_table
[2].ccktxbb_valuearray
[6] = 0x08;
1314 priv
->cck_txbbgain_table
[2].ccktxbb_valuearray
[7] = 0x03;
1316 priv
->cck_txbbgain_table
[3].ccktxbb_valuearray
[0] = 0x2d;
1317 priv
->cck_txbbgain_table
[3].ccktxbb_valuearray
[1] = 0x2d;
1318 priv
->cck_txbbgain_table
[3].ccktxbb_valuearray
[2] = 0x27;
1319 priv
->cck_txbbgain_table
[3].ccktxbb_valuearray
[3] = 0x1f;
1320 priv
->cck_txbbgain_table
[3].ccktxbb_valuearray
[4] = 0x18;
1321 priv
->cck_txbbgain_table
[3].ccktxbb_valuearray
[5] = 0x0f;
1322 priv
->cck_txbbgain_table
[3].ccktxbb_valuearray
[6] = 0x08;
1323 priv
->cck_txbbgain_table
[3].ccktxbb_valuearray
[7] = 0x03;
1325 priv
->cck_txbbgain_table
[4].ccktxbb_valuearray
[0] = 0x2b;
1326 priv
->cck_txbbgain_table
[4].ccktxbb_valuearray
[1] = 0x2a;
1327 priv
->cck_txbbgain_table
[4].ccktxbb_valuearray
[2] = 0x25;
1328 priv
->cck_txbbgain_table
[4].ccktxbb_valuearray
[3] = 0x1e;
1329 priv
->cck_txbbgain_table
[4].ccktxbb_valuearray
[4] = 0x16;
1330 priv
->cck_txbbgain_table
[4].ccktxbb_valuearray
[5] = 0x0e;
1331 priv
->cck_txbbgain_table
[4].ccktxbb_valuearray
[6] = 0x07;
1332 priv
->cck_txbbgain_table
[4].ccktxbb_valuearray
[7] = 0x03;
1334 priv
->cck_txbbgain_table
[5].ccktxbb_valuearray
[0] = 0x28;
1335 priv
->cck_txbbgain_table
[5].ccktxbb_valuearray
[1] = 0x28;
1336 priv
->cck_txbbgain_table
[5].ccktxbb_valuearray
[2] = 0x22;
1337 priv
->cck_txbbgain_table
[5].ccktxbb_valuearray
[3] = 0x1c;
1338 priv
->cck_txbbgain_table
[5].ccktxbb_valuearray
[4] = 0x15;
1339 priv
->cck_txbbgain_table
[5].ccktxbb_valuearray
[5] = 0x0d;
1340 priv
->cck_txbbgain_table
[5].ccktxbb_valuearray
[6] = 0x07;
1341 priv
->cck_txbbgain_table
[5].ccktxbb_valuearray
[7] = 0x03;
1343 priv
->cck_txbbgain_table
[6].ccktxbb_valuearray
[0] = 0x26;
1344 priv
->cck_txbbgain_table
[6].ccktxbb_valuearray
[1] = 0x25;
1345 priv
->cck_txbbgain_table
[6].ccktxbb_valuearray
[2] = 0x21;
1346 priv
->cck_txbbgain_table
[6].ccktxbb_valuearray
[3] = 0x1b;
1347 priv
->cck_txbbgain_table
[6].ccktxbb_valuearray
[4] = 0x14;
1348 priv
->cck_txbbgain_table
[6].ccktxbb_valuearray
[5] = 0x0d;
1349 priv
->cck_txbbgain_table
[6].ccktxbb_valuearray
[6] = 0x06;
1350 priv
->cck_txbbgain_table
[6].ccktxbb_valuearray
[7] = 0x03;
1352 priv
->cck_txbbgain_table
[7].ccktxbb_valuearray
[0] = 0x24;
1353 priv
->cck_txbbgain_table
[7].ccktxbb_valuearray
[1] = 0x23;
1354 priv
->cck_txbbgain_table
[7].ccktxbb_valuearray
[2] = 0x1f;
1355 priv
->cck_txbbgain_table
[7].ccktxbb_valuearray
[3] = 0x19;
1356 priv
->cck_txbbgain_table
[7].ccktxbb_valuearray
[4] = 0x13;
1357 priv
->cck_txbbgain_table
[7].ccktxbb_valuearray
[5] = 0x0c;
1358 priv
->cck_txbbgain_table
[7].ccktxbb_valuearray
[6] = 0x06;
1359 priv
->cck_txbbgain_table
[7].ccktxbb_valuearray
[7] = 0x03;
1361 priv
->cck_txbbgain_table
[8].ccktxbb_valuearray
[0] = 0x22;
1362 priv
->cck_txbbgain_table
[8].ccktxbb_valuearray
[1] = 0x21;
1363 priv
->cck_txbbgain_table
[8].ccktxbb_valuearray
[2] = 0x1d;
1364 priv
->cck_txbbgain_table
[8].ccktxbb_valuearray
[3] = 0x18;
1365 priv
->cck_txbbgain_table
[8].ccktxbb_valuearray
[4] = 0x11;
1366 priv
->cck_txbbgain_table
[8].ccktxbb_valuearray
[5] = 0x0b;
1367 priv
->cck_txbbgain_table
[8].ccktxbb_valuearray
[6] = 0x06;
1368 priv
->cck_txbbgain_table
[8].ccktxbb_valuearray
[7] = 0x02;
1370 priv
->cck_txbbgain_table
[9].ccktxbb_valuearray
[0] = 0x20;
1371 priv
->cck_txbbgain_table
[9].ccktxbb_valuearray
[1] = 0x20;
1372 priv
->cck_txbbgain_table
[9].ccktxbb_valuearray
[2] = 0x1b;
1373 priv
->cck_txbbgain_table
[9].ccktxbb_valuearray
[3] = 0x16;
1374 priv
->cck_txbbgain_table
[9].ccktxbb_valuearray
[4] = 0x11;
1375 priv
->cck_txbbgain_table
[9].ccktxbb_valuearray
[5] = 0x08;
1376 priv
->cck_txbbgain_table
[9].ccktxbb_valuearray
[6] = 0x05;
1377 priv
->cck_txbbgain_table
[9].ccktxbb_valuearray
[7] = 0x02;
1379 priv
->cck_txbbgain_table
[10].ccktxbb_valuearray
[0] = 0x1f;
1380 priv
->cck_txbbgain_table
[10].ccktxbb_valuearray
[1] = 0x1e;
1381 priv
->cck_txbbgain_table
[10].ccktxbb_valuearray
[2] = 0x1a;
1382 priv
->cck_txbbgain_table
[10].ccktxbb_valuearray
[3] = 0x15;
1383 priv
->cck_txbbgain_table
[10].ccktxbb_valuearray
[4] = 0x10;
1384 priv
->cck_txbbgain_table
[10].ccktxbb_valuearray
[5] = 0x0a;
1385 priv
->cck_txbbgain_table
[10].ccktxbb_valuearray
[6] = 0x05;
1386 priv
->cck_txbbgain_table
[10].ccktxbb_valuearray
[7] = 0x02;
1388 priv
->cck_txbbgain_table
[11].ccktxbb_valuearray
[0] = 0x1d;
1389 priv
->cck_txbbgain_table
[11].ccktxbb_valuearray
[1] = 0x1c;
1390 priv
->cck_txbbgain_table
[11].ccktxbb_valuearray
[2] = 0x18;
1391 priv
->cck_txbbgain_table
[11].ccktxbb_valuearray
[3] = 0x14;
1392 priv
->cck_txbbgain_table
[11].ccktxbb_valuearray
[4] = 0x0f;
1393 priv
->cck_txbbgain_table
[11].ccktxbb_valuearray
[5] = 0x0a;
1394 priv
->cck_txbbgain_table
[11].ccktxbb_valuearray
[6] = 0x05;
1395 priv
->cck_txbbgain_table
[11].ccktxbb_valuearray
[7] = 0x02;
1397 priv
->cck_txbbgain_table
[12].ccktxbb_valuearray
[0] = 0x1b;
1398 priv
->cck_txbbgain_table
[12].ccktxbb_valuearray
[1] = 0x1a;
1399 priv
->cck_txbbgain_table
[12].ccktxbb_valuearray
[2] = 0x17;
1400 priv
->cck_txbbgain_table
[12].ccktxbb_valuearray
[3] = 0x13;
1401 priv
->cck_txbbgain_table
[12].ccktxbb_valuearray
[4] = 0x0e;
1402 priv
->cck_txbbgain_table
[12].ccktxbb_valuearray
[5] = 0x09;
1403 priv
->cck_txbbgain_table
[12].ccktxbb_valuearray
[6] = 0x04;
1404 priv
->cck_txbbgain_table
[12].ccktxbb_valuearray
[7] = 0x02;
1406 priv
->cck_txbbgain_table
[13].ccktxbb_valuearray
[0] = 0x1a;
1407 priv
->cck_txbbgain_table
[13].ccktxbb_valuearray
[1] = 0x19;
1408 priv
->cck_txbbgain_table
[13].ccktxbb_valuearray
[2] = 0x16;
1409 priv
->cck_txbbgain_table
[13].ccktxbb_valuearray
[3] = 0x12;
1410 priv
->cck_txbbgain_table
[13].ccktxbb_valuearray
[4] = 0x0d;
1411 priv
->cck_txbbgain_table
[13].ccktxbb_valuearray
[5] = 0x09;
1412 priv
->cck_txbbgain_table
[13].ccktxbb_valuearray
[6] = 0x04;
1413 priv
->cck_txbbgain_table
[13].ccktxbb_valuearray
[7] = 0x02;
1415 priv
->cck_txbbgain_table
[14].ccktxbb_valuearray
[0] = 0x18;
1416 priv
->cck_txbbgain_table
[14].ccktxbb_valuearray
[1] = 0x17;
1417 priv
->cck_txbbgain_table
[14].ccktxbb_valuearray
[2] = 0x15;
1418 priv
->cck_txbbgain_table
[14].ccktxbb_valuearray
[3] = 0x11;
1419 priv
->cck_txbbgain_table
[14].ccktxbb_valuearray
[4] = 0x0c;
1420 priv
->cck_txbbgain_table
[14].ccktxbb_valuearray
[5] = 0x08;
1421 priv
->cck_txbbgain_table
[14].ccktxbb_valuearray
[6] = 0x04;
1422 priv
->cck_txbbgain_table
[14].ccktxbb_valuearray
[7] = 0x02;
1424 priv
->cck_txbbgain_table
[15].ccktxbb_valuearray
[0] = 0x17;
1425 priv
->cck_txbbgain_table
[15].ccktxbb_valuearray
[1] = 0x16;
1426 priv
->cck_txbbgain_table
[15].ccktxbb_valuearray
[2] = 0x13;
1427 priv
->cck_txbbgain_table
[15].ccktxbb_valuearray
[3] = 0x10;
1428 priv
->cck_txbbgain_table
[15].ccktxbb_valuearray
[4] = 0x0c;
1429 priv
->cck_txbbgain_table
[15].ccktxbb_valuearray
[5] = 0x08;
1430 priv
->cck_txbbgain_table
[15].ccktxbb_valuearray
[6] = 0x04;
1431 priv
->cck_txbbgain_table
[15].ccktxbb_valuearray
[7] = 0x02;
1433 priv
->cck_txbbgain_table
[16].ccktxbb_valuearray
[0] = 0x16;
1434 priv
->cck_txbbgain_table
[16].ccktxbb_valuearray
[1] = 0x15;
1435 priv
->cck_txbbgain_table
[16].ccktxbb_valuearray
[2] = 0x12;
1436 priv
->cck_txbbgain_table
[16].ccktxbb_valuearray
[3] = 0x0f;
1437 priv
->cck_txbbgain_table
[16].ccktxbb_valuearray
[4] = 0x0b;
1438 priv
->cck_txbbgain_table
[16].ccktxbb_valuearray
[5] = 0x07;
1439 priv
->cck_txbbgain_table
[16].ccktxbb_valuearray
[6] = 0x04;
1440 priv
->cck_txbbgain_table
[16].ccktxbb_valuearray
[7] = 0x01;
1442 priv
->cck_txbbgain_table
[17].ccktxbb_valuearray
[0] = 0x14;
1443 priv
->cck_txbbgain_table
[17].ccktxbb_valuearray
[1] = 0x14;
1444 priv
->cck_txbbgain_table
[17].ccktxbb_valuearray
[2] = 0x11;
1445 priv
->cck_txbbgain_table
[17].ccktxbb_valuearray
[3] = 0x0e;
1446 priv
->cck_txbbgain_table
[17].ccktxbb_valuearray
[4] = 0x0b;
1447 priv
->cck_txbbgain_table
[17].ccktxbb_valuearray
[5] = 0x07;
1448 priv
->cck_txbbgain_table
[17].ccktxbb_valuearray
[6] = 0x03;
1449 priv
->cck_txbbgain_table
[17].ccktxbb_valuearray
[7] = 0x02;
1451 priv
->cck_txbbgain_table
[18].ccktxbb_valuearray
[0] = 0x13;
1452 priv
->cck_txbbgain_table
[18].ccktxbb_valuearray
[1] = 0x13;
1453 priv
->cck_txbbgain_table
[18].ccktxbb_valuearray
[2] = 0x10;
1454 priv
->cck_txbbgain_table
[18].ccktxbb_valuearray
[3] = 0x0d;
1455 priv
->cck_txbbgain_table
[18].ccktxbb_valuearray
[4] = 0x0a;
1456 priv
->cck_txbbgain_table
[18].ccktxbb_valuearray
[5] = 0x06;
1457 priv
->cck_txbbgain_table
[18].ccktxbb_valuearray
[6] = 0x03;
1458 priv
->cck_txbbgain_table
[18].ccktxbb_valuearray
[7] = 0x01;
1460 priv
->cck_txbbgain_table
[19].ccktxbb_valuearray
[0] = 0x12;
1461 priv
->cck_txbbgain_table
[19].ccktxbb_valuearray
[1] = 0x12;
1462 priv
->cck_txbbgain_table
[19].ccktxbb_valuearray
[2] = 0x0f;
1463 priv
->cck_txbbgain_table
[19].ccktxbb_valuearray
[3] = 0x0c;
1464 priv
->cck_txbbgain_table
[19].ccktxbb_valuearray
[4] = 0x09;
1465 priv
->cck_txbbgain_table
[19].ccktxbb_valuearray
[5] = 0x06;
1466 priv
->cck_txbbgain_table
[19].ccktxbb_valuearray
[6] = 0x03;
1467 priv
->cck_txbbgain_table
[19].ccktxbb_valuearray
[7] = 0x01;
1469 priv
->cck_txbbgain_table
[20].ccktxbb_valuearray
[0] = 0x11;
1470 priv
->cck_txbbgain_table
[20].ccktxbb_valuearray
[1] = 0x11;
1471 priv
->cck_txbbgain_table
[20].ccktxbb_valuearray
[2] = 0x0f;
1472 priv
->cck_txbbgain_table
[20].ccktxbb_valuearray
[3] = 0x0c;
1473 priv
->cck_txbbgain_table
[20].ccktxbb_valuearray
[4] = 0x09;
1474 priv
->cck_txbbgain_table
[20].ccktxbb_valuearray
[5] = 0x06;
1475 priv
->cck_txbbgain_table
[20].ccktxbb_valuearray
[6] = 0x03;
1476 priv
->cck_txbbgain_table
[20].ccktxbb_valuearray
[7] = 0x01;
1478 priv
->cck_txbbgain_table
[21].ccktxbb_valuearray
[0] = 0x10;
1479 priv
->cck_txbbgain_table
[21].ccktxbb_valuearray
[1] = 0x10;
1480 priv
->cck_txbbgain_table
[21].ccktxbb_valuearray
[2] = 0x0e;
1481 priv
->cck_txbbgain_table
[21].ccktxbb_valuearray
[3] = 0x0b;
1482 priv
->cck_txbbgain_table
[21].ccktxbb_valuearray
[4] = 0x08;
1483 priv
->cck_txbbgain_table
[21].ccktxbb_valuearray
[5] = 0x05;
1484 priv
->cck_txbbgain_table
[21].ccktxbb_valuearray
[6] = 0x03;
1485 priv
->cck_txbbgain_table
[21].ccktxbb_valuearray
[7] = 0x01;
1487 priv
->cck_txbbgain_table
[22].ccktxbb_valuearray
[0] = 0x0f;
1488 priv
->cck_txbbgain_table
[22].ccktxbb_valuearray
[1] = 0x0f;
1489 priv
->cck_txbbgain_table
[22].ccktxbb_valuearray
[2] = 0x0d;
1490 priv
->cck_txbbgain_table
[22].ccktxbb_valuearray
[3] = 0x0b;
1491 priv
->cck_txbbgain_table
[22].ccktxbb_valuearray
[4] = 0x08;
1492 priv
->cck_txbbgain_table
[22].ccktxbb_valuearray
[5] = 0x05;
1493 priv
->cck_txbbgain_table
[22].ccktxbb_valuearray
[6] = 0x03;
1494 priv
->cck_txbbgain_table
[22].ccktxbb_valuearray
[7] = 0x01;
1496 //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1497 //This Table is for CH14
1498 priv
->cck_txbbgain_ch14_table
[0].ccktxbb_valuearray
[0] = 0x36;
1499 priv
->cck_txbbgain_ch14_table
[0].ccktxbb_valuearray
[1] = 0x35;
1500 priv
->cck_txbbgain_ch14_table
[0].ccktxbb_valuearray
[2] = 0x2e;
1501 priv
->cck_txbbgain_ch14_table
[0].ccktxbb_valuearray
[3] = 0x1b;
1502 priv
->cck_txbbgain_ch14_table
[0].ccktxbb_valuearray
[4] = 0x00;
1503 priv
->cck_txbbgain_ch14_table
[0].ccktxbb_valuearray
[5] = 0x00;
1504 priv
->cck_txbbgain_ch14_table
[0].ccktxbb_valuearray
[6] = 0x00;
1505 priv
->cck_txbbgain_ch14_table
[0].ccktxbb_valuearray
[7] = 0x00;
1507 priv
->cck_txbbgain_ch14_table
[1].ccktxbb_valuearray
[0] = 0x33;
1508 priv
->cck_txbbgain_ch14_table
[1].ccktxbb_valuearray
[1] = 0x32;
1509 priv
->cck_txbbgain_ch14_table
[1].ccktxbb_valuearray
[2] = 0x2b;
1510 priv
->cck_txbbgain_ch14_table
[1].ccktxbb_valuearray
[3] = 0x19;
1511 priv
->cck_txbbgain_ch14_table
[1].ccktxbb_valuearray
[4] = 0x00;
1512 priv
->cck_txbbgain_ch14_table
[1].ccktxbb_valuearray
[5] = 0x00;
1513 priv
->cck_txbbgain_ch14_table
[1].ccktxbb_valuearray
[6] = 0x00;
1514 priv
->cck_txbbgain_ch14_table
[1].ccktxbb_valuearray
[7] = 0x00;
1516 priv
->cck_txbbgain_ch14_table
[2].ccktxbb_valuearray
[0] = 0x30;
1517 priv
->cck_txbbgain_ch14_table
[2].ccktxbb_valuearray
[1] = 0x2f;
1518 priv
->cck_txbbgain_ch14_table
[2].ccktxbb_valuearray
[2] = 0x29;
1519 priv
->cck_txbbgain_ch14_table
[2].ccktxbb_valuearray
[3] = 0x18;
1520 priv
->cck_txbbgain_ch14_table
[2].ccktxbb_valuearray
[4] = 0x00;
1521 priv
->cck_txbbgain_ch14_table
[2].ccktxbb_valuearray
[5] = 0x00;
1522 priv
->cck_txbbgain_ch14_table
[2].ccktxbb_valuearray
[6] = 0x00;
1523 priv
->cck_txbbgain_ch14_table
[2].ccktxbb_valuearray
[7] = 0x00;
1525 priv
->cck_txbbgain_ch14_table
[3].ccktxbb_valuearray
[0] = 0x2d;
1526 priv
->cck_txbbgain_ch14_table
[3].ccktxbb_valuearray
[1] = 0x2d;
1527 priv
->cck_txbbgain_ch14_table
[3].ccktxbb_valuearray
[2] = 0x27;
1528 priv
->cck_txbbgain_ch14_table
[3].ccktxbb_valuearray
[3] = 0x17;
1529 priv
->cck_txbbgain_ch14_table
[3].ccktxbb_valuearray
[4] = 0x00;
1530 priv
->cck_txbbgain_ch14_table
[3].ccktxbb_valuearray
[5] = 0x00;
1531 priv
->cck_txbbgain_ch14_table
[3].ccktxbb_valuearray
[6] = 0x00;
1532 priv
->cck_txbbgain_ch14_table
[3].ccktxbb_valuearray
[7] = 0x00;
1534 priv
->cck_txbbgain_ch14_table
[4].ccktxbb_valuearray
[0] = 0x2b;
1535 priv
->cck_txbbgain_ch14_table
[4].ccktxbb_valuearray
[1] = 0x2a;
1536 priv
->cck_txbbgain_ch14_table
[4].ccktxbb_valuearray
[2] = 0x25;
1537 priv
->cck_txbbgain_ch14_table
[4].ccktxbb_valuearray
[3] = 0x15;
1538 priv
->cck_txbbgain_ch14_table
[4].ccktxbb_valuearray
[4] = 0x00;
1539 priv
->cck_txbbgain_ch14_table
[4].ccktxbb_valuearray
[5] = 0x00;
1540 priv
->cck_txbbgain_ch14_table
[4].ccktxbb_valuearray
[6] = 0x00;
1541 priv
->cck_txbbgain_ch14_table
[4].ccktxbb_valuearray
[7] = 0x00;
1543 priv
->cck_txbbgain_ch14_table
[5].ccktxbb_valuearray
[0] = 0x28;
1544 priv
->cck_txbbgain_ch14_table
[5].ccktxbb_valuearray
[1] = 0x28;
1545 priv
->cck_txbbgain_ch14_table
[5].ccktxbb_valuearray
[2] = 0x22;
1546 priv
->cck_txbbgain_ch14_table
[5].ccktxbb_valuearray
[3] = 0x14;
1547 priv
->cck_txbbgain_ch14_table
[5].ccktxbb_valuearray
[4] = 0x00;
1548 priv
->cck_txbbgain_ch14_table
[5].ccktxbb_valuearray
[5] = 0x00;
1549 priv
->cck_txbbgain_ch14_table
[5].ccktxbb_valuearray
[6] = 0x00;
1550 priv
->cck_txbbgain_ch14_table
[5].ccktxbb_valuearray
[7] = 0x00;
1552 priv
->cck_txbbgain_ch14_table
[6].ccktxbb_valuearray
[0] = 0x26;
1553 priv
->cck_txbbgain_ch14_table
[6].ccktxbb_valuearray
[1] = 0x25;
1554 priv
->cck_txbbgain_ch14_table
[6].ccktxbb_valuearray
[2] = 0x21;
1555 priv
->cck_txbbgain_ch14_table
[6].ccktxbb_valuearray
[3] = 0x13;
1556 priv
->cck_txbbgain_ch14_table
[6].ccktxbb_valuearray
[4] = 0x00;
1557 priv
->cck_txbbgain_ch14_table
[6].ccktxbb_valuearray
[5] = 0x00;
1558 priv
->cck_txbbgain_ch14_table
[6].ccktxbb_valuearray
[6] = 0x00;
1559 priv
->cck_txbbgain_ch14_table
[6].ccktxbb_valuearray
[7] = 0x00;
1561 priv
->cck_txbbgain_ch14_table
[7].ccktxbb_valuearray
[0] = 0x24;
1562 priv
->cck_txbbgain_ch14_table
[7].ccktxbb_valuearray
[1] = 0x23;
1563 priv
->cck_txbbgain_ch14_table
[7].ccktxbb_valuearray
[2] = 0x1f;
1564 priv
->cck_txbbgain_ch14_table
[7].ccktxbb_valuearray
[3] = 0x12;
1565 priv
->cck_txbbgain_ch14_table
[7].ccktxbb_valuearray
[4] = 0x00;
1566 priv
->cck_txbbgain_ch14_table
[7].ccktxbb_valuearray
[5] = 0x00;
1567 priv
->cck_txbbgain_ch14_table
[7].ccktxbb_valuearray
[6] = 0x00;
1568 priv
->cck_txbbgain_ch14_table
[7].ccktxbb_valuearray
[7] = 0x00;
1570 priv
->cck_txbbgain_ch14_table
[8].ccktxbb_valuearray
[0] = 0x22;
1571 priv
->cck_txbbgain_ch14_table
[8].ccktxbb_valuearray
[1] = 0x21;
1572 priv
->cck_txbbgain_ch14_table
[8].ccktxbb_valuearray
[2] = 0x1d;
1573 priv
->cck_txbbgain_ch14_table
[8].ccktxbb_valuearray
[3] = 0x11;
1574 priv
->cck_txbbgain_ch14_table
[8].ccktxbb_valuearray
[4] = 0x00;
1575 priv
->cck_txbbgain_ch14_table
[8].ccktxbb_valuearray
[5] = 0x00;
1576 priv
->cck_txbbgain_ch14_table
[8].ccktxbb_valuearray
[6] = 0x00;
1577 priv
->cck_txbbgain_ch14_table
[8].ccktxbb_valuearray
[7] = 0x00;
1579 priv
->cck_txbbgain_ch14_table
[9].ccktxbb_valuearray
[0] = 0x20;
1580 priv
->cck_txbbgain_ch14_table
[9].ccktxbb_valuearray
[1] = 0x20;
1581 priv
->cck_txbbgain_ch14_table
[9].ccktxbb_valuearray
[2] = 0x1b;
1582 priv
->cck_txbbgain_ch14_table
[9].ccktxbb_valuearray
[3] = 0x10;
1583 priv
->cck_txbbgain_ch14_table
[9].ccktxbb_valuearray
[4] = 0x00;
1584 priv
->cck_txbbgain_ch14_table
[9].ccktxbb_valuearray
[5] = 0x00;
1585 priv
->cck_txbbgain_ch14_table
[9].ccktxbb_valuearray
[6] = 0x00;
1586 priv
->cck_txbbgain_ch14_table
[9].ccktxbb_valuearray
[7] = 0x00;
1588 priv
->cck_txbbgain_ch14_table
[10].ccktxbb_valuearray
[0] = 0x1f;
1589 priv
->cck_txbbgain_ch14_table
[10].ccktxbb_valuearray
[1] = 0x1e;
1590 priv
->cck_txbbgain_ch14_table
[10].ccktxbb_valuearray
[2] = 0x1a;
1591 priv
->cck_txbbgain_ch14_table
[10].ccktxbb_valuearray
[3] = 0x0f;
1592 priv
->cck_txbbgain_ch14_table
[10].ccktxbb_valuearray
[4] = 0x00;
1593 priv
->cck_txbbgain_ch14_table
[10].ccktxbb_valuearray
[5] = 0x00;
1594 priv
->cck_txbbgain_ch14_table
[10].ccktxbb_valuearray
[6] = 0x00;
1595 priv
->cck_txbbgain_ch14_table
[10].ccktxbb_valuearray
[7] = 0x00;
1597 priv
->cck_txbbgain_ch14_table
[11].ccktxbb_valuearray
[0] = 0x1d;
1598 priv
->cck_txbbgain_ch14_table
[11].ccktxbb_valuearray
[1] = 0x1c;
1599 priv
->cck_txbbgain_ch14_table
[11].ccktxbb_valuearray
[2] = 0x18;
1600 priv
->cck_txbbgain_ch14_table
[11].ccktxbb_valuearray
[3] = 0x0e;
1601 priv
->cck_txbbgain_ch14_table
[11].ccktxbb_valuearray
[4] = 0x00;
1602 priv
->cck_txbbgain_ch14_table
[11].ccktxbb_valuearray
[5] = 0x00;
1603 priv
->cck_txbbgain_ch14_table
[11].ccktxbb_valuearray
[6] = 0x00;
1604 priv
->cck_txbbgain_ch14_table
[11].ccktxbb_valuearray
[7] = 0x00;
1606 priv
->cck_txbbgain_ch14_table
[12].ccktxbb_valuearray
[0] = 0x1b;
1607 priv
->cck_txbbgain_ch14_table
[12].ccktxbb_valuearray
[1] = 0x1a;
1608 priv
->cck_txbbgain_ch14_table
[12].ccktxbb_valuearray
[2] = 0x17;
1609 priv
->cck_txbbgain_ch14_table
[12].ccktxbb_valuearray
[3] = 0x0e;
1610 priv
->cck_txbbgain_ch14_table
[12].ccktxbb_valuearray
[4] = 0x00;
1611 priv
->cck_txbbgain_ch14_table
[12].ccktxbb_valuearray
[5] = 0x00;
1612 priv
->cck_txbbgain_ch14_table
[12].ccktxbb_valuearray
[6] = 0x00;
1613 priv
->cck_txbbgain_ch14_table
[12].ccktxbb_valuearray
[7] = 0x00;
1615 priv
->cck_txbbgain_ch14_table
[13].ccktxbb_valuearray
[0] = 0x1a;
1616 priv
->cck_txbbgain_ch14_table
[13].ccktxbb_valuearray
[1] = 0x19;
1617 priv
->cck_txbbgain_ch14_table
[13].ccktxbb_valuearray
[2] = 0x16;
1618 priv
->cck_txbbgain_ch14_table
[13].ccktxbb_valuearray
[3] = 0x0d;
1619 priv
->cck_txbbgain_ch14_table
[13].ccktxbb_valuearray
[4] = 0x00;
1620 priv
->cck_txbbgain_ch14_table
[13].ccktxbb_valuearray
[5] = 0x00;
1621 priv
->cck_txbbgain_ch14_table
[13].ccktxbb_valuearray
[6] = 0x00;
1622 priv
->cck_txbbgain_ch14_table
[13].ccktxbb_valuearray
[7] = 0x00;
1624 priv
->cck_txbbgain_ch14_table
[14].ccktxbb_valuearray
[0] = 0x18;
1625 priv
->cck_txbbgain_ch14_table
[14].ccktxbb_valuearray
[1] = 0x17;
1626 priv
->cck_txbbgain_ch14_table
[14].ccktxbb_valuearray
[2] = 0x15;
1627 priv
->cck_txbbgain_ch14_table
[14].ccktxbb_valuearray
[3] = 0x0c;
1628 priv
->cck_txbbgain_ch14_table
[14].ccktxbb_valuearray
[4] = 0x00;
1629 priv
->cck_txbbgain_ch14_table
[14].ccktxbb_valuearray
[5] = 0x00;
1630 priv
->cck_txbbgain_ch14_table
[14].ccktxbb_valuearray
[6] = 0x00;
1631 priv
->cck_txbbgain_ch14_table
[14].ccktxbb_valuearray
[7] = 0x00;
1633 priv
->cck_txbbgain_ch14_table
[15].ccktxbb_valuearray
[0] = 0x17;
1634 priv
->cck_txbbgain_ch14_table
[15].ccktxbb_valuearray
[1] = 0x16;
1635 priv
->cck_txbbgain_ch14_table
[15].ccktxbb_valuearray
[2] = 0x13;
1636 priv
->cck_txbbgain_ch14_table
[15].ccktxbb_valuearray
[3] = 0x0b;
1637 priv
->cck_txbbgain_ch14_table
[15].ccktxbb_valuearray
[4] = 0x00;
1638 priv
->cck_txbbgain_ch14_table
[15].ccktxbb_valuearray
[5] = 0x00;
1639 priv
->cck_txbbgain_ch14_table
[15].ccktxbb_valuearray
[6] = 0x00;
1640 priv
->cck_txbbgain_ch14_table
[15].ccktxbb_valuearray
[7] = 0x00;
1642 priv
->cck_txbbgain_ch14_table
[16].ccktxbb_valuearray
[0] = 0x16;
1643 priv
->cck_txbbgain_ch14_table
[16].ccktxbb_valuearray
[1] = 0x15;
1644 priv
->cck_txbbgain_ch14_table
[16].ccktxbb_valuearray
[2] = 0x12;
1645 priv
->cck_txbbgain_ch14_table
[16].ccktxbb_valuearray
[3] = 0x0b;
1646 priv
->cck_txbbgain_ch14_table
[16].ccktxbb_valuearray
[4] = 0x00;
1647 priv
->cck_txbbgain_ch14_table
[16].ccktxbb_valuearray
[5] = 0x00;
1648 priv
->cck_txbbgain_ch14_table
[16].ccktxbb_valuearray
[6] = 0x00;
1649 priv
->cck_txbbgain_ch14_table
[16].ccktxbb_valuearray
[7] = 0x00;
1651 priv
->cck_txbbgain_ch14_table
[17].ccktxbb_valuearray
[0] = 0x14;
1652 priv
->cck_txbbgain_ch14_table
[17].ccktxbb_valuearray
[1] = 0x14;
1653 priv
->cck_txbbgain_ch14_table
[17].ccktxbb_valuearray
[2] = 0x11;
1654 priv
->cck_txbbgain_ch14_table
[17].ccktxbb_valuearray
[3] = 0x0a;
1655 priv
->cck_txbbgain_ch14_table
[17].ccktxbb_valuearray
[4] = 0x00;
1656 priv
->cck_txbbgain_ch14_table
[17].ccktxbb_valuearray
[5] = 0x00;
1657 priv
->cck_txbbgain_ch14_table
[17].ccktxbb_valuearray
[6] = 0x00;
1658 priv
->cck_txbbgain_ch14_table
[17].ccktxbb_valuearray
[7] = 0x00;
1660 priv
->cck_txbbgain_ch14_table
[18].ccktxbb_valuearray
[0] = 0x13;
1661 priv
->cck_txbbgain_ch14_table
[18].ccktxbb_valuearray
[1] = 0x13;
1662 priv
->cck_txbbgain_ch14_table
[18].ccktxbb_valuearray
[2] = 0x10;
1663 priv
->cck_txbbgain_ch14_table
[18].ccktxbb_valuearray
[3] = 0x0a;
1664 priv
->cck_txbbgain_ch14_table
[18].ccktxbb_valuearray
[4] = 0x00;
1665 priv
->cck_txbbgain_ch14_table
[18].ccktxbb_valuearray
[5] = 0x00;
1666 priv
->cck_txbbgain_ch14_table
[18].ccktxbb_valuearray
[6] = 0x00;
1667 priv
->cck_txbbgain_ch14_table
[18].ccktxbb_valuearray
[7] = 0x00;
1669 priv
->cck_txbbgain_ch14_table
[19].ccktxbb_valuearray
[0] = 0x12;
1670 priv
->cck_txbbgain_ch14_table
[19].ccktxbb_valuearray
[1] = 0x12;
1671 priv
->cck_txbbgain_ch14_table
[19].ccktxbb_valuearray
[2] = 0x0f;
1672 priv
->cck_txbbgain_ch14_table
[19].ccktxbb_valuearray
[3] = 0x09;
1673 priv
->cck_txbbgain_ch14_table
[19].ccktxbb_valuearray
[4] = 0x00;
1674 priv
->cck_txbbgain_ch14_table
[19].ccktxbb_valuearray
[5] = 0x00;
1675 priv
->cck_txbbgain_ch14_table
[19].ccktxbb_valuearray
[6] = 0x00;
1676 priv
->cck_txbbgain_ch14_table
[19].ccktxbb_valuearray
[7] = 0x00;
1678 priv
->cck_txbbgain_ch14_table
[20].ccktxbb_valuearray
[0] = 0x11;
1679 priv
->cck_txbbgain_ch14_table
[20].ccktxbb_valuearray
[1] = 0x11;
1680 priv
->cck_txbbgain_ch14_table
[20].ccktxbb_valuearray
[2] = 0x0f;
1681 priv
->cck_txbbgain_ch14_table
[20].ccktxbb_valuearray
[3] = 0x09;
1682 priv
->cck_txbbgain_ch14_table
[20].ccktxbb_valuearray
[4] = 0x00;
1683 priv
->cck_txbbgain_ch14_table
[20].ccktxbb_valuearray
[5] = 0x00;
1684 priv
->cck_txbbgain_ch14_table
[20].ccktxbb_valuearray
[6] = 0x00;
1685 priv
->cck_txbbgain_ch14_table
[20].ccktxbb_valuearray
[7] = 0x00;
1687 priv
->cck_txbbgain_ch14_table
[21].ccktxbb_valuearray
[0] = 0x10;
1688 priv
->cck_txbbgain_ch14_table
[21].ccktxbb_valuearray
[1] = 0x10;
1689 priv
->cck_txbbgain_ch14_table
[21].ccktxbb_valuearray
[2] = 0x0e;
1690 priv
->cck_txbbgain_ch14_table
[21].ccktxbb_valuearray
[3] = 0x08;
1691 priv
->cck_txbbgain_ch14_table
[21].ccktxbb_valuearray
[4] = 0x00;
1692 priv
->cck_txbbgain_ch14_table
[21].ccktxbb_valuearray
[5] = 0x00;
1693 priv
->cck_txbbgain_ch14_table
[21].ccktxbb_valuearray
[6] = 0x00;
1694 priv
->cck_txbbgain_ch14_table
[21].ccktxbb_valuearray
[7] = 0x00;
1696 priv
->cck_txbbgain_ch14_table
[22].ccktxbb_valuearray
[0] = 0x0f;
1697 priv
->cck_txbbgain_ch14_table
[22].ccktxbb_valuearray
[1] = 0x0f;
1698 priv
->cck_txbbgain_ch14_table
[22].ccktxbb_valuearray
[2] = 0x0d;
1699 priv
->cck_txbbgain_ch14_table
[22].ccktxbb_valuearray
[3] = 0x08;
1700 priv
->cck_txbbgain_ch14_table
[22].ccktxbb_valuearray
[4] = 0x00;
1701 priv
->cck_txbbgain_ch14_table
[22].ccktxbb_valuearray
[5] = 0x00;
1702 priv
->cck_txbbgain_ch14_table
[22].ccktxbb_valuearray
[6] = 0x00;
1703 priv
->cck_txbbgain_ch14_table
[22].ccktxbb_valuearray
[7] = 0x00;
1705 priv
->btxpower_tracking
= TRUE
;
1706 priv
->txpower_count
= 0;
1707 priv
->btxpower_trackingInit
= FALSE
;
1712 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device
*dev
)
1714 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1716 // Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism
1717 // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1718 // 3-wire by driver cause RF goes into wrong state.
1719 if(priv
->ieee80211
->FwRWRF
)
1720 priv
->btxpower_tracking
= TRUE
;
1722 priv
->btxpower_tracking
= FALSE
;
1723 priv
->txpower_count
= 0;
1724 priv
->btxpower_trackingInit
= FALSE
;
1728 void dm_initialize_txpower_tracking(struct net_device
*dev
)
1730 #if (defined RTL8190P)
1731 dm_InitializeTXPowerTracking_TSSI(dev
);
1732 #elif (defined RTL8192SU)
1733 // 2009/01/12 MH Enable for 92S series channel 1-14 CCK tx pwer setting for MP.
1735 dm_InitializeTXPowerTracking_TSSI(dev
);
1737 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1738 if(priv
->bDcut
== TRUE
)
1739 dm_InitializeTXPowerTracking_TSSI(dev
);
1741 dm_InitializeTXPowerTracking_ThermalMeter(dev
);
1743 }// dm_InitializeTXPowerTracking
1746 static void dm_CheckTXPowerTracking_TSSI(struct net_device
*dev
)
1748 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1749 static u32 tx_power_track_counter
= 0;
1751 if(!priv
->btxpower_tracking
)
1755 if((tx_power_track_counter
% 30 == 0)&&(tx_power_track_counter
!= 0))
1757 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1758 queue_delayed_work(priv
->priv_wq
,&priv
->txpower_tracking_wq
,0);
1760 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1761 schedule_task(&priv
->txpower_tracking_wq
);
1763 queue_work(priv
->priv_wq
,&priv
->txpower_tracking_wq
);
1767 tx_power_track_counter
++;
1773 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device
*dev
)
1775 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1776 static u8 TM_Trigger
=0;
1782 tmpRegA
= PHY_QueryRFReg(Adapter
, RF90_PATH_A
, 0x12, 0x078); // 0x12: RF Reg[10:7]
1783 PHY_SetRFReg(Adapter
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4d);
1785 PHY_SetRFReg(Adapter
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4f);
1788 DbgPrint("Trigger and readback ThermalMeter, write RF reg0x2 = 0x4d to 0x4f for 50 times\n");
1790 //DbgPrint("dm_CheckTXPowerTracking() \n");
1791 if(!priv
->btxpower_tracking
)
1795 if(priv
->txpower_count
<= 2)
1797 priv
->txpower_count
++;
1804 //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash
1805 //actually write reg0x02 bit1=0, then bit1=1.
1806 //DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1808 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bRFRegOffsetMask
, 0x4d);
1809 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bRFRegOffsetMask
, 0x4f);
1810 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bRFRegOffsetMask
, 0x4d);
1811 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bRFRegOffsetMask
, 0x4f);
1813 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4d);
1814 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4f);
1815 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4d);
1816 rtl8192_phy_SetRFReg(dev
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4f);
1823 //DbgPrint("Schedule TxPowerTrackingWorkItem\n");
1824 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1825 queue_delayed_work(priv
->priv_wq
,&priv
->txpower_tracking_wq
,0);
1827 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1828 schedule_task(&priv
->txpower_tracking_wq
);
1830 queue_work(priv
->priv_wq
,&priv
->txpower_tracking_wq
);
1839 static void dm_check_txpower_tracking(struct net_device
*dev
)
1841 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1842 //static u32 tx_power_track_counter = 0;
1845 dm_CheckTXPowerTracking_TSSI(dev
);
1847 if(priv
->bDcut
== TRUE
)
1848 dm_CheckTXPowerTracking_TSSI(dev
);
1850 dm_CheckTXPowerTracking_ThermalMeter(dev
);
1853 } // dm_CheckTXPowerTracking
1856 static void dm_CCKTxPowerAdjust_TSSI(struct net_device
*dev
, bool bInCH14
)
1859 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1864 TempVal
= priv
->cck_txbbgain_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[0] +
1865 (priv
->cck_txbbgain_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[1]<<8) ;
1867 rtl8192_setBBreg(dev
, rCCK0_TxFilter1
,bMaskHWord
, TempVal
);
1868 //Write 0xa24 ~ 0xa27
1870 TempVal
= priv
->cck_txbbgain_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[2] +
1871 (priv
->cck_txbbgain_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[3]<<8) +
1872 (priv
->cck_txbbgain_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[4]<<16 )+
1873 (priv
->cck_txbbgain_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[5]<<24);
1874 rtl8192_setBBreg(dev
, rCCK0_TxFilter2
,bMaskDWord
, TempVal
);
1877 TempVal
= priv
->cck_txbbgain_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[6] +
1878 (priv
->cck_txbbgain_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[7]<<8) ;
1880 rtl8192_setBBreg(dev
, rCCK0_DebugPort
,bMaskLWord
, TempVal
);
1884 TempVal
= priv
->cck_txbbgain_ch14_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[0] +
1885 (priv
->cck_txbbgain_ch14_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[1]<<8) ;
1887 rtl8192_setBBreg(dev
, rCCK0_TxFilter1
,bMaskHWord
, TempVal
);
1888 //Write 0xa24 ~ 0xa27
1890 TempVal
= priv
->cck_txbbgain_ch14_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[2] +
1891 (priv
->cck_txbbgain_ch14_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[3]<<8) +
1892 (priv
->cck_txbbgain_ch14_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[4]<<16 )+
1893 (priv
->cck_txbbgain_ch14_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[5]<<24);
1894 rtl8192_setBBreg(dev
, rCCK0_TxFilter2
,bMaskDWord
, TempVal
);
1897 TempVal
= priv
->cck_txbbgain_ch14_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[6] +
1898 (priv
->cck_txbbgain_ch14_table
[priv
->cck_present_attentuation
].ccktxbb_valuearray
[7]<<8) ;
1900 rtl8192_setBBreg(dev
, rCCK0_DebugPort
,bMaskLWord
, TempVal
);
1906 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device
*dev
, bool bInCH14
)
1909 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1915 TempVal
= CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][0] +
1916 (CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][1]<<8) ;
1917 rtl8192_setBBreg(dev
, rCCK0_TxFilter1
, bMaskHWord
, TempVal
);
1918 RT_TRACE(COMP_POWER_TRACKING
, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1919 rCCK0_TxFilter1
, TempVal
);
1920 //Write 0xa24 ~ 0xa27
1922 TempVal
= CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][2] +
1923 (CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][3]<<8) +
1924 (CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][4]<<16 )+
1925 (CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][5]<<24);
1926 rtl8192_setBBreg(dev
, rCCK0_TxFilter2
, bMaskDWord
, TempVal
);
1927 RT_TRACE(COMP_POWER_TRACKING
, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1928 rCCK0_TxFilter2
, TempVal
);
1931 TempVal
= CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][6] +
1932 (CCKSwingTable_Ch1_Ch13
[priv
->CCK_index
][7]<<8) ;
1934 rtl8192_setBBreg(dev
, rCCK0_DebugPort
, bMaskLWord
, TempVal
);
1935 RT_TRACE(COMP_POWER_TRACKING
, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1936 rCCK0_DebugPort
, TempVal
);
1940 // priv->CCKTxPowerAdjustCntNotCh14++; //cosa add for debug.
1942 TempVal
= CCKSwingTable_Ch14
[priv
->CCK_index
][0] +
1943 (CCKSwingTable_Ch14
[priv
->CCK_index
][1]<<8) ;
1945 rtl8192_setBBreg(dev
, rCCK0_TxFilter1
, bMaskHWord
, TempVal
);
1946 RT_TRACE(COMP_POWER_TRACKING
, "CCK chnl 14, reg 0x%x = 0x%x\n",
1947 rCCK0_TxFilter1
, TempVal
);
1948 //Write 0xa24 ~ 0xa27
1950 TempVal
= CCKSwingTable_Ch14
[priv
->CCK_index
][2] +
1951 (CCKSwingTable_Ch14
[priv
->CCK_index
][3]<<8) +
1952 (CCKSwingTable_Ch14
[priv
->CCK_index
][4]<<16 )+
1953 (CCKSwingTable_Ch14
[priv
->CCK_index
][5]<<24);
1954 rtl8192_setBBreg(dev
, rCCK0_TxFilter2
, bMaskDWord
, TempVal
);
1955 RT_TRACE(COMP_POWER_TRACKING
, "CCK chnl 14, reg 0x%x = 0x%x\n",
1956 rCCK0_TxFilter2
, TempVal
);
1959 TempVal
= CCKSwingTable_Ch14
[priv
->CCK_index
][6] +
1960 (CCKSwingTable_Ch14
[priv
->CCK_index
][7]<<8) ;
1962 rtl8192_setBBreg(dev
, rCCK0_DebugPort
, bMaskLWord
, TempVal
);
1963 RT_TRACE(COMP_POWER_TRACKING
,"CCK chnl 14, reg 0x%x = 0x%x\n",
1964 rCCK0_DebugPort
, TempVal
);
1970 extern void dm_cck_txpower_adjust(
1971 struct net_device
*dev
,
1974 { // dm_CCKTxPowerAdjust
1976 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1978 dm_CCKTxPowerAdjust_TSSI(dev
, binch14
);
1980 if(priv
->bDcut
== TRUE
)
1981 dm_CCKTxPowerAdjust_TSSI(dev
, binch14
);
1983 dm_CCKTxPowerAdjust_ThermalMeter(dev
, binch14
);
1989 static void dm_txpower_reset_recovery(
1990 struct net_device
*dev
1993 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1995 RT_TRACE(COMP_POWER_TRACKING
, "Start Reset Recovery ==>\n");
1996 rtl8192_setBBreg(dev
, rOFDM0_XATxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfa_txpowertrackingindex
].txbbgain_value
);
1997 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery: Fill in 0xc80 is %08x\n",priv
->txbbgain_table
[priv
->rfa_txpowertrackingindex
].txbbgain_value
);
1998 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv
->rfa_txpowertrackingindex
);
1999 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv
->txbbgain_table
[priv
->rfa_txpowertrackingindex
].txbb_iq_amplifygain
);
2000 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery: CCK Attenuation is %d dB\n",priv
->cck_present_attentuation
);
2001 dm_cck_txpower_adjust(dev
,priv
->bcck_in_ch14
);
2003 rtl8192_setBBreg(dev
, rOFDM0_XCTxIQImbalance
, bMaskDWord
, priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex
].txbbgain_value
);
2004 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery: Fill in 0xc90 is %08x\n",priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex
].txbbgain_value
);
2005 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv
->rfc_txpowertrackingindex
);
2006 RT_TRACE(COMP_POWER_TRACKING
, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv
->txbbgain_table
[priv
->rfc_txpowertrackingindex
].txbb_iq_amplifygain
);
2008 } // dm_TXPowerResetRecovery
2010 extern void dm_restore_dynamic_mechanism_state(struct net_device
*dev
)
2012 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2013 u32 reg_ratr
= priv
->rate_adaptive
.last_ratr
;
2017 RT_TRACE(COMP_RATE
, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
2022 // Restore previous state for rate adaptive
2024 if(priv
->rate_adaptive
.rate_adaptive_disabled
)
2026 // TODO: Only 11n mode is implemented currently,
2027 if( !(priv
->ieee80211
->mode
==WIRELESS_MODE_N_24G
||
2028 priv
->ieee80211
->mode
==WIRELESS_MODE_N_5G
))
2031 /* 2007/11/15 MH Copy from 8190PCI. */
2033 ratr_value
= reg_ratr
;
2034 if(priv
->rf_type
== RF_1T2R
) // 1T2R, Spatial Stream 2 should be disabled
2036 ratr_value
&=~ (RATE_ALL_OFDM_2SS
);
2037 //DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);
2039 //DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);
2040 //cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);
2041 write_nic_dword(dev
, RATR0
, ratr_value
);
2042 write_nic_byte(dev
, UFWP
, 1);
2043 #if 0 // Disable old code.
2046 index
= (u1Byte
)((((pu4Byte
)(val
))[0]) >> 28);
2047 input_value
= (((pu4Byte
)(val
))[0]) & 0x0fffffff;
2048 // TODO: Correct it. Emily 2007.01.11
2049 PlatformEFIOWrite4Byte(Adapter
, RATR0
+index
*4, input_value
);
2052 //Resore TX Power Tracking Index
2053 if(priv
->btxpower_trackingInit
&& priv
->btxpower_tracking
){
2054 dm_txpower_reset_recovery(dev
);
2058 //Restore BB Initial Gain
2060 dm_bb_initialgain_restore(dev
);
2062 } // DM_RestoreDynamicMechanismState
2064 static void dm_bb_initialgain_restore(struct net_device
*dev
)
2066 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2067 u32 bit_mask
= 0x7f; //Bit0~ Bit6
2069 if(dm_digtable
.dig_algorithm
== DIG_ALGO_BY_RSSI
)
2072 //Disable Initial Gain
2073 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
2074 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x8); // Only clear byte 1 and rewrite.
2075 rtl8192_setBBreg(dev
, rOFDM0_XAAGCCore1
, bit_mask
, (u32
)priv
->initgain_backup
.xaagccore1
);
2076 rtl8192_setBBreg(dev
, rOFDM0_XBAGCCore1
, bit_mask
, (u32
)priv
->initgain_backup
.xbagccore1
);
2077 rtl8192_setBBreg(dev
, rOFDM0_XCAGCCore1
, bit_mask
, (u32
)priv
->initgain_backup
.xcagccore1
);
2078 rtl8192_setBBreg(dev
, rOFDM0_XDAGCCore1
, bit_mask
, (u32
)priv
->initgain_backup
.xdagccore1
);
2079 bit_mask
= bMaskByte2
;
2080 rtl8192_setBBreg(dev
, rCCK0_CCA
, bit_mask
, (u32
)priv
->initgain_backup
.cca
);
2082 RT_TRACE(COMP_DIG
, "dm_BBInitialGainRestore 0xc50 is %x\n",priv
->initgain_backup
.xaagccore1
);
2083 RT_TRACE(COMP_DIG
, "dm_BBInitialGainRestore 0xc58 is %x\n",priv
->initgain_backup
.xbagccore1
);
2084 RT_TRACE(COMP_DIG
, "dm_BBInitialGainRestore 0xc60 is %x\n",priv
->initgain_backup
.xcagccore1
);
2085 RT_TRACE(COMP_DIG
, "dm_BBInitialGainRestore 0xc68 is %x\n",priv
->initgain_backup
.xdagccore1
);
2086 RT_TRACE(COMP_DIG
, "dm_BBInitialGainRestore 0xa0a is %x\n",priv
->initgain_backup
.cca
);
2087 //Enable Initial Gain
2088 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
2089 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x1); // Only clear byte 1 and rewrite.
2091 } // dm_BBInitialGainRestore
2094 extern void dm_backup_dynamic_mechanism_state(struct net_device
*dev
)
2096 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2098 // Fsync to avoid reset
2099 priv
->bswitch_fsync
= false;
2100 priv
->bfsync_processing
= false;
2101 //Backup BB InitialGain
2102 dm_bb_initialgain_backup(dev
);
2104 } // DM_BackupDynamicMechanismState
2107 static void dm_bb_initialgain_backup(struct net_device
*dev
)
2109 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2110 u32 bit_mask
= bMaskByte0
; //Bit0~ Bit6
2112 if(dm_digtable
.dig_algorithm
== DIG_ALGO_BY_RSSI
)
2115 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
2116 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x8); // Only clear byte 1 and rewrite.
2117 priv
->initgain_backup
.xaagccore1
= (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XAAGCCore1
, bit_mask
);
2118 priv
->initgain_backup
.xbagccore1
= (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XBAGCCore1
, bit_mask
);
2119 priv
->initgain_backup
.xcagccore1
= (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XCAGCCore1
, bit_mask
);
2120 priv
->initgain_backup
.xdagccore1
= (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XDAGCCore1
, bit_mask
);
2121 bit_mask
= bMaskByte2
;
2122 priv
->initgain_backup
.cca
= (u8
)rtl8192_QueryBBReg(dev
, rCCK0_CCA
, bit_mask
);
2124 RT_TRACE(COMP_DIG
, "BBInitialGainBackup 0xc50 is %x\n",priv
->initgain_backup
.xaagccore1
);
2125 RT_TRACE(COMP_DIG
, "BBInitialGainBackup 0xc58 is %x\n",priv
->initgain_backup
.xbagccore1
);
2126 RT_TRACE(COMP_DIG
, "BBInitialGainBackup 0xc60 is %x\n",priv
->initgain_backup
.xcagccore1
);
2127 RT_TRACE(COMP_DIG
, "BBInitialGainBackup 0xc68 is %x\n",priv
->initgain_backup
.xdagccore1
);
2128 RT_TRACE(COMP_DIG
, "BBInitialGainBackup 0xa0a is %x\n",priv
->initgain_backup
.cca
);
2130 } // dm_BBInitialGainBakcup
2133 /*-----------------------------------------------------------------------------
2134 * Function: dm_change_dynamic_initgain_thresh()
2146 * 05/29/2008 amy Create Version 0 porting from windows code.
2148 *---------------------------------------------------------------------------*/
2149 extern void dm_change_dynamic_initgain_thresh(struct net_device
*dev
,
2154 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2155 if(dm_type
== DIG_TYPE_THRESH_HIGHPWR_HIGH
)
2156 priv
->MidHighPwrTHR_L2
= (u8
)dm_value
;
2157 else if(dm_type
== DIG_TYPE_THRESH_HIGHPWR_LOW
)
2158 priv
->MidHighPwrTHR_L1
= (u8
)dm_value
;
2161 if (dm_type
== DIG_TYPE_THRESH_HIGH
)
2163 dm_digtable
.rssi_high_thresh
= dm_value
;
2165 else if (dm_type
== DIG_TYPE_THRESH_LOW
)
2167 dm_digtable
.rssi_low_thresh
= dm_value
;
2169 else if (dm_type
== DIG_TYPE_THRESH_HIGHPWR_HIGH
)
2171 dm_digtable
.rssi_high_power_highthresh
= dm_value
;
2173 else if (dm_type
== DIG_TYPE_THRESH_HIGHPWR_HIGH
)
2175 dm_digtable
.rssi_high_power_highthresh
= dm_value
;
2177 else if (dm_type
== DIG_TYPE_ENABLE
)
2179 dm_digtable
.dig_state
= DM_STA_DIG_MAX
;
2180 dm_digtable
.dig_enable_flag
= true;
2182 else if (dm_type
== DIG_TYPE_DISABLE
)
2184 dm_digtable
.dig_state
= DM_STA_DIG_MAX
;
2185 dm_digtable
.dig_enable_flag
= false;
2187 else if (dm_type
== DIG_TYPE_DBG_MODE
)
2189 if(dm_value
>= DM_DBG_MAX
)
2190 dm_value
= DM_DBG_OFF
;
2191 dm_digtable
.dbg_mode
= (u8
)dm_value
;
2193 else if (dm_type
== DIG_TYPE_RSSI
)
2197 dm_digtable
.rssi_val
= (long)dm_value
;
2199 else if (dm_type
== DIG_TYPE_ALGORITHM
)
2201 if (dm_value
>= DIG_ALGO_MAX
)
2202 dm_value
= DIG_ALGO_BY_FALSE_ALARM
;
2203 if(dm_digtable
.dig_algorithm
!= (u8
)dm_value
)
2204 dm_digtable
.dig_algorithm_switch
= 1;
2205 dm_digtable
.dig_algorithm
= (u8
)dm_value
;
2207 else if (dm_type
== DIG_TYPE_BACKOFF
)
2211 dm_digtable
.backoff_val
= (u8
)dm_value
;
2213 else if(dm_type
== DIG_TYPE_RX_GAIN_MIN
)
2217 dm_digtable
.rx_gain_range_min
= (u8
)dm_value
;
2219 else if(dm_type
== DIG_TYPE_RX_GAIN_MAX
)
2223 dm_digtable
.rx_gain_range_max
= (u8
)dm_value
;
2225 } /* DM_ChangeDynamicInitGainThresh */
2227 dm_change_fsync_setting(
2228 struct net_device
*dev
,
2232 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2234 if (DM_Type
== 0) // monitor 0xc38 register
2238 priv
->framesyncMonitor
= (u8
)DM_Value
;
2239 //DbgPrint("pHalData->framesyncMonitor = %d", pHalData->framesyncMonitor);
2244 dm_change_rxpath_selection_setting(
2245 struct net_device
*dev
,
2249 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2250 prate_adaptive pRA
= (prate_adaptive
)&(priv
->rate_adaptive
);
2257 DM_RxPathSelTable
.Enable
= (u8
)DM_Value
;
2259 else if(DM_Type
== 1)
2263 DM_RxPathSelTable
.DbgMode
= (u8
)DM_Value
;
2265 else if(DM_Type
== 2)
2269 DM_RxPathSelTable
.SS_TH_low
= (u8
)DM_Value
;
2271 else if(DM_Type
== 3)
2275 DM_RxPathSelTable
.diff_TH
= (u8
)DM_Value
;
2277 else if(DM_Type
== 4)
2279 if(DM_Value
>= CCK_Rx_Version_MAX
)
2280 DM_Value
= CCK_Rx_Version_1
;
2281 DM_RxPathSelTable
.cck_method
= (u8
)DM_Value
;
2283 else if(DM_Type
== 10)
2287 DM_RxPathSelTable
.rf_rssi
[0] = (u8
)DM_Value
;
2289 else if(DM_Type
== 11)
2293 DM_RxPathSelTable
.rf_rssi
[1] = (u8
)DM_Value
;
2295 else if(DM_Type
== 12)
2299 DM_RxPathSelTable
.rf_rssi
[2] = (u8
)DM_Value
;
2301 else if(DM_Type
== 13)
2305 DM_RxPathSelTable
.rf_rssi
[3] = (u8
)DM_Value
;
2307 else if(DM_Type
== 20)
2311 pRA
->ping_rssi_enable
= (u8
)DM_Value
;
2313 else if(DM_Type
== 21)
2317 pRA
->ping_rssi_thresh_for_ra
= DM_Value
;
2322 extern void dm_force_tx_fw_info(struct net_device
*dev
,
2326 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2328 if (force_type
== 0) // don't force TxSC
2330 //DbgPrint("Set Force SubCarrier Off\n");
2331 priv
->tx_fwinfo_force_subcarriermode
= 0;
2333 else if(force_type
== 1) //force
2335 //DbgPrint("Set Force SubCarrier On\n");
2336 priv
->tx_fwinfo_force_subcarriermode
= 1;
2339 priv
->tx_fwinfo_force_subcarrierval
= (u8
)force_value
;
2344 /*-----------------------------------------------------------------------------
2345 * Function: dm_dig_init()
2347 * Overview: Set DIG scheme init value.
2357 * 05/15/2008 amy Create Version 0 porting from windows code.
2359 *---------------------------------------------------------------------------*/
2360 static void dm_dig_init(struct net_device
*dev
)
2362 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2363 /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
2364 dm_digtable
.dig_enable_flag
= true;
2365 dm_digtable
.dig_algorithm
= DIG_ALGO_BY_RSSI
;
2366 dm_digtable
.dbg_mode
= DM_DBG_OFF
; //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig
2367 dm_digtable
.dig_algorithm_switch
= 0;
2369 /* 2007/10/04 MH Define init gain threshol. */
2370 dm_digtable
.dig_state
= DM_STA_DIG_MAX
;
2371 dm_digtable
.dig_highpwr_state
= DM_STA_DIG_MAX
;
2372 dm_digtable
.initialgain_lowerbound_state
= false;
2374 dm_digtable
.rssi_low_thresh
= DM_DIG_THRESH_LOW
;
2375 dm_digtable
.rssi_high_thresh
= DM_DIG_THRESH_HIGH
;
2377 dm_digtable
.rssi_high_power_lowthresh
= DM_DIG_HIGH_PWR_THRESH_LOW
;
2378 dm_digtable
.rssi_high_power_highthresh
= DM_DIG_HIGH_PWR_THRESH_HIGH
;
2380 dm_digtable
.rssi_val
= 50; //for new dig debug rssi value
2381 dm_digtable
.backoff_val
= DM_DIG_BACKOFF
;
2382 dm_digtable
.rx_gain_range_max
= DM_DIG_MAX
;
2383 if(priv
->CustomerID
== RT_CID_819x_Netcore
)
2384 dm_digtable
.rx_gain_range_min
= DM_DIG_MIN_Netcore
;
2386 dm_digtable
.rx_gain_range_min
= DM_DIG_MIN
;
2391 /*-----------------------------------------------------------------------------
2392 * Function: dm_ctrl_initgain_byrssi()
2394 * Overview: Driver must monitor RSSI and notify firmware to change initial
2395 * gain according to different threshold. BB team provide the
2396 * suggested solution.
2398 * Input: struct net_device *dev
2406 * 05/27/2008 amy Create Version 0 porting from windows code.
2407 *---------------------------------------------------------------------------*/
2408 static void dm_ctrl_initgain_byrssi(struct net_device
*dev
)
2411 if (dm_digtable
.dig_enable_flag
== false)
2414 if(dm_digtable
.dig_algorithm
== DIG_ALGO_BY_FALSE_ALARM
)
2415 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev
);
2416 else if(dm_digtable
.dig_algorithm
== DIG_ALGO_BY_RSSI
)
2417 dm_ctrl_initgain_byrssi_by_driverrssi(dev
);
2424 static void dm_ctrl_initgain_byrssi_by_driverrssi(
2425 struct net_device
*dev
)
2427 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2431 if (dm_digtable
.dig_enable_flag
== false)
2434 //DbgPrint("Dig by Sw Rssi \n");
2435 if(dm_digtable
.dig_algorithm_switch
) // if swithed algorithm, we have to disable FW Dig.
2437 if(fw_dig
<= 3) // execute several times to make sure the FW Dig is disabled
2440 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x8); // Only clear byte 1 and rewrite.
2442 dm_digtable
.dig_state
= DM_STA_DIG_OFF
; //fw dig off.
2445 if(priv
->ieee80211
->state
== IEEE80211_LINKED
)
2446 dm_digtable
.cur_connect_state
= DIG_CONNECT
;
2448 dm_digtable
.cur_connect_state
= DIG_DISCONNECT
;
2450 //DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d \n",
2451 //DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);
2453 if(dm_digtable
.dbg_mode
== DM_DBG_OFF
)
2454 dm_digtable
.rssi_val
= priv
->undecorated_smoothed_pwdb
;
2455 //DbgPrint("DM_DigTable.Rssi_val = %d \n", DM_DigTable.Rssi_val);
2456 dm_initial_gain(dev
);
2459 if(dm_digtable
.dig_algorithm_switch
)
2460 dm_digtable
.dig_algorithm_switch
= 0;
2461 dm_digtable
.pre_connect_state
= dm_digtable
.cur_connect_state
;
2463 } /* dm_CtrlInitGainByRssi */
2465 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
2466 struct net_device
*dev
)
2468 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2469 static u32 reset_cnt
= 0;
2472 if (dm_digtable
.dig_enable_flag
== false)
2475 if(dm_digtable
.dig_algorithm_switch
)
2477 dm_digtable
.dig_state
= DM_STA_DIG_MAX
;
2480 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x1); // Only clear byte 1 and rewrite.
2481 dm_digtable
.dig_algorithm_switch
= 0;
2484 if (priv
->ieee80211
->state
!= IEEE80211_LINKED
)
2487 // For smooth, we can not change DIG state.
2488 if ((priv
->undecorated_smoothed_pwdb
> dm_digtable
.rssi_low_thresh
) &&
2489 (priv
->undecorated_smoothed_pwdb
< dm_digtable
.rssi_high_thresh
))
2493 //DbgPrint("Dig by Fw False Alarm\n");
2494 //if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)
2495 /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
2496 pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
2497 DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
2498 /* 1. When RSSI decrease, We have to judge if it is smaller than a treshold
2499 and then execute below step. */
2500 if ((priv
->undecorated_smoothed_pwdb
<= dm_digtable
.rssi_low_thresh
))
2502 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
2503 will be reset to init value. We must prevent the condition. */
2504 if (dm_digtable
.dig_state
== DM_STA_DIG_OFF
&&
2505 (priv
->reset_count
== reset_cnt
))
2511 reset_cnt
= priv
->reset_count
;
2514 // If DIG is off, DIG high power state must reset.
2515 dm_digtable
.dig_highpwr_state
= DM_STA_DIG_MAX
;
2516 dm_digtable
.dig_state
= DM_STA_DIG_OFF
;
2519 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x8); // Only clear byte 1 and rewrite.
2521 // 1.2 Set initial gain.
2522 write_nic_byte(dev
, rOFDM0_XAAGCCore1
, 0x17);
2523 write_nic_byte(dev
, rOFDM0_XBAGCCore1
, 0x17);
2524 write_nic_byte(dev
, rOFDM0_XCAGCCore1
, 0x17);
2525 write_nic_byte(dev
, rOFDM0_XDAGCCore1
, 0x17);
2527 // 1.3 Lower PD_TH for OFDM.
2528 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
2530 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2531 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2533 rtl8192_setBBreg(dev
, (rOFDM0_XATxAFE
+3), bMaskByte0
, 0x00);
2536 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x40);
2538 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x00);
2541 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2542 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2544 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2548 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2551 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x42);
2553 // 1.4 Lower CS ratio for CCK.
2554 write_nic_byte(dev
, 0xa0a, 0x08);
2556 // 1.5 Higher EDCCA.
2557 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
2562 /* 2. When RSSI increase, We have to judge if it is larger than a treshold
2563 and then execute below step. */
2564 if ((priv
->undecorated_smoothed_pwdb
>= dm_digtable
.rssi_high_thresh
) )
2568 if (dm_digtable
.dig_state
== DM_STA_DIG_ON
&&
2569 (priv
->reset_count
== reset_cnt
))
2571 dm_ctrl_initgain_byrssi_highpwr(dev
);
2576 if (priv
->reset_count
!= reset_cnt
)
2579 reset_cnt
= priv
->reset_count
;
2582 dm_digtable
.dig_state
= DM_STA_DIG_ON
;
2583 //DbgPrint("DIG ON\n\r");
2585 // 2.1 Set initial gain.
2586 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
2587 if (reset_flag
== 1)
2589 write_nic_byte(dev
, rOFDM0_XAAGCCore1
, 0x2c);
2590 write_nic_byte(dev
, rOFDM0_XBAGCCore1
, 0x2c);
2591 write_nic_byte(dev
, rOFDM0_XCAGCCore1
, 0x2c);
2592 write_nic_byte(dev
, rOFDM0_XDAGCCore1
, 0x2c);
2596 write_nic_byte(dev
, rOFDM0_XAAGCCore1
, 0x20);
2597 write_nic_byte(dev
, rOFDM0_XBAGCCore1
, 0x20);
2598 write_nic_byte(dev
, rOFDM0_XCAGCCore1
, 0x20);
2599 write_nic_byte(dev
, rOFDM0_XDAGCCore1
, 0x20);
2602 // 2.2 Higher PD_TH for OFDM.
2603 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
2605 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2606 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2608 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x42);
2610 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x20);
2613 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2614 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2616 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2619 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
2622 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x44);
2624 // 2.3 Higher CS ratio for CCK.
2625 write_nic_byte(dev
, 0xa0a, 0xcd);
2628 /* 2008/01/11 MH 90/92 series are the same. */
2629 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);
2632 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x1); // Only clear byte 1 and rewrite.
2636 dm_ctrl_initgain_byrssi_highpwr(dev
);
2638 } /* dm_CtrlInitGainByRssi */
2641 /*-----------------------------------------------------------------------------
2642 * Function: dm_ctrl_initgain_byrssi_highpwr()
2654 * 05/28/2008 amy Create Version 0 porting from windows code.
2656 *---------------------------------------------------------------------------*/
2657 static void dm_ctrl_initgain_byrssi_highpwr(
2658 struct net_device
* dev
)
2660 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2661 static u32 reset_cnt_highpwr
= 0;
2663 // For smooth, we can not change high power DIG state in the range.
2664 if ((priv
->undecorated_smoothed_pwdb
> dm_digtable
.rssi_high_power_lowthresh
) &&
2665 (priv
->undecorated_smoothed_pwdb
< dm_digtable
.rssi_high_power_highthresh
))
2670 /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
2671 it is larger than a treshold and then execute below step. */
2672 // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
2673 if (priv
->undecorated_smoothed_pwdb
>= dm_digtable
.rssi_high_power_highthresh
)
2675 if (dm_digtable
.dig_highpwr_state
== DM_STA_DIG_ON
&&
2676 (priv
->reset_count
== reset_cnt_highpwr
))
2679 dm_digtable
.dig_highpwr_state
= DM_STA_DIG_ON
;
2681 // 3.1 Higher PD_TH for OFDM for high power state.
2682 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
2685 rtl8192_setBBreg(dev
, (rOFDM0_XATxAFE
+3), bMaskByte0
, 0x10);
2688 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x41);
2690 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x10);
2693 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2694 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2699 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x43);
2703 if (dm_digtable
.dig_highpwr_state
== DM_STA_DIG_OFF
&&
2704 (priv
->reset_count
== reset_cnt_highpwr
))
2707 dm_digtable
.dig_highpwr_state
= DM_STA_DIG_OFF
;
2709 if (priv
->undecorated_smoothed_pwdb
< dm_digtable
.rssi_high_power_lowthresh
&&
2710 priv
->undecorated_smoothed_pwdb
>= dm_digtable
.rssi_high_thresh
)
2712 // 3.2 Recover PD_TH for OFDM for normal power region.
2713 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
2716 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x42);
2718 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x20);
2720 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2721 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2726 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x44);
2730 reset_cnt_highpwr
= priv
->reset_count
;
2732 } /* dm_CtrlInitGainByRssiHighPwr */
2735 static void dm_initial_gain(
2736 struct net_device
* dev
)
2738 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2740 static u8 initialized
=0, force_write
=0;
2741 static u32 reset_cnt
=0;
2743 if(dm_digtable
.dig_algorithm_switch
)
2749 if(dm_digtable
.pre_connect_state
== dm_digtable
.cur_connect_state
)
2751 if(dm_digtable
.cur_connect_state
== DIG_CONNECT
)
2753 if((dm_digtable
.rssi_val
+10-dm_digtable
.backoff_val
) > dm_digtable
.rx_gain_range_max
)
2754 dm_digtable
.cur_ig_value
= dm_digtable
.rx_gain_range_max
;
2755 else if((dm_digtable
.rssi_val
+10-dm_digtable
.backoff_val
) < dm_digtable
.rx_gain_range_min
)
2756 dm_digtable
.cur_ig_value
= dm_digtable
.rx_gain_range_min
;
2758 dm_digtable
.cur_ig_value
= dm_digtable
.rssi_val
+10-dm_digtable
.backoff_val
;
2760 else //current state is disconnected
2762 if(dm_digtable
.cur_ig_value
== 0)
2763 dm_digtable
.cur_ig_value
= priv
->DefaultInitialGain
[0];
2765 dm_digtable
.cur_ig_value
= dm_digtable
.pre_ig_value
;
2768 else // disconnected -> connected or connected -> disconnected
2770 dm_digtable
.cur_ig_value
= priv
->DefaultInitialGain
[0];
2771 dm_digtable
.pre_ig_value
= 0;
2773 //DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);
2775 // if silent reset happened, we should rewrite the values back
2776 if(priv
->reset_count
!= reset_cnt
)
2779 reset_cnt
= priv
->reset_count
;
2782 if(dm_digtable
.pre_ig_value
!= read_nic_byte(dev
, rOFDM0_XAAGCCore1
))
2786 if((dm_digtable
.pre_ig_value
!= dm_digtable
.cur_ig_value
)
2787 || !initialized
|| force_write
)
2789 initial_gain
= (u8
)dm_digtable
.cur_ig_value
;
2790 //DbgPrint("Write initial gain = 0x%x\n", initial_gain);
2791 // Set initial gain.
2792 write_nic_byte(dev
, rOFDM0_XAAGCCore1
, initial_gain
);
2793 write_nic_byte(dev
, rOFDM0_XBAGCCore1
, initial_gain
);
2794 write_nic_byte(dev
, rOFDM0_XCAGCCore1
, initial_gain
);
2795 write_nic_byte(dev
, rOFDM0_XDAGCCore1
, initial_gain
);
2796 dm_digtable
.pre_ig_value
= dm_digtable
.cur_ig_value
;
2803 static void dm_pd_th(
2804 struct net_device
* dev
)
2806 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2807 static u8 initialized
=0, force_write
=0;
2808 static u32 reset_cnt
= 0;
2810 if(dm_digtable
.dig_algorithm_switch
)
2816 if(dm_digtable
.pre_connect_state
== dm_digtable
.cur_connect_state
)
2818 if(dm_digtable
.cur_connect_state
== DIG_CONNECT
)
2820 if (dm_digtable
.rssi_val
>= dm_digtable
.rssi_high_power_highthresh
)
2821 dm_digtable
.curpd_thstate
= DIG_PD_AT_HIGH_POWER
;
2822 else if ((dm_digtable
.rssi_val
<= dm_digtable
.rssi_low_thresh
))
2823 dm_digtable
.curpd_thstate
= DIG_PD_AT_LOW_POWER
;
2824 else if ((dm_digtable
.rssi_val
>= dm_digtable
.rssi_high_thresh
) &&
2825 (dm_digtable
.rssi_val
< dm_digtable
.rssi_high_power_lowthresh
))
2826 dm_digtable
.curpd_thstate
= DIG_PD_AT_NORMAL_POWER
;
2828 dm_digtable
.curpd_thstate
= dm_digtable
.prepd_thstate
;
2832 dm_digtable
.curpd_thstate
= DIG_PD_AT_LOW_POWER
;
2835 else // disconnected -> connected or connected -> disconnected
2837 dm_digtable
.curpd_thstate
= DIG_PD_AT_LOW_POWER
;
2840 // if silent reset happened, we should rewrite the values back
2841 if(priv
->reset_count
!= reset_cnt
)
2844 reset_cnt
= priv
->reset_count
;
2848 if((dm_digtable
.prepd_thstate
!= dm_digtable
.curpd_thstate
) ||
2849 (initialized
<=3) || force_write
)
2851 //DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);
2852 if(dm_digtable
.curpd_thstate
== DIG_PD_AT_LOW_POWER
)
2854 // Lower PD_TH for OFDM.
2855 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
2857 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2858 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2860 rtl8192_setBBreg(dev
, (rOFDM0_XATxAFE
+3), bMaskByte0
, 0x00);
2863 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x40);
2865 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x00);
2868 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2869 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2873 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x42);
2875 else if(dm_digtable
.curpd_thstate
== DIG_PD_AT_NORMAL_POWER
)
2877 // Higher PD_TH for OFDM.
2878 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
2880 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2881 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2883 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x42);
2885 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x20);
2887 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2888 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2892 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x44);
2894 else if(dm_digtable
.curpd_thstate
== DIG_PD_AT_HIGH_POWER
)
2896 // Higher PD_TH for OFDM for high power state.
2897 if (priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
)
2900 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x41);
2902 write_nic_byte(dev
, (rOFDM0_XATxAFE
+3), 0x10);
2904 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2905 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2909 write_nic_byte(dev
, rOFDM0_RxDetector1
, 0x43);
2911 dm_digtable
.prepd_thstate
= dm_digtable
.curpd_thstate
;
2912 if(initialized
<= 3)
2919 static void dm_cs_ratio(
2920 struct net_device
* dev
)
2922 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2923 static u8 initialized
=0,force_write
=0;
2924 static u32 reset_cnt
= 0;
2926 if(dm_digtable
.dig_algorithm_switch
)
2932 if(dm_digtable
.pre_connect_state
== dm_digtable
.cur_connect_state
)
2934 if(dm_digtable
.cur_connect_state
== DIG_CONNECT
)
2936 if ((dm_digtable
.rssi_val
<= dm_digtable
.rssi_low_thresh
))
2937 dm_digtable
.curcs_ratio_state
= DIG_CS_RATIO_LOWER
;
2938 else if ((dm_digtable
.rssi_val
>= dm_digtable
.rssi_high_thresh
) )
2939 dm_digtable
.curcs_ratio_state
= DIG_CS_RATIO_HIGHER
;
2941 dm_digtable
.curcs_ratio_state
= dm_digtable
.precs_ratio_state
;
2945 dm_digtable
.curcs_ratio_state
= DIG_CS_RATIO_LOWER
;
2948 else // disconnected -> connected or connected -> disconnected
2950 dm_digtable
.curcs_ratio_state
= DIG_CS_RATIO_LOWER
;
2953 // if silent reset happened, we should rewrite the values back
2954 if(priv
->reset_count
!= reset_cnt
)
2957 reset_cnt
= priv
->reset_count
;
2962 if((dm_digtable
.precs_ratio_state
!= dm_digtable
.curcs_ratio_state
) ||
2963 !initialized
|| force_write
)
2965 //DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);
2966 if(dm_digtable
.curcs_ratio_state
== DIG_CS_RATIO_LOWER
)
2968 // Lower CS ratio for CCK.
2969 write_nic_byte(dev
, 0xa0a, 0x08);
2971 else if(dm_digtable
.curcs_ratio_state
== DIG_CS_RATIO_HIGHER
)
2973 // Higher CS ratio for CCK.
2974 write_nic_byte(dev
, 0xa0a, 0xcd);
2976 dm_digtable
.precs_ratio_state
= dm_digtable
.curcs_ratio_state
;
2983 extern void dm_init_edca_turbo(struct net_device
* dev
)
2985 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2987 priv
->bcurrent_turbo_EDCA
= false;
2988 priv
->ieee80211
->bis_any_nonbepkts
= false;
2989 priv
->bis_cur_rdlstate
= false;
2990 } // dm_init_edca_turbo
2993 static void dm_check_edca_turbo(
2994 struct net_device
* dev
)
2996 struct r8192_priv
*priv
= ieee80211_priv(dev
);
2997 PRT_HIGH_THROUGHPUT pHTInfo
= priv
->ieee80211
->pHTInfo
;
2998 //PSTA_QOS pStaQos = pMgntInfo->pStaQos;
3000 // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
3001 static unsigned long lastTxOkCnt
= 0;
3002 static unsigned long lastRxOkCnt
= 0;
3003 unsigned long curTxOkCnt
= 0;
3004 unsigned long curRxOkCnt
= 0;
3007 // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
3008 // should follow the settings from QAP. By Bruce, 2007-12-07.
3011 if(priv
->ieee80211
->state
!= IEEE80211_LINKED
)
3012 goto dm_CheckEdcaTurbo_EXIT
;
3014 // We do not turn on EDCA turbo mode for some AP that has IOT issue
3015 if(priv
->ieee80211
->pHTInfo
->IOTAction
& HT_IOT_ACT_DISABLE_EDCA_TURBO
)
3016 goto dm_CheckEdcaTurbo_EXIT
;
3019 u8
* peername
[11] = {"unknown", "realtek", "realtek_92se", "broadcom", "ralink", "atheros", "cisco", "marvell", "92u_softap", "self_softap"};
3020 static int wb_tmp
= 0;
3022 printk("%s():iot peer is %#x:%s, bssid:"MAC_FMT
"\n",__FUNCTION__
,pHTInfo
->IOTPeer
,peername
[pHTInfo
->IOTPeer
], MAC_ARG(priv
->ieee80211
->current_network
.bssid
));
3026 // Check the status for current condition.
3027 if(!priv
->ieee80211
->bis_any_nonbepkts
)
3029 curTxOkCnt
= priv
->stats
.txbytesunicast
- lastTxOkCnt
;
3030 curRxOkCnt
= priv
->stats
.rxbytesunicast
- lastRxOkCnt
;
3032 // Modify EDCA parameters selection bias
3033 // For some APs, use downlink EDCA parameters for uplink+downlink
3034 if(priv
->ieee80211
->pHTInfo
->IOTAction
& HT_IOT_ACT_EDCA_BIAS_ON_RX
)
3036 if(curTxOkCnt
> 4*curRxOkCnt
)
3038 if(priv
->bis_cur_rdlstate
|| !priv
->bcurrent_turbo_EDCA
)
3040 write_nic_dword(dev
, EDCAPARA_BE
, edca_setting_UL
[pHTInfo
->IOTPeer
]);
3041 priv
->bis_cur_rdlstate
= false;
3046 if(!priv
->bis_cur_rdlstate
|| !priv
->bcurrent_turbo_EDCA
)
3048 write_nic_dword(dev
, EDCAPARA_BE
, edca_setting_DL
[pHTInfo
->IOTPeer
]);
3049 priv
->bis_cur_rdlstate
= true;
3052 priv
->bcurrent_turbo_EDCA
= true;
3056 if(curRxOkCnt
> 4*curTxOkCnt
)
3058 if(!priv
->bis_cur_rdlstate
|| !priv
->bcurrent_turbo_EDCA
)
3060 write_nic_dword(dev
, EDCAPARA_BE
, edca_setting_DL
[pHTInfo
->IOTPeer
]);
3061 priv
->bis_cur_rdlstate
= true;
3066 if(priv
->bis_cur_rdlstate
|| !priv
->bcurrent_turbo_EDCA
)
3068 write_nic_dword(dev
, EDCAPARA_BE
, edca_setting_UL
[pHTInfo
->IOTPeer
]);
3069 priv
->bis_cur_rdlstate
= false;
3072 priv
->bcurrent_turbo_EDCA
= true;
3075 // For RT-AP, we needs to turn it on when Rx>Tx
3076 if(curRxOkCnt
> 4*curTxOkCnt
)
3078 //printk("%s():curRxOkCnt > 4*curTxOkCnt\n");
3079 if(!priv
->bis_cur_rdlstate
|| !priv
->bcurrent_turbo_EDCA
)
3081 write_nic_dword(dev
, EDCAPARA_BE
, edca_setting_DL
[pHTInfo
->IOTPeer
]);
3082 priv
->bis_cur_rdlstate
= true;
3088 //printk("%s():curRxOkCnt < 4*curTxOkCnt\n");
3089 if(priv
->bis_cur_rdlstate
|| !priv
->bcurrent_turbo_EDCA
)
3091 write_nic_dword(dev
, EDCAPARA_BE
, edca_setting_UL
[pHTInfo
->IOTPeer
]);
3092 priv
->bis_cur_rdlstate
= false;
3097 priv
->bcurrent_turbo_EDCA
= true;
3103 // Turn Off EDCA turbo here.
3104 // Restore original EDCA according to the declaration of AP.
3106 if(priv
->bcurrent_turbo_EDCA
)
3112 struct ieee80211_qos_parameters
*qos_parameters
= &priv
->ieee80211
->current_network
.qos_data
.parameters
;
3113 u8 mode
= priv
->ieee80211
->mode
;
3115 // For Each time updating EDCA parameter, reset EDCA turbo mode status.
3116 dm_init_edca_turbo(dev
);
3117 u1bAIFS
= qos_parameters
->aifs
[0] * ((mode
&(IEEE_G
|IEEE_N_24G
)) ?9:20) + aSifsTime
;
3118 u4bAcParam
= ((((u32
)(qos_parameters
->tx_op_limit
[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET
)|
3119 (((u32
)(qos_parameters
->cw_max
[0]))<< AC_PARAM_ECW_MAX_OFFSET
)|
3120 (((u32
)(qos_parameters
->cw_min
[0]))<< AC_PARAM_ECW_MIN_OFFSET
)|
3121 ((u32
)u1bAIFS
<< AC_PARAM_AIFS_OFFSET
));
3122 //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
3123 write_nic_dword(dev
, EDCAPARA_BE
, u4bAcParam
);
3126 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
3128 // TODO: Modified this part and try to set acm control in only 1 IO processing!!
3130 PACI_AIFSN pAciAifsn
= (PACI_AIFSN
)&(qos_parameters
->aifs
[0]);
3131 u8 AcmCtrl
= read_nic_byte( dev
, AcmHwCtrl
);
3132 if( pAciAifsn
->f
.ACM
)
3134 AcmCtrl
|= AcmHw_BeqEn
;
3138 AcmCtrl
&= (~AcmHw_BeqEn
);
3141 RT_TRACE( COMP_QOS
,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl
) ;
3142 write_nic_byte(dev
, AcmHwCtrl
, AcmCtrl
);
3145 priv
->bcurrent_turbo_EDCA
= false;
3150 dm_CheckEdcaTurbo_EXIT
:
3151 // Set variables for next time.
3152 priv
->ieee80211
->bis_any_nonbepkts
= false;
3153 lastTxOkCnt
= priv
->stats
.txbytesunicast
;
3154 lastRxOkCnt
= priv
->stats
.rxbytesunicast
;
3155 } // dm_CheckEdcaTurbo
3158 extern void DM_CTSToSelfSetting(struct net_device
* dev
,u32 DM_Type
, u32 DM_Value
)
3160 struct r8192_priv
*priv
= ieee80211_priv((struct net_device
*)dev
);
3162 if (DM_Type
== 0) // CTS to self disable/enable
3166 priv
->ieee80211
->bCTSToSelfEnable
= (bool)DM_Value
;
3167 //DbgPrint("pMgntInfo->bCTSToSelfEnable = %d\n", pMgntInfo->bCTSToSelfEnable);
3169 else if(DM_Type
== 1) //CTS to self Th
3173 priv
->ieee80211
->CTSToSelfTH
= (u8
)DM_Value
;
3174 //DbgPrint("pMgntInfo->CTSToSelfTH = %d\n", pMgntInfo->CTSToSelfTH);
3178 static void dm_init_ctstoself(struct net_device
* dev
)
3180 struct r8192_priv
*priv
= ieee80211_priv((struct net_device
*)dev
);
3182 priv
->ieee80211
->bCTSToSelfEnable
= TRUE
;
3183 priv
->ieee80211
->CTSToSelfTH
= CTSToSelfTHVal
;
3186 static void dm_ctstoself(struct net_device
*dev
)
3188 struct r8192_priv
*priv
= ieee80211_priv((struct net_device
*)dev
);
3189 PRT_HIGH_THROUGHPUT pHTInfo
= priv
->ieee80211
->pHTInfo
;
3190 static unsigned long lastTxOkCnt
= 0;
3191 static unsigned long lastRxOkCnt
= 0;
3192 unsigned long curTxOkCnt
= 0;
3193 unsigned long curRxOkCnt
= 0;
3195 if(priv
->ieee80211
->bCTSToSelfEnable
!= TRUE
)
3197 pHTInfo
->IOTAction
&= ~HT_IOT_ACT_FORCED_CTS2SELF
;
3202 2. Linksys350/Linksys300N
3203 3. <50 disable, >55 enable
3206 if(pHTInfo
->IOTPeer
== HT_IOT_PEER_BROADCOM
)
3208 curTxOkCnt
= priv
->stats
.txbytesunicast
- lastTxOkCnt
;
3209 curRxOkCnt
= priv
->stats
.rxbytesunicast
- lastRxOkCnt
;
3210 if(curRxOkCnt
> 4*curTxOkCnt
) //downlink, disable CTS to self
3212 pHTInfo
->IOTAction
&= ~HT_IOT_ACT_FORCED_CTS2SELF
;
3213 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");
3218 pHTInfo
->IOTAction
|= HT_IOT_ACT_FORCED_CTS2SELF
;
3220 if(priv
->undecorated_smoothed_pwdb
< priv
->ieee80211
->CTSToSelfTH
) // disable CTS to self
3222 pHTInfo
->IOTAction
&= ~HT_IOT_ACT_FORCED_CTS2SELF
;
3223 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled\n");
3225 else if(priv
->undecorated_smoothed_pwdb
>= (priv
->ieee80211
->CTSToSelfTH
+5)) // enable CTS to self
3227 pHTInfo
->IOTAction
|= HT_IOT_ACT_FORCED_CTS2SELF
;
3228 //DbgPrint("dm_CTSToSelf() ==> CTS to self enabled\n");
3233 lastTxOkCnt
= priv
->stats
.txbytesunicast
;
3234 lastRxOkCnt
= priv
->stats
.rxbytesunicast
;
3240 /*-----------------------------------------------------------------------------
3241 * Function: dm_rf_operation_test_callback()
3243 * Overview: Only for RF operation test now.
3253 * 05/29/2008 amy Create Version 0 porting from windows code.
3255 *---------------------------------------------------------------------------*/
3256 extern void dm_rf_operation_test_callback(unsigned long dev
)
3258 // struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
3262 for(erfpath
=0; erfpath
<4; erfpath
++)
3264 //DbgPrint("Set RF-%d\n\r", eRFPath);
3265 //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
3270 //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500);
3276 //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500);
3281 PHY_SetRFReg(Adapter
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4d);
3283 PHY_SetRFReg(Adapter
, RF90_PATH_A
, 0x02, bMask12Bits
, 0x4f);
3285 PHY_SetRFReg(Adapter
, RF90_PATH_C
, 0x02, bMask12Bits
, 0x4d);
3287 PHY_SetRFReg(Adapter
, RF90_PATH_C
, 0x02, bMask12Bits
, 0x4f);
3292 PHY_QueryRFReg(Adapter
, RF90_PATH_A
, 0x02, bMask12Bits
);
3294 PHY_QueryRFReg(Adapter
, RF90_PATH_A
, 0x02, bMask12Bits
);
3296 PHY_QueryRFReg(Adapter
, RF90_PATH_A
, 0x12, bMask12Bits
);
3298 PHY_QueryRFReg(Adapter
, RF90_PATH_A
, 0x12, bMask12Bits
);
3300 PHY_QueryRFReg(Adapter
, RF90_PATH_A
, 0x21, bMask12Bits
);
3302 PHY_QueryRFReg(Adapter
, RF90_PATH_A
, 0x21, bMask12Bits
);
3309 } /* DM_RfOperationTestCallBack */
3312 /*-----------------------------------------------------------------------------
3313 * Function: dm_check_rfctrl_gpio()
3315 * Overview: Copy 8187B template for 9xseries.
3325 * 05/28/2008 amy Create Version 0 porting from windows code.
3327 *---------------------------------------------------------------------------*/
3329 static void dm_check_rfctrl_gpio(struct net_device
* dev
)
3331 //struct r8192_priv *priv = ieee80211_priv(dev);
3333 // Walk around for DTM test, we will not enable HW - radio on/off because r/w
3334 // page 1 register before Lextra bus is enabled cause system fails when resuming
3335 // from S4. 20080218, Emily
3337 // Stop to execute workitem to prevent S3/S4 bug.
3348 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
3349 queue_delayed_work(priv
->priv_wq
,&priv
->gpio_change_rf_wq
,0);
3351 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3352 schedule_task(&priv
->gpio_change_rf_wq
);
3354 queue_work(priv
->priv_wq
,&priv
->gpio_change_rf_wq
);
3359 } /* dm_CheckRfCtrlGPIO */
3362 /*-----------------------------------------------------------------------------
3363 * Function: dm_check_pbc_gpio()
3365 * Overview: Check if PBC button is pressed.
3375 * 05/28/2008 amy Create Version 0 porting from windows code.
3377 *---------------------------------------------------------------------------*/
3378 static void dm_check_pbc_gpio(struct net_device
*dev
)
3381 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3385 tmp1byte
= read_nic_byte(dev
,GPI
);
3386 if(tmp1byte
== 0xff)
3389 if (tmp1byte
&BIT6
|| tmp1byte
&BIT0
)
3391 // Here we only set bPbcPressed to TRUE
3392 // After trigger PBC, the variable will be set to FALSE
3393 RT_TRACE(COMP_IO
, "CheckPbcGPIO - PBC is pressed\n");
3394 priv
->bpbc_pressed
= true;
3398 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3401 write_nic_byte(dev
, MAC_PINMUX_CFG
, (GPIOMUX_EN
| GPIOSEL_GPIO
));
3403 tmp1byte
= read_nic_byte(dev
, GPIO_IO_SEL
);
3404 tmp1byte
&= ~(HAL_8192S_HW_GPIO_WPS_BIT
);
3405 write_nic_byte(dev
, GPIO_IO_SEL
, tmp1byte
);
3407 tmp1byte
= read_nic_byte(dev
, GPIO_IN
);
3409 RT_TRACE(COMP_IO
, "CheckPbcGPIO - %x\n", tmp1byte
);
3411 // Add by hpfan 2008.07.07 to fix read GPIO error from S3
3412 if (tmp1byte
== 0xff)
3415 if (tmp1byte
&HAL_8192S_HW_GPIO_WPS_BIT
)
3417 // Here we only set bPbcPressed to TRUE
3418 // After trigger PBC, the variable will be set to FALSE
3419 RT_TRACE(COMP_IO
, "CheckPbcGPIO - PBC is pressed\n");
3420 priv
->bpbc_pressed
= true;
3430 /*-----------------------------------------------------------------------------
3431 * Function: dm_GPIOChangeRF
3432 * Overview: PCI will not support workitem call back HW radio on-off control.
3442 * 02/21/2008 MHC Create Version 0.
3444 *---------------------------------------------------------------------------*/
3445 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
3446 extern void dm_gpio_change_rf_callback(struct work_struct
*work
)
3448 struct delayed_work
*dwork
= container_of(work
,struct delayed_work
,work
);
3449 struct r8192_priv
*priv
= container_of(dwork
,struct r8192_priv
,gpio_change_rf_wq
);
3450 struct net_device
*dev
= priv
->ieee80211
->dev
;
3452 extern void dm_gpio_change_rf_callback(struct net_device
*dev
)
3454 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3457 RT_RF_POWER_STATE eRfPowerStateToSet
;
3458 bool bActuallySet
= false;
3465 RT_TRACE((COMP_INIT
| COMP_POWER
| COMP_RF
),"dm_gpio_change_rf_callback(): Callback function breaks out!!\n");
3469 // 0x108 GPIO input register is read only
3470 //set 0x108 B1= 1: RF-ON; 0: RF-OFF.
3471 tmp1byte
= read_nic_byte(dev
,GPI
);
3473 eRfPowerStateToSet
= (tmp1byte
&BIT1
) ? eRfOn
: eRfOff
;
3475 if( (priv
->bHwRadioOff
== true) && (eRfPowerStateToSet
== eRfOn
))
3477 RT_TRACE(COMP_RF
, "gpiochangeRF - HW Radio ON\n");
3479 priv
->bHwRadioOff
= false;
3480 bActuallySet
= true;
3482 else if ( (priv
->bHwRadioOff
== false) && (eRfPowerStateToSet
== eRfOff
))
3484 RT_TRACE(COMP_RF
, "gpiochangeRF - HW Radio OFF\n");
3485 priv
->bHwRadioOff
= true;
3486 bActuallySet
= true;
3492 MgntActSet_RF_State(dev
, eRfPowerStateToSet
, RF_CHANGE_BY_HW
);
3493 //DrvIFIndicateCurrentPhyStatus(pAdapter);
3504 } /* dm_GPIOChangeRF */
3507 /*-----------------------------------------------------------------------------
3508 * Function: DM_RFPathCheckWorkItemCallBack()
3510 * Overview: Check if Current RF RX path is enabled
3520 * 01/30/2008 MHC Create Version 0.
3522 *---------------------------------------------------------------------------*/
3523 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
3524 extern void dm_rf_pathcheck_workitemcallback(struct work_struct
*work
)
3526 struct delayed_work
*dwork
= container_of(work
,struct delayed_work
,work
);
3527 struct r8192_priv
*priv
= container_of(dwork
,struct r8192_priv
,rfpath_check_wq
);
3528 struct net_device
*dev
=priv
->ieee80211
->dev
;
3530 extern void dm_rf_pathcheck_workitemcallback(struct net_device
*dev
)
3532 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3534 //bool bactually_set = false;
3538 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
3539 always be the same. We only read 0xc04 now. */
3540 rfpath
= read_nic_byte(dev
, 0xc04);
3542 // Check Bit 0-3, it means if RF A-D is enabled.
3543 for (i
= 0; i
< RF90_PATH_MAX
; i
++)
3545 if (rfpath
& (0x01<<i
))
3546 priv
->brfpath_rxenable
[i
] = 1;
3548 priv
->brfpath_rxenable
[i
] = 0;
3550 if(!DM_RxPathSelTable
.Enable
)
3553 dm_rxpath_sel_byrssi(dev
);
3554 } /* DM_RFPathCheckWorkItemCallBack */
3556 static void dm_init_rxpath_selection(struct net_device
* dev
)
3559 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3560 DM_RxPathSelTable
.Enable
= 1; //default enabled
3561 DM_RxPathSelTable
.SS_TH_low
= RxPathSelection_SS_TH_low
;
3562 DM_RxPathSelTable
.diff_TH
= RxPathSelection_diff_TH
;
3563 if(priv
->CustomerID
== RT_CID_819x_Netcore
)
3564 DM_RxPathSelTable
.cck_method
= CCK_Rx_Version_2
;
3566 DM_RxPathSelTable
.cck_method
= CCK_Rx_Version_1
;
3567 DM_RxPathSelTable
.DbgMode
= DM_DBG_OFF
;
3568 DM_RxPathSelTable
.disabledRF
= 0;
3571 DM_RxPathSelTable
.rf_rssi
[i
] = 50;
3572 DM_RxPathSelTable
.cck_pwdb_sta
[i
] = -64;
3573 DM_RxPathSelTable
.rf_enable_rssi_th
[i
] = 100;
3577 static void dm_rxpath_sel_byrssi(struct net_device
* dev
)
3579 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3580 u8 i
, max_rssi_index
=0, min_rssi_index
=0, sec_rssi_index
=0, rf_num
=0;
3581 u8 tmp_max_rssi
=0, tmp_min_rssi
=0, tmp_sec_rssi
=0;
3582 u8 cck_default_Rx
=0x2; //RF-C
3583 u8 cck_optional_Rx
=0x3;//RF-D
3584 long tmp_cck_max_pwdb
=0, tmp_cck_min_pwdb
=0, tmp_cck_sec_pwdb
=0;
3585 u8 cck_rx_ver2_max_index
=0, cck_rx_ver2_min_index
=0, cck_rx_ver2_sec_index
=0;
3588 static u8 disabled_rf_cnt
=0, cck_Rx_Path_initialized
=0;
3589 u8 update_cck_rx_path
;
3591 if(priv
->rf_type
!= RF_2T4R
)
3594 if(!cck_Rx_Path_initialized
)
3596 DM_RxPathSelTable
.cck_Rx_path
= (read_nic_byte(dev
, 0xa07)&0xf);
3597 cck_Rx_Path_initialized
= 1;
3600 DM_RxPathSelTable
.disabledRF
= 0xf;
3601 DM_RxPathSelTable
.disabledRF
&=~ (read_nic_byte(dev
, 0xc04));
3603 if(priv
->ieee80211
->mode
== WIRELESS_MODE_B
)
3605 DM_RxPathSelTable
.cck_method
= CCK_Rx_Version_2
; //pure B mode, fixed cck version2
3606 //DbgPrint("Pure B mode, use cck rx version2 \n");
3609 //decide max/sec/min rssi index
3610 for (i
=0; i
<RF90_PATH_MAX
; i
++)
3612 if(!DM_RxPathSelTable
.DbgMode
)
3613 DM_RxPathSelTable
.rf_rssi
[i
] = priv
->stats
.rx_rssi_percentage
[i
];
3615 if(priv
->brfpath_rxenable
[i
])
3618 cur_rf_rssi
= DM_RxPathSelTable
.rf_rssi
[i
];
3620 if(rf_num
== 1) // find first enabled rf path and the rssi values
3621 { //initialize, set all rssi index to the same one
3622 max_rssi_index
= min_rssi_index
= sec_rssi_index
= i
;
3623 tmp_max_rssi
= tmp_min_rssi
= tmp_sec_rssi
= cur_rf_rssi
;
3625 else if(rf_num
== 2)
3626 { // we pick up the max index first, and let sec and min to be the same one
3627 if(cur_rf_rssi
>= tmp_max_rssi
)
3629 tmp_max_rssi
= cur_rf_rssi
;
3634 tmp_sec_rssi
= tmp_min_rssi
= cur_rf_rssi
;
3635 sec_rssi_index
= min_rssi_index
= i
;
3640 if(cur_rf_rssi
> tmp_max_rssi
)
3642 tmp_sec_rssi
= tmp_max_rssi
;
3643 sec_rssi_index
= max_rssi_index
;
3644 tmp_max_rssi
= cur_rf_rssi
;
3647 else if(cur_rf_rssi
== tmp_max_rssi
)
3648 { // let sec and min point to the different index
3649 tmp_sec_rssi
= cur_rf_rssi
;
3652 else if((cur_rf_rssi
< tmp_max_rssi
) &&(cur_rf_rssi
> tmp_sec_rssi
))
3654 tmp_sec_rssi
= cur_rf_rssi
;
3657 else if(cur_rf_rssi
== tmp_sec_rssi
)
3659 if(tmp_sec_rssi
== tmp_min_rssi
)
3660 { // let sec and min point to the different index
3661 tmp_sec_rssi
= cur_rf_rssi
;
3666 // This case we don't need to set any index
3669 else if((cur_rf_rssi
< tmp_sec_rssi
) && (cur_rf_rssi
> tmp_min_rssi
))
3671 // This case we don't need to set any index
3673 else if(cur_rf_rssi
== tmp_min_rssi
)
3675 if(tmp_sec_rssi
== tmp_min_rssi
)
3676 { // let sec and min point to the different index
3677 tmp_min_rssi
= cur_rf_rssi
;
3682 // This case we don't need to set any index
3685 else if(cur_rf_rssi
< tmp_min_rssi
)
3687 tmp_min_rssi
= cur_rf_rssi
;
3695 // decide max/sec/min cck pwdb index
3696 if(DM_RxPathSelTable
.cck_method
== CCK_Rx_Version_2
)
3698 for (i
=0; i
<RF90_PATH_MAX
; i
++)
3700 if(priv
->brfpath_rxenable
[i
])
3703 cur_cck_pwdb
= DM_RxPathSelTable
.cck_pwdb_sta
[i
];
3705 if(rf_num
== 1) // find first enabled rf path and the rssi values
3706 { //initialize, set all rssi index to the same one
3707 cck_rx_ver2_max_index
= cck_rx_ver2_min_index
= cck_rx_ver2_sec_index
= i
;
3708 tmp_cck_max_pwdb
= tmp_cck_min_pwdb
= tmp_cck_sec_pwdb
= cur_cck_pwdb
;
3710 else if(rf_num
== 2)
3711 { // we pick up the max index first, and let sec and min to be the same one
3712 if(cur_cck_pwdb
>= tmp_cck_max_pwdb
)
3714 tmp_cck_max_pwdb
= cur_cck_pwdb
;
3715 cck_rx_ver2_max_index
= i
;
3719 tmp_cck_sec_pwdb
= tmp_cck_min_pwdb
= cur_cck_pwdb
;
3720 cck_rx_ver2_sec_index
= cck_rx_ver2_min_index
= i
;
3725 if(cur_cck_pwdb
> tmp_cck_max_pwdb
)
3727 tmp_cck_sec_pwdb
= tmp_cck_max_pwdb
;
3728 cck_rx_ver2_sec_index
= cck_rx_ver2_max_index
;
3729 tmp_cck_max_pwdb
= cur_cck_pwdb
;
3730 cck_rx_ver2_max_index
= i
;
3732 else if(cur_cck_pwdb
== tmp_cck_max_pwdb
)
3733 { // let sec and min point to the different index
3734 tmp_cck_sec_pwdb
= cur_cck_pwdb
;
3735 cck_rx_ver2_sec_index
= i
;
3737 else if((cur_cck_pwdb
< tmp_cck_max_pwdb
) &&(cur_cck_pwdb
> tmp_cck_sec_pwdb
))
3739 tmp_cck_sec_pwdb
= cur_cck_pwdb
;
3740 cck_rx_ver2_sec_index
= i
;
3742 else if(cur_cck_pwdb
== tmp_cck_sec_pwdb
)
3744 if(tmp_cck_sec_pwdb
== tmp_cck_min_pwdb
)
3745 { // let sec and min point to the different index
3746 tmp_cck_sec_pwdb
= cur_cck_pwdb
;
3747 cck_rx_ver2_sec_index
= i
;
3751 // This case we don't need to set any index
3754 else if((cur_cck_pwdb
< tmp_cck_sec_pwdb
) && (cur_cck_pwdb
> tmp_cck_min_pwdb
))
3756 // This case we don't need to set any index
3758 else if(cur_cck_pwdb
== tmp_cck_min_pwdb
)
3760 if(tmp_cck_sec_pwdb
== tmp_cck_min_pwdb
)
3761 { // let sec and min point to the different index
3762 tmp_cck_min_pwdb
= cur_cck_pwdb
;
3763 cck_rx_ver2_min_index
= i
;
3767 // This case we don't need to set any index
3770 else if(cur_cck_pwdb
< tmp_cck_min_pwdb
)
3772 tmp_cck_min_pwdb
= cur_cck_pwdb
;
3773 cck_rx_ver2_min_index
= i
;
3783 // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
3784 update_cck_rx_path
= 0;
3785 if(DM_RxPathSelTable
.cck_method
== CCK_Rx_Version_2
)
3787 cck_default_Rx
= cck_rx_ver2_max_index
;
3788 cck_optional_Rx
= cck_rx_ver2_sec_index
;
3789 if(tmp_cck_max_pwdb
!= -64)
3790 update_cck_rx_path
= 1;
3793 if(tmp_min_rssi
< DM_RxPathSelTable
.SS_TH_low
&& disabled_rf_cnt
< 2)
3795 if((tmp_max_rssi
- tmp_min_rssi
) >= DM_RxPathSelTable
.diff_TH
)
3797 //record the enabled rssi threshold
3798 DM_RxPathSelTable
.rf_enable_rssi_th
[min_rssi_index
] = tmp_max_rssi
+5;
3799 //disable the BB Rx path, OFDM
3800 rtl8192_setBBreg(dev
, rOFDM0_TRxPathEnable
, 0x1<<min_rssi_index
, 0x0); // 0xc04[3:0]
3801 rtl8192_setBBreg(dev
, rOFDM1_TRxPathEnable
, 0x1<<min_rssi_index
, 0x0); // 0xd04[3:0]
3804 if(DM_RxPathSelTable
.cck_method
== CCK_Rx_Version_1
)
3806 cck_default_Rx
= max_rssi_index
;
3807 cck_optional_Rx
= sec_rssi_index
;
3809 update_cck_rx_path
= 1;
3813 if(update_cck_rx_path
)
3815 DM_RxPathSelTable
.cck_Rx_path
= (cck_default_Rx
<<2)|(cck_optional_Rx
);
3816 rtl8192_setBBreg(dev
, rCCK0_AFESetting
, 0x0f000000, DM_RxPathSelTable
.cck_Rx_path
);
3819 if(DM_RxPathSelTable
.disabledRF
)
3823 if((DM_RxPathSelTable
.disabledRF
>>i
) & 0x1) //disabled rf
3825 if(tmp_max_rssi
>= DM_RxPathSelTable
.rf_enable_rssi_th
[i
])
3827 //enable the BB Rx path
3828 //DbgPrint("RF-%d is enabled. \n", 0x1<<i);
3829 rtl8192_setBBreg(dev
, rOFDM0_TRxPathEnable
, 0x1<<i
, 0x1); // 0xc04[3:0]
3830 rtl8192_setBBreg(dev
, rOFDM1_TRxPathEnable
, 0x1<<i
, 0x1); // 0xd04[3:0]
3831 DM_RxPathSelTable
.rf_enable_rssi_th
[i
] = 100;
3839 /*-----------------------------------------------------------------------------
3840 * Function: dm_check_rx_path_selection()
3842 * Overview: Call a workitem to check current RXRF path and Rx Path selection by RSSI.
3852 * 05/28/2008 amy Create Version 0 porting from windows code.
3854 *---------------------------------------------------------------------------*/
3855 static void dm_check_rx_path_selection(struct net_device
*dev
)
3857 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3858 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
3859 queue_delayed_work(priv
->priv_wq
,&priv
->rfpath_check_wq
,0);
3861 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3862 schedule_task(&priv
->rfpath_check_wq
);
3864 queue_work(priv
->priv_wq
,&priv
->rfpath_check_wq
);
3867 } /* dm_CheckRxRFPath */
3870 static void dm_init_fsync (struct net_device
*dev
)
3872 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3874 priv
->ieee80211
->fsync_time_interval
= 500;
3875 priv
->ieee80211
->fsync_rate_bitmap
= 0x0f000800;
3876 priv
->ieee80211
->fsync_rssi_threshold
= 30;
3878 priv
->ieee80211
->bfsync_enable
= true;
3880 priv
->ieee80211
->bfsync_enable
= false;
3882 priv
->ieee80211
->fsync_multiple_timeinterval
= 3;
3883 priv
->ieee80211
->fsync_firstdiff_ratethreshold
= 100;
3884 priv
->ieee80211
->fsync_seconddiff_ratethreshold
= 200;
3885 priv
->ieee80211
->fsync_state
= Default_Fsync
;
3886 priv
->framesyncMonitor
= 1; // current default 0xc38 monitor on
3888 init_timer(&priv
->fsync_timer
);
3889 priv
->fsync_timer
.data
= (unsigned long)dev
;
3890 priv
->fsync_timer
.function
= dm_fsync_timer_callback
;
3894 static void dm_deInit_fsync(struct net_device
*dev
)
3896 struct r8192_priv
*priv
= ieee80211_priv(dev
);
3897 del_timer_sync(&priv
->fsync_timer
);
3900 extern void dm_fsync_timer_callback(unsigned long data
)
3902 struct net_device
*dev
= (struct net_device
*)data
;
3903 struct r8192_priv
*priv
= ieee80211_priv((struct net_device
*)data
);
3904 u32 rate_index
, rate_count
= 0, rate_count_diff
=0;
3905 bool bSwitchFromCountDiff
= false;
3906 bool bDoubleTimeInterval
= false;
3908 if( priv
->ieee80211
->state
== IEEE80211_LINKED
&&
3909 priv
->ieee80211
->bfsync_enable
&&
3910 (priv
->ieee80211
->pHTInfo
->IOTAction
& HT_IOT_ACT_CDD_FSYNC
))
3912 // Count rate 54, MCS [7], [12, 13, 14, 15]
3914 for(rate_index
= 0; rate_index
<= 27; rate_index
++)
3916 rate_bitmap
= 1 << rate_index
;
3917 if(priv
->ieee80211
->fsync_rate_bitmap
& rate_bitmap
)
3918 rate_count
+= priv
->stats
.received_rate_histogram
[1][rate_index
];
3921 if(rate_count
< priv
->rate_record
)
3922 rate_count_diff
= 0xffffffff - rate_count
+ priv
->rate_record
;
3924 rate_count_diff
= rate_count
- priv
->rate_record
;
3925 if(rate_count_diff
< priv
->rateCountDiffRecord
)
3928 u32 DiffNum
= priv
->rateCountDiffRecord
- rate_count_diff
;
3930 if(DiffNum
>= priv
->ieee80211
->fsync_seconddiff_ratethreshold
)
3931 priv
->ContiuneDiffCount
++;
3933 priv
->ContiuneDiffCount
= 0;
3935 // Contiune count over
3936 if(priv
->ContiuneDiffCount
>=2)
3938 bSwitchFromCountDiff
= true;
3939 priv
->ContiuneDiffCount
= 0;
3944 // Stop contiune count
3945 priv
->ContiuneDiffCount
= 0;
3948 //If Count diff <= FsyncRateCountThreshold
3949 if(rate_count_diff
<= priv
->ieee80211
->fsync_firstdiff_ratethreshold
)
3951 bSwitchFromCountDiff
= true;
3952 priv
->ContiuneDiffCount
= 0;
3954 priv
->rate_record
= rate_count
;
3955 priv
->rateCountDiffRecord
= rate_count_diff
;
3956 RT_TRACE(COMP_HALDM
, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv
->rate_record
, rate_count
, rate_count_diff
, priv
->bswitch_fsync
);
3957 // if we never receive those mcs rate and rssi > 30 % then switch fsyn
3958 if(priv
->undecorated_smoothed_pwdb
> priv
->ieee80211
->fsync_rssi_threshold
&& bSwitchFromCountDiff
)
3960 bDoubleTimeInterval
= true;
3961 priv
->bswitch_fsync
= !priv
->bswitch_fsync
;
3962 if(priv
->bswitch_fsync
)
3965 write_nic_byte(dev
, 0xC36, 0x00);
3967 write_nic_byte(dev
,0xC36, 0x1c);
3969 write_nic_byte(dev
, 0xC3e, 0x90);
3974 write_nic_byte(dev
, 0xC36, 0x40);
3976 write_nic_byte(dev
, 0xC36, 0x5c);
3978 write_nic_byte(dev
, 0xC3e, 0x96);
3981 else if(priv
->undecorated_smoothed_pwdb
<= priv
->ieee80211
->fsync_rssi_threshold
)
3983 if(priv
->bswitch_fsync
)
3985 priv
->bswitch_fsync
= false;
3987 write_nic_byte(dev
, 0xC36, 0x40);
3989 write_nic_byte(dev
, 0xC36, 0x5c);
3991 write_nic_byte(dev
, 0xC3e, 0x96);
3994 if(bDoubleTimeInterval
){
3995 if(timer_pending(&priv
->fsync_timer
))
3996 del_timer_sync(&priv
->fsync_timer
);
3997 priv
->fsync_timer
.expires
= jiffies
+ MSECS(priv
->ieee80211
->fsync_time_interval
*priv
->ieee80211
->fsync_multiple_timeinterval
);
3998 add_timer(&priv
->fsync_timer
);
4001 if(timer_pending(&priv
->fsync_timer
))
4002 del_timer_sync(&priv
->fsync_timer
);
4003 priv
->fsync_timer
.expires
= jiffies
+ MSECS(priv
->ieee80211
->fsync_time_interval
);
4004 add_timer(&priv
->fsync_timer
);
4009 // Let Register return to default value;
4010 if(priv
->bswitch_fsync
)
4012 priv
->bswitch_fsync
= false;
4014 write_nic_byte(dev
, 0xC36, 0x40);
4016 write_nic_byte(dev
, 0xC36, 0x5c);
4018 write_nic_byte(dev
, 0xC3e, 0x96);
4020 priv
->ContiuneDiffCount
= 0;
4022 rtl8192_setBBreg(dev
, rOFDM0_RxDetector2
, bMaskDWord
, 0x164052cd);
4025 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x164052cd);
4027 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x465c52cd);
4031 RT_TRACE(COMP_HALDM
, "ContiuneDiffCount %d\n", priv
->ContiuneDiffCount
);
4032 RT_TRACE(COMP_HALDM
, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv
->rate_record
, rate_count
, rate_count_diff
, priv
->bswitch_fsync
);
4035 static void dm_StartHWFsync(struct net_device
*dev
)
4037 RT_TRACE(COMP_HALDM
, "%s\n", __FUNCTION__
);
4038 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x465c12cf);
4039 write_nic_byte(dev
, 0xc3b, 0x41);
4042 static void dm_EndSWFsync(struct net_device
*dev
)
4044 struct r8192_priv
*priv
= ieee80211_priv(dev
);
4046 RT_TRACE(COMP_HALDM
, "%s\n", __FUNCTION__
);
4047 del_timer_sync(&(priv
->fsync_timer
));
4049 // Let Register return to default value;
4050 if(priv
->bswitch_fsync
)
4052 priv
->bswitch_fsync
= false;
4055 write_nic_byte(dev
, 0xC36, 0x40);
4057 write_nic_byte(dev
, 0xC36, 0x5c);
4060 write_nic_byte(dev
, 0xC3e, 0x96);
4063 priv
->ContiuneDiffCount
= 0;
4065 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x465c52cd);
4070 static void dm_StartSWFsync(struct net_device
*dev
)
4072 struct r8192_priv
*priv
= ieee80211_priv(dev
);
4076 RT_TRACE(COMP_HALDM
,"%s\n", __FUNCTION__
);
4077 // Initial rate record to zero, start to record.
4078 priv
->rate_record
= 0;
4079 // Initial contiune diff count to zero, start to record.
4080 priv
->ContiuneDiffCount
= 0;
4081 priv
->rateCountDiffRecord
= 0;
4082 priv
->bswitch_fsync
= false;
4084 if(priv
->ieee80211
->mode
== WIRELESS_MODE_N_24G
)
4086 priv
->ieee80211
->fsync_firstdiff_ratethreshold
= 600;
4087 priv
->ieee80211
->fsync_seconddiff_ratethreshold
= 0xffff;
4091 priv
->ieee80211
->fsync_firstdiff_ratethreshold
= 200;
4092 priv
->ieee80211
->fsync_seconddiff_ratethreshold
= 200;
4094 for(rateIndex
= 0; rateIndex
<= 27; rateIndex
++)
4096 rateBitmap
= 1 << rateIndex
;
4097 if(priv
->ieee80211
->fsync_rate_bitmap
& rateBitmap
)
4098 priv
->rate_record
+= priv
->stats
.received_rate_histogram
[1][rateIndex
];
4100 if(timer_pending(&priv
->fsync_timer
))
4101 del_timer_sync(&priv
->fsync_timer
);
4102 priv
->fsync_timer
.expires
= jiffies
+ MSECS(priv
->ieee80211
->fsync_time_interval
);
4103 add_timer(&priv
->fsync_timer
);
4106 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x465c12cd);
4111 static void dm_EndHWFsync(struct net_device
*dev
)
4113 RT_TRACE(COMP_HALDM
,"%s\n", __FUNCTION__
);
4114 write_nic_dword(dev
, rOFDM0_RxDetector2
, 0x465c52cd);
4115 write_nic_byte(dev
, 0xc3b, 0x49);
4119 void dm_check_fsync(struct net_device
*dev
)
4121 #define RegC38_Default 0
4122 #define RegC38_NonFsync_Other_AP 1
4123 #define RegC38_Fsync_AP_BCM 2
4124 struct r8192_priv
*priv
= ieee80211_priv(dev
);
4126 static u8 reg_c38_State
=RegC38_Default
;
4127 static u32 reset_cnt
=0;
4129 RT_TRACE(COMP_HALDM
, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv
->ieee80211
->fsync_rssi_threshold
, priv
->ieee80211
->fsync_time_interval
, priv
->ieee80211
->fsync_multiple_timeinterval
);
4130 RT_TRACE(COMP_HALDM
, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv
->ieee80211
->fsync_rate_bitmap
, priv
->ieee80211
->fsync_firstdiff_ratethreshold
, priv
->ieee80211
->fsync_seconddiff_ratethreshold
);
4132 if( priv
->ieee80211
->state
== IEEE80211_LINKED
&&
4133 (priv
->ieee80211
->pHTInfo
->IOTAction
& HT_IOT_ACT_CDD_FSYNC
))
4135 if(priv
->ieee80211
->bfsync_enable
== 0)
4137 switch(priv
->ieee80211
->fsync_state
)
4140 dm_StartHWFsync(dev
);
4141 priv
->ieee80211
->fsync_state
= HW_Fsync
;
4145 dm_StartHWFsync(dev
);
4146 priv
->ieee80211
->fsync_state
= HW_Fsync
;
4155 switch(priv
->ieee80211
->fsync_state
)
4158 dm_StartSWFsync(dev
);
4159 priv
->ieee80211
->fsync_state
= SW_Fsync
;
4163 dm_StartSWFsync(dev
);
4164 priv
->ieee80211
->fsync_state
= SW_Fsync
;
4172 if(priv
->framesyncMonitor
)
4174 if(reg_c38_State
!= RegC38_Fsync_AP_BCM
)
4175 { //For broadcom AP we write different default value
4177 write_nic_byte(dev
, rOFDM0_RxDetector3
, 0x15);
4179 write_nic_byte(dev
, rOFDM0_RxDetector3
, 0x95);
4182 reg_c38_State
= RegC38_Fsync_AP_BCM
;
4188 switch(priv
->ieee80211
->fsync_state
)
4192 priv
->ieee80211
->fsync_state
= Default_Fsync
;
4196 priv
->ieee80211
->fsync_state
= Default_Fsync
;
4203 if(priv
->framesyncMonitor
)
4205 if(priv
->ieee80211
->state
== IEEE80211_LINKED
)
4207 if(priv
->undecorated_smoothed_pwdb
<= RegC38_TH
)
4209 if(reg_c38_State
!= RegC38_NonFsync_Other_AP
)
4212 write_nic_byte(dev
, rOFDM0_RxDetector3
, 0x10);
4214 write_nic_byte(dev
, rOFDM0_RxDetector3
, 0x90);
4217 reg_c38_State
= RegC38_NonFsync_Other_AP
;
4219 if (Adapter
->HardwareType
== HARDWARE_TYPE_RTL8190P
)
4220 DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x10);
4222 DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x90);
4226 else if(priv
->undecorated_smoothed_pwdb
>= (RegC38_TH
+5))
4230 write_nic_byte(dev
, rOFDM0_RxDetector3
, priv
->framesync
);
4231 reg_c38_State
= RegC38_Default
;
4232 //DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x \n", pHalData->framesync);
4240 write_nic_byte(dev
, rOFDM0_RxDetector3
, priv
->framesync
);
4241 reg_c38_State
= RegC38_Default
;
4242 //DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x \n", pHalData->framesync);
4247 if(priv
->framesyncMonitor
)
4249 if(priv
->reset_count
!= reset_cnt
)
4250 { //After silent reset, the reg_c38_State will be returned to default value
4251 write_nic_byte(dev
, rOFDM0_RxDetector3
, priv
->framesync
);
4252 reg_c38_State
= RegC38_Default
;
4253 reset_cnt
= priv
->reset_count
;
4254 //DbgPrint("reg_c38_State = 0 for silent reset. \n");
4261 write_nic_byte(dev
, rOFDM0_RxDetector3
, priv
->framesync
);
4262 reg_c38_State
= RegC38_Default
;
4263 //DbgPrint("framesync no monitor, write 0xc38 = 0x%x \n", pHalData->framesync);
4269 /*-----------------------------------------------------------------------------
4270 * Function: DM_CheckLBusStatus()
4272 * Overview: For 9x series, we must make sure LBUS is active for IO.
4282 * 02/22/2008 MHC Create Version 0.
4284 *---------------------------------------------------------------------------*/
4285 extern s1Byte
DM_CheckLBusStatus(IN PADAPTER Adapter
)
4287 PMGNT_INFO pMgntInfo
=&Adapter
->MgntInfo
;
4289 #if (HAL_CODE_BASE & RTL819X)
4291 #if (HAL_CODE_BASE == RTL8192)
4293 #if( DEV_BUS_TYPE==PCI_INTERFACE)
4294 //return (pMgntInfo->bLbusEnable); // For debug only
4298 #if( DEV_BUS_TYPE==USB_INTERFACE)
4302 #endif // #if (HAL_CODE_BASE == RTL8192)
4304 #if (HAL_CODE_BASE == RTL8190)
4306 #endif // #if (HAL_CODE_BASE == RTL8190)
4308 #endif // #if (HAL_CODE_BASE & RTL819X)
4309 } /* DM_CheckLBusStatus */
4313 /*-----------------------------------------------------------------------------
4314 * Function: dm_shadow_init()
4316 * Overview: Store all NIC MAC/BB register content.
4326 * 05/29/2008 amy Create Version 0 porting from windows code.
4328 *---------------------------------------------------------------------------*/
4329 extern void dm_shadow_init(struct net_device
*dev
)
4334 for (page
= 0; page
< 5; page
++)
4335 for (offset
= 0; offset
< 256; offset
++)
4337 dm_shadow
[page
][offset
] = read_nic_byte(dev
, offset
+page
*256);
4338 //DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);
4341 for (page
= 8; page
< 11; page
++)
4342 for (offset
= 0; offset
< 256; offset
++)
4343 dm_shadow
[page
][offset
] = read_nic_byte(dev
, offset
+page
*256);
4345 for (page
= 12; page
< 15; page
++)
4346 for (offset
= 0; offset
< 256; offset
++)
4347 dm_shadow
[page
][offset
] = read_nic_byte(dev
, offset
+page
*256);
4349 } /* dm_shadow_init */
4351 /*---------------------------Define function prototype------------------------*/
4352 /*-----------------------------------------------------------------------------
4353 * Function: DM_DynamicTxPower()
4355 * Overview: Detect Signal strength to control TX Registry
4356 Tx Power Control For Near/Far Range
4366 * 03/06/2008 Jacken Create Version 0.
4368 *---------------------------------------------------------------------------*/
4369 static void dm_init_dynamic_txpower(struct net_device
*dev
)
4371 struct r8192_priv
*priv
= ieee80211_priv(dev
);
4373 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
4374 priv
->ieee80211
->bdynamic_txpower_enable
= true; //Default to enable Tx Power Control
4375 priv
->bLastDTPFlag_High
= false;
4376 priv
->bLastDTPFlag_Low
= false;
4377 priv
->bDynamicTxHighPower
= false;
4378 priv
->bDynamicTxLowPower
= false;
4381 static void dm_dynamic_txpower(struct net_device
*dev
)
4383 struct r8192_priv
*priv
= ieee80211_priv(dev
);
4384 unsigned int txhipower_threshhold
=0;
4385 unsigned int txlowpower_threshold
=0;
4386 if(priv
->ieee80211
->bdynamic_txpower_enable
!= true)
4388 priv
->bDynamicTxHighPower
= false;
4389 priv
->bDynamicTxLowPower
= false;
4392 //printk("priv->ieee80211->current_network.unknown_cap_exist is %d ,priv->ieee80211->current_network.broadcom_cap_exist is %d\n",priv->ieee80211->current_network.unknown_cap_exist,priv->ieee80211->current_network.broadcom_cap_exist);
4393 if((priv
->ieee80211
->current_network
.atheros_cap_exist
) && (priv
->ieee80211
->mode
== IEEE_G
)){
4394 txhipower_threshhold
= TX_POWER_ATHEROAP_THRESH_HIGH
;
4395 txlowpower_threshold
= TX_POWER_ATHEROAP_THRESH_LOW
;
4399 txhipower_threshhold
= TX_POWER_NEAR_FIELD_THRESH_HIGH
;
4400 txlowpower_threshold
= TX_POWER_NEAR_FIELD_THRESH_LOW
;
4403 // printk("=======>%s(): txhipower_threshhold is %d,txlowpower_threshold is %d\n",__FUNCTION__,txhipower_threshhold,txlowpower_threshold);
4404 RT_TRACE(COMP_TXAGC
,"priv->undecorated_smoothed_pwdb = %ld \n" , priv
->undecorated_smoothed_pwdb
);
4406 if(priv
->ieee80211
->state
== IEEE80211_LINKED
)
4408 if(priv
->undecorated_smoothed_pwdb
>= txhipower_threshhold
)
4410 priv
->bDynamicTxHighPower
= true;
4411 priv
->bDynamicTxLowPower
= false;
4415 // high power state check
4416 if(priv
->undecorated_smoothed_pwdb
< txlowpower_threshold
&& priv
->bDynamicTxHighPower
== true)
4418 priv
->bDynamicTxHighPower
= false;
4420 // low power state check
4421 if(priv
->undecorated_smoothed_pwdb
< 35)
4423 priv
->bDynamicTxLowPower
= true;
4425 else if(priv
->undecorated_smoothed_pwdb
>= 40)
4427 priv
->bDynamicTxLowPower
= false;
4433 //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;
4434 priv
->bDynamicTxHighPower
= false;
4435 priv
->bDynamicTxLowPower
= false;
4438 if( (priv
->bDynamicTxHighPower
!= priv
->bLastDTPFlag_High
) ||
4439 (priv
->bDynamicTxLowPower
!= priv
->bLastDTPFlag_Low
) )
4441 RT_TRACE(COMP_TXAGC
,"SetTxPowerLevel8190() channel = %d \n" , priv
->ieee80211
->current_network
.channel
);
4443 #if defined(RTL8190P) || defined(RTL8192E)
4444 SetTxPowerLevel8190(Adapter
,pHalData
->CurrentChannel
);
4448 rtl8192_phy_setTxPower(dev
,priv
->ieee80211
->current_network
.channel
);
4449 //pHalData->bStartTxCtrlByTPCNFR = FALSE; //Clear th flag of Set TX Power from Sitesurvey
4453 priv
->bLastDTPFlag_High
= priv
->bDynamicTxHighPower
;
4454 priv
->bLastDTPFlag_Low
= priv
->bDynamicTxLowPower
;
4456 } /* dm_dynamic_txpower */
4458 //added by vivi, for read tx rate and retrycount
4459 static void dm_check_txrateandretrycount(struct net_device
* dev
)
4461 struct r8192_priv
*priv
= ieee80211_priv(dev
);
4462 struct ieee80211_device
* ieee
= priv
->ieee80211
;
4464 // priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
4466 ieee
->softmac_stats
.CurrentShowTxate
= read_nic_byte(dev
, TX_RATE_REG
);
4468 ieee
->softmac_stats
.CurrentShowTxate
= read_nic_byte(dev
, Current_Tx_Rate_Reg
);
4470 //printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);
4471 //for initial tx rate
4472 // priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);
4473 ieee
->softmac_stats
.last_packet_rate
= read_nic_byte(dev
,Initial_Tx_Rate_Reg
);
4474 //for tx tx retry count
4475 // priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
4476 ieee
->softmac_stats
.txretrycount
= read_nic_dword(dev
, Tx_Retry_Count_Reg
);
4479 static void dm_send_rssi_tofw(struct net_device
*dev
)
4482 DCMD_TXCMD_T tx_cmd
;
4483 struct r8192_priv
*priv
= ieee80211_priv(dev
);
4485 // If we test chariot, we should stop the TX command ?
4486 // Because 92E will always silent reset when we send tx command. We use register
4487 // 0x1e0(byte) to botify driver.
4488 write_nic_byte(dev
, DRIVER_RSSI
, (u8
)priv
->undecorated_smoothed_pwdb
);
4491 tx_cmd
.Op
= TXCMD_SET_RX_RSSI
;
4493 tx_cmd
.Value
= priv
->undecorated_smoothed_pwdb
;
4495 cmpk_message_handle_tx(dev
, (u8
*)&tx_cmd
,
4496 DESC_PACKET_TYPE_INIT
, sizeof(DCMD_TXCMD_T
));
4503 dm_CheckProtection(struct net_device
*dev
)
4505 struct r8192_priv
*priv
= ieee80211_priv(dev
);
4506 //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
4509 if(priv
->ieee80211
->pHTInfo
->IOTAction
& (HT_IOT_ACT_FORCED_RTS
|HT_IOT_ACT_FORCED_CTS2SELF
))
4511 CurRate
= read_nic_byte(dev
, INIMCS_SEL
);
4512 if(CurRate
<= DESC92S_RATE11M
)
4513 priv
->bDmDisableProtect
= true;
4515 priv
->bDmDisableProtect
= fasle
;
4520 /*---------------------------Define function prototype------------------------*/