From b441ee30c5c5d1cbb8e50c7c344245fbdc275a5e Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 7 Apr 2003 00:17:52 +0000 Subject: [PATCH] Eleminate mips_cpu and move it into cpu_data. --- arch/mips/ddb5xxx/ddb5477/setup.c | 2 +- arch/mips/dec/prom/init.c | 8 +- arch/mips/dec/setup.c | 2 +- arch/mips/dec/time.c | 2 +- arch/mips/kernel/branch.c | 2 +- arch/mips/kernel/cpu-probe.c | 323 +++++++++++++++--------------- arch/mips/kernel/proc.c | 18 +- arch/mips/kernel/ptrace.c | 6 +- arch/mips/kernel/setup.c | 3 +- arch/mips/kernel/smp.c | 3 +- arch/mips/kernel/time.c | 10 +- arch/mips/kernel/traps.c | 32 +-- arch/mips/lasat/prom.c | 2 +- arch/mips/lib/dump_tlb.c | 4 +- arch/mips/lib/r3k_dump_tlb.c | 4 +- arch/mips/math-emu/cp1emu.c | 2 +- arch/mips/mips-boards/atlas/atlas_setup.c | 2 +- arch/mips/mips-boards/malta/malta_setup.c | 2 +- arch/mips/mips-boards/sead/sead_setup.c | 2 +- arch/mips/mm/c-mips32.c | 43 ++-- arch/mips/mm/c-r4k.c | 8 +- arch/mips/mm/c-tx39.c | 28 +-- arch/mips/mm/c-tx49.c | 16 +- arch/mips/mm/init.c | 2 +- arch/mips/mm/loadmmu.c | 4 +- arch/mips/mm/pg-mips32.c | 8 +- arch/mips/mm/tlb-r3k.c | 8 +- arch/mips/mm/tlb-r4k.c | 18 +- arch/mips/mm/tlb-sb1.c | 12 +- arch/mips/sgi-ip27/ip27-init.c | 3 +- arch/mips/vr41xx/common/bcu.c | 12 +- arch/mips/vr41xx/common/cmu.c | 2 +- arch/mips/vr41xx/common/giu.c | 2 +- arch/mips/vr41xx/common/icu.c | 2 +- arch/mips/vr41xx/common/pciu.c | 2 +- arch/mips/vr41xx/common/serial.c | 7 +- arch/mips/vr41xx/common/time.c | 2 +- arch/mips/vr41xx/zao-capcella/init.c | 2 +- arch/mips64/kernel/branch.c | 2 +- arch/mips64/kernel/cpu-probe.c | 323 +++++++++++++++--------------- arch/mips64/kernel/proc.c | 18 +- arch/mips64/kernel/ptrace.c | 8 +- arch/mips64/kernel/setup.c | 2 +- arch/mips64/kernel/smp.c | 3 +- arch/mips64/kernel/time.c | 10 +- arch/mips64/kernel/traps.c | 29 +-- arch/mips64/lib/dump_tlb.c | 4 +- arch/mips64/mm/c-mips64.c | 64 +++--- arch/mips64/mm/c-r4k.c | 8 +- arch/mips64/mm/init.c | 2 +- arch/mips64/mm/loadmmu.c | 4 +- arch/mips64/mm/pg-mips64.c | 8 +- arch/mips64/mm/tlb-r4k.c | 14 +- arch/mips64/mm/tlb-sb1.c | 12 +- include/asm-mips/cache.h | 23 +-- include/asm-mips/cpu.h | 18 -- include/asm-mips/fpu.h | 18 +- include/asm-mips/mips32_cache.h | 50 ++--- include/asm-mips/processor.h | 38 +++- include/asm-mips/r4kcache.h | 60 +++--- include/asm-mips64/bootinfo.h | 2 +- include/{asm-mips => asm-mips64}/cache.h | 23 +-- include/asm-mips64/cpu.h | 18 -- include/asm-mips64/fpu.h | 18 +- include/asm-mips64/mips64_cache.h | 54 +++-- include/asm-mips64/processor.h | 39 +++- include/asm-mips64/r4kcache.h | 92 ++++++--- 67 files changed, 787 insertions(+), 787 deletions(-) copy include/{asm-mips => asm-mips64}/cache.h (55%) diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c index 9b292debbff..d3821365c05 100644 --- a/arch/mips/ddb5xxx/ddb5477/setup.c +++ b/arch/mips/ddb5xxx/ddb5477/setup.c @@ -143,7 +143,7 @@ static void __init ddb_time_init(void) /* mips_counter_frequency is 1/2 of the cpu core freq */ i = (read_32bit_cp0_register(CP0_CONFIG) >> 28 ) & 7; - if ((mips_cpu.cputype == CPU_R5432) && (i == 3)) + if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) i = 4; mips_counter_frequency = bus_frequency*(i+4)/4; } diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c index 352540c0b58..fb0d8f76365 100644 --- a/arch/mips/dec/prom/init.c +++ b/arch/mips/dec/prom/init.c @@ -94,8 +94,8 @@ int __init prom_init(s32 argc, s32 *argv, u32 magic, s32 *prom_vec) /* Were we compiled with the right CPU option? */ #if defined(CONFIG_CPU_R3000) - if ((mips_cpu.cputype == CPU_R4000SC) || - (mips_cpu.cputype == CPU_R4400SC)) { + if ((current_cpu_data.cputype == CPU_R4000SC) || + (current_cpu_data.cputype == CPU_R4400SC)) { prom_printf("Sorry, this kernel is compiled for the wrong CPU type!\n"); prom_printf("Please recompile with \"CONFIG_CPU_R4x00 = y\"\n"); dec_machine_halt(); @@ -103,8 +103,8 @@ int __init prom_init(s32 argc, s32 *argv, u32 magic, s32 *prom_vec) #endif #if defined(CONFIG_CPU_R4X00) - if ((mips_cpu.cputype == CPU_R3000) || - (mips_cpu.cputype == CPU_R3000A)) { + if ((current_cpu_data.cputype == CPU_R3000) || + (current_cpu_data.cputype == CPU_R3000A)) { prom_printf("Sorry, this kernel is compiled for the wrong CPU type!\n"); prom_printf("Please recompile with \"CONFIG_CPU_R3000 = y\"\n"); dec_machine_halt(); diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index 864db69317c..6985f005cf2 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -722,7 +722,7 @@ void __init init_IRQ(void) set_except_vector(0, decstation_handle_int); /* Free the FPU interrupt if the exception is present. */ - if (!(mips_cpu.options & MIPS_CPU_NOFPUEX)) { + if (!(current_cpu_data.options & MIPS_CPU_NOFPUEX)) { cpu_fpu_mask = 0; dec_interrupt[DEC_IRQ_FPU] = -1; } diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c index e33a785edc4..071586442e1 100644 --- a/arch/mips/dec/time.c +++ b/arch/mips/dec/time.c @@ -478,7 +478,7 @@ void __init time_init(void) xtime.tv_usec = 0; write_unlock_irq(&xtime_lock); - if (mips_cpu.options & MIPS_CPU_COUNTER) { + if (current_cpu_data.options & MIPS_CPU_COUNTER) { write_c0_count(0); do_gettimeoffset = do_fast_gettimeoffset; irq0.handler = r4k_timer_interrupt; diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index 8165789cbeb..c6b13fdfb18 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -163,7 +163,7 @@ int __compute_return_epc(struct pt_regs *regs) * And now the FPA/cp1 branch instructions. */ case cop1_op: - if (!(mips_cpu.options & MIPS_CPU_FPU)) + if (!(current_cpu_data.options & MIPS_CPU_FPU)) fcr31 = current->thread.fpu.soft.sr; else asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0095647ead8..46080426328 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -49,7 +49,7 @@ void au1k_wait(void) static inline void check_wait(void) { printk("Checking for 'wait' instruction... "); - switch(mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_R3081: case CPU_R3081E: cpu_wait = r3081_wait; @@ -139,16 +139,6 @@ static inline int cpu_has_fpu(void) return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); } -/* declaration of the global struct */ -struct mips_cpu mips_cpu = { - .processor_id = PRID_IMP_UNKNOWN, - .fpu_id = FPIR_IMP_NONE, - .cputype = CPU_UNKNOWN -}; - -/* Shortcut for assembler access to mips_cpu.options */ -int *cpuoptions = &mips_cpu.options; - #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ | MIPS_CPU_COUNTER | MIPS_CPU_CACHE_CDEX) @@ -157,110 +147,117 @@ __init void cpu_probe(void) #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) unsigned long config0 = read_c0_config(); unsigned long config1; +#endif + current_cpu_data.processor_id = PRID_IMP_UNKNOWN; + current_cpu_data.fpu_id = FPIR_IMP_NONE; + current_cpu_data.cputype = CPU_UNKNOWN; + +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) if (config0 & (1 << 31)) { /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */ - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC; config1 = read_c0_config1(); if (config1 & (1 << 3)) - mips_cpu.options |= MIPS_CPU_WATCH; + current_cpu_data.options |= MIPS_CPU_WATCH; if (config1 & (1 << 2)) - mips_cpu.options |= MIPS_CPU_MIPS16; + current_cpu_data.options |= MIPS_CPU_MIPS16; if (config1 & (1 << 1)) - mips_cpu.options |= MIPS_CPU_EJTAG; + current_cpu_data.options |= MIPS_CPU_EJTAG; if (config1 & 1) { - mips_cpu.options |= MIPS_CPU_FPU; + current_cpu_data.options |= MIPS_CPU_FPU; #if defined(CONFIG_CPU_MIPS64) - mips_cpu.options |= MIPS_CPU_32FPR; + current_cpu_data.options |= MIPS_CPU_32FPR; #endif } - mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT; + current_cpu_data.scache.flags = MIPS_CACHE_NOT_PRESENT; } #endif - mips_cpu.processor_id = read_c0_prid(); - switch (mips_cpu.processor_id & 0xff0000) { + current_cpu_data.processor_id = read_c0_prid(); + switch (current_cpu_data.processor_id & 0xff0000) { case PRID_COMP_LEGACY: - switch (mips_cpu.processor_id & 0xff00) { + switch (current_cpu_data.processor_id & 0xff00) { case PRID_IMP_R2000: - mips_cpu.cputype = CPU_R2000; - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; + current_cpu_data.cputype = CPU_R2000; + current_cpu_data.isa_level = MIPS_CPU_ISA_I; + current_cpu_data.options = MIPS_CPU_TLB | + MIPS_CPU_NOFPUEX; if (cpu_has_fpu()) - mips_cpu.options |= MIPS_CPU_FPU; - mips_cpu.tlbsize = 64; + current_cpu_data.options |= MIPS_CPU_FPU; + current_cpu_data.tlbsize = 64; break; case PRID_IMP_R3000: - if ((mips_cpu.processor_id & 0xff) == PRID_REV_R3000A) + if ((current_cpu_data.processor_id & 0xff) == PRID_REV_R3000A) if (cpu_has_confreg()) - mips_cpu.cputype = CPU_R3081E; + current_cpu_data.cputype = CPU_R3081E; else - mips_cpu.cputype = CPU_R3000A; + current_cpu_data.cputype = CPU_R3000A; else - mips_cpu.cputype = CPU_R3000; - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; + current_cpu_data.cputype = CPU_R3000; + current_cpu_data.isa_level = MIPS_CPU_ISA_I; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; if (cpu_has_fpu()) - mips_cpu.options |= MIPS_CPU_FPU; - mips_cpu.tlbsize = 64; + current_cpu_data.options |= MIPS_CPU_FPU; + current_cpu_data.tlbsize = 64; break; case PRID_IMP_R4000: - if ((mips_cpu.processor_id & 0xff) >= PRID_REV_R4400) - mips_cpu.cputype = CPU_R4400SC; + if ((current_cpu_data.processor_id & 0xff) >= PRID_REV_R4400) + current_cpu_data.cputype = CPU_R4400SC; else - mips_cpu.cputype = CPU_R4000SC; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R4000SC; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_VCE; - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; break; case PRID_IMP_VR41XX: - switch (mips_cpu.processor_id & 0xf0) { + switch (current_cpu_data.processor_id & 0xf0) { #ifndef CONFIG_VR4181 case PRID_REV_VR4111: - mips_cpu.cputype = CPU_VR4111; + current_cpu_data.cputype = CPU_VR4111; break; #else case PRID_REV_VR4181: - mips_cpu.cputype = CPU_VR4181; + current_cpu_data.cputype = CPU_VR4181; break; #endif case PRID_REV_VR4121: - mips_cpu.cputype = CPU_VR4121; + current_cpu_data.cputype = CPU_VR4121; break; case PRID_REV_VR4122: - if ((mips_cpu.processor_id & 0xf) < 0x3) - mips_cpu.cputype = CPU_VR4122; + if ((current_cpu_data.processor_id & 0xf) < 0x3) + current_cpu_data.cputype = CPU_VR4122; else - mips_cpu.cputype = CPU_VR4181A; + current_cpu_data.cputype = CPU_VR4181A; break; case PRID_REV_VR4131: - mips_cpu.cputype = CPU_VR4131; - mips_cpu.icache.ways = 2; - mips_cpu.dcache.ways = 2; + current_cpu_data.cputype = CPU_VR4131; + current_cpu_data.icache.ways = 2; + current_cpu_data.dcache.ways = 2; break; default: printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); - mips_cpu.cputype = CPU_VR41XX; + current_cpu_data.cputype = CPU_VR41XX; break; } - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS; - mips_cpu.tlbsize = 32; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS; + current_cpu_data.tlbsize = 32; break; case PRID_IMP_R4300: - mips_cpu.cputype = CPU_R4300; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R4300; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 32; + current_cpu_data.tlbsize = 32; break; case PRID_IMP_R4600: - mips_cpu.cputype = CPU_R4600; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU; - mips_cpu.tlbsize = 48; + current_cpu_data.cputype = CPU_R4600; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU; + current_cpu_data.tlbsize = 48; break; #if 0 case PRID_IMP_R4650: @@ -270,100 +267,100 @@ __init void cpu_probe(void) * for documentation. Commented out because it shares * it's c0_prid id number with the TX3900. */ - mips_cpu.cputype = CPU_R4650; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU; - mips_cpu.tlbsize = 48; + current_cpu_data.cputype = CPU_R4650; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU; + current_cpu_data.tlbsize = 48; break; #endif case PRID_IMP_TX39: - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB; + current_cpu_data.isa_level = MIPS_CPU_ISA_I; + current_cpu_data.options = MIPS_CPU_TLB; - if ((mips_cpu.processor_id & 0xf0) == + if ((current_cpu_data.processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { - mips_cpu.cputype = CPU_TX3927; - mips_cpu.tlbsize = 64; - mips_cpu.icache.ways = 2; - mips_cpu.dcache.ways = 2; + current_cpu_data.cputype = CPU_TX3927; + current_cpu_data.tlbsize = 64; + current_cpu_data.icache.ways = 2; + current_cpu_data.dcache.ways = 2; } else { - switch (mips_cpu.processor_id & 0xff) { + switch (current_cpu_data.processor_id & 0xff) { case PRID_REV_TX3912: - mips_cpu.cputype = CPU_TX3912; - mips_cpu.tlbsize = 32; + current_cpu_data.cputype = CPU_TX3912; + current_cpu_data.tlbsize = 32; break; case PRID_REV_TX3922: - mips_cpu.cputype = CPU_TX3922; - mips_cpu.tlbsize = 64; + current_cpu_data.cputype = CPU_TX3922; + current_cpu_data.tlbsize = 64; break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; break; } } break; case PRID_IMP_R4700: - mips_cpu.cputype = CPU_R4700; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R4700; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; break; case PRID_IMP_TX49: - mips_cpu.cputype = CPU_TX49XX; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_TX49XX; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 48; - mips_cpu.icache.ways = 4; - mips_cpu.dcache.ways = 4; + current_cpu_data.tlbsize = 48; + current_cpu_data.icache.ways = 4; + current_cpu_data.dcache.ways = 4; break; case PRID_IMP_R5000: - mips_cpu.cputype = CPU_R5000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R5000; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; break; case PRID_IMP_R5432: - mips_cpu.cputype = CPU_R5432; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R5432; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH; - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; break; case PRID_IMP_R5500: - mips_cpu.cputype = CPU_R5500; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R5500; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH; - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; break; case PRID_IMP_NEVADA: - mips_cpu.cputype = CPU_NEVADA; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_NEVADA; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_DIVEC; - mips_cpu.tlbsize = 48; - mips_cpu.icache.ways = 2; - mips_cpu.dcache.ways = 2; + current_cpu_data.tlbsize = 48; + current_cpu_data.icache.ways = 2; + current_cpu_data.dcache.ways = 2; break; case PRID_IMP_R6000: - mips_cpu.cputype = CPU_R6000; - mips_cpu.isa_level = MIPS_CPU_ISA_II; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU; - mips_cpu.tlbsize = 32; + current_cpu_data.cputype = CPU_R6000; + current_cpu_data.isa_level = MIPS_CPU_ISA_II; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_FPU; + current_cpu_data.tlbsize = 32; break; case PRID_IMP_R6000A: - mips_cpu.cputype = CPU_R6000A; - mips_cpu.isa_level = MIPS_CPU_ISA_II; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU; - mips_cpu.tlbsize = 32; + current_cpu_data.cputype = CPU_R6000A; + current_cpu_data.isa_level = MIPS_CPU_ISA_II; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_FPU; + current_cpu_data.tlbsize = 32; break; case PRID_IMP_RM7000: - mips_cpu.cputype = CPU_RM7000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_RM7000; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; /* * Undocumented RM7000: Bit 29 in the info register of @@ -373,119 +370,119 @@ __init void cpu_probe(void) * 29 1 => 64 entry JTLB * 0 => 48 entry JTLB */ - mips_cpu.tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; + current_cpu_data.tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; break; case PRID_IMP_R8000: - mips_cpu.cputype = CPU_R8000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + current_cpu_data.cputype = CPU_R8000; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 384; /* has weird TLB: 3-way x 128 */ + current_cpu_data.tlbsize = 384; /* has weird TLB: 3-way x 128 */ break; case PRID_IMP_R10000: - mips_cpu.cputype = CPU_R10000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + current_cpu_data.cputype = CPU_R10000; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH; - mips_cpu.tlbsize = 64; + current_cpu_data.tlbsize = 64; break; case PRID_IMP_R12000: - mips_cpu.cputype = CPU_R12000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + current_cpu_data.cputype = CPU_R12000; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH; - mips_cpu.tlbsize = 64; + current_cpu_data.tlbsize = 64; break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; break; } break; #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) case PRID_COMP_MIPS: - switch (mips_cpu.processor_id & 0xff00) { + switch (current_cpu_data.processor_id & 0xff00) { case PRID_IMP_4KC: - mips_cpu.cputype = CPU_4KC; - mips_cpu.isa_level = MIPS_CPU_ISA_M32; + current_cpu_data.cputype = CPU_4KC; + current_cpu_data.isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_4KEC: - mips_cpu.cputype = CPU_4KEC; - mips_cpu.isa_level = MIPS_CPU_ISA_M32; + current_cpu_data.cputype = CPU_4KEC; + current_cpu_data.isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_4KSC: - mips_cpu.cputype = CPU_4KSC; - mips_cpu.isa_level = MIPS_CPU_ISA_M32; + current_cpu_data.cputype = CPU_4KSC; + current_cpu_data.isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_5KC: - mips_cpu.cputype = CPU_5KC; - mips_cpu.isa_level = MIPS_CPU_ISA_M64; + current_cpu_data.cputype = CPU_5KC; + current_cpu_data.isa_level = MIPS_CPU_ISA_M64; break; case PRID_IMP_20KC: - mips_cpu.cputype = CPU_20KC; - mips_cpu.isa_level = MIPS_CPU_ISA_M64; + current_cpu_data.cputype = CPU_20KC; + current_cpu_data.isa_level = MIPS_CPU_ISA_M64; break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; break; } break; case PRID_COMP_ALCHEMY: - switch (mips_cpu.processor_id & 0xff00) { + switch (current_cpu_data.processor_id & 0xff00) { case PRID_IMP_AU1_REV1: case PRID_IMP_AU1_REV2: - switch ((mips_cpu.processor_id >> 24) & 0xff) { + switch ((current_cpu_data.processor_id >> 24) & 0xff) { case 0: - mips_cpu.cputype = CPU_AU1000; + current_cpu_data.cputype = CPU_AU1000; break; case 1: - mips_cpu.cputype = CPU_AU1500; + current_cpu_data.cputype = CPU_AU1500; break; case 2: - mips_cpu.cputype = CPU_AU1100; + current_cpu_data.cputype = CPU_AU1100; break; default: panic("Unknown Au Core!"); break; } - mips_cpu.isa_level = MIPS_CPU_ISA_M32; + current_cpu_data.isa_level = MIPS_CPU_ISA_M32; break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; break; } break; #endif /* CONFIG_CPU_MIPS32 */ case PRID_COMP_SIBYTE: - switch (mips_cpu.processor_id & 0xff00) { + switch (current_cpu_data.processor_id & 0xff00) { case PRID_IMP_SB1: - mips_cpu.cputype = CPU_SB1; - mips_cpu.isa_level = MIPS_CPU_ISA_M64; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + current_cpu_data.cputype = CPU_SB1; + current_cpu_data.isa_level = MIPS_CPU_ISA_M64; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_MCHECK | MIPS_CPU_EJTAG | MIPS_CPU_WATCH; #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS /* FPU in pass1 is known to have issues. */ - mips_cpu.options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; + current_cpu_data.options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; #endif break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; break; } break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; } - if (mips_cpu.options & MIPS_CPU_FPU) - mips_cpu.fpu_id = cpu_get_fpu_id(); + if (current_cpu_data.options & MIPS_CPU_FPU) + current_cpu_data.fpu_id = cpu_get_fpu_id(); } __init void cpu_report(void) { - printk("CPU revision is: %08x\n", mips_cpu.processor_id); - if (mips_cpu.options & MIPS_CPU_FPU) - printk("FPU revision is: %08x\n", mips_cpu.fpu_id); + printk("CPU revision is: %08x\n", current_cpu_data.processor_id); + if (current_cpu_data.options & MIPS_CPU_FPU) + printk("FPU revision is: %08x\n", current_cpu_data.fpu_id); } diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 03e2fe1515b..e748ad77ca2 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -79,8 +79,8 @@ static const char *cpu_name[] = { static int show_cpuinfo(struct seq_file *m, void *v) { - unsigned int version = mips_cpu.processor_id; - unsigned int fp_vers = mips_cpu.fpu_id; + unsigned int version = current_cpu_data.processor_id; + unsigned int fp_vers = current_cpu_data.fpu_id; unsigned long n = (unsigned long) v - 1; char fmt [64]; @@ -97,9 +97,9 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", - (mips_cpu.options & MIPS_CPU_FPU) ? " FPU V%d.%d" : ""); - seq_printf(m, fmt, cpu_name[mips_cpu.cputype <= CPU_LAST ? - mips_cpu.cputype : CPU_UNKNOWN], + (current_cpu_data.options & MIPS_CPU_FPU) ? " FPU V%d.%d" : ""); + seq_printf(m, fmt, cpu_name[current_cpu_data.cputype <= CPU_LAST ? + current_cpu_data.cputype : CPU_UNKNOWN], (version >> 4) & 0x0f, version & 0x0f, (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", @@ -107,15 +107,15 @@ static int show_cpuinfo(struct seq_file *m, void *v) (loops_per_jiffy / (5000/HZ)) % 100); seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); seq_printf(m, "microsecond timers\t: %s\n", - (mips_cpu.options & MIPS_CPU_COUNTER) ? "yes" : "no"); - seq_printf(m, "tlb_entries\t\t: %d\n", mips_cpu.tlbsize); + (current_cpu_data.options & MIPS_CPU_COUNTER) ? "yes" : "no"); + seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize); seq_printf(m, "extra interrupt vector\t: %s\n", - (mips_cpu.options & MIPS_CPU_DIVEC) ? "yes" : "no"); + (current_cpu_data.options & MIPS_CPU_DIVEC) ? "yes" : "no"); seq_printf(m, "hardware watchpoint\t: %s\n", watch_available ? "yes" : "no"); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", - (mips_cpu.options & MIPS_CPU_VCE) ? "%d" : "not available"); + (current_cpu_data.options & MIPS_CPU_VCE) ? "%d" : "not available"); seq_printf(m, fmt, 'D', vced_count); seq_printf(m, fmt, 'I', vcei_count); diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 438ed3fa382..52ea0c13d26 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -143,7 +143,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) tmp = regs->lo; break; case FPC_CSR: - if (!(mips_cpu.options & MIPS_CPU_FPU)) + if (!(current_cpu_data.options & MIPS_CPU_FPU)) tmp = child->thread.fpu.soft.sr; else tmp = child->thread.fpu.hard.control; @@ -151,7 +151,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) case FPC_EIR: { /* implementation / version register */ unsigned int flags; - if (!(mips_cpu.options & MIPS_CPU_FPU)) { + if (!(current_cpu_data.options & MIPS_CPU_FPU)) { break; } @@ -222,7 +222,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) regs->lo = data; break; case FPC_CSR: - if (!(mips_cpu.options & MIPS_CPU_FPU)) + if (!(current_cpu_data.options & MIPS_CPU_FPU)) child->thread.fpu.soft.sr = data; else child->thread.fpu.hard.control = data; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index df8bd2b1026..73a6107c8cb 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -691,7 +691,8 @@ void __init setup_arch(char **cmdline_p) int __init fpu_disable(char *s) { - mips_cpu.options &= ~MIPS_CPU_FPU; + current_cpu_data.options &= ~MIPS_CPU_FPU; + return 1; } __setup("nofpu", fpu_disable); diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index ff2e483a7e1..8c34d67d7e8 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -77,7 +77,7 @@ unsigned long cache_decay_ticks; void smp_tune_scheduling (void) { - struct cache_desc *cd = &mips_cpu.scache; + struct cache_desc *cd = ¤t_cpu_data.scache; unsigned long cachesize; /* kB */ unsigned long bandwidth = 350; /* MB/s */ unsigned long cpu_khz; @@ -135,6 +135,7 @@ asmlinkage void start_secondary(void) { unsigned int cpu = smp_processor_id(); + cpu_probe(); prom_init_secondary(); per_cpu_trap_init(); diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 3c0e783c05b..76fcb624534 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -340,7 +340,7 @@ void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) */ void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - if (mips_cpu.options & MIPS_CPU_COUNTER) { + if (current_cpu_data.options & MIPS_CPU_COUNTER) { unsigned int count; /* @@ -492,15 +492,15 @@ void __init time_init(void) xtime.tv_nsec = 0; /* choose appropriate gettimeoffset routine */ - if (!(mips_cpu.options & MIPS_CPU_COUNTER)) { + if (!(current_cpu_data.options & MIPS_CPU_COUNTER)) { /* no cpu counter - sorry */ do_gettimeoffset = null_gettimeoffset; } else if (mips_counter_frequency != 0) { /* we have cpu counter and know counter frequency! */ do_gettimeoffset = fixed_rate_gettimeoffset; - } else if ((mips_cpu.isa_level == MIPS_CPU_ISA_M32) || - (mips_cpu.isa_level == MIPS_CPU_ISA_I) || - (mips_cpu.isa_level == MIPS_CPU_ISA_II) ) { + } else if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32) || + (current_cpu_data.isa_level == MIPS_CPU_ISA_I) || + (current_cpu_data.isa_level == MIPS_CPU_ISA_II) ) { /* we need to calibrate the counter but we don't have * 64-bit division. */ do_gettimeoffset = calibrate_div32_gettimeoffset; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index d46567b0019..ec21ebe6e1b 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -690,7 +690,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) init_fpu(); current->used_math = 1; } - if (!(mips_cpu.options & MIPS_CPU_FPU)) { + if (!(current_cpu_data.options & MIPS_CPU_FPU)) { int sig = fpu_emulator_cop1Handler(0, regs, ¤t->thread.fpu.soft); if (sig) force_sig(sig, current); @@ -700,7 +700,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) bad_cid: #ifndef CONFIG_CPU_HAS_LLSC - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_TX3927: case CPU_TX39XX: do_ri(regs); @@ -753,7 +753,7 @@ asmlinkage void do_reserved(struct pt_regs *regs) static inline void watch_init(void) { - if (mips_cpu.options & MIPS_CPU_WATCH) { + if (current_cpu_data.options & MIPS_CPU_WATCH) { set_except_vector(23, handle_watch); watch_available = 1; } @@ -765,7 +765,7 @@ static inline void watch_init(void) */ static inline void parity_protection_init(void) { - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_5KC: /* Set the PE bit (bit 31) in the c0_ecc register. */ printk(KERN_INFO "Enable the cache parity protection for " @@ -870,7 +870,7 @@ void *set_except_vector(int n, void *addr) unsigned long old_handler = exception_handlers[n]; exception_handlers[n] = handler; - if (n == 0 && mips_cpu.options & MIPS_CPU_DIVEC) { + if (n == 0 && current_cpu_data.options & MIPS_CPU_DIVEC) { *(volatile u32 *)(KSEG0+0x200) = 0x08000000 | (0x03ffffff & (handler >> 2)); flush_icache_range(KSEG0+0x200, KSEG0 + 0x204); @@ -898,7 +898,7 @@ void __init per_cpu_trap_init(void) * Some MIPS CPUs have a dedicated interrupt vector which reduces the * interrupt processing overhead. Use it where available. */ - if (mips_cpu.options & MIPS_CPU_DIVEC) + if (current_cpu_data.options & MIPS_CPU_DIVEC) set_c0_cause(CAUSEF_IV); cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; @@ -928,7 +928,7 @@ void __init trap_init(void) * Copy the EJTAG debug exception vector handler code to it's final * destination. */ - if (mips_cpu.options & MIPS_CPU_EJTAG) + if (current_cpu_data.options & MIPS_CPU_EJTAG) memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80); /* @@ -941,7 +941,7 @@ void __init trap_init(void) * Some MIPS CPUs have a dedicated interrupt vector which reduces the * interrupt processing overhead. Use it where available. */ - if (mips_cpu.options & MIPS_CPU_DIVEC) + if (current_cpu_data.options & MIPS_CPU_DIVEC) memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8); /* @@ -974,21 +974,21 @@ void __init trap_init(void) set_except_vector(13, handle_tr); set_except_vector(22, handle_mdmx); - if ((mips_cpu.options & MIPS_CPU_FPU) && - !(mips_cpu.options & MIPS_CPU_NOFPUEX)) + if ((current_cpu_data.options & MIPS_CPU_FPU) && + !(current_cpu_data.options & MIPS_CPU_NOFPUEX)) set_except_vector(15, handle_fpe); - if (mips_cpu.options & MIPS_CPU_MCHECK) + if (current_cpu_data.options & MIPS_CPU_MCHECK) set_except_vector(24, handle_mcheck); - if (mips_cpu.options & MIPS_CPU_VCE) + if (current_cpu_data.options & MIPS_CPU_VCE) memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80); - else if (mips_cpu.options & MIPS_CPU_4KEX) + else if (current_cpu_data.options & MIPS_CPU_4KEX) memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); else memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80); - if (mips_cpu.cputype == CPU_R6000 || mips_cpu.cputype == CPU_R6000A) { + if (current_cpu_data.cputype == CPU_R6000 || current_cpu_data.cputype == CPU_R6000A) { /* * The R6000 is the only R-series CPU that features a machine * check exception (similar to the R4000 cache error) and @@ -1001,7 +1001,7 @@ void __init trap_init(void) //set_except_vector(15, handle_ndc); } - if (mips_cpu.options & MIPS_CPU_FPU) { + if (current_cpu_data.options & MIPS_CPU_FPU) { save_fp_context = _save_fp_context; restore_fp_context = _restore_fp_context; } else { @@ -1011,7 +1011,7 @@ void __init trap_init(void) flush_icache_range(KSEG0, KSEG0 + 0x400); - if (mips_cpu.isa_level == MIPS_CPU_ISA_IV) + if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) set_c0_status(ST0_XX); atomic_inc(&init_mm.mm_count); /* XXX UP? */ diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c index e21d22348be..984a7afe0e7 100644 --- a/arch/mips/lasat/prom.c +++ b/arch/mips/lasat/prom.c @@ -98,7 +98,7 @@ void __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { setup_prom_vectors(); - if (mips_cpu.cputype == CPU_R5000) + if (current_cpu_data.cputype == CPU_R5000) mips_machtype = MACH_LASAT_200; else mips_machtype = MACH_LASAT_100; diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index fca63b93e90..e77edb7c50f 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c @@ -91,7 +91,7 @@ void dump_tlb(int first, int last) void dump_tlb_all(void) { - dump_tlb(0, mips_cpu.tlbsize - 1); + dump_tlb(0, current_cpu_data.tlbsize - 1); } void dump_tlb_wired(void) @@ -138,7 +138,7 @@ dump_tlb_addr(unsigned long addr) void dump_tlb_nonwired(void) { - dump_tlb(read_c0_wired(), mips_cpu.tlbsize - 1); + dump_tlb(read_c0_wired(), current_cpu_data.tlbsize - 1); } void diff --git a/arch/mips/lib/r3k_dump_tlb.c b/arch/mips/lib/r3k_dump_tlb.c index b0f04d868d7..8f0535a7040 100644 --- a/arch/mips/lib/r3k_dump_tlb.c +++ b/arch/mips/lib/r3k_dump_tlb.c @@ -66,7 +66,7 @@ dump_tlb(int first, int last) void dump_tlb_all(void) { - dump_tlb(0, mips_cpu.tlbsize - 1); + dump_tlb(0, current_cpu_data.tlbsize - 1); } void @@ -105,7 +105,7 @@ void dump_tlb_nonwired(void) { int wired = r3k_have_wired_reg ? read_c0_wired() : 8; - dump_tlb(wired, mips_cpu.tlbsize - 1); + dump_tlb(wired, current_cpu_data.tlbsize - 1); } void diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index dbdf87b6e6b..f99956dd823 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -1313,7 +1313,7 @@ int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, sig = cop1Emulate(xcp, ctx); } - if (mips_cpu.options & MIPS_CPU_FPU) + if (current_cpu_data.options & MIPS_CPU_FPU) break; if (sig) break; diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c index 077987d2dcb..5a3e8df5e9a 100644 --- a/arch/mips/mips-boards/atlas/atlas_setup.c +++ b/arch/mips/mips-boards/atlas/atlas_setup.c @@ -122,7 +122,7 @@ void __init atlas_setup(void) argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "nofpu")) != NULL) - mips_cpu.options &= ~MIPS_CPU_FPU; + current_cpu_data.options &= ~MIPS_CPU_FPU; rtc_ops = &atlas_rtc_ops; board_time_init = mips_time_init; diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index e0a8d39e78a..92ae2f191de 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -135,7 +135,7 @@ void __init malta_setup(void) argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "nofpu")) != NULL) - mips_cpu.options &= ~MIPS_CPU_FPU; + current_cpu_data.options &= ~MIPS_CPU_FPU; rtc_ops = &malta_rtc_ops; diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c index 9f8ab9bcfa1..1acb5efaee0 100644 --- a/arch/mips/mips-boards/sead/sead_setup.c +++ b/arch/mips/mips-boards/sead/sead_setup.c @@ -72,7 +72,7 @@ void __init sead_setup(void) argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "nofpu")) != NULL) - mips_cpu.options &= ~MIPS_CPU_FPU; + current_cpu_data.options &= ~MIPS_CPU_FPU; board_time_init = mips_time_init; board_timer_setup = mips_timer_setup; diff --git a/arch/mips/mm/c-mips32.c b/arch/mips/mm/c-mips32.c index b79041bce75..80dec12bd96 100644 --- a/arch/mips/mm/c-mips32.c +++ b/arch/mips/mm/c-mips32.c @@ -228,7 +228,7 @@ static void mips32_flush_cache_sigtramp(unsigned long addr) static void mips32_flush_icache_all(void) { - if (mips_cpu.icache.flags | MIPS_CACHE_VTAG_CACHE) + if (current_cpu_data.icache.flags | MIPS_CACHE_VTAG_CACHE) blast_icache(); } @@ -238,31 +238,32 @@ static void __init probe_icache(unsigned long config) unsigned long config1; unsigned int lsize; - mips_cpu.icache.flags = 0; + current_cpu_data.icache.flags = 0; config1 = read_c0_config1(); if ((lsize = ((config1 >> 19) & 7))) - mips_cpu.icache.linesz = 2 << lsize; + current_cpu_data.icache.linesz = 2 << lsize; else - mips_cpu.icache.linesz = lsize; - mips_cpu.icache.sets = 64 << ((config1 >> 22) & 7); - mips_cpu.icache.ways = 1 + ((config1 >> 16) & 7); + current_cpu_data.icache.linesz = lsize; + current_cpu_data.icache.sets = 64 << ((config1 >> 22) & 7); + current_cpu_data.icache.ways = 1 + ((config1 >> 16) & 7); - ic_lsize = mips_cpu.icache.linesz; - icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways * ic_lsize; + ic_lsize = current_cpu_data.icache.linesz; + icache_size = current_cpu_data.icache.sets * + current_cpu_data.icache.ways * ic_lsize; - if ((config & 0x8) || (mips_cpu.cputype == CPU_20KC)) { + if ((config & 0x8) || (current_cpu_data.cputype == CPU_20KC)) { /* * The CPU has a virtually tagged I-cache. * Some older 20Kc chips doesn't have the 'VI' bit in * the config register, so we also check for 20Kc. */ - mips_cpu.icache.flags = MIPS_CACHE_VTAG_CACHE; + current_cpu_data.icache.flags = MIPS_CACHE_VTAG_CACHE; printk("Virtually tagged I-cache detected\n"); } printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n", - icache_size >> 10, ic_lsize, mips_cpu.icache.ways); + icache_size >> 10, ic_lsize, current_cpu_data.icache.ways); } static void __init probe_dcache(unsigned long config) @@ -270,21 +271,21 @@ static void __init probe_dcache(unsigned long config) unsigned long config1; unsigned int lsize; - mips_cpu.dcache.flags = 0; + current_cpu_data.dcache.flags = 0; config1 = read_c0_config1(); if ((lsize = ((config1 >> 10) & 7))) - mips_cpu.dcache.linesz = 2 << lsize; + current_cpu_data.dcache.linesz = 2 << lsize; else - mips_cpu.dcache.linesz= lsize; - mips_cpu.dcache.sets = 64 << ((config1 >> 13) & 7); - mips_cpu.dcache.ways = 1 + ((config1 >> 7) & 7); + current_cpu_data.dcache.linesz= lsize; + current_cpu_data.dcache.sets = 64 << ((config1 >> 13) & 7); + current_cpu_data.dcache.ways = 1 + ((config1 >> 7) & 7); - dc_lsize = mips_cpu.dcache.linesz; - dcache_size = mips_cpu.dcache.sets * mips_cpu.dcache.ways * dc_lsize; + dc_lsize = current_cpu_data.dcache.linesz; + dcache_size = current_cpu_data.dcache.sets * current_cpu_data.dcache.ways * dc_lsize; printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n", - dcache_size >> 10, dc_lsize, mips_cpu.dcache.ways); + dcache_size >> 10, dc_lsize, current_cpu_data.dcache.ways); } void __init ld_mmu_mips32(void) @@ -301,7 +302,7 @@ void __init ld_mmu_mips32(void) probe_icache(config); probe_dcache(config); - if (!(mips_cpu.scache.flags & MIPS_CACHE_NOT_PRESENT)) + if (!(current_cpu_data.scache.flags & MIPS_CACHE_NOT_PRESENT)) panic("Dunno how to handle MIPS32 with second level cache"); /* @@ -309,7 +310,7 @@ void __init ld_mmu_mips32(void) * code supports virtually indexed processors and will be unnecessarily * unefficient on physically indexed processors. */ - shm_align_mask = max_t(unsigned long, mips_cpu.dcache.sets * dc_lsize, + shm_align_mask = max_t(unsigned long, current_cpu_data.dcache.sets * dc_lsize, PAGE_SIZE) - 1; _clear_page = (void *)mips32_clear_page_dc; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index b4ce668ccbd..7220331f0f0 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -562,7 +562,7 @@ static void r4600v20k_flush_cache_sigtramp(unsigned long addr) static void __init probe_icache(unsigned long config) { - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR41XX: case CPU_VR4111: case CPU_VR4121: @@ -595,7 +595,7 @@ static void __init probe_icache(unsigned long config) static void __init probe_dcache(unsigned long config) { - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR41XX: case CPU_VR4111: case CPU_VR4121: @@ -766,7 +766,7 @@ static inline void __init setup_scache(unsigned int config) return; } - switch(mips_cpu.cputype) { + switch(current_cpu_data.cputype) { case CPU_R5000: case CPU_NEVADA: setup_noscache_funcs(); @@ -796,7 +796,7 @@ void __init ld_mmu_r4xx0(void) probe_dcache(config); setup_scache(config); - switch(mips_cpu.cputype) { + switch(current_cpu_data.cputype) { case CPU_R4600: /* QED style two way caches? */ case CPU_R4700: case CPU_R5000: diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index fe689c49f9d..8f3c9fcc222 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -27,8 +27,8 @@ static unsigned long icache_size, dcache_size; /* Size in bytes */ extern long scache_size; -#define icache_lsize mips_cpu.icache.linesz -#define dcache_lsize mips_cpu.dcache.linesz +#define icache_lsize current_cpu_data.icache.linesz +#define dcache_lsize current_cpu_data.dcache.linesz #include @@ -79,7 +79,7 @@ static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size) /* TX39H2,TX39H3 */ static inline void tx39_blast_dcache_page(unsigned long addr) { - if (mips_cpu.cputype != CPU_TX3912) + if (current_cpu_data.cputype != CPU_TX3912) blast_dcache16_page(addr); } @@ -311,7 +311,7 @@ static __init void tx39_probe_cache(void) dcache_size = 1 << (10 + ((config >> 16) & 3)); icache_lsize = 16; - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_TX3912: dcache_lsize = 4; break; @@ -337,7 +337,7 @@ void __init ld_mmu_tx39(void) tx39_probe_cache(); - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_TX3912: /* TX39/H core (writethru direct-map cache) */ flush_cache_all = tx39h_flush_icache_all; @@ -381,20 +381,20 @@ void __init ld_mmu_tx39(void) _dma_cache_inv = tx39_dma_cache_inv; shm_align_mask = max_t(unsigned long, - (dcache_size / mips_cpu.dcache.ways) - 1, + (dcache_size / current_cpu_data.dcache.ways) - 1, PAGE_SIZE - 1); break; } - if (mips_cpu.icache.ways == 0) - mips_cpu.icache.ways = 1; - if (mips_cpu.dcache.ways == 0) - mips_cpu.dcache.ways = 1; - mips_cpu.icache.sets = - icache_size / mips_cpu.icache.ways / mips_cpu.icache.linesz; - mips_cpu.dcache.sets = - dcache_size / mips_cpu.dcache.ways / mips_cpu.dcache.linesz; + if (current_cpu_data.icache.ways == 0) + current_cpu_data.icache.ways = 1; + if (current_cpu_data.dcache.ways == 0) + current_cpu_data.dcache.ways = 1; + current_cpu_data.icache.sets = + icache_size / current_cpu_data.icache.ways / current_cpu_data.icache.linesz; + current_cpu_data.dcache.sets = + dcache_size / current_cpu_data.dcache.ways / current_cpu_data.dcache.linesz; printk("Primary instruction cache %dkb, linesize %d bytes\n", (int) (icache_size >> 10), (int) icache_lsize); diff --git a/arch/mips/mm/c-tx49.c b/arch/mips/mm/c-tx49.c index 85df0acc942..2fc579d5e66 100644 --- a/arch/mips/mm/c-tx49.c +++ b/arch/mips/mm/c-tx49.c @@ -33,10 +33,10 @@ /* Primary cache parameters. */ static unsigned long icache_size, dcache_size; /* Size in bytes */ -#define ic_lsize mips_cpu.icache.linesz -#define dc_lsize mips_cpu.dcache.linesz -#define ic_ways mips_cpu.icache.ways -#define dc_ways mips_cpu.dcache.ways +#define ic_lsize current_cpu_data.icache.linesz +#define dc_lsize current_cpu_data.dcache.linesz +#define ic_ways current_cpu_data.icache.ways +#define dc_ways current_cpu_data.dcache.ways static unsigned long scache_size; #include @@ -271,8 +271,8 @@ static void __init probe_icache(unsigned long config) icache_size = 1 << (12 + ((config >> 9) & 7)); ic_lsize = 16 << ((config >> 5) & 1); ic_ways = 4; - mips_cpu.icache.sets = icache_size / - (ic_lsize * mips_cpu.icache.ways); + current_cpu_data.icache.sets = icache_size / + (ic_lsize * current_cpu_data.icache.ways); printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n", icache_size >> 10, ic_lsize, ic_ways); @@ -283,8 +283,8 @@ static void __init probe_dcache(unsigned long config) dcache_size = 1 << (12 + ((config >> 6) & 7)); dc_lsize = 16 << ((config >> 4) & 1); dc_ways = 4; - mips_cpu.dcache.sets = dcache_size / - (dc_lsize * mips_cpu.dcache.ways); + current_cpu_data.dcache.sets = dcache_size / + (dc_lsize * current_cpu_data.dcache.ways); printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n", dcache_size >> 10, dc_lsize, dc_ways); diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 60260512d4d..cc9963f180c 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -57,7 +57,7 @@ static inline unsigned long setup_zero_pages(void) unsigned long order, size; struct page *page; - if (mips_cpu.options & MIPS_CPU_VCE) + if (current_cpu_data.options & MIPS_CPU_VCE) order = 3; else order = 0; diff --git a/arch/mips/mm/loadmmu.c b/arch/mips/mm/loadmmu.c index d0ee4753981..96c77119dab 100644 --- a/arch/mips/mm/loadmmu.c +++ b/arch/mips/mm/loadmmu.c @@ -72,7 +72,7 @@ extern void sb1_tlb_init(void); void __init load_mmu(void) { - if (mips_cpu.options & MIPS_CPU_4KTLB) { + if (current_cpu_data.options & MIPS_CPU_4KTLB) { #if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ defined(CONFIG_CPU_NEVADA) @@ -96,7 +96,7 @@ void __init load_mmu(void) ld_mmu_mips32(); r4k_tlb_init(); #endif - } else switch(mips_cpu.cputype) { + } else switch (current_cpu_data.cputype) { #ifdef CONFIG_CPU_R3000 case CPU_R2000: case CPU_R3000: diff --git a/arch/mips/mm/pg-mips32.c b/arch/mips/mm/pg-mips32.c index 7cdfcf420d7..284e7fee094 100644 --- a/arch/mips/mm/pg-mips32.c +++ b/arch/mips/mm/pg-mips32.c @@ -34,7 +34,7 @@ void mips32_clear_page_dc(unsigned long page) { unsigned long i; - if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) { + if (current_cpu_data.options & MIPS_CPU_CACHE_CDEX) { for (i=page; i> PAGE_SHIFT; - if (size <= mips_cpu.tlbsize) { + if (size <= current_cpu_data.tlbsize) { int oldpid = read_c0_entryhi() & ASID_MASK; int newpid = cpu_context(cpu, mm) & ASID_MASK; @@ -130,7 +130,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) #endif local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - if (size <= mips_cpu.tlbsize) { + if (size <= current_cpu_data.tlbsize) { int pid = read_c0_entryhi(); start &= PAGE_MASK; diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 0bdb0ea2954..ff8e605e59c 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -54,7 +54,7 @@ void local_flush_tlb_all(void) entry = read_c0_wired(); /* Blast 'em all away. */ - while (entry < mips_cpu.tlbsize) { + while (entry < current_cpu_data.tlbsize) { /* * Make sure all entries differ. If they're not different * MIPS32 will take revenge ... @@ -100,7 +100,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; - if (size <= mips_cpu.tlbsize/2) { + if (size <= current_cpu_data.tlbsize/2) { int oldpid = read_c0_entryhi() & ASID_MASK; int newpid = cpu_context(cpu, mm) & ASID_MASK; @@ -145,7 +145,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; - if (size <= mips_cpu.tlbsize / 2) { + if (size <= current_cpu_data.tlbsize / 2) { int pid = read_c0_entryhi(); start &= (PAGE_MASK << 1); @@ -394,7 +394,7 @@ static void __init probe_tlb(unsigned long config) if (!((config >> 7) & 3)) panic("No MMU present"); else - mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1; + current_cpu_data.tlbsize = ((config1 >> 25) & 0x3f) + 1; #endif } @@ -412,14 +412,14 @@ void __init r4k_tlb_init(void) probe_tlb(config); write_c0_pagemask(PM_4K); write_c0_wired(0); - temp_tlb_entry = mips_cpu.tlbsize - 1; + temp_tlb_entry = current_cpu_data.tlbsize - 1; local_flush_tlb_all(); - if ((mips_cpu.options & MIPS_CPU_4KEX) - && (mips_cpu.options & MIPS_CPU_4KTLB)) { - if (mips_cpu.cputype == CPU_NEVADA) + if ((current_cpu_data.options & MIPS_CPU_4KEX) + && (current_cpu_data.options & MIPS_CPU_4KTLB)) { + if (current_cpu_data.cputype == CPU_NEVADA) memcpy((void *)KSEG0, &except_vec0_nevada, 0x80); - else if (mips_cpu.cputype == CPU_R4600) + else if (current_cpu_data.cputype == CPU_R4600) memcpy((void *)KSEG0, &except_vec0_r4600, 0x80); else memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); diff --git a/arch/mips/mm/tlb-sb1.c b/arch/mips/mm/tlb-sb1.c index fb745c11b2f..a9aded2d6ed 100644 --- a/arch/mips/mm/tlb-sb1.c +++ b/arch/mips/mm/tlb-sb1.c @@ -73,7 +73,7 @@ void sb1_dump_tlb(void) printk("\n\nFull TLB Dump:\n" "Idx EntryHi EntryLo0 EntryLo1 PageMask\n" "--------------------------------------------------------------\n"); - for (entry = 0; entry < mips_cpu.tlbsize; entry++) { + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { write_c0_index(entry); printk("\n%02i ", entry); tlb_read(); @@ -95,7 +95,7 @@ void local_flush_tlb_all(void) old_ctx = read_c0_entryhi() & ASID_MASK; write_c0_entrylo0(0); write_c0_entrylo1(0); - for (entry = 0; entry < mips_cpu.tlbsize; entry++) { + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { write_c0_entryhi(KSEG0 + (PAGE_SIZE << 1) * entry); write_c0_index(entry); tlb_write_indexed(); @@ -121,7 +121,7 @@ void sb1_sanitize_tlb(void) /* Save old context and create impossible VPN2 value */ write_c0_entrylo0(0); write_c0_entrylo1(0); - for (entry = 0; entry < mips_cpu.tlbsize; entry++) { + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { do { addr += inc; write_c0_entryhi(addr); @@ -148,7 +148,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, int size; size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; - if (size <= (mips_cpu.tlbsize/2)) { + if (size <= (current_cpu_data.tlbsize/2)) { int oldpid = read_c0_entryhi() & ASID_MASK; int newpid = cpu_asid(cpu, mm); @@ -186,7 +186,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) size = (size + 1) >> 1; local_irq_save(flags); - if (size <= (mips_cpu.tlbsize/2)) { + if (size <= (current_cpu_data.tlbsize/2)) { int pid = read_c0_entryhi(); start &= (PAGE_MASK << 1); @@ -352,7 +352,7 @@ void sb1_tlb_init(void) write_c0_pagemask(PM_4K); config1 = read_c0_config1(); - mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1; + current_cpu_data.tlbsize = ((config1 >> 25) & 0x3f) + 1; /* * We don't know what state the firmware left the TLB's in, so this is diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c index d78b73f78c0..745d692b4ad 100644 --- a/arch/mips/sgi-ip27/ip27-init.c +++ b/arch/mips/sgi-ip27/ip27-init.c @@ -377,7 +377,7 @@ void per_cpu_init(void) set_c0_status(SRB_DEV0 | SRB_DEV1); if (is_slave) { clear_c0_status(ST0_BEV); - if (mips_cpu.isa_level == MIPS_CPU_ISA_IV) + if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) set_c0_status(ST0_XX); set_c0_status(ST0_KX|ST0_SX|ST0_UX); sti(); @@ -425,6 +425,7 @@ static volatile cpumask_t boot_barrier; void __init start_secondary(void) { CPUMASK_CLRB(boot_barrier, getcpuid()); /* needs atomicity */ + cpu_probe(); per_cpu_init(); per_cpu_trap_init(); #if 0 diff --git a/arch/mips/vr41xx/common/bcu.c b/arch/mips/vr41xx/common/bcu.c index 7f54849f242..db20b96d508 100644 --- a/arch/mips/vr41xx/common/bcu.c +++ b/arch/mips/vr41xx/common/bcu.c @@ -69,7 +69,7 @@ unsigned long vr41xx_vtclock = 0; static inline u16 read_clkspeed(void) { - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: return readw(VR4111_CLKSPEEDREG); case CPU_VR4122: return readw(VR4122_CLKSPEEDREG); @@ -86,7 +86,7 @@ static inline unsigned long calculate_pclock(u16 clkspeed) { unsigned long pclock = 0; - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: pclock = 18432000 * 64; @@ -110,7 +110,7 @@ static inline unsigned long calculate_pclock(u16 clkspeed) static inline unsigned long calculate_vtclock(u16 clkspeed, unsigned long pclock) { - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR4111: /* The NEC VR4111 doesn't have the VTClock. */ break; @@ -151,7 +151,7 @@ static inline unsigned long calculate_tclock(u16 clkspeed, unsigned long pclock, { unsigned long tclock = 0; - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR4111: if (!(clkspeed & DIV2B)) tclock = pclock / 2; @@ -182,8 +182,8 @@ static inline unsigned long calculate_mips_counter_frequency(unsigned long tcloc /* * VR4131 Revision 2.0 and 2.1 use a value of (tclock / 2). */ - if ((mips_cpu.processor_id == PRID_VR4131_REV2_0) || - (mips_cpu.processor_id == PRID_VR4131_REV2_1)) + if ((current_cpu_data.processor_id == PRID_VR4131_REV2_0) || + (current_cpu_data.processor_id == PRID_VR4131_REV2_1)) tclock /= 2; else tclock /= 4; diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c index c80070b9416..64d8c8894b4 100644 --- a/arch/mips/vr41xx/common/cmu.c +++ b/arch/mips/vr41xx/common/cmu.c @@ -66,7 +66,7 @@ void vr41xx_clock_mask(u16 mask) void __init vr41xx_cmu_init(u16 mask) { - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: vr41xx_cmu_base = VR4111_CMUCLKMSK; diff --git a/arch/mips/vr41xx/common/giu.c b/arch/mips/vr41xx/common/giu.c index b0061855f99..d0015c64429 100644 --- a/arch/mips/vr41xx/common/giu.c +++ b/arch/mips/vr41xx/common/giu.c @@ -241,7 +241,7 @@ void __init vr41xx_giuint_init(void) { int i; - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: vr41xx_giu_base = VR4111_GIUIOSELL; diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index 88b735a1c12..9de6426649a 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c @@ -283,7 +283,7 @@ static void __init vr41xx_icu_init(void) { int i; - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: vr41xx_icu1_base = VR4111_SYSINT1REG; diff --git a/arch/mips/vr41xx/common/pciu.c b/arch/mips/vr41xx/common/pciu.c index 198743da604..5f1ae0cfad7 100644 --- a/arch/mips/vr41xx/common/pciu.c +++ b/arch/mips/vr41xx/common/pciu.c @@ -217,7 +217,7 @@ void __init vr41xx_pciu_init(struct vr41xx_pci_address_map *map) /* Clear bus error */ n = readl(BUSERRADREG); - if (mips_cpu.cputype == CPU_VR4122) { + if (current_cpu_data.cputype == CPU_VR4122) { writel(0UL, PCITRDYVREG); pciu_write_config_dword(PCI_CACHE_LINE_SIZE, 0x0000f804); } else { diff --git a/arch/mips/vr41xx/common/serial.c b/arch/mips/vr41xx/common/serial.c index e6094df389f..c8803d1d32c 100644 --- a/arch/mips/vr41xx/common/serial.c +++ b/arch/mips/vr41xx/common/serial.c @@ -99,7 +99,7 @@ void vr41xx_siu_ifselect(int interface, int module) val |= USE_IRDA | SIU_USES_IRDA; } - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: writew(val, VR4111_SIUIRSEL); @@ -126,7 +126,7 @@ void __init vr41xx_siu_init(int interface, int module) s.baud_base = SIU_BASE_BAUD; s.irq = SIU_IRQ; s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: s.iomem_base = (unsigned char *)VR4111_SIURB; @@ -153,7 +153,8 @@ void __init vr41xx_dsiu_init(void) { struct serial_struct s; - if (mips_cpu.cputype != CPU_VR4122 && mips_cpu.cputype != CPU_VR4131) + if (current_cpu_data.cputype != CPU_VR4122 && + current_cpu_data.cputype != CPU_VR4131) return; memset(&s, 0, sizeof(s)); diff --git a/arch/mips/vr41xx/common/time.c b/arch/mips/vr41xx/common/time.c index a74327eaf36..cadf68a9794 100644 --- a/arch/mips/vr41xx/common/time.c +++ b/arch/mips/vr41xx/common/time.c @@ -62,7 +62,7 @@ extern int vr41xx_rtc_set_time(unsigned long sec); void vr41xx_time_init(void) { - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: vr41xx_rtc_base = VR4111_ETIMELREG; diff --git a/arch/mips/vr41xx/zao-capcella/init.c b/arch/mips/vr41xx/zao-capcella/init.c index 98568dc7bd7..30b837a179d 100644 --- a/arch/mips/vr41xx/zao-capcella/init.c +++ b/arch/mips/vr41xx/zao-capcella/init.c @@ -51,7 +51,7 @@ void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec) mips_machgroup = MACH_GROUP_NEC_VR41XX; mips_machtype = MACH_ZAO_CAPCELLA; - switch (mips_cpu.processor_id) { + switch (current_cpu_data.processor_id) { case PRID_VR4131_REV1_2: config = read_c0_config(); config &= ~0x00000030UL; diff --git a/arch/mips64/kernel/branch.c b/arch/mips64/kernel/branch.c index 41bfe3e2a97..a36deeeba59 100644 --- a/arch/mips64/kernel/branch.c +++ b/arch/mips64/kernel/branch.c @@ -164,7 +164,7 @@ int __compute_return_epc(struct pt_regs *regs) * And now the FPA/cp1 branch instructions. */ case cop1_op: - if (!(mips_cpu.options & MIPS_CPU_FPU)) + if (!(current_cpu_data.options & MIPS_CPU_FPU)) fcr31 = current->thread.fpu.soft.sr; else asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); diff --git a/arch/mips64/kernel/cpu-probe.c b/arch/mips64/kernel/cpu-probe.c index 08b6d796c2c..3a4148c4a6f 100644 --- a/arch/mips64/kernel/cpu-probe.c +++ b/arch/mips64/kernel/cpu-probe.c @@ -66,7 +66,7 @@ void au1k_wait(void) static inline void check_wait(void) { printk("Checking for 'wait' instruction... "); - switch(mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_R3081: case CPU_R3081E: cpu_wait = r3081_wait; @@ -378,16 +378,6 @@ static inline int cpu_has_fpu(void) return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); } -/* declaration of the global struct */ -struct mips_cpu mips_cpu = { - .processor_id = PRID_IMP_UNKNOWN, - .fpu_id = FPIR_IMP_NONE, - .cputype = CPU_UNKNOWN -}; - -/* Shortcut for assembler access to mips_cpu.options */ -int *cpuoptions = &mips_cpu.options; - #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ | MIPS_CPU_COUNTER | MIPS_CPU_CACHE_CDEX) @@ -396,110 +386,117 @@ __init void cpu_probe(void) #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) unsigned long config0 = read_c0_config(); unsigned long config1; +#endif + current_cpu_data.processor_id = PRID_IMP_UNKNOWN; + current_cpu_data.fpu_id = FPIR_IMP_NONE; + current_cpu_data.cputype = CPU_UNKNOWN; + +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) if (config0 & (1 << 31)) { /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */ - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC; config1 = read_c0_config1(); if (config1 & (1 << 3)) - mips_cpu.options |= MIPS_CPU_WATCH; + current_cpu_data.options |= MIPS_CPU_WATCH; if (config1 & (1 << 2)) - mips_cpu.options |= MIPS_CPU_MIPS16; + current_cpu_data.options |= MIPS_CPU_MIPS16; if (config1 & (1 << 1)) - mips_cpu.options |= MIPS_CPU_EJTAG; + current_cpu_data.options |= MIPS_CPU_EJTAG; if (config1 & 1) { - mips_cpu.options |= MIPS_CPU_FPU; + current_cpu_data.options |= MIPS_CPU_FPU; #if defined(CONFIG_CPU_MIPS64) - mips_cpu.options |= MIPS_CPU_32FPR; + current_cpu_data.options |= MIPS_CPU_32FPR; #endif } - mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT; + current_cpu_data.scache.flags = MIPS_CACHE_NOT_PRESENT; } #endif - mips_cpu.processor_id = read_c0_prid(); - switch (mips_cpu.processor_id & 0xff0000) { + current_cpu_data.processor_id = read_c0_prid(); + switch (current_cpu_data.processor_id & 0xff0000) { case PRID_COMP_LEGACY: - switch (mips_cpu.processor_id & 0xff00) { + switch (current_cpu_data.processor_id & 0xff00) { case PRID_IMP_R2000: - mips_cpu.cputype = CPU_R2000; - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; + current_cpu_data.cputype = CPU_R2000; + current_cpu_data.isa_level = MIPS_CPU_ISA_I; + current_cpu_data.options = MIPS_CPU_TLB | + MIPS_CPU_NOFPUEX; if (cpu_has_fpu()) - mips_cpu.options |= MIPS_CPU_FPU; - mips_cpu.tlbsize = 64; + current_cpu_data.options |= MIPS_CPU_FPU; + current_cpu_data.tlbsize = 64; break; case PRID_IMP_R3000: - if ((mips_cpu.processor_id & 0xff) == PRID_REV_R3000A) + if ((current_cpu_data.processor_id & 0xff) == PRID_REV_R3000A) if (cpu_has_confreg()) - mips_cpu.cputype = CPU_R3081E; + current_cpu_data.cputype = CPU_R3081E; else - mips_cpu.cputype = CPU_R3000A; + current_cpu_data.cputype = CPU_R3000A; else - mips_cpu.cputype = CPU_R3000; - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; + current_cpu_data.cputype = CPU_R3000; + current_cpu_data.isa_level = MIPS_CPU_ISA_I; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; if (cpu_has_fpu()) - mips_cpu.options |= MIPS_CPU_FPU; - mips_cpu.tlbsize = 64; + current_cpu_data.options |= MIPS_CPU_FPU; + current_cpu_data.tlbsize = 64; break; case PRID_IMP_R4000: - if ((mips_cpu.processor_id & 0xff) >= PRID_REV_R4400) - mips_cpu.cputype = CPU_R4400SC; + if ((current_cpu_data.processor_id & 0xff) >= PRID_REV_R4400) + current_cpu_data.cputype = CPU_R4400SC; else - mips_cpu.cputype = CPU_R4000SC; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R4000SC; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_VCE; - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; break; case PRID_IMP_VR41XX: - switch (mips_cpu.processor_id & 0xf0) { + switch (current_cpu_data.processor_id & 0xf0) { #ifndef CONFIG_VR4181 case PRID_REV_VR4111: - mips_cpu.cputype = CPU_VR4111; + current_cpu_data.cputype = CPU_VR4111; break; #else case PRID_REV_VR4181: - mips_cpu.cputype = CPU_VR4181; + current_cpu_data.cputype = CPU_VR4181; break; #endif case PRID_REV_VR4121: - mips_cpu.cputype = CPU_VR4121; + current_cpu_data.cputype = CPU_VR4121; break; case PRID_REV_VR4122: - if ((mips_cpu.processor_id & 0xf) < 0x3) - mips_cpu.cputype = CPU_VR4122; + if ((current_cpu_data.processor_id & 0xf) < 0x3) + current_cpu_data.cputype = CPU_VR4122; else - mips_cpu.cputype = CPU_VR4181A; + current_cpu_data.cputype = CPU_VR4181A; break; case PRID_REV_VR4131: - mips_cpu.cputype = CPU_VR4131; - mips_cpu.icache.ways = 2; - mips_cpu.dcache.ways = 2; + current_cpu_data.cputype = CPU_VR4131; + current_cpu_data.icache.ways = 2; + current_cpu_data.dcache.ways = 2; break; default: printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); - mips_cpu.cputype = CPU_VR41XX; + current_cpu_data.cputype = CPU_VR41XX; break; } - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS; - mips_cpu.tlbsize = 32; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS; + current_cpu_data.tlbsize = 32; break; case PRID_IMP_R4300: - mips_cpu.cputype = CPU_R4300; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R4300; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 32; + current_cpu_data.tlbsize = 32; break; case PRID_IMP_R4600: - mips_cpu.cputype = CPU_R4600; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU; - mips_cpu.tlbsize = 48; + current_cpu_data.cputype = CPU_R4600; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU; + current_cpu_data.tlbsize = 48; break; #if 0 case PRID_IMP_R4650: @@ -509,100 +506,100 @@ __init void cpu_probe(void) * for documentation. Commented out because it shares * it's c0_prid id number with the TX3900. */ - mips_cpu.cputype = CPU_R4650; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU; - mips_cpu.tlbsize = 48; + current_cpu_data.cputype = CPU_R4650; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU; + current_cpu_data.tlbsize = 48; break; #endif case PRID_IMP_TX39: - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB; + current_cpu_data.isa_level = MIPS_CPU_ISA_I; + current_cpu_data.options = MIPS_CPU_TLB; - if ((mips_cpu.processor_id & 0xf0) == + if ((current_cpu_data.processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { - mips_cpu.cputype = CPU_TX3927; - mips_cpu.tlbsize = 64; - mips_cpu.icache.ways = 2; - mips_cpu.dcache.ways = 2; + current_cpu_data.cputype = CPU_TX3927; + current_cpu_data.tlbsize = 64; + current_cpu_data.icache.ways = 2; + current_cpu_data.dcache.ways = 2; } else { - switch (mips_cpu.processor_id & 0xff) { + switch (current_cpu_data.processor_id & 0xff) { case PRID_REV_TX3912: - mips_cpu.cputype = CPU_TX3912; - mips_cpu.tlbsize = 32; + current_cpu_data.cputype = CPU_TX3912; + current_cpu_data.tlbsize = 32; break; case PRID_REV_TX3922: - mips_cpu.cputype = CPU_TX3922; - mips_cpu.tlbsize = 64; + current_cpu_data.cputype = CPU_TX3922; + current_cpu_data.tlbsize = 64; break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; break; } } break; case PRID_IMP_R4700: - mips_cpu.cputype = CPU_R4700; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R4700; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; break; case PRID_IMP_TX49: - mips_cpu.cputype = CPU_TX49XX; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_TX49XX; + current_cpu_data.isa_level = MIPS_CPU_ISA_III; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 48; - mips_cpu.icache.ways = 4; - mips_cpu.dcache.ways = 4; + current_cpu_data.tlbsize = 48; + current_cpu_data.icache.ways = 4; + current_cpu_data.dcache.ways = 4; break; case PRID_IMP_R5000: - mips_cpu.cputype = CPU_R5000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R5000; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; break; case PRID_IMP_R5432: - mips_cpu.cputype = CPU_R5432; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R5432; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH; - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; break; case PRID_IMP_R5500: - mips_cpu.cputype = CPU_R5500; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_R5500; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH; - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; break; case PRID_IMP_NEVADA: - mips_cpu.cputype = CPU_NEVADA; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_NEVADA; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_DIVEC; - mips_cpu.tlbsize = 48; - mips_cpu.icache.ways = 2; - mips_cpu.dcache.ways = 2; + current_cpu_data.tlbsize = 48; + current_cpu_data.icache.ways = 2; + current_cpu_data.dcache.ways = 2; break; case PRID_IMP_R6000: - mips_cpu.cputype = CPU_R6000; - mips_cpu.isa_level = MIPS_CPU_ISA_II; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU; - mips_cpu.tlbsize = 32; + current_cpu_data.cputype = CPU_R6000; + current_cpu_data.isa_level = MIPS_CPU_ISA_II; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_FPU; + current_cpu_data.tlbsize = 32; break; case PRID_IMP_R6000A: - mips_cpu.cputype = CPU_R6000A; - mips_cpu.isa_level = MIPS_CPU_ISA_II; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU; - mips_cpu.tlbsize = 32; + current_cpu_data.cputype = CPU_R6000A; + current_cpu_data.isa_level = MIPS_CPU_ISA_II; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_FPU; + current_cpu_data.tlbsize = 32; break; case PRID_IMP_RM7000: - mips_cpu.cputype = CPU_RM7000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | + current_cpu_data.cputype = CPU_RM7000; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; /* * Undocumented RM7000: Bit 29 in the info register of @@ -612,119 +609,119 @@ __init void cpu_probe(void) * 29 1 => 64 entry JTLB * 0 => 48 entry JTLB */ - mips_cpu.tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; + current_cpu_data.tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; break; case PRID_IMP_R8000: - mips_cpu.cputype = CPU_R8000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + current_cpu_data.cputype = CPU_R8000; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 384; /* has weird TLB: 3-way x 128 */ + current_cpu_data.tlbsize = 384; /* has weird TLB: 3-way x 128 */ break; case PRID_IMP_R10000: - mips_cpu.cputype = CPU_R10000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + current_cpu_data.cputype = CPU_R10000; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH; - mips_cpu.tlbsize = 64; + current_cpu_data.tlbsize = 64; break; case PRID_IMP_R12000: - mips_cpu.cputype = CPU_R12000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + current_cpu_data.cputype = CPU_R12000; + current_cpu_data.isa_level = MIPS_CPU_ISA_IV; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH; - mips_cpu.tlbsize = 64; + current_cpu_data.tlbsize = 64; break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; break; } break; #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) case PRID_COMP_MIPS: - switch (mips_cpu.processor_id & 0xff00) { + switch (current_cpu_data.processor_id & 0xff00) { case PRID_IMP_4KC: - mips_cpu.cputype = CPU_4KC; - mips_cpu.isa_level = MIPS_CPU_ISA_M32; + current_cpu_data.cputype = CPU_4KC; + current_cpu_data.isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_4KEC: - mips_cpu.cputype = CPU_4KEC; - mips_cpu.isa_level = MIPS_CPU_ISA_M32; + current_cpu_data.cputype = CPU_4KEC; + current_cpu_data.isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_4KSC: - mips_cpu.cputype = CPU_4KSC; - mips_cpu.isa_level = MIPS_CPU_ISA_M32; + current_cpu_data.cputype = CPU_4KSC; + current_cpu_data.isa_level = MIPS_CPU_ISA_M32; break; case PRID_IMP_5KC: - mips_cpu.cputype = CPU_5KC; - mips_cpu.isa_level = MIPS_CPU_ISA_M64; + current_cpu_data.cputype = CPU_5KC; + current_cpu_data.isa_level = MIPS_CPU_ISA_M64; break; case PRID_IMP_20KC: - mips_cpu.cputype = CPU_20KC; - mips_cpu.isa_level = MIPS_CPU_ISA_M64; + current_cpu_data.cputype = CPU_20KC; + current_cpu_data.isa_level = MIPS_CPU_ISA_M64; break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; break; } break; case PRID_COMP_ALCHEMY: - switch (mips_cpu.processor_id & 0xff00) { + switch (current_cpu_data.processor_id & 0xff00) { case PRID_IMP_AU1_REV1: case PRID_IMP_AU1_REV2: - switch ((mips_cpu.processor_id >> 24) & 0xff) { + switch ((current_cpu_data.processor_id >> 24) & 0xff) { case 0: - mips_cpu.cputype = CPU_AU1000; + current_cpu_data.cputype = CPU_AU1000; break; case 1: - mips_cpu.cputype = CPU_AU1500; + current_cpu_data.cputype = CPU_AU1500; break; case 2: - mips_cpu.cputype = CPU_AU1100; + current_cpu_data.cputype = CPU_AU1100; break; default: panic("Unknown Au Core!"); break; } - mips_cpu.isa_level = MIPS_CPU_ISA_M32; + current_cpu_data.isa_level = MIPS_CPU_ISA_M32; break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; break; } break; #endif /* CONFIG_CPU_MIPS32 */ case PRID_COMP_SIBYTE: - switch (mips_cpu.processor_id & 0xff00) { + switch (current_cpu_data.processor_id & 0xff00) { case PRID_IMP_SB1: - mips_cpu.cputype = CPU_SB1; - mips_cpu.isa_level = MIPS_CPU_ISA_M64; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + current_cpu_data.cputype = CPU_SB1; + current_cpu_data.isa_level = MIPS_CPU_ISA_M64; + current_cpu_data.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_MCHECK | MIPS_CPU_EJTAG | MIPS_CPU_WATCH; #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS /* FPU in pass1 is known to have issues. */ - mips_cpu.options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; + current_cpu_data.options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; #endif break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; break; } break; default: - mips_cpu.cputype = CPU_UNKNOWN; + current_cpu_data.cputype = CPU_UNKNOWN; } - if (mips_cpu.options & MIPS_CPU_FPU) - mips_cpu.fpu_id = cpu_get_fpu_id(); + if (current_cpu_data.options & MIPS_CPU_FPU) + current_cpu_data.fpu_id = cpu_get_fpu_id(); } __init void cpu_report(void) { - printk("CPU revision is: %08x\n", mips_cpu.processor_id); - if (mips_cpu.options & MIPS_CPU_FPU) - printk("FPU revision is: %08x\n", mips_cpu.fpu_id); + printk("CPU revision is: %08x\n", current_cpu_data.processor_id); + if (current_cpu_data.options & MIPS_CPU_FPU) + printk("FPU revision is: %08x\n", current_cpu_data.fpu_id); } diff --git a/arch/mips64/kernel/proc.c b/arch/mips64/kernel/proc.c index 03e2fe1515b..e748ad77ca2 100644 --- a/arch/mips64/kernel/proc.c +++ b/arch/mips64/kernel/proc.c @@ -79,8 +79,8 @@ static const char *cpu_name[] = { static int show_cpuinfo(struct seq_file *m, void *v) { - unsigned int version = mips_cpu.processor_id; - unsigned int fp_vers = mips_cpu.fpu_id; + unsigned int version = current_cpu_data.processor_id; + unsigned int fp_vers = current_cpu_data.fpu_id; unsigned long n = (unsigned long) v - 1; char fmt [64]; @@ -97,9 +97,9 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", - (mips_cpu.options & MIPS_CPU_FPU) ? " FPU V%d.%d" : ""); - seq_printf(m, fmt, cpu_name[mips_cpu.cputype <= CPU_LAST ? - mips_cpu.cputype : CPU_UNKNOWN], + (current_cpu_data.options & MIPS_CPU_FPU) ? " FPU V%d.%d" : ""); + seq_printf(m, fmt, cpu_name[current_cpu_data.cputype <= CPU_LAST ? + current_cpu_data.cputype : CPU_UNKNOWN], (version >> 4) & 0x0f, version & 0x0f, (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", @@ -107,15 +107,15 @@ static int show_cpuinfo(struct seq_file *m, void *v) (loops_per_jiffy / (5000/HZ)) % 100); seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); seq_printf(m, "microsecond timers\t: %s\n", - (mips_cpu.options & MIPS_CPU_COUNTER) ? "yes" : "no"); - seq_printf(m, "tlb_entries\t\t: %d\n", mips_cpu.tlbsize); + (current_cpu_data.options & MIPS_CPU_COUNTER) ? "yes" : "no"); + seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize); seq_printf(m, "extra interrupt vector\t: %s\n", - (mips_cpu.options & MIPS_CPU_DIVEC) ? "yes" : "no"); + (current_cpu_data.options & MIPS_CPU_DIVEC) ? "yes" : "no"); seq_printf(m, "hardware watchpoint\t: %s\n", watch_available ? "yes" : "no"); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", - (mips_cpu.options & MIPS_CPU_VCE) ? "%d" : "not available"); + (current_cpu_data.options & MIPS_CPU_VCE) ? "%d" : "not available"); seq_printf(m, fmt, 'D', vced_count); seq_printf(m, fmt, 'I', vcei_count); diff --git a/arch/mips64/kernel/ptrace.c b/arch/mips64/kernel/ptrace.c index 92757b7f193..1e3bc263c02 100644 --- a/arch/mips64/kernel/ptrace.c +++ b/arch/mips64/kernel/ptrace.c @@ -135,7 +135,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) tmp = regs->lo; break; case FPC_CSR: - if (mips_cpu.options & MIPS_CPU_FPU) + if (current_cpu_data.options & MIPS_CPU_FPU) tmp = child->thread.fpu.hard.control; else tmp = child->thread.fpu.soft.sr; @@ -196,7 +196,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) regs->lo = data; break; case FPC_CSR: - if (mips_cpu.options & MIPS_CPU_FPU) + if (current_cpu_data.options & MIPS_CPU_FPU) child->thread.fpu.hard.control = data; else child->thread.fpu.soft.sr = data; @@ -349,7 +349,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) tmp = regs->lo; break; case FPC_CSR: - if (mips_cpu.options & MIPS_CPU_FPU) + if (current_cpu_data.options & MIPS_CPU_FPU) tmp = child->thread.fpu.hard.control; else tmp = child->thread.fpu.soft.sr; @@ -410,7 +410,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) regs->lo = data; break; case FPC_CSR: - if (mips_cpu.options & MIPS_CPU_FPU) + if (current_cpu_data.options & MIPS_CPU_FPU) child->thread.fpu.hard.control = data; else child->thread.fpu.soft.sr = data; diff --git a/arch/mips64/kernel/setup.c b/arch/mips64/kernel/setup.c index 2bc85930333..eddca9cba58 100644 --- a/arch/mips64/kernel/setup.c +++ b/arch/mips64/kernel/setup.c @@ -467,7 +467,7 @@ void __init setup_arch(char **cmdline_p) int __init fpu_disable(char *s) { - mips_cpu.options &= ~MIPS_CPU_FPU; + current_cpu_data.options &= ~MIPS_CPU_FPU; return 1; } __setup("nofpu", fpu_disable); diff --git a/arch/mips64/kernel/smp.c b/arch/mips64/kernel/smp.c index ff2e483a7e1..8c34d67d7e8 100644 --- a/arch/mips64/kernel/smp.c +++ b/arch/mips64/kernel/smp.c @@ -77,7 +77,7 @@ unsigned long cache_decay_ticks; void smp_tune_scheduling (void) { - struct cache_desc *cd = &mips_cpu.scache; + struct cache_desc *cd = ¤t_cpu_data.scache; unsigned long cachesize; /* kB */ unsigned long bandwidth = 350; /* MB/s */ unsigned long cpu_khz; @@ -135,6 +135,7 @@ asmlinkage void start_secondary(void) { unsigned int cpu = smp_processor_id(); + cpu_probe(); prom_init_secondary(); per_cpu_trap_init(); diff --git a/arch/mips64/kernel/time.c b/arch/mips64/kernel/time.c index 3c0e783c05b..76fcb624534 100644 --- a/arch/mips64/kernel/time.c +++ b/arch/mips64/kernel/time.c @@ -340,7 +340,7 @@ void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) */ void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - if (mips_cpu.options & MIPS_CPU_COUNTER) { + if (current_cpu_data.options & MIPS_CPU_COUNTER) { unsigned int count; /* @@ -492,15 +492,15 @@ void __init time_init(void) xtime.tv_nsec = 0; /* choose appropriate gettimeoffset routine */ - if (!(mips_cpu.options & MIPS_CPU_COUNTER)) { + if (!(current_cpu_data.options & MIPS_CPU_COUNTER)) { /* no cpu counter - sorry */ do_gettimeoffset = null_gettimeoffset; } else if (mips_counter_frequency != 0) { /* we have cpu counter and know counter frequency! */ do_gettimeoffset = fixed_rate_gettimeoffset; - } else if ((mips_cpu.isa_level == MIPS_CPU_ISA_M32) || - (mips_cpu.isa_level == MIPS_CPU_ISA_I) || - (mips_cpu.isa_level == MIPS_CPU_ISA_II) ) { + } else if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32) || + (current_cpu_data.isa_level == MIPS_CPU_ISA_I) || + (current_cpu_data.isa_level == MIPS_CPU_ISA_II) ) { /* we need to calibrate the counter but we don't have * 64-bit division. */ do_gettimeoffset = calibrate_div32_gettimeoffset; diff --git a/arch/mips64/kernel/traps.c b/arch/mips64/kernel/traps.c index dd466d5596b..5d022ff2bbe 100644 --- a/arch/mips64/kernel/traps.c +++ b/arch/mips64/kernel/traps.c @@ -562,7 +562,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) current->used_math = 1; } - if (!(mips_cpu.options & MIPS_CPU_FPU)) { + if (!(current_cpu_data.options & MIPS_CPU_FPU)) { int sig = fpu_emulator_cop1Handler(0, regs, ¤t->thread.fpu.soft); if (sig) force_sig(sig, current); @@ -616,7 +616,7 @@ asmlinkage void do_reserved(struct pt_regs *regs) static inline void watch_init(void) { - if (mips_cpu.options & MIPS_CPU_WATCH) { + if (current_cpu_data.options & MIPS_CPU_WATCH) { set_except_vector(23, handle_watch); watch_available = 1; } @@ -635,7 +635,7 @@ void *set_except_vector(int n, void *addr) unsigned long old_handler = exception_handlers[n]; exception_handlers[n] = handler; - if (n == 0 && mips_cpu.options & MIPS_CPU_DIVEC) { + if (n == 0 && current_cpu_data.options & MIPS_CPU_DIVEC) { *(volatile u32 *)(KSEG0+0x200) = 0x08000000 | (0x03ffffff & (handler >> 2)); flush_icache_range(KSEG0+0x200, KSEG0 + 0x204); @@ -664,7 +664,7 @@ void __init per_cpu_trap_init(void) * Some MIPS CPUs have a dedicated interrupt vector which reduces the * interrupt processing overhead. Use it where available. */ - if (mips_cpu.options & MIPS_CPU_DIVEC) + if (current_cpu_data.options & MIPS_CPU_DIVEC) set_c0_cause(CAUSEF_IV); cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; @@ -701,7 +701,7 @@ void __init trap_init(void) * Some MIPS CPUs have a dedicated interrupt vector which reduces the * interrupt processing overhead. Use it where available. */ - if (mips_cpu.options & MIPS_CPU_DIVEC) + if (current_cpu_data.options & MIPS_CPU_DIVEC) memcpy((void *)(KSEG0 + 0x200), &except_vec4, 0x80); /* @@ -728,24 +728,25 @@ void __init trap_init(void) set_except_vector(13, handle_tr); set_except_vector(22, handle_mdmx); - if ((mips_cpu.options & MIPS_CPU_FPU) && - !(mips_cpu.options & MIPS_CPU_NOFPUEX)) + if ((current_cpu_data.options & MIPS_CPU_FPU) && + !(current_cpu_data.options & MIPS_CPU_NOFPUEX)) set_except_vector(15, handle_fpe); - if (mips_cpu.options & MIPS_CPU_MCHECK) + if (current_cpu_data.options & MIPS_CPU_MCHECK) set_except_vector(24, handle_mcheck); - if (mips_cpu.options & MIPS_CPU_VCE) { + if (current_cpu_data.options & MIPS_CPU_VCE) { /* VCE and DIVEC are mutually exclusive. */ - if (mips_cpu.options & MIPS_CPU_DIVEC) + if (current_cpu_data.options & MIPS_CPU_DIVEC) BUG(); memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x100); - } else if (mips_cpu.options & MIPS_CPU_4KEX) + } else if (current_cpu_data.options & MIPS_CPU_4KEX) memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); else memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80); - if (mips_cpu.cputype == CPU_R6000 || mips_cpu.cputype == CPU_R6000A) { + if (current_cpu_data.cputype == CPU_R6000 || + current_cpu_data.cputype == CPU_R6000A) { /* * The R6000 is the only R-series CPU that features a machine * check exception (similar to the R4000 cache error) and @@ -758,7 +759,7 @@ void __init trap_init(void) //set_except_vector(15, handle_ndc); } - if (mips_cpu.options & MIPS_CPU_FPU) { + if (current_cpu_data.options & MIPS_CPU_FPU) { save_fp_context = _save_fp_context; restore_fp_context = _restore_fp_context; } else { @@ -768,7 +769,7 @@ void __init trap_init(void) flush_icache_range(KSEG0, KSEG0 + 0x400); - if (mips_cpu.isa_level == MIPS_CPU_ISA_IV) + if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) set_c0_status(ST0_XX); atomic_inc(&init_mm.mm_count); /* XXX UP? */ diff --git a/arch/mips64/lib/dump_tlb.c b/arch/mips64/lib/dump_tlb.c index 4815a95af3d..6dcaf0d3dc3 100644 --- a/arch/mips64/lib/dump_tlb.c +++ b/arch/mips64/lib/dump_tlb.c @@ -87,7 +87,7 @@ void dump_tlb(int first, int last) void dump_tlb_all(void) { - dump_tlb(0, mips_cpu.tlbsize - 1); + dump_tlb(0, current_cpu_data.tlbsize - 1); } void dump_tlb_wired(void) @@ -132,7 +132,7 @@ void dump_tlb_addr(unsigned long addr) void dump_tlb_nonwired(void) { - dump_tlb(read_c0_wired(), mips_cpu.tlbsize - 1); + dump_tlb(read_c0_wired(), current_cpu_data.tlbsize - 1); } void dump_list_process(struct task_struct *t, void *address) diff --git a/arch/mips64/mm/c-mips64.c b/arch/mips64/mm/c-mips64.c index 5b87d8156ea..1bd3cc18b29 100644 --- a/arch/mips64/mm/c-mips64.c +++ b/arch/mips64/mm/c-mips64.c @@ -433,7 +433,7 @@ static void mips64_flush_cache_sigtramp(unsigned long addr) static void mips64_flush_icache_all(void) { - if (mips_cpu.icache.flags | MIPS_CACHE_VTAG_CACHE) { + if (current_cpu_data.icache.flags | MIPS_CACHE_VTAG_CACHE) { blast_icache(); } } @@ -444,7 +444,7 @@ static void __init probe_icache(unsigned long config) unsigned long config1; unsigned int lsize; - mips_cpu.icache.flags = 0; + current_cpu_data.icache.flags = 0; if (!(config & (1 << 31))) { /* * Not a MIPS64 complainant CPU. @@ -452,41 +452,41 @@ static void __init probe_icache(unsigned long config) */ icache_size = 1 << (12 + ((config >> 9) & 7)); ic_lsize = 16 << ((config >> 5) & 1); - mips_cpu.icache.linesz = ic_lsize; + current_cpu_data.icache.linesz = ic_lsize; /* * We cannot infer associativity - assume direct map * unless probe template indicates otherwise */ - if(!mips_cpu.icache.ways) mips_cpu.icache.ways = 1; - mips_cpu.icache.sets = - (icache_size / ic_lsize) / mips_cpu.icache.ways; + if (!current_cpu_data.icache.ways) current_cpu_data.icache.ways = 1; + current_cpu_data.icache.sets = + (icache_size / ic_lsize) / current_cpu_data.icache.ways; } else { config1 = read_c0_config1(); if ((lsize = ((config1 >> 19) & 7))) - mips_cpu.icache.linesz = 2 << lsize; + current_cpu_data.icache.linesz = 2 << lsize; else - mips_cpu.icache.linesz = lsize; - mips_cpu.icache.sets = 64 << ((config1 >> 22) & 7); - mips_cpu.icache.ways = 1 + ((config1 >> 16) & 7); + current_cpu_data.icache.linesz = lsize; + current_cpu_data.icache.sets = 64 << ((config1 >> 22) & 7); + current_cpu_data.icache.ways = 1 + ((config1 >> 16) & 7); - ic_lsize = mips_cpu.icache.linesz; - icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways * + ic_lsize = current_cpu_data.icache.linesz; + icache_size = current_cpu_data.icache.sets * current_cpu_data.icache.ways * ic_lsize; - if ((config & 0x8) || (mips_cpu.cputype == CPU_20KC)) { + if ((config & 0x8) || (current_cpu_data.cputype == CPU_20KC)) { /* * The CPU has a virtually tagged I-cache. * Some older 20Kc chips doesn't have the 'VI' bit in * the config register, so we also check for 20Kc. */ - mips_cpu.icache.flags = MIPS_CACHE_VTAG_CACHE; + current_cpu_data.icache.flags = MIPS_CACHE_VTAG_CACHE; printk("Virtually tagged I-cache detected\n"); } } printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n", - icache_size >> 10, ic_lsize, mips_cpu.icache.ways); + icache_size >> 10, ic_lsize, current_cpu_data.icache.ways); } static void __init probe_dcache(unsigned long config) @@ -494,7 +494,7 @@ static void __init probe_dcache(unsigned long config) unsigned long config1; unsigned int lsize; - mips_cpu.dcache.flags = 0; + current_cpu_data.dcache.flags = 0; if (!(config & (1 << 31))) { /* * Not a MIPS64 complainant CPU. @@ -502,31 +502,31 @@ static void __init probe_dcache(unsigned long config) */ dcache_size = 1 << (12 + ((config >> 6) & 7)); dc_lsize = 16 << ((config >> 4) & 1); - mips_cpu.dcache.linesz = dc_lsize; + current_cpu_data.dcache.linesz = dc_lsize; /* * We cannot infer associativity - assume direct map * unless probe template indicates otherwise */ - if(!mips_cpu.dcache.ways) mips_cpu.dcache.ways = 1; - mips_cpu.dcache.sets = - (dcache_size / dc_lsize) / mips_cpu.dcache.ways; + if (!current_cpu_data.dcache.ways) current_cpu_data.dcache.ways = 1; + current_cpu_data.dcache.sets = + (dcache_size / dc_lsize) / current_cpu_data.dcache.ways; } else { config1 = read_c0_config1(); if ((lsize = ((config1 >> 10) & 7))) - mips_cpu.dcache.linesz = 2 << lsize; + current_cpu_data.dcache.linesz = 2 << lsize; else - mips_cpu.dcache.linesz= lsize; - mips_cpu.dcache.sets = 64 << ((config1 >> 13) & 7); - mips_cpu.dcache.ways = 1 + ((config1 >> 7) & 7); + current_cpu_data.dcache.linesz= lsize; + current_cpu_data.dcache.sets = 64 << ((config1 >> 13) & 7); + current_cpu_data.dcache.ways = 1 + ((config1 >> 7) & 7); - dc_lsize = mips_cpu.dcache.linesz; + dc_lsize = current_cpu_data.dcache.linesz; dcache_size = - mips_cpu.dcache.sets * mips_cpu.dcache.ways + current_cpu_data.dcache.sets * current_cpu_data.dcache.ways * dc_lsize; } printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n", - dcache_size >> 10, dc_lsize, mips_cpu.dcache.ways); + dcache_size >> 10, dc_lsize, current_cpu_data.dcache.ways); } @@ -541,7 +541,7 @@ static int __init probe_scache(unsigned long config) unsigned long flags, addr, begin, end, pow2; int tmp; - if (mips_cpu.scache.flags == MIPS_CACHE_NOT_PRESENT) + if (current_cpu_data.scache.flags == MIPS_CACHE_NOT_PRESENT) return 0; tmp = ((config >> 17) & 1); @@ -660,14 +660,14 @@ static inline void __init setup_scache(unsigned int config) sc_present = probe_scache_kseg1(config); if (sc_present) { - mips_cpu.scache.linesz = sc_lsize; + current_cpu_data.scache.linesz = sc_lsize; /* * We cannot infer associativity - assume direct map * unless probe template indicates otherwise */ - if(!mips_cpu.scache.ways) mips_cpu.scache.ways = 1; - mips_cpu.scache.sets = - (scache_size / sc_lsize) / mips_cpu.scache.ways; + if(!current_cpu_data.scache.ways) current_cpu_data.scache.ways = 1; + current_cpu_data.scache.sets = + (scache_size / sc_lsize) / current_cpu_data.scache.ways; setup_scache_funcs(); return; diff --git a/arch/mips64/mm/c-r4k.c b/arch/mips64/mm/c-r4k.c index b4ce668ccbd..7220331f0f0 100644 --- a/arch/mips64/mm/c-r4k.c +++ b/arch/mips64/mm/c-r4k.c @@ -562,7 +562,7 @@ static void r4600v20k_flush_cache_sigtramp(unsigned long addr) static void __init probe_icache(unsigned long config) { - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR41XX: case CPU_VR4111: case CPU_VR4121: @@ -595,7 +595,7 @@ static void __init probe_icache(unsigned long config) static void __init probe_dcache(unsigned long config) { - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_VR41XX: case CPU_VR4111: case CPU_VR4121: @@ -766,7 +766,7 @@ static inline void __init setup_scache(unsigned int config) return; } - switch(mips_cpu.cputype) { + switch(current_cpu_data.cputype) { case CPU_R5000: case CPU_NEVADA: setup_noscache_funcs(); @@ -796,7 +796,7 @@ void __init ld_mmu_r4xx0(void) probe_dcache(config); setup_scache(config); - switch(mips_cpu.cputype) { + switch(current_cpu_data.cputype) { case CPU_R4600: /* QED style two way caches? */ case CPU_R4700: case CPU_R5000: diff --git a/arch/mips64/mm/init.c b/arch/mips64/mm/init.c index 585a12927ef..37f78d5d0a0 100644 --- a/arch/mips64/mm/init.c +++ b/arch/mips64/mm/init.c @@ -92,7 +92,7 @@ unsigned long setup_zero_pages(void) unsigned long order, size; struct page *page; - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_R4000SC: case CPU_R4000MC: case CPU_R4400SC: diff --git a/arch/mips64/mm/loadmmu.c b/arch/mips64/mm/loadmmu.c index 2146b46f321..8f192a6a77c 100644 --- a/arch/mips64/mm/loadmmu.c +++ b/arch/mips64/mm/loadmmu.c @@ -63,7 +63,7 @@ extern void r4k_tlb_init(void); void __init load_mmu(void) { - if (mips_cpu.options & MIPS_CPU_4KTLB) { + if (current_cpu_data.options & MIPS_CPU_4KTLB) { #if defined (CONFIG_CPU_R4300) \ || defined (CONFIG_CPU_R4X00) \ || defined (CONFIG_CPU_R5000) \ @@ -87,7 +87,7 @@ void __init load_mmu(void) r4k_tlb_init(); #endif - } else switch(mips_cpu.cputype) { + } else switch(current_cpu_data.cputype) { #ifdef CONFIG_CPU_R10000 case CPU_R10000: case CPU_R12000: diff --git a/arch/mips64/mm/pg-mips64.c b/arch/mips64/mm/pg-mips64.c index 69328062f36..2dc7d5adf53 100644 --- a/arch/mips64/mm/pg-mips64.c +++ b/arch/mips64/mm/pg-mips64.c @@ -37,7 +37,7 @@ void mips64_clear_page_dc(unsigned long page) { unsigned long i; - if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) + if (current_cpu_data.options & MIPS_CPU_CACHE_CDEX) { for (i=page; i> PAGE_SHIFT; size = (size + 1) >> 1; - if(size <= mips_cpu.tlbsize/2) { + if(size <= current_cpu_data.tlbsize/2) { int oldpid = read_c0_entryhi() & ASID_MASK; int newpid = cpu_asid(cpu, mm); @@ -149,7 +149,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) local_irq_save(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; - if (size <= mips_cpu.tlbsize/2) { + if (size <= current_cpu_data.tlbsize/2) { int pid = read_c0_entryhi(); start &= (PAGE_MASK << 1); @@ -357,16 +357,16 @@ static void __init probe_tlb(unsigned long config) * Not a MIPS64 complainant CPU. * Config 1 register not supported, we assume R4k style. */ - mips_cpu.tlbsize = 48; + current_cpu_data.tlbsize = 48; } else { config1 = read_c0_config1(); if (!((config >> 7) & 3)) panic("No MMU present"); else - mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1; + current_cpu_data.tlbsize = ((config1 >> 25) & 0x3f) + 1; } - printk("Number of TLB entries %d.\n", mips_cpu.tlbsize); + printk("Number of TLB entries %d.\n", current_cpu_data.tlbsize); } void __init r4k_tlb_init(void) @@ -376,7 +376,7 @@ void __init r4k_tlb_init(void) probe_tlb(config); write_c0_pagemask(PM_4K); write_c0_wired(0); - temp_tlb_entry = mips_cpu.tlbsize - 1; + temp_tlb_entry = current_cpu_data.tlbsize - 1; local_flush_tlb_all(); memcpy((void *)(KSEG0 + 0x80), except_vec1_r4k, 0x80); diff --git a/arch/mips64/mm/tlb-sb1.c b/arch/mips64/mm/tlb-sb1.c index 5c9272a0f40..1c9d49acfca 100644 --- a/arch/mips64/mm/tlb-sb1.c +++ b/arch/mips64/mm/tlb-sb1.c @@ -77,7 +77,7 @@ void sb1_dump_tlb(void) printk("\n\nFull TLB Dump:\n" "Idx EntryHi EntryLo0 EntryLo1 PageMask\n" "--------------------------------------------------------------\n"); - for (entry = 0; entry < mips_cpu.tlbsize; entry++) { + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { write_c0_index(entry); printk("\n%02i ", entry); __asm__ __volatile__ ( @@ -104,7 +104,7 @@ void local_flush_tlb_all(void) old_ctx = read_c0_entryhi() & ASID_MASK; write_c0_entrylo0(0); write_c0_entrylo1(0); - for (entry = 0; entry < mips_cpu.tlbsize; entry++) { + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { write_c0_entryhi(KSEG0 + (PAGE_SIZE << 1) * entry); write_c0_index(entry); tlb_write_indexed(); @@ -130,7 +130,7 @@ void sb1_sanitize_tlb(void) /* Save old context and create impossible VPN2 value */ write_c0_entrylo0(0); write_c0_entrylo1(0); - for (entry = 0; entry < mips_cpu.tlbsize; entry++) { + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { do { addr += inc; write_c0_entryhi(addr); @@ -157,7 +157,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, int size; size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; - if (size <= (mips_cpu.tlbsize/2)) { + if (size <= (current_cpu_data.tlbsize/2)) { int oldpid = read_c0_entryhi() & ASID_MASK; int newpid = cpu_asid(cpu, mm); @@ -195,7 +195,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) size = (size + 1) >> 1; local_irq_save(flags); - if (size <= (mips_cpu.tlbsize/2)) { + if (size <= (current_cpu_data.tlbsize/2)) { int pid = read_c0_entryhi(); start &= (PAGE_MASK << 1); @@ -308,7 +308,7 @@ void sb1_tlb_init(void) write_c0_pagemask(PM_4K); config1 = read_c0_config1(); - mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1; + current_cpu_data.tlbsize = ((config1 >> 25) & 0x3f) + 1; /* * We don't know what state the firmware left the TLB's in, so this is diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h index 2fc53620cc0..4057cb45f74 100644 --- a/include/asm-mips/cache.h +++ b/include/asm-mips/cache.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1997, 98, 99, 2000 Ralf Baechle + * Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. */ #ifndef _ASM_CACHE_H @@ -11,25 +11,8 @@ #include -#ifndef __ASSEMBLY__ -/* - * Descriptor for a cache - */ -struct cache_desc { - int linesz; - int sets; - int ways; - int flags; /* Details like write thru/back, coherent, etc. */ -}; -#endif /* !__ASSEMBLY__ */ - -/* - * Flag definitions - */ -#define MIPS_CACHE_NOT_PRESENT 0x00000001 -#define MIPS_CACHE_VTAG_CACHE 0x00000002 /* Virtually tagged cache. */ - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R6000) || defined(CONFIG_CPU_TX39XX) +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R6000) || \ + defined(CONFIG_CPU_TX39XX) #define L1_CACHE_BYTES 16 #define L1_CACHE_SHIFT_MAX 4 /* largest L1 which this arch supports */ #else diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index b913f56d54c..e94217d2192 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -110,24 +110,6 @@ extern void cpu_probe(void); extern void cpu_report(void); -/* - * Capability and feature descriptor structure for MIPS CPU - */ -struct mips_cpu { - unsigned int processor_id; - unsigned int fpu_id; - unsigned int cputype; - int isa_level; - int options; - int tlbsize; - struct cache_desc icache; /* Primary I-cache */ - struct cache_desc dcache; /* Primary D or combined I/D cache */ - struct cache_desc scache; /* Secondary cache */ - struct cache_desc tcache; /* Tertiary/split secondary cache */ -}; - -extern struct mips_cpu mips_cpu; - enum cputype { CPU_UNKNOWN, CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 83767c888e8..97ef5f4e642 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -61,13 +61,13 @@ do { \ #define enable_fpu() \ do { \ - if (mips_cpu.options & MIPS_CPU_FPU) \ + if (current_cpu_data.options & MIPS_CPU_FPU) \ __enable_fpu(); \ } while (0) #define disable_fpu() \ do { \ - if (mips_cpu.options & MIPS_CPU_FPU) \ + if (current_cpu_data.options & MIPS_CPU_FPU) \ __disable_fpu(); \ } while (0) @@ -76,13 +76,13 @@ do { \ static inline int is_fpu_owner(void) { - return (mips_cpu.options & MIPS_CPU_FPU) && + return (current_cpu_data.options & MIPS_CPU_FPU) && test_thread_flag(TIF_USEDFPU); } static inline void own_fpu(void) { - if (mips_cpu.options & MIPS_CPU_FPU) { + if (current_cpu_data.options & MIPS_CPU_FPU) { __enable_fpu(); KSTK_STATUS(current) |= ST0_CU1; set_thread_flag(TIF_USEDFPU); @@ -91,7 +91,7 @@ static inline void own_fpu(void) static inline void loose_fpu(void) { - if (mips_cpu.options & MIPS_CPU_FPU) { + if (current_cpu_data.options & MIPS_CPU_FPU) { KSTK_STATUS(current) &= ~ST0_CU1; clear_thread_flag(TIF_USEDFPU); __disable_fpu(); @@ -100,7 +100,7 @@ static inline void loose_fpu(void) static inline void init_fpu(void) { - if (mips_cpu.options & MIPS_CPU_FPU) { + if (current_cpu_data.options & MIPS_CPU_FPU) { _init_fpu(); } else { fpu_emulator_init_fpu(); @@ -109,19 +109,19 @@ static inline void init_fpu(void) static inline void save_fp(struct task_struct *tsk) { - if (mips_cpu.options & MIPS_CPU_FPU) + if (current_cpu_data.options & MIPS_CPU_FPU) _save_fp(tsk); } static inline void restore_fp(struct task_struct *tsk) { - if (mips_cpu.options & MIPS_CPU_FPU) + if (current_cpu_data.options & MIPS_CPU_FPU) _restore_fp(tsk); } static inline unsigned long long *get_fpu_regs(struct task_struct *tsk) { - if (mips_cpu.options & MIPS_CPU_FPU) { + if (current_cpu_data.options & MIPS_CPU_FPU) { if ((tsk == current) && is_fpu_owner()) _save_fp(current); return (unsigned long long *)&tsk->thread.fpu.hard.fp_regs[0]; diff --git a/include/asm-mips/mips32_cache.h b/include/asm-mips/mips32_cache.h index caaa25e425c..44bb50d9673 100644 --- a/include/asm-mips/mips32_cache.h +++ b/include/asm-mips/mips32_cache.h @@ -1,11 +1,7 @@ /* - * mips32_cache.h - * * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -19,8 +15,6 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - * * Inline assembly cache operations. * * This file is the original r4cache.c file with modification that makes the @@ -29,18 +23,18 @@ * FIXME: Handle split L2 caches. * */ -#ifndef _MIPS_R4KCACHE_H -#define _MIPS_R4KCACHE_H +#ifndef _ASM_R4KCACHE_H +#define _ASM_R4KCACHE_H #include #include static inline void flush_icache_line_indexed(unsigned long addr) { - unsigned long waystep = icache_size/mips_cpu.icache.ways; + unsigned long waystep = icache_size / current_cpu_data.icache.ways; unsigned int way; - for (way = 0; way < mips_cpu.icache.ways; way++) + for (way = 0; way < current_cpu_data.icache.ways; way++) { __asm__ __volatile__( ".set noreorder\n\t" @@ -58,10 +52,10 @@ static inline void flush_icache_line_indexed(unsigned long addr) static inline void flush_dcache_line_indexed(unsigned long addr) { - unsigned long waystep = dcache_size/mips_cpu.dcache.ways; + unsigned long waystep = dcache_size / current_cpu_data.dcache.ways; unsigned int way; - for (way = 0; way < mips_cpu.dcache.ways; way++) + for (way = 0; way < current_cpu_data.dcache.ways; way++) { __asm__ __volatile__( ".set noreorder\n\t" @@ -79,10 +73,10 @@ static inline void flush_dcache_line_indexed(unsigned long addr) static inline void flush_scache_line_indexed(unsigned long addr) { - unsigned long waystep = scache_size/mips_cpu.scache.ways; + unsigned long waystep = scache_size / current_cpu_data.scache.ways; unsigned int way; - for (way = 0; way < mips_cpu.scache.ways; way++) + for (way = 0; way < current_cpu_data.scache.ways; way++) { __asm__ __volatile__( ".set noreorder\n\t" @@ -214,7 +208,7 @@ static inline void protected_writeback_dcache_line(unsigned long addr) static inline void blast_dcache(void) { unsigned long start = KSEG0; - unsigned long end = (start + dcache_size); + unsigned long end = start + dcache_size; while(start < end) { cache_unroll(start,Index_Writeback_Inv_D); @@ -225,7 +219,7 @@ static inline void blast_dcache(void) static inline void blast_dcache_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while(start < end) { cache_unroll(start,Hit_Writeback_Inv_D); @@ -236,11 +230,11 @@ static inline void blast_dcache_page(unsigned long page) static inline void blast_dcache_page_indexed(unsigned long page) { unsigned long start; - unsigned long end = (page + PAGE_SIZE); - unsigned long waystep = dcache_size/mips_cpu.dcache.ways; + unsigned long end = page + PAGE_SIZE; + unsigned long waystep = dcache_size / current_cpu_data.dcache.ways; unsigned int way; - for (way = 0; way < mips_cpu.dcache.ways; way++) { + for (way = 0; way < current_cpu_data.dcache.ways; way++) { start = page + way*waystep; while(start < end) { cache_unroll(start,Index_Writeback_Inv_D); @@ -252,7 +246,7 @@ static inline void blast_dcache_page_indexed(unsigned long page) static inline void blast_icache(void) { unsigned long start = KSEG0; - unsigned long end = (start + icache_size); + unsigned long end = start + icache_size; while(start < end) { cache_unroll(start,Index_Invalidate_I); @@ -263,7 +257,7 @@ static inline void blast_icache(void) static inline void blast_icache_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while(start < end) { cache_unroll(start,Hit_Invalidate_I); @@ -274,11 +268,11 @@ static inline void blast_icache_page(unsigned long page) static inline void blast_icache_page_indexed(unsigned long page) { unsigned long start; - unsigned long end = (page + PAGE_SIZE); - unsigned long waystep = icache_size/mips_cpu.icache.ways; + unsigned long end = page + PAGE_SIZE; + unsigned long waystep = icache_size / current_cpu_data.icache.ways; unsigned int way; - for (way = 0; way < mips_cpu.icache.ways; way++) { + for (way = 0; way < current_cpu_data.icache.ways; way++) { start = page + way*waystep; while(start < end) { cache_unroll(start,Index_Invalidate_I); @@ -312,11 +306,11 @@ static inline void blast_scache_page(unsigned long page) static inline void blast_scache_page_indexed(unsigned long page) { unsigned long start; - unsigned long end = (page + PAGE_SIZE); - unsigned long waystep = scache_size/mips_cpu.scache.ways; + unsigned long end = page + PAGE_SIZE; + unsigned long waystep = scache_size/current_cpu_data.scache.ways; unsigned int way; - for (way = 0; way < mips_cpu.scache.ways; way++) { + for (way = 0; way < current_cpu_data.scache.ways; way++) { start = page + way*waystep; while(start < end) { cache_unroll(start,Index_Writeback_Inv_SD); @@ -325,4 +319,4 @@ static inline void blast_scache_page_indexed(unsigned long page) } } -#endif /* !(_MIPS_R4KCACHE_H) */ +#endif /* _ASM_R4KCACHE_H */ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 0b5521cda63..8ef9b07c5aa 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -4,7 +4,7 @@ * for more details. * * Copyright (C) 1994 Waldorf GMBH - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002 Ralf Baechle + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle * Copyright (C) 1996 Paul M. Antoine * Copyright (C) 1999 Silicon Graphics, Inc. */ @@ -30,9 +30,39 @@ #include #include +/* + * Descriptor for a cache + */ +struct cache_desc { + int linesz; + int sets; + int ways; + int flags; /* Details like write thru/back, coherent, etc. */ +}; + +/* + * Flag definitions + */ +#define MIPS_CACHE_NOT_PRESENT 0x00000001 +#define MIPS_CACHE_VTAG_CACHE 0x00000002 /* Virtually tagged cache. */ + struct cpuinfo_mips { unsigned long udelay_val; unsigned long asid_cache; + + /* + * Capability and feature descriptor structure for MIPS CPU + */ + unsigned int processor_id; + unsigned int fpu_id; + unsigned int cputype; + int isa_level; + int options; + int tlbsize; + struct cache_desc icache; /* Primary I-cache */ + struct cache_desc dcache; /* Primary D or combined I/D cache */ + struct cache_desc scache; /* Secondary cache */ + struct cache_desc tcache; /* Tertiary/split secondary cache */ } __attribute__((__aligned__(SMP_CACHE_BYTES))); /* @@ -62,12 +92,6 @@ extern int EISA_bus; #define MCA_bus__is_a_macro /* for versions in ksyms.c */ /* - * MIPS has no problems with write protection - */ -#define wp_works_ok 1 -#define wp_works_ok__is_a_macro /* for versions in ksyms.c */ - -/* * User space process size: 2GB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. TASK_SIZE * for a 64 bit kernel expandable to 8192EB, of which the current MIPS diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 6c214fffeba..07e3a63fd24 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -126,7 +126,7 @@ static inline void protected_writeback_dcache_line(unsigned long addr) static inline void blast_dcache16(void) { unsigned long start = KSEG0; - unsigned long end = (start + dcache_size); + unsigned long end = start + dcache_size; while (start < end) { cache16_unroll32(start,Index_Writeback_Inv_D); @@ -137,8 +137,9 @@ static inline void blast_dcache16(void) static inline void blast_dcache16_wayLSB(void) { unsigned long start = KSEG0; - unsigned long end = (start + mips_cpu.dcache.sets * mips_cpu.dcache.linesz); - int way, ways = mips_cpu.dcache.ways; + unsigned long end = start + current_cpu_data.dcache.sets * + current_cpu_data.dcache.linesz; + int way, ways = current_cpu_data.dcache.ways; while (start < end) { /* LSB of VA select the way */ @@ -151,7 +152,7 @@ static inline void blast_dcache16_wayLSB(void) static inline void blast_dcache16_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache16_unroll32(start,Hit_Writeback_Inv_D); @@ -162,7 +163,7 @@ static inline void blast_dcache16_page(unsigned long page) static inline void blast_dcache16_page_indexed(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache16_unroll32(start,Index_Writeback_Inv_D); @@ -173,8 +174,8 @@ static inline void blast_dcache16_page_indexed(unsigned long page) static inline void blast_dcache16_page_indexed_wayLSB(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - int way, ways = mips_cpu.dcache.ways; + unsigned long end = start + PAGE_SIZE; + int way, ways = current_cpu_data.dcache.ways; while (start < end) { /* LSB of VA select the way */ @@ -187,7 +188,7 @@ static inline void blast_dcache16_page_indexed_wayLSB(unsigned long page) static inline void blast_icache16(void) { unsigned long start = KSEG0; - unsigned long end = (start + icache_size); + unsigned long end = start + icache_size; while (start < end) { cache16_unroll32(start,Index_Invalidate_I); @@ -198,8 +199,9 @@ static inline void blast_icache16(void) static inline void blast_icache16_wayLSB(void) { unsigned long start = KSEG0; - unsigned long end = (start + mips_cpu.icache.sets * mips_cpu.icache.linesz); - int way, ways = mips_cpu.icache.ways; + unsigned long end = start + current_cpu_data.icache.sets * + current_cpu_data.icache.linesz; + int way, ways = current_cpu_data.icache.ways; while (start < end) { /* LSB of VA select the way */ @@ -212,7 +214,7 @@ static inline void blast_icache16_wayLSB(void) static inline void blast_icache16_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache16_unroll32(start,Hit_Invalidate_I); @@ -223,7 +225,7 @@ static inline void blast_icache16_page(unsigned long page) static inline void blast_icache16_page_indexed(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache16_unroll32(start,Index_Invalidate_I); @@ -234,8 +236,8 @@ static inline void blast_icache16_page_indexed(unsigned long page) static inline void blast_icache16_page_indexed_wayLSB(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - int way, ways = mips_cpu.icache.ways; + unsigned long end = start + PAGE_SIZE; + int way, ways = current_cpu_data.icache.ways; while (start < end) { /* LSB of VA select the way */ @@ -307,7 +309,7 @@ static inline void blast_scache16_page_indexed(unsigned long page) static inline void blast_dcache32(void) { unsigned long start = KSEG0; - unsigned long end = (start + dcache_size); + unsigned long end = start + dcache_size; while (start < end) { cache32_unroll32(start,Index_Writeback_Inv_D); @@ -318,8 +320,9 @@ static inline void blast_dcache32(void) static inline void blast_dcache32_wayLSB(void) { unsigned long start = KSEG0; - unsigned long end = (start + mips_cpu.dcache.sets * mips_cpu.dcache.linesz); - int way, ways = mips_cpu.dcache.ways; + unsigned long end = start + current_cpu_data.dcache.sets * + current_cpu_data.dcache.linesz; + int way, ways = current_cpu_data.dcache.ways; while (start < end) { /* LSB of VA select the way */ @@ -344,7 +347,7 @@ static inline void blast_dcache32_wayLSB(void) static inline void blast_dcache32_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; /* * Sigh ... workaround for R4600 v1.7 bug. Explanation see above. @@ -361,7 +364,7 @@ static inline void blast_dcache32_page(unsigned long page) static inline void blast_dcache32_page_indexed(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache32_unroll32(start,Index_Writeback_Inv_D); @@ -372,8 +375,8 @@ static inline void blast_dcache32_page_indexed(unsigned long page) static inline void blast_dcache32_page_indexed_wayLSB(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - int way, ways = mips_cpu.dcache.ways; + unsigned long end = start + PAGE_SIZE; + int way, ways = current_cpu_data.dcache.ways; while (start < end) { /* LSB of VA select the way */ @@ -386,7 +389,7 @@ static inline void blast_dcache32_page_indexed_wayLSB(unsigned long page) static inline void blast_icache32(void) { unsigned long start = KSEG0; - unsigned long end = (start + icache_size); + unsigned long end = start + icache_size; while (start < end) { cache32_unroll32(start,Index_Invalidate_I); @@ -397,8 +400,9 @@ static inline void blast_icache32(void) static inline void blast_icache32_wayLSB(void) { unsigned long start = KSEG0; - unsigned long end = (start + mips_cpu.icache.sets * mips_cpu.icache.linesz); - int way, ways = mips_cpu.icache.ways; + unsigned long end = start + current_cpu_data.icache.sets * + current_cpu_data.icache.linesz; + int way, ways = current_cpu_data.icache.ways; while (start < end) { /* LSB of VA select the way */ @@ -411,7 +415,7 @@ static inline void blast_icache32_wayLSB(void) static inline void blast_icache32_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache32_unroll32(start,Hit_Invalidate_I); @@ -422,7 +426,7 @@ static inline void blast_icache32_page(unsigned long page) static inline void blast_icache32_page_indexed(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache32_unroll32(start,Index_Invalidate_I); @@ -433,8 +437,8 @@ static inline void blast_icache32_page_indexed(unsigned long page) static inline void blast_icache32_page_indexed_wayLSB(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - int way, ways = mips_cpu.icache.ways; + unsigned long end = start + PAGE_SIZE; + int way, ways = current_cpu_data.icache.ways; while (start < end) { /* LSB of VA select the way */ diff --git a/include/asm-mips64/bootinfo.h b/include/asm-mips64/bootinfo.h index 70418ebdc42..579911cbf99 100644 --- a/include/asm-mips64/bootinfo.h +++ b/include/asm-mips64/bootinfo.h @@ -83,7 +83,7 @@ /* * Valid machtype for group SGI */ -#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ +#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ #define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ #define MACH_SGI_IP28 2 /* Indigo2 Impact */ #define MACH_SGI_IP32 3 /* O2 */ diff --git a/include/asm-mips/cache.h b/include/asm-mips64/cache.h similarity index 55% copy from include/asm-mips/cache.h copy to include/asm-mips64/cache.h index 2fc53620cc0..4057cb45f74 100644 --- a/include/asm-mips/cache.h +++ b/include/asm-mips64/cache.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1997, 98, 99, 2000 Ralf Baechle + * Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. */ #ifndef _ASM_CACHE_H @@ -11,25 +11,8 @@ #include -#ifndef __ASSEMBLY__ -/* - * Descriptor for a cache - */ -struct cache_desc { - int linesz; - int sets; - int ways; - int flags; /* Details like write thru/back, coherent, etc. */ -}; -#endif /* !__ASSEMBLY__ */ - -/* - * Flag definitions - */ -#define MIPS_CACHE_NOT_PRESENT 0x00000001 -#define MIPS_CACHE_VTAG_CACHE 0x00000002 /* Virtually tagged cache. */ - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R6000) || defined(CONFIG_CPU_TX39XX) +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R6000) || \ + defined(CONFIG_CPU_TX39XX) #define L1_CACHE_BYTES 16 #define L1_CACHE_SHIFT_MAX 4 /* largest L1 which this arch supports */ #else diff --git a/include/asm-mips64/cpu.h b/include/asm-mips64/cpu.h index 7d728f57980..83cad8589b3 100644 --- a/include/asm-mips64/cpu.h +++ b/include/asm-mips64/cpu.h @@ -110,24 +110,6 @@ extern void cpu_probe(void); extern void cpu_report(void); -/* - * Capability and feature descriptor structure for MIPS CPU - */ -struct mips_cpu { - unsigned int processor_id; - unsigned int fpu_id; - unsigned int cputype; - int isa_level; - int options; - int tlbsize; - struct cache_desc icache; /* Primary I-cache */ - struct cache_desc dcache; /* Primary D or combined I/D cache */ - struct cache_desc scache; /* Secondary cache */ - struct cache_desc tcache; /* Tertiary/split secondary cache */ -}; - -extern struct mips_cpu mips_cpu; - enum cputype { CPU_UNKNOWN, CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, diff --git a/include/asm-mips64/fpu.h b/include/asm-mips64/fpu.h index 3d525e1f41c..49d2f4b304c 100644 --- a/include/asm-mips64/fpu.h +++ b/include/asm-mips64/fpu.h @@ -61,13 +61,13 @@ do { \ #define enable_fpu() \ do { \ - if (mips_cpu.options & MIPS_CPU_FPU) \ + if (current_cpu_data.options & MIPS_CPU_FPU) \ __enable_fpu(); \ } while (0) #define disable_fpu() \ do { \ - if (mips_cpu.options & MIPS_CPU_FPU) \ + if (current_cpu_data.options & MIPS_CPU_FPU) \ __disable_fpu(); \ } while (0) @@ -76,13 +76,13 @@ do { \ static inline int is_fpu_owner(void) { - return (mips_cpu.options & MIPS_CPU_FPU) && + return (current_cpu_data.options & MIPS_CPU_FPU) && test_thread_flag(TIF_USEDFPU); } static inline void own_fpu(void) { - if (mips_cpu.options & MIPS_CPU_FPU) { + if (current_cpu_data.options & MIPS_CPU_FPU) { __enable_fpu(); KSTK_STATUS(current) |= ST0_CU1; set_thread_flag(TIF_USEDFPU); @@ -91,7 +91,7 @@ static inline void own_fpu(void) static inline void loose_fpu(void) { - if (mips_cpu.options & MIPS_CPU_FPU) { + if (current_cpu_data.options & MIPS_CPU_FPU) { KSTK_STATUS(current) &= ~ST0_CU1; clear_thread_flag(TIF_USEDFPU); __disable_fpu(); @@ -100,7 +100,7 @@ static inline void loose_fpu(void) static inline void init_fpu(void) { - if (mips_cpu.options & MIPS_CPU_FPU) { + if (current_cpu_data.options & MIPS_CPU_FPU) { _init_fpu(); } else { fpu_emulator_init_fpu(); @@ -109,19 +109,19 @@ static inline void init_fpu(void) static inline void save_fp(struct task_struct *tsk) { - if (mips_cpu.options & MIPS_CPU_FPU) + if (current_cpu_data.options & MIPS_CPU_FPU) _save_fp(tsk); } static inline void restore_fp(struct task_struct *tsk) { - if (mips_cpu.options & MIPS_CPU_FPU) + if (current_cpu_data.options & MIPS_CPU_FPU) _restore_fp(tsk); } static inline unsigned long *get_fpu_regs(struct task_struct *tsk) { - if (mips_cpu.options & MIPS_CPU_FPU) { + if (current_cpu_data.options & MIPS_CPU_FPU) { if ((tsk == current) && is_fpu_owner()) _save_fp(current); return (unsigned long *)&tsk->thread.fpu.hard.fp_regs[0]; diff --git a/include/asm-mips64/mips64_cache.h b/include/asm-mips64/mips64_cache.h index b9005dbbba8..289c879c878 100644 --- a/include/asm-mips64/mips64_cache.h +++ b/include/asm-mips64/mips64_cache.h @@ -1,11 +1,7 @@ /* - * mips64_cache.h - * * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -19,8 +15,6 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - * * Inline assembly cache operations. * * This file is the original r4cache.c file with modification that makes the @@ -29,18 +23,18 @@ * FIXME: Handle split L2 caches. * */ -#ifndef _MIPS_MIPS64_CACHE_H -#define _MIPS_MIPS64_CACHE_H +#ifndef _ASM_MIPS64_CACHE_H +#define _ASM_MIPS64_CACHE_H #include #include static inline void flush_icache_line_indexed(unsigned long addr) { - unsigned long waystep = icache_size/mips_cpu.icache.ways; + unsigned long waystep = icache_size / current_cpu_data.icache.ways; unsigned int way; - for (way = 0; way < mips_cpu.icache.ways; way++) + for (way = 0; way < current_cpu_data.icache.ways; way++) { __asm__ __volatile__( ".set noreorder\n\t" @@ -56,10 +50,10 @@ static inline void flush_icache_line_indexed(unsigned long addr) static inline void flush_dcache_line_indexed(unsigned long addr) { - unsigned long waystep = dcache_size/mips_cpu.dcache.ways; + unsigned long waystep = dcache_size / current_cpu_data.dcache.ways; unsigned int way; - for (way = 0; way < mips_cpu.dcache.ways; way++) + for (way = 0; way < current_cpu_data.dcache.ways; way++) { __asm__ __volatile__( ".set noreorder\n\t" @@ -75,10 +69,10 @@ static inline void flush_dcache_line_indexed(unsigned long addr) static inline void flush_scache_line_indexed(unsigned long addr) { - unsigned long waystep = scache_size/mips_cpu.scache.ways; + unsigned long waystep = scache_size / current_cpu_data.scache.ways; unsigned int way; - for (way = 0; way < mips_cpu.scache.ways; way++) + for (way = 0; way < current_cpu_data.scache.ways; way++) { __asm__ __volatile__( ".set noreorder\n\t" @@ -189,7 +183,7 @@ static inline void protected_writeback_dcache_line(unsigned long addr) static inline void blast_dcache(void) { unsigned long start = KSEG0; - unsigned long end = (start + dcache_size); + unsigned long end = start + dcache_size; while(start < end) { cache_unroll(start,Index_Writeback_Inv_D); @@ -200,7 +194,7 @@ static inline void blast_dcache(void) static inline void blast_dcache_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while(start < end) { cache_unroll(start,Hit_Writeback_Inv_D); @@ -211,11 +205,11 @@ static inline void blast_dcache_page(unsigned long page) static inline void blast_dcache_page_indexed(unsigned long page) { unsigned long start; - unsigned long end = (page + PAGE_SIZE); - unsigned long waystep = dcache_size/mips_cpu.dcache.ways; + unsigned long end = page + PAGE_SIZE; + unsigned long waystep = dcache_size / current_cpu_data.dcache.ways; unsigned int way; - for (way = 0; way < mips_cpu.dcache.ways; way++) { + for (way = 0; way < current_cpu_data.dcache.ways; way++) { start = page + way*waystep; while(start < end) { cache_unroll(start,Index_Writeback_Inv_D); @@ -227,7 +221,7 @@ static inline void blast_dcache_page_indexed(unsigned long page) static inline void blast_icache(void) { unsigned long start = KSEG0; - unsigned long end = (start + icache_size); + unsigned long end = start + icache_size; while(start < end) { cache_unroll(start,Index_Invalidate_I); @@ -238,7 +232,7 @@ static inline void blast_icache(void) static inline void blast_icache_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while(start < end) { cache_unroll(start,Hit_Invalidate_I); @@ -249,11 +243,11 @@ static inline void blast_icache_page(unsigned long page) static inline void blast_icache_page_indexed(unsigned long page) { unsigned long start; - unsigned long end = (page + PAGE_SIZE); - unsigned long waystep = icache_size/mips_cpu.icache.ways; + unsigned long end = page + PAGE_SIZE; + unsigned long waystep = icache_size / current_cpu_data.icache.ways; unsigned int way; - for (way = 0; way < mips_cpu.icache.ways; way++) { + for (way = 0; way < current_cpu_data.icache.ways; way++) { start = page + way*waystep; while(start < end) { cache_unroll(start,Index_Invalidate_I); @@ -287,12 +281,12 @@ static inline void blast_scache_page(unsigned long page) static inline void blast_scache_page_indexed(unsigned long page) { unsigned long start; - unsigned long end = (page + PAGE_SIZE); - unsigned long waystep = scache_size/mips_cpu.scache.ways; + unsigned long end = page + PAGE_SIZE; + unsigned long waystep = scache_size / current_cpu_data.scache.ways; unsigned int way; - for (way = 0; way < mips_cpu.scache.ways; way++) { - start = page + way*waystep; + for (way = 0; way < current_cpu_data.scache.ways; way++) { + start = page + way * waystep; while(start < end) { cache_unroll(start,Index_Writeback_Inv_SD); start += sc_lsize; @@ -300,6 +294,4 @@ static inline void blast_scache_page_indexed(unsigned long page) } } -#endif /* !(_MIPS_MIPS64_CACHE_H) */ - - +#endif /* _ASM_MIPS64_CACHE_H */ diff --git a/include/asm-mips64/processor.h b/include/asm-mips64/processor.h index 8bf9c06cbf6..9ec6a2ee228 100644 --- a/include/asm-mips64/processor.h +++ b/include/asm-mips64/processor.h @@ -4,7 +4,7 @@ * for more details. * * Copyright (C) 1994 Waldorf GMBH - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Ralf Baechle + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle * Modified further for R[236]000 compatibility by Paul M. Antoine * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ @@ -42,9 +42,24 @@ #include #endif +/* + * Descriptor for a cache + */ +struct cache_desc { + int linesz; + int sets; + int ways; + int flags; /* Details like write thru/back, coherent, etc. */ +}; + +/* + * Flag definitions + */ +#define MIPS_CACHE_NOT_PRESENT 0x00000001 +#define MIPS_CACHE_VTAG_CACHE 0x00000002 /* Virtually tagged cache. */ + struct cpuinfo_mips { unsigned long udelay_val; - unsigned long last_asn; unsigned long asid_cache; #if defined(CONFIG_SGI_IP27) cpuid_t p_cpuid; /* PROM assigned cpuid */ @@ -61,6 +76,20 @@ struct cpuinfo_mips { unsigned long prof_multiplier; unsigned long prof_counter; #endif + + /* + * Capability and feature descriptor structure for MIPS CPU + */ + unsigned int processor_id; + unsigned int fpu_id; + unsigned int cputype; + int isa_level; + int options; + int tlbsize; + struct cache_desc icache; /* Primary I-cache */ + struct cache_desc dcache; /* Primary D or combined I/D cache */ + struct cache_desc scache; /* Secondary cache */ + struct cache_desc tcache; /* Tertiary/split secondary cache */ } __attribute__((aligned(128))); /* @@ -91,12 +120,6 @@ extern int EISA_bus; #define MCA_bus__is_a_macro /* for versions in ksyms.c */ /* - * MIPS has no problems with write protection - */ -#define wp_works_ok 1 -#define wp_works_ok__is_a_macro /* for versions in ksyms.c */ - -/* * User space process size: 1TB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. TASK_SIZE * is limited to 1TB by the R4000 architecture; R10000 and better can diff --git a/include/asm-mips64/r4kcache.h b/include/asm-mips64/r4kcache.h index b08e67f17bd..07e3a63fd24 100644 --- a/include/asm-mips64/r4kcache.h +++ b/include/asm-mips64/r4kcache.h @@ -126,7 +126,7 @@ static inline void protected_writeback_dcache_line(unsigned long addr) static inline void blast_dcache16(void) { unsigned long start = KSEG0; - unsigned long end = (start + dcache_size); + unsigned long end = start + dcache_size; while (start < end) { cache16_unroll32(start,Index_Writeback_Inv_D); @@ -137,12 +137,13 @@ static inline void blast_dcache16(void) static inline void blast_dcache16_wayLSB(void) { unsigned long start = KSEG0; - unsigned long end = (start + mips_cpu.dcache.sets * mips_cpu.dcache.linesz); - int way; + unsigned long end = start + current_cpu_data.dcache.sets * + current_cpu_data.dcache.linesz; + int way, ways = current_cpu_data.dcache.ways; while (start < end) { /* LSB of VA select the way */ - for (way = 0; way < mips_cpu.dcache.ways; way++) + for (way = 0; way < ways; way++) cache16_unroll32(start|way,Index_Writeback_Inv_D); start += 0x200; } @@ -151,7 +152,7 @@ static inline void blast_dcache16_wayLSB(void) static inline void blast_dcache16_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache16_unroll32(start,Hit_Writeback_Inv_D); @@ -162,7 +163,7 @@ static inline void blast_dcache16_page(unsigned long page) static inline void blast_dcache16_page_indexed(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache16_unroll32(start,Index_Writeback_Inv_D); @@ -173,12 +174,12 @@ static inline void blast_dcache16_page_indexed(unsigned long page) static inline void blast_dcache16_page_indexed_wayLSB(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - int way; + unsigned long end = start + PAGE_SIZE; + int way, ways = current_cpu_data.dcache.ways; while (start < end) { /* LSB of VA select the way */ - for (way = 0; way < mips_cpu.dcache.ways; way++) + for (way = 0; way < ways; way++) cache16_unroll32(start|way,Index_Writeback_Inv_D); start += 0x200; } @@ -187,7 +188,7 @@ static inline void blast_dcache16_page_indexed_wayLSB(unsigned long page) static inline void blast_icache16(void) { unsigned long start = KSEG0; - unsigned long end = (start + icache_size); + unsigned long end = start + icache_size; while (start < end) { cache16_unroll32(start,Index_Invalidate_I); @@ -198,12 +199,13 @@ static inline void blast_icache16(void) static inline void blast_icache16_wayLSB(void) { unsigned long start = KSEG0; - unsigned long end = (start + mips_cpu.icache.sets * mips_cpu.icache.linesz); - int way; + unsigned long end = start + current_cpu_data.icache.sets * + current_cpu_data.icache.linesz; + int way, ways = current_cpu_data.icache.ways; while (start < end) { /* LSB of VA select the way */ - for (way = 0; way < mips_cpu.icache.ways; way++) + for (way = 0; way < ways; way++) cache16_unroll32(start|way,Index_Invalidate_I); start += 0x200; } @@ -212,7 +214,7 @@ static inline void blast_icache16_wayLSB(void) static inline void blast_icache16_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache16_unroll32(start,Hit_Invalidate_I); @@ -223,7 +225,7 @@ static inline void blast_icache16_page(unsigned long page) static inline void blast_icache16_page_indexed(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache16_unroll32(start,Index_Invalidate_I); @@ -231,6 +233,20 @@ static inline void blast_icache16_page_indexed(unsigned long page) } } +static inline void blast_icache16_page_indexed_wayLSB(unsigned long page) +{ + unsigned long start = page; + unsigned long end = start + PAGE_SIZE; + int way, ways = current_cpu_data.icache.ways; + + while (start < end) { + /* LSB of VA select the way */ + for (way = 0; way < ways; way++) + cache16_unroll32(start|way,Index_Invalidate_I); + start += 0x200; + } +} + static inline void blast_scache16(void) { unsigned long start = KSEG0; @@ -293,7 +309,7 @@ static inline void blast_scache16_page_indexed(unsigned long page) static inline void blast_dcache32(void) { unsigned long start = KSEG0; - unsigned long end = (start + dcache_size); + unsigned long end = start + dcache_size; while (start < end) { cache32_unroll32(start,Index_Writeback_Inv_D); @@ -304,12 +320,13 @@ static inline void blast_dcache32(void) static inline void blast_dcache32_wayLSB(void) { unsigned long start = KSEG0; - unsigned long end = (start + mips_cpu.dcache.sets * mips_cpu.dcache.linesz); - int way; + unsigned long end = start + current_cpu_data.dcache.sets * + current_cpu_data.dcache.linesz; + int way, ways = current_cpu_data.dcache.ways; while (start < end) { /* LSB of VA select the way */ - for (way = 0; way < mips_cpu.dcache.ways; way++) + for (way = 0; way < ways; way++) cache32_unroll32(start|way,Index_Writeback_Inv_D); start += 0x400; } @@ -330,7 +347,7 @@ static inline void blast_dcache32_wayLSB(void) static inline void blast_dcache32_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; /* * Sigh ... workaround for R4600 v1.7 bug. Explanation see above. @@ -347,7 +364,7 @@ static inline void blast_dcache32_page(unsigned long page) static inline void blast_dcache32_page_indexed(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache32_unroll32(start,Index_Writeback_Inv_D); @@ -358,12 +375,12 @@ static inline void blast_dcache32_page_indexed(unsigned long page) static inline void blast_dcache32_page_indexed_wayLSB(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - int way; + unsigned long end = start + PAGE_SIZE; + int way, ways = current_cpu_data.dcache.ways; while (start < end) { /* LSB of VA select the way */ - for (way = 0; way < mips_cpu.dcache.ways; way++) + for (way = 0; way < ways; way++) cache32_unroll32(start|way,Index_Writeback_Inv_D); start += 0x400; } @@ -372,7 +389,7 @@ static inline void blast_dcache32_page_indexed_wayLSB(unsigned long page) static inline void blast_icache32(void) { unsigned long start = KSEG0; - unsigned long end = (start + icache_size); + unsigned long end = start + icache_size; while (start < end) { cache32_unroll32(start,Index_Invalidate_I); @@ -383,12 +400,13 @@ static inline void blast_icache32(void) static inline void blast_icache32_wayLSB(void) { unsigned long start = KSEG0; - unsigned long end = (start + mips_cpu.icache.sets * mips_cpu.icache.linesz); - int way; + unsigned long end = start + current_cpu_data.icache.sets * + current_cpu_data.icache.linesz; + int way, ways = current_cpu_data.icache.ways; while (start < end) { /* LSB of VA select the way */ - for (way = 0; way < mips_cpu.icache.ways; way++) + for (way = 0; way < ways; way++) cache32_unroll32(start|way,Index_Invalidate_I); start += 0x400; } @@ -397,7 +415,7 @@ static inline void blast_icache32_wayLSB(void) static inline void blast_icache32_page(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache32_unroll32(start,Hit_Invalidate_I); @@ -408,7 +426,7 @@ static inline void blast_icache32_page(unsigned long page) static inline void blast_icache32_page_indexed(unsigned long page) { unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); + unsigned long end = start + PAGE_SIZE; while (start < end) { cache32_unroll32(start,Index_Invalidate_I); @@ -416,6 +434,20 @@ static inline void blast_icache32_page_indexed(unsigned long page) } } +static inline void blast_icache32_page_indexed_wayLSB(unsigned long page) +{ + unsigned long start = page; + unsigned long end = start + PAGE_SIZE; + int way, ways = current_cpu_data.icache.ways; + + while (start < end) { + /* LSB of VA select the way */ + for (way = 0; way < ways; way++) + cache32_unroll32(start|way,Index_Invalidate_I); + start += 0x400; + } +} + static inline void blast_scache32(void) { unsigned long start = KSEG0; -- 2.11.4.GIT