From a69fb3990ea91cdc649af0ab1659cf8e71b14907 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 29 Jul 2003 03:21:47 +0000 Subject: [PATCH] Goodbye mips64. 31704 lines of code bite the dust. --- arch/mips/{Kconfig-shared => Kconfig} | 18 + arch/mips/Makefile | 222 +++- arch/mips/defconfig | 2 +- arch/mips/defconfig-atlas | 2 +- arch/mips/defconfig-capcella | 2 +- arch/mips/defconfig-cobalt | 2 +- arch/mips/defconfig-ddb5476 | 2 +- arch/mips/defconfig-ddb5477 | 2 +- arch/mips/defconfig-decstation | 2 +- arch/mips/defconfig-e55 | 2 +- arch/mips/defconfig-eagle | 2 +- arch/mips/defconfig-ev64120 | 2 +- arch/mips/defconfig-ev96100 | 2 +- arch/mips/defconfig-hp-lj | 2 +- arch/mips/defconfig-ip22 | 2 +- arch/{mips64 => mips}/defconfig-ip27 | 1 - arch/{mips64 => mips}/defconfig-ip32 | 1 - arch/mips/defconfig-it8172 | 2 +- arch/mips/defconfig-ivr | 2 +- arch/mips/defconfig-jmr3927 | 2 +- arch/mips/defconfig-lasat200 | 2 +- arch/mips/defconfig-malta | 2 +- arch/mips/defconfig-mpc30x | 2 +- arch/mips/defconfig-ocelot | 2 +- arch/mips/defconfig-osprey | 2 +- arch/mips/defconfig-pb1000 | 2 +- arch/mips/defconfig-pb1100 | 2 +- arch/mips/defconfig-pb1500 | 2 +- arch/mips/defconfig-rm200 | 2 +- arch/mips/defconfig-sb1250-swarm | 2 +- arch/mips/defconfig-sead | 2 +- arch/mips/defconfig-tb0226 | 2 +- arch/mips/defconfig-tb0229 | 2 +- arch/mips/defconfig-workpad | 2 +- arch/mips/kernel/ioctl32.c | 8 +- arch/mips/kernel/linux32.c | 60 +- arch/mips/kernel/offset.c | 7 + arch/mips/kernel/pci-dma.c | 4 + arch/mips/kernel/reg.c | 69 ++ arch/mips/kernel/scall32-o32.S | 4 +- arch/mips/kernel/scall64-64.S | 6 +- arch/mips/kernel/signal.c | 2 +- arch/mips/kernel/signal32.c | 10 +- arch/mips/kernel/signal_n32.c | 8 +- arch/mips/kernel/syscall.c | 1 + arch/mips/mm-64/tlbex-r4k.S | 17 +- arch/mips/mm/fault.c | 25 - arch/mips/mm/ioremap.c | 4 +- arch/mips/vmlinux.lds.S | 25 +- arch/mips64/.cvsignore | 2 - arch/mips64/Kconfig | 17 - arch/mips64/Makefile | 493 --------- arch/mips64/defconfig | 651 ------------ arch/mips64/defconfig-atlas | 547 ---------- arch/mips64/defconfig-decstation | 573 ----------- arch/mips64/defconfig-ip22 | 645 ------------ arch/mips64/defconfig-malta | 558 ---------- arch/mips64/defconfig-rm200 | 681 ------------- arch/mips64/defconfig-sb1250-swarm | 613 ----------- arch/mips64/defconfig-sead | 392 ------- arch/mips64/vmlinux.lds.S | 174 ---- drivers/net/sgiseeq.c | 22 +- drivers/scsi/sgiwd93.c | 8 +- include/asm-mips/.cvsignore | 1 + include/asm-mips/a.out.h | 73 +- include/{asm-mips64 => asm-mips}/addrspace.h | 64 +- include/{asm-mips64 => asm-mips}/arc/hinv.h | 0 include/asm-mips/asm.h | 13 +- include/asm-mips/{asmmacro.h => asmmacro-32.h} | 35 +- .../asmmacro.h => asm-mips/asmmacro-64.h} | 35 +- include/asm-mips/asmmacro.h | 237 +---- include/asm-mips/atomic.h | 80 +- include/asm-mips/bitops.h | 245 +++-- include/asm-mips/byteorder.h | 8 +- include/{asm-mips64 => asm-mips}/cachectl.h | 3 +- include/asm-mips/cacheops.h | 4 +- include/asm-mips/checksum.h | 36 +- include/{asm-mips64 => asm-mips}/compat.h | 0 include/asm-mips/dec/prom.h | 6 +- include/{asm-mips64 => asm-mips}/delay.h | 44 +- include/asm-mips/div64.h | 50 +- include/asm-mips/dma.h | 10 +- include/asm-mips/elf.h | 88 +- include/asm-mips/fcntl.h | 28 +- include/asm-mips/fpregdef.h | 55 +- include/asm-mips/fpu.h | 4 + include/asm-mips/gdb-stub.h | 427 ++++---- include/asm-mips/hdreg.h | 11 +- include/asm-mips/hw_irq.h | 2 + include/asm-mips/i8259.h | 6 +- include/asm-mips/io.h | 82 +- include/asm-mips/ioctl.h | 15 +- include/{asm-mips64 => asm-mips}/ip32/crime.h | 0 include/{asm-mips64 => asm-mips}/ip32/ip32_ints.h | 0 include/{asm-mips64 => asm-mips}/ip32/mace.h | 0 include/{asm-mips64 => asm-mips}/ip32/machine.h | 0 include/asm-mips/ipc.h | 6 +- include/asm-mips/irq.h | 31 +- include/asm-mips/irq_cpu.h | 6 +- include/{asm-mips64 => asm-mips}/m48t35.h | 0 include/asm-mips/mmu_context.h | 11 +- include/{asm-mips64 => asm-mips}/mmzone.h | 0 include/asm-mips/namei.h | 8 +- include/asm-mips/paccess.h | 215 ++-- include/asm-mips/page-32.h | 26 + include/asm-mips/page-64.h | 31 + include/asm-mips/page.h | 27 +- include/{asm-mips64 => asm-mips}/pci/bridge.h | 0 include/{asm-mips64 => asm-mips}/pgalloc.h | 38 +- include/asm-mips/pgtable-32.h | 224 ++++ include/asm-mips/pgtable-64.h | 209 ++++ include/asm-mips/pgtable.h | 234 +---- include/asm-mips/posix_types.h | 24 +- include/asm-mips/processor.h | 93 +- include/asm-mips/ptrace.h | 41 +- include/asm-mips/reg.h | 66 -- include/asm-mips/regdef.h | 60 +- include/asm-mips/resource.h | 12 +- include/asm-mips/serial.h | 125 ++- include/asm-mips/sfp-machine.h | 47 - include/asm-mips/sgialib.h | 4 +- include/asm-mips/shmbuf.h | 2 +- include/asm-mips/shmiq.h | 225 ----- include/asm-mips/sigcontext.h | 125 ++- include/asm-mips/siginfo.h | 86 +- include/asm-mips/signal.h | 6 +- include/asm-mips/sim.h | 97 ++ include/{asm-mips64 => asm-mips}/sn/addrs.h | 0 include/{asm-mips64 => asm-mips}/sn/agent.h | 0 include/{asm-mips64 => asm-mips}/sn/arch.h | 0 include/{asm-mips64 => asm-mips}/sn/gda.h | 0 include/{asm-mips64 => asm-mips}/sn/intr.h | 0 include/{asm-mips64 => asm-mips}/sn/intr_public.h | 0 include/{asm-mips64 => asm-mips}/sn/io.h | 9 +- include/{asm-mips64 => asm-mips}/sn/ioc3.h | 0 include/{asm-mips64 => asm-mips}/sn/klconfig.h | 0 include/{asm-mips64 => asm-mips}/sn/kldir.h | 0 include/{asm-mips64 => asm-mips}/sn/klkernvars.h | 0 include/{asm-mips64 => asm-mips}/sn/launch.h | 0 .../{asm-mips64 => asm-mips}/sn/mapped_kernel.h | 0 include/{asm-mips64 => asm-mips}/sn/nmi.h | 2 +- include/{asm-mips64 => asm-mips}/sn/sn0/addrs.h | 0 include/{asm-mips64 => asm-mips}/sn/sn0/arch.h | 0 include/{asm-mips64 => asm-mips}/sn/sn0/hub.h | 0 include/{asm-mips64 => asm-mips}/sn/sn0/hubio.h | 0 include/{asm-mips64 => asm-mips}/sn/sn0/hubmd.h | 0 include/{asm-mips64 => asm-mips}/sn/sn0/hubni.h | 0 include/{asm-mips64 => asm-mips}/sn/sn0/hubpi.h | 0 include/{asm-mips64 => asm-mips}/sn/sn0/ip27.h | 0 include/{asm-mips64 => asm-mips}/sn/sn0/sn0_fru.h | 0 include/{asm-mips64 => asm-mips}/sn/sn_private.h | 0 include/{asm-mips64 => asm-mips}/sn/types.h | 0 include/asm-mips/socket.h | 8 + include/asm-mips/sockios.h | 6 +- include/asm-mips/stackframe.h | 269 ++--- include/asm-mips/stat.h | 57 ++ include/asm-mips/statfs.h | 27 +- include/asm-mips/string.h | 18 +- include/asm-mips/sysmips.h | 6 +- include/asm-mips/system.h | 66 +- include/asm-mips/termbits.h | 16 +- include/asm-mips/termios.h | 3 +- include/asm-mips/thread_info.h | 10 +- include/asm-mips/tlbflush.h | 4 +- include/asm-mips/topology.h | 7 + include/asm-mips/traps.h | 8 +- include/asm-mips/types.h | 11 +- include/{asm-mips64 => asm-mips}/uaccess.h | 163 ++- include/asm-mips/unaligned.h | 303 +++--- include/asm-mips/unistd.h | 580 ++++++++++- include/asm-mips/user.h | 16 +- include/asm-mips/watch.h | 6 +- include/asm-mips/wbflush.h | 6 +- include/{asm-mips64 => asm-mips}/xtalk/xtalk.h | 0 include/{asm-mips64 => asm-mips}/xtalk/xwidget.h | 0 include/asm-mips64/.cvsignore | 1 - include/asm-mips64/a.out.h | 33 - include/asm-mips64/arc/types.h | 72 -- include/asm-mips64/asm.h | 386 ------- include/asm-mips64/atomic.h | 195 ---- include/asm-mips64/bcache.h | 62 -- include/asm-mips64/bitops.h | 647 ------------ include/asm-mips64/bootinfo.h | 219 ---- include/asm-mips64/branch.h | 38 - include/asm-mips64/break.h | 33 - include/asm-mips64/bug.h | 21 - include/asm-mips64/bugs.h | 23 - include/asm-mips64/byteorder.h | 29 - include/asm-mips64/cache.h | 25 - include/asm-mips64/cacheflush.h | 65 -- include/asm-mips64/cacheops.h | 81 -- include/asm-mips64/checksum.h | 258 ----- include/asm-mips64/cpu.h | 211 ---- include/asm-mips64/current.h | 23 - include/asm-mips64/dec/ecc.h | 51 - include/asm-mips64/dec/interrupts.h | 125 --- include/asm-mips64/dec/io.h | 20 - include/asm-mips64/dec/ioasic.h | 36 - include/asm-mips64/dec/ioasic_addrs.h | 151 --- include/asm-mips64/dec/ioasic_ints.h | 74 -- include/asm-mips64/dec/kn01.h | 83 -- include/asm-mips64/dec/kn02.h | 106 -- include/asm-mips64/dec/kn02ba.h | 67 -- include/asm-mips64/dec/kn02ca.h | 79 -- include/asm-mips64/dec/kn02xa.h | 75 -- include/asm-mips64/dec/kn03.h | 83 -- include/asm-mips64/dec/kn05.h | 70 -- include/asm-mips64/dec/kn230.h | 26 - include/asm-mips64/dec/machtype.h | 27 - include/asm-mips64/dec/prom.h | 169 ---- include/asm-mips64/dec/rtc-dec.h | 32 - include/asm-mips64/dec/tc.h | 43 - include/asm-mips64/dec/tcinfo.h | 47 - include/asm-mips64/dec/tcmodule.h | 39 - include/asm-mips64/div64.h | 49 - include/asm-mips64/dma-mapping.h | 228 ----- include/asm-mips64/dma.h | 313 ------ include/asm-mips64/ds1286.h | 59 -- include/asm-mips64/elf.h | 219 ---- include/asm-mips64/errno.h | 123 --- include/asm-mips64/fcntl.h | 93 -- include/asm-mips64/floppy.h | 101 -- include/asm-mips64/fpregdef.h | 50 - include/asm-mips64/fpu.h | 137 --- include/asm-mips64/fpu_emulator.h | 38 - include/asm-mips64/gcc/sgidefs.h | 17 - include/asm-mips64/gdb-stub.h | 213 ---- include/asm-mips64/gfx.h | 55 - include/asm-mips64/gt64120.h | 399 -------- include/asm-mips64/hardirq.h | 103 -- include/asm-mips64/hdreg.h | 18 - include/asm-mips64/hw_irq.h | 31 - include/asm-mips64/i8259.h | 23 - include/asm-mips64/ide.h | 74 -- include/asm-mips64/init.h | 1 - include/asm-mips64/inst.h | 371 ------- include/asm-mips64/io.h | 515 ---------- include/asm-mips64/ioctl.h | 88 -- include/asm-mips64/ioctls.h | 105 -- include/asm-mips64/ip32/io.h | 15 - include/asm-mips64/ipc.h | 33 - include/asm-mips64/ipcbuf.h | 28 - include/asm-mips64/irq.h | 58 -- include/asm-mips64/irq_cpu.h | 18 - include/asm-mips64/isadep.h | 35 - include/asm-mips64/keyboard.h | 96 -- include/asm-mips64/kmap_types.h | 35 - include/asm-mips64/linkage.h | 6 - include/asm-mips64/mc146818rtc.h | 60 -- include/asm-mips64/mips-boards/atlas.h | 62 -- include/asm-mips64/mips-boards/atlasint.h | 51 - include/asm-mips64/mips-boards/bonito64.h | 432 -------- include/asm-mips64/mips-boards/generic.h | 111 -- include/asm-mips64/mips-boards/gt64120.h | 337 ------- include/asm-mips64/mips-boards/io.h | 34 - include/asm-mips64/mips-boards/malta.h | 78 -- include/asm-mips64/mips-boards/maltaint.h | 33 - include/asm-mips64/mips-boards/msc01_pci.h | 244 ----- include/asm-mips64/mips-boards/piix4.h | 86 -- include/asm-mips64/mips-boards/saa9730_uart.h | 69 -- include/asm-mips64/mips-boards/sead.h | 36 - include/asm-mips64/mips-boards/seadint.h | 35 - include/asm-mips64/mipsregs.h | 904 ----------------- include/asm-mips64/mman.h | 71 -- include/asm-mips64/mmu.h | 6 - include/asm-mips64/mmu_context.h | 167 --- include/asm-mips64/module.h | 14 - include/asm-mips64/msgbuf.h | 30 - include/asm-mips64/mv64340.h | 1037 ------------------- include/asm-mips64/mv64340_dep.h | 51 - include/asm-mips64/namei.h | 17 - include/asm-mips64/ng1.h | 55 - include/asm-mips64/paccess.h | 99 -- include/asm-mips64/page.h | 136 --- include/asm-mips64/param.h | 46 - include/asm-mips64/parport.h | 15 - include/asm-mips64/pci.h | 131 --- include/asm-mips64/percpu.h | 6 - include/asm-mips64/pgtable-bits.h | 102 -- include/asm-mips64/pgtable.h | 476 --------- include/asm-mips64/poll.h | 27 - include/asm-mips64/posix_types.h | 143 --- include/asm-mips64/processor.h | 313 ------ include/asm-mips64/ptrace.h | 116 --- include/asm-mips64/r4kcache.h | 569 ----------- include/asm-mips64/reboot.h | 16 - include/asm-mips64/reg.h | 67 -- include/asm-mips64/regdef.h | 52 - include/asm-mips64/resource.h | 54 - include/asm-mips64/riscos-syscall.h | 979 ------------------ include/asm-mips64/rmap.h | 7 - include/asm-mips64/rtc.h | 10 - include/asm-mips64/scatterlist.h | 23 - include/asm-mips64/sections.h | 10 - include/asm-mips64/segment.h | 6 - include/asm-mips64/semaphore-helper.h | 182 ---- include/asm-mips64/semaphore.h | 194 ---- include/asm-mips64/sembuf.h | 22 - include/asm-mips64/serial.h | 161 --- include/asm-mips64/sfp-machine.h | 47 - include/asm-mips64/sgi/gio.h | 86 -- include/asm-mips64/sgi/hpc3.h | 317 ------ include/asm-mips64/sgi/io.h | 21 - include/asm-mips64/sgi/ioc.h | 235 ----- include/asm-mips64/sgi/ip22.h | 77 -- include/asm-mips64/sgi/mc.h | 231 ----- include/asm-mips64/sgi/sgi.h | 47 - include/asm-mips64/sgialib.h | 127 --- include/asm-mips64/sgiarcs.h | 547 ---------- include/asm-mips64/sgidefs.h | 44 - include/asm-mips64/shmbuf.h | 38 - include/asm-mips64/shmiq.h | 233 ----- include/asm-mips64/shmparam.h | 11 - include/asm-mips64/sibyte/board.h | 68 -- include/asm-mips64/sibyte/carmel.h | 58 -- include/asm-mips64/sibyte/io.h | 21 - include/asm-mips64/sibyte/sb1250.h | 61 -- include/asm-mips64/sibyte/sb1250_defs.h | 242 ----- include/asm-mips64/sibyte/sb1250_dma.h | 594 ----------- include/asm-mips64/sibyte/sb1250_genbus.h | 276 ----- include/asm-mips64/sibyte/sb1250_int.h | 247 ----- include/asm-mips64/sibyte/sb1250_l2c.h | 128 --- include/asm-mips64/sibyte/sb1250_ldt.h | 425 -------- include/asm-mips64/sibyte/sb1250_mac.h | 643 ------------ include/asm-mips64/sibyte/sb1250_mc.h | 548 ---------- include/asm-mips64/sibyte/sb1250_regs.h | 836 --------------- include/asm-mips64/sibyte/sb1250_scd.h | 582 ----------- include/asm-mips64/sibyte/sb1250_smbus.h | 170 ---- include/asm-mips64/sibyte/sb1250_syncser.h | 148 --- include/asm-mips64/sibyte/sb1250_uart.h | 354 ------- include/asm-mips64/sibyte/sentosa.h | 40 - include/asm-mips64/sibyte/swarm.h | 55 - include/asm-mips64/sibyte/trace_prof.h | 109 -- include/asm-mips64/sigcontext.h | 50 - include/asm-mips64/siginfo.h | 220 ---- include/asm-mips64/signal.h | 153 --- include/asm-mips64/smp.h | 102 -- include/asm-mips64/smplock.h | 67 -- include/asm-mips64/sni.h | 106 -- include/asm-mips64/socket.h | 85 -- include/asm-mips64/sockios.h | 23 - include/asm-mips64/softirq.h | 20 - include/asm-mips64/spinlock.h | 170 ---- include/asm-mips64/stackframe.h | 270 ----- include/asm-mips64/stat.h | 53 - include/asm-mips64/statfs.h | 54 - include/asm-mips64/string.h | 24 - include/asm-mips64/suspend.h | 6 - include/asm-mips64/sysmips.h | 24 - include/asm-mips64/system.h | 356 ------- include/asm-mips64/termbits.h | 206 ---- include/asm-mips64/termios.h | 146 --- include/asm-mips64/thread_info.h | 103 -- include/asm-mips64/time.h | 85 -- include/asm-mips64/timex.h | 58 -- include/asm-mips64/tlb.h | 18 - include/asm-mips64/tlbdebug.h | 20 - include/asm-mips64/tlbflush.h | 52 - include/asm-mips64/topology.h | 13 - include/asm-mips64/traps.h | 26 - include/asm-mips64/types.h | 87 -- include/asm-mips64/ucontext.h | 21 - include/asm-mips64/unaligned.h | 154 --- include/asm-mips64/unistd.h | 1067 -------------------- include/asm-mips64/user.h | 57 -- include/asm-mips64/vga.h | 19 - include/asm-mips64/war.h | 132 --- include/asm-mips64/watch.h | 35 - include/asm-mips64/wbflush.h | 18 - include/asm-mips64/xor.h | 1 - 370 files changed, 3754 insertions(+), 34837 deletions(-) rename arch/mips/{Kconfig-shared => Kconfig} (98%) rename arch/{mips64 => mips}/defconfig-ip27 (99%) rename arch/{mips64 => mips}/defconfig-ip32 (99%) create mode 100644 arch/mips/kernel/reg.c delete mode 100644 arch/mips64/.cvsignore delete mode 100644 arch/mips64/Kconfig delete mode 100644 arch/mips64/Makefile delete mode 100644 arch/mips64/defconfig delete mode 100644 arch/mips64/defconfig-atlas delete mode 100644 arch/mips64/defconfig-decstation delete mode 100644 arch/mips64/defconfig-ip22 delete mode 100644 arch/mips64/defconfig-malta delete mode 100644 arch/mips64/defconfig-rm200 delete mode 100644 arch/mips64/defconfig-sb1250-swarm delete mode 100644 arch/mips64/defconfig-sead delete mode 100644 arch/mips64/vmlinux.lds.S rewrite include/asm-mips/a.out.h (76%) rename include/{asm-mips64 => asm-mips}/addrspace.h (69%) rename include/{asm-mips64 => asm-mips}/arc/hinv.h (100%) copy include/asm-mips/{asmmacro.h => asmmacro-32.h} (90%) rename include/{asm-mips64/asmmacro.h => asm-mips/asmmacro-64.h} (87%) rewrite include/asm-mips/asmmacro.h (89%) rename include/{asm-mips64 => asm-mips}/cachectl.h (87%) rename include/{asm-mips64 => asm-mips}/compat.h (100%) rename include/{asm-mips64 => asm-mips}/delay.h (60%) rewrite include/asm-mips/gdb-stub.h (69%) rename include/{asm-mips64 => asm-mips}/ip32/crime.h (100%) rename include/{asm-mips64 => asm-mips}/ip32/ip32_ints.h (100%) rename include/{asm-mips64 => asm-mips}/ip32/mace.h (100%) rename include/{asm-mips64 => asm-mips}/ip32/machine.h (100%) rename include/{asm-mips64 => asm-mips}/m48t35.h (100%) rename include/{asm-mips64 => asm-mips}/mmzone.h (100%) rewrite include/asm-mips/paccess.h (63%) create mode 100644 include/asm-mips/page-32.h create mode 100644 include/asm-mips/page-64.h rename include/{asm-mips64 => asm-mips}/pci/bridge.h (100%) rename include/{asm-mips64 => asm-mips}/pgalloc.h (72%) create mode 100644 include/asm-mips/pgtable-32.h create mode 100644 include/asm-mips/pgtable-64.h delete mode 100644 include/asm-mips/reg.h delete mode 100644 include/asm-mips/sfp-machine.h delete mode 100644 include/asm-mips/shmiq.h rewrite include/asm-mips/sigcontext.h (61%) create mode 100644 include/asm-mips/sim.h rename include/{asm-mips64 => asm-mips}/sn/addrs.h (100%) rename include/{asm-mips64 => asm-mips}/sn/agent.h (100%) rename include/{asm-mips64 => asm-mips}/sn/arch.h (100%) rename include/{asm-mips64 => asm-mips}/sn/gda.h (100%) rename include/{asm-mips64 => asm-mips}/sn/intr.h (100%) rename include/{asm-mips64 => asm-mips}/sn/intr_public.h (100%) rename include/{asm-mips64 => asm-mips}/sn/io.h (90%) rename include/{asm-mips64 => asm-mips}/sn/ioc3.h (100%) rename include/{asm-mips64 => asm-mips}/sn/klconfig.h (100%) rename include/{asm-mips64 => asm-mips}/sn/kldir.h (100%) rename include/{asm-mips64 => asm-mips}/sn/klkernvars.h (100%) rename include/{asm-mips64 => asm-mips}/sn/launch.h (100%) rename include/{asm-mips64 => asm-mips}/sn/mapped_kernel.h (100%) rename include/{asm-mips64 => asm-mips}/sn/nmi.h (99%) rename include/{asm-mips64 => asm-mips}/sn/sn0/addrs.h (100%) rename include/{asm-mips64 => asm-mips}/sn/sn0/arch.h (100%) rename include/{asm-mips64 => asm-mips}/sn/sn0/hub.h (100%) rename include/{asm-mips64 => asm-mips}/sn/sn0/hubio.h (100%) rename include/{asm-mips64 => asm-mips}/sn/sn0/hubmd.h (100%) rename include/{asm-mips64 => asm-mips}/sn/sn0/hubni.h (100%) rename include/{asm-mips64 => asm-mips}/sn/sn0/hubpi.h (100%) rename include/{asm-mips64 => asm-mips}/sn/sn0/ip27.h (100%) rename include/{asm-mips64 => asm-mips}/sn/sn0/sn0_fru.h (100%) rename include/{asm-mips64 => asm-mips}/sn/sn_private.h (100%) rename include/{asm-mips64 => asm-mips}/sn/types.h (100%) rename include/{asm-mips64 => asm-mips}/uaccess.h (77%) rewrite include/asm-mips/unaligned.h (69%) rename include/{asm-mips64 => asm-mips}/xtalk/xtalk.h (100%) rename include/{asm-mips64 => asm-mips}/xtalk/xwidget.h (100%) delete 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a/arch/mips/Kconfig-shared +++ b/arch/mips/Kconfig @@ -1,3 +1,21 @@ +config MIPS + bool + default y + +config MIPS64 + bool "64-bit kernel" + help + Select this option if you want to build a 64-bit kernel. You should + only select this option if you have hardware that actually has a + 32-bit processor and if your application will actually benefit from + 64-bit processing, otherwise say N. You must say Y for kernels for + SGI IP27 (Origin 200 and 2000). If in doubt say N. + +config MIPS32 + bool + depends on MIPS64 = 'n' + default y + mainmenu "Linux/MIPS Kernel Configuration" source "init/Kconfig" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 4deef2d10b5..6c4ee27be20 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -3,7 +3,7 @@ # License. See the file "COPYING" in the main directory of this archive # for more details. # -# Copyright (C) 1994, 1995, 1996 by Ralf Baechle +# Copyright (C) 1994, 95, 96, 2003 by Ralf Baechle # DECStation modifications by Paul M. Antoine, 1996 # Copyright (C) 2002 Maciej W. Rozycki # @@ -13,23 +13,6 @@ # # -# Select the object file format to substitute into the linker script. -# -ifdef CONFIG_CPU_LITTLE_ENDIAN -tool-prefix = mipsel-linux- -JIFFIES32 = jiffies_64 -LDFLAGS_BLOB := --format binary --oformat elf32-tradlittlemips -else -tool-prefix = mips-linux- -JIFFIES32 = jiffies_64 + 4 -LDFLAGS_BLOB := --format binary --oformat elf32-tradbigmips -endif - -ifdef CONFIG_CROSSCOMPILE -CROSS_COMPILE := $(tool-prefix) -endif - -# # GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel # code since it only slows down the whole thing. At some point we might make # use of global pointer optimizations but their use of $28 conflicts with @@ -41,6 +24,7 @@ endif # cflags-y := -I $(TOPDIR)/include/asm/gcc cflags-y += -G 0 -mno-abicalls -fno-pic -pipe +cflags-$(CONFIG_MIPS64) += -mabi=64 LDFLAGS_vmlinux += -G 0 -static # -N MODFLAGS += -mlong-calls @@ -52,35 +36,71 @@ check_warning = $(shell if $(CC) $(1) -c -o /dev/null -xc /dev/null > /dev/null # # CPU-dependent compiler/assembler options for optimization. -# -cflags-$(CONFIG_CPU_R3000) += -mcpu=r3000 -mips1 -cflags-$(CONFIG_CPU_TX39XX) += -mcpu=r3000 -mips1 -cflags-$(CONFIG_CPU_R6000) += -mcpu=r6000 -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_R4300) += -mcpu=r4300 -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_VR41XX) += -mcpu=r4600 -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_R4X00) += -mcpu=r4600 -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_TX49XX) += -mcpu=r4600 -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_MIPS32) += -mcpu=r4600 -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_MIPS64) += -mcpu=r4600 -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_R5000) += -mcpu=r5000 -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_R5432) += -mcpu=r5000 -mips2 -Wa,--trap -# Cannot use -mmad with currently recommended tools -cflags-$(CONFIG_CPU_NEVADA) += -mcpu=r5000 -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_RM7000) += -mcpu=r5000 -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_RM7000) += $(call check_gcc, -mcpu=r7000, -mcpu=r5000) \ - -mips2 -Wa,--trap -cflags-$(CONFIG_CPU_SB1) += $(call check_gcc, -mcpu=sb1, -mcpu=r8000) \ - -mips2 -Wa,--trap +# This is done in several steps: +# +# - cflags-y contains the options which select for which processor to +# optimize the code for. The options should not contain any +# options that change the ISA level but only compiler flags to +# tune performance of the generated code. +# - 32bit-isa-y contains the options which select the ISA for 32-bit kernels. +# A kernel built those options will only work on hardware which +# actually supports this ISA. +# - 64bit-isa-y contains the options which select the ISA for 64-bit kernels. +# A kernel built those options will only work on hardware which +# actually supports this ISA. +# +cflags-$(CONFIG_CPU_R3000) += -mcpu=r3000 +32bit-isa-$(CONFIG_CPU_R3000) += -mips1 +64bit-isa-$(CONFIG_CPU_R3000) += -mboom +cflags-$(CONFIG_CPU_TX39XX) += -mcpu=r3000 +32bit-isa-$(CONFIG_CPU_TX39XX) += -mips1 +64bit-isa-$(CONFIG_CPU_TX39XX) += -mboom +cflags-$(CONFIG_CPU_R6000) += -mcpu=r6000 +32bit-isa-$(CONFIG_CPU_R6000) += -mips2 -Wa,--trap +64bit-isa-$(CONFIG_CPU_R6000) += -mboom -Wa,--trap +cflags-$(CONFIG_CPU_R4300) += -mcpu=r4300 +32bit-isa-$(CONFIG_CPU_R4300) += -mips2 -Wa,--trap +64bit-isa-$(CONFIG_CPU_R4300) += -mips3 -Wa,--trap +cflags-$(CONFIG_CPU_VR41XX) += -mcpu=r4600 +32bit-isa-$(CONFIG_CPU_VR41XX) += -mips2 -Wa,--trap +64bit-isa-$(CONFIG_CPU_VR41XX) += -mips3 -Wa,--trap +cflags-$(CONFIG_CPU_R4X00) += -mcpu=r4600 +32bit-isa-$(CONFIG_CPU_R4X00) += -mips2 -Wa,--trap +64bit-isa-$(CONFIG_CPU_R4X00) += -mips3 -Wa,--trap +cflags-$(CONFIG_CPU_MIPS32) += -mcpu=r4600 +32bit-isa-$(CONFIG_CPU_MIPS32) += $(call check_gcc, -mips32, -mips2) -Wa,--trap +64bit-isa-$(CONFIG_CPU_MIPS32) += -mboom -Wa,--trap +cflags-$(CONFIG_CPU_MIPS64) += +32bit-isa-$(CONFIG_CPU_MIPS64) += $(call check_gcc, -mips32, -mips2) -Wa,--trap +64bit-isa-$(CONFIG_CPU_MIPS64) += $(call check_gcc, -mips64, -mips4) -Wa,--trap +cflags-$(CONFIG_CPU_R5000) += -mcpu=r8000 +32bit-isa-$(CONFIG_CPU_R5000) += -mips2 -Wa,--trap +64bit-isa-$(CONFIG_CPU_R5000) += -mips4 -Wa,--trap +cflags-$(CONFIG_CPU_R5432) += -mcpu=r5000 +32bit-isa-$(CONFIG_CPU_R5432) += -mips1 -Wa,--trap +64bit-isa-$(CONFIG_CPU_R5432) += -mips3 -Wa,--trap +cflags-$(CONFIG_CPU_NEVADA) += -mcpu=r8000 -mmad +32bit-isa-$(CONFIG_CPU_NEVADA) += -mips2 -Wa,--trap +64bit-isa-$(CONFIG_CPU_NEVADA) += -mips3 -Wa,--trap +cflags-$(CONFIG_CPU_RM7000) += $(call check_gcc, -mcpu=r7000, -mcpu=r5000) +32bit-isa-$(CONFIG_CPU_RM7000) += -mips2 -Wa,--trap +64bit-isa-$(CONFIG_CPU_RM7000) += -mips4 -Wa,--trap +cflags-$(CONFIG_CPU_SB1) += $(call check_gcc, -mcpu=sb1, -mcpu=r8000) +32bit-isa-$(CONFIG_CPU_SB1) += $(call check_gcc, -mips32, -mips2) -Wa,--trap +64bit-isa-$(CONFIG_CPU_SB1) += $(call check_gcc, -mips64, -mips4) -Wa,--trap +cflags-$(CONFIG_CPU_R8000) += -mcpu=r8000 +32bit-isa-$(CONFIG_CPU_R8000) += -mips2 -Wa,--trap +64bit-isa-$(CONFIG_CPU_R8000) += -mips4 -Wa,--trap +cflags-$(CONFIG_CPU_R10000) += -mcpu=r8000 +32bit-isa-$(CONFIG_CPU_R10000) += -mips2 -Wa,--trap +64bit-isa-$(CONFIG_CPU_R10000) += -mips4 -Wa,--trap + ifdef CONFIG_CPU_SB1 ifdef CONFIG_SB1_PASS_1_WORKAROUNDS MODFLAGS += -msb1-pass1-workarounds endif endif -AFLAGS += $(cflags-y) -CFLAGS += $(cflags-y) - - # # ramdisk/initrd support # You need a compressed ramdisk image, named ramdisk.gz in @@ -289,11 +309,17 @@ load-$(CONFIG_TANBAC_TB0229) += 0x80000000 # SGI IP22 (Indy/Indigo2) # # Set the load address to >= 0x88069000 if you want to leave space for symmon, -# 0x88002000 for production kernels. Note that the value must be 8kb aligned -# or the handling of the current variable will break. +# 0x80002000 for production kernels. Note that the value must be aligned to +# a multiple of the kernel stack size or the handling of the current variable +# will break so for 64-bit kernels we have to raise the start address by 8kb. # core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/ +ifdef CONFIG_MIPS32 load-$(CONFIG_SGI_IP22) += 0x88002000 +endif +ifdef CONFIG_MIPS64 +load-$(CONFIG_SGI_IP22) += 0x88004000 +endif # # SGI-IP27 (Origin200/2000) @@ -315,11 +341,18 @@ endif # # SGI-IP32 (O2) # -# Set the load address to >= 0x????????? if you want to leave space for symmon,+# 0x80002000 for production kernels. Note that the value must be 16kb aligned -# or the handling of the current variable will break. +# Set the load address to >= 0x????????? if you want to leave space for symmon, +# 0x80002000 for production kernels. Note that the value must be aligned to +# a multiple of the kernel stack size or the handling of the current variable +# will break so for 64-bit kernels we have to raise the start address by 8kb. # core-$(CONFIG_SGI_IP32) += arch/mips/sgi-ip32/ -load-$(CONFIG_SGI_IP32) += 0x80002000 +ifdef CONFIG_MIPS32 +load-$(CONFIG_SGI_IP32) += 0x88002000 +endif +ifdef CONFIG_MIPS64 +load-$(CONFIG_SGI_IP32) += 0x88004000 +endif # # Sibyte SB1250 SOC @@ -374,6 +407,62 @@ load-$(CONFIG_TOSHIBA_RBTX4927) += 0x80020000 drivers-$(CONFIG_PCI) += arch/mips/pci/ +# +# Select the object file format to substitute into the linker script. +# +ifdef CONFIG_CPU_LITTLE_ENDIAN +32bit-tool-prefix = mips64el-linux- +64bit-tool-prefix = mips64el-linux- +32bit-bfd = elf32-tradlittlemips +64bit-bfd = elf64-tradlittlemips +else +32bit-tool-prefix = mips64-linux- +64bit-tool-prefix = mips64-linux- +32bit-bfd = elf32-tradbigmips +64bit-bfd = elf64-tradbigmips +endif + +ifdef CONFIG_MIPS32 +tool-prefix = $(32bit-tool-prefix) +build-bfd = $(32bit-bfd) +cflags-y += $(32bit-isa-y) +endif +ifdef CONFIG_MIPS64 +tool-prefix = $(64bit-tool-prefix) +build-bfd = $(64bit-bfd) +cflags-y += $(64bit-isa-y) +endif + +ifdef CONFIG_MIPS32 +ifdef CONFIG_CPU_LITTLE_ENDIAN +JIFFIES = jiffies_64 +else +JIFFIES = jiffies_64 + 4 +endif +else +JIFFIES = jiffies_64 +endif + +ifdef CONFIG_CROSSCOMPILE +CROSS_COMPILE := $(tool-prefix) +endif + +# +# Some machines like the Indy need 32-bit ELF binaries for booting purposes. +# Other need ECOFF, so we build a 32-bit ELF binary for them which we then +# convert to ECOFF using elf2ecoff. +# +# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit +# ELF files from 32-bit files by conversion. +# +#AS += -64 +#LDFLAGS += -m elf64bmip +cflags-$(CONFIG_BOOT_ELF32) += -Wa,-32 +cflags-$(CONFIG_BOOT_ELF64) += -Wa,-32 + +GRRR=-Wa,-mgp64 +cflags-$(CONFIG_BOOT_ELF32) += -Wa,-32 $(call check_warning, $(GRRR),) +cflags-$(CONFIG_BOOT_ELF64) += -Wa,-32 $(call check_warning, $(GRRR),) # # Choosing incompatible machines durings configuration will result in @@ -381,7 +470,16 @@ drivers-$(CONFIG_PCI) += arch/mips/pci/ # none has been choosen above. # -AFLAGS_vmlinux.lds.o := -D"LOADADDR=$(load-y)" -D"JIFFIES32=$(JIFFIES32)" +AFLAGS_vmlinux.lds.o := \ + -D"LOADADDR=$(load-y)" \ + -D"JIFFIES=$(JIFFIES)" \ + -imacros $(srctree)/include/asm-$(ARCH)/sn/mapped_kernel.h + +AFLAGS += $(cflags-y) +CFLAGS += $(cflags-y) + +LDFLAGS += --oformat $(32bit-bfd) +LDFLAGS_BLOB := --format binary --oformat $(64bit-bfd) head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o @@ -445,8 +543,23 @@ archclean: define filechk_gen-asm-offset.h (set -e; \ - echo "#ifndef __ASM_OFFSET_H"; \ - echo "#define __ASM_OFFSET_H"; \ + echo "#ifndef _ASM_OFFSET_H"; \ + echo "#define _ASM_OFFSET_H"; \ + echo "/*"; \ + echo " * DO NOT MODIFY."; \ + echo " *"; \ + echo " * This file was generated by arch/$(ARCH)/Makefile"; \ + echo " *"; \ + echo " */"; \ + echo ""; \ + sed -ne "/^@@@/s///p"; \ + echo "#endif /* _ASM_OFFSET_H */" ) +endef + +define filechk_gen-asm-reg.h + (set -e; \ + echo "#ifndef _ASM_REG_H"; \ + echo "#define _ASM_REG_H"; \ echo "/*"; \ echo " * DO NOT MODIFY."; \ echo " *"; \ @@ -455,16 +568,21 @@ define filechk_gen-asm-offset.h echo " */"; \ echo ""; \ sed -ne "/^@@@/s///p"; \ - echo "#endif /* __ASM_OFFSET_H */" ) + echo "#endif /* _ASM_REG_H */" ) endef -prepare: include/asm-$(ARCH)/offset.h +prepare: include/asm-$(ARCH)/offset.h \ + include/asm-$(ARCH)/reg.h arch/$(ARCH)/kernel/offset.s: include/asm include/linux/version.h \ include/config/MARKER include/asm-$(ARCH)/offset.h: arch/$(ARCH)/kernel/offset.s $(call filechk,gen-asm-offset.h) +include/asm-$(ARCH)/reg.h: arch/$(ARCH)/kernel/reg.s + $(call filechk,gen-asm-reg.h) CLEAN_FILES += include/asm-$(ARCH)/offset.h.tmp \ - include/asm-$(ARCH)/offset.h + include/asm-$(ARCH)/offset.h \ + include/asm-$(ARCH)/reg.h.tmp \ + include/asm-$(ARCH)/reg.h diff --git a/arch/mips/defconfig b/arch/mips/defconfig index ccdc6177519..5881ba749fc 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-atlas b/arch/mips/defconfig-atlas index 59afcb223cd..5de45b8d8d2 100644 --- a/arch/mips/defconfig-atlas +++ b/arch/mips/defconfig-atlas @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-capcella b/arch/mips/defconfig-capcella index 9830781bba7..9d0c9147c29 100644 --- a/arch/mips/defconfig-capcella +++ b/arch/mips/defconfig-capcella @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-cobalt b/arch/mips/defconfig-cobalt index 615b7b8b6a5..eb318c25f7f 100644 --- a/arch/mips/defconfig-cobalt +++ b/arch/mips/defconfig-cobalt @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-ddb5476 b/arch/mips/defconfig-ddb5476 index 8dfda5da4ba..a67ae85a4b7 100644 --- a/arch/mips/defconfig-ddb5476 +++ b/arch/mips/defconfig-ddb5476 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-ddb5477 b/arch/mips/defconfig-ddb5477 index 3b56a5d02c0..ab1d8f93716 100644 --- a/arch/mips/defconfig-ddb5477 +++ b/arch/mips/defconfig-ddb5477 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-decstation b/arch/mips/defconfig-decstation index abbfd18df32..d17cd2de718 100644 --- a/arch/mips/defconfig-decstation +++ b/arch/mips/defconfig-decstation @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-e55 b/arch/mips/defconfig-e55 index a6d1ba528da..47c52907d92 100644 --- a/arch/mips/defconfig-e55 +++ b/arch/mips/defconfig-e55 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-eagle b/arch/mips/defconfig-eagle index cec2489e755..b7b5565bed3 100644 --- a/arch/mips/defconfig-eagle +++ b/arch/mips/defconfig-eagle @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-ev64120 b/arch/mips/defconfig-ev64120 index 809200e3fce..8e94d4d0f20 100644 --- a/arch/mips/defconfig-ev64120 +++ b/arch/mips/defconfig-ev64120 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-ev96100 b/arch/mips/defconfig-ev96100 index 9eab980d595..3ae99aab160 100644 --- a/arch/mips/defconfig-ev96100 +++ b/arch/mips/defconfig-ev96100 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-hp-lj b/arch/mips/defconfig-hp-lj index 1b4a97da24c..6fc941064ab 100644 --- a/arch/mips/defconfig-hp-lj +++ b/arch/mips/defconfig-hp-lj @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-ip22 b/arch/mips/defconfig-ip22 index ccdc6177519..5881ba749fc 100644 --- a/arch/mips/defconfig-ip22 +++ b/arch/mips/defconfig-ip22 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips64/defconfig-ip27 b/arch/mips/defconfig-ip27 similarity index 99% rename from arch/mips64/defconfig-ip27 rename to arch/mips/defconfig-ip27 index 74d95d4549a..2305b6dc3ea 100644 --- a/arch/mips64/defconfig-ip27 +++ b/arch/mips/defconfig-ip27 @@ -2,7 +2,6 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -# CONFIG_MIPS32 is not set CONFIG_MIPS64=y # diff --git a/arch/mips64/defconfig-ip32 b/arch/mips/defconfig-ip32 similarity index 99% rename from arch/mips64/defconfig-ip32 rename to arch/mips/defconfig-ip32 index 50b1ab28b88..a1f628182f2 100644 --- a/arch/mips64/defconfig-ip32 +++ b/arch/mips/defconfig-ip32 @@ -2,7 +2,6 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -# CONFIG_MIPS32 is not set CONFIG_MIPS64=y # diff --git a/arch/mips/defconfig-it8172 b/arch/mips/defconfig-it8172 index 563e7cbf075..373f102f2ab 100644 --- a/arch/mips/defconfig-it8172 +++ b/arch/mips/defconfig-it8172 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-ivr b/arch/mips/defconfig-ivr index f820ea8f3ba..52380ec275f 100644 --- a/arch/mips/defconfig-ivr +++ b/arch/mips/defconfig-ivr @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-jmr3927 b/arch/mips/defconfig-jmr3927 index 2a4dd541067..cd65a22f2db 100644 --- a/arch/mips/defconfig-jmr3927 +++ b/arch/mips/defconfig-jmr3927 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-lasat200 b/arch/mips/defconfig-lasat200 index 0f8d2d01c66..6392b8f5275 100644 --- a/arch/mips/defconfig-lasat200 +++ b/arch/mips/defconfig-lasat200 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-malta b/arch/mips/defconfig-malta index 49c9d0b1b73..98dd0d012db 100644 --- a/arch/mips/defconfig-malta +++ b/arch/mips/defconfig-malta @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-mpc30x b/arch/mips/defconfig-mpc30x index eab3564ebf1..5df64f90d9e 100644 --- a/arch/mips/defconfig-mpc30x +++ b/arch/mips/defconfig-mpc30x @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-ocelot b/arch/mips/defconfig-ocelot index 38b2ed73596..92770056196 100644 --- a/arch/mips/defconfig-ocelot +++ b/arch/mips/defconfig-ocelot @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-osprey b/arch/mips/defconfig-osprey index 7a6d337da51..d00bc5de1a6 100644 --- a/arch/mips/defconfig-osprey +++ b/arch/mips/defconfig-osprey @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-pb1000 b/arch/mips/defconfig-pb1000 index 3cfb3dcfad0..96ff6d38cf1 100644 --- a/arch/mips/defconfig-pb1000 +++ b/arch/mips/defconfig-pb1000 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-pb1100 b/arch/mips/defconfig-pb1100 index 41b927869a5..78a3f5782a1 100644 --- a/arch/mips/defconfig-pb1100 +++ b/arch/mips/defconfig-pb1100 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-pb1500 b/arch/mips/defconfig-pb1500 index ba8ed1a9795..388a4242b33 100644 --- a/arch/mips/defconfig-pb1500 +++ b/arch/mips/defconfig-pb1500 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-rm200 b/arch/mips/defconfig-rm200 index 2cd91dbaaf8..e021d68df89 100644 --- a/arch/mips/defconfig-rm200 +++ b/arch/mips/defconfig-rm200 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-sb1250-swarm b/arch/mips/defconfig-sb1250-swarm index 17dab298ee2..a468cfbafb8 100644 --- a/arch/mips/defconfig-sb1250-swarm +++ b/arch/mips/defconfig-sb1250-swarm @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-sead b/arch/mips/defconfig-sead index 3336d2713f1..8e632c05487 100644 --- a/arch/mips/defconfig-sead +++ b/arch/mips/defconfig-sead @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-tb0226 b/arch/mips/defconfig-tb0226 index ab3631e140a..ce38ff6dadc 100644 --- a/arch/mips/defconfig-tb0226 +++ b/arch/mips/defconfig-tb0226 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-tb0229 b/arch/mips/defconfig-tb0229 index afdfd70af72..3b77e682751 100644 --- a/arch/mips/defconfig-tb0229 +++ b/arch/mips/defconfig-tb0229 @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/defconfig-workpad b/arch/mips/defconfig-workpad index 54b4c91bc40..57a22781a16 100644 --- a/arch/mips/defconfig-workpad +++ b/arch/mips/defconfig-workpad @@ -2,8 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -CONFIG_MIPS32=y # CONFIG_MIPS64 is not set +CONFIG_MIPS32=y # # Code maturity level options diff --git a/arch/mips/kernel/ioctl32.c b/arch/mips/kernel/ioctl32.c index fab1eacd184..77777859a90 100644 --- a/arch/mips/kernel/ioctl32.c +++ b/arch/mips/kernel/ioctl32.c @@ -338,13 +338,13 @@ struct ifreq32 { struct ifmap32 ifru_map; char ifru_slave[IFNAMSIZ]; /* Just fits the size */ char ifru_newname[IFNAMSIZ]; - __kernel_caddr_t32 ifru_data; + compat_caddr_t ifru_data; } ifr_ifru; }; struct ifconf32 { int ifc_len; /* size of buffer */ - __kernel_caddr_t32 ifcbuf; + compat_caddr_t ifcbuf; }; #ifdef CONFIG_NET @@ -679,8 +679,8 @@ struct mtget32 { __u32 mt_dsreg; __u32 mt_gstat; __u32 mt_erreg; - __kernel_daddr_t32 mt_fileno; - __kernel_daddr_t32 mt_blkno; + compat_daddr_t mt_fileno; + compat_daddr_t mt_blkno; }; #define MTIOCGET32 _IOR('m', 2, struct mtget32) diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 2991013a31b..20b227a51a7 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -449,7 +450,7 @@ put_rusage (struct rusage32 *ru, struct rusage *r) } asmlinkage int -sys32_wait4(__kernel_pid_t32 pid, unsigned int * stat_addr, int options, +sys32_wait4(compat_pid_t pid, unsigned int * stat_addr, int options, struct rusage32 * ru) { if (!ru) @@ -471,7 +472,7 @@ sys32_wait4(__kernel_pid_t32 pid, unsigned int * stat_addr, int options, } asmlinkage int -sys32_waitpid(__kernel_pid_t32 pid, unsigned int *stat_addr, int options) +sys32_waitpid(compat_pid_t pid, unsigned int *stat_addr, int options) { return sys32_wait4(pid, stat_addr, options, NULL); } @@ -1017,7 +1018,7 @@ out_nofds: extern asmlinkage int sys_sched_rr_get_interval(pid_t pid, struct timespec *interval); -asmlinkage int sys32_sched_rr_get_interval(__kernel_pid_t32 pid, +asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid, struct compat_timespec *interval) { struct timespec t; @@ -1038,22 +1039,22 @@ struct msgbuf32 { s32 mtype; char mtext[1]; }; struct ipc_perm32 { key_t key; - __kernel_uid_t32 uid; - __kernel_gid_t32 gid; - __kernel_uid_t32 cuid; - __kernel_gid_t32 cgid; - __kernel_mode_t32 mode; + compat_uid_t uid; + compat_gid_t gid; + compat_uid_t cuid; + compat_gid_t cgid; + compat_mode_t mode; unsigned short seq; }; struct ipc64_perm32 { key_t key; - __kernel_uid_t32 uid; - __kernel_gid_t32 gid; - __kernel_uid_t32 cuid; - __kernel_gid_t32 cgid; - __kernel_mode_t32 mode; - unsigned short seq; + compat_uid_t uid; + compat_gid_t gid; + compat_uid_t cuid; + compat_gid_t cgid; + compat_mode_t mode; + unsigned short seq; unsigned short __pad1; unsigned int __unused1; unsigned int __unused2; @@ -1092,8 +1093,8 @@ struct msqid_ds32 unsigned short msg_cbytes; unsigned short msg_qnum; unsigned short msg_qbytes; - __kernel_ipc_pid_t32 msg_lspid; - __kernel_ipc_pid_t32 msg_lrpid; + compat_ipc_pid_t msg_lspid; + compat_ipc_pid_t msg_lrpid; }; struct msqid64_ds32 { @@ -1107,8 +1108,8 @@ struct msqid64_ds32 { unsigned int msg_cbytes; unsigned int msg_qnum; unsigned int msg_qbytes; - __kernel_pid_t32 msg_lspid; - __kernel_pid_t32 msg_lrpid; + compat_pid_t msg_lspid; + compat_pid_t msg_lrpid; unsigned int __unused4; unsigned int __unused5; }; @@ -1119,8 +1120,8 @@ struct shmid_ds32 { compat_time_t shm_atime; compat_time_t shm_dtime; compat_time_t shm_ctime; - __kernel_ipc_pid_t32 shm_cpid; - __kernel_ipc_pid_t32 shm_lpid; + compat_ipc_pid_t shm_cpid; + compat_ipc_pid_t shm_lpid; unsigned short shm_nattch; }; @@ -1130,8 +1131,8 @@ struct shmid64_ds32 { compat_time_t shm_atime; compat_time_t shm_dtime; compat_time_t shm_ctime; - __kernel_pid_t32 shm_cpid; - __kernel_pid_t32 shm_lpid; + compat_pid_t shm_cpid; + compat_pid_t shm_lpid; unsigned int shm_nattch; unsigned int __unused1; unsigned int __unused2; @@ -1605,11 +1606,11 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) struct sysctl_args32 { - __kernel_caddr_t32 name; + compat_caddr_t name; int nlen; - __kernel_caddr_t32 oldval; - __kernel_caddr_t32 oldlenp; - __kernel_caddr_t32 newval; + compat_caddr_t oldval; + compat_caddr_t oldlenp; + compat_caddr_t newval; compat_size_t newlen; unsigned int __unused[4]; }; @@ -1666,7 +1667,7 @@ asmlinkage long sys32_sysctl(struct sysctl_args32 *args) extern asmlinkage int sys_sched_setaffinity(pid_t pid, unsigned int len, unsigned long *user_mask_ptr); -asmlinkage int sys32_sched_setaffinity(__kernel_pid_t32 pid, unsigned int len, +asmlinkage int sys32_sched_setaffinity(compat_pid_t pid, unsigned int len, u32 *user_mask_ptr) { unsigned long kernel_mask; @@ -1690,7 +1691,7 @@ asmlinkage int sys32_sched_setaffinity(__kernel_pid_t32 pid, unsigned int len, extern asmlinkage int sys_sched_getaffinity(pid_t pid, unsigned int len, unsigned long *user_mask_ptr); -asmlinkage int sys32_sched_getaffinity(__kernel_pid_t32 pid, unsigned int len, +asmlinkage int sys32_sched_getaffinity(compat_pid_t pid, unsigned int len, u32 *user_mask_ptr) { unsigned long kernel_mask; @@ -1817,7 +1818,8 @@ asmlinkage int sys32_adjtimex(struct timex32 *utp) extern asmlinkage ssize_t sys_sendfile(int out_fd, int in_fd, off_t *offset, size_t count); -asmlinkage int sys32_sendfile(int out_fd, int in_fd, __kernel_off_t32 *offset, s32 count) +asmlinkage int sys32_sendfile(int out_fd, int in_fd, compat_off_t *offset, + s32 count) { mm_segment_t old_fs = get_fs(); int ret; diff --git a/arch/mips/kernel/offset.c b/arch/mips/kernel/offset.c index dc70eb96e6e..995cd4b2c74 100644 --- a/arch/mips/kernel/offset.c +++ b/arch/mips/kernel/offset.c @@ -96,6 +96,7 @@ void output_thread_info_defines(void) offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block); constant("#define _THREAD_SIZE_ORDER ", THREAD_SIZE_ORDER); constant("#define _THREAD_SIZE ", THREAD_SIZE); + constant("#define _THREAD_MASK ", THREAD_MASK); linefeed; } @@ -211,8 +212,14 @@ void output_mm_defines(void) offset("#define MM_CONTEXT ", struct mm_struct, context); linefeed; constant("#define _PAGE_SIZE ", PAGE_SIZE); + constant("#define _PAGE_SHIFT ", PAGE_SHIFT); + linefeed; constant("#define _PGD_ORDER ", PGD_ORDER); constant("#define _PGDIR_SHIFT ", PGDIR_SHIFT); + constant("#define _PMD_SHIFT ", PMD_SHIFT); + linefeed; + constant("#define _PTRS_PER_PGD ", PTRS_PER_PGD); + constant("#define _PTRS_PER_PMD ", PTRS_PER_PMD); linefeed; } diff --git a/arch/mips/kernel/pci-dma.c b/arch/mips/kernel/pci-dma.c index 6bf6beeeafd..0bcdad3980d 100644 --- a/arch/mips/kernel/pci-dma.c +++ b/arch/mips/kernel/pci-dma.c @@ -16,6 +16,10 @@ #include +#ifndef UNCAC_BASE /* Hack ... */ +#define UNCAC_BASE 0x9000000000000000UL +#endif + void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t * dma_handle, int gfp) { diff --git a/arch/mips/kernel/reg.c b/arch/mips/kernel/reg.c new file mode 100644 index 00000000000..8367292fd7b --- /dev/null +++ b/arch/mips/kernel/reg.c @@ -0,0 +1,69 @@ +/* + * offset.c: Calculate pt_regs and task_struct indices. + * + * Copyright (C) 1996 David S. Miller + * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle + */ +#include +#include +#include +#include + +#include +#include + +#define text(t) __asm__("\n@@@" t) +#define _offset(type, member) ((unsigned long) &(((type *)NULL)->member)) +#define index(string, ptr, member) \ + __asm__("\n@@@" string "%0" : : "i" (_offset(ptr, member)/sizeof(long))) +#define size(string, size) \ + __asm__("\n@@@" string "%0" : : "i" (sizeof(size))) +#define linefeed text("") + +void output_ptreg_defines(void) +{ + text("/* MIPS pt_regs indices. */"); + index("#define EF_R0 ", struct pt_regs, regs[0]); + index("#define EF_R1 ", struct pt_regs, regs[1]); + index("#define EF_R2 ", struct pt_regs, regs[2]); + index("#define EF_R3 ", struct pt_regs, regs[3]); + index("#define EF_R4 ", struct pt_regs, regs[4]); + index("#define EF_R5 ", struct pt_regs, regs[5]); + index("#define EF_R6 ", struct pt_regs, regs[6]); + index("#define EF_R7 ", struct pt_regs, regs[7]); + index("#define EF_R8 ", struct pt_regs, regs[8]); + index("#define EF_R9 ", struct pt_regs, regs[9]); + index("#define EF_R10 ", struct pt_regs, regs[10]); + index("#define EF_R11 ", struct pt_regs, regs[11]); + index("#define EF_R12 ", struct pt_regs, regs[12]); + index("#define EF_R13 ", struct pt_regs, regs[13]); + index("#define EF_R14 ", struct pt_regs, regs[14]); + index("#define EF_R15 ", struct pt_regs, regs[15]); + index("#define EF_R16 ", struct pt_regs, regs[16]); + index("#define EF_R17 ", struct pt_regs, regs[17]); + index("#define EF_R18 ", struct pt_regs, regs[18]); + index("#define EF_R19 ", struct pt_regs, regs[19]); + index("#define EF_R20 ", struct pt_regs, regs[20]); + index("#define EF_R21 ", struct pt_regs, regs[21]); + index("#define EF_R22 ", struct pt_regs, regs[22]); + index("#define EF_R23 ", struct pt_regs, regs[23]); + index("#define EF_R24 ", struct pt_regs, regs[24]); + index("#define EF_R25 ", struct pt_regs, regs[25]); + index("#define EF_R26 ", struct pt_regs, regs[26]); + index("#define EF_R27 ", struct pt_regs, regs[27]); + index("#define EF_R28 ", struct pt_regs, regs[28]); + index("#define EF_R29 ", struct pt_regs, regs[29]); + index("#define EF_R30 ", struct pt_regs, regs[30]); + index("#define EF_R31 ", struct pt_regs, regs[31]); + linefeed; + index("#define EF_LO ", struct pt_regs, lo); + index("#define EF_HI ", struct pt_regs, hi); + linefeed; + index("#define EF_EPC ", struct pt_regs, cp0_epc); + index("#define EF_BVADDR ", struct pt_regs, cp0_badvaddr); + index("#define EF_STATUS ", struct pt_regs, cp0_status); + index("#define EF_CAUSE ", struct pt_regs, cp0_cause); + linefeed; + size("#define EF_SIZE ", struct pt_regs); + linefeed; +} diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index f0b7457044f..ae2a9ce3295 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -20,7 +20,7 @@ #include /* Highest syscall used of any syscall flavour */ -#define MAX_SYSCALL_NO __NR_Linux + __NR_Linux_syscalls +#define MAX_SYSCALL_NO __NR_O32_Linux + __NR_O32_Linux_syscalls .align 5 NESTED(handle_sys, PT_SIZE, sp) @@ -260,7 +260,7 @@ bad_alignment: LEAF(sys_syscall) lw t0, PT_R29(sp) # user sp - sltu v0, a0, __NR_Linux + __NR_Linux_syscalls + 1 + sltu v0, a0, __NR_O32_Linux + __NR_O32_Linux_syscalls + 1 beqz v0, enosys sll v0, a0, 2 diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 242e539abb1..297404c2311 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -39,14 +39,14 @@ NESTED(handle_sys64, PT_SIZE, sp) ld t1, PT_EPC(sp) # skip syscall on return FEXPORT(__handle_sys64) - subu t0, v0, __NR_Linux # check syscall number - sltiu t0, t0, __NR_Linux_syscalls + 1 + subu t0, v0, __NR_64_Linux # check syscall number + sltiu t0, t0, __NR_64_Linux_syscalls + 1 daddiu t1, 4 # skip to next instruction beqz t0, illegal_syscall sd t1, PT_EPC(sp) dsll t0, v0, 3 # offset into table - ld t2, (sys_call_table - (__NR_Linux * 8))(t0) + ld t2, (sys_call_table - (__NR_64_Linux * 8))(t0) # syscall routine sd a3, PT_R26(sp) # save a3 for syscall restarting diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 335ecdf215c..f1b5a848a56 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index b0a8b4f2336..5048c66b4bb 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -16,18 +16,24 @@ #include #include #include -#include #include #include #include #include -#include +#include #include #include #include #include +/* + * Including #include #include -#include +#include #include #include #include #include +/* + * Including #include #include +#include #include #include #include diff --git a/arch/mips/mm-64/tlbex-r4k.S b/arch/mips/mm-64/tlbex-r4k.S index 63a783593f5..76cb601ffba 100644 --- a/arch/mips/mm-64/tlbex-r4k.S +++ b/arch/mips/mm-64/tlbex-r4k.S @@ -13,10 +13,11 @@ #include #include #include -#include #include #include +#define _VMALLOC_START 0xc000000000000000 + /* * After this macro runs we have a pointer to the pte of the address * that caused the fault in PTR. @@ -32,13 +33,13 @@ #endif bltz \tmp, \kaddr ld \ptr, (\ptr) - dsrl \tmp, (PGDIR_SHIFT-3) # get pgd offset in bytes - andi \tmp, ((PTRS_PER_PGD - 1)<<3) + dsrl \tmp, (_PGDIR_SHIFT-3) # get pgd offset in bytes + andi \tmp, ((_PTRS_PER_PGD - 1)<<3) daddu \ptr, \tmp # add in pgd offset dmfc0 \tmp, CP0_BADVADDR ld \ptr, (\ptr) # get pmd pointer - dsrl \tmp, (PMD_SHIFT-3) # get pmd offset in bytes - andi \tmp, ((PTRS_PER_PMD - 1)<<3) + dsrl \tmp, (_PMD_SHIFT-3) # get pmd offset in bytes + andi \tmp, ((_PTRS_PER_PMD - 1)<<3) daddu \ptr, \tmp # add in pmd offset dmfc0 \tmp, CP0_XCONTEXT ld \ptr, (\ptr) # get pte pointer @@ -55,14 +56,14 @@ * First, determine that the address is in/above vmalloc range. */ dmfc0 \tmp, CP0_BADVADDR - dli \ptr, VMALLOC_START + dli \ptr, _VMALLOC_START /* * Now find offset into kptbl. */ dsubu \tmp, \tmp, \ptr dla \ptr, kptbl - dsrl \tmp, (PAGE_SHIFT+1) # get vpn2 + dsrl \tmp, (_PAGE_SHIFT+1) # get vpn2 dsll \tmp, 4 # byte offset of pte daddu \ptr, \ptr, \tmp @@ -111,7 +112,7 @@ LEAF(except_vec1_sb1) dmfc0 k0, CP0_BADVADDR dmfc0 k1, CP0_ENTRYHI xor k0, k1 - dsrl k0, k0, PAGE_SHIFT+1 + dsrl k0, k0, _PAGE_SHIFT+1 bnez k0, 1f #endif .set noat diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index 6d73190d229..451ad0d9f75 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -38,31 +38,6 @@ #define dpf_reg(r) (regs->regs[r]) /* - * Unlock any spinlocks which will prevent us from getting the out - */ -void bust_spinlocks(int yes) -{ - int loglevel_save = console_loglevel; - - if (yes) { - oops_in_progress = 1; - return; - } -#ifdef CONFIG_VT - unblank_screen(); -#endif - oops_in_progress = 0; - /* - * OK, the message is on the console. Now we call printk() - * without oops_in_progress set so that printk will give klogd - * a poke. Hold onto your hats... - */ - console_loglevel = 15; /* NMI oopser may have shut the console up */ - printk(" "); - console_loglevel = loglevel_save; -} - -/* * This routine handles page faults. It determines the address, * and the problem, and then passes it off to one of the appropriate * routines. diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c index 1dfe2ddfe97..d6a2bfa0574 100644 --- a/arch/mips/mm/ioremap.c +++ b/arch/mips/mm/ioremap.c @@ -172,7 +172,7 @@ void * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags) #define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == KSEG1) -void iounmap(void *addr) +void __iounmap(void *addr) { struct vm_struct *p; @@ -190,4 +190,4 @@ void iounmap(void *addr) } EXPORT_SYMBOL(__ioremap); -EXPORT_SYMBOL(iounmap); +EXPORT_SYMBOL(__iounmap); diff --git a/arch/mips/vmlinux.lds.S b/arch/mips/vmlinux.lds.S index 7fef4b274fe..2efca322928 100644 --- a/arch/mips/vmlinux.lds.S +++ b/arch/mips/vmlinux.lds.S @@ -1,10 +1,27 @@ #include +#undef mips /* CPP really sucks for this job */ +#define mips mips OUTPUT_ARCH(mips) ENTRY(kernel_entry) -jiffies = JIFFIES32; +jiffies = JIFFIES; SECTIONS { +#ifdef CONFIG_BOOT_ELF64 + /* Read-only sections, merged into text segment: */ + /* . = 0xc000000000000000; */ + + /* This is the value for an Origin kernel, taken from an IRIX kernel. */ + /* . = 0xc00000000001c000; */ + + /* Set the vaddr for the text segment to a value + >= 0xa800 0000 0001 9000 if no symmon is going to configured + >= 0xa800 0000 0030 0000 otherwise */ + + /* . = 0xa800000000300000; */ + /* . = 0xa800000000300000; */ + . = 0xffffffff80300000; +#endif . = LOADADDR; /* read-only */ _text = .; /* Text and read-only data */ @@ -64,7 +81,13 @@ SECTIONS _edata = .; /* End of data section */ +#ifdef CONFIG_MIPS32 . = ALIGN(8192); /* init_task */ +#endif +#ifdef CONFIG_MIPS64 + . = ALIGN(16384); /* init_task */ +#endif + . = . + MAPPED_OFFSET; /* for CONFIG_MAPPED_KERNEL */ .data.init_task : { *(.data.init_task) } /* will be freed after init */ diff --git a/arch/mips64/.cvsignore b/arch/mips64/.cvsignore deleted file mode 100644 index ef09ae635f7..00000000000 --- a/arch/mips64/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -.*.cmd -vmlinux.lds.s diff --git a/arch/mips64/Kconfig b/arch/mips64/Kconfig deleted file mode 100644 index 7c3d8bb0a46..00000000000 --- a/arch/mips64/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# -config MIPS - bool - default y - -config MIPS32 - bool - default n - -config MIPS64 - bool - default y - -source "arch/mips/Kconfig-shared" diff --git a/arch/mips64/Makefile b/arch/mips64/Makefile deleted file mode 100644 index 3c5e2671bb4..00000000000 --- a/arch/mips64/Makefile +++ /dev/null @@ -1,493 +0,0 @@ -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Copyright (C) 1994, 1995, 1996 by Ralf Baechle -# DECStation modifications by Paul M. Antoine, 1996 -# Copyright (C) 2002 Maciej W. Rozycki -# -# This file is included by the global makefile so that you can add your own -# architecture-specific flags and dependencies. Remember to do have actions -# for "archclean" cleaning up for this architecture. -# - -# -# Select the object file format to substitute into the linker script. -# -ifdef CONFIG_CPU_LITTLE_ENDIAN -tool-prefix = mips64el-linux- -32bit-bfd = elf32-tradlittlemips -64bit-bfd = elf64-tradlittlemips -else -tool-prefix = mips64-linux- -32bit-bfd = elf32-tradbigmips -64bit-bfd = elf64-tradbigmips -endif - -ifdef CONFIG_CROSSCOMPILE -CROSS_COMPILE := $(tool-prefix) -endif - -# -# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel -# code since it only slows down the whole thing. At some point we might make -# use of global pointer optimizations but their use of $28 conflicts with -# the current pointer optimization. -# -# The DECStation requires an ECOFF kernel for remote booting, other MIPS -# machines may also. Since BFD is incredibly buggy with respect to -# crossformat linking we rely on the elf2ecoff tool for format conversion. -# -cflags-y := -I $(TOPDIR)/include/asm/gcc -cflags-y += -G 0 -mno-abicalls -fno-pic -Wa,--trap -pipe -cflags-$(CONFIG_MIPS64) += -mabi=64 -Wa,--trap -LDFLAGS_vmlinux += -G 0 -static # -N -MODFLAGS += -mlong-calls - -cflags-$(CONFIG_KGDB) += -g -cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer - -check_gcc = $(shell if $(AS) $(1) -o /dev/null -xc /dev/null > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi) -check_warning = $(shell if $(CC) $(1) -c -o /dev/null -xc /dev/null > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi) - -# -# CPU-dependent compiler/assembler options for optimization. -# -cflags-$(CONFIG_CPU_R4300) += -mcpu=r4300 -mips3 -cflags-$(CONFIG_CPU_R4X00) += -mcpu=r4600 -mips3 -cflags-$(CONFIG_CPU_R5000) += -mcpu=r8000 -mips4 -cflags-$(CONFIG_CPU_NEVADA) += -mcpu=r8000 -mips3 -mmad -cflags-$(CONFIG_CPU_RM7000) += $(call check_gcc, -mcpu=r7000, -mcpu=r5000) \ - -mips4 -cflags-$(CONFIG_CPU_SB1) += $(call check_gcc, -mcpu=sb1, -mcpu=r8000) \ - $(call check_gcc, -mips64, -mips4) -cflags-$(CONFIG_CPU_R8000) += -mcpu=r8000 -mips4 -cflags-$(CONFIG_CPU_R10000) += -mcpu=r8000 -mips4 -ifdef CONFIG_CPU_SB1 -ifdef CONFIG_SB1_PASS_1_WORKAROUNDS -MODFLAGS += -msb1-pass1-workarounds -endif -endif -# Should be used then we get a MIPS64 compiler -#cflags-$(CONFIG_CPU_MIPS64) += -mips64 -cflags-$(CONFIG_CPU_MIPS64) += -mcpu=r8000 -mips4 - -# -# ramdisk/initrd support -# You need a compressed ramdisk image, named ramdisk.gz in -# arch/mips/ramdisk -# -ifdef CONFIG_EMBEDDED_RAMDISK -CORE_FILES += arch/mips/ramdisk/ramdisk.o -SUBDIRS += arch/mips/ramdisk -endif - -# -# Firmware support -# -libs-$(CONFIG_ARC) += arch/mips/arc/ -libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ - -# -# Board-dependent options and extra files -# - -# -# Acer PICA 61, Mips Magnum 4000 and Olivetti M700. -# -core-$(CONFIG_MIPS_JAZZ) += arch/mips/jazz/ -load-$(CONFIG_MIPS_JAZZ) += 0x80080000 - - -# -# Au1500 (Alchemy Semi PB1500) eval board -# -core-$(CONFIG_MIPS_PB1500) += arch/mips/au1000/common/ -libs-$(CONFIG_MIPS_PB1500) += arch/mips/au1000/pb1500/ -load-$(CONFIG_MIPS_PB1500) += 0x80100000 - -# -# Baget/MIPS -# -libs-$(CONFIG_BAGET_MIPS) += arch/mips/baget/ arch/mips/baget/prom/ -load-$(CONFIG_BAGET_MIPS) += 0x80001000 - -# -# Cobalt Server -# -core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/ -load-$(CONFIG_MIPS_COBALT) += 0x80080000 - -# -# DECstation family -# -core-$(CONFIG_DECSTATION) += arch/mips/dec/ -libs-$(CONFIG_DECSTATION) += arch/mips/dec/prom/ -load-$(CONFIG_DECSTATION) += 0x80040000 -CLEAN_FILES += drivers/tc/lk201-map.c - -# -# Galileo EV64120 Board -# -core-$(CONFIG_MIPS_EV64120) += arch/mips/galileo-boards/ev64120/ -load-$(CONFIG_MIPS_EV64120) += 0x80100000 - -# -# Galileo EV96100 Board -# -core-$(CONFIG_MIPS_EV96100) += arch/mips/galileo-boards/generic/ \ - arch/mips/galileo-boards/ev96100/ -load-$(CONFIG_MIPS_EV96100) += 0x80100000 - -# -# Globespan IVR eval board with QED 5231 CPU -# -core-$(CONFIG_ITE_BOARD_GEN) += arch/mips/ite-boards/generic/ -core-$(CONFIG_MIPS_IVR) += arch/mips/ite-boards/ivr/ -load-$(CONFIG_MIPS_IVR) += 0x80100000 - -# -# HP LaserJet -# -core-$(CONFIG_HP_LASERJET) += arch/mips/hp-lj/ -load-$(CONFIG_HP_LASERJET) += 0x80030000 - -# -# ITE 8172 eval board with QED 5231 CPU -# -core-$(CONFIG_MIPS_ITE8172) += arch/mips/ite-boards/qed-4n-s01b/ -load-$(CONFIG_MIPS_ITE8172) += 0x80100000 - -# -# MIPS Atlas board -# -core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/ -core-$(CONFIG_MIPS_ATLAS) += arch/mips/mips-boards/atlas/ -load-$(CONFIG_MIPS_ATLAS) += 0x80100000 - -# -# MIPS Malta board -# -core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/ -load-$(CONFIG_MIPS_MALTA) += 0x80100000 - -# -# MIPS SEAD board -# -core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/ -load-$(CONFIG_MIPS_SEAD) += 0x80100000 - -# -# Momentum Ocelot board -# -# The Ocelot setup.o must be linked early - it does the ioremap() for the -# mips_io_port_base. -# -core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \ - arch/mips/gt64120/momenco_ocelot/ -load-$(CONFIG_MOMENCO_OCELOT) += 0x80100000 - -# -# Momentum Ocelot-G board -# -# The Ocelot-G setup.o must be linked early - it does the ioremap() for the -# mips_io_port_base. -# -core-$(CONFIG_MOMENCO_OCELOT_G) += arch/mips/momentum/ocelot_g/ -load-$(CONFIG_MOMENCO_OCELOT_G) += 0x80100000 - -# -# Momentum Ocelot-C and -CS boards -# -# The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the -# mips_io_port_base. -core-$(CONFIG_MOMENCO_OCELOT_C) += arch/mips/momentum/ocelot_c/ -load-$(CONFIG_MOMENCO_OCELOT_C) += 0x80100000 - -# -# NEC DDB Vrc-5074 -# -core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ -core-$(CONFIG_DDB5074) += arch/mips/ddb5xxx/ddb5074/ -load-$(CONFIG_DDB5074) += 0x80080000 - -# -# NEC DDB Vrc-5476 -# -core-$(CONFIG_DDB5476) += arch/mips/ddb5xxx/ddb5476/ -load-$(CONFIG_DDB5476) += 0x80080000 - -# -# NEC DDB Vrc-5477 -# -core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/ -load-$(CONFIG_DDB5477) += 0x80100000 - -core-$(CONFIG_LASAT) += arch/mips/lasat/ -load-$(CONFIG_LASAT) += 0x80000000 - -# -# NEC Osprey (vr4181) board -# -core-$(CONFIG_NEC_OSPREY) += arch/mips/vr4181/common/ \ - arch/mips/vr4181/osprey/ -load-$(CONFIG_NEC_OSPREY) += 0x80002000 - -# -# NEC Eagle/Hawk (VR4122/VR4131) board -# -core-$(CONFIG_VR41XX_COMMON) += arch/mips/vr41xx/common/ -core-$(CONFIG_NEC_EAGLE) += arch/mips/vr41xx/nec-eagle/ -load-$(CONFIG_NEC_EAGLE) += 0x80000000 - -# -# ZAO Networks Capcella (VR4131) -# -core-$(CONFIG_ZAO_CAPCELLA) += arch/mips/vr41xx/zao-capcella/ -load-$(CONFIG_ZAO_CAPCELLA) += 0x80000000 - -# -# Victor MP-C303/304 (VR4122) -# -core-$(CONFIG_VICTOR_MPC30X) += arch/mips/vr41xx/victor-mpc30x/ -load-$(CONFIG_VICTOR_MPC30X) += 0x80001000 - -# -# IBM WorkPad z50 (VR4121) -# -core-$(CONFIG_IBM_WORKPAD) += arch/mips/vr41xx/ibm-workpad/ -load-$(CONFIG_IBM_WORKPAD) += 0x80004000 - -# -# CASIO CASSIPEIA E-55/65 (VR4111) -# -core-$(CONFIG_CASIO_E55) += arch/mips/vr41xx/casio-e55/ -load-$(CONFIG_CASIO_E55) += 0x80004000 - -# -# TANBAC TB0226 Mbase (VR4131) -# -core-$(CONFIG_TANBAC_TB0226) += arch/mips/vr41xx/tanbac-tb0226/ -load-$(CONFIG_TANBAC_TB0226) += 0x80000000 - -# -# TANBAC TB0229 VR4131DIMM (VR4131) -# -core-$(CONFIG_TANBAC_TB0229) += arch/mips/vr41xx/tanbac-tb0229/ -load-$(CONFIG_TANBAC_TB0229) += 0x80000000 - -# -# SGI IP22 (Indy/Indigo2) -# -# Set the load address to >= 0x88069000 if you want to leave space for symmon, -# 0x88004000 for production kernels. Note that the value must be 16kb aligned -# or the handling of the current variable will break. -# -core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/ -load-$(CONFIG_SGI_IP22) += 0x88004000 - -# -# SGI-IP27 (Origin200/2000) -# -# Set the load address to >= 0xc000000000300000 if you want to leave space for -# symmon, 0xc00000000001c000 for production kernels. Note that the value -# must be 16kb aligned or the handling of the current variable will break. -# -ifdef CONFIG_SGI_IP27 -core-$(CONFIG_SGI_IP27) += arch/mips/sgi-ip27/ -#load-$(CONFIG_SGI_IP27) += 0xa80000000001c000 -ifdef CONFIG_MAPPED_KERNEL -load-$(CONFIG_SGI_IP27) += 0xc001c000 -else -load-$(CONFIG_SGI_IP27) += 0x8001c000 -endif -endif - -# -# SGI-IP32 (O2) -# -# Set the load address to >= 0x????????? if you want to leave space for symmon, -# 0x80002000 for production kernels. Note that the value must be 16kb aligned -# or the handling of the current variable will break. -# -core-$(CONFIG_SGI_IP32) += arch/mips/sgi-ip32/ -load-$(CONFIG_SGI_IP32) += 0x80002000 - -# -# Sibyte SB1250 SOC -# -# This is a LIB so that it links at the end, and initcalls are later -# the sequence; but it is built as an object so that modules don't get -# removed (as happens, even if they have __initcall/module_init) -# -core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/ -ifdef CONFIG_SIBYTE_BCM112X -ifdef CONFIG_MIPS_UNCACHED -load-y += 0xa0100000 -else -load-y += 0x80100000 -endif -endif -ifdef CONFIG_SIBYTE_SB1250 -ifdef CONFIG_MIPS_UNCACHED -load-y += 0xa0100000 -else -load-y += 0x80100000 -endif -endif - -# -# Sibyte BCM91120x (Carmel) board -# Sibyte BCM91120C (CRhine) board -# Sibyte BCM91125C (CRhone) board -# Sibyte BCM91125E (Rhone) board -# Sibyte SWARM board -# -libs-$(CONFIG_SIBYTE_CARMEL) += arch/mips/sibyte/swarm/ -load-$(CONFIG_SIBYTE_CARMEL) := 0x80100000 -libs-$(CONFIG_SIBYTE_CRHINE) += arch/mips/sibyte/swarm/ -load-$(CONFIG_SIBYTE_CRHINE) := 0x80100000 -libs-$(CONFIG_SIBYTE_CRHONE) += arch/mips/sibyte/swarm/ -load-$(CONFIG_SIBYTE_CRHONE) := 0x80100000 -libs-$(CONFIG_SIBYTE_RHONE) += arch/mips/sibyte/swarm/ -load-$(CONFIG_SIBYTE_RHONE) := 0x80100000 -libs-$(CONFIG_SIBYTE_SENTOSA) += arch/mips/sibyte/swarm/ -load-$(CONFIG_SIBYTE_SENTOSA) := 0x80100000 -libs-$(CONFIG_SIBYTE_SWARM) += arch/mips/sibyte/swarm/ -load-$(CONFIG_SIBYTE_SWARM) := 0x80100000 - -# -# SNI RM200 PCI -# -core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/ -load-$(CONFIG_SNI_RM200_PCI) += 0x80080000 - -# -# Toshiba JMR-TX3927 board -# -core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/jmr3927/rbhma3100/ \ - arch/mips/jmr3927/common/ -load-$(CONFIG_TOSHIBA_JMR3927) += 0x80050000 - -# -# Toshiba RBTX4927 board or -# Toshiba RBTX4937 board -# -core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/ -core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ -load-$(CONFIG_TOSHIBA_RBTX4927) += 0x80020000 - -drivers-$(CONFIG_PCI) += arch/mips/pci/ - -# -# Some machines like the Indy need 32-bit ELF binaries for booting purposes. -# Other need ECOFF, so we build a 32-bit ELF binary for them which we then -# convert to ECOFF using elf2ecoff. -# -# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit -# ELF files from 32-bit files by conversion. -# -#AS += -64 -#LDFLAGS += -m elf64bmip -cflags-$(CONFIG_BOOT_ELF32) += -Wa,-32 -cflags-$(CONFIG_BOOT_ELF64) += -Wa,-32 - -GRRR=-Wa,-mgp64 -cflags-$(CONFIG_BOOT_ELF32) += -Wa,-32 $(call check_warning, $(GRRR),) -cflags-$(CONFIG_BOOT_ELF64) += -Wa,-32 $(call check_warning, $(GRRR),) - -AFLAGS_vmlinux.lds.o := -imacros $(srctree)/include/asm-mips64/sn/mapped_kernel.h \ - -D"LOADADDR=$(load-y)" - -AFLAGS += $(cflags-y) -CFLAGS += $(cflags-y) - -LDFLAGS += --oformat $(32bit-bfd) -LDFLAGS_BLOB := --format binary --oformat $(64bit-bfd) - -head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o - -libs-y += arch/mips/lib/ -libs-$(CONFIG_MIPS32) += arch/mips/lib-32/ -libs-$(CONFIG_MIPS64) += arch/mips/lib-64/ - -core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ -core-$(CONFIG_MIPS32) += arch/mips/mm-32/ -core-$(CONFIG_MIPS64) += arch/mips/mm-64/ - -ifdef CONFIG_BAGET_MIPS - -BAGETBOOT = $(MAKE) -C arch/$(ARCH)/baget - -balo: vmlinux - $(BAGETBOOT) balo - -endif - -ifdef CONFIG_LASAT -rom.bin rom.sw: vmlinux - $(call descend,arch/mips/lasat/image,$@) -endif - -ifdef CONFIG_MAPPED_KERNEL -vmlinux.64: vmlinux - $(OBJCOPY) -O $(64bit-bfd) --change-addresses=0xbfffffff40000000 $< $@ -else -vmlinux.64: vmlinux - $(OBJCOPY) -O $(64bit-bfd) --change-addresses=0xa7ffffff80000000 $< $@ -endif - -makeboot =$(Q)$(MAKE) -f scripts/Makefile.build obj=arch/mips/boot $(1) - -# -# SNI firmware is f*cked in interesting ways ... -# -ifdef CONFIG_SNI_RM200_PCI -all: vmlinux.rm200 -endif - -vmlinux.ecoff vmlinux.rm200: vmlinux - +@$(call makeboot,$@) - -CLEAN_FILES += vmlinux.ecoff \ - vmlinux.rm200.tmp \ - vmlinux.rm200 - -archclean: - @$(MAKE) -f scripts/Makefile.clean obj=arch/mips/boot - @$(MAKE) -f scripts/Makefile.clean obj=arch/mips/baget - @$(MAKE) -f scripts/Makefile.clean obj=arch/mips/lasat - -# Generate - -#undef mips /* CPP really sucks for this job */ -#define mips mips -OUTPUT_ARCH(mips) -ENTRY(kernel_entry) -jiffies = jiffies_64; -SECTIONS -{ -#ifdef CONFIG_BOOT_ELF64 - /* Read-only sections, merged into text segment: */ - /* . = 0xc000000000000000; */ - - /* This is the value for an Origin kernel, taken from an IRIX kernel. */ - /* . = 0xc00000000001c000; */ - - /* Set the vaddr for the text segment to a value - >= 0xa800 0000 0001 9000 if no symmon is going to configured - >= 0xa800 0000 0030 0000 otherwise */ - - /* . = 0xa800000000300000; */ - /* . = 0xa800000000300000; */ - . = 0xffffffff80300000; -#endif - . = LOADADDR; - /* read-only */ - _text = .; /* Text and read-only data */ - .text : { - *(.text) - *(.fixup) - *(.gnu.warning) - } =0 - - _etext = .; /* End of text section */ - - . = ALIGN(16); /* Exception table */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - __start___dbe_table = .; /* Exception table for data bus errors */ - __dbe_table : { *(__dbe_table) } - __stop___dbe_table = .; - - RODATA - - . = ALIGN(64); - - /* writeable */ - .data : { /* Data */ - *(.data) - - /* Align the initial ramdisk image (INITRD) on page boundaries. */ - . = ALIGN(4096); - __rd_start = .; - *(.initrd) - . = ALIGN(4096); - __rd_end = .; - - CONSTRUCTORS - } - _gp = . + 0x8000; - .lit8 : { *(.lit8) } - .lit4 : { *(.lit4) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { *(.sdata) } - - . = ALIGN(4096); - __nosave_begin = .; - .data_nosave : { *(.data.nosave) } - . = ALIGN(4096); - __nosave_end = .; - - . = ALIGN(4096); - .data.page_aligned : { *(.data.idt) } - - . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } - - _edata = .; /* End of data section */ - - . = ALIGN(16384); /* init_task */ - . = . + MAPPED_OFFSET; /* for CONFIG_MAPPED_KERNEL */ - .data.init_task : { *(.data.init_task) } - - /* will be freed after init */ - . = ALIGN(4096); /* Init code and data */ - __init_begin = .; - /* /DISCARD/ doesn't work for .reginfo */ - .reginfo : { *(.reginfo) } - .init.text : { - _sinittext = .; - *(.init.text) - _einittext = .; - } - .init.data : { *(.init.data) } - . = ALIGN(16); - __setup_start = .; - .init.setup : { *(.init.setup) } - __setup_end = .; - __start___param = .; - __param : { *(__param) } - __stop___param = .; - __initcall_start = .; - .initcall.init : { - *(.initcall1.init) - *(.initcall2.init) - *(.initcall3.init) - *(.initcall4.init) - *(.initcall5.init) - *(.initcall6.init) - *(.initcall7.init) - } - __initcall_end = .; - __con_initcall_start = .; - .con_initcall.init : { *(.con_initcall.init) } - __con_initcall_end = .; - SECURITY_INIT - . = ALIGN(4096); - __initramfs_start = .; - .init.ramfs : { *(.init.ramfs) } - __initramfs_end = .; - . = ALIGN(32); - __per_cpu_start = .; - .data.percpu : { *(.data.percpu) } - __per_cpu_end = .; - . = ALIGN(4096); - __init_end = .; - /* freed after init ends here */ - - __bss_start = .; /* BSS */ - .sbss : { - *(.sbss) - *(.scommon) - } - .bss : { - *(.bss) - *(COMMON) - } - __bss_stop = .; - - _end = . ; - - /* Sections to be discarded */ - /DISCARD/ : { - *(.exit.text) - *(.exit.data) - *(.exitcall.exit) - } - - /* This is the MIPS specific mdebug section. */ - .mdebug : { *(.mdebug) } - /* These are needed for ELF backends which have not yet been - converted to the new style linker. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - /* DWARF debug sections. - Symbols in the .debug DWARF section are relative to the beginning of the - section so we begin .debug at 0. It's not clear yet what needs to happen - for the others. */ - .debug 0 : { *(.debug) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .line 0 : { *(.line) } - /* These must appear regardless of . */ - .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } - .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - .comment : { *(.comment) } - .note : { *(.note) } -} diff --git a/drivers/net/sgiseeq.c b/drivers/net/sgiseeq.c index d5f56eabd06..e3b6dee2c2d 100644 --- a/drivers/net/sgiseeq.c +++ b/drivers/net/sgiseeq.c @@ -177,7 +177,7 @@ static int seeq_init_ring(struct net_device *dev) if (!buffer) return -ENOMEM; ib->tx_desc[i].buf_vaddr = KSEG1ADDR(buffer); - ib->tx_desc[i].tdma.pbuf = PHYSADDR(buffer); + ib->tx_desc[i].tdma.pbuf = virt_to_bus(buffer); } ib->tx_desc[i].tdma.cntinfo = (TCNTINFO_INIT); } @@ -191,7 +191,7 @@ static int seeq_init_ring(struct net_device *dev) if (!buffer) return -ENOMEM; ib->rx_desc[i].buf_vaddr = KSEG1ADDR(buffer); - ib->rx_desc[i].rdma.pbuf = PHYSADDR(buffer); + ib->rx_desc[i].rdma.pbuf = virt_to_bus(buffer); } ib->rx_desc[i].rdma.cntinfo = (RCNTINFO_INIT); } @@ -268,8 +268,8 @@ static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp, hregs->rx_dconfig |= RDMACFG_INIT; - hregs->rx_ndptr = PHYSADDR(&sp->srings.rx_desc[0]); - hregs->tx_ndptr = PHYSADDR(&sp->srings.tx_desc[0]); + hregs->rx_ndptr = virt_to_bus(sp->srings.rx_desc); + hregs->tx_ndptr = virt_to_bus(sp->srings.tx_desc); seeq_go(sp, hregs, sregs); return 0; @@ -294,7 +294,7 @@ static inline void rx_maybe_restart(struct sgiseeq_private *sp, struct sgiseeq_regs *sregs) { if (!(hregs->rx_ctrl & HPC3_ERXCTRL_ACTIVE)) { - hregs->rx_ndptr = PHYSADDR(&sp->srings.rx_desc[sp->rx_new]); + hregs->rx_ndptr = virt_to_bus(sp->srings.rx_desc + sp->rx_new); seeq_go(sp, hregs, sregs); } } @@ -376,7 +376,7 @@ static inline void kick_tx(struct sgiseeq_tx_desc *td, (HPCDMA_XIU | HPCDMA_ETXD)) td = (struct sgiseeq_tx_desc *)(long) KSEG1ADDR(td->tdma.pnext); if (td->tdma.cntinfo & HPCDMA_XIU) { - hregs->tx_ndptr = PHYSADDR(td); + hregs->tx_ndptr = virt_to_bus(td); hregs->tx_ctrl = HPC3_ETXCTRL_ACTIVE; } } @@ -409,7 +409,7 @@ static inline void sgiseeq_tx(struct net_device *dev, struct sgiseeq_private *sp break; if (!(td->tdma.cntinfo & (HPCDMA_ETXD))) { if (!(status & HPC3_ETXCTRL_ACTIVE)) { - hregs->tx_ndptr = PHYSADDR(td); + hregs->tx_ndptr = virt_to_bus(td); hregs->tx_ctrl = HPC3_ETXCTRL_ACTIVE; } break; @@ -579,11 +579,11 @@ static inline void setup_tx_ring(struct sgiseeq_tx_desc *buf, int nbufs) int i = 0; while (i < (nbufs - 1)) { - buf[i].tdma.pnext = PHYSADDR(&buf[i + 1]); + buf[i].tdma.pnext = virt_to_bus(buf + i + 1); buf[i].tdma.pbuf = 0; i++; } - buf[i].tdma.pnext = PHYSADDR(&buf[0]); + buf[i].tdma.pnext = virt_to_bus(buf); } static inline void setup_rx_ring(struct sgiseeq_rx_desc *buf, int nbufs) @@ -591,12 +591,12 @@ static inline void setup_rx_ring(struct sgiseeq_rx_desc *buf, int nbufs) int i = 0; while (i < (nbufs - 1)) { - buf[i].rdma.pnext = PHYSADDR(&buf[i + 1]); + buf[i].rdma.pnext = virt_to_bus(buf + i + 1); buf[i].rdma.pbuf = 0; i++; } buf[i].rdma.pbuf = 0; - buf[i].rdma.pnext = PHYSADDR(&buf[0]); + buf[i].rdma.pnext = virt_to_bus(buf); } #define ALIGNED(x) ((((unsigned long)(x)) + 0xf) & ~(0xf)) diff --git a/drivers/scsi/sgiwd93.c b/drivers/scsi/sgiwd93.c index ea20ff07fc7..86cbb93df53 100644 --- a/drivers/scsi/sgiwd93.c +++ b/drivers/scsi/sgiwd93.c @@ -91,7 +91,7 @@ void fill_hpc_entries (struct hpc_chunk **hcp, char *addr, unsigned long len) unsigned long physaddr; unsigned long count; - physaddr = PHYSADDR(addr); + physaddr = virt_to_bus(addr); while (len) { /* * even cntinfo could be up to 16383, without @@ -145,7 +145,7 @@ static int dma_setup(Scsi_Cmnd *cmd, int datainp) #endif /* Start up the HPC. */ - hregs->ndptr = PHYSADDR(hdata->dma_bounce_buffer); + hregs->ndptr = virt_to_bus(hdata->dma_bounce_buffer); if(datainp) { dma_cache_inv((unsigned long) cmd->SCp.ptr, cmd->SCp.this_residual); hregs->ctrl = (HPC3_SCTRL_ACTIVE); @@ -202,13 +202,13 @@ static inline void init_hpc_chain(uchar *buf) start = (unsigned long) buf; end = start + PAGE_SIZE; while(start < end) { - hcp->desc.pnext = PHYSADDR((hcp + 1)); + hcp->desc.pnext = virt_to_bus((hcp + 1)); hcp->desc.cntinfo = HPCDMA_EOX; hcp++; start += sizeof(struct hpc_chunk); }; hcp--; - hcp->desc.pnext = PHYSADDR(buf); + hcp->desc.pnext = virt_to_bus(buf); /* Force flush to memory */ dma_cache_wback_inv((unsigned long) buf, PAGE_SIZE); diff --git a/include/asm-mips/.cvsignore b/include/asm-mips/.cvsignore index cd157aea989..7337c06a461 100644 --- a/include/asm-mips/.cvsignore +++ b/include/asm-mips/.cvsignore @@ -1 +1,2 @@ offset.h +reg.h diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h dissimilarity index 76% index c50f2aa24ee..e42b3093e90 100644 --- a/include/asm-mips/a.out.h +++ b/include/asm-mips/a.out.h @@ -1,26 +1,47 @@ -#ifndef __ASM_MIPS_A_OUT_H -#define __ASM_MIPS_A_OUT_H - -struct exec -{ - unsigned long a_info; /* Use macros N_MAGIC, etc for access */ - unsigned a_text; /* length of text, in bytes */ - unsigned a_data; /* length of data, in bytes */ - unsigned a_bss; /* length of uninitialized data area for file, in bytes */ - unsigned a_syms; /* length of symbol table data in file, in bytes */ - unsigned a_entry; /* start address */ - unsigned a_trsize; /* length of relocation info for text, in bytes */ - unsigned a_drsize; /* length of relocation info for data, in bytes */ -}; - -#define N_TRSIZE(a) ((a).a_trsize) -#define N_DRSIZE(a) ((a).a_drsize) -#define N_SYMSIZE(a) ((a).a_syms) - -#ifdef __KERNEL__ - -#define STACK_TOP TASK_SIZE - -#endif - -#endif /* __ASM_MIPS_A_OUT_H */ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2003 by Ralf Baechle + */ +#ifndef _ASM_A_OUT_H +#define _ASM_A_OUT_H + +#ifdef __KERNEL__ + +#include + +#endif + +struct exec +{ + unsigned long a_info; /* Use macros N_MAGIC, etc for access */ + unsigned a_text; /* length of text, in bytes */ + unsigned a_data; /* length of data, in bytes */ + unsigned a_bss; /* length of uninitialized data area for + file, in bytes */ + unsigned a_syms; /* length of symbol table data in file, + in bytes */ + unsigned a_entry; /* start address */ + unsigned a_trsize; /* length of relocation info for text, in + bytes */ + unsigned a_drsize; /* length of relocation info for data, in bytes */ +}; + +#define N_TRSIZE(a) ((a).a_trsize) +#define N_DRSIZE(a) ((a).a_drsize) +#define N_SYMSIZE(a) ((a).a_syms) + +#ifdef __KERNEL__ + +#ifdef CONFIG_MIPS32 +#define STACK_TOP TASK_SIZE +#endif +#ifdef CONFIG_MIPS64 +#define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE) +#endif + +#endif + +#endif /* _ASM_A_OUT_H */ diff --git a/include/asm-mips64/addrspace.h b/include/asm-mips/addrspace.h similarity index 69% rename from include/asm-mips64/addrspace.h rename to include/asm-mips/addrspace.h index 19cdd947e5c..ec5cb629bf9 100644 --- a/include/asm-mips64/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -3,12 +3,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1999 by Ralf Baechle + * Copyright (C) 1996, 99 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. - * Copyright (C) 2002 Maciej W. Rozycki */ -#ifndef __ASM_ADDRSPACE_H -#define __ASM_ADDRSPACE_H +#ifndef _ASM_ADDRSPACE_H +#define _ASM_ADDRSPACE_H #include @@ -38,27 +38,26 @@ /* * Memory segments (32bit kernel mode addresses) + * These are the traditional names used in the 32-bit universe. */ -#define KUSEG 0x0000000000000000 -#define KSEG0 0xffffffff80000000 -#define KSEG1 0xffffffffa0000000 -#define KSEG2 0xffffffffc0000000 -#define KSEG3 0xffffffffe0000000 +#define KUSEG 0x00000000 +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 +#define KSEG2 0xc0000000 +#define KSEG3 0xe0000000 + +//#define K0BASE KSEG0 /* * Returns the kernel segment base of a given address */ -#define KSEGX(a) ((_ACAST64_ (a)) & 0xffffffffe0000000) +#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) /* - * Returns the physical address of a KSEG0/KSEG1 address + * Returns the physical address of a CKSEGx / XKPHYS address */ -#define XPHYSADDR(a) ((_ACAST64_ (a)) & 0x000000ffffffffff) -#define CPHYSADDR(a) ((_ACAST64_ (a)) & 0x000000001fffffff) - -#define PHYSADDR(a) ({ \ - const _ATYPE64_ _a = _ACAST64_ (a); \ - _a == _ACAST32_ _a ? CPHYSADDR(_a) : XPHYSADDR(_a); }) +#define CPHYSADDR(a) ((_ACAST32_ (a)) & 0x1fffffff) +#define XPHYSADDR(a) ((_ACAST64_ (a)) & 0x000000ffffffffff) /* * Map an address to a certain kernel segment @@ -68,8 +67,15 @@ #define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) #define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) +#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) + /* * Memory segments (64bit kernel mode addresses) + * The compatibility segments use the full 64-bit sign extended value. Note + * the R8000 doesn't have them so don't reference these in generic MIPS code. */ #define XKUSEG 0x0000000000000000 #define XKSSEG 0x4000000000000000 @@ -80,6 +86,26 @@ #define CKSSEG 0xffffffffc0000000 #define CKSEG3 0xffffffffe0000000 +/* + * Cache modes for XKPHYS address conversion macros + */ +#define K_CALG_COH_EXCL1_NOL2 0 +#define K_CALG_COH_SHRL1_NOL2 1 +#define K_CALG_UNCACHED 2 +#define K_CALG_NONCOHERENT 3 +#define K_CALG_COH_EXCL 4 +#define K_CALG_COH_SHAREABLE 5 +#define K_CALG_NOTUSED 6 +#define K_CALG_UNCACHED_ACCEL 7 + +/* + * 64-bit address conversions + */ +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) +#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) +#define PHYS_TO_XKPHYS(cm,a) (0x8000000000000000 | ((cm)<<59) | (a)) + #if defined (CONFIG_CPU_R4300) \ || defined (CONFIG_CPU_R4X00) \ || defined (CONFIG_CPU_R5000) \ @@ -122,7 +148,7 @@ #define KUBASE 0 #define KUSIZE_32 0x0000000080000000 /* KUSIZE for a 32 bit proc */ -#define K0BASE 0xa800000000000000 +//#define K0BASE 0xa800000000000000 #define K0BASE_EXL_WR K0BASE /* exclusive on write */ #define K0BASE_NONCOH 0x9800000000000000 /* noncoherent */ #define K0BASE_EXL 0xa000000000000000 /* exclusive */ @@ -143,4 +169,4 @@ #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) #define PHYS_TO_K0(x) (_ACAST64_ (x) | K0BASE) -#endif /* __ASM_ADDRSPACE_H */ +#endif /* _ASM_ADDRSPACE_H */ diff --git a/include/asm-mips64/arc/hinv.h b/include/asm-mips/arc/hinv.h similarity index 100% rename from include/asm-mips64/arc/hinv.h rename to include/asm-mips/arc/hinv.h diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h index 95df7fbde74..e2f08891cf1 100644 --- a/include/asm-mips/asm.h +++ b/include/asm-mips/asm.h @@ -3,8 +3,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 1996, 1997 by Ralf Baechle - * Copyright (C) 2002 Maciej W. Rozycki + * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle + * Copyright (C) 1999 by Silicon Graphics, Inc. + * Copyright (C) 2001 MIPS Technologies, Inc. * * Some useful macros for MIPS assembler code * @@ -12,8 +13,8 @@ * away by gas in -O mode. These nops are however required to fill delay * slots in noreorder mode. */ -#ifndef __ASM_ASM_H -#define __ASM_ASM_H +#ifndef _ASM_ASM_H +#define _ASM_ASM_H #include #include @@ -136,7 +137,7 @@ symbol = value * MIPS IV implementations are free to treat this as a nop. The R5000 * is one of them. So we should have an option not to use this instruction. */ -#if CONFIG_CPU_HAS_PREFETCH +#ifdef CONFIG_CPU_HAS_PREFETCH #define PREF(hint,addr) \ .set push; \ @@ -397,4 +398,4 @@ symbol = value #define SSNOP sll zero,zero,1 -#endif /* __ASM_ASM_H */ +#endif /* _ASM_ASM_H */ diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro-32.h similarity index 90% copy from include/asm-mips/asmmacro.h copy to include/asm-mips/asmmacro-32.h index f98fee4c3a7..98b46645ea2 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro-32.h @@ -4,8 +4,8 @@ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1998, 1999, 2003 Ralf Baechle */ -#ifndef _ASM_ASMMACRO_H -#define _ASM_ASMMACRO_H +#ifndef _ASM_ASMMACRO_32_H +#define _ASM_ASMMACRO_32_H #include #include @@ -13,35 +13,6 @@ #include #include - .macro local_irq_enable reg=t0 - mfc0 \reg, CP0_STATUS - ori \reg, \reg, 1 - mtc0 \reg, CP0_STATUS - .endm - - .macro local_irq_disable reg=t0 - mfc0 \reg, CP0_STATUS - ori \reg, \reg, 1 - xori \reg, \reg, 1 - mtc0 \reg, CP0_STATUS - SSNOP; SSNOP; SSNOP - .endm - -#ifdef CONFIG_CPU_SB1 - .macro fpu_enable_hazard - .set push - .set noreorder - .set mips2 - SSNOP - bnezl $0, .+4 - SSNOP - .set pop - .endm -#else - .macro fpu_enable_hazard - .endm -#endif - .macro fpu_save_double thread tmp=t0 cfc1 \tmp, fcr31 sdc1 $f0, THREAD_FPR0(\thread) @@ -185,4 +156,4 @@ LONG_L ra, THREAD_REG31(\thread) .endm -#endif /* _ASM_ASMMACRO_H */ +#endif /* _ASM_ASMMACRO_32_H */ diff --git a/include/asm-mips64/asmmacro.h b/include/asm-mips/asmmacro-64.h similarity index 87% rename from include/asm-mips64/asmmacro.h rename to include/asm-mips/asmmacro-64.h index d5a7390df84..abc38322045 100644 --- a/include/asm-mips64/asmmacro.h +++ b/include/asm-mips/asmmacro-64.h @@ -5,8 +5,8 @@ * Copyright (C) 1998, 1999 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. */ -#ifndef _ASM_ASMMACRO_H -#define _ASM_ASMMACRO_H +#ifndef _ASM_ASMMACRO_64_H +#define _ASM_ASMMACRO_64_H #include #include @@ -14,35 +14,6 @@ #include #include - .macro local_irq_enable reg=t0 - mfc0 \reg, CP0_STATUS - ori \reg, \reg, 1 - mtc0 \reg, CP0_STATUS - .endm - - .macro local_irq_disable reg=t0 - mfc0 \reg, CP0_STATUS - ori \reg, \reg, 1 - xori \reg, \reg, 1 - mtc0 \reg, CP0_STATUS - SSNOP; SSNOP; SSNOP - .endm - -#ifdef CONFIG_CPU_SB1 - .macro fpu_enable_hazard - .set push - .set noreorder - .set mips2 - SSNOP - bnezl $0, .+4 - SSNOP - .set pop - .endm -#else - .macro fpu_enable_hazard - .endm -#endif - .macro fpu_save_16even thread tmp=t0 cfc1 \tmp, fcr31 sdc1 $f2, THREAD_FPR2(\thread) @@ -149,4 +120,4 @@ LONG_L ra, THREAD_REG31(\thread) .endm -#endif /* _ASM_ASMMACRO_H */ +#endif /* _ASM_ASMMACRO_64_H */ diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h dissimilarity index 89% index f98fee4c3a7..c70f00d8336 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h @@ -1,188 +1,49 @@ -/* - * asmmacro.h: Assembler macros to make things easier to read. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1998, 1999, 2003 Ralf Baechle - */ -#ifndef _ASM_ASMMACRO_H -#define _ASM_ASMMACRO_H - -#include -#include -#include -#include -#include - - .macro local_irq_enable reg=t0 - mfc0 \reg, CP0_STATUS - ori \reg, \reg, 1 - mtc0 \reg, CP0_STATUS - .endm - - .macro local_irq_disable reg=t0 - mfc0 \reg, CP0_STATUS - ori \reg, \reg, 1 - xori \reg, \reg, 1 - mtc0 \reg, CP0_STATUS - SSNOP; SSNOP; SSNOP - .endm - -#ifdef CONFIG_CPU_SB1 - .macro fpu_enable_hazard - .set push - .set noreorder - .set mips2 - SSNOP - bnezl $0, .+4 - SSNOP - .set pop - .endm -#else - .macro fpu_enable_hazard - .endm -#endif - - .macro fpu_save_double thread tmp=t0 - cfc1 \tmp, fcr31 - sdc1 $f0, THREAD_FPR0(\thread) - sdc1 $f2, THREAD_FPR2(\thread) - sdc1 $f4, THREAD_FPR4(\thread) - sdc1 $f6, THREAD_FPR6(\thread) - sdc1 $f8, THREAD_FPR8(\thread) - sdc1 $f10, THREAD_FPR10(\thread) - sdc1 $f12, THREAD_FPR12(\thread) - sdc1 $f14, THREAD_FPR14(\thread) - sdc1 $f16, THREAD_FPR16(\thread) - sdc1 $f18, THREAD_FPR18(\thread) - sdc1 $f20, THREAD_FPR20(\thread) - sdc1 $f22, THREAD_FPR22(\thread) - sdc1 $f24, THREAD_FPR24(\thread) - sdc1 $f26, THREAD_FPR26(\thread) - sdc1 $f28, THREAD_FPR28(\thread) - sdc1 $f30, THREAD_FPR30(\thread) - sw \tmp, THREAD_FCR31(\thread) - .endm - - .macro fpu_save_single thread tmp=t0 - cfc1 \tmp, fcr31 - swc1 $f0, THREAD_FPR0(\thread) - swc1 $f1, THREAD_FPR1(\thread) - swc1 $f2, THREAD_FPR2(\thread) - swc1 $f3, THREAD_FPR3(\thread) - swc1 $f4, THREAD_FPR4(\thread) - swc1 $f5, THREAD_FPR5(\thread) - swc1 $f6, THREAD_FPR6(\thread) - swc1 $f7, THREAD_FPR7(\thread) - swc1 $f8, THREAD_FPR8(\thread) - swc1 $f9, THREAD_FPR9(\thread) - swc1 $f10, THREAD_FPR10(\thread) - swc1 $f11, THREAD_FPR11(\thread) - swc1 $f12, THREAD_FPR12(\thread) - swc1 $f13, THREAD_FPR13(\thread) - swc1 $f14, THREAD_FPR14(\thread) - swc1 $f15, THREAD_FPR15(\thread) - swc1 $f16, THREAD_FPR16(\thread) - swc1 $f17, THREAD_FPR17(\thread) - swc1 $f18, THREAD_FPR18(\thread) - swc1 $f19, THREAD_FPR19(\thread) - swc1 $f20, THREAD_FPR20(\thread) - swc1 $f21, THREAD_FPR21(\thread) - swc1 $f22, THREAD_FPR22(\thread) - swc1 $f23, THREAD_FPR23(\thread) - swc1 $f24, THREAD_FPR24(\thread) - swc1 $f25, THREAD_FPR25(\thread) - swc1 $f26, THREAD_FPR26(\thread) - swc1 $f27, THREAD_FPR27(\thread) - swc1 $f28, THREAD_FPR28(\thread) - swc1 $f29, THREAD_FPR29(\thread) - swc1 $f30, THREAD_FPR30(\thread) - swc1 $f31, THREAD_FPR31(\thread) - sw \tmp, THREAD_FCR31(\thread) - .endm - - .macro fpu_restore_double thread tmp=t0 - lw \tmp, THREAD_FCR31(\thread) - ldc1 $f0, THREAD_FPR0(\thread) - ldc1 $f2, THREAD_FPR2(\thread) - ldc1 $f4, THREAD_FPR4(\thread) - ldc1 $f6, THREAD_FPR6(\thread) - ldc1 $f8, THREAD_FPR8(\thread) - ldc1 $f10, THREAD_FPR10(\thread) - ldc1 $f12, THREAD_FPR12(\thread) - ldc1 $f14, THREAD_FPR14(\thread) - ldc1 $f16, THREAD_FPR16(\thread) - ldc1 $f18, THREAD_FPR18(\thread) - ldc1 $f20, THREAD_FPR20(\thread) - ldc1 $f22, THREAD_FPR22(\thread) - ldc1 $f24, THREAD_FPR24(\thread) - ldc1 $f26, THREAD_FPR26(\thread) - ldc1 $f28, THREAD_FPR28(\thread) - ldc1 $f30, THREAD_FPR30(\thread) - ctc1 \tmp, fcr31 - .endm - - .macro fpu_restore_single thread tmp=t0 - lw \tmp, THREAD_FCR31(\thread) - lwc1 $f0, THREAD_FPR0(\thread) - lwc1 $f1, THREAD_FPR1(\thread) - lwc1 $f2, THREAD_FPR2(\thread) - lwc1 $f3, THREAD_FPR3(\thread) - lwc1 $f4, THREAD_FPR4(\thread) - lwc1 $f5, THREAD_FPR5(\thread) - lwc1 $f6, THREAD_FPR6(\thread) - lwc1 $f7, THREAD_FPR7(\thread) - lwc1 $f8, THREAD_FPR8(\thread) - lwc1 $f9, THREAD_FPR9(\thread) - lwc1 $f10, THREAD_FPR10(\thread) - lwc1 $f11, THREAD_FPR11(\thread) - lwc1 $f12, THREAD_FPR12(\thread) - lwc1 $f13, THREAD_FPR13(\thread) - lwc1 $f14, THREAD_FPR14(\thread) - lwc1 $f15, THREAD_FPR15(\thread) - lwc1 $f16, THREAD_FPR16(\thread) - lwc1 $f17, THREAD_FPR17(\thread) - lwc1 $f18, THREAD_FPR18(\thread) - lwc1 $f19, THREAD_FPR19(\thread) - lwc1 $f20, THREAD_FPR20(\thread) - lwc1 $f21, THREAD_FPR21(\thread) - lwc1 $f22, THREAD_FPR22(\thread) - lwc1 $f23, THREAD_FPR23(\thread) - lwc1 $f24, THREAD_FPR24(\thread) - lwc1 $f25, THREAD_FPR25(\thread) - lwc1 $f26, THREAD_FPR26(\thread) - lwc1 $f27, THREAD_FPR27(\thread) - lwc1 $f28, THREAD_FPR28(\thread) - lwc1 $f29, THREAD_FPR29(\thread) - lwc1 $f30, THREAD_FPR30(\thread) - lwc1 $f31, THREAD_FPR31(\thread) - ctc1 \tmp, fcr31 - .endm - - .macro cpu_save_nonscratch thread - LONG_S s0, THREAD_REG16(\thread) - LONG_S s1, THREAD_REG17(\thread) - LONG_S s2, THREAD_REG18(\thread) - LONG_S s3, THREAD_REG19(\thread) - LONG_S s4, THREAD_REG20(\thread) - LONG_S s5, THREAD_REG21(\thread) - LONG_S s6, THREAD_REG22(\thread) - LONG_S s7, THREAD_REG23(\thread) - LONG_S sp, THREAD_REG29(\thread) - LONG_S fp, THREAD_REG30(\thread) - .endm - - .macro cpu_restore_nonscratch thread - LONG_L s0, THREAD_REG16(\thread) - LONG_L s1, THREAD_REG17(\thread) - LONG_L s2, THREAD_REG18(\thread) - LONG_L s3, THREAD_REG19(\thread) - LONG_L s4, THREAD_REG20(\thread) - LONG_L s5, THREAD_REG21(\thread) - LONG_L s6, THREAD_REG22(\thread) - LONG_L s7, THREAD_REG23(\thread) - LONG_L sp, THREAD_REG29(\thread) - LONG_L fp, THREAD_REG30(\thread) - LONG_L ra, THREAD_REG31(\thread) - .endm - -#endif /* _ASM_ASMMACRO_H */ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef _ASM_ASMMACRO_H +#define _ASM_ASMMACRO_H + +#include + +#ifdef CONFIG_MIPS32 +#include +#endif +#ifdef CONFIG_MIPS64 +#include +#endif + + .macro local_irq_enable reg=t0 + mfc0 \reg, CP0_STATUS + ori \reg, \reg, 1 + mtc0 \reg, CP0_STATUS + .endm + + .macro local_irq_disable reg=t0 + mfc0 \reg, CP0_STATUS + ori \reg, \reg, 1 + xori \reg, \reg, 1 + mtc0 \reg, CP0_STATUS + SSNOP; SSNOP; SSNOP + .endm + +#ifdef CONFIG_CPU_SB1 + .macro fpu_enable_hazard + .set push + .set noreorder + .set mips2 + SSNOP + bnezl $0, .+4 + SSNOP + .set pop + .endm +#else + .macro fpu_enable_hazard + .endm +#endif + +#endif /* _ASM_ASMMACRO_H */ diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index b7675395b47..dbf13e7bb1a 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -9,10 +9,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1997, 2000 by Ralf Baechle + * Copyright (C) 1996, 1997, 1999, 2000 by Ralf Baechle */ -#ifndef __ASM_ATOMIC_H -#define __ASM_ATOMIC_H +#ifndef _ASM_ATOMIC_H +#define _ASM_ATOMIC_H #include @@ -129,12 +129,12 @@ static __inline__ void atomic_add(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - "1: ll %0, %1 # atomic_add\n" - " addu %0, %2 \n" - " sc %0, %1 \n" - " beqz %0, 1b \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); + "1: ll %0, %1 # atomic_add \n" + " addu %0, %2 \n" + " sc %0, %1 \n" + " beqz %0, 1b \n" + : "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter)); } /* @@ -150,12 +150,14 @@ static __inline__ void atomic_sub(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - "1: ll %0, %1 # atomic_sub\n" - " subu %0, %2 \n" - " sc %0, %1 \n" - " beqz %0, 1b \n" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); + " .set noreorder # atomic_sub \n" + "1: ll %0, %1 \n" + " subu %0, %2 \n" + " sc %0, %1 \n" + " beqz %0, 1b \n" + " .set reorder \n" + : "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter)); } /* @@ -166,18 +168,17 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) unsigned long temp, result; __asm__ __volatile__( - ".set push # atomic_add_return\n" - ".set noreorder \n" - "1: ll %1, %2 \n" - " addu %0, %1, %3 \n" - " sc %0, %2 \n" - " beqz %0, 1b \n" - " addu %0, %1, %3 \n" - " sync \n" - ".set pop \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); + " .set noreorder # atomic_add_return \n" + "1: ll %1, %2 \n" + " addu %0, %1, %3 \n" + " sc %0, %2 \n" + " beqz %0, 1b \n" + " addu %0, %1, %3 \n" + " sync \n" + " .set reorder \n" + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter) + : "memory"); return result; } @@ -187,18 +188,17 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) unsigned long temp, result; __asm__ __volatile__( - ".set push \n" - ".set noreorder # atomic_sub_return\n" - "1: ll %1, %2 \n" - " subu %0, %1, %3 \n" - " sc %0, %2 \n" - " beqz %0, 1b \n" - " subu %0, %1, %3 \n" - " sync \n" - ".set pop \n" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); + " .set noreorder # atomic_sub_return \n" + "1: ll %1, %2 \n" + " subu %0, %1, %3 \n" + " sc %0, %2 \n" + " beqz %0, 1b \n" + " subu %0, %1, %3 \n" + " sync \n" + " .set reorder \n" + : "=&r" (result), "=&r" (temp), "=m" (v->counter) + : "Ir" (i), "m" (v->counter) + : "memory"); return result; } @@ -279,4 +279,4 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) #endif /* defined(__KERNEL__) */ -#endif /* __ASM_ATOMIC_H */ +#endif /* _ASM_ATOMIC_H */ diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 7c9b6f51a9b..5befbf3df73 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -4,7 +4,7 @@ * for more details. * * Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org) - * Copyright (c) 2000 Silicon Graphics, Inc. + * Copyright (c) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_BITOPS_H #define _ASM_BITOPS_H @@ -17,9 +17,13 @@ #if (_MIPS_SZLONG == 32) #define SZLONG_LOG 5 #define SZLONG_MASK 31UL +#define __LL "ll" +#define __SC "sc" #elif (_MIPS_SZLONG == 64) #define SZLONG_LOG 6 -#define SZLONG_MASK 63UL +#define SZLONG_MASK 63UL +#define __LL "lld" +#define __SC "scd" #endif #ifdef __KERNEL__ @@ -67,18 +71,18 @@ * Note that @nr may be almost arbitrarily large; this function is not * restricted to acting on a single-word quantity. */ -static __inline__ void set_bit(int nr, volatile unsigned long *addr) +static inline void set_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( - "1:\tll\t%0, %1\t\t# set_bit\n\t" + "1:\t" __LL "\t%0, %1\t\t# set_bit\n\t" "or\t%0, %2\n\t" - "sc\t%0, %1\n\t" + __SC "\t%0, %1\n\t" "beqz\t%0, 1b" : "=&r" (temp), "=m" (*m) - : "ir" (1UL << (nr & 0x1f)), "m" (*m)); + : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } /* @@ -90,11 +94,11 @@ static __inline__ void set_bit(int nr, volatile unsigned long *addr) * If it's called on the same region of memory simultaneously, the effect * may be that only one operation succeeds. */ -static __inline__ void __set_bit(int nr, volatile unsigned long * addr) +static inline void __set_bit(unsigned long nr, volatile unsigned long * addr) { - unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - *m |= 1UL << (nr & 31); + *m |= 1UL << (nr & SZLONG_MASK); } /* @@ -107,18 +111,18 @@ static __inline__ void __set_bit(int nr, volatile unsigned long * addr) * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() * in order to ensure changes are visible on other processors. */ -static __inline__ void clear_bit(int nr, volatile unsigned long *addr) +static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( - "1:\tll\t%0, %1\t\t# clear_bit\n\t" + "1:\t" __LL "\t%0, %1\t\t# clear_bit\n\t" "and\t%0, %2\n\t" - "sc\t%0, %1\n\t" + __SC "\t%0, %1\n\t" "beqz\t%0, 1b\n\t" : "=&r" (temp), "=m" (*m) - : "ir" (~(1UL << (nr & 0x1f))), "m" (*m)); + : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); } /* @@ -130,34 +134,34 @@ static __inline__ void clear_bit(int nr, volatile unsigned long *addr) * If it's called on the same region of memory simultaneously, the effect * may be that only one operation succeeds. */ -static __inline__ void __clear_bit(int nr, volatile unsigned long * addr) +static inline void __clear_bit(unsigned long nr, volatile unsigned long * addr) { - unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - *m &= ~(1UL << (nr & 31)); + *m &= ~(1UL << (nr & SZLONG_MASK)); } /* * change_bit - Toggle a bit in memory - * @nr: Bit to clear + * @nr: Bit to change * @addr: Address to start counting from * * change_bit() is atomic and may not be reordered. * Note that @nr may be almost arbitrarily large; this function is not * restricted to acting on a single-word quantity. */ -static __inline__ void change_bit(int nr, volatile unsigned long *addr) +static inline void change_bit(unsigned long nr, volatile unsigned long *addr) { - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( - "1:\tll\t%0, %1\t\t# change_bit\n\t" + "1:\t" __LL "\t%0, %1\t\t# change_bit\n\t" "xor\t%0, %2\n\t" - "sc\t%0, %1\n\t" + __SC "\t%0, %1\n\t" "beqz\t%0, 1b" : "=&r" (temp), "=m" (*m) - : "ir" (1UL << (nr & 0x1f)), "m" (*m)); + : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); } /* @@ -169,11 +173,11 @@ static __inline__ void change_bit(int nr, volatile unsigned long *addr) * If it's called on the same region of memory simultaneously, the effect * may be that only one operation succeeds. */ -static __inline__ void __change_bit(int nr, volatile unsigned long * addr) +static inline void __change_bit(unsigned long nr, volatile unsigned long * addr) { - unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - *m ^= 1UL << (nr & 31); + *m ^= 1UL << (nr & SZLONG_MASK); } /* @@ -184,17 +188,17 @@ static __inline__ void __change_bit(int nr, volatile unsigned long * addr) * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ -static __inline__ int test_and_set_bit(int nr, volatile unsigned long *addr) +static inline int test_and_set_bit(unsigned long nr, + volatile unsigned long *addr) { - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); - unsigned long temp; - int res; + unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); + unsigned long temp, res; __asm__ __volatile__( ".set\tnoreorder\t\t# test_and_set_bit\n" - "1:\tll\t%0, %1\n\t" + "1:\t" __LL "\t%0, %1\n\t" "or\t%2, %0, %3\n\t" - "sc\t%2, %1\n\t" + __SC "\t%2, %1\n\t" "beqz\t%2, 1b\n\t" " and\t%2, %0, %3\n\t" #ifdef CONFIG_SMP @@ -202,7 +206,7 @@ static __inline__ int test_and_set_bit(int nr, volatile unsigned long *addr) #endif ".set\treorder" : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << (nr & 0x1f)), "m" (*m) + : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); return res != 0; @@ -217,14 +221,15 @@ static __inline__ int test_and_set_bit(int nr, volatile unsigned long *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static __inline__ int __test_and_set_bit(int nr, volatile unsigned long * addr) +static inline int __test_and_set_bit(unsigned long nr, + volatile unsigned long *addr) { volatile unsigned long *a = addr; unsigned long mask; int retval; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += nr >> SZLONG_LOG; + mask = 1 << (nr & SZLONG_MASK); retval = (mask & *a) != 0; *a |= mask; @@ -239,17 +244,18 @@ static __inline__ int __test_and_set_bit(int nr, volatile unsigned long * addr) * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ -static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr) +static inline int test_and_clear_bit(unsigned long nr, + volatile unsigned long *addr) { - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp, res; __asm__ __volatile__( ".set\tnoreorder\t\t# test_and_clear_bit\n" - "1:\tll\t%0, %1\n\t" + "1:\t" __LL "\t%0, %1\n\t" "or\t%2, %0, %3\n\t" "xor\t%2, %3\n\t" - "sc\t%2, %1\n\t" + __SC "\t%2, %1\n\t" "beqz\t%2, 1b\n\t" " and\t%2, %0, %3\n\t" #ifdef CONFIG_SMP @@ -257,7 +263,7 @@ static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr) #endif ".set\treorder" : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << (nr & 0x1f)), "m" (*m) + : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); return res != 0; @@ -272,15 +278,16 @@ static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static __inline__ int __test_and_clear_bit(int nr, +static inline int __test_and_clear_bit(unsigned long nr, volatile unsigned long * addr) { volatile unsigned long *a = addr; - unsigned long mask, retval; + unsigned long mask; + int retval; - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; + a += (nr >> SZLONG_LOG); + mask = 1UL << (nr & SZLONG_MASK); + retval = ((mask & *a) != 0); *a &= ~mask; return retval; @@ -294,16 +301,17 @@ static __inline__ int __test_and_clear_bit(int nr, * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ -static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr) +static inline int test_and_change_bit(unsigned long nr, + volatile unsigned long *addr) { - unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp, res; __asm__ __volatile__( ".set\tnoreorder\t\t# test_and_change_bit\n" - "1:\tll\t%0, %1\n\t" + "1:\t" __LL "\t%0, %1\n\t" "xor\t%2, %0, %3\n\t" - "sc\t%2, %1\n\t" + __SC "\t%2, %1\n\t" "beqz\t%2, 1b\n\t" " and\t%2, %0, %3\n\t" #ifdef CONFIG_SMP @@ -311,7 +319,7 @@ static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr) #endif ".set\treorder" : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << (nr & 0x1f)), "m" (*m) + : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) : "memory"); return res != 0; @@ -326,16 +334,16 @@ static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static __inline__ int __test_and_change_bit(int nr, +static inline int __test_and_change_bit(unsigned long nr, volatile unsigned long *addr) { volatile unsigned long *a = addr; unsigned long mask; int retval; - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; + a += (nr >> SZLONG_LOG); + mask = 1UL << (nr & SZLONG_MASK); + retval = ((mask & *a) != 0); *a ^= mask; return retval; @@ -353,14 +361,14 @@ static __inline__ int __test_and_change_bit(int nr, * Note that @nr may be almost arbitrarily large; this function is not * restricted to acting on a single-word quantity. */ -static __inline__ void set_bit(int nr, volatile unsigned long * addr) +static inline void set_bit(unsigned long nr, volatile unsigned long * addr) { volatile unsigned long *a = addr; unsigned long mask; __bi_flags; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += nr >> SZLONG_LOG; + mask = 1 << (nr & SZLONG_MASK); __bi_local_irq_save(flags); *a |= mask; __bi_local_irq_restore(flags); @@ -375,13 +383,13 @@ static __inline__ void set_bit(int nr, volatile unsigned long * addr) * If it's called on the same region of memory simultaneously, the effect * may be that only one operation succeeds. */ -static __inline__ void __set_bit(int nr, volatile unsigned long * addr) +static inline void __set_bit(unsigned long nr, volatile unsigned long * addr) { volatile unsigned long *a = addr; unsigned long mask; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += nr >> SZLONG_LOG; + mask = 1 << (nr & SZLONG_MASK); *a |= mask; } @@ -395,26 +403,26 @@ static __inline__ void __set_bit(int nr, volatile unsigned long * addr) * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() * in order to ensure changes are visible on other processors. */ -static __inline__ void clear_bit(int nr, volatile unsigned long * addr) +static inline void clear_bit(unsigned long nr, volatile unsigned long * addr) { volatile unsigned long *a = addr; unsigned long mask; __bi_flags; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += nr >> SZLONG_LOG; + mask = 1 << (nr & SZLONG_MASK); __bi_local_irq_save(flags); *a &= ~mask; __bi_local_irq_restore(flags); } -static __inline__ void __clear_bit(int nr, volatile unsigned long * addr) +static inline void __clear_bit(unsigned long nr, volatile unsigned long * addr) { volatile unsigned long *a = addr; unsigned long mask; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += nr >> SZLONG_LOG; + mask = 1 << (nr & SZLONG_MASK); *a &= ~mask; } @@ -427,14 +435,14 @@ static __inline__ void __clear_bit(int nr, volatile unsigned long * addr) * Note that @nr may be almost arbitrarily large; this function is not * restricted to acting on a single-word quantity. */ -static __inline__ void change_bit(int nr, volatile unsigned long * addr) +static inline void change_bit(unsigned long nr, volatile unsigned long * addr) { volatile unsigned long *a = addr; unsigned long mask; __bi_flags; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += nr >> SZLONG_LOG; + mask = 1 << (nr & SZLONG_MASK); __bi_local_irq_save(flags); *a ^= mask; __bi_local_irq_restore(flags); @@ -449,11 +457,11 @@ static __inline__ void change_bit(int nr, volatile unsigned long * addr) * If it's called on the same region of memory simultaneously, the effect * may be that only one operation succeeds. */ -static __inline__ void __change_bit(int nr, volatile unsigned long * addr) +static inline void __change_bit(unsigned long nr, volatile unsigned long * addr) { - unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - *m ^= 1UL << (nr & 31); + *m ^= 1UL << (nr & SZLONG_MASK); } /* @@ -464,15 +472,16 @@ static __inline__ void __change_bit(int nr, volatile unsigned long * addr) * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ -static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr) +static inline int test_and_set_bit(unsigned long nr, + volatile unsigned long * addr) { volatile unsigned long *a = addr; unsigned long mask; int retval; __bi_flags; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += nr >> SZLONG_LOG; + mask = 1 << (nr & SZLONG_MASK); __bi_local_irq_save(flags); retval = (mask & *a) != 0; *a |= mask; @@ -490,14 +499,15 @@ static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static __inline__ int __test_and_set_bit(int nr, volatile unsigned long * addr) +static inline int __test_and_set_bit(unsigned long nr, + volatile unsigned long *addr) { volatile unsigned long *a = addr; unsigned long mask; int retval; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += nr >> SZLONG_LOG; + mask = 1 << (nr & SZLONG_MASK); retval = (mask & *a) != 0; *a |= mask; @@ -512,15 +522,16 @@ static __inline__ int __test_and_set_bit(int nr, volatile unsigned long * addr) * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ -static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr) +static inline int test_and_clear_bit(unsigned long nr, + volatile unsigned long * addr) { volatile unsigned long *a = addr; unsigned long mask; int retval; __bi_flags; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += nr >> SZLONG_LOG; + mask = 1 << (nr & SZLONG_MASK); __bi_local_irq_save(flags); retval = (mask & *a) != 0; *a &= ~mask; @@ -538,16 +549,16 @@ static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static __inline__ int __test_and_clear_bit(int nr, +static inline int __test_and_clear_bit(unsigned long nr, volatile unsigned long * addr) { volatile unsigned long *a = addr; unsigned long mask; int retval; - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; + a += (nr >> SZLONG_LOG); + mask = 1UL << (nr & SZLONG_MASK); + retval = ((mask & *a) != 0); *a &= ~mask; return retval; @@ -561,14 +572,15 @@ static __inline__ int __test_and_clear_bit(int nr, * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ -static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr) +static inline int test_and_change_bit(unsigned long nr, + volatile unsigned long * addr) { volatile unsigned long *a = addr; unsigned long mask, retval; __bi_flags; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += nr >> SZLONG_LOG; + mask = 1 << (nr & SZLONG_MASK); __bi_local_irq_save(flags); retval = (mask & *a) != 0; *a ^= mask; @@ -586,15 +598,15 @@ static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static __inline__ int __test_and_change_bit(int nr, +static inline int __test_and_change_bit(unsigned long nr, volatile unsigned long * addr) { volatile unsigned long *a = addr; unsigned long mask; int retval; - a += nr >> 5; - mask = 1 << (nr & 0x1f); + a += (nr >> SZLONG_LOG); + mask = 1 << (nr & SZLONG_MASK); retval = (mask & *a) != 0; *a ^= mask; @@ -613,7 +625,7 @@ static __inline__ int __test_and_change_bit(int nr, * @nr: bit number to test * @addr: Address to start counting from */ -static inline int test_bit(int nr, const volatile unsigned long *addr) +static inline int test_bit(unsigned long nr, const volatile unsigned long *addr) { return 1UL & (((const volatile unsigned long *) addr)[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK)); } @@ -624,16 +636,26 @@ static inline int test_bit(int nr, const volatile unsigned long *addr) * * Undefined if no zero exists, so code should check against ~0UL first. */ -static __inline__ unsigned long ffz(unsigned long word) +static inline unsigned long ffz(unsigned long word) { int b = 0, s; word = ~word; +#ifdef CONFIG_MIPS32 s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s; s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s; s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s; s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s; s = 1; if (word << 31 != 0) s = 0; b += s; +#endif +#ifdef CONFIG_MIPS64 + s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s; + s = 16; if (word << 48 != 0) s = 0; b += s; word >>= s; + s = 8; if (word << 56 != 0) s = 0; b += s; word >>= s; + s = 4; if (word << 60 != 0) s = 0; b += s; word >>= s; + s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s; + s = 1; if (word << 63 != 0) s = 0; b += s; +#endif return b; } @@ -644,7 +666,7 @@ static __inline__ unsigned long ffz(unsigned long word) * * Undefined if no bit exists, so code should check against 0 first. */ -static __inline__ unsigned long __ffs(unsigned long word) +static inline unsigned long __ffs(unsigned long word) { return ffz(~word); } @@ -763,23 +785,30 @@ found_middle: /* * Every architecture must define this function. It's the fastest - * way of searching a 168-bit bitmap where the first 128 bits are - * unlikely to be set. It's guaranteed that at least one of the 168 + * way of searching a 140-bit bitmap where the first 100 bits are + * unlikely to be set. It's guaranteed that at least one of the 140 * bits is cleared. */ static inline int sched_find_first_bit(unsigned long *b) { +#ifdef CONFIG_MIPS32 if (unlikely(b[0])) return __ffs(b[0]); if (unlikely(b[1])) return __ffs(b[1]) + 32; if (unlikely(b[2])) return __ffs(b[2]) + 64; - if (unlikely(b[3])) + if (b[3]) return __ffs(b[3]) + 96; - if (b[4]) - return __ffs(b[4]) + 128; - return __ffs(b[5]) + 32 + 128; + return __ffs(b[4]) + 128; +#endif +#ifdef CONFIG_MIPS64 + if (unlikely(b[0])) + return __ffs(b[0]); + if (unlikely(b[1])) + return __ffs(b[1]) + 64; + return __ffs(b[2]) + 128; +#endif } /* @@ -800,9 +829,9 @@ static inline int sched_find_first_bit(unsigned long *b) * The Hamming Weight of a number is the total number of bits set in it. */ -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) static inline int __test_and_set_le_bit(unsigned long nr, unsigned long *addr) { @@ -858,15 +887,15 @@ static inline unsigned long ext2_ffz(unsigned int word) static inline unsigned long find_next_zero_le_bit(unsigned long *addr, unsigned long size, unsigned long offset) { - unsigned int *p = ((unsigned int *) addr) + (offset >> 5); - unsigned int result = offset & ~31; + unsigned int *p = ((unsigned int *) addr) + (offset >> SZLONG_LOG); + unsigned int result = offset & ~SZLONG_MASK; unsigned int tmp; if (offset >= size) return size; size -= result; - offset &= 31; + offset &= SZLONG_MASK; if (offset) { tmp = cpu_to_le32p(p++); tmp |= ~0U >> (32-offset); /* bug or feature ? */ diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index 445af5ec37e..d1fe9e5c62e 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h @@ -3,10 +3,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) by Ralf Baechle + * Copyright (C) 1996, 99, 2003 by Ralf Baechle */ -#ifndef _MIPS_BYTEORDER_H -#define _MIPS_BYTEORDER_H +#ifndef _ASM_BYTEORDER_H +#define _ASM_BYTEORDER_H #include @@ -27,4 +27,4 @@ # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" #endif -#endif /* _MIPS_BYTEORDER_H */ +#endif /* _ASM_BYTEORDER_H */ diff --git a/include/asm-mips64/cachectl.h b/include/asm-mips/cachectl.h similarity index 87% rename from include/asm-mips64/cachectl.h rename to include/asm-mips/cachectl.h index d33e91de558..f3ce721861d 100644 --- a/include/asm-mips64/cachectl.h +++ b/include/asm-mips/cachectl.h @@ -3,8 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle */ #ifndef _ASM_CACHECTL #define _ASM_CACHECTL diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index 91a2bed3669..c4a1ec31ff6 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h @@ -23,14 +23,14 @@ #define Hit_Invalidate_I 0x10 #define Hit_Invalidate_D 0x11 #define Hit_Writeback_Inv_D 0x15 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 /* * R4000-specific cacheops */ #define Create_Dirty_Excl_D 0x0d #define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 /* * R4000SC and R4400SC-specific cacheops diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h index 756e6a6429c..d0cb514e8c0 100644 --- a/include/asm-mips/checksum.h +++ b/include/asm-mips/checksum.h @@ -3,14 +3,19 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 1996, 1997, 1998, 2001 by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2001 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2001 Thiemo Seufer. + * Copyright (C) 2002 Maciej W. Rozycki */ #ifndef _ASM_CHECKSUM_H #define _ASM_CHECKSUM_H -#include +#include #include +#include + /* * computes the checksum of a memory block at buff, length len, * and adds in "sum" (32-bit) @@ -87,19 +92,18 @@ static inline unsigned short int csum_fold(unsigned int sum) static inline unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl) { - unsigned int sum; - unsigned long dummy; + unsigned int dummy, sum; /* - * This is for 32-bit MIPS processors. + * This is for 32-bit processors ... but works just fine for 64-bit + * processors for now ... XXX */ __asm__ __volatile__( ".set\tnoreorder\t\t\t# ip_fast_csum\n\t" ".set\tnoat\n\t" "lw\t%0, (%1)\n\t" "subu\t%2, 4\n\t" - "#blez\t%2, 2f\n\t" - " sll\t%2, 2\n\t" + "sll\t%2, 2\n\t" "lw\t%3, 4(%1)\n\t" "addu\t%2, %1\n\t" "addu\t%0, %3\n\t" @@ -133,14 +137,13 @@ static inline unsigned short ip_fast_csum(unsigned char *iph, * computes the checksum of the TCP/UDP pseudo-header * returns a 16-bit checksum, already complemented */ -static inline unsigned long csum_tcpudp_nofold(unsigned long saddr, - unsigned long daddr, - unsigned short len, - unsigned short proto, - unsigned int sum) +static inline unsigned int csum_tcpudp_nofold(unsigned int saddr, + unsigned int daddr, unsigned short len, unsigned short proto, + unsigned int sum) { __asm__( ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t" +#ifdef CONFIG_MIPS32 "addu\t%0, %2\n\t" "sltu\t$1, %0, %2\n\t" "addu\t%0, $1\n\t" @@ -152,6 +155,15 @@ static inline unsigned long csum_tcpudp_nofold(unsigned long saddr, "addu\t%0, %4\n\t" "sltu\t$1, %0, %4\n\t" "addu\t%0, $1\n\t" +#endif +#ifdef CONFIG_MIPS64 + "daddu\t%0, %2\n\t" + "daddu\t%0, %3\n\t" + "daddu\t%0, %4\n\t" + "dsll32\t$1, %0, 0\n\t" + "daddu\t%0, $1\n\t" + "dsrl32\t%0, %0, 0\n\t" +#endif ".set\tat" : "=r" (sum) : "0" (daddr), "r"(saddr), diff --git a/include/asm-mips64/compat.h b/include/asm-mips/compat.h similarity index 100% rename from include/asm-mips64/compat.h rename to include/asm-mips/compat.h diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h index 75142177974..93d7f858443 100644 --- a/include/asm-mips/dec/prom.h +++ b/include/asm-mips/dec/prom.h @@ -12,8 +12,8 @@ * * Based on arch/mips/dec/prom/prom.h by the Anonymous. */ -#ifndef __ASM_MIPS_DEC_PROM_H -#define __ASM_MIPS_DEC_PROM_H +#ifndef _ASM_DEC_PROM_H +#define _ASM_DEC_PROM_H #include @@ -166,4 +166,4 @@ extern void prom_meminit(u32); extern void prom_identify_arch(u32); extern void prom_init_cmdline(s32, s32 *, u32); -#endif /* __ASM_MIPS_DEC_PROM_H */ +#endif /* _ASM_DEC_PROM_H */ diff --git a/include/asm-mips64/delay.h b/include/asm-mips/delay.h similarity index 60% rename from include/asm-mips64/delay.h rename to include/asm-mips/delay.h index c32d4f835ad..91fdf79fd68 100644 --- a/include/asm-mips64/delay.h +++ b/include/asm-mips/delay.h @@ -4,7 +4,7 @@ * for more details. * * Copyright (C) 1994 by Waldorf Electronics - * Copyright (C) 1995 - 2000 by Ralf Baechle + * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_DELAY_H @@ -15,10 +15,18 @@ extern unsigned long loops_per_jiffy; -static __inline__ void -__delay(unsigned long loops) +static inline void __delay(unsigned long loops) { - __asm__ __volatile__ ( + if (sizeof(long) == 4) + __asm__ __volatile__ ( + ".set\tnoreorder\n" + "1:\tbnez\t%0,1b\n\t" + "subu\t%0,1\n\t" + ".set\treorder" + : "=r" (loops) + : "0" (loops)); + else if (sizeof(long) == 8) + __asm__ __volatile__ ( ".set\tnoreorder\n" "1:\tbnez\t%0,1b\n\t" "dsubu\t%0,1\n\t" @@ -27,6 +35,7 @@ __delay(unsigned long loops) :"0" (loops)); } + /* * Division by multiplication: you don't have to worry about * loss of precision. @@ -37,24 +46,35 @@ __delay(unsigned long loops) * first constant multiplications gets optimized away if the delay is * a constant) */ -static __inline__ void __udelay(unsigned long usecs, unsigned long lpj) + +static inline void __udelay(unsigned long usecs, unsigned long lpj) { unsigned long lo; /* * The common rates of 1000 and 128 are rounded wrongly by the - * catchall case. Excessive precission? Probably ... + * catchall case for 64-bit. Excessive precission? Probably ... */ -#if (HZ == 128) +#if defined(CONFIG_MIPS64) && (HZ == 128) usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */ -#elif (HZ == 1000) +#elif defined(CONFIG_MIPS64) && (HZ == 1000) usecs *= 0x004189374BC6A7f0UL; /* 2**64 / (1000000 / HZ) */ -#else +#elif defined(CONFIG_MIPS64) usecs *= (0x8000000000000000UL / (500000 / HZ)); +#else /* 32-bit junk follows here */ + usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) + + 0x80000000ULL) >> 32); #endif - __asm__("dmultu\t%2,%3" - :"=h" (usecs), "=l" (lo) - :"r" (usecs),"r" (lpj)); + + if (sizeof(long) == 4) + __asm__("multu\t%2, %3" + : "=h" (usecs), "=l" (lo) + : "r" (usecs),"r" (lpj)); + else if (sizeof(long) == 8) + __asm__("dmultu\t%2, %3" + : "=h" (usecs), "=l" (lo) + : "r" (usecs),"r" (lpj)); + __delay(usecs); } diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h index 6ef773a65ac..7e7e2ea0d6c 100644 --- a/include/asm-mips/div64.h +++ b/include/asm-mips/div64.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2000 Maciej W. Rozycki + * Copyright (C) 2000 Maciej W. Rozycki + * Copyright (C) 2003 Ralf Baechle * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -8,6 +9,8 @@ #ifndef _ASM_DIV64_H #define _ASM_DIV64_H +#if (_MIPS_SZLONG == 32) + /* * No traps on overflows for any of these... */ @@ -72,5 +75,50 @@ __quot = __quot << 32 | __low; \ (n) = __quot; \ __mod; }) +#endif /* (_MIPS_SZLONG == 32) */ + +#if (_MIPS_SZLONG == 64) + +/* + * Don't use this one in new code + */ +#define do_div64_32(res, high, low, base) ({ \ + unsigned int __quot, __mod; \ + unsigned long __div; \ + unsigned int __low, __high, __base; \ + \ + __high = (high); \ + __low = (low); \ + __div = __high; \ + __div = __div << 32 | __low; \ + __base = (base); \ + \ + __mod = __div % __base; \ + __div = __div / __base; \ + \ + __quot = __div; \ + (res) = __quot; \ + __mod; }) + +/* + * Hey, we're already 64-bit, no + * need to play games.. + */ +#define do_div(n, base) ({ \ + unsigned long __quot; \ + unsigned int __mod; \ + unsigned long __div; \ + unsigned int __base; \ + \ + __div = (n); \ + __base = (base); \ + \ + __mod = __div % __base; \ + __quot = __div / __base; \ + \ + (n) = __quot; \ + __mod; }) + +#endif /* (_MIPS_SZLONG == 64) */ #endif /* _ASM_DIV64_H */ diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h index eb21f821b94..6aaf9939a71 100644 --- a/include/asm-mips/dma.h +++ b/include/asm-mips/dma.h @@ -9,8 +9,8 @@ * as the R4030 on Jazz boards behave totally different! */ -#ifndef __ASM_MIPS_DMA_H -#define __ASM_MIPS_DMA_H +#ifndef _ASM_DMA_H +#define _ASM_DMA_H #include #include /* need byte IO */ @@ -302,10 +302,12 @@ static __inline__ int get_dma_residue(unsigned int dmanr) extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ extern void free_dma(unsigned int dmanr); /* release it again */ +/* From PCI */ + #ifdef CONFIG_PCI extern int isa_dma_bridge_buggy; #else -#define isa_dma_bridge_buggy (0) +#define isa_dma_bridge_buggy (0) #endif -#endif /* __ASM_MIPS_DMA_H */ +#endif /* _ASM_DMA_H */ diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index 2d5e51c1df1..e2df9ee000c 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -3,8 +3,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ -#ifndef __ASM_ELF_H -#define __ASM_ELF_H +#ifndef _ASM_ELF_H +#define _ASM_ELF_H + +#include /* ELF header e_flags defines. */ /* MIPS architecture level. */ @@ -110,6 +112,7 @@ #define SHF_MIPS_GPREL 0x10000000 +#ifndef ELF_ARCH /* ELF register definitions */ #define ELF_NGREG 45 #define ELF_NFPREG 33 @@ -120,6 +123,32 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef double elf_fpreg_t; typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; +#ifdef CONFIG_MIPS32 +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(hdr) \ +({ \ + int __res = 1; \ + struct elfhdr *__h = (hdr); \ + \ + if (__h->e_machine != EM_MIPS) \ + __res = 0; \ + if (__h->e_ident[EI_CLASS] != ELFCLASS64) \ + __res = 0; \ + \ + __res; \ +}) + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 + +#endif /* CONFIG_MIPS32 */ + +#ifdef CONFIG_MIPS64 + /* * This is used to ensure we don't load something for the wrong architecture. */ @@ -141,13 +170,16 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; __res; \ }) -/* This one accepts IRIX binaries. */ -#define irix_elf_check_arch(hdr) ((hdr)->e_machine == EM_MIPS) +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS64 + +#endif /* CONFIG_MIPS64 */ /* * These are used to set parameters in the core dumps. */ -#define ELF_CLASS ELFCLASS32 #ifdef __MIPSEB__ #define ELF_DATA ELFDATA2MSB #elif __MIPSEL__ @@ -155,6 +187,46 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #endif #define ELF_ARCH EM_MIPS +#endif /* !defined(ELF_ARCH) */ + +#ifdef __KERNEL__ + +#ifdef CONFIG_MIPS32 + +#define SET_PERSONALITY(ex, ibcs2) \ +do { \ + if (ibcs2) \ + set_personality(PER_SVR4); \ + set_personality(PER_LINUX); \ +} while (0) + +#endif /* CONFIG_MIPS32 */ + +#ifdef CONFIG_MIPS64 + +#define SET_PERSONALITY(ex, ibcs2) \ +do { current->thread.mflags &= ~MF_ABI_MASK; \ + if ((ex).e_ident[EI_CLASS] == ELFCLASS32) { \ + if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ + ((ex).e_flags & EF_MIPS_ABI) == 0) \ + current->thread.mflags |= MF_N32; \ + else \ + current->thread.mflags |= MF_O32; \ + } else \ + current->thread.mflags |= MF_N64; \ + if (ibcs2) \ + set_personality(PER_SVR4); \ + else if (current->personality != PER_LINUX32) \ + set_personality(PER_LINUX); \ +} while (0) + +#endif /* CONFIG_MIPS64 */ + +#endif /* __KERNEL__ */ + +/* This one accepts IRIX binaries. */ +#define irix_elf_check_arch(hdr) ((hdr)->e_machine == EM_MIPS) + #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 @@ -197,10 +269,8 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; the loader. We need to make sure that it is out of the way of the program that it will "exec", and that there is sufficient room for the brk. */ +#ifndef ELF_ET_DYN_BASE #define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) - -#ifdef __KERNEL__ -#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) #endif -#endif /* __ASM_ELF_H */ +#endif /* _ASM_ELF_H */ diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h index 29003d919e0..e2b9c0a2537 100644 --- a/include/asm-mips/fcntl.h +++ b/include/asm-mips/fcntl.h @@ -3,10 +3,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2003 Ralf Baechle */ -#ifndef __ASM_FCNTL_H -#define __ASM_FCNTL_H +#ifndef _ASM_FCNTL_H +#define _ASM_FCNTL_H /* open/fcntl - O_SYNC is only implemented on blocks devices and on files located on an ext2 file system */ @@ -43,9 +43,11 @@ #define F_SETSIG 10 /* for sockets. */ #define F_GETSIG 11 /* for sockets. */ +#ifndef __mips64 #define F_GETLK64 33 /* using 'struct flock64' */ #define F_SETLK64 34 #define F_SETLKW64 35 +#endif /* for F_[GET|SET]FL */ #define FD_CLOEXEC 1 /* actually anything with low bit set goes */ @@ -81,6 +83,8 @@ * contain all the same fields as struct flock. */ +#ifndef __mips64 + typedef struct flock { short l_type; short l_whence; @@ -99,6 +103,22 @@ typedef struct flock64 { pid_t l_pid; } flock64_t; +#else /* 64-bit definitions */ + +typedef struct flock { + short l_type; + short l_whence; + __kernel_off_t l_start; + __kernel_off_t l_len; + __kernel_pid_t l_pid; +} flock_t; + +#ifdef __KERNEL__ +#define flock64 flock +#endif + +#endif + #define F_LINUX_SPECIFIC_BASE 1024 -#endif /* __ASM_FCNTL_H */ +#endif /* _ASM_FCNTL_H */ diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h index b942b18311f..1d9aa097918 100644 --- a/include/asm-mips/fpregdef.h +++ b/include/asm-mips/fpregdef.h @@ -5,10 +5,16 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995 by Ralf Baechle + * Copyright (C) 1995, 1999 Ralf Baechle + * Copyright (C) 1985 MIPS Computer Systems, Inc. + * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. */ -#ifndef __ASM_MIPS_FPREGDEF_H -#define __ASM_MIPS_FPREGDEF_H +#ifndef _ASM_FPREGDEF_H +#define _ASM_FPREGDEF_H + +#include + +#if _MIPS_SIM == _MIPS_SIM_ABI32 /* * These definitions only cover the R3000-ish 16/32 register model. @@ -49,4 +55,45 @@ #define fcr31 $31 /* FPU status register */ -#endif /* !defined (__ASM_MIPS_FPREGDEF_H) */ +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ + +#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 + +#define fv0 $f0 /* return value */ +#define fv1 $f2 +#define fa0 $f12 /* argument registers */ +#define fa1 $f13 +#define fa2 $f14 +#define fa3 $f15 +#define fa4 $f16 +#define fa5 $f17 +#define fa6 $f18 +#define fa7 $f19 +#define ft0 $f4 /* caller saved */ +#define ft1 $f5 +#define ft2 $f6 +#define ft3 $f7 +#define ft4 $f8 +#define ft5 $f9 +#define ft6 $f10 +#define ft7 $f11 +#define ft8 $f20 +#define ft9 $f21 +#define ft10 $f22 +#define ft11 $f23 +#define ft12 $f1 +#define ft13 $f3 +#define fs0 $f24 /* callee saved */ +#define fs1 $f25 +#define fs2 $f26 +#define fs3 $f27 +#define fs4 $f28 +#define fs5 $f29 +#define fs6 $f30 +#define fs7 $f31 + +#define fcr31 $31 + +#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ + +#endif /* _ASM_FPREGDEF_H */ diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 7559728be0d..1957677c451 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -21,10 +21,14 @@ #include struct sigcontext; +struct sigcontext32; extern asmlinkage int (*save_fp_context)(struct sigcontext *sc); extern asmlinkage int (*restore_fp_context)(struct sigcontext *sc); +extern asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc); +extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc); + extern void fpu_emulator_init_fpu(void); extern void _init_fpu(void); extern void _save_fp(struct task_struct *); diff --git a/include/asm-mips/gdb-stub.h b/include/asm-mips/gdb-stub.h dissimilarity index 69% index 12ec0196e3f..1e269fa2704 100644 --- a/include/asm-mips/gdb-stub.h +++ b/include/asm-mips/gdb-stub.h @@ -1,213 +1,214 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 Andreas Busse - */ -#ifndef __ASM_MIPS_GDB_STUB_H -#define __ASM_MIPS_GDB_STUB_H - - -/* - * important register numbers - */ - -#define REG_EPC 37 -#define REG_FP 72 -#define REG_SP 29 - -/* - * Stack layout for the GDB exception handler - * Derived from the stack layout described in asm-mips/stackframe.h - * - * The first PTRSIZE*5 bytes are argument save space for C subroutines. - */ -#define NUMREGS 90 - -#define GDB_FR_REG0 (PTRSIZE*5) /* 0 */ -#define GDB_FR_REG1 ((GDB_FR_REG0) + 4) /* 1 */ -#define GDB_FR_REG2 ((GDB_FR_REG1) + 4) /* 2 */ -#define GDB_FR_REG3 ((GDB_FR_REG2) + 4) /* 3 */ -#define GDB_FR_REG4 ((GDB_FR_REG3) + 4) /* 4 */ -#define GDB_FR_REG5 ((GDB_FR_REG4) + 4) /* 5 */ -#define GDB_FR_REG6 ((GDB_FR_REG5) + 4) /* 6 */ -#define GDB_FR_REG7 ((GDB_FR_REG6) + 4) /* 7 */ -#define GDB_FR_REG8 ((GDB_FR_REG7) + 4) /* 8 */ -#define GDB_FR_REG9 ((GDB_FR_REG8) + 4) /* 9 */ -#define GDB_FR_REG10 ((GDB_FR_REG9) + 4) /* 10 */ -#define GDB_FR_REG11 ((GDB_FR_REG10) + 4) /* 11 */ -#define GDB_FR_REG12 ((GDB_FR_REG11) + 4) /* 12 */ -#define GDB_FR_REG13 ((GDB_FR_REG12) + 4) /* 13 */ -#define GDB_FR_REG14 ((GDB_FR_REG13) + 4) /* 14 */ -#define GDB_FR_REG15 ((GDB_FR_REG14) + 4) /* 15 */ -#define GDB_FR_REG16 ((GDB_FR_REG15) + 4) /* 16 */ -#define GDB_FR_REG17 ((GDB_FR_REG16) + 4) /* 17 */ -#define GDB_FR_REG18 ((GDB_FR_REG17) + 4) /* 18 */ -#define GDB_FR_REG19 ((GDB_FR_REG18) + 4) /* 19 */ -#define GDB_FR_REG20 ((GDB_FR_REG19) + 4) /* 20 */ -#define GDB_FR_REG21 ((GDB_FR_REG20) + 4) /* 21 */ -#define GDB_FR_REG22 ((GDB_FR_REG21) + 4) /* 22 */ -#define GDB_FR_REG23 ((GDB_FR_REG22) + 4) /* 23 */ -#define GDB_FR_REG24 ((GDB_FR_REG23) + 4) /* 24 */ -#define GDB_FR_REG25 ((GDB_FR_REG24) + 4) /* 25 */ -#define GDB_FR_REG26 ((GDB_FR_REG25) + 4) /* 26 */ -#define GDB_FR_REG27 ((GDB_FR_REG26) + 4) /* 27 */ -#define GDB_FR_REG28 ((GDB_FR_REG27) + 4) /* 28 */ -#define GDB_FR_REG29 ((GDB_FR_REG28) + 4) /* 29 */ -#define GDB_FR_REG30 ((GDB_FR_REG29) + 4) /* 30 */ -#define GDB_FR_REG31 ((GDB_FR_REG30) + 4) /* 31 */ - -/* - * Saved special registers - */ -#define GDB_FR_STATUS ((GDB_FR_REG31) + 4) /* 32 */ -#define GDB_FR_LO ((GDB_FR_STATUS) + 4) /* 33 */ -#define GDB_FR_HI ((GDB_FR_LO) + 4) /* 34 */ -#define GDB_FR_BADVADDR ((GDB_FR_HI) + 4) /* 35 */ -#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + 4) /* 36 */ -#define GDB_FR_EPC ((GDB_FR_CAUSE) + 4) /* 37 */ - -/* - * Saved floating point registers - */ -#define GDB_FR_FPR0 ((GDB_FR_EPC) + 4) /* 38 */ -#define GDB_FR_FPR1 ((GDB_FR_FPR0) + 4) /* 39 */ -#define GDB_FR_FPR2 ((GDB_FR_FPR1) + 4) /* 40 */ -#define GDB_FR_FPR3 ((GDB_FR_FPR2) + 4) /* 41 */ -#define GDB_FR_FPR4 ((GDB_FR_FPR3) + 4) /* 42 */ -#define GDB_FR_FPR5 ((GDB_FR_FPR4) + 4) /* 43 */ -#define GDB_FR_FPR6 ((GDB_FR_FPR5) + 4) /* 44 */ -#define GDB_FR_FPR7 ((GDB_FR_FPR6) + 4) /* 45 */ -#define GDB_FR_FPR8 ((GDB_FR_FPR7) + 4) /* 46 */ -#define GDB_FR_FPR9 ((GDB_FR_FPR8) + 4) /* 47 */ -#define GDB_FR_FPR10 ((GDB_FR_FPR9) + 4) /* 48 */ -#define GDB_FR_FPR11 ((GDB_FR_FPR10) + 4) /* 49 */ -#define GDB_FR_FPR12 ((GDB_FR_FPR11) + 4) /* 50 */ -#define GDB_FR_FPR13 ((GDB_FR_FPR12) + 4) /* 51 */ -#define GDB_FR_FPR14 ((GDB_FR_FPR13) + 4) /* 52 */ -#define GDB_FR_FPR15 ((GDB_FR_FPR14) + 4) /* 53 */ -#define GDB_FR_FPR16 ((GDB_FR_FPR15) + 4) /* 54 */ -#define GDB_FR_FPR17 ((GDB_FR_FPR16) + 4) /* 55 */ -#define GDB_FR_FPR18 ((GDB_FR_FPR17) + 4) /* 56 */ -#define GDB_FR_FPR19 ((GDB_FR_FPR18) + 4) /* 57 */ -#define GDB_FR_FPR20 ((GDB_FR_FPR19) + 4) /* 58 */ -#define GDB_FR_FPR21 ((GDB_FR_FPR20) + 4) /* 59 */ -#define GDB_FR_FPR22 ((GDB_FR_FPR21) + 4) /* 60 */ -#define GDB_FR_FPR23 ((GDB_FR_FPR22) + 4) /* 61 */ -#define GDB_FR_FPR24 ((GDB_FR_FPR23) + 4) /* 62 */ -#define GDB_FR_FPR25 ((GDB_FR_FPR24) + 4) /* 63 */ -#define GDB_FR_FPR26 ((GDB_FR_FPR25) + 4) /* 64 */ -#define GDB_FR_FPR27 ((GDB_FR_FPR26) + 4) /* 65 */ -#define GDB_FR_FPR28 ((GDB_FR_FPR27) + 4) /* 66 */ -#define GDB_FR_FPR29 ((GDB_FR_FPR28) + 4) /* 67 */ -#define GDB_FR_FPR30 ((GDB_FR_FPR29) + 4) /* 68 */ -#define GDB_FR_FPR31 ((GDB_FR_FPR30) + 4) /* 69 */ - -#define GDB_FR_FSR ((GDB_FR_FPR31) + 4) /* 70 */ -#define GDB_FR_FIR ((GDB_FR_FSR) + 4) /* 71 */ -#define GDB_FR_FRP ((GDB_FR_FIR) + 4) /* 72 */ - -#define GDB_FR_DUMMY ((GDB_FR_FRP) + 4) /* 73, unused ??? */ - -/* - * Again, CP0 registers - */ -#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + 4) /* 74 */ -#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + 4) /* 75 */ -#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + 4) /* 76 */ -#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + 4) /* 77 */ -#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + 4) /* 78 */ -#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + 4) /* 79 */ -#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + 4) /* 80 */ -#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + 4) /* 81 */ -#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + 4) /* 82 */ -#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + 4) /* 83 */ -#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + 4) /* 84 */ -#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + 4) /* 85 */ -#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + 4) /* 86 */ -#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + 4) /* 87 */ -#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + 4) /* 88 */ -#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + 4) /* 89 */ - -#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + 4) + (PTRSIZE-1)) & ~(PTRSIZE-1)) - -#ifndef __ASSEMBLY__ - -/* - * This is the same as above, but for the high-level - * part of the GDB stub. - */ - -struct gdb_regs { - /* - * Pad bytes for argument save space on the stack - * 20/40 Bytes for 32/64 bit code - */ - unsigned long pad0[5]; - - /* - * saved main processor registers - */ - long reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; - long reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15; - long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23; - long reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31; - - /* - * Saved special registers - */ - long cp0_status; - long lo; - long hi; - long cp0_badvaddr; - long cp0_cause; - long cp0_epc; - - /* - * Saved floating point registers - */ - long fpr0, fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7; - long fpr8, fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15; - long fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23; - long fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31; - - long cp1_fsr; - long cp1_fir; - - /* - * Frame pointer - */ - long frame_ptr; - long dummy; /* unused */ - - /* - * saved cp0 registers - */ - long cp0_index; - long cp0_random; - long cp0_entrylo0; - long cp0_entrylo1; - long cp0_context; - long cp0_pagemask; - long cp0_wired; - long cp0_reg7; - long cp0_reg8; - long cp0_reg9; - long cp0_entryhi; - long cp0_reg11; - long cp0_reg12; - long cp0_reg13; - long cp0_reg14; - long cp0_prid; -}; - -/* - * Prototypes - */ - -void set_debug_traps(void); -void set_async_breakpoint(unsigned long *epc); - -#endif /* !__ASSEMBLY__ */ -#endif /* __ASM_MIPS_GDB_STUB_H */ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 Andreas Busse + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef _ASM_GDB_STUB_H +#define _ASM_GDB_STUB_H + + +/* + * important register numbers + */ + +#define REG_EPC 37 +#define REG_FP 72 +#define REG_SP 29 + +/* + * Stack layout for the GDB exception handler + * Derived from the stack layout described in asm-mips/stackframe.h + * + * The first PTRSIZE*5 bytes are argument save space for C subroutines. + */ +#define NUMREGS 90 + +#define GDB_FR_REG0 (PTRSIZE*5) /* 0 */ +#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ +#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ +#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ +#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ +#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ +#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ +#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ +#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ +#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ +#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ +#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ +#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ +#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ +#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ +#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ +#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ +#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ +#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ +#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ +#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ +#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ +#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ +#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ +#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ +#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ +#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ +#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ +#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ +#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ +#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ +#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ + +/* + * Saved special registers + */ +#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ +#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ +#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ +#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ +#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ +#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ + +/* + * Saved floating point registers + */ +#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ +#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ +#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ +#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ +#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ +#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ +#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ +#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ +#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ +#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ +#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ +#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ +#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ +#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ +#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ +#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ +#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ +#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ +#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ +#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ +#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ +#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ +#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ +#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ +#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ +#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ +#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ +#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ +#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ +#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ +#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ +#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ + +#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ +#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ +#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ + +#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ + +/* + * Again, CP0 registers + */ +#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ +#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ +#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ +#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ +#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ +#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ +#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ +#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ +#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ +#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ +#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ +#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ +#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ +#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ +#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ +#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ + +#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) + +#ifndef __ASSEMBLY__ + +/* + * This is the same as above, but for the high-level + * part of the GDB stub. + */ + +struct gdb_regs { + /* + * Pad bytes for argument save space on the stack + * 20/40 Bytes for 32/64 bit code + */ + unsigned long pad0[5]; + + /* + * saved main processor registers + */ + long reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; + long reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15; + long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23; + long reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31; + + /* + * Saved special registers + */ + long cp0_status; + long lo; + long hi; + long cp0_badvaddr; + long cp0_cause; + long cp0_epc; + + /* + * Saved floating point registers + */ + long fpr0, fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7; + long fpr8, fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15; + long fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23; + long fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31; + + long cp1_fsr; + long cp1_fir; + + /* + * Frame pointer + */ + long frame_ptr; + long dummy; /* unused */ + + /* + * saved cp0 registers + */ + long cp0_index; + long cp0_random; + long cp0_entrylo0; + long cp0_entrylo1; + long cp0_context; + long cp0_pagemask; + long cp0_wired; + long cp0_reg7; + long cp0_reg8; + long cp0_reg9; + long cp0_entryhi; + long cp0_reg11; + long cp0_reg12; + long cp0_reg13; + long cp0_reg14; + long cp0_prid; +}; + +/* + * Prototypes + */ + +void set_debug_traps(void); +void set_async_breakpoint(unsigned long *epc); + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASM_GDB_STUB_H */ diff --git a/include/asm-mips/hdreg.h b/include/asm-mips/hdreg.h index 4b90cf6bf98..0a952a91063 100644 --- a/include/asm-mips/hdreg.h +++ b/include/asm-mips/hdreg.h @@ -1,12 +1,13 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * This file contains the MIPS architecture specific IDE code. + * * Copyright (C) 1994-1996 Linus Torvalds & authors * Copyright (C) 2001 Ralf Baechle */ - -/* - * This file contains the MIPS architecture specific IDE code. - */ - #ifndef _ASM_HDREG_H #define _ASM_HDREG_H diff --git a/include/asm-mips/hw_irq.h b/include/asm-mips/hw_irq.h index 8be338b9ac1..6996095113d 100644 --- a/include/asm-mips/hw_irq.h +++ b/include/asm-mips/hw_irq.h @@ -19,6 +19,8 @@ extern int i8259A_irq_pending(unsigned int irq); extern void make_8259A_irq(unsigned int irq); extern void init_8259A(int aeoi); +#include + extern atomic_t irq_err_count; /* This may not be apropriate for all machines, we'll see ... */ diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h index f58612ec7da..742130c8be4 100644 --- a/include/asm-mips/i8259.h +++ b/include/asm-mips/i8259.h @@ -10,8 +10,8 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ -#ifndef __ASM_MIPS_I8259_H -#define __ASM_MIPS_I8259_H +#ifndef _ASM_I8259_H +#define _ASM_I8259_H #include @@ -20,4 +20,4 @@ extern void init_i8259_irqs(void); -#endif /* __ASM_MIPS_I8259_H */ +#endif /* _ASM_I8259_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index e857349b1ca..aff491b61f6 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -6,7 +6,6 @@ * Copyright (C) 1994, 1995 Waldorf GmbH * Copyright (C) 1994 - 2000 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 FSMLabs, Inc. */ #ifndef _ASM_IO_H #define _ASM_IO_H @@ -15,9 +14,9 @@ #include #include +#include #include #include -#include #ifdef CONFIG_SGI_IP27 extern unsigned long bus_to_baddr[256]; @@ -41,9 +40,12 @@ extern unsigned long bus_to_baddr[256]; #if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__) #define __ioswab8(x) (x) + #ifdef CONFIG_SGI_IP22 -/* IP22 seems braindead enough to swap 16bits values in hardware, but - not 32bits. Go figure... Can't tell without documentation. */ +/* + * IP22 seems braindead enough to swap 16bits values in hardware, but + * not 32bits. Go figure... Can't tell without documentation. + */ #define __ioswab16(x) (x) #else #define __ioswab16(x) swab16(x) @@ -60,16 +62,6 @@ extern unsigned long bus_to_baddr[256]; #endif -/* - * Historically I wrote this stuff the same way as Linus did - * because I was young and clueless. And now it's so jucky that I - * don't want to put my eyes on it again to get rid of it :-) - * - * I'll do it then, because this code offends both me and my compiler - * - particularly the bits of inline asm which end up doing crap like - * 'lb $2,$2($5)' -- dwmw2 - */ - #define IO_SPACE_LIMIT 0xffff /* @@ -126,7 +118,7 @@ extern const unsigned long mips_io_port_base; */ static inline unsigned long virt_to_phys(volatile void * address) { - return PHYSADDR(address); + return (unsigned long)address - PAGE_OFFSET; } /* @@ -143,7 +135,7 @@ static inline unsigned long virt_to_phys(volatile void * address) */ static inline void * phys_to_virt(unsigned long address) { - return (void *)KSEG0ADDR(address); + return (void *)(address + PAGE_OFFSET); } /* @@ -151,12 +143,12 @@ static inline void * phys_to_virt(unsigned long address) */ static inline unsigned long isa_virt_to_bus(volatile void * address) { - return PHYSADDR(address); + return (unsigned long)address - PAGE_OFFSET; } static inline void * isa_bus_to_virt(unsigned long address) { - return (void *)KSEG0ADDR(address); + return (void *)(address + PAGE_OFFSET); } #define isa_page_to_bus page_to_phys @@ -172,7 +164,8 @@ static inline void * isa_bus_to_virt(unsigned long address) /* * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. + * for the processor. This implies the assumption that there is only + * one of these busses. */ extern unsigned long isa_slot_offset; @@ -182,7 +175,7 @@ extern unsigned long isa_slot_offset; #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags); - +extern void __iounmap(void *addr); /* * ioremap - map bus memory into CPU space @@ -234,6 +227,7 @@ extern void iounmap(void *addr); #define __raw_readb(addr) (*(volatile unsigned char *)(addr)) #define __raw_readw(addr) (*(volatile unsigned short *)(addr)) #define __raw_readl(addr) (*(volatile unsigned int *)(addr)) +#ifdef CONFIG_MIPS32 #define ____raw_readq(addr) \ ({ \ u64 __res; \ @@ -249,6 +243,10 @@ extern void iounmap(void *addr); \ __res; \ }) +#endif +#ifdef CONFIG_MIPS64 +#define ____raw_readq(addr) (*(volatile unsigned long *)(addr)) +#endif #define __raw_readq(addr) \ ({ \ @@ -270,6 +268,7 @@ extern void iounmap(void *addr); #define __raw_writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (b)) #define __raw_writew(w,addr) ((*(volatile unsigned short *)(addr)) = (w)) #define __raw_writel(l,addr) ((*(volatile unsigned int *)(addr)) = (l)) +#ifdef CONFIG_MIPS32 #define ____raw_writeq(val,addr) \ ({ \ u64 __tmp; \ @@ -285,6 +284,10 @@ extern void iounmap(void *addr); : "=r" (__tmp) \ : "0" ((unsigned long long)val), "r" (addr)); \ }) +#endif +#ifdef CONFIG_MIPS64 +#define ____raw_writeq(l,addr) ((*(volatile unsigned long *)(addr)) = (l)) +#endif #define __raw_writeq(val,addr) \ ({ \ @@ -344,7 +347,7 @@ extern void iounmap(void *addr); * Returns 1 on a match. */ static inline int check_signature(unsigned long io_addr, - const unsigned char *signature, int length) + const unsigned char *signature, int length) { int retval = 0; do { @@ -371,8 +374,7 @@ out: * This function is deprecated. New drivers should use ioremap and * check_signature. */ -#define isa_check_signature(io, s, l) check_signature(i,s,l) - +#define isa_check_signature(io, s, l) check_signature(i,s,l) #define outb(val,port) \ do { \ @@ -381,7 +383,7 @@ do { \ #define outw(val,port) \ do { \ - *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val); \ + *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\ } while(0) #define outl(val,port) \ @@ -407,13 +409,6 @@ do { \ SLOW_DOWN_IO; \ } while(0) -#define inb(port) __inb(port) -#define inw(port) __inw(port) -#define inl(port) __inl(port) -#define inb_p(port) __inb_p(port) -#define inw_p(port) __inw_p(port) -#define inl_p(port) __inl_p(port) - static inline unsigned char __inb(unsigned long port) { return __ioswab8(*(volatile u8 *)(mips_io_port_base + port)); @@ -458,12 +453,12 @@ static inline unsigned int __inl_p(unsigned long port) return __ioswab32(__val); } -#define outsb(port, addr, count) __outsb(port, addr, count) -#define insb(port, addr, count) __insb(port, addr, count) -#define outsw(port, addr, count) __outsw(port, addr, count) -#define insw(port, addr, count) __insw(port, addr, count) -#define outsl(port, addr, count) __outsl(port, addr, count) -#define insl(port, addr, count) __insl(port, addr, count) +#define inb(port) __inb(port) +#define inw(port) __inw(port) +#define inl(port) __inl(port) +#define inb_p(port) __inb_p(port) +#define inw_p(port) __inw_p(port) +#define inl_p(port) __inl_p(port) static inline void __outsb(unsigned long port, void *addr, unsigned int count) { @@ -513,6 +508,13 @@ static inline void __insl(unsigned long port, void *addr, unsigned int count) } } +#define outsb(port, addr, count) __outsb(port, addr, count) +#define insb(port, addr, count) __insb(port, addr, count) +#define outsw(port, addr, count) __outsw(port, addr, count) +#define insw(port, addr, count) __insw(port, addr, count) +#define outsl(port, addr, count) __outsl(port, addr, count) +#define insl(port, addr, count) __insl(port, addr, count) + /* * The caches on some architectures aren't dma-coherent and have need to * handle this in software. There are three types of operations that @@ -537,9 +539,9 @@ extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); -#define dma_cache_wback_inv(start, size)_dma_cache_wback_inv(start,size) -#define dma_cache_wback(start, size) _dma_cache_wback(start,size) -#define dma_cache_inv(start, size) _dma_cache_inv(start,size) +#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size) +#define dma_cache_wback(start, size) _dma_cache_wback(start,size) +#define dma_cache_inv(start, size) _dma_cache_inv(start,size) #else /* Sane hardware */ diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h index ab54abc3d6d..d0fc1a9051d 100644 --- a/include/asm-mips/ioctl.h +++ b/include/asm-mips/ioctl.h @@ -1,14 +1,12 @@ /* - * Linux ioctl() stuff. - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 1996, 2001 by Ralf Baechle + * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle */ -#ifndef __ASM_MIPS_IOCTL_H -#define __ASM_MIPS_IOCTL_H +#ifndef _ASM_IOCTL_H +#define _ASM_IOCTL_H /* * The original linux ioctl numbering scheme was just a general @@ -40,6 +38,11 @@ #define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) /* + * We to additionally limit parameters to a maximum 255 bytes. + */ +#define _IOC_SLMASK 0xff + +/* * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. * And this turns out useful to catch old ioctl numbers in header * files for us. @@ -82,4 +85,4 @@ #define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) #define IOCSIZE_SHIFT (_IOC_SIZESHIFT) -#endif /* __ASM_MIPS_IOCTL_H */ +#endif /* _ASM_IOCTL_H */ diff --git a/include/asm-mips64/ip32/crime.h b/include/asm-mips/ip32/crime.h similarity index 100% rename from include/asm-mips64/ip32/crime.h rename to include/asm-mips/ip32/crime.h diff --git a/include/asm-mips64/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h similarity index 100% rename from include/asm-mips64/ip32/ip32_ints.h rename to include/asm-mips/ip32/ip32_ints.h diff --git a/include/asm-mips64/ip32/mace.h b/include/asm-mips/ip32/mace.h similarity index 100% rename from include/asm-mips64/ip32/mace.h rename to include/asm-mips/ip32/mace.h diff --git a/include/asm-mips64/ip32/machine.h b/include/asm-mips/ip32/machine.h similarity index 100% rename from include/asm-mips64/ip32/machine.h rename to include/asm-mips/ip32/machine.h diff --git a/include/asm-mips/ipc.h b/include/asm-mips/ipc.h index eaf4b863143..377bbd5ef62 100644 --- a/include/asm-mips/ipc.h +++ b/include/asm-mips/ipc.h @@ -1,5 +1,5 @@ -#ifndef __ASM_MIPS_IPC_H -#define __ASM_MIPS_IPC_H +#ifndef _ASM_IPC_H +#define _ASM_IPC_H /* * These are used to wrap system calls on MIPS. @@ -30,4 +30,4 @@ struct ipc_kludge { #define IPCCALL(version,op) ((version)<<16 | (op)) -#endif /* __ASM_MIPS_IPC_H */ +#endif /* _ASM_IPC_H */ diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 4bb7750583d..92001d3b401 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h @@ -13,8 +13,37 @@ #include #include +#include -#define NR_IRQS 128 /* Largest number of ints of all machines. */ +#ifdef CONFIG_SGI_IP27 + +#define NR_IRQS 256 + +/* + * Number of levels in INT_PEND0. Can be set to 128 if we also + * consider INT_PEND1. + */ +#define PERNODE_LEVELS 64 + +extern int node_level_to_irq[MAX_COMPACT_NODES][PERNODE_LEVELS]; + +/* + * we need to map irq's up to at least bit 7 of the INT_MASK0_A register + * since bits 0-6 are pre-allocated for other purposes. + */ +#define LEAST_LEVEL 7 +#define FAST_IRQ_TO_LEVEL(i) ((i) + LEAST_LEVEL) +#define LEVEL_TO_IRQ(c, l) \ + (node_level_to_irq[CPUID_TO_COMPACT_NODEID(c)][(l)]) + +#else + +/* + * Largest number of ints of all machines except IP27 + */ +#define NR_IRQS 128 + +#endif #ifdef CONFIG_I8259 static inline int irq_canonicalize(int irq) diff --git a/include/asm-mips/irq_cpu.h b/include/asm-mips/irq_cpu.h index 9baaca62a18..d49ec776024 100644 --- a/include/asm-mips/irq_cpu.h +++ b/include/asm-mips/irq_cpu.h @@ -10,9 +10,9 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ -#ifndef __ASM_MIPS_IRQ_CPU_H -#define __ASM_MIPS_IRQ_CPU_H +#ifndef _ASM_IRQ_CPU_H +#define _ASM_IRQ_CPU_H extern void mips_cpu_irq_init(int irq_base); -#endif /* __ASM_MIPS_IRQ_CPU_H */ +#endif /* _ASM_IRQ_CPU_H */ diff --git a/include/asm-mips64/m48t35.h b/include/asm-mips/m48t35.h similarity index 100% rename from include/asm-mips64/m48t35.h rename to include/asm-mips/m48t35.h diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index 97deb9b0d67..db7ac0c7b7f 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -28,9 +28,16 @@ */ #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ pgd_current[smp_processor_id()] = (unsigned long)(pgd) +#ifdef CONFIG_MIPS32 #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << (23 + 3)); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) +#endif +#ifdef CONFIG_MIPS64 +#define TLBMISS_HANDLER_SETUP() \ + write_c0_context((unsigned long) smp_processor_id() << 23); \ + TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) +#endif extern unsigned long pgd_current[]; #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) @@ -94,7 +101,7 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm) static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) { - unsigned cpu = smp_processor_id(); + unsigned int cpu = smp_processor_id(); unsigned long flags; local_irq_save(flags); @@ -144,7 +151,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) write_c0_entryhi(cpu_context(cpu, next)); TLBMISS_HANDLER_SETUP_PGD(next->pgd); - /* mark mmu ownership change */ + /* mark mmu ownership change */ clear_bit(cpu, &prev->cpu_vm_mask); set_bit(cpu, &next->cpu_vm_mask); diff --git a/include/asm-mips64/mmzone.h b/include/asm-mips/mmzone.h similarity index 100% rename from include/asm-mips64/mmzone.h rename to include/asm-mips/mmzone.h diff --git a/include/asm-mips/namei.h b/include/asm-mips/namei.h index dce62e3018c..5f2308a4f62 100644 --- a/include/asm-mips/namei.h +++ b/include/asm-mips/namei.h @@ -1,10 +1,8 @@ /* - * linux/include/asm-mips/namei.h - * * Included from linux/fs/namei.c */ -#ifndef __ASM_NAMEI_H -#define __ASM_NAMEI_H +#ifndef _ASM_NAMEI_H +#define _ASM_NAMEI_H #include @@ -26,4 +24,4 @@ static inline char *__emul_prefix(void) #endif /* !defined(CONFIG_BINFMT_IRIX) */ -#endif /* __ASM_NAMEI_H */ +#endif /* _ASM_NAMEI_H */ diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h dissimilarity index 63% index e67d89c9a23..36cec9e3169 100644 --- a/include/asm-mips/paccess.h +++ b/include/asm-mips/paccess.h @@ -1,102 +1,113 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * - * Protected memory access. Used for everything that might take revenge - * by sending a DBE error like accessing possibly non-existant memory or - * devices. - */ -#ifndef _ASM_PACCESS_H -#define _ASM_PACCESS_H - -#include - -extern asmlinkage void handle_ibe(void); -extern asmlinkage void handle_dbe(void); - -#define put_dbe(x,ptr) __put_dbe((x),(ptr),sizeof(*(ptr))) -#define get_dbe(x,ptr) __get_dbe((x),(ptr),sizeof(*(ptr))) - -struct __large_pstruct { unsigned long buf[100]; }; -#define __mp(x) (*(struct __large_pstruct *)(x)) - -#define __get_dbe(x,ptr,size) ({ \ -int __gu_err; \ -__typeof(*(ptr)) __gu_val; \ -unsigned long __gu_addr; \ -__asm__("":"=r" (__gu_val)); \ -__gu_addr = (unsigned long) (ptr); \ -__asm__("":"=r" (__gu_err)); \ -switch (size) { \ -case 1: __get_dbe_asm("lb"); break; \ -case 2: __get_dbe_asm("lh"); break; \ -case 4: __get_dbe_asm("lw"); break; \ -case 8: __get_dbe_asm("ld"); break; \ -default: __get_dbe_unknown(); break; \ -} x = (__typeof__(*(ptr))) __gu_val; __gu_err; }) - -#define __get_dbe_asm(insn) \ -({ \ -__asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\tnoreorder\n\t" \ - insn "\t%1,%2\n\t" \ - "1:\tmove\t%0,$0\n" \ - ".set\tpop\n\t" \ - "2:\n\t" \ - ".section\t.fixup,\"ax\"\n" \ - "3:\tli\t%0,%3\n\t" \ - "move\t%1,$0\n\t" \ - "j\t2b\n\t" \ - ".previous\n\t" \ - ".section\t__dbe_table,\"a\"\n\t" \ - ".word\t1b-4,3b\n\t" \ - ".previous" \ - :"=r" (__gu_err), "=r" (__gu_val) \ - :"o" (__mp(__gu_addr)), "i" (-EFAULT)); }) - -extern void __get_dbe_unknown(void); - -#define __put_dbe(x,ptr,size) ({ \ -int __pu_err; \ -__typeof__(*(ptr)) __pu_val; \ -unsigned long __pu_addr; \ -__pu_val = (x); \ -__pu_addr = (unsigned long) (ptr); \ -__asm__("":"=r" (__pu_err)); \ -switch (size) { \ -case 1: __put_dbe_asm("sb"); break; \ -case 2: __put_dbe_asm("sh"); break; \ -case 4: __put_dbe_asm("sw"); break; \ -case 8: __put_dbe_asm("sd"); break; \ -default: __put_dbe_unknown(); break; \ -} __pu_err; }) - -#define __put_dbe_asm(insn) \ -({ \ -__asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\tnoreorder\n\t" \ - insn "\t%1,%2\n\t" \ - "1:\tmove\t%0,$0\n" \ - ".set\tpop\n\t" \ - "2:\n\t" \ - ".section\t.fixup,\"ax\"\n" \ - "3:\tli\t%0,%3\n\t" \ - "j\t2b\n\t" \ - ".previous\n\t" \ - ".section\t__dbe_table,\"a\"\n\t" \ - ".word\t1b-4,3b\n\t" \ - ".previous" \ - :"=r" (__pu_err) \ - :"r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT)); }) - -extern void __put_dbe_unknown(void); - -extern unsigned long search_dbe_table(unsigned long addr); - -#endif /* _ASM_PACCESS_H */ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * + * Protected memory access. Used for everything that might take revenge + * by sending a DBE error like accessing possibly non-existant memory or + * devices. + */ +#ifndef _ASM_PACCESS_H +#define _ASM_PACCESS_H + +#include +#include + +#ifdef CONFIG_MIPS32 +#define __PA_ADDR ".word" +#endif +#ifdef CONFIG_MIPS64 +#define __PA_ADDR ".dword" +#endif + +extern asmlinkage void handle_ibe(void); +extern asmlinkage void handle_dbe(void); + +#define put_dbe(x,ptr) __put_dbe((x),(ptr),sizeof(*(ptr))) +#define get_dbe(x,ptr) __get_dbe((x),(ptr),sizeof(*(ptr))) + +struct __large_pstruct { unsigned long buf[100]; }; +#define __mp(x) (*(struct __large_pstruct *)(x)) + +#define __get_dbe(x,ptr,size) \ +({ \ + long __gu_err; \ + __typeof(*(ptr)) __gu_val; \ + unsigned long __gu_addr; \ + __asm__("":"=r" (__gu_val)); \ + __gu_addr = (unsigned long) (ptr); \ + __asm__("":"=r" (__gu_err)); \ + switch (size) { \ + case 1: __get_dbe_asm("lb"); break; \ + case 2: __get_dbe_asm("lh"); break; \ + case 4: __get_dbe_asm("lw"); break; \ + case 8: __get_dbe_asm("ld"); break; \ + default: __get_dbe_unknown(); break; \ + } \ + x = (__typeof__(*(ptr))) __gu_val; \ + __gu_err; \ +}) + +#define __get_dbe_asm(insn) \ +({ \ + __asm__ __volatile__( \ + "1:\t" insn "\t%1,%2\n\t" \ + "move\t%0,$0\n" \ + "2:\n\t" \ + ".section\t.fixup,\"ax\"\n" \ + "3:\tli\t%0,%3\n\t" \ + "move\t%1,$0\n\t" \ + "j\t2b\n\t" \ + ".previous\n\t" \ + ".section\t__dbe_table,\"a\"\n\t" \ + __PA_ADDR "\t1b, 3b\n\t" \ + ".previous" \ + :"=r" (__gu_err), "=r" (__gu_val) \ + :"o" (__mp(__gu_addr)), "i" (-EFAULT)); \ +}) + +extern void __get_dbe_unknown(void); + +#define __put_dbe(x,ptr,size) \ +({ \ + long __pu_err; \ + __typeof__(*(ptr)) __pu_val; \ + long __pu_addr; \ + __pu_val = (x); \ + __pu_addr = (long) (ptr); \ + __asm__("":"=r" (__pu_err)); \ + switch (size) { \ + case 1: __put_dbe_asm("sb"); break; \ + case 2: __put_dbe_asm("sh"); break; \ + case 4: __put_dbe_asm("sw"); break; \ + case 8: __put_dbe_asm("sd"); break; \ + default: __put_dbe_unknown(); break; \ + } \ + __pu_err; \ +}) + +#define __put_dbe_asm(insn) \ +({ \ + __asm__ __volatile__( \ + "1:\t" insn "\t%1,%2\n\t" \ + "move\t%0,$0\n" \ + "2:\n\t" \ + ".section\t.fixup,\"ax\"\n" \ + "3:\tli\t%0,%3\n\t" \ + "j\t2b\n\t" \ + ".previous\n\t" \ + ".section\t__dbe_table,\"a\"\n\t" \ + __PA_ADDR "\t1b, 3b\n\t" \ + ".previous" \ + : "=r" (__pu_err) \ + : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT)); \ +}) + +extern void __put_dbe_unknown(void); + +extern unsigned long search_dbe_table(unsigned long addr); + +#endif /* _ASM_PACCESS_H */ diff --git a/include/asm-mips/page-32.h b/include/asm-mips/page-32.h new file mode 100644 index 00000000000..dcc4e0d047c --- /dev/null +++ b/include/asm-mips/page-32.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_PAGE_32_H +#define _ASM_PAGE_32_H + +#include + +/* + * This handles the memory map. + * We handle pages at KSEG0 for kernels with 32 bit address space. + */ +#define PAGE_OFFSET 0x80000000UL +#define UNCAC_BASE 0xa0000000UL + +/* + * Memory above this physical address will be considered highmem. + */ +#define HIGHMEM_START 0x20000000UL + +#endif /* _ASM_PAGE_32_H */ diff --git a/include/asm-mips/page-64.h b/include/asm-mips/page-64.h new file mode 100644 index 00000000000..1581d26c8e3 --- /dev/null +++ b/include/asm-mips/page-64.h @@ -0,0 +1,31 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_PAGE_64_H +#define _ASM_PAGE_64_H + +#include + +/* + * This handles the memory map. + */ +#ifdef CONFIG_NONCOHERENT_IO +#define PAGE_OFFSET 0x9800000000000000UL +#else +#define PAGE_OFFSET 0xa800000000000000UL +#endif + + +/* + * Memory above this physical address will be considered highmem. + * Fixme: 59 bits is a fictive number and makes assumptions about processors + * in the distant future. Nobody will care for a few years :-) + */ +#define HIGHMEM_START (1UL << 59UL) + +#endif /* _ASM_PAGE_64_H */ diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index b373b832210..41e3beb9395 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -1,17 +1,23 @@ /* - * Definitions for page handling - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994 - 1999 by Ralf Baechle + * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_PAGE_H #define _ASM_PAGE_H #include +#ifdef CONFIG_MIPS32 +#include +#endif +#ifdef CONFIG_MIPS64 +#include +#endif + /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 #define PAGE_SIZE (1UL << PAGE_SHIFT) @@ -100,23 +106,19 @@ static __inline__ int get_order(unsigned long size) /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) -/* - * This handles the memory map. - * We handle pages at KSEG0 for kernels with 32 bit address space. - */ -#define PAGE_OFFSET 0x80000000UL -#define UNCAC_BASE 0xa0000000UL - #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) + +#ifndef CONFIG_DISCONTIGMEM #define pfn_to_page(pfn) (mem_map + (pfn)) #define page_to_pfn(page) ((unsigned long)((page) - mem_map)) #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) #define pfn_valid(pfn) ((pfn) < max_mapnr) #define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) +#endif #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) @@ -124,11 +126,6 @@ static __inline__ int get_order(unsigned long size) #define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) #define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) -/* - * Memory above this physical address will be considered highmem. - */ -#define HIGHMEM_START 0x20000000UL - #endif /* defined (__KERNEL__) */ #endif /* _ASM_PAGE_H */ diff --git a/include/asm-mips64/pci/bridge.h b/include/asm-mips/pci/bridge.h similarity index 100% rename from include/asm-mips64/pci/bridge.h rename to include/asm-mips/pci/bridge.h diff --git a/include/asm-mips64/pgalloc.h b/include/asm-mips/pgalloc.h similarity index 72% rename from include/asm-mips64/pgalloc.h rename to include/asm-mips/pgalloc.h index 71406afc592..7e27e2732d6 100644 --- a/include/asm-mips64/pgalloc.h +++ b/include/asm-mips/pgalloc.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994 - 2001 by Ralf Baechle at alii + * Copyright (C) 1994 - 2001, 2003 by Ralf Baechle * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. */ #ifndef _ASM_PGALLOC_H @@ -12,9 +12,6 @@ #include #include #include -#include - -#define check_pgt_cache() do { } while (0) static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) @@ -28,13 +25,17 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, set_pmd(pmd, __pmd((unsigned long)page_address(pte))); } -#define pgd_populate(mm, pgd, pmd) set_pgd(pgd, __pgd(pmd)) +/* + * Initialize a new pgd / pmd table with invalid pointers. + */ +extern void pgd_init(unsigned long page); +extern void pmd_init(unsigned long page, unsigned long pagetable); static inline pgd_t *pgd_alloc(struct mm_struct *mm) { pgd_t *ret, *init; - ret = (pgd_t *) __get_free_pages(GFP_KERNEL, 1); + ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER); if (ret) { init = pgd_offset(&init_mm, 0); pgd_init((unsigned long)ret); @@ -55,8 +56,7 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, { pte_t *pte; - pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, - PTE_ORDER); + pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, PTE_ORDER); if (pte) clear_page(pte); @@ -88,6 +88,21 @@ static inline void pte_free(struct page *pte) #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) #define __pmd_free_tlb(tlb,x) do { } while (0) +#ifdef CONFIG_MIPS32 +#define pgd_populate(mm, pmd, pte) BUG() + +/* + * allocating and freeing a pmd is trivial: the 1-entry pmd is + * inside the pgd, so has no extra memory associated with it. + */ +#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); }) +#define pmd_free(x) do { } while (0) +#endif + +#ifdef CONFIG_MIPS64 + +#define pgd_populate(mm, pgd, pmd) set_pgd(pgd, __pgd(pmd)) + static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) { pmd_t *pmd; @@ -103,7 +118,14 @@ static inline void pmd_free(pmd_t *pmd) free_pages((unsigned long)pmd, PMD_ORDER); } +#endif + +/* + * Used for the b0rked handling of kernel pagetables on the 64-bit kernel. + */ extern pte_t kptbl[(PAGE_SIZE << PGD_ORDER)/sizeof(pte_t)]; extern pmd_t kpmdtbl[PTRS_PER_PMD]; +#define check_pgt_cache() do { } while (0) + #endif /* _ASM_PGALLOC_H */ diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h new file mode 100644 index 00000000000..83a446eff0d --- /dev/null +++ b/include/asm-mips/pgtable-32.h @@ -0,0 +1,224 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle + * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. + */ +#ifndef _ASM_PGTABLE_32_H +#define _ASM_PGTABLE_32_H + +#include +#include +#include + +#include +#include +#include + +/* + * - add_wired_entry() add a fixed TLB entry, and move wired register + */ +extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask); + +/* + * - add_temporary_entry() add a temporary TLB entry. We use TLB entries + * starting at the top and working down. This is for populating the + * TLB before trap_init() puts the TLB miss handler in place. It + * should be used only for entries matching the actual page tables, + * to prevent inconsistencies. + */ +extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask); + + +/* Basically we have the same two-level (which is the logical three level + * Linux page table layout folded) page tables as the i386. Some day + * when we have proper page coloring support we can have a 1% quicker + * tlb refill handling mechanism, but for now it is a bit slower but + * works even with the cache aliasing problem the R4k and above have. + */ + +/* PMD_SHIFT determines the size of the area a second-level page table can map */ +#ifdef CONFIG_64BIT_PHYS_ADDR +#define PMD_SHIFT 21 +#else +#define PMD_SHIFT 22 +#endif +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) + +/* PGDIR_SHIFT determines what a third-level page table entry can map */ +#define PGDIR_SHIFT PMD_SHIFT +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* + * Entries per page directory level: we use two-level, so + * we don't really have any PMD directory physically. + */ +#ifdef CONFIG_64BIT_PHYS_ADDR +#define PTRS_PER_PTE 512 +#define PTRS_PER_PMD 1 +#define PTRS_PER_PGD 2048 +#define PGD_ORDER 1 +#define PMD_ORDER 0 +#define PTE_ORDER 0 +#else +#define PTRS_PER_PTE 1024 +#define PTRS_PER_PMD 1 +#define PTRS_PER_PGD 1024 +#define PGD_ORDER 0 +#define PMD_ORDER 0 +#define PTE_ORDER 0 +#endif + +#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) +#define FIRST_USER_PGD_NR 0 + +#define VMALLOC_START KSEG2 +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) + +#if CONFIG_HIGHMEM +# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) +#else +# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) +#endif + +#ifdef CONFIG_64BIT_PHYS_ADDR +#define pte_ERROR(e) \ + printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e)) +#else +#define pte_ERROR(e) \ + printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) +#endif +#define pmd_ERROR(e) \ + printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) +#define pgd_ERROR(e) \ + printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) + +extern void load_pgd(unsigned long pg_dir); + +extern pmd_t invalid_pte_table[PAGE_SIZE/sizeof(pmd_t)]; + +/* + * Empty pgd/pmd entries point to the invalid_pte_table. + */ +static inline int pmd_none(pmd_t pmd) +{ + return pmd_val(pmd) == (unsigned long) invalid_pte_table; +} + +#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) + +static inline int pmd_present(pmd_t pmd) +{ + return pmd_val(pmd) != (unsigned long) invalid_pte_table; +} + +static inline void pmd_clear(pmd_t *pmdp) +{ + pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); +} + +/* + * The "pgd_xxx()" functions here are trivial for a folded two-level + * setup: the pgd is never bad, and a pmd always exists (as it's folded + * into the pgd entry) + */ +static inline int pgd_none(pgd_t pgd) { return 0; } +static inline int pgd_bad(pgd_t pgd) { return 0; } +static inline int pgd_present(pgd_t pgd) { return 1; } +static inline void pgd_clear(pgd_t *pgdp) { } + +#define pte_page(x) pfn_to_page(pte_pfn(x)) +#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) +#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) + +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + +/* + * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset + * into this range: + */ +#define pte_to_pgoff(_pte) \ + ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 )) + +#define pgoff_to_pte(off) \ + ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE }) + +#else + +/* + * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset + * into this range: + */ +#define pte_to_pgoff(_pte) \ + ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) + +#define pgoff_to_pte(off) \ + ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE }) + +#endif + +#define __pgd_offset(address) pgd_index(address) +#define __pmd_offset(address) \ + (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) + +/* to find an entry in a kernel page-table-directory */ +#define pgd_offset_k(address) pgd_offset(&init_mm, address) + +#define pgd_index(address) ((address) >> PGDIR_SHIFT) + +/* to find an entry in a page-table-directory */ +#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) + +/* Find an entry in the second-level page table.. */ +static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) +{ + return (pmd_t *) dir; +} + +/* Find an entry in the third-level page table.. */ +#define __pte_offset(address) \ + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define pte_offset(dir, address) \ + ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address)) +#define pte_offset_kernel(dir, address) \ + ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address)) + +#define pte_offset_map(dir, address) \ + ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) +#define pte_offset_map_nested(dir, address) \ + ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) +#define pte_unmap(pte) ((void)(pte)) +#define pte_unmap_nested(pte) ((void)(pte)) + +extern pgd_t swapper_pg_dir[1024]; +extern void paging_init(void); + +/* Swap entries must have VALID and GLOBAL bits cleared. */ +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + +#define __swp_type(x) (((x).val >> 1) & 0x7f) +#define __swp_offset(x) ((x).val >> 10) +#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 10) }) +#else + +#define __swp_type(x) (((x).val >> 1) & 0x1f) +#define __swp_offset(x) ((x).val >> 8) +#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) }) +#endif + +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) + +#ifdef CONFIG_64BIT_PHYS_ADDR +typedef u64 pte_addr_t; +#else +typedef pte_t *pte_addr_t; +#endif + +#endif /* _ASM_PGTABLE_32_H */ diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h new file mode 100644 index 00000000000..5e80af4559b --- /dev/null +++ b/include/asm-mips/pgtable-64.h @@ -0,0 +1,209 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle + * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. + */ +#ifndef _ASM_PGTABLE_64_H +#define _ASM_PGTABLE_64_H + +#include +#include +#include + +#ifndef __ASSEMBLY__ + +#include +#include +#include + +/* + * Each address space has 2 4K pages as its page directory, giving 1024 + * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a + * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to + * page tables. Each page table is a single 4K page, giving 512 (== + * PTRS_PER_PTE) 8 byte ptes. Each pgde is initialized to point to + * invalid_pmd_table, each pmde is initialized to point to + * invalid_pte_table, each pte is initialized to 0. When memory is low, + * and a pmd table or a page table allocation fails, empty_bad_pmd_table + * and empty_bad_page_table is returned back to higher layer code, so + * that the failure is recognized later on. Linux does not seem to + * handle these failures very well though. The empty_bad_page_table has + * invalid pte entries in it, to force page faults. + * Vmalloc handling: vmalloc uses swapper_pg_dir[0] (returned by + * pgd_offset_k), which is initalized to point to kpmdtbl. kpmdtbl is + * the only single page pmd in the system. kpmdtbl entries point into + * kptbl[] array. We reserve 1 << PGD_ORDER pages to hold the + * vmalloc range translations, which the fault handler looks at. + */ + +#endif /* !__ASSEMBLY__ */ + +/* PMD_SHIFT determines the size of the area a second-level page table can map */ +#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3)) +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) + +/* PGDIR_SHIFT determines what a third-level page table entry can map */ +#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + 1 - 3)) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* Entries per page directory level: we use two-level, so we don't really + have any PMD directory physically. */ +#define PTRS_PER_PGD 1024 +#define PTRS_PER_PMD 1024 +#define PTRS_PER_PTE 512 +#define PGD_ORDER 1 +#define PMD_ORDER 1 +#define PTE_ORDER 0 + +#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) +#define FIRST_USER_PGD_NR 0 + +#define VMALLOC_START XKSEG +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END \ + (VMALLOC_START + ((1 << PGD_ORDER) * PTRS_PER_PTE * PAGE_SIZE)) + +#ifndef __ASSEMBLY__ + +#define pte_ERROR(e) \ + printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) +#define pmd_ERROR(e) \ + printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) +#define pgd_ERROR(e) \ + printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) + +extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; +extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)]; +extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; +extern pmd_t empty_bad_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; + +/* + * Empty pmd entries point to the invalid_pte_table. + */ +static inline int pmd_none(pmd_t pmd) +{ + return pmd_val(pmd) == (unsigned long) invalid_pte_table; +} + +#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) + +static inline int pmd_present(pmd_t pmd) +{ + return pmd_val(pmd) != (unsigned long) invalid_pte_table; +} + +static inline void pmd_clear(pmd_t *pmdp) +{ + pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); +} + +/* + * Empty pgd entries point to the invalid_pmd_table. + */ +static inline int pgd_none(pgd_t pgd) +{ + return pgd_val(pgd) == (unsigned long) invalid_pmd_table; +} + +#define pgd_bad(pgd) (pgd_val(pgd) &~ PAGE_MASK) + +static inline int pgd_present(pgd_t pgd) +{ + return pgd_val(pgd) != (unsigned long) invalid_pmd_table; +} + +static inline void pgd_clear(pgd_t *pgdp) +{ + pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table); +} + +#ifdef CONFIG_DISCONTIGMEM + +#define pte_page(x) (NODE_MEM_MAP(PHYSADDR_TO_NID(pte_val(x))) + \ + PLAT_NODE_DATA_LOCALNR(pte_val(x), PHYSADDR_TO_NID(pte_val(x)))) + +#else +#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT))) +#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) +#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#endif + +/* + * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset + * into this range: + */ +#define pte_to_pgoff(_pte) \ + ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) + +#define pgoff_to_pte(off) \ + ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE }) + +#define __pgd_offset(address) pgd_index(address) +#define page_pte(page) page_pte_prot(page, __pgprot(0)) + +/* to find an entry in a kernel page-table-directory */ +#define pgd_offset_k(address) pgd_offset(&init_mm, 0) + +#define pgd_index(address) ((address) >> PGDIR_SHIFT) + +/* to find an entry in a page-table-directory */ +#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) + +static inline unsigned long pgd_page(pgd_t pgd) +{ + return pgd_val(pgd); +} + +/* Find an entry in the second-level page table.. */ +static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address) +{ + return (pmd_t *) pgd_page(*dir) + + ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1)); +} + +/* Find an entry in the third-level page table.. */ +#define __pte_offset(address) \ + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define pte_offset(dir, address) \ + ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address)) +#define pte_offset_kernel(dir, address) \ + ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address)) +#define pte_offset_map(dir, address) \ + ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) +#define pte_offset_map_nested(dir, address) \ + ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) +#define pte_unmap(pte) ((void)(pte)) +#define pte_unmap_nested(pte) ((void)(pte)) + +/* + * Initialize a new pgd / pmd table with invalid pointers. + */ +extern void pgd_init(unsigned long page); +extern void pmd_init(unsigned long page, unsigned long pagetable); + +extern pgd_t swapper_pg_dir[1024]; +extern void paging_init(void); + +/* + * Non-present pages: high 24 bits are offset, next 8 bits type, + * low 32 bits zero. + */ +static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) +{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; } + +#define __swp_type(x) (((x).val >> 32) & 0xff) +#define __swp_offset(x) ((x).val >> 40) +#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) + +typedef pte_t *pte_addr_t; + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_PGTABLE_64_H */ diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 6b6117f80d8..d0add5ddacd 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -3,98 +3,32 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle at alii - * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2003 Ralf Baechle */ #ifndef _ASM_PGTABLE_H #define _ASM_PGTABLE_H #include -#include -#include -#include -#include -#include - -/* - * - add_wired_entry() add a fixed TLB entry, and move wired register - */ -extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask); - -/* - * - add_temporary_entry() add a temporary TLB entry. We use TLB entries - * starting at the top and working down. This is for populating the - * TLB before trap_init() puts the TLB miss handler in place. It - * should be used only for entries matching the actual page tables, - * to prevent inconsistencies. - */ -extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask); - - -/* Basically we have the same two-level (which is the logical three level - * Linux page table layout folded) page tables as the i386. Some day - * when we have proper page coloring support we can have a 1% quicker - * tlb refill handling mechanism, but for now it is a bit slower but - * works even with the cache aliasing problem the R4k and above have. - */ - -/* PMD_SHIFT determines the size of the area a second-level page table can map */ -#ifdef CONFIG_64BIT_PHYS_ADDR -#define PMD_SHIFT 21 -#else -#define PMD_SHIFT 22 +#ifdef CONFIG_MIPS32 +#include #endif -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT PMD_SHIFT -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* - * Entries per page directory level: we use two-level, so - * we don't really have any PMD directory physically. - */ -#ifdef CONFIG_64BIT_PHYS_ADDR -#define PTRS_PER_PTE 512 -#define PTRS_PER_PMD 1 -#define PTRS_PER_PGD 2048 -#define PGD_ORDER 1 -#else -#define PTRS_PER_PTE 1024 -#define PTRS_PER_PMD 1 -#define PTRS_PER_PGD 1024 -#define PGD_ORDER 0 -#endif - -#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) -#define FIRST_USER_PGD_NR 0 - -#define VMALLOC_START KSEG2 -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) - -#if CONFIG_HIGHMEM -# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) -#else -# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) +#ifdef CONFIG_MIPS64 +#include #endif #include #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ PAGE_CACHABLE_DEFAULT) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ +#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ PAGE_CACHABLE_DEFAULT) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ PAGE_CACHABLE_DEFAULT) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT) -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ +#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ PAGE_CACHABLE_DEFAULT) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) @@ -122,18 +56,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, #define __S110 PAGE_SHARED #define __S111 PAGE_SHARED -#ifdef CONFIG_64BIT_PHYS_ADDR -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e)) -#else -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) -#endif -#define pmd_ERROR(e) \ - printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) -#define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) - /* * ZERO_PAGE is a global shared page that is always zero; used * for zero-mapped memory areas etc.. @@ -145,10 +67,6 @@ extern unsigned long zero_page_mask; #define ZERO_PAGE(vaddr) \ (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))) -extern void load_pgd(unsigned long pg_dir); - -extern pmd_t invalid_pte_table[PAGE_SIZE/sizeof(pmd_t)]; - /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. @@ -161,7 +79,8 @@ extern pmd_t invalid_pte_table[PAGE_SIZE/sizeof(pmd_t)]; #define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) -/* Certain architectures need to do special things when pte's +/* + * Certain architectures need to do special things when pte's * within a page table are directly modified. Thus, the following * hook is made available. */ @@ -199,67 +118,8 @@ static inline void pte_clear(pte_t *ptep) #define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0) #define set_pgd(pgdptr, pgdval) do { *(pgdptr) = (pgdval); } while(0) -/* - * Empty pgd/pmd entries point to the invalid_pte_table. - */ -static inline int pmd_none(pmd_t pmd) -{ - return pmd_val(pmd) == (unsigned long) invalid_pte_table; -} - -#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) - -static inline int pmd_present(pmd_t pmd) -{ - return (pmd_val(pmd) != (unsigned long) invalid_pte_table); -} - -static inline void pmd_clear(pmd_t *pmdp) -{ - pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); -} - -/* - * The "pgd_xxx()" functions here are trivial for a folded two-level - * setup: the pgd is never bad, and a pmd always exists (as it's folded - * into the pgd entry) - */ -static inline int pgd_none(pgd_t pgd) { return 0; } -static inline int pgd_bad(pgd_t pgd) { return 0; } -static inline int pgd_present(pgd_t pgd) { return 1; } -static inline void pgd_clear(pgd_t *pgdp) { } - -#define pte_page(x) pfn_to_page(pte_pfn(x)) -#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) -#define PTE_FILE_MAX_BITS 27 - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - -/* - * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset - * into this range: - */ -#define pte_to_pgoff(_pte) \ - ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 )) - -#define pgoff_to_pte(off) \ - ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE }) - -#else - -/* - * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset - * into this range: - */ -#define pte_to_pgoff(_pte) \ - ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) - -#define pgoff_to_pte(off) \ - ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE }) - -#endif +#define PTE_FILE_MAX_BITS 27 /* * The following only work if pte_present() is true. @@ -356,50 +216,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); } -#define __pgd_offset(address) pgd_index(address) -#define __pmd_offset(address) \ - (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) - -/* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) - -#define pgd_index(address) ((address) >> PGDIR_SHIFT) - -/* to find an entry in a page-table-directory */ -#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) - -/* Find an entry in the second-level page table.. */ -static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) -{ - return (pmd_t *) dir; -} - -/* Find an entry in the third-level page table.. */ -#define __pte_offset(address) \ - (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) -#define pte_offset(dir, address) \ - ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address)) -#define pte_offset_kernel(dir, address) \ - ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address)) - -#ifdef CONFIG_HIGHPTE -#define pte_offset_map(dir, address) \ - ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE0) + __pte_offset(address)) -#define pte_offset_map_nested(dir, address) \ - ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE1) + __pte_offset(address)) -#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0) -#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1) -#else -#define pte_offset_map(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) -#define pte_offset_map_nested(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) -#define pte_unmap(pte) ((void)(pte)) -#define pte_unmap_nested(pte) ((void)(pte)) -#endif - -extern pgd_t swapper_pg_dir[1024]; -extern void paging_init(void); extern void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte); @@ -413,34 +229,12 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, __update_cache(vma, address, pte); } -/* Swap entries must have VALID and GLOBAL bits cleared. */ -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - -#define __swp_type(x) (((x).val >> 1) & 0x7f) -#define __swp_offset(x) ((x).val >> 10) -#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 10) }) -#else - -#define __swp_type(x) (((x).val >> 1) & 0x1f) -#define __swp_offset(x) ((x).val >> 8) -#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) }) -#endif - -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) - - -/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ +#ifndef CONFIG_DISCONTIGMEM #define kern_addr_valid(addr) (1) +#endif #include -#ifdef CONFIG_64BIT_PHYS_ADDR -typedef u64 pte_addr_t; -#else -typedef pte_t *pte_addr_t; -#endif - /* * We provide our own get_unmapped area to cope with the virtual aliasing * constraints placed on us by the cache architecture. diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h index 2c6ccfc714b..8fce1f864ce 100644 --- a/include/asm-mips/posix_types.h +++ b/include/asm-mips/posix_types.h @@ -3,11 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle + * Copyright (C) 1996, 97, 98, 99, 2000 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_POSIX_TYPES_H #define _ASM_POSIX_TYPES_H +#include + /* * This file is generally used by user-level software, so you need to * be a little careful about namespace pollution etc. Also, we cannot @@ -17,15 +20,27 @@ typedef unsigned int __kernel_dev_t; typedef unsigned long __kernel_ino_t; typedef unsigned int __kernel_mode_t; +#if (_MIPS_SZLONG == 32) typedef unsigned long __kernel_nlink_t; +#endif +#if (_MIPS_SZLONG == 64) +typedef unsigned int __kernel_nlink_t; +#endif typedef long __kernel_off_t; typedef int __kernel_pid_t; typedef int __kernel_ipc_pid_t; typedef int __kernel_uid_t; typedef int __kernel_gid_t; +#if (_MIPS_SZLONG == 32) typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; typedef int __kernel_ptrdiff_t; +#endif +#if (_MIPS_SZLONG == 64) +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#endif typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; @@ -47,7 +62,12 @@ typedef long long __kernel_loff_t; #endif typedef struct { - long val[2]; +#if (_MIPS_SZLONG == 32) + long val[2]; +#endif +#if (_MIPS_SZLONG == 64) + int val[2]; +#endif } __kernel_fsid_t; #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 621ca21fd05..c08e0bf6e76 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -12,9 +12,6 @@ #define _ASM_PROCESSOR_H #include -#include -#include -#include /* * Return current * instruction pointer ("program counter"). @@ -27,9 +24,13 @@ #include #include -#include #include +#if defined(CONFIG_SGI_IP27) +#include +#include +#endif + /* * Descriptor for a cache */ @@ -51,21 +52,37 @@ struct cache_desc { #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ struct cpuinfo_mips { - unsigned long udelay_val; - unsigned long asid_cache; + unsigned long udelay_val; + unsigned long asid_cache; +#if defined(CONFIG_SGI_IP27) + cpuid_t p_cpuid; /* PROM assigned cpuid */ + cnodeid_t p_nodeid; /* my node ID in compact-id-space */ + nasid_t p_nasid; /* my node ID in numa-as-id-space */ + unsigned char p_slice; /* Physical position on node board */ + hub_intmasks_t p_intmasks; /* SN0 per-CPU interrupt masks */ +#endif +#if 0 + unsigned long loops_per_sec; + unsigned long ipi_count; + unsigned long irq_attempt[NR_IRQS]; + unsigned long smp_local_irq_count; + unsigned long prof_multiplier; + unsigned long prof_counter; +#endif + /* * Capability and feature descriptor structure for MIPS CPU */ - unsigned long options; - unsigned int processor_id; - unsigned int fpu_id; - unsigned int cputype; - int isa_level; - int tlbsize; - struct cache_desc icache; /* Primary I-cache */ - struct cache_desc dcache; /* Primary D or combined I/D cache */ - struct cache_desc scache; /* Secondary cache */ - struct cache_desc tcache; /* Tertiary/split secondary cache */ + unsigned long options; + unsigned int processor_id; + unsigned int fpu_id; + unsigned int cputype; + int isa_level; + int tlbsize; + struct cache_desc icache; /* Primary I-cache */ + struct cache_desc dcache; /* Primary D or combined I/D cache */ + struct cache_desc scache; /* Secondary cache */ + struct cache_desc tcache; /* Tertiary/split secondary cache */ } __attribute__((aligned(SMP_CACHE_BYTES))); /* @@ -85,12 +102,21 @@ struct cpuinfo_mips { #define cpu_has_cache_cdex (cpu_data[0].options & MIPS_CPU_CACHE_CDEX) #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) +/* no FPU exception; never set on 64-bit */ +#ifdef CONFIG_MIPS64 +#define cpu_has_nofpuex 0 +#else #define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) +#endif #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) #define cpu_has_ic_fills_f_dc (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC) +#ifdef CONFIG_MIPS64 +#define cpu_has_64bits 1 +#else #define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +#endif #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) extern struct cpuinfo_mips cpu_data[]; @@ -118,18 +144,38 @@ extern int EISA_bus; #define MCA_bus 0 #define MCA_bus__is_a_macro /* for versions in ksyms.c */ +#ifdef CONFIG_MIPS32 /* * User space process size: 2GB. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. TASK_SIZE - * for a 64 bit kernel expandable to 8192EB, of which the current MIPS - * implementations will "only" be able to use 1TB ... + * so don't change it unless you know what you are doing. */ #define TASK_SIZE 0x7fff8000UL -/* This decides where the kernel will search for a free chunk of vm +/* + * This decides where the kernel will search for a free chunk of vm * space during mmap's. */ #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) +#endif + +#ifdef CONFIG_MIPS64 +/* + * User space process size: 1TB. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. TASK_SIZE + * is limited to 1TB by the R4000 architecture; R10000 and better can + * support 16TB; the architectural reserve for future expansion is + * 8192EB ... + */ +#define TASK_SIZE32 0x7fff8000UL +#define TASK_SIZE 0x10000000000UL + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE ((current->thread.mflags & MF_32BIT_ADDR) ? \ + PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) +#endif /* * Size of io_bitmap in longwords: 32 is ports 0-0x3ff. @@ -192,11 +238,18 @@ struct thread_struct { unsigned long trap_no; #define MF_FIXADE 1 /* Fix address errors in software */ #define MF_LOGADE 2 /* Log address errors to syslog */ +#define MF_32BIT_REGS 4 /* also implies 16/32 fprs */ +#define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */ unsigned long mflags; unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_oldctx; }; +#define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR) +#define MF_O32 (MF_32BIT_REGS | MF_32BIT_ADDR) +#define MF_N32 MF_32BIT_ADDR +#define MF_N64 0 + #endif /* !__ASSEMBLY__ */ #define INIT_THREAD { \ diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 0ea92a11e78..4f816115db6 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h @@ -3,14 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000 by Ralf Baechle - * - * Machine dependent structs and defines to help the user use - * the ptrace system call. + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_PTRACE_H #define _ASM_PTRACE_H +#include + #include /* 0 - 31 are integer registers, 32 - 63 are fp registers. */ @@ -30,8 +30,10 @@ * system call/exception. As usual the registers k0/k1 aren't being saved. */ struct pt_regs { +#ifdef CONFIG_MIPS32 /* Pad bytes for argument save space on the stack. */ unsigned long pad0[6]; +#endif /* Saved main processor registers. */ unsigned long regs[32]; @@ -49,37 +51,6 @@ struct pt_regs { unsigned long cp0_cause; }; -/* Used in declaration of save_static functions. */ -#define static_unused static __attribute__((unused)) - -#define __str2(x) #x -#define __str(x) __str2(x) - -#define save_static_function(symbol) \ -__asm__ ( \ - ".text\n\t" \ - ".globl\t" #symbol "\n\t" \ - ".align\t2\n\t" \ - ".type\t" #symbol ", @function\n\t" \ - ".ent\t" #symbol ", 0\n" \ - #symbol":\n\t" \ - ".frame\t$29, 0, $31\n\t" \ - "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \ - "sw\t$17,"__str(PT_R17)"($29)\n\t" \ - "sw\t$18,"__str(PT_R18)"($29)\n\t" \ - "sw\t$19,"__str(PT_R19)"($29)\n\t" \ - "sw\t$20,"__str(PT_R20)"($29)\n\t" \ - "sw\t$21,"__str(PT_R21)"($29)\n\t" \ - "sw\t$22,"__str(PT_R22)"($29)\n\t" \ - "sw\t$23,"__str(PT_R23)"($29)\n\t" \ - "sw\t$30,"__str(PT_R30)"($29)\n\t" \ - ".end\t" #symbol "\n\t" \ - ".size\t" #symbol",. - " #symbol) - -#define save_static(frame) do { } while (0) - -#define nabi_no_regargs - #endif /* !__ASSEMBLY__ */ /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h deleted file mode 100644 index 36181de82a8..00000000000 --- a/include/asm-mips/reg.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Various register offset definitions for debuggers, core file - * examiners and whatnot. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999 by Ralf Baechle - */ -#ifndef __ASM_MIPS_REG_H -#define __ASM_MIPS_REG_H - -/* - * This defines/structures correspond to the register layout on stack - - * if the order here is changed, it needs to be updated in - * include/asm-mips/stackframe.h - */ -#define EF_REG0 6 -#define EF_REG1 7 -#define EF_REG2 8 -#define EF_REG3 9 -#define EF_REG4 10 -#define EF_REG5 11 -#define EF_REG6 12 -#define EF_REG7 13 -#define EF_REG8 14 -#define EF_REG9 15 -#define EF_REG10 16 -#define EF_REG11 17 -#define EF_REG12 18 -#define EF_REG13 19 -#define EF_REG14 20 -#define EF_REG15 21 -#define EF_REG16 22 -#define EF_REG17 23 -#define EF_REG18 24 -#define EF_REG19 25 -#define EF_REG20 26 -#define EF_REG21 27 -#define EF_REG22 28 -#define EF_REG23 29 -#define EF_REG24 30 -#define EF_REG25 31 -/* - * k0/k1 unsaved - */ -#define EF_REG28 34 -#define EF_REG29 35 -#define EF_REG30 36 -#define EF_REG31 37 - -/* - * Saved special registers - */ -#define EF_LO 38 -#define EF_HI 39 - -#define EF_CP0_EPC 40 -#define EF_CP0_BADVADDR 41 -#define EF_CP0_STATUS 42 -#define EF_CP0_CAUSE 43 - -#define EF_SIZE 180 /* size in bytes */ - -#endif /* __ASM_MIPS_REG_H */ diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h index 691d047b676..7c8ecb6b9c4 100644 --- a/include/asm-mips/regdef.h +++ b/include/asm-mips/regdef.h @@ -1,15 +1,18 @@ /* - * include/asm-mips/regdefs.h - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995 by Ralf Baechle + * Copyright (C) 1985 MIPS Computer Systems, Inc. + * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle + * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. */ +#ifndef _ASM_REGDEF_H +#define _ASM_REGDEF_H + +#include -#ifndef __ASM_MIPS_REGDEF_H -#define __ASM_MIPS_REGDEF_H +#if _MIPS_SIM == _MIPS_SIM_ABI32 /* * Symbolic register names for 32 bit ABI @@ -49,4 +52,49 @@ #define s8 $30 /* same like fp! */ #define ra $31 /* return address */ -#endif /* __ASM_MIPS_REGDEF_H */ +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ + +#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 + +#define zero $0 /* wired zero */ +#define AT $at /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value - caller saved */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ +#define ta0 $8 +#define a5 $9 +#define ta1 $9 +#define a6 $10 +#define ta2 $10 +#define a7 $11 +#define ta3 $11 +#define t0 $12 /* caller saved */ +#define t1 $13 +#define t2 $14 +#define t3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 /* callee address for PIC/temp */ +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer - caller saved for PIC */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* callee saved */ +#define ra $31 /* return address */ + +#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ + +#endif /* _ASM_REGDEF_H */ diff --git a/include/asm-mips/resource.h b/include/asm-mips/resource.h index 286b71b7057..4beb2150f37 100644 --- a/include/asm-mips/resource.h +++ b/include/asm-mips/resource.h @@ -3,7 +3,8 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 96, 98, 2000 by Ralf Baechle + * Copyright (C) 1995, 96, 98, 99, 2000 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. */ #ifndef _ASM_RESOURCE_H #define _ASM_RESOURCE_H @@ -21,17 +22,24 @@ #define RLIMIT_RSS 7 /* max resident set size */ #define RLIMIT_NPROC 8 /* max number of processes */ #define RLIMIT_MEMLOCK 9 /* max locked-in-memory address space */ -#define RLIMIT_LOCKS 10 /* maximum file locks held */ +#define RLIMIT_LOCKS 10 /* maximum file locks held */ #define RLIM_NLIMITS 11 /* Number of limit flavors. */ #ifdef __KERNEL__ +#include + /* * SuS says limits have to be unsigned. * Which makes a ton more sense anyway. */ +#ifdef CONFIG_MIPS32 #define RLIM_INFINITY 0x7fffffffUL +#endif +#ifdef CONFIG_MIPS64 +#define RLIM_INFINITY (~0UL) +#endif #define INIT_RLIMITS \ { \ diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index 52cf01ccdab..4e95feb89d1 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h @@ -6,6 +6,9 @@ * Copyright (C) 1999 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ +#ifndef _ASM_SERIAL_H +#define _ASM_SERIAL_H + #include #include @@ -16,7 +19,7 @@ * clock, since the 16550A is capable of handling a top speed of 1.5 * megabits/second; but this requires the faster clock. */ -#define BASE_BAUD ( 1843200 / 16 ) +#define BASE_BAUD (1843200 / 16) #ifndef CONFIG_OLIVETTI_M700 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know @@ -323,10 +326,14 @@ #define OCELOT_C_SERIAL2_IRQ 81 #define OCELOT_C_SERIAL2_BASE 0xfd000000 -#define _OCELOT_C_SERIAL_INIT(int, base) \ - { baud_base: OCELOT_C_BASE_BAUD, irq: int, flags: STD_COM_FLAGS,\ - iomem_base: (u8 *) base, iomem_reg_shift: 2, \ - io_type: SERIAL_IO_MEM } +#define _OCELOT_C_SERIAL_INIT(int, base) \ + { .baud_base = OCELOT_C_BASE_BAUD, \ + .irq = (int), \ + .flags = STD_COM_FLAGS, \ + .iomem_base = (u8 *) base, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM \ + } #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \ _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE) @@ -347,21 +354,95 @@ #define DDB5477_SERIAL_PORT_DEFNS #endif -#define SERIAL_PORT_DFNS \ - IVR_SERIAL_PORT_DEFNS \ - ITE_SERIAL_PORT_DEFNS \ - ATLAS_SERIAL_PORT_DEFNS \ - SEAD_SERIAL_PORT_DEFNS \ - COBALT_SERIAL_PORT_DEFNS \ - LASAT_SERIAL_PORT_DEFNS \ - EV96100_SERIAL_PORT_DEFNS \ - JAZZ_SERIAL_PORT_DEFNS \ - STD_SERIAL_PORT_DEFNS \ - EXTRA_SERIAL_PORT_DEFNS \ - HUB6_SERIAL_PORT_DFNS \ - MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ - AU1X00_SERIAL_PORT_DEFNS \ - TXX927_SERIAL_PORT_DEFNS \ +#ifdef CONFIG_SGI_IP27 + +/* + * Note about serial ports and consoles: + * For console output, everyone uses the IOC3 UARTA (offset 0x178) + * connected to the master node (look in ip27_setup_console() and + * ip27prom_console_write()). + * + * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port + * addresses on a partitioned machine. Since we currently use the ioc3 + * serial ports, we use dynamic serial port discovery that the serial.c + * driver uses for pci/pnp ports (there is an entry for the SGI ioc3 + * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater + * than UARTB's, although UARTA on o200s has traditionally been known as + * port 0. So, we just use one serial port from each ioc3 (since the + * serial driver adds addresses to get to higher ports). + * + * The first one to do a register_console becomes the preferred console + * (if there is no kernel command line console= directive). /dev/console + * (ie 5, 1) is then "aliased" into the device number returned by the + * "device" routine referred to in this console structure + * (ip27prom_console_dev). + * + * Also look in ip27-pci.c:pci_fixuop_ioc3() for some comments on working + * around ioc3 oddities in this respect. + * + * The IOC3 serials use a 22MHz clock rate with an additional divider by 3. + * (IOC3_BAUD = (22000000 / (3*16))) + * + * At the moment this is only a skeleton definition as we register all serials + * at runtime. + */ + +#define IP27_SERIAL_PORT_DEFNS +#else +#define IP27_SERIAL_PORT_DEFNS +#endif /* CONFIG_SGI_IP27 */ + +#ifdef CONFIG_SGI_IP32 + +#include + +/* + * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory + */ + +/* Standard COM flags (except for COM4, because of the 8514 problem) */ +#ifdef CONFIG_SERIAL_DETECT_IRQ +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) +#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) +#else +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF/* | ASYNC_SKIP_TEST*/) +#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF +#endif + +#define IP32_SERIAL_PORT_DEFNS \ + { .baud_base = BASE_BAUD, \ + .irq = MACEISA_SERIAL1_IRQ, \ + .flags = STD_COM_FLAGS, \ + .iomem_base = (u8*)MACE_BASE+MACEISA_SER1_BASE, \ + .iomem_reg_shift = 8, \ + .io_type = SERIAL_IO_MEM}, \ + { .baud_base = BASE_BAUD, \ + .irq = MACEISA_SERIAL2_IRQ, \ + .flags = STD_COM_FLAGS, \ + .iomem_base = (u8*)MACE_BASE+MACEISA_SER2_BASE, \ + .iomem_reg_shift = 8, \ + .io_type = SERIAL_IO_MEM}, +#else +#define IP32_SERIAL_PORT_DEFNS +#endif /* CONFIG_SGI_IP31 */ + +#define SERIAL_PORT_DFNS \ + IVR_SERIAL_PORT_DEFNS \ + ITE_SERIAL_PORT_DEFNS \ + ATLAS_SERIAL_PORT_DEFNS \ + SEAD_SERIAL_PORT_DEFNS \ + COBALT_SERIAL_PORT_DEFNS \ + LASAT_SERIAL_PORT_DEFNS \ + EV96100_SERIAL_PORT_DEFNS \ + JAZZ_SERIAL_PORT_DEFNS \ + STD_SERIAL_PORT_DEFNS \ + EXTRA_SERIAL_PORT_DEFNS \ + HUB6_SERIAL_PORT_DFNS \ + MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ + MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ + MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ + AU1X00_SERIAL_PORT_DEFNS \ + TXX927_SERIAL_PORT_DEFNS \ DDB5477_SERIAL_PORT_DEFNS + +#endif /* _ASM_SERIAL_H */ diff --git a/include/asm-mips/sfp-machine.h b/include/asm-mips/sfp-machine.h deleted file mode 100644 index 3b2a40f0e23..00000000000 --- a/include/asm-mips/sfp-machine.h +++ /dev/null @@ -1,47 +0,0 @@ -#define _FP_W_TYPE_SIZE 32 -#define _FP_W_TYPE unsigned long -#define _FP_WS_TYPE signed long -#define _FP_I_TYPE long - -#define _FP_MUL_MEAT_S(R,X,Y) \ - _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) -#define _FP_MUL_MEAT_D(R,X,Y) \ - _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) -#define _FP_MUL_MEAT_Q(R,X,Y) \ - _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) - -#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(S,R,X,Y) -#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) -#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) - -#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) -#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 -#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 -#define _FP_NANSIGN_S 0 -#define _FP_NANSIGN_D 0 -#define _FP_NANSIGN_Q 0 - -#define _FP_KEEPNANFRACP 1 -/* From my experiments it seems X is chosen unless one of the - NaNs is sNaN, in which case the result is NANSIGN/NANFRAC. */ -#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ - do { \ - if ((_FP_FRAC_HIGH_RAW_##fs(X) | \ - _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs) \ - { \ - R##_s = _FP_NANSIGN_##fs; \ - _FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \ - } \ - else \ - { \ - R##_s = X##_s; \ - _FP_FRAC_COPY_##wc(R,X); \ - } \ - R##_c = FP_CLS_NAN; \ - } while (0) - -#define FP_EX_INVALID (1 << 4) -#define FP_EX_DIVZERO (1 << 3) -#define FP_EX_OVERFLOW (1 << 2) -#define FP_EX_UNDERFLOW (1 << 1) -#define FP_EX_INEXACT (1 << 0) diff --git a/include/asm-mips/sgialib.h b/include/asm-mips/sgialib.h index a1bc4f8dd02..30b497b82a2 100644 --- a/include/asm-mips/sgialib.h +++ b/include/asm-mips/sgialib.h @@ -41,8 +41,8 @@ extern void prom_printf(char *fmt, ...); #define PROM_MAX_PMEMBLOCKS 32 struct prom_pmemblock { LONG base; /* Within KSEG0 or XKPHYS. */ - ULONG size; /* In bytes. */ - ULONG type; /* free or prom memory */ + ULONG size; /* In bytes. */ + ULONG type; /* free or prom memory */ }; /* Get next memory descriptor after CURR, returns first descriptor diff --git a/include/asm-mips/shmbuf.h b/include/asm-mips/shmbuf.h index 6d8e211eb73..f994438277b 100644 --- a/include/asm-mips/shmbuf.h +++ b/include/asm-mips/shmbuf.h @@ -7,7 +7,7 @@ * between kernel and user space. * * Pad space is left for: - * - 2 miscellaneous 32-bit values + * - 2 miscellaneous 32-bit rsp. 64-bit values */ struct shmid64_ds { diff --git a/include/asm-mips/shmiq.h b/include/asm-mips/shmiq.h deleted file mode 100644 index 80d3a5c9810..00000000000 --- a/include/asm-mips/shmiq.h +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Please note that the comments on this file may be out of date - * and that they represent what I have figured about the shmiq device - * so far in IRIX. - * - * This also contains some streams and idev bits. - * - * They may contain errors, please, refer to the source code of the Linux - * kernel for a definitive answer on what we have implemented - * - * Miguel. - */ - -/* STREAMs ioctls */ -#define STRIOC ('S' << 8) -#define I_STR (STRIOC | 010) -#define I_PUSH (STRIOC | 02) -#define I_LINK (STRIOC | 014) -#define I_UNLINK (STRIOC | 015) - -/* Data structure passed on I_STR ioctls */ -struct strioctl { - int ic_cmd; /* streams ioctl command */ - int ic_timout; /* timeout */ - int ic_len; /* lenght of data */ - void *ic_dp; /* data */ -}; - -/* - * For mapping the shared memory input queue, you have to: - * - * 1. Map /dev/zero for the number of bytes you want to use - * for your shared memory input queue plus the size of the - * sharedMemoryInputQueue structure + 4 (I still have not figured - * what this one is for - * - * 2. Open /dev/shmiq - * - * 3. Open /dev/qcntlN N is [0..Nshmiqs] - * - * 4. Fill a shmiqreq structure. user_vaddr should point to the return - * address from the /dev/zero mmap. Arg is the number of shmqevents - * that fit into the /dev/zero region (remember that at the beginning there - * is a sharedMemoryInputQueue header). - * - * 5. Issue the ioctl (qcntlfd, QIOCATTACH, &your_shmiqreq); - */ - -struct shmiqreq { - char *user_vaddr; - int arg; -}; - -/* map the shmiq into the process address space */ -#define QIOCATTACH _IOW('Q',1,struct shmiqreq) - -/* remove mappings */ -#define QIOCDETACH _IO('Q',2) - -/* - * A shared memory input queue event. - */ -struct shmqdata { - unsigned char device; /* device major */ - unsigned char which; /* device minor */ - unsigned char type; /* event type */ - unsigned char flags; /* little event data */ - union { - int pos; /* big event data */ - short ptraxis [2]; /* event data for PTR events */ - } un; -}; - -/* indetifies the shmiq and the device */ -struct shmiqlinkid { - short int devminor; - short int index; -}; - -struct shmqevent { - union { - int time; - struct shmiqlinkid id; - } un ; - struct shmqdata data ; -}; - -/* - * sharedMemoryInputQueue: this describes the shared memory input queue. - * - * head is the user index into the events, user can modify this one. - * tail is managed by the kernel. - * flags is one of SHMIQ_OVERFLOW or SHMIQ_CORRUPTED - * if OVERFLOW is set it seems ioctl QUIOCSERVICED should be called - * to notify the kernel. - * events where the kernel sticks the events. - */ -struct sharedMemoryInputQueue { - volatile int head; /* user's index into events */ - volatile int tail; /* kernel's index into events */ - volatile unsigned int flags; /* place for out-of-band data */ -#define SHMIQ_OVERFLOW 1 -#define SHMIQ_CORRUPTED 2 - struct shmqevent events[1]; /* input event buffer */ -}; - -/* have to figure this one out */ -#define QIOCGETINDX _IOWR('Q', 8, int) - - -/* acknowledge shmiq overflow */ -#define QIOCSERVICED _IO('Q', 3) - -/* Double indirect I_STR ioctl, yeah, fun fun fun */ - -struct muxioctl { - int index; /* lower stream index */ - int realcmd; /* the actual command for the subdevice */ -}; -/* Double indirect ioctl */ -#define QIOCIISTR _IOW('Q', 7, struct muxioctl) - -/* Cursor ioclts: */ - -/* set cursor tracking mode */ -#define QIOCURSTRK _IOW('Q', 4, int) - -/* set cursor filter box */ -#define QIOCURSIGN _IOW('Q', 5, int [4]) - -/* set cursor axes */ -struct shmiqsetcurs { - short index; - short axes; -}; - -#define QIOCSETCURS _IOWR('Q', 9, struct shmiqsetcurs) - -/* set cursor position */ -struct shmiqsetcpos { - short x; - short y; -}; -#define QIOCSETCPOS _IOWR('Q', 10, struct shmiqsetcpos) - -/* get time since last event */ -#define QIOCGETITIME _IOR('Q', 11, time_t) - -/* set current screen */ -#define QIOCSETSCRN _IOW('Q',6,int) - - -/* -------------------- iDev stuff -------------------- */ - -#define IDEV_MAX_NAME_LEN 15 -#define IDEV_MAX_TYPE_LEN 15 - -typedef struct { - char devName[IDEV_MAX_NAME_LEN+1]; - char devType[IDEV_MAX_TYPE_LEN+1]; - unsigned short nButtons; - unsigned short nValuators; - unsigned short nLEDs; - unsigned short nStrDpys; - unsigned short nIntDpys; - unsigned char nBells; - unsigned char flags; -#define IDEV_HAS_KEYMAP 0x01 -#define IDEV_HAS_PROXIMITY 0x02 -#define IDEV_HAS_PCKBD 0x04 -} idevDesc; - -typedef struct { - char *nothing_for_now; -} idevInfo; - -#define IDEV_KEYMAP_NAME_LEN 15 - -typedef struct { - char name[IDEV_KEYMAP_NAME_LEN+1]; -} idevKeymapDesc; - -/* The valuator definition */ -typedef struct { - unsigned hwMinRes; - unsigned hwMaxRes; - int hwMinVal; - int hwMaxVal; - - unsigned char possibleModes; -#define IDEV_ABSOLUTE 0x0 -#define IDEV_RELATIVE 0x1 -#define IDEV_EITHER 0x2 - - unsigned char mode; /* One of: IDEV_ABSOLUTE, IDEV_RELATIVE */ - - unsigned short resolution; - int minVal; - int maxVal; -} idevValuatorDesc; - -/* This is used to query a specific valuator with the IDEVGETVALUATORDESC ioctl */ -typedef struct { - short valNum; - unsigned short flags; - idevValuatorDesc desc; -} idevGetSetValDesc; - -#define IDEVGETDEVICEDESC _IOWR('i', 0, idevDesc) -#define IDEVGETVALUATORDESC _IOWR('i', 1, idevGetSetValDesc) -#define IDEVGETKEYMAPDESC _IOWR('i', 2, idevKeymapDesc) -#define IDEVINITDEVICE _IOW ('i', 51, unsigned int) - - -#ifdef __KERNEL__ - -/* These are only interpreted by SHMIQ-attacheable devices and are internal - * to the kernel - */ -#define SHMIQ_OFF _IO('Q',1) -#define SHMIQ_ON _IO('Q',2) - -void shmiq_push_event (struct shmqevent *e); -int get_sioc (struct strioctl *sioc, unsigned long arg); -#endif diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h dissimilarity index 61% index 8ce99dc5e78..09979bd2251 100644 --- a/include/asm-mips/sigcontext.h +++ b/include/asm-mips/sigcontext.h @@ -1,35 +1,90 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 2000 by Ralf Baechle - */ -#ifndef _ASM_SIGCONTEXT_H -#define _ASM_SIGCONTEXT_H - -/* - * Keep this struct definition in sync with the sigcontext fragment - * in arch/mips/tools/offset.c - */ -struct sigcontext { - unsigned int sc_regmask; /* Unused */ - unsigned int sc_status; - unsigned long long sc_pc; - unsigned long long sc_regs[32]; - unsigned long long sc_fpregs[32]; - unsigned int sc_ownedfp; /* Unused */ - unsigned int sc_fpc_csr; - unsigned int sc_fpc_eir; /* Unused */ - unsigned int sc_used_math; - unsigned int sc_ssflags; /* Unused */ - unsigned long long sc_mdhi; - unsigned long long sc_mdlo; - - unsigned int sc_cause; /* Unused */ - unsigned int sc_badvaddr; /* Unused */ - - unsigned long sc_sigset[4]; /* kernel's sigset_t */ -}; - -#endif /* _ASM_SIGCONTEXT_H */ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997, 1999 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#ifndef _ASM_SIGCONTEXT_H +#define _ASM_SIGCONTEXT_H + +#include + +#if _MIPS_SIM == _MIPS_SIM_ABI32 + +/* + * Keep this struct definition in sync with the sigcontext fragment + * in arch/mips/tools/offset.c + */ +struct sigcontext { + unsigned int sc_regmask; /* Unused */ + unsigned int sc_status; + unsigned long long sc_pc; + unsigned long long sc_regs[32]; + unsigned long long sc_fpregs[32]; + unsigned int sc_ownedfp; /* Unused */ + unsigned int sc_fpc_csr; + unsigned int sc_fpc_eir; /* Unused */ + unsigned int sc_used_math; + unsigned int sc_ssflags; /* Unused */ + unsigned long long sc_mdhi; + unsigned long long sc_mdlo; + + unsigned int sc_cause; /* Unused */ + unsigned int sc_badvaddr; /* Unused */ + + unsigned long sc_sigset[4]; /* kernel's sigset_t */ +}; + +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ + +#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 + +#include + +/* + * Keep this struct definition in sync with the sigcontext fragment + * in arch/mips/tools/offset.c + * + * Warning: this structure illdefined with sc_badvaddr being just an unsigned + * int so it was changed to unsigned long in 2.6.0-test1. This may break + * binary compatibility - no prisoners. + */ +struct sigcontext { + unsigned long sc_regs[32]; + unsigned long sc_fpregs[32]; + unsigned long sc_mdhi; + unsigned long sc_mdlo; + unsigned long sc_pc; + unsigned long sc_badvaddr; + unsigned int sc_status; + unsigned int sc_fpc_csr; + unsigned int sc_fpc_eir; + unsigned int sc_used_math; + unsigned int sc_cause; +}; + +struct sigcontext32 { + __u32 sc_regmask; /* Unused */ + __u32 sc_status; + __u64 sc_pc; + __u64 sc_regs[32]; + __u64 sc_fpregs[32]; + __u32 sc_ownedfp; /* Unused */ + __u32 sc_fpc_csr; + __u32 sc_fpc_eir; /* Unused */ + __u32 sc_used_math; + __u32 sc_ssflags; /* Unused */ + __u64 sc_mdhi; + __u64 sc_mdlo; + + __u32 sc_cause; /* Unused */ + __u32 sc_badvaddr; /* Unused */ + + __u32 sc_sigset[4]; /* kernel's sigset_t */ +}; + +#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ + +#endif /* _ASM_SIGCONTEXT_H */ diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h index a9f27578857..2137ba45836 100644 --- a/include/asm-mips/siginfo.h +++ b/include/asm-mips/siginfo.h @@ -3,12 +3,16 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1998, 1999 by Ralf Baechle + * Copyright (C) 1998, 1999, 2001 Ralf Baechle + * Copyright (C) 2000, 2001 Silicon Graphics, Inc. */ #ifndef _ASM_SIGINFO_H #define _ASM_SIGINFO_H +#include + #define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4) +#define SI_PAD_SIZE ((SI_MAX_SIZE/sizeof(int)) - 4) #define HAVE_ARCH_SIGINFO_T #define HAVE_ARCH_SIGEVENT_T @@ -22,9 +26,7 @@ struct siginfo; #include -/* The sigval union matches IRIX 32/n32 ABIs for binary compatibility. */ - -/* This structure matches IRIX 32/n32 ABIs for binary compatibility but +/* This structure matches the 32/n32 ABIs for source compatibility but has Linux extensions. */ typedef struct siginfo { @@ -65,7 +67,12 @@ typedef struct siginfo { /* SIGPOLL, SIGXFSZ (To do ...) */ struct { +#ifdef CONFIG_MIPS32 int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ +#endif +#ifdef CONFIG_MIPS64 + long _band; /* POLL_IN, POLL_OUT, POLL_MSG */ +#endif int _fd; } _sigpoll; @@ -88,6 +95,77 @@ typedef struct siginfo { } _sifields; } siginfo_t; +#if defined(__KERNEL__) && defined(CONFIG_COMPAT) + +#include + +#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3) + +typedef union sigval32 { + int sival_int; + s32 sival_ptr; +} sigval_t32; + +typedef struct siginfo32 { + int si_signo; + int si_code; + int si_errno; + + union { + int _pad[SI_PAD_SIZE32]; + + /* kill() */ + struct { + compat_pid_t _pid; /* sender's pid */ + compat_uid_t _uid; /* sender's uid */ + } _kill; + + /* SIGCHLD */ + struct { + compat_pid_t _pid; /* which child */ + compat_uid_t _uid; /* sender's uid */ + compat_clock_t _utime; + int _status; /* exit code */ + compat_clock_t _stime; + } _sigchld; + + /* IRIX SIGCHLD */ + struct { + compat_pid_t _pid; /* which child */ + compat_clock_t _utime; + int _status; /* exit code */ + compat_clock_t _stime; + } _irix_sigchld; + + /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ + struct { + s32 _addr; /* faulting insn/memory ref. */ + } _sigfault; + + /* SIGPOLL, SIGXFSZ (To do ...) */ + struct { + int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ + int _fd; + } _sigpoll; + + /* POSIX.1b timers */ + struct { + unsigned int _timer1; + unsigned int _timer2; + } _timer; + + /* POSIX.1b signals */ + struct { + compat_pid_t _pid; /* sender's pid */ + compat_uid_t _uid; /* sender's uid */ + sigval_t32 _sigval; + } _rt; + + } _sifields; +} siginfo_t32; + +#endif /* defined(__KERNEL__) && defined(CONFIG_COMPAT) */ + /* * si_code values * Again these have been choosen to be IRIX compatible. diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h index 7547fd224d5..40d73cc2a1e 100644 --- a/include/asm-mips/signal.h +++ b/include/asm-mips/signal.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 1996, 1997, 1998, 1999 by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2003 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. */ #ifndef _ASM_SIGNAL_H @@ -13,7 +13,7 @@ #include #define _NSIG 128 -#define _NSIG_BPW 32 +#define _NSIG_BPW (sizeof(unsigned long) * 8) #define _NSIG_WORDS (_NSIG / _NSIG_BPW) typedef struct { @@ -87,7 +87,7 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ #define SA_ONESHOT SA_RESETHAND #define SA_INTERRUPT 0x20000000 /* dummy -- ignored */ -#define SA_RESTORER 0x04000000 +#define SA_RESTORER 0x04000000 /* Only for o32 */ /* * sigaltstack controls diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h new file mode 100644 index 00000000000..59de82024d3 --- /dev/null +++ b/include/asm-mips/sim.h @@ -0,0 +1,97 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999, 2000, 2003 Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_SIM_H +#define _ASM_SIM_H + +#include + +#include + +#ifdef CONFIG_MIPS32 + +/* Used in declaration of save_static functions. */ +#define static_unused static __attribute__((unused)) + +#define __str2(x) #x +#define __str(x) __str2(x) + +#define save_static_function(symbol) \ +__asm__ ( \ + ".text\n\t" \ + ".globl\t" #symbol "\n\t" \ + ".align\t2\n\t" \ + ".type\t" #symbol ", @function\n\t" \ + ".ent\t" #symbol ", 0\n" \ + #symbol":\n\t" \ + ".frame\t$29, 0, $31\n\t" \ + "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \ + "sw\t$17,"__str(PT_R17)"($29)\n\t" \ + "sw\t$18,"__str(PT_R18)"($29)\n\t" \ + "sw\t$19,"__str(PT_R19)"($29)\n\t" \ + "sw\t$20,"__str(PT_R20)"($29)\n\t" \ + "sw\t$21,"__str(PT_R21)"($29)\n\t" \ + "sw\t$22,"__str(PT_R22)"($29)\n\t" \ + "sw\t$23,"__str(PT_R23)"($29)\n\t" \ + "sw\t$30,"__str(PT_R30)"($29)\n\t" \ + ".end\t" #symbol "\n\t" \ + ".size\t" #symbol",. - " #symbol) + +#define save_static(frame) do { } while (0) + +#define nabi_no_regargs + +#endif /* CONFIG_MIPS32 */ + +#ifdef CONFIG_MIPS64 + +/* Used in declaration of save_static functions. */ +#define static_unused static __attribute__((unused)) + +#define __str2(x) #x +#define __str(x) __str2(x) + +#define save_static_function(symbol) \ +__asm__ ( \ + ".text\n\t" \ + ".globl\t" #symbol "\n\t" \ + ".align\t2\n\t" \ + ".type\t" #symbol ", @function\n\t" \ + ".ent\t" #symbol ", 0\n" \ + #symbol":\n\t" \ + ".frame\t$29, 0, $31\n\t" \ + ".end\t" #symbol "\n\t" \ + ".size\t" #symbol",. - " #symbol) + +#define save_static(frame) \ + __asm__ __volatile__( \ + "sd\t$16,"__str(PT_R16)"(%0)\n\t" \ + "sd\t$17,"__str(PT_R17)"(%0)\n\t" \ + "sd\t$18,"__str(PT_R18)"(%0)\n\t" \ + "sd\t$19,"__str(PT_R19)"(%0)\n\t" \ + "sd\t$20,"__str(PT_R20)"(%0)\n\t" \ + "sd\t$21,"__str(PT_R21)"(%0)\n\t" \ + "sd\t$22,"__str(PT_R22)"(%0)\n\t" \ + "sd\t$23,"__str(PT_R23)"(%0)\n\t" \ + "sd\t$30,"__str(PT_R30)"(%0)\n\t" \ + : /* No outputs */ \ + : "r" (frame)) + +#define nabi_no_regargs \ + unsigned long __dummy0, \ + unsigned long __dummy1, \ + unsigned long __dummy2, \ + unsigned long __dummy3, \ + unsigned long __dummy4, \ + unsigned long __dummy5, \ + unsigned long __dummy6, \ + unsigned long __dummy7, + +#endif /* CONFIG_MIPS64 */ + +#endif /* _ASM_SIM_H */ diff --git a/include/asm-mips64/sn/addrs.h b/include/asm-mips/sn/addrs.h similarity index 100% rename from include/asm-mips64/sn/addrs.h rename to include/asm-mips/sn/addrs.h diff --git a/include/asm-mips64/sn/agent.h b/include/asm-mips/sn/agent.h similarity index 100% rename from include/asm-mips64/sn/agent.h rename to include/asm-mips/sn/agent.h diff --git a/include/asm-mips64/sn/arch.h b/include/asm-mips/sn/arch.h similarity index 100% rename from include/asm-mips64/sn/arch.h rename to include/asm-mips/sn/arch.h diff --git a/include/asm-mips64/sn/gda.h b/include/asm-mips/sn/gda.h similarity index 100% rename from include/asm-mips64/sn/gda.h rename to include/asm-mips/sn/gda.h diff --git a/include/asm-mips64/sn/intr.h b/include/asm-mips/sn/intr.h similarity index 100% rename from include/asm-mips64/sn/intr.h rename to include/asm-mips/sn/intr.h diff --git a/include/asm-mips64/sn/intr_public.h b/include/asm-mips/sn/intr_public.h similarity index 100% rename from include/asm-mips64/sn/intr_public.h rename to include/asm-mips/sn/intr_public.h diff --git a/include/asm-mips64/sn/io.h b/include/asm-mips/sn/io.h similarity index 90% rename from include/asm-mips64/sn/io.h rename to include/asm-mips/sn/io.h index 905f0fa8943..2b4eee31e2a 100644 --- a/include/asm-mips64/sn/io.h +++ b/include/asm-mips/sn/io.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000 Ralf Baechle + * Copyright (C) 2000, 2003 Ralf Baechle * Copyright (C) 2000 Silicon Graphics, Inc. */ #ifndef _ASM_SN_IO_H @@ -63,13 +63,6 @@ #include -#define IO_SPACE_BASE IO_BASE - -/* Because we only have PCI I/O ports. */ -#define IO_SPACE_LIMIT 0xffffffff - -/* No isa_* versions, the Origin doesn't have ISA / EISA bridges. */ - #endif /* CONFIG_SGI_IO */ #endif /* _ASM_SN_IO_H */ diff --git a/include/asm-mips64/sn/ioc3.h b/include/asm-mips/sn/ioc3.h similarity index 100% rename from include/asm-mips64/sn/ioc3.h rename to include/asm-mips/sn/ioc3.h diff --git a/include/asm-mips64/sn/klconfig.h b/include/asm-mips/sn/klconfig.h similarity index 100% rename from include/asm-mips64/sn/klconfig.h rename to include/asm-mips/sn/klconfig.h diff --git a/include/asm-mips64/sn/kldir.h b/include/asm-mips/sn/kldir.h similarity index 100% rename from include/asm-mips64/sn/kldir.h rename to include/asm-mips/sn/kldir.h diff --git a/include/asm-mips64/sn/klkernvars.h b/include/asm-mips/sn/klkernvars.h similarity index 100% rename from include/asm-mips64/sn/klkernvars.h rename to include/asm-mips/sn/klkernvars.h diff --git a/include/asm-mips64/sn/launch.h b/include/asm-mips/sn/launch.h similarity index 100% rename from include/asm-mips64/sn/launch.h rename to include/asm-mips/sn/launch.h diff --git a/include/asm-mips64/sn/mapped_kernel.h b/include/asm-mips/sn/mapped_kernel.h similarity index 100% rename from include/asm-mips64/sn/mapped_kernel.h rename to include/asm-mips/sn/mapped_kernel.h diff --git a/include/asm-mips64/sn/nmi.h b/include/asm-mips/sn/nmi.h similarity index 99% rename from include/asm-mips64/sn/nmi.h rename to include/asm-mips/sn/nmi.h index f84e700b188..6b7b0b5f372 100644 --- a/include/asm-mips64/sn/nmi.h +++ b/include/asm-mips/sn/nmi.h @@ -8,7 +8,7 @@ #ifndef __ASM_SN_NMI_H #define __ASM_SN_NMI_H -#ident "$Revision: 1.4 $" +#ident "$Revision: 1.5 $" #include diff --git a/include/asm-mips64/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h similarity index 100% rename from include/asm-mips64/sn/sn0/addrs.h rename to include/asm-mips/sn/sn0/addrs.h diff --git a/include/asm-mips64/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h similarity index 100% rename from include/asm-mips64/sn/sn0/arch.h rename to include/asm-mips/sn/sn0/arch.h diff --git a/include/asm-mips64/sn/sn0/hub.h b/include/asm-mips/sn/sn0/hub.h similarity index 100% rename from include/asm-mips64/sn/sn0/hub.h rename to include/asm-mips/sn/sn0/hub.h diff --git a/include/asm-mips64/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h similarity index 100% rename from include/asm-mips64/sn/sn0/hubio.h rename to include/asm-mips/sn/sn0/hubio.h diff --git a/include/asm-mips64/sn/sn0/hubmd.h b/include/asm-mips/sn/sn0/hubmd.h similarity index 100% rename from include/asm-mips64/sn/sn0/hubmd.h rename to include/asm-mips/sn/sn0/hubmd.h diff --git a/include/asm-mips64/sn/sn0/hubni.h b/include/asm-mips/sn/sn0/hubni.h similarity index 100% rename from include/asm-mips64/sn/sn0/hubni.h rename to include/asm-mips/sn/sn0/hubni.h diff --git a/include/asm-mips64/sn/sn0/hubpi.h b/include/asm-mips/sn/sn0/hubpi.h similarity index 100% rename from include/asm-mips64/sn/sn0/hubpi.h rename to include/asm-mips/sn/sn0/hubpi.h diff --git a/include/asm-mips64/sn/sn0/ip27.h b/include/asm-mips/sn/sn0/ip27.h similarity index 100% rename from include/asm-mips64/sn/sn0/ip27.h rename to include/asm-mips/sn/sn0/ip27.h diff --git a/include/asm-mips64/sn/sn0/sn0_fru.h b/include/asm-mips/sn/sn0/sn0_fru.h similarity index 100% rename from include/asm-mips64/sn/sn0/sn0_fru.h rename to include/asm-mips/sn/sn0/sn0_fru.h diff --git a/include/asm-mips64/sn/sn_private.h b/include/asm-mips/sn/sn_private.h similarity index 100% rename from include/asm-mips64/sn/sn_private.h rename to include/asm-mips/sn/sn_private.h diff --git a/include/asm-mips64/sn/types.h b/include/asm-mips/sn/types.h similarity index 100% rename from include/asm-mips64/sn/types.h rename to include/asm-mips/sn/types.h diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h index 7288078773e..df9fcb53d71 100644 --- a/include/asm-mips/socket.h +++ b/include/asm-mips/socket.h @@ -1,3 +1,11 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997, 1999, 2000, 2001 Ralf Baechle + * Copyright (C) 2000, 2001 Silicon Graphics, Inc. + */ #ifndef _ASM_SOCKET_H #define _ASM_SOCKET_H diff --git a/include/asm-mips/sockios.h b/include/asm-mips/sockios.h index 18ca5f9a425..87a50bf039e 100644 --- a/include/asm-mips/sockios.h +++ b/include/asm-mips/sockios.h @@ -7,8 +7,8 @@ * * Copyright (C) 1995 by Ralf Baechle */ -#ifndef __ASM_MIPS_SOCKIOS_H -#define __ASM_MIPS_SOCKIOS_H +#ifndef _ASM_SOCKIOS_H +#define _ASM_SOCKIOS_H #include @@ -22,4 +22,4 @@ #define SIOCGSTAMP 0x8906 /* Get stamp - linux-specific */ -#endif /* __ASM_MIPS_SOCKIOS_H */ +#endif /* _ASM_SOCKIOS_H */ diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 6385ffd6575..298dc4f6dd2 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -3,80 +3,101 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995, 1996, 2001 Ralf Baechle - * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. + * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle + * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. + * Copyright (C) 1999 Silicon Graphics, Inc. */ -#ifndef __ASM_STACKFRAME_H -#define __ASM_STACKFRAME_H +#ifndef _ASM_STACKFRAME_H +#define _ASM_STACKFRAME_H #include -#include -#include -#include +#include + #include +#include #include .macro SAVE_AT .set push .set noat - sw $1, PT_R1(sp) + LONG_S $1, PT_R1(sp) .set pop .endm .macro SAVE_TEMP mfhi v1 - sw $8, PT_R8(sp) - sw $9, PT_R9(sp) - sw v1, PT_HI(sp) + LONG_S $8, PT_R8(sp) + LONG_S $9, PT_R9(sp) + LONG_S v1, PT_HI(sp) mflo v1 - sw $10,PT_R10(sp) - sw $11, PT_R11(sp) - sw v1, PT_LO(sp) - sw $12, PT_R12(sp) - sw $13, PT_R13(sp) - sw $14, PT_R14(sp) - sw $15, PT_R15(sp) - sw $24, PT_R24(sp) + LONG_S $10, PT_R10(sp) + LONG_S $11, PT_R11(sp) + LONG_S v1, PT_LO(sp) + LONG_S $12, PT_R12(sp) + LONG_S $13, PT_R13(sp) + LONG_S $14, PT_R14(sp) + LONG_S $15, PT_R15(sp) + LONG_S $24, PT_R24(sp) .endm .macro SAVE_STATIC - sw $16, PT_R16(sp) - sw $17, PT_R17(sp) - sw $18, PT_R18(sp) - sw $19, PT_R19(sp) - sw $20, PT_R20(sp) - sw $21, PT_R21(sp) - sw $22, PT_R22(sp) - sw $23, PT_R23(sp) - sw $30, PT_R30(sp) + LONG_S $16, PT_R16(sp) + LONG_S $17, PT_R17(sp) + LONG_S $18, PT_R18(sp) + LONG_S $19, PT_R19(sp) + LONG_S $20, PT_R20(sp) + LONG_S $21, PT_R21(sp) + LONG_S $22, PT_R22(sp) + LONG_S $23, PT_R23(sp) + LONG_S $30, PT_R30(sp) .endm #ifdef CONFIG_SMP - .macro get_saved_sp - mfc0 k0, CP0_CONTEXT - lui k1, %hi(kernelsp) - srl k0, k0, 23 - sll k0, k0, 2 - addu k1, k0 - lw k1, %lo(kernelsp)(k1) + .macro get_saved_sp /* SMP variation */ +#ifdef CONFIG_MIPS32 + mfc0 k0, CP0_CONTEXT + lui k1, %hi(kernelsp) + srl k0, k0, 23 + sll k0, k0, 2 + addu k1, k0 + LONG_L k1, %lo(kernelsp)(k1) +#endif +#ifdef CONFIG_MIPS64 + MFC0 k1, CP0_CONTEXT + dsra k1, 23 + lui k0, %hi(pgd_current) + daddiu k0, %lo(pgd_current) + dsubu k1, k0 + lui k0, %hi(kernelsp) + daddu k1, k0 + LONG_L k1, %lo(kernelsp)(k1) +#endif .endm .macro set_saved_sp stackp temp temp2 +#ifdef CONFIG_MIPS32 mfc0 \temp, CP0_CONTEXT srl \temp, 23 sll \temp, 2 - sw \stackp, kernelsp(temp) + LONG_S \stackp, kernelsp(temp) +#endif +#ifdef CONFIG_MIPS64 + lw \temp, TI_CPU(gp) + dsll \temp, 3 + lui \temp2, %hi(kernelsp) + daddu \temp, \temp2 + LONG_S \stackp, %lo(kernelsp)(\temp) +#endif .endm #else - .macro get_saved_sp + .macro get_saved_sp /* Uniprocessor variation */ lui k1, %hi(kernelsp) - lw k1, %lo(kernelsp)(k1) + LONG_L k1, %lo(kernelsp)(k1) .endm .macro set_saved_sp stackp temp temp2 - sw \stackp, kernelsp + LONG_S \stackp, kernelsp .endm - #endif #ifdef CONFIG_PREEMPT @@ -100,29 +121,28 @@ move k1, sp .set reorder /* Called from user mode, new stack. */ - get_saved_sp -8: - move k0, sp - subu sp, k1, PT_SIZE - sw k0, PT_R29(sp) - sw $3, PT_R3(sp) - sw $0, PT_R0(sp) + get_saved_sp +8: move k0, sp + PTR_SUBU sp, k1, PT_SIZE + LONG_S k0, PT_R29(sp) + LONG_S $3, PT_R3(sp) + LONG_S $0, PT_R0(sp) mfc0 v1, CP0_STATUS - sw $2, PT_R2(sp) - sw v1, PT_STATUS(sp) - sw $4, PT_R4(sp) + LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) + LONG_S $4, PT_R4(sp) mfc0 v1, CP0_CAUSE - sw $5, PT_R5(sp) - sw v1, PT_CAUSE(sp) - sw $6, PT_R6(sp) - mfc0 v1, CP0_EPC - sw $7, PT_R7(sp) - sw v1, PT_EPC(sp) - sw $25, PT_R25(sp) - sw $28, PT_R28(sp) - sw $31, PT_R31(sp) - ori $28, sp, 0x1fff - xori $28, 0x1fff + LONG_S $5, PT_R5(sp) + LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) + MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) + LONG_S v1, PT_EPC(sp) + LONG_S $25, PT_R25(sp) + LONG_S $28, PT_R28(sp) + LONG_S $31, PT_R31(sp) + ori $28, sp, _THREAD_MASK + xori $28, _THREAD_MASK bump_lock_count .set pop .endm @@ -137,36 +157,36 @@ .macro RESTORE_AT .set push .set noat - lw $1, PT_R1(sp) + LONG_L $1, PT_R1(sp) .set pop .endm .macro RESTORE_TEMP - lw $24, PT_LO(sp) - lw $8, PT_R8(sp) - lw $9, PT_R9(sp) + LONG_L $24, PT_LO(sp) + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) mtlo $24 - lw $24, PT_HI(sp) - lw $10,PT_R10(sp) - lw $11, PT_R11(sp) + LONG_L $24, PT_HI(sp) + LONG_L $10, PT_R10(sp) + LONG_L $11, PT_R11(sp) mthi $24 - lw $12, PT_R12(sp) - lw $13, PT_R13(sp) - lw $14, PT_R14(sp) - lw $15, PT_R15(sp) - lw $24, PT_R24(sp) + LONG_L $12, PT_R12(sp) + LONG_L $13, PT_R13(sp) + LONG_L $14, PT_R14(sp) + LONG_L $15, PT_R15(sp) + LONG_L $24, PT_R24(sp) .endm .macro RESTORE_STATIC - lw $16, PT_R16(sp) - lw $17, PT_R17(sp) - lw $18, PT_R18(sp) - lw $19, PT_R19(sp) - lw $20, PT_R20(sp) - lw $21, PT_R21(sp) - lw $22, PT_R22(sp) - lw $23, PT_R23(sp) - lw $30, PT_R30(sp) + LONG_L $16, PT_R16(sp) + LONG_L $17, PT_R17(sp) + LONG_L $18, PT_R18(sp) + LONG_L $19, PT_R19(sp) + LONG_L $20, PT_R20(sp) + LONG_L $21, PT_R21(sp) + LONG_L $22, PT_R22(sp) + LONG_L $23, PT_R23(sp) + LONG_L $30, PT_R30(sp) .endm #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) @@ -181,27 +201,27 @@ mtc0 t0, CP0_STATUS li v1, 0xff00 and t0, v1 - lw v0, PT_STATUS(sp) + LONG_L v0, PT_STATUS(sp) nor v1, $0, v1 and v0, v1 or v0, t0 mtc0 v0, CP0_STATUS - lw $31, PT_R31(sp) - lw $28, PT_R28(sp) - lw $25, PT_R25(sp) - lw $7, PT_R7(sp) - lw $6, PT_R6(sp) - lw $5, PT_R5(sp) - lw $4, PT_R4(sp) - lw $3, PT_R3(sp) - lw $2, PT_R2(sp) + LONG_L $31, PT_R31(sp) + LONG_L $28, PT_R28(sp) + LONG_L $25, PT_R25(sp) + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $3, PT_R3(sp) + LONG_L $2, PT_R2(sp) .endm .macro RESTORE_SP_AND_RET .set push .set noreorder - lw k0, PT_EPC(sp) - lw sp, PT_R29(sp) + LONG_L k0, PT_EPC(sp) + LONG_L sp, PT_R29(sp) jr k0 rfe .set pop @@ -219,26 +239,26 @@ mtc0 t0, CP0_STATUS li v1, 0xff00 and t0, v1 - lw v0, PT_STATUS(sp) + LONG_L v0, PT_STATUS(sp) nor v1, $0, v1 and v0, v1 or v0, t0 mtc0 v0, CP0_STATUS - lw v1, PT_EPC(sp) - mtc0 v1, CP0_EPC - lw $31, PT_R31(sp) - lw $28, PT_R28(sp) - lw $25, PT_R25(sp) - lw $7, PT_R7(sp) - lw $6, PT_R6(sp) - lw $5, PT_R5(sp) - lw $4, PT_R4(sp) - lw $3, PT_R3(sp) - lw $2, PT_R2(sp) + LONG_L v1, PT_EPC(sp) + MTC0 v1, CP0_EPC + LONG_L $31, PT_R31(sp) + LONG_L $28, PT_R28(sp) + LONG_L $25, PT_R25(sp) + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $3, PT_R3(sp) + LONG_L $2, PT_R2(sp) .endm .macro RESTORE_SP_AND_RET - lw sp, PT_R29(sp) + LONG_L sp, PT_R29(sp) .set mips3 eret .set mips0 @@ -247,7 +267,7 @@ #endif .macro RESTORE_SP - lw sp, PT_R29(sp) + LONG_L sp, PT_R29(sp) .endm .macro RESTORE_ALL @@ -266,17 +286,16 @@ RESTORE_SP_AND_RET .endm - /* * Move to kernel mode and disable interrupts. * Set cp0 enable bit as sign that we're running on the kernel stack */ .macro CLI - mfc0 t0,CP0_STATUS - li t1,ST0_CU0|0x1f - or t0,t1 - xori t0,0x1f - mtc0 t0,CP0_STATUS + mfc0 t0, CP0_STATUS + li t1, ST0_CU0 | 0x1f + or t0, t1 + xori t0, 0x1f + mtc0 t0, CP0_STATUS .endm /* @@ -284,11 +303,11 @@ * Set cp0 enable bit as sign that we're running on the kernel stack */ .macro STI - mfc0 t0,CP0_STATUS - li t1,ST0_CU0|0x1f - or t0,t1 - xori t0,0x1e - mtc0 t0,CP0_STATUS + mfc0 t0, CP0_STATUS + li t1, ST0_CU0 | 0x1f + or t0, t1 + xori t0, 0x1e + mtc0 t0, CP0_STATUS .endm /* @@ -296,11 +315,11 @@ * Set cp0 enable bit as sign that we're running on the kernel stack */ .macro KMODE - mfc0 t0,CP0_STATUS - li t1,ST0_CU0|0x1e - or t0,t1 - xori t0,0x1e - mtc0 t0,CP0_STATUS + mfc0 t0, CP0_STATUS + li t1, ST0_CU0 | 0x1e + or t0, t1 + xori t0, 0x1e + mtc0 t0, CP0_STATUS .endm -#endif /* __ASM_STACKFRAME_H */ +#endif /* _ASM_STACKFRAME_H */ diff --git a/include/asm-mips/stat.h b/include/asm-mips/stat.h index 693b886fcd6..53ce689129a 100644 --- a/include/asm-mips/stat.h +++ b/include/asm-mips/stat.h @@ -1,8 +1,20 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1999, 2000 Ralf Baechle + * Copyright (C) 2000 Silicon Graphics, Inc. + */ #ifndef _ASM_STAT_H #define _ASM_STAT_H #include +#include + +#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32) + struct stat { dev_t st_dev; long st_pad1[3]; /* Reserved for network id */ @@ -72,4 +84,49 @@ struct stat64 { long long st_blocks; }; +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ + +#if _MIPS_SIM == _MIPS_SIM_ABI64 + +/* The memory layout is the same as of struct stat64 of the 32-bit kernel. */ +struct stat { + dev_t st_dev; + unsigned int st_pad0[3]; /* Reserved for st_dev expansion */ + + unsigned long st_ino; + + mode_t st_mode; + nlink_t st_nlink; + + uid_t st_uid; + gid_t st_gid; + + dev_t st_rdev; + unsigned int st_pad1[3]; /* Reserved for st_rdev expansion */ + + off_t st_size; + + /* + * Actually this should be timestruc_t st_atime, st_mtime and st_ctime + * but we don't have it under Linux. + */ + unsigned int st_atime; + unsigned int st_atime_nsec; + + unsigned int st_mtime; + unsigned int st_mtime_nsec; + + unsigned int st_ctime; + unsigned int st_ctime_nsec; + + unsigned int st_blksize; + unsigned int st_pad2; + + unsigned long st_blocks; +}; + +#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ + +#define STAT_HAVE_NSEC 1 + #endif /* _ASM_STAT_H */ diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h index fb56e50c2cf..58a8999eef3 100644 --- a/include/asm-mips/statfs.h +++ b/include/asm-mips/statfs.h @@ -9,6 +9,7 @@ #define _ASM_STATFS_H #include +#include #ifndef __KERNEL_STRICT_NAMES @@ -35,8 +36,10 @@ struct statfs { long f_spare[6]; }; +#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32) + /* - * Unlike the 32-bit version the 64-bit version has none of the ABI baggage. + * Unlike the traditional version the LFAPI version has none of the ABI junk */ struct statfs64 { __u32 f_type; @@ -52,4 +55,26 @@ struct statfs64 { __u32 f_spare[5]; }; +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ + +#if _MIPS_SIM == _MIPS_SIM_ABI64 + +struct statfs64 { /* Same as struct statfs */ + long f_type; + long f_bsize; + long f_frsize; /* Fragment size - unsupported */ + long f_blocks; + long f_bfree; + long f_files; + long f_ffree; + + /* Linux specials */ + long f_bavail; + __kernel_fsid_t f_fsid; + long f_namelen; + long f_spare[6]; +}; + +#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ + #endif /* _ASM_STATFS_H */ diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index ba8385541d1..c8d52f03eca 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -3,14 +3,21 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1994, 1995, 1996, 1997, 1998, 2001 Ralf Baechle + * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle + * Copyright (c) 2000 by Silicon Graphics, Inc. * Copyright (c) 2001 MIPS Technologies, Inc. */ -#ifndef __ASM_STRING_H -#define __ASM_STRING_H +#ifndef _ASM_STRING_H +#define _ASM_STRING_H #include +/* + * Most of the inline functions are rather naive implementations so I just + * didn't bother updating them for 64-bit ... + */ +#ifdef CONFIG_MIPS32 + #define __HAVE_ARCH_STRCPY static __inline__ char *strcpy(char *__dest, __const__ char *__src) { @@ -119,6 +126,7 @@ strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) return __res; } +#endif /* CONFIG_MIPS32 */ #define __HAVE_ARCH_MEMSET extern void *memset(void *__s, int __c, size_t __count); @@ -132,6 +140,7 @@ extern void *memmove(void *__dest, __const__ void *__src, size_t __n); /* Don't build bcopy at all ... */ #define __HAVE_ARCH_BCOPY +#ifdef CONFIG_MIPS32 #define __HAVE_ARCH_MEMSCAN static __inline__ void *memscan(void *__addr, int __c, size_t __size) { @@ -151,5 +160,6 @@ static __inline__ void *memscan(void *__addr, int __c, size_t __size) return __addr; } +#endif /* CONFIG_MIPS32 */ -#endif /* __ASM_STRING_H */ +#endif /* _ASM_STRING_H */ diff --git a/include/asm-mips/sysmips.h b/include/asm-mips/sysmips.h index f0d13cfd5e5..4f47b7d6a5f 100644 --- a/include/asm-mips/sysmips.h +++ b/include/asm-mips/sysmips.h @@ -7,8 +7,8 @@ * * Copyright (C) 1995 by Ralf Baechle */ -#ifndef __ASM_MIPS_SYSMIPS_H -#define __ASM_MIPS_SYSMIPS_H +#ifndef _ASM_SYSMIPS_H +#define _ASM_SYSMIPS_H /* * Commands for the sysmips(2) call @@ -22,4 +22,4 @@ #define MIPS_RDNVRAM 10 /* read NVRAM */ #define MIPS_ATOMIC_SET 2001 /* atomically set variable */ -#endif /* __ASM_MIPS_SYSMIPS_H */ +#endif /* _ASM_SYSMIPS_H */ diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 584f5e87453..c227061e39c 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -3,13 +3,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994 - 1999 by Ralf Baechle + * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle * Copyright (C) 1996 by Paul M. Antoine - * Copyright (C) 1994 - 1999 by Ralf Baechle - * - * Changed set_except_vector declaration to allow return of previous - * vector address value - necessary for "borrowing" vectors. - * + * Copyright (C) 1999 Silicon Graphics * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. */ @@ -284,12 +280,10 @@ do { \ (last) = resume(prev, next, next->thread_info); \ } while(0) -/* - * For 32 and 64 bit operands we can take advantage of ll and sc. - * FIXME: This doesn't work for R3000 machines. - */ -static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) +static inline unsigned long xchg_u32(volatile int * m, unsigned int val) { + __u32 retval; + #ifdef CONFIG_CPU_HAS_LLSC unsigned long dummy; @@ -304,31 +298,69 @@ static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) " ll\t%0, %3\n\t" "sync\n\t" ".set\tpop" - : "=&r" (val), "=m" (*m), "=&r" (dummy) + : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) : "memory"); +#else + unsigned long flags; + + local_irq_save(flags); + retval = *m; + *m = val; + local_irq_restore(flags); /* implies memory barrier */ +#endif + + return retval; +} + +#ifdef CONFIG_MIPS64 +static inline __u64 xchg_u64(volatile __u64 * m, __u64 long val) +{ + __u64 retval; + +#ifdef CONFIG_CPU_HAS_LLDSCD + unsigned long dummy; - return val; + __asm__ __volatile__( + ".set\tpush\t\t\t\t# xchg_u64\n\t" + ".set\tnoreorder\n\t" + ".set\tnomacro\n\t" + "lld\t%0, %3\n" + "1:\tmove\t%2, %z4\n\t" + "scd\t%2, %1\n\t" + "beqzl\t%2, 1b\n\t" + " lld\t%0, %3\n\t" + "sync\n\t" + ".set\tpop" + : "=&r" (retval), "=m" (*m), "=&r" (dummy) + : "R" (*m), "Jr" (val) + : "memory"); #else - unsigned long flags, retval; + unsigned long flags; local_irq_save(flags); retval = *m; *m = val; local_irq_restore(flags); /* implies memory barrier */ +#endif + return retval; -#endif /* Processor-dependent optimization */ } +#else +extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val); +#define xchg_u64 __xchg_u64_unsupported_on_32bit_kernels +#endif #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) #define tas(ptr) (xchg((ptr),1)) -static __inline__ unsigned long -__xchg(unsigned long x, volatile void * ptr, int size) +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) { switch (size) { case 4: return xchg_u32(ptr, x); + case 8: + return xchg_u64(ptr, x); } return x; } diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h index 7f2692415d7..71b712b9c9a 100644 --- a/include/asm-mips/termbits.h +++ b/include/asm-mips/termbits.h @@ -1,12 +1,11 @@ /* - * termbits stuff for Linux/MIPS. - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 1996, 2001 Ralf Baechle - * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 1995, 1996, 1999, 2001 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2001 MIPS Technologies, Inc. */ #ifndef _ASM_TERMBITS_H #define _ASM_TERMBITS_H @@ -14,8 +13,14 @@ #include typedef unsigned char cc_t; +#if (_MIPS_SZLONG == 32) typedef unsigned long speed_t; typedef unsigned long tcflag_t; +#endif +#if (_MIPS_SZLONG == 64) +typedef __u32 speed_t; +typedef __u32 tcflag_t; +#endif /* * The ABI says nothing about NCC but seems to use NCCS as @@ -27,9 +32,6 @@ struct termios { tcflag_t c_oflag; /* output mode flags */ tcflag_t c_cflag; /* control mode flags */ tcflag_t c_lflag; /* local mode flags */ - /* - * Seems nonexistent in the ABI, but Linux assumes existence ... - */ cc_t c_line; /* line discipline */ cc_t c_cc[NCCS]; /* control characters */ }; diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h index cfe73cd7350..3bf796a975d 100644 --- a/include/asm-mips/termios.h +++ b/include/asm-mips/termios.h @@ -3,7 +3,8 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 1996, 2001 by Ralf Baechle + * Copyright (C) 1995, 1996, 2000, 2001 by Ralf Baechle + * Copyright (C) 2000, 2001 Silicon Graphics, Inc. */ #ifndef _ASM_TERMIOS_H #define _ASM_TERMIOS_H diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index 99ec130a780..31536c90b7b 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -1,4 +1,4 @@ -/* thread_info.h: i386 low-level thread information +/* thread_info.h: MIPS low-level thread information * * Copyright (C) 2002 David Howells (dhowells@redhat.com) * - Incorporating suggestions made by Linus Torvalds and Dave Miller @@ -9,6 +9,8 @@ #ifdef __KERNEL__ +#include + #ifndef __ASSEMBLY__ #include @@ -62,8 +64,14 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define current_thread_info() __current_thread_info /* thread information allocation */ +#ifdef CONFIG_MIPS32 +#define THREAD_SIZE_ORDER (1) +#endif +#ifdef CONFIG_MIPS64 #define THREAD_SIZE_ORDER (1) +#endif #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) +#define THREAD_MASK (THREAD_SIZE - 1UL) #define alloc_thread_info(tsk) ((struct thread_info *) \ __get_free_pages(GFP_KERNEL,THREAD_SIZE_ORDER)) #define free_thread_info(ti) free_pages((unsigned long) (ti), THREAD_SIZE_ORDER) diff --git a/include/asm-mips/tlbflush.h b/include/asm-mips/tlbflush.h index 9ce1779d413..bb4ae3cdcbf 100644 --- a/include/asm-mips/tlbflush.h +++ b/include/asm-mips/tlbflush.h @@ -7,8 +7,8 @@ /* * TLB flushing: * - * - flush_tlb_all() flushes all processes TLBs - * - flush_tlb_mm(mm) flushes the specified mm context TLB's + * - flush_tlb_all() flushes all processes TLB entries + * - flush_tlb_mm(mm) flushes the specified mm context TLB entries * - flush_tlb_page(vma, vmaddr) flushes one page * - flush_tlb_range(vma, start, end) flushes a range of pages * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages diff --git a/include/asm-mips/topology.h b/include/asm-mips/topology.h index 592a9934af0..b383688c4ea 100644 --- a/include/asm-mips/topology.h +++ b/include/asm-mips/topology.h @@ -1,6 +1,13 @@ #ifndef __ASM_TOPOLOGY_H #define __ASM_TOPOLOGY_H +#if CONFIG_SGI_IP27 + +#include + +#define cpu_to_node(cpu) (cputocnode(cpu)) +#endif + #include #endif /* __ASM_TOPOLOGY_H */ diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h index 7f00e31e7c4..17901226300 100644 --- a/include/asm-mips/traps.h +++ b/include/asm-mips/traps.h @@ -1,6 +1,4 @@ /* - * include/asm-mips/traps.h - * * Trap handling definitions. * * Copyright (C) 2002, 2003 Maciej W. Rozycki @@ -10,8 +8,8 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ -#ifndef __ASM_MIPS_TRAPS_H -#define __ASM_MIPS_TRAPS_H +#ifndef _ASM_TRAPS_H +#define _ASM_TRAPS_H /* * Possible status responses for a board_be_handler backend. @@ -23,4 +21,4 @@ extern void (*board_be_init)(void); extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup); -#endif /* __ASM_MIPS_TRAPS_H */ +#endif /* _ASM_TRAPS_H */ diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h index 2f5d4ef94ef..f2e512303a4 100644 --- a/include/asm-mips/types.h +++ b/include/asm-mips/types.h @@ -13,7 +13,12 @@ #ifndef __ASSEMBLY__ +#ifdef CONFIG_MIPS32 typedef unsigned short umode_t; +#endif +#ifdef CONFIG_MIPS64 +typedef unsigned int umode_t; +#endif /* * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the @@ -77,13 +82,17 @@ typedef unsigned long long u64; #endif -#if defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR) +#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ + || defined(CONFIG_MIPS64) typedef u64 dma_addr_t; #else typedef u32 dma_addr_t; #endif typedef u64 dma64_addr_t; +/* + * Don't use phys_t. You've been warned. + */ #ifdef CONFIG_64BIT_PHYS_ADDR typedef unsigned long long phys_t; #else diff --git a/include/asm-mips64/uaccess.h b/include/asm-mips/uaccess.h similarity index 77% rename from include/asm-mips64/uaccess.h rename to include/asm-mips/uaccess.h index b3b8cd053bd..e167bbe31ef 100644 --- a/include/asm-mips64/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -12,9 +12,6 @@ #include #include -#define STR(x) __STR(x) -#define __STR(x) #x - /* * The fs value determines whether argument validity checking should be * performed or not. If get_fs() == USER_DS, checking is performed, with @@ -22,12 +19,48 @@ * * For historical reasons, these macros are grossly misnamed. */ +#ifdef CONFIG_MIPS32 +#define __UA_ADDR ".word" +#define __UA_LA "la" +#define __UA_ADDU "addu" + +#define KERNEL_DS ((mm_segment_t) { (unsigned long) 0L }) +#define USER_DS ((mm_segment_t) { (unsigned long) -1L }) + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +#define __access_ok(addr, size, mask) \ + (((signed long)((mask)&(addr | ((addr) + (size)) | __ua_size(size)))) >= 0) + +#define __access_mask ((long)(get_fs().seg)) + +#define access_ok(type, addr, size) \ + __access_ok(((unsigned long)(addr)),(size),__access_mask) + +#endif /* CONFIG_MIPS32 */ + +#ifdef CONFIG_MIPS64 +#define __UA_ADDR ".dword" +#define __UA_LA "dla" +#define __UA_ADDU "daddu" + #define KERNEL_DS ((mm_segment_t) { 0UL }) #define USER_DS ((mm_segment_t) { -TASK_SIZE }) #define VERIFY_READ 0 #define VERIFY_WRITE 1 +#define __access_ok(addr, size, mask) \ + (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) + +#define __access_mask get_fs().seg + +#define access_ok(type, addr, size) \ + __access_ok((unsigned long)(addr), (size), __access_mask) + +#endif /* CONFIG_MIPS64 */ + #define get_ds() (KERNEL_DS) #define get_fs() (current_thread_info()->addr_limit) #define set_fs(x) (current_thread_info()->addr_limit = (x)) @@ -44,17 +77,12 @@ * - AND "size" doesn't have any high-bits set * - AND "addr+size" doesn't have any high-bits set * - OR we are in kernel mode. + * + * __ua_size() is a trick to avoid runtime checking of positive constant + * sizes; for those we already know at compile time that the size is ok. */ #define __ua_size(size) \ - ((__builtin_constant_p(size) && (size)) > 0 ? 0 : (size)) - -#define __access_ok(addr, size, mask) \ - (((mask) & ((addr) | ((addr) + (size)) | __ua_size(size))) == 0) - -#define __access_mask get_fs().seg - -#define access_ok(type, addr, size) \ - __access_ok((unsigned long)(addr), (size), __access_mask) + ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size)) static inline int verify_area(int type, const void * addr, unsigned long size) { @@ -91,6 +119,16 @@ static inline int verify_area(int type, const void * addr, unsigned long size) struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct *)(x)) +/* + * Yuck. We need two variants, one for 64bit operation and one + * for 32 bit mode and old iron. + */ +#ifdef __mips64 +#define __GET_USER_DW __get_user_asm("ld") +#else +#define __GET_USER_DW __get_user_asm_ll32 +#endif + #define __get_user_nocheck(x,ptr,size) \ ({ \ long __gu_err; \ @@ -103,7 +141,7 @@ struct __large_struct { unsigned long buf[100]; }; case 1: __get_user_asm("lb"); break; \ case 2: __get_user_asm("lh"); break; \ case 4: __get_user_asm("lw"); break; \ - case 8: __get_user_asm("ld"); break; \ + case 8: __GET_USER_DW; break; \ default: __get_user_unknown(); break; \ } x = (__typeof__(*(ptr))) __gu_val; __gu_err; \ }) @@ -121,7 +159,7 @@ struct __large_struct { unsigned long buf[100]; }; case 1: __get_user_asm("lb"); break; \ case 2: __get_user_asm("lh"); break; \ case 4: __get_user_asm("lw"); break; \ - case 8: __get_user_asm("ld"); break; \ + case 8: __GET_USER_DW; break; \ default: __get_user_unknown(); break; \ } \ } x = (__typeof__(*(ptr))) __gu_val; __gu_err; \ @@ -139,14 +177,48 @@ struct __large_struct { unsigned long buf[100]; }; "j\t2b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ - ".dword\t1b,3b\n\t" \ + __UA_ADDR "\t1b,3b\n\t" \ ".previous" \ :"=r" (__gu_err), "=r" (__gu_val) \ :"o" (__m(__gu_addr)), "i" (-EFAULT)); \ }) +/* + * Get a long long 64 using 32 bit registers. + */ +#define __get_user_asm_ll32 \ +({ \ + __asm__ __volatile__( \ + "1:\tlw\t%1,%2\n" \ + "2:\tlw\t%D1,%3\n\t" \ + "move\t%0,$0\n" \ + "3:\t.section\t.fixup,\"ax\"\n" \ + "4:\tli\t%0,%4\n\t" \ + "move\t%1,$0\n\t" \ + "move\t%D1,$0\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + __UA_ADDR "\t1b,4b\n\t" \ + __UA_ADDR "\t2b,4b\n\t" \ + ".previous" \ + :"=r" (__gu_err), "=&r" (__gu_val) \ + :"o" (__m(__gu_addr)), "o" (__m(__gu_addr + 4)), \ + "i" (-EFAULT)); \ +}) + extern void __get_user_unknown(void); +/* + * Yuck. We need two variants, one for 64bit operation and one + * for 32 bit mode and old iron. + */ +#ifdef __mips64 +#define __PUT_USER_DW __put_user_asm("sd") +#else +#define __PUT_USER_DW __put_user_asm_ll32 +#endif + #define __put_user_nocheck(x,ptr,size) \ ({ \ long __pu_err; \ @@ -159,9 +231,10 @@ extern void __get_user_unknown(void); case 1: __put_user_asm("sb"); break; \ case 2: __put_user_asm("sh"); break; \ case 4: __put_user_asm("sw"); break; \ - case 8: __put_user_asm("sd"); break; \ + case 8: __PUT_USER_DW; break; \ default: __put_user_unknown(); break; \ - } __pu_err; \ + } \ + __pu_err; \ }) #define __put_user_check(x,ptr,size) \ @@ -172,34 +245,55 @@ extern void __get_user_unknown(void); __pu_val = (x); \ __pu_addr = (long) (ptr); \ __asm__("":"=r" (__pu_err)); \ - if (__access_ok(__pu_addr,size,__access_mask)) { \ + if (__access_ok(__pu_addr,size,__access_mask)) { \ switch (size) { \ case 1: __put_user_asm("sb"); break; \ case 2: __put_user_asm("sh"); break; \ case 4: __put_user_asm("sw"); break; \ - case 8: __put_user_asm("sd"); break; \ + case 8: __PUT_USER_DW; break; \ default: __put_user_unknown(); break; \ } \ - } __pu_err; \ + } \ + __pu_err; \ }) #define __put_user_asm(insn) \ ({ \ __asm__ __volatile__( \ "1:\t" insn "\t%z1, %2\t\t\t# __put_user_asm\n\t" \ - "move\t%0,$0\n" \ + "move\t%0, $0\n" \ "2:\n\t" \ ".section\t.fixup,\"ax\"\n" \ "3:\tli\t%0,%3\n\t" \ "j\t2b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ - ".dword\t1b,3b\n\t" \ + __UA_ADDR "\t1b,3b\n\t" \ ".previous" \ :"=r" (__pu_err) \ :"Jr" (__pu_val), "o" (__m(__pu_addr)), "i" (-EFAULT)); \ }) +#define __put_user_asm_ll32 \ +({ \ + __asm__ __volatile__( \ + "1:\tsw\t%1, %2\t\t\t# __put_user_asm_ll32\n\t" \ + "2:\tsw\t%D1, %3\n" \ + "move\t%0, $0\n" \ + "3:\n\t" \ + ".section\t.fixup,\"ax\"\n" \ + "4:\tli\t%0,%4\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + __UA_ADDR "\t1b,4b\n\t" \ + __UA_ADDR "\t2b,4b\n\t" \ + ".previous" \ + :"=r" (__pu_err) \ + :"r" (__pu_val), "o" (__m(__pu_addr)), \ + "o" (__m(__pu_addr + 4)), "i" (-EFAULT)); \ +}) + extern void __put_user_unknown(void); /* @@ -207,13 +301,13 @@ extern void __put_user_unknown(void); * jump instructions */ #ifdef MODULE -#define __MODULE_JAL(destination) \ - ".set\tnoat\n\t" \ - "dla\t$1, " #destination "\n\t" \ - "jalr\t$1\n\t" \ +#define __MODULE_JAL(destination) \ + ".set\tnoat\n\t" \ + __UA_LA "\t$1, " #destination "\n\t" \ + "jalr\t$1\n\t" \ ".set\tat\n\t" #else -#define __MODULE_JAL(destination) \ +#define __MODULE_JAL(destination) \ "jal\t" #destination "\n\t" #endif @@ -261,7 +355,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); __cu_len = (n); \ if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) \ __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, \ - __cu_len); \ + __cu_len); \ __cu_len; \ }) @@ -278,10 +372,10 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); ".set\tnoreorder\n\t" \ __MODULE_JAL(__copy_user) \ ".set\tnoat\n\t" \ - "daddu\t$1, %1, %2\n\t" \ + __UA_ADDU "\t$1, %1, %2\n\t" \ ".set\tat\n\t" \ ".set\treorder\n\t" \ - "move\t%0, $6" \ + "move\t%0, $6" /* XXX */ \ : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ : \ : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ @@ -456,13 +550,4 @@ struct exception_table_entry unsigned long nextinsn; }; -/* Returns 0 if exception not found and fixup.unit otherwise. */ -extern unsigned long search_exception_table(unsigned long addr); - -/* Returns the new pc */ -#define fixup_exception(map_reg, fixup_unit, pc) \ -({ \ - fixup_unit; \ -}) - #endif /* _ASM_UACCESS_H */ diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h dissimilarity index 69% index 3bd9d412f1d..de71d13ec5b 100644 --- a/include/asm-mips/unaligned.h +++ b/include/asm-mips/unaligned.h @@ -1,159 +1,144 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_UNALIGNED_H -#define _ASM_UNALIGNED_H - -extern void __get_unaligned_bad_length(void); -extern void __put_unaligned_bad_length(void); - -/* - * Load double unaligned. - * - * This could have been implemented in plain C like IA64 but egcs 1.0.3a - * inflates this to 23 instructions ... - */ -static inline unsigned long long __ldq_u(const unsigned long long * __addr) -{ - unsigned long long __res; - - __asm__("ulw\t%0, %1\n\t" - "ulw\t%D0, 4+%1" - : "=&r" (__res) - : "m" (*__addr)); - - return __res; -} - -/* - * Load word unaligned. - */ -static inline unsigned long __ldl_u(const unsigned int * __addr) -{ - unsigned long __res; - - __asm__("ulw\t%0,%1" - : "=&r" (__res) - : "m" (*__addr)); - - return __res; -} - -/* - * Load halfword unaligned. - */ -static inline unsigned long __ldw_u(const unsigned short * __addr) -{ - unsigned long __res; - - __asm__("ulh\t%0,%1" - : "=&r" (__res) - : "m" (*__addr)); - - return __res; -} - -/* - * Store doubleword ununaligned. - */ -static inline void __stq_u(unsigned long __val, unsigned long long * __addr) -{ - __asm__("usw\t%1, %0\n\t" - "usw\t%D1, 4+%0" - : "=m" (*__addr) - : "r" (__val)); -} - -/* - * Store long ununaligned. - */ -static inline void __stl_u(unsigned long __val, unsigned int * __addr) -{ - __asm__("usw\t%1, %0" - : "=m" (*__addr) - : "r" (__val)); -} - -/* - * Store word ununaligned. - */ -static inline void __stw_u(unsigned long __val, unsigned short * __addr) -{ - __asm__("ush\t%1, %0" - : "=m" (*__addr) - : "r" (__val)); -} - -/* - * get_unaligned - get value from possibly mis-aligned location - * @ptr: pointer to value - * - * This macro should be used for accessing values larger in size than - * single bytes at locations that are expected to be improperly aligned, - * e.g. retrieving a u16 value from a location not u16-aligned. - * - * Note that unaligned accesses can be very expensive on some architectures. - */ -#define get_unaligned(ptr) \ -({ \ - __typeof__(*(ptr)) __val; \ - \ - switch (sizeof(*(ptr))) { \ - case 1: \ - __val = *(const unsigned char *)ptr; \ - break; \ - case 2: \ - __val = __ldw_u((const unsigned short *)ptr); \ - break; \ - case 4: \ - __val = __ldl_u((const unsigned int *)ptr); \ - break; \ - case 8: \ - __val = __ldq_u((const unsigned long long *)ptr); \ - break; \ - default: \ - __get_unaligned_bad_length(); \ - break; \ - } \ - \ - __val; \ -}) - -/* - * put_unaligned - put value to a possibly mis-aligned location - * @val: value to place - * @ptr: pointer to location - * - * This macro should be used for placing values larger in size than - * single bytes at locations that are expected to be improperly aligned, - * e.g. writing a u16 value to a location not u16-aligned. - * - * Note that unaligned accesses can be very expensive on some architectures. - */ -#define put_unaligned(val,ptr) \ -do { \ - switch (sizeof(*(ptr))) { \ - case 1: \ - *(unsigned char *)(ptr) = (val); \ - break; \ - case 2: \ - __stw_u(val, (unsigned short *)(ptr)); \ - break; \ - case 4: \ - __stl_u(val, (unsigned int *)(ptr)); \ - break; \ - case 8: \ - __stq_u(val, (unsigned long long *)(ptr)); \ - break; \ - default: \ - __put_unaligned_bad_length(); \ - break; \ - } \ -} while(0) - -#endif /* _ASM_UNALIGNED_H */ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1999, 2000, 2001, 2003 by Ralf Baechle + * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. + */ +#ifndef _ASM_UNALIGNED_H +#define _ASM_UNALIGNED_H + +#include + +/* + * get_unaligned - get value from possibly mis-aligned location + * @ptr: pointer to value + * + * This macro should be used for accessing values larger in size than + * single bytes at locations that are expected to be improperly aligned, + * e.g. retrieving a u16 value from a location not u16-aligned. + * + * Note that unaligned accesses can be very expensive on some architectures. + */ +#define get_unaligned(ptr) \ + ((__typeof__(*(ptr)))__get_unaligned((ptr), sizeof(*(ptr)))) + +/* + * put_unaligned - put value to a possibly mis-aligned location + * @val: value to place + * @ptr: pointer to location + * + * This macro should be used for placing values larger in size than + * single bytes at locations that are expected to be improperly aligned, + * e.g. writing a u16 value to a location not u16-aligned. + * + * Note that unaligned accesses can be very expensive on some architectures. + */ +#define put_unaligned(x,ptr) \ + __put_unaligned((__u64)(x), (ptr), sizeof(*(ptr))) + +/* + * This is a silly but good way to make sure that + * the get/put functions are indeed always optimized, + * and that we use the correct sizes. + */ +extern void bad_unaligned_access_length(void); + +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ + +struct __una_u64 { __u64 x __attribute__((packed)); }; +struct __una_u32 { __u32 x __attribute__((packed)); }; +struct __una_u16 { __u16 x __attribute__((packed)); }; + +/* + * Elemental unaligned loads + */ + +extern inline __u64 __uldq(const __u64 * r11) +{ + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +} + +extern inline __u32 __uldl(const __u32 * r11) +{ + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +} + +extern inline __u16 __uldw(const __u16 * r11) +{ + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +} + +/* + * Elemental unaligned stores + */ + +extern inline void __ustq(__u64 r5, __u64 * r11) +{ + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +} + +extern inline void __ustl(__u32 r5, __u32 * r11) +{ + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +} + +extern inline void __ustw(__u16 r5, __u16 * r11) +{ + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +} + +extern inline __u64 __get_unaligned(const void *ptr, size_t size) +{ + __u64 val; + + switch (size) { + case 1: + val = *(const __u8 *)ptr; + break; + case 2: + val = __uldw((const __u16 *)ptr); + break; + case 4: + val = __uldl((const __u32 *)ptr); + break; + case 8: + val = __uldq((const __u64 *)ptr); + break; + default: + bad_unaligned_access_length(); + } + return val; +} + +extern inline void __put_unaligned(__u64 val, void *ptr, size_t size) +{ + switch (size) { + case 1: + *(__u8 *)ptr = (val); + break; + case 2: + __ustw(val, (__u16 *)ptr); + break; + case 4: + __ustl(val, (__u32 *)ptr); + break; + case 8: + __ustq(val, (__u64 *)ptr); + break; + default: + bad_unaligned_access_length(); + } +} + +#endif /* _ASM_UNALIGNED_H */ diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index f427e1153e2..76e5fa162f2 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -4,10 +4,21 @@ * for more details. * * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * + * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto + * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A */ #ifndef _ASM_UNISTD_H #define _ASM_UNISTD_H +#include + +#if _MIPS_SIM == _MIPS_SIM_ABI32 + +/* + * Linux o32 style syscalls are in the range from 4000 to 4999. + */ #define __NR_Linux 4000 #define __NR_syscall (__NR_Linux + 0) #define __NR_exit (__NR_Linux + 1) @@ -279,10 +290,507 @@ #define __NR_utimes (__NR_Linux + 267) /* - * Offset of the last Linux flavoured syscall + * Offset of the last Linux o32 flavoured syscall */ #define __NR_Linux_syscalls 267 +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ + +#define __NR_O32_Linux 4000 +#define __NR_O32_Linux_syscalls 267 + +#if _MIPS_SIM == _MIPS_SIM_ABI64 + +/* + * Linux 64-bit syscalls are in the range from 5000 to 5999. + */ +#define __NR_Linux 5000 +#define __NR_read (__NR_Linux + 0) +#define __NR_write (__NR_Linux + 1) +#define __NR_open (__NR_Linux + 2) +#define __NR_close (__NR_Linux + 3) +#define __NR_stat (__NR_Linux + 4) +#define __NR_fstat (__NR_Linux + 5) +#define __NR_lstat (__NR_Linux + 6) +#define __NR_poll (__NR_Linux + 7) +#define __NR_lseek (__NR_Linux + 8) +#define __NR_mmap (__NR_Linux + 9) +#define __NR_mprotect (__NR_Linux + 10) +#define __NR_munmap (__NR_Linux + 11) +#define __NR_brk (__NR_Linux + 12) +#define __NR_rt_sigaction (__NR_Linux + 13) +#define __NR_rt_sigprocmask (__NR_Linux + 14) +#define __NR_ioctl (__NR_Linux + 15) +#define __NR_pread64 (__NR_Linux + 16) +#define __NR_pwrite64 (__NR_Linux + 17) +#define __NR_readv (__NR_Linux + 18) +#define __NR_writev (__NR_Linux + 19) +#define __NR_access (__NR_Linux + 20) +#define __NR_pipe (__NR_Linux + 21) +#define __NR__newselect (__NR_Linux + 22) +#define __NR_sched_yield (__NR_Linux + 23) +#define __NR_mremap (__NR_Linux + 24) +#define __NR_msync (__NR_Linux + 25) +#define __NR_mincore (__NR_Linux + 26) +#define __NR_madvise (__NR_Linux + 27) +#define __NR_shmget (__NR_Linux + 28) +#define __NR_shmat (__NR_Linux + 29) +#define __NR_shmctl (__NR_Linux + 30) +#define __NR_dup (__NR_Linux + 31) +#define __NR_dup2 (__NR_Linux + 32) +#define __NR_pause (__NR_Linux + 33) +#define __NR_nanosleep (__NR_Linux + 34) +#define __NR_getitimer (__NR_Linux + 35) +#define __NR_setitimer (__NR_Linux + 36) +#define __NR_alarm (__NR_Linux + 37) +#define __NR_getpid (__NR_Linux + 38) +#define __NR_sendfile (__NR_Linux + 39) +#define __NR_socket (__NR_Linux + 40) +#define __NR_connect (__NR_Linux + 41) +#define __NR_accept (__NR_Linux + 42) +#define __NR_sendto (__NR_Linux + 43) +#define __NR_recvfrom (__NR_Linux + 44) +#define __NR_sendmsg (__NR_Linux + 45) +#define __NR_recvmsg (__NR_Linux + 46) +#define __NR_shutdown (__NR_Linux + 47) +#define __NR_bind (__NR_Linux + 48) +#define __NR_listen (__NR_Linux + 49) +#define __NR_getsockname (__NR_Linux + 50) +#define __NR_getpeername (__NR_Linux + 51) +#define __NR_socketpair (__NR_Linux + 52) +#define __NR_setsockopt (__NR_Linux + 53) +#define __NR_getsockopt (__NR_Linux + 54) +#define __NR_clone (__NR_Linux + 55) +#define __NR_fork (__NR_Linux + 56) +#define __NR_execve (__NR_Linux + 57) +#define __NR_exit (__NR_Linux + 58) +#define __NR_wait4 (__NR_Linux + 59) +#define __NR_kill (__NR_Linux + 60) +#define __NR_uname (__NR_Linux + 61) +#define __NR_semget (__NR_Linux + 62) +#define __NR_semop (__NR_Linux + 63) +#define __NR_semctl (__NR_Linux + 64) +#define __NR_shmdt (__NR_Linux + 65) +#define __NR_msgget (__NR_Linux + 66) +#define __NR_msgsnd (__NR_Linux + 67) +#define __NR_msgrcv (__NR_Linux + 68) +#define __NR_msgctl (__NR_Linux + 69) +#define __NR_fcntl (__NR_Linux + 70) +#define __NR_flock (__NR_Linux + 71) +#define __NR_fsync (__NR_Linux + 72) +#define __NR_fdatasync (__NR_Linux + 73) +#define __NR_truncate (__NR_Linux + 74) +#define __NR_ftruncate (__NR_Linux + 75) +#define __NR_getdents (__NR_Linux + 76) +#define __NR_getcwd (__NR_Linux + 77) +#define __NR_chdir (__NR_Linux + 78) +#define __NR_fchdir (__NR_Linux + 79) +#define __NR_rename (__NR_Linux + 80) +#define __NR_mkdir (__NR_Linux + 81) +#define __NR_rmdir (__NR_Linux + 82) +#define __NR_creat (__NR_Linux + 83) +#define __NR_link (__NR_Linux + 84) +#define __NR_unlink (__NR_Linux + 85) +#define __NR_symlink (__NR_Linux + 86) +#define __NR_readlink (__NR_Linux + 87) +#define __NR_chmod (__NR_Linux + 88) +#define __NR_fchmod (__NR_Linux + 89) +#define __NR_chown (__NR_Linux + 90) +#define __NR_fchown (__NR_Linux + 91) +#define __NR_lchown (__NR_Linux + 92) +#define __NR_umask (__NR_Linux + 93) +#define __NR_gettimeofday (__NR_Linux + 94) +#define __NR_getrlimit (__NR_Linux + 95) +#define __NR_getrusage (__NR_Linux + 96) +#define __NR_sysinfo (__NR_Linux + 97) +#define __NR_times (__NR_Linux + 98) +#define __NR_ptrace (__NR_Linux + 99) +#define __NR_getuid (__NR_Linux + 100) +#define __NR_syslog (__NR_Linux + 101) +#define __NR_getgid (__NR_Linux + 102) +#define __NR_setuid (__NR_Linux + 103) +#define __NR_setgid (__NR_Linux + 104) +#define __NR_geteuid (__NR_Linux + 105) +#define __NR_getegid (__NR_Linux + 106) +#define __NR_setpgid (__NR_Linux + 107) +#define __NR_getppid (__NR_Linux + 108) +#define __NR_getpgrp (__NR_Linux + 109) +#define __NR_setsid (__NR_Linux + 110) +#define __NR_setreuid (__NR_Linux + 111) +#define __NR_setregid (__NR_Linux + 112) +#define __NR_getgroups (__NR_Linux + 113) +#define __NR_setgroups (__NR_Linux + 114) +#define __NR_setresuid (__NR_Linux + 115) +#define __NR_getresuid (__NR_Linux + 116) +#define __NR_setresgid (__NR_Linux + 117) +#define __NR_getresgid (__NR_Linux + 118) +#define __NR_getpgid (__NR_Linux + 119) +#define __NR_setfsuid (__NR_Linux + 120) +#define __NR_setfsgid (__NR_Linux + 121) +#define __NR_getsid (__NR_Linux + 122) +#define __NR_capget (__NR_Linux + 123) +#define __NR_capset (__NR_Linux + 124) +#define __NR_rt_sigpending (__NR_Linux + 125) +#define __NR_rt_sigtimedwait (__NR_Linux + 126) +#define __NR_rt_sigqueueinfo (__NR_Linux + 127) +#define __NR_rt_sigsuspend (__NR_Linux + 128) +#define __NR_sigaltstack (__NR_Linux + 129) +#define __NR_utime (__NR_Linux + 130) +#define __NR_mknod (__NR_Linux + 131) +#define __NR_personality (__NR_Linux + 132) +#define __NR_ustat (__NR_Linux + 133) +#define __NR_statfs (__NR_Linux + 134) +#define __NR_fstatfs (__NR_Linux + 135) +#define __NR_sysfs (__NR_Linux + 136) +#define __NR_getpriority (__NR_Linux + 137) +#define __NR_setpriority (__NR_Linux + 138) +#define __NR_sched_setparam (__NR_Linux + 139) +#define __NR_sched_getparam (__NR_Linux + 140) +#define __NR_sched_setscheduler (__NR_Linux + 141) +#define __NR_sched_getscheduler (__NR_Linux + 142) +#define __NR_sched_get_priority_max (__NR_Linux + 143) +#define __NR_sched_get_priority_min (__NR_Linux + 144) +#define __NR_sched_rr_get_interval (__NR_Linux + 145) +#define __NR_mlock (__NR_Linux + 146) +#define __NR_munlock (__NR_Linux + 147) +#define __NR_mlockall (__NR_Linux + 148) +#define __NR_munlockall (__NR_Linux + 149) +#define __NR_vhangup (__NR_Linux + 150) +#define __NR_pivot_root (__NR_Linux + 151) +#define __NR__sysctl (__NR_Linux + 152) +#define __NR_prctl (__NR_Linux + 153) +#define __NR_adjtimex (__NR_Linux + 154) +#define __NR_setrlimit (__NR_Linux + 155) +#define __NR_chroot (__NR_Linux + 156) +#define __NR_sync (__NR_Linux + 157) +#define __NR_acct (__NR_Linux + 158) +#define __NR_settimeofday (__NR_Linux + 159) +#define __NR_mount (__NR_Linux + 160) +#define __NR_umount2 (__NR_Linux + 161) +#define __NR_swapon (__NR_Linux + 162) +#define __NR_swapoff (__NR_Linux + 163) +#define __NR_reboot (__NR_Linux + 164) +#define __NR_sethostname (__NR_Linux + 165) +#define __NR_setdomainname (__NR_Linux + 166) +#define __NR_create_module (__NR_Linux + 167) +#define __NR_init_module (__NR_Linux + 168) +#define __NR_delete_module (__NR_Linux + 169) +#define __NR_get_kernel_syms (__NR_Linux + 170) +#define __NR_query_module (__NR_Linux + 171) +#define __NR_quotactl (__NR_Linux + 172) +#define __NR_nfsservctl (__NR_Linux + 173) +#define __NR_getpmsg (__NR_Linux + 174) +#define __NR_putpmsg (__NR_Linux + 175) +#define __NR_afs_syscall (__NR_Linux + 176) +#define __NR_reserved177 (__NR_Linux + 177) +#define __NR_gettid (__NR_Linux + 178) +#define __NR_readahead (__NR_Linux + 179) +#define __NR_setxattr (__NR_Linux + 180) +#define __NR_lsetxattr (__NR_Linux + 181) +#define __NR_fsetxattr (__NR_Linux + 182) +#define __NR_getxattr (__NR_Linux + 183) +#define __NR_lgetxattr (__NR_Linux + 184) +#define __NR_fgetxattr (__NR_Linux + 185) +#define __NR_listxattr (__NR_Linux + 186) +#define __NR_llistxattr (__NR_Linux + 187) +#define __NR_flistxattr (__NR_Linux + 188) +#define __NR_removexattr (__NR_Linux + 189) +#define __NR_lremovexattr (__NR_Linux + 190) +#define __NR_fremovexattr (__NR_Linux + 191) +#define __NR_tkill (__NR_Linux + 192) +#define __NR_time (__NR_Linux + 193) +#define __NR_futex (__NR_Linux + 194) +#define __NR_sched_setaffinity (__NR_Linux + 195) +#define __NR_sched_getaffinity (__NR_Linux + 196) +#define __NR_cacheflush (__NR_Linux + 197) +#define __NR_cachectl (__NR_Linux + 198) +#define __NR_sysmips (__NR_Linux + 199) +#define __NR_io_setup (__NR_Linux + 200) +#define __NR_io_destroy (__NR_Linux + 201) +#define __NR_io_getevents (__NR_Linux + 202) +#define __NR_io_submit (__NR_Linux + 203) +#define __NR_io_cancel (__NR_Linux + 204) +#define __NR_exit_group (__NR_Linux + 205) +#define __NR_lookup_dcookie (__NR_Linux + 206) +#define __NR_epoll_create (__NR_Linux + 207) +#define __NR_epoll_ctl (__NR_Linux + 208) +#define __NR_epoll_wait (__NR_Linux + 209) +#define __NR_remap_file_pages (__NR_Linux + 210) +#define __NR_rt_sigreturn (__NR_Linux + 211) +#define __NR_set_tid_address (__NR_Linux + 212) +#define __NR_restart_syscall (__NR_Linux + 213) +#define __NR_semtimedop (__NR_Linux + 214) +#define __NR_fadvise64 (__NR_Linux + 215) +#define __NR_timer_create (__NR_Linux + 216) +#define __NR_timer_settime (__NR_Linux + 217) +#define __NR_timer_gettime (__NR_Linux + 218) +#define __NR_timer_getoverrun (__NR_Linux + 219) +#define __NR_timer_delete (__NR_Linux + 220) +#define __NR_clock_settime (__NR_Linux + 221) +#define __NR_clock_gettime (__NR_Linux + 222) +#define __NR_clock_getres (__NR_Linux + 223) +#define __NR_clock_nanosleep (__NR_Linux + 224) +#define __NR_tgkill (__NR_Linux + 225) +#define __NR_utimes (__NR_Linux + 226) + +/* + * Offset of the last Linux flavoured syscall + */ +#define __NR_Linux_syscalls 226 + +#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ + +#define __NR_64_Linux 5000 +#define __NR_64_Linux_syscalls 226 + +#if _MIPS_SIM == _MIPS_SIM_NABI32 + +/* + * Linux N32 syscalls are in the range from 6000 to 6999. + */ +#define __NR_Linux 6000 +#define __NR_read (__NR_Linux + 0) +#define __NR_write (__NR_Linux + 1) +#define __NR_open (__NR_Linux + 2) +#define __NR_close (__NR_Linux + 3) +#define __NR_stat (__NR_Linux + 4) +#define __NR_fstat (__NR_Linux + 5) +#define __NR_lstat (__NR_Linux + 6) +#define __NR_poll (__NR_Linux + 7) +#define __NR_lseek (__NR_Linux + 8) +#define __NR_mmap (__NR_Linux + 9) +#define __NR_mprotect (__NR_Linux + 10) +#define __NR_munmap (__NR_Linux + 11) +#define __NR_brk (__NR_Linux + 12) +#define __NR_rt_sigaction (__NR_Linux + 13) +#define __NR_rt_sigprocmask (__NR_Linux + 14) +#define __NR_ioctl (__NR_Linux + 15) +#define __NR_pread64 (__NR_Linux + 16) +#define __NR_pwrite64 (__NR_Linux + 17) +#define __NR_readv (__NR_Linux + 18) +#define __NR_writev (__NR_Linux + 19) +#define __NR_access (__NR_Linux + 20) +#define __NR_pipe (__NR_Linux + 21) +#define __NR__newselect (__NR_Linux + 22) +#define __NR_sched_yield (__NR_Linux + 23) +#define __NR_mremap (__NR_Linux + 24) +#define __NR_msync (__NR_Linux + 25) +#define __NR_mincore (__NR_Linux + 26) +#define __NR_madvise (__NR_Linux + 27) +#define __NR_shmget (__NR_Linux + 28) +#define __NR_shmat (__NR_Linux + 29) +#define __NR_shmctl (__NR_Linux + 30) +#define __NR_dup (__NR_Linux + 31) +#define __NR_dup2 (__NR_Linux + 32) +#define __NR_pause (__NR_Linux + 33) +#define __NR_nanosleep (__NR_Linux + 34) +#define __NR_getitimer (__NR_Linux + 35) +#define __NR_setitimer (__NR_Linux + 36) +#define __NR_alarm (__NR_Linux + 37) +#define __NR_getpid (__NR_Linux + 38) +#define __NR_sendfile (__NR_Linux + 39) +#define __NR_socket (__NR_Linux + 40) +#define __NR_connect (__NR_Linux + 41) +#define __NR_accept (__NR_Linux + 42) +#define __NR_sendto (__NR_Linux + 43) +#define __NR_recvfrom (__NR_Linux + 44) +#define __NR_sendmsg (__NR_Linux + 45) +#define __NR_recvmsg (__NR_Linux + 46) +#define __NR_shutdown (__NR_Linux + 47) +#define __NR_bind (__NR_Linux + 48) +#define __NR_listen (__NR_Linux + 49) +#define __NR_getsockname (__NR_Linux + 50) +#define __NR_getpeername (__NR_Linux + 51) +#define __NR_socketpair (__NR_Linux + 52) +#define __NR_setsockopt (__NR_Linux + 53) +#define __NR_getsockopt (__NR_Linux + 54) +#define __NR_clone (__NR_Linux + 55) +#define __NR_fork (__NR_Linux + 56) +#define __NR_execve (__NR_Linux + 57) +#define __NR_exit (__NR_Linux + 58) +#define __NR_wait4 (__NR_Linux + 59) +#define __NR_kill (__NR_Linux + 60) +#define __NR_uname (__NR_Linux + 61) +#define __NR_semget (__NR_Linux + 62) +#define __NR_semop (__NR_Linux + 63) +#define __NR_semctl (__NR_Linux + 64) +#define __NR_shmdt (__NR_Linux + 65) +#define __NR_msgget (__NR_Linux + 66) +#define __NR_msgsnd (__NR_Linux + 67) +#define __NR_msgrcv (__NR_Linux + 68) +#define __NR_msgctl (__NR_Linux + 69) +#define __NR_fcntl (__NR_Linux + 70) +#define __NR_flock (__NR_Linux + 71) +#define __NR_fsync (__NR_Linux + 72) +#define __NR_fdatasync (__NR_Linux + 73) +#define __NR_truncate (__NR_Linux + 74) +#define __NR_ftruncate (__NR_Linux + 75) +#define __NR_getdents (__NR_Linux + 76) +#define __NR_getcwd (__NR_Linux + 77) +#define __NR_chdir (__NR_Linux + 78) +#define __NR_fchdir (__NR_Linux + 79) +#define __NR_rename (__NR_Linux + 80) +#define __NR_mkdir (__NR_Linux + 81) +#define __NR_rmdir (__NR_Linux + 82) +#define __NR_creat (__NR_Linux + 83) +#define __NR_link (__NR_Linux + 84) +#define __NR_unlink (__NR_Linux + 85) +#define __NR_symlink (__NR_Linux + 86) +#define __NR_readlink (__NR_Linux + 87) +#define __NR_chmod (__NR_Linux + 88) +#define __NR_fchmod (__NR_Linux + 89) +#define __NR_chown (__NR_Linux + 90) +#define __NR_fchown (__NR_Linux + 91) +#define __NR_lchown (__NR_Linux + 92) +#define __NR_umask (__NR_Linux + 93) +#define __NR_gettimeofday (__NR_Linux + 94) +#define __NR_getrlimit (__NR_Linux + 95) +#define __NR_getrusage (__NR_Linux + 96) +#define __NR_sysinfo (__NR_Linux + 97) +#define __NR_times (__NR_Linux + 98) +#define __NR_ptrace (__NR_Linux + 99) +#define __NR_getuid (__NR_Linux + 100) +#define __NR_syslog (__NR_Linux + 101) +#define __NR_getgid (__NR_Linux + 102) +#define __NR_setuid (__NR_Linux + 103) +#define __NR_setgid (__NR_Linux + 104) +#define __NR_geteuid (__NR_Linux + 105) +#define __NR_getegid (__NR_Linux + 106) +#define __NR_setpgid (__NR_Linux + 107) +#define __NR_getppid (__NR_Linux + 108) +#define __NR_getpgrp (__NR_Linux + 109) +#define __NR_setsid (__NR_Linux + 110) +#define __NR_setreuid (__NR_Linux + 111) +#define __NR_setregid (__NR_Linux + 112) +#define __NR_getgroups (__NR_Linux + 113) +#define __NR_setgroups (__NR_Linux + 114) +#define __NR_setresuid (__NR_Linux + 115) +#define __NR_getresuid (__NR_Linux + 116) +#define __NR_setresgid (__NR_Linux + 117) +#define __NR_getresgid (__NR_Linux + 118) +#define __NR_getpgid (__NR_Linux + 119) +#define __NR_setfsuid (__NR_Linux + 120) +#define __NR_setfsgid (__NR_Linux + 121) +#define __NR_getsid (__NR_Linux + 122) +#define __NR_capget (__NR_Linux + 123) +#define __NR_capset (__NR_Linux + 124) +#define __NR_rt_sigpending (__NR_Linux + 125) +#define __NR_rt_sigtimedwait (__NR_Linux + 126) +#define __NR_rt_sigqueueinfo (__NR_Linux + 127) +#define __NR_rt_sigsuspend (__NR_Linux + 128) +#define __NR_sigaltstack (__NR_Linux + 129) +#define __NR_utime (__NR_Linux + 130) +#define __NR_mknod (__NR_Linux + 131) +#define __NR_personality (__NR_Linux + 132) +#define __NR_ustat (__NR_Linux + 133) +#define __NR_statfs (__NR_Linux + 134) +#define __NR_fstatfs (__NR_Linux + 135) +#define __NR_sysfs (__NR_Linux + 136) +#define __NR_getpriority (__NR_Linux + 137) +#define __NR_setpriority (__NR_Linux + 138) +#define __NR_sched_setparam (__NR_Linux + 139) +#define __NR_sched_getparam (__NR_Linux + 140) +#define __NR_sched_setscheduler (__NR_Linux + 141) +#define __NR_sched_getscheduler (__NR_Linux + 142) +#define __NR_sched_get_priority_max (__NR_Linux + 143) +#define __NR_sched_get_priority_min (__NR_Linux + 144) +#define __NR_sched_rr_get_interval (__NR_Linux + 145) +#define __NR_mlock (__NR_Linux + 146) +#define __NR_munlock (__NR_Linux + 147) +#define __NR_mlockall (__NR_Linux + 148) +#define __NR_munlockall (__NR_Linux + 149) +#define __NR_vhangup (__NR_Linux + 150) +#define __NR_pivot_root (__NR_Linux + 151) +#define __NR__sysctl (__NR_Linux + 152) +#define __NR_prctl (__NR_Linux + 153) +#define __NR_adjtimex (__NR_Linux + 154) +#define __NR_setrlimit (__NR_Linux + 155) +#define __NR_chroot (__NR_Linux + 156) +#define __NR_sync (__NR_Linux + 157) +#define __NR_acct (__NR_Linux + 158) +#define __NR_settimeofday (__NR_Linux + 159) +#define __NR_mount (__NR_Linux + 160) +#define __NR_umount2 (__NR_Linux + 161) +#define __NR_swapon (__NR_Linux + 162) +#define __NR_swapoff (__NR_Linux + 163) +#define __NR_reboot (__NR_Linux + 164) +#define __NR_sethostname (__NR_Linux + 165) +#define __NR_setdomainname (__NR_Linux + 166) +#define __NR_create_module (__NR_Linux + 167) +#define __NR_init_module (__NR_Linux + 168) +#define __NR_delete_module (__NR_Linux + 169) +#define __NR_get_kernel_syms (__NR_Linux + 170) +#define __NR_query_module (__NR_Linux + 171) +#define __NR_quotactl (__NR_Linux + 172) +#define __NR_nfsservctl (__NR_Linux + 173) +#define __NR_getpmsg (__NR_Linux + 174) +#define __NR_putpmsg (__NR_Linux + 175) +#define __NR_afs_syscall (__NR_Linux + 176) +#define __NR_reserved177 (__NR_Linux + 177) +#define __NR_gettid (__NR_Linux + 178) +#define __NR_readahead (__NR_Linux + 179) +#define __NR_setxattr (__NR_Linux + 180) +#define __NR_lsetxattr (__NR_Linux + 181) +#define __NR_fsetxattr (__NR_Linux + 182) +#define __NR_getxattr (__NR_Linux + 183) +#define __NR_lgetxattr (__NR_Linux + 184) +#define __NR_fgetxattr (__NR_Linux + 185) +#define __NR_listxattr (__NR_Linux + 186) +#define __NR_llistxattr (__NR_Linux + 187) +#define __NR_flistxattr (__NR_Linux + 188) +#define __NR_removexattr (__NR_Linux + 189) +#define __NR_lremovexattr (__NR_Linux + 190) +#define __NR_fremovexattr (__NR_Linux + 191) +#define __NR_tkill (__NR_Linux + 192) +#define __NR_time (__NR_Linux + 193) +#define __NR_futex (__NR_Linux + 194) +#define __NR_sched_setaffinity (__NR_Linux + 195) +#define __NR_sched_getaffinity (__NR_Linux + 196) +#define __NR_cacheflush (__NR_Linux + 197) +#define __NR_cachectl (__NR_Linux + 198) +#define __NR_sysmips (__NR_Linux + 199) +#define __NR_io_setup (__NR_Linux + 200) +#define __NR_io_destroy (__NR_Linux + 201) +#define __NR_io_getevents (__NR_Linux + 202) +#define __NR_io_submit (__NR_Linux + 203) +#define __NR_io_cancel (__NR_Linux + 204) +#define __NR_exit_group (__NR_Linux + 205) +#define __NR_lookup_dcookie (__NR_Linux + 206) +#define __NR_epoll_create (__NR_Linux + 207) +#define __NR_epoll_ctl (__NR_Linux + 208) +#define __NR_epoll_wait (__NR_Linux + 209) +#define __NR_remap_file_pages (__NR_Linux + 210) +#define __NR_rt_sigreturn (__NR_Linux + 211) +#define __NR_fcntl64 (__NR_Linux + 212) +#define __NR_set_tid_address (__NR_Linux + 213) +#define __NR_restart_syscall (__NR_Linux + 214) +#define __NR_semtimedop (__NR_Linux + 215) +#define __NR_fadvise64 (__NR_Linux + 216) +#define __NR_statfs64 (__NR_Linux + 217) +#define __NR_fstatfs64 (__NR_Linux + 218) +#define __NR_sendfile64 (__NR_Linux + 219) +#define __NR_timer_create (__NR_Linux + 221) +#define __NR_timer_settime (__NR_Linux + 222) +#define __NR_timer_gettime (__NR_Linux + 223) +#define __NR_timer_getoverrun (__NR_Linux + 224) +#define __NR_timer_delete (__NR_Linux + 225) +#define __NR_clock_settime (__NR_Linux + 226) +#define __NR_clock_gettime (__NR_Linux + 227) +#define __NR_clock_getres (__NR_Linux + 228) +#define __NR_clock_nanosleep (__NR_Linux + 229) +#define __NR_tgkill (__NR_Linux + 230) +#define __NR_utimes (__NR_Linux + 231) + +/* + * Offset of the last N32 flavoured syscall + */ +#define __NR_Linux_syscalls 231 + +#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ + +#define __NR_N32_Linux 6000 +#define __NR_N32_Linux_syscalls 231 + #ifndef __ASSEMBLY__ /* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ @@ -409,6 +917,8 @@ type name(atype a, btype b, ctype c, dtype d) \ return -1; \ } +#if (_MIPS_SIM == _MIPS_SIM_ABIN32) + /* * Using those means your brain needs more than an oil change ;-) */ @@ -475,6 +985,66 @@ type name(atype a, btype b, ctype c, dtype d, etype e, ftype f) \ return -1; \ } +#endif /* (_MIPS_SIM == _MIPS_SIM_ABIN32) */ + +#if (_MIPS_SIM == _MIPS_SIM_NABIN32) || (_MIPS_SIM == _MIPS_SIM_ABI64) + +#define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ +type name (atype a,btype b,ctype c,dtype d,etype e) \ +{ \ + register unsigned long __a0 asm("$4") = (unsigned long) a; \ + register unsigned long __a1 asm("$5") = (unsigned long) b; \ + register unsigned long __a2 asm("$6") = (unsigned long) c; \ + register unsigned long __a3 asm("$7") = (unsigned long) d; \ + register unsigned long __a4 asm("$8") = (unsigned long) e; \ + unsigned long __v0; \ + \ + __asm__ volatile ( \ + ".set\tnoreorder\n\t" \ + "li\t$2, %6\t\t\t# " #name "\n\t" \ + "syscall\n\t" \ + "move\t%0, $2\n\t" \ + ".set\treorder" \ + : "=&r" (__v0), "+r" (__a3), "+r" (__a4) \ + : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \ + : "$2","$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ + \ + if (__a3 == 0) \ + return (type) __v0; \ + errno = __v0; \ + return -1; \ +} + +#define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \ +type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \ +{ \ + register unsigned long __a0 asm("$4") = (unsigned long) a; \ + register unsigned long __a1 asm("$5") = (unsigned long) b; \ + register unsigned long __a2 asm("$6") = (unsigned long) c; \ + register unsigned long __a3 asm("$7") = (unsigned long) d; \ + register unsigned long __a4 asm("$8") = (unsigned long) e; \ + register unsigned long __a5 asm("$9") = (unsigned long) f; \ + unsigned long __v0; \ + \ + __asm__ volatile ( \ + ".set\tnoreorder\n\t" \ + "li\t$2, %6\t\t\t# " #name "\n\t" \ + "syscall\n\t" \ + "move\t%0, $2\n\t" \ + ".set\treorder" \ + : "=&r" (__v0), "+r" (__a3) \ + : "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "r" (__a5), \ + "i" (__NR_##name) \ + : "$2","$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ + \ + if (__a3 == 0) \ + return (type) __v0; \ + errno = __v0; \ + return -1; \ +} + +#endif /* (_MIPS_SIM == _MIPS_SIM_NABIN32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */ + #ifdef __KERNEL_SYSCALLS__ /* @@ -499,7 +1069,13 @@ static inline _syscall3(int,execve,const char *,file,char **,argv,char **,envp) static inline _syscall3(int,open,const char *,file,int,flag,int,mode) static inline _syscall1(int,close,int,fd) static inline _syscall1(int,_exit,int,exitcode) -static inline _syscall3(pid_t,waitpid,pid_t,pid,int *,wait_stat,int,options) +struct rusage; +static inline _syscall4(pid_t,wait4,pid_t,pid,int *,stat_addr,int,options,struct rusage *,ru) + +static inline pid_t waitpid(int pid, int * wait_stat, int flags) +{ + return wait4(pid, wait_stat, flags, NULL); +} #endif /* __KERNEL_SYSCALLS__ */ #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-mips/user.h b/include/asm-mips/user.h index 3e55ed5466d..89bf8b4cab3 100644 --- a/include/asm-mips/user.h +++ b/include/asm-mips/user.h @@ -1,5 +1,12 @@ -#ifndef __ASM_MIPS_USER_H -#define __ASM_MIPS_USER_H +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle + */ +#ifndef _ASM_USER_H +#define _ASM_USER_H #include #include @@ -28,7 +35,8 @@ * to write an integer number of pages. */ struct user { - unsigned long regs[EF_SIZE/4+64]; /* integer and fp regs */ + unsigned long regs[EF_SIZE / /* integer and fp regs */ + sizeof(unsigned long) + 64]; size_t u_tsize; /* text size (pages) */ size_t u_dsize; /* data size (pages) */ size_t u_ssize; /* stack size (pages) */ @@ -47,4 +55,4 @@ struct user { #define HOST_DATA_START_ADDR (u.start_data) #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) -#endif /* __ASM_MIPS_USER_H */ +#endif /* _ASM_USER_H */ diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h index 337d8af5426..6aa90cae111 100644 --- a/include/asm-mips/watch.h +++ b/include/asm-mips/watch.h @@ -5,8 +5,8 @@ * * Copyright (C) 1996, 1997, 1998, 2000, 2001 by Ralf Baechle */ -#ifndef __ASM_WATCH_H -#define __ASM_WATCH_H +#ifndef _ASM_WATCH_H +#define _ASM_WATCH_H #include @@ -32,4 +32,4 @@ extern asmlinkage void __watch_reenable(void); if (cpu_has_watch) \ __watch_reenable() -#endif /* __ASM_WATCH_H */ +#endif /* _ASM_WATCH_H */ diff --git a/include/asm-mips/wbflush.h b/include/asm-mips/wbflush.h index 8aac7ea7b6f..c3bef50f37a 100644 --- a/include/asm-mips/wbflush.h +++ b/include/asm-mips/wbflush.h @@ -8,8 +8,8 @@ * Copyright (c) 1998 Harald Koerfgen * Copyright (C) 2002 Maciej W. Rozycki */ -#ifndef __ASM_MIPS_WBFLUSH_H -#define __ASM_MIPS_WBFLUSH_H +#ifndef _ASM_WBFLUSH_H +#define _ASM_WBFLUSH_H #include @@ -32,4 +32,4 @@ extern void wbflush_setup(void); #endif /* !CONFIG_CPU_HAS_WB */ -#endif /* __ASM_MIPS_WBFLUSH_H */ +#endif /* _ASM_WBFLUSH_H */ diff --git a/include/asm-mips64/xtalk/xtalk.h b/include/asm-mips/xtalk/xtalk.h similarity index 100% rename from include/asm-mips64/xtalk/xtalk.h rename to include/asm-mips/xtalk/xtalk.h diff --git a/include/asm-mips64/xtalk/xwidget.h b/include/asm-mips/xtalk/xwidget.h similarity index 100% rename from include/asm-mips64/xtalk/xwidget.h rename to include/asm-mips/xtalk/xwidget.h diff --git a/include/asm-mips64/.cvsignore b/include/asm-mips64/.cvsignore deleted file mode 100644 index cd157aea989..00000000000 --- a/include/asm-mips64/.cvsignore +++ /dev/null @@ -1 +0,0 @@ -offset.h diff --git a/include/asm-mips64/a.out.h b/include/asm-mips64/a.out.h deleted file mode 100644 index 92c10e3cd08..00000000000 --- a/include/asm-mips64/a.out.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999 by Ralf Baechle - */ -#ifndef _ASM_A_OUT_H -#define _ASM_A_OUT_H - -struct exec -{ - unsigned long a_info; /* Use macros N_MAGIC, etc for access */ - unsigned a_text; /* length of text, in bytes */ - unsigned a_data; /* length of data, in bytes */ - unsigned a_bss; /* length of uninitialized data area for file, in bytes */ - unsigned a_syms; /* length of symbol table data in file, in bytes */ - unsigned a_entry; /* start address */ - unsigned a_trsize; /* length of relocation info for text, in bytes */ - unsigned a_drsize; /* length of relocation info for data, in bytes */ -}; - -#define N_TRSIZE(a) ((a).a_trsize) -#define N_DRSIZE(a) ((a).a_drsize) -#define N_SYMSIZE(a) ((a).a_syms) - -#ifdef __KERNEL__ - -#define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE) - -#endif - -#endif /* _ASM_A_OUT_H */ diff --git a/include/asm-mips64/arc/types.h b/include/asm-mips64/arc/types.h deleted file mode 100644 index 79ca5d9da1f..00000000000 --- a/include/asm-mips64/arc/types.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright 1999 Ralf Baechle (ralf@gnu.org) - * Copyright 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_ARC_TYPES_H -#define _ASM_ARC_TYPES_H - -#include - -#ifdef CONFIG_ARC32 - -typedef char CHAR; -typedef short SHORT; -typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__))); -typedef long LONG __attribute__ ((__mode__ (__SI__))); -typedef unsigned char UCHAR; -typedef unsigned short USHORT; -typedef unsigned long ULONG __attribute__ ((__mode__ (__SI__))); -typedef void VOID; - -/* The pointer types. Note that we're using a 64-bit compiler but all - pointer in the ARC structures are only 32-bit, so we need some disgusting - workarounds. Keep your vomit bag handy. */ -typedef LONG _PCHAR; -typedef LONG _PSHORT; -typedef LONG _PLARGE_INTEGER; -typedef LONG _PLONG; -typedef LONG _PUCHAR; -typedef LONG _PUSHORT; -typedef LONG _PULONG; -typedef LONG _PVOID; - -#endif /* CONFIG_ARC32 */ - -#ifdef CONFIG_ARC64 - -typedef char CHAR; -typedef short SHORT; -typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__))); -typedef long LONG __attribute__ ((__mode__ (__DI__))); -typedef unsigned char UCHAR; -typedef unsigned short USHORT; -typedef unsigned long ULONG __attribute__ ((__mode__ (__DI__))); -typedef void VOID; - -/* The pointer types. We're 64-bit and the firmware is also 64-bit, so - live is sane ... */ -typedef CHAR *_PCHAR; -typedef SHORT *_PSHORT; -typedef LARGE_INTEGER *_PLARGE_INTEGER; -typedef LONG *_PLONG; -typedef UCHAR *_PUCHAR; -typedef USHORT *_PUSHORT; -typedef ULONG *_PULONG; -typedef VOID *_PVOID; - -#endif /* CONFIG_ARC64 */ - -typedef CHAR *PCHAR; -typedef SHORT *PSHORT; -typedef LARGE_INTEGER *PLARGE_INTEGER; -typedef LONG *PLONG; -typedef UCHAR *PUCHAR; -typedef USHORT *PUSHORT; -typedef ULONG *PULONG; -typedef VOID *PVOID; - -#endif /* _ASM_ARC_TYPES_H */ diff --git a/include/asm-mips64/asm.h b/include/asm-mips64/asm.h deleted file mode 100644 index c3c64aedd23..00000000000 --- a/include/asm-mips64/asm.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle - * Copyright (C) 1999 by Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - * Copyright (C) 2002 Maciej W. Rozycki - * - * Some useful macros for MIPS assembler code - * - * Some of the routines below contain useless nops that will be optimized - * away by gas in -O mode. These nops are however required to fill delay - * slots in noreorder mode. - */ -#ifndef __ASM_ASM_H -#define __ASM_ASM_H - -#include - -/* - * PIC specific declarations - * Not used for the kernel but here seems to be the right place. - */ -#ifdef __PIC__ -#define CPRESTORE(register) \ - .cprestore register -#define CPADD(register) \ - .cpadd register -#define CPLOAD(register) \ - .cpload register -#else -#define CPRESTORE(register) -#define CPADD(register) -#define CPLOAD(register) -#endif - -/* - * LEAF - declare leaf routine - */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp,0,ra - -/* - * NESTED - declare nested routine entry point - */ -#define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp, framesize, rpc - -/* - * END - mark end of function - */ -#define END(function) \ - .end function; \ - .size function,.-function - -/* - * EXPORT - export definition of symbol - */ -#define EXPORT(symbol) \ - .globl symbol; \ -symbol: - -/* - * FEXPORT - export definition of a function symbol - */ -#define FEXPORT(symbol) \ - .globl symbol; \ - .type symbol,@function; \ -symbol: - -/* - * ABS - export absolute symbol - */ -#define ABS(symbol,value) \ - .globl symbol; \ -symbol = value - -#define PANIC(msg) \ - .set push; \ - .set reorder; \ - PTR_LA a0,8f; \ - jal panic; \ -9: b 9b; \ - .set pop; \ - TEXT(msg) - -/* - * Print formatted string - */ -#define PRINT(string) \ - .set push; \ - .set reorder; \ - PTR_LA a0,8f; \ - jal printk; \ - .set pop; \ - TEXT(string) - -#define TEXT(msg) \ - .pushsection .data; \ -8: .asciiz msg; \ - .popsection; - -/* - * Build text tables - */ -#define TTABLE(string) \ - .pushsection .text; \ - .word 1f; \ - .popsection \ - .pushsection .data; \ -1: .asciiz string; \ - .popsection - -/* - * MIPS IV pref instruction. - * Use with .set noreorder only! - * - * MIPS IV implementations are free to treat this as a nop. The R5000 - * is one of them. So we should have an option not to use this instruction. - */ -#ifdef CONFIG_CPU_HAS_PREFETCH - -#define PREF(hint,addr) \ - pref hint,addr - -#define PREFX(hint,addr) \ - prefx hint,addr - -#else /* !CONFIG_CPU_HAS_PREFETCH */ - -#define PREF(hint,addr) -#define PREFX(hint,addr) - -#endif /* !CONFIG_CPU_HAS_PREFETCH */ - -/* - * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. - */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) -#define MOVN(rd,rs,rt) \ - .set push; \ - .set reorder; \ - beqz rt,9f; \ - move rd,rs; \ - .set pop; \ -9: -#define MOVZ(rd,rs,rt) \ - .set push; \ - .set reorder; \ - bnez rt,9f; \ - move rd,rs; \ - .set pop; \ -9: -#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) -#define MOVN(rd,rs,rt) \ - .set push; \ - .set noreorder; \ - bnezl rt,9f; \ - move rd,rs; \ - .set pop; \ -9: -#define MOVZ(rd,rs,rt) \ - .set push; \ - .set noreorder; \ - beqzl rt,9f; \ - move rd,rs; \ - .set pop; \ -9: -#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MOVN(rd,rs,rt) \ - movn rd,rs,rt -#define MOVZ(rd,rs,rt) \ - movz rd,rs,rt -#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ - -/* - * Stack alignment - */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) -#define ALSZ 7 -#define ALMASK ~7 -#endif -#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define ALSZ 15 -#define ALMASK ~15 -#endif - -/* - * Macros to handle different pointer/register sizes for 32/64-bit code - */ - -/* - * Size of a register - */ -#ifdef __mips64 -#define SZREG 8 -#else -#define SZREG 4 -#endif - -/* - * Use the following macros in assemblercode to load/store registers, - * pointers etc. - */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) -#define REG_S sw -#define REG_L lw -#define REG_SUBU subu -#define REG_ADDU addu -#endif -#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define REG_S sd -#define REG_L ld -#define REG_SUBU dsubu -#define REG_ADDU daddu -#endif - -/* - * How to add/sub/load/store/shift C int variables. - */ -#if (_MIPS_SZINT == 32) -#define INT_ADD add -#define INT_ADDU addu -#define INT_ADDI addi -#define INT_ADDIU addiu -#define INT_SUB sub -#define INT_SUBU subu -#define INT_L lw -#define INT_S sw -#define INT_SLL sll -#define INT_SLLV sllv -#define INT_SRL srl -#define INT_SRLV srlv -#define INT_SRA sra -#define INT_SRAV srav -#endif - -#if (_MIPS_SZINT == 64) -#define INT_ADD dadd -#define INT_ADDU daddu -#define INT_ADDI daddi -#define INT_ADDIU daddiu -#define INT_SUB dsub -#define INT_SUBU dsubu -#define INT_L ld -#define INT_S sd -#define INT_SLL dsll -#define INT_SLLV dsllv -#define INT_SRL dsrl -#define INT_SRLV dsrlv -#define INT_SRA dsra -#define INT_SRAV dsrav -#endif - -/* - * How to add/sub/load/store/shift C long variables. - */ -#if (_MIPS_SZLONG == 32) -#define LONG_ADD add -#define LONG_ADDU addu -#define LONG_ADDI addi -#define LONG_ADDIU addiu -#define LONG_SUB sub -#define LONG_SUBU subu -#define LONG_L lw -#define LONG_S sw -#define LONG_SLL sll -#define LONG_SLLV sllv -#define LONG_SRL srl -#define LONG_SRLV srlv -#define LONG_SRA sra -#define LONG_SRAV srav - -#define LONG .word -#define LONGSIZE 4 -#define LONGMASK 3 -#define LONGLOG 2 -#endif - -#if (_MIPS_SZLONG == 64) -#define LONG_ADD dadd -#define LONG_ADDU daddu -#define LONG_ADDI daddi -#define LONG_ADDIU daddiu -#define LONG_SUB dsub -#define LONG_SUBU dsubu -#define LONG_L ld -#define LONG_S sd -#define LONG_SLL dsll -#define LONG_SLLV dsllv -#define LONG_SRL dsrl -#define LONG_SRLV dsrlv -#define LONG_SRA dsra -#define LONG_SRAV dsrav - -#define LONG .dword -#define LONGSIZE 8 -#define LONGMASK 7 -#define LONGLOG 3 -#endif - -/* - * How to add/sub/load/store/shift pointers. - */ -#if (_MIPS_SZPTR == 32) -#define PTR_ADD add -#define PTR_ADDU addu -#define PTR_ADDI addi -#define PTR_ADDIU addiu -#define PTR_SUB sub -#define PTR_SUBU subu -#define PTR_L lw -#define PTR_S sw -#define PTR_LA la -#define PTR_SLL sll -#define PTR_SLLV sllv -#define PTR_SRL srl -#define PTR_SRLV srlv -#define PTR_SRA sra -#define PTR_SRAV srav - -#define PTR_SCALESHIFT 2 - -#define PTR .word -#define PTRSIZE 4 -#define PTRLOG 2 -#endif - -#if (_MIPS_SZPTR == 64) -#define PTR_ADD dadd -#define PTR_ADDU daddu -#define PTR_ADDI daddi -#define PTR_ADDIU daddiu -#define PTR_SUB dsub -#define PTR_SUBU dsubu -#define PTR_L ld -#define PTR_S sd -#define PTR_LA dla -#define PTR_SLL dsll -#define PTR_SLLV dsllv -#define PTR_SRL dsrl -#define PTR_SRLV dsrlv -#define PTR_SRA dsra -#define PTR_SRAV dsrav - -#define PTR_SCALESHIFT 3 - -#define PTR .dword -#define PTRSIZE 8 -#define PTRLOG 3 -#endif - -/* - * Some cp0 registers were extended to 64bit for MIPS III. - */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) -#define MFC0 mfc0 -#define MTC0 mtc0 -#endif -#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MFC0 dmfc0 -#define MTC0 dmtc0 -#endif - -#define SSNOP sll zero,zero,1 - -#endif /* __ASM_ASM_H */ diff --git a/include/asm-mips64/atomic.h b/include/asm-mips64/atomic.h deleted file mode 100644 index c98484c674a..00000000000 --- a/include/asm-mips64/atomic.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Atomic operations that C can't guarantee us. Useful for - * resource counting etc.. - * - * But use these as seldom as possible since they are much more slower - * than regular operations. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1999, 2000 by Ralf Baechle - */ -#ifndef _ASM_ATOMIC_H -#define _ASM_ATOMIC_H - -#include - -typedef struct { volatile int counter; } atomic_t; - -#ifdef __KERNEL__ -#define ATOMIC_INIT(i) { (i) } - -/* - * atomic_read - read atomic variable - * @v: pointer of type atomic_t - * - * Atomically reads the value of @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#define atomic_read(v) ((v)->counter) - -/* - * atomic_set - set atomic variable - * @v: pointer of type atomic_t - * @i: required value - * - * Atomically sets the value of @v to @i. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#define atomic_set(v,i) ((v)->counter = (i)) - -static __inline__ void atomic_add(int i, volatile atomic_t * v) -{ - unsigned long temp; - - __asm__ __volatile__( - "1:\tll\t%0,%1\t\t\t# atomic_add\n\t" - "addu\t%0,%2\n\t" - "sc\t%0,%1\n\t" - "beqz\t%0,1b" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); -} - -/* - * atomic_sub - subtract the atomic variable - * @i: integer value to subtract - * @v: pointer of type atomic_t - * - * Atomically subtracts @i from @v. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -static __inline__ void atomic_sub(int i, volatile atomic_t * v) -{ - unsigned long temp; - - __asm__ __volatile__( - "1:\tll\t%0,%1\t\t\t# atomic_sub\n\t" - "subu\t%0,%2\n\t" - "sc\t%0,%1\n\t" - "beqz\t%0,1b" - : "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter)); -} - -/* - * Same as above, but return the result value - */ -static __inline__ int atomic_add_return(int i, atomic_t * v) -{ - unsigned long temp, result; - - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# atomic_add_return\n" - "1:\tll\t%1,%2\n\t" - "addu\t%0,%1,%3\n\t" - "sc\t%0,%2\n\t" - "beqz\t%0,1b\n\t" - "addu\t%0,%1,%3\n\t" - "sync\n\t" - ".set\treorder" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - - return result; -} - -static __inline__ int atomic_sub_return(int i, atomic_t * v) -{ - unsigned long temp, result; - - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# atomic_sub_return\n" - "1:\tll\t%1,%2\n\t" - "subu\t%0,%1,%3\n\t" - "sc\t%0,%2\n\t" - "beqz\t%0,1b\n\t" - "subu\t%0,%1,%3\n\t" - "sync\n\t" - ".set\treorder" - : "=&r" (result), "=&r" (temp), "=m" (v->counter) - : "Ir" (i), "m" (v->counter) - : "memory"); - - return result; -} - -#define atomic_dec_return(v) atomic_sub_return(1,(v)) -#define atomic_inc_return(v) atomic_add_return(1,(v)) - -/* - * atomic_sub_and_test - subtract value from variable and test result - * @i: integer value to subtract - * @v: pointer of type atomic_t - * - * Atomically subtracts @i from @v and returns - * true if the result is zero, or false for all - * other cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) - -/* - * atomic_inc_and_test - increment and test - * @v: pointer of type atomic_t - * - * Atomically increments @v by 1 - * and returns true if the result is zero, or false for all - * other cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0) - -/* - * atomic_dec_and_test - decrement by 1 and test - * @v: pointer of type atomic_t - * - * Atomically decrements @v by 1 and - * returns true if the result is 0, or false for all other - * cases. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) - -/* - * atomic_inc - increment atomic variable - * @v: pointer of type atomic_t - * - * Atomically increments @v by 1. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#define atomic_inc(v) atomic_add(1,(v)) - -/* - * atomic_dec - decrement and test - * @v: pointer of type atomic_t - * - * Atomically decrements @v by 1. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#define atomic_dec(v) atomic_sub(1,(v)) - -/* - * atomic_add_negative - add and test if negative - * @v: pointer of type atomic_t - * @i: integer value to add - * - * Atomically adds @i to @v and returns true - * if the result is negative, or false when - * result is greater than or equal to zero. Note that the guaranteed - * useful range of an atomic_t is only 24 bits. - */ -#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) - -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() - -#endif /* defined(__KERNEL__) */ - -#endif /* _ASM_ATOMIC_H */ diff --git a/include/asm-mips64/bcache.h b/include/asm-mips64/bcache.h deleted file mode 100644 index 446102b34f4..00000000000 --- a/include/asm-mips64/bcache.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1997, 1999 by Ralf Baechle - * Copyright (c) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_BCACHE_H -#define _ASM_BCACHE_H - -#include - -/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent, - chipset implemented caches. On machines with other CPUs the CPU does the - cache thing itself. */ -struct bcache_ops { - void (*bc_enable)(void); - void (*bc_disable)(void); - void (*bc_wback_inv)(unsigned long page, unsigned long size); - void (*bc_inv)(unsigned long page, unsigned long size); -}; - -extern void indy_sc_init(void); -extern void sni_pcimt_sc_init(void); - -#ifdef CONFIG_BOARD_SCACHE - -extern struct bcache_ops *bcops; - -static inline void bc_enable(void) -{ - bcops->bc_enable(); -} - -static inline void bc_disable(void) -{ - bcops->bc_disable(); -} - -static inline void bc_wback_inv(unsigned long page, unsigned long size) -{ - bcops->bc_wback_inv(page, size); -} - -static inline void bc_inv(unsigned long page, unsigned long size) -{ - bcops->bc_inv(page, size); -} - -#else /* !defined(CONFIG_BOARD_SCACHE) */ - -/* Not R4000 / R4400 / R4600 / R5000. */ - -#define bc_enable() do { } while (0) -#define bc_disable() do { } while (0) -#define bc_wback_inv(page, size) do { } while (0) -#define bc_inv(page, size) do { } while (0) - -#endif /* !defined(CONFIG_BOARD_SCACHE) */ - -#endif /* _ASM_BCACHE_H */ diff --git a/include/asm-mips64/bitops.h b/include/asm-mips64/bitops.h deleted file mode 100644 index 828d32038b4..00000000000 --- a/include/asm-mips64/bitops.h +++ /dev/null @@ -1,647 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1994, 95, 96, 97, 98, 99, 2000 Ralf Baechle - * Copyright (c) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_BITOPS_H -#define _ASM_BITOPS_H - -#include -#include -#include -#include /* sigh ... */ - -#if (_MIPS_SZLONG == 32) -#define SZLONG_LOG 5 -#define SZLONG_MASK 31UL -#elif (_MIPS_SZLONG == 64) -#define SZLONG_LOG 6 -#define SZLONG_MASK 63UL -#endif - -#ifndef __KERNEL__ -#error "Don't do this, sucker ..." -#endif - -#include -#include - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() - -/* - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void set_bit(unsigned long nr, volatile unsigned long *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 6); - unsigned long temp; - - __asm__ __volatile__( - "1:\tlld\t%0, %1\t\t# set_bit\n\t" - "or\t%0, %2\n\t" - "scd\t%0, %1\n\t" - "beqz\t%0, 1b" - : "=&r" (temp), "=m" (*m) - : "ir" (1UL << (nr & 0x3f)), "m" (*m) - : "memory"); -} - -/* - * __set_bit - Set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike set_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static inline void __set_bit(int nr, volatile unsigned long * addr) -{ - unsigned long * m = ((unsigned long *) addr) + (nr >> 6); - - *m |= 1UL << (nr & 0x3f); -} - -/* - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() - * in order to ensure changes are visible on other processors. - */ -static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 6); - unsigned long temp; - - __asm__ __volatile__( - "1:\tlld\t%0, %1\t\t# clear_bit\n\t" - "and\t%0, %2\n\t" - "scd\t%0, %1\n\t" - "beqz\t%0, 1b\n\t" - : "=&r" (temp), "=m" (*m) - : "ir" (~(1UL << (nr & 0x3f))), "m" (*m)); -} - -/* - * __clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * Unlike clear_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static inline void __clear_bit(int nr, volatile unsigned long * addr) -{ - unsigned long * m = ((unsigned long *) addr) + (nr >> 6); - - *m &= ~(1UL << (nr & 0x3f)); -} - -/* - * change_bit - Toggle a bit in memory - * @nr: Bit to change - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void change_bit(unsigned long nr, volatile unsigned long *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 6); - unsigned long temp; - - __asm__ __volatile__( - "1:\tlld\t%0, %1\t\t# change_bit\n\t" - "xor\t%0, %2\n\t" - "scd\t%0, %1\n\t" - "beqz\t%0, 1b" - :"=&r" (temp), "=m" (*m) - :"ir" (1UL << (nr & 0x3f)), "m" (*m)); -} - -/* - * __change_bit - Toggle a bit in memory - * @nr: the bit to change - * @addr: the address to start counting from - * - * Unlike change_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static inline void __change_bit(int nr, volatile unsigned long * addr) -{ - unsigned long * m = ((unsigned long *) addr) + (nr >> 6); - - *m ^= 1UL << (nr & 0x3f); -} - -/* - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline unsigned long test_and_set_bit(unsigned long nr, - volatile unsigned long *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 6); - unsigned long temp, res; - - __asm__ __volatile__( - ".set\tnoreorder\t\t# test_and_set_bit\n" - "1:\tlld\t%0, %1\n\t" - "or\t%2, %0, %3\n\t" - "scd\t%2, %1\n\t" - "beqz\t%2, 1b\n\t" - " and\t%2, %0, %3\n\t" -#ifdef CONFIG_SMP - "sync\n\t" -#endif - ".set\treorder" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << (nr & 0x3f)), "m" (*m) - : "memory"); - - return res != 0; -} - -/* - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask, retval; - long *a = (unsigned long *) addr; - - a += (nr >> 6); - mask = 1UL << (nr & 0x3f); - retval = ((mask & *a) != 0); - *a |= mask; - - return retval; -} - -/* - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline unsigned long test_and_clear_bit(unsigned long nr, - volatile unsigned long *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 6); - unsigned long temp, res; - - __asm__ __volatile__( - ".set\tnoreorder\t\t# test_and_clear_bit\n" - "1:\tlld\t%0, %1\n\t" - "or\t%2, %0, %3\n\t" - "xor\t%2, %3\n\t" - "scd\t%2, %1\n\t" - "beqz\t%2, 1b\n\t" - " and\t%2, %0, %3\n\t" -#ifdef CONFIG_SMP - "sync\n\t" -#endif - ".set\treorder" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << (nr & 0x3f)), "m" (*m) - : "memory"); - - return res != 0; -} - -/* - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile unsigned long * addr) -{ - unsigned long mask, retval; - unsigned long *a = (unsigned long *) addr; - - a += (nr >> 6); - mask = 1UL << (nr & 0x3f); - retval = ((mask & *a) != 0); - *a &= ~mask; - - return retval; -} - -/* - * test_and_change_bit - Change a bit and return its new value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline unsigned long test_and_change_bit(unsigned long nr, - volatile unsigned long *addr) -{ - unsigned long *m = ((unsigned long *) addr) + (nr >> 6); - unsigned long temp, res; - - __asm__ __volatile__( - ".set\tnoreorder\t\t# test_and_change_bit\n" - "1:\tlld\t%0, %1\n\t" - "xor\t%2, %0, %3\n\t" - "scd\t%2, %1\n\t" - "beqz\t%2, 1b\n\t" - " and\t%2, %0, %3\n\t" -#ifdef CONFIG_SMP - "sync\n\t" -#endif - ".set\treorder" - : "=&r" (temp), "=m" (*m), "=&r" (res) - : "r" (1UL << (nr & 0x3f)), "m" (*m) - : "memory"); - - return res != 0; -} - -/* - * __test_and_change_bit - Change a bit and return its old value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_change_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask, retval; - unsigned long *a = (unsigned long *) addr; - - a += (nr >> 6); - mask = 1UL << (nr & 0x3f); - retval = ((mask & *a) != 0); - *a ^= mask; - - return retval; -} -/* - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile unsigned long * addr) -{ - return 1UL & (((const volatile unsigned long *) addr)[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK)); -} - -/* - * ffz - find first zero in word. - * @word: The word to search - * - * Undefined if no zero exists, so code should check against ~0UL first. - */ -static __inline__ unsigned long ffz(unsigned long word) -{ - int b = 0, s; - - word = ~word; - s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s; - s = 16; if (word << 48 != 0) s = 0; b += s; word >>= s; - s = 8; if (word << 56 != 0) s = 0; b += s; word >>= s; - s = 4; if (word << 60 != 0) s = 0; b += s; word >>= s; - s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s; - s = 1; if (word << 63 != 0) s = 0; b += s; - - return b; -} - -/* - * __ffs - find first bit in word. - * @word: The word to search - * - * Undefined if no bit exists, so code should check against 0 first. - */ -static __inline__ unsigned long __ffs(unsigned long word) -{ - return ffz(~word); -} - -/* - * fls: find last bit set. - */ - -#define fls(x) generic_fls(x) - -/* - * find_next_zero_bit - find the first zero bit in a memory region - * @addr: The address to base the search on - * @offset: The bitnumber to start searching at - * @size: The maximum size to search - */ -static inline unsigned long find_next_zero_bit(unsigned long *addr, - unsigned long size, unsigned long offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> SZLONG_LOG); - unsigned long result = offset & ~SZLONG_MASK; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= SZLONG_MASK; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (_MIPS_SZLONG-offset); - if (size < _MIPS_SZLONG) - goto found_first; - if (~tmp) - goto found_middle; - size -= _MIPS_SZLONG; - result += _MIPS_SZLONG; - } - while (size & ~SZLONG_MASK) { - if (~(tmp = *(p++))) - goto found_middle; - result += _MIPS_SZLONG; - size -= _MIPS_SZLONG; - } - if (!size) - return result; - tmp = *p; - -found_first: - tmp |= ~0UL << size; - if (tmp == ~0UL) /* Are any bits zero? */ - return result + size; /* Nope. */ -found_middle: - return result + ffz(tmp); -} - -#define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) - -/* - * find_next_bit - find the next set bit in a memory region - * @addr: The address to base the search on - * @offset: The bitnumber to start searching at - * @size: The maximum size to search - */ -static inline unsigned long find_next_bit(unsigned long *addr, - unsigned long size, unsigned long offset) -{ - unsigned long *p = addr + (offset >> SZLONG_LOG); - unsigned long result = offset & ~SZLONG_MASK; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= SZLONG_MASK; - if (offset) { - tmp = *(p++); - tmp &= ~0UL << offset; - if (size < _MIPS_SZLONG) - goto found_first; - if (tmp) - goto found_middle; - size -= _MIPS_SZLONG; - result += _MIPS_SZLONG; - } - while (size & ~SZLONG_MASK) { - if ((tmp = *(p++))) - goto found_middle; - result += _MIPS_SZLONG; - size -= _MIPS_SZLONG; - } - if (!size) - return result; - tmp = *p; - -found_first: - tmp &= ~0UL >> (_MIPS_SZLONG - size); - if (tmp == 0UL) /* Are any bits set? */ - return result + size; /* Nope. */ -found_middle: - return result + __ffs(tmp); -} - -/* - * find_first_bit - find the first set bit in a memory region - * @addr: The address to start the search at - * @size: The maximum size to search - * - * Returns the bit-number of the first set bit, not the number of the byte - * containing a bit. - */ -#define find_first_bit(addr, size) \ - find_next_bit((addr), (size), 0) - -#ifdef __KERNEL__ - -/* - * Every architecture must define this function. It's the fastest - * way of searching a 168-bit bitmap where the first 128 bits are - * unlikely to be set. It's guaranteed that at least one of the 168 - * bits is cleared. - */ -static inline int sched_find_first_bit(unsigned long *b) -{ - if (unlikely(b[0])) - return __ffs(b[0]); - if (unlikely(b[1])) - return __ffs(b[1]) + 64; - return __ffs(b[2]) + 128; -} - -/* - * ffs - find first bit set - * @x: the word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -#define ffs(x) generic_ffs(x) - -/* - * hweightN - returns the hamming weight of a N-bit word - * @x: the word to weigh - * - * The Hamming Weight of a number is the total number of bits set in it. - */ - -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) - -static inline int __test_and_set_le_bit(unsigned long nr, unsigned long *addr) -{ - unsigned char *ADDR = (unsigned char *) addr; - int mask, retval; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - retval = (mask & *ADDR) != 0; - *ADDR |= mask; - - return retval; -} - -static inline int __test_and_clear_le_bit(unsigned long nr, unsigned long *addr) -{ - unsigned char *ADDR = (unsigned char *) addr; - int mask, retval; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - retval = (mask & *ADDR) != 0; - *ADDR &= ~mask; - - return retval; -} - -static inline int test_le_bit(unsigned long nr, const unsigned long * addr) -{ - const unsigned char *ADDR = (const unsigned char *) addr; - int mask; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - - return ((mask & *ADDR) != 0); -} - -static inline unsigned long ext2_ffz(unsigned int word) -{ - int b = 0, s; - - word = ~word; - s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s; - s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s; - s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s; - s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s; - s = 1; if (word << 31 != 0) s = 0; b += s; - - return b; -} - -static inline unsigned long find_next_zero_le_bit(unsigned long *addr, - unsigned long size, unsigned long offset) -{ - unsigned int *p = ((unsigned int *) addr) + (offset >> 5); - unsigned int result = offset & ~31; - unsigned int tmp; - - if (offset >= size) - return size; - - size -= result; - offset &= 31; - if (offset) { - tmp = cpu_to_le32p(p++); - tmp |= ~0U >> (32-offset); /* bug or feature ? */ - if (size < 32) - goto found_first; - if (tmp != ~0U) - goto found_middle; - size -= 32; - result += 32; - } - while (size >= 32) { - if ((tmp = cpu_to_le32p(p++)) != ~0U) - goto found_middle; - result += 32; - size -= 32; - } - if (!size) - return result; - - tmp = cpu_to_le32p(p); -found_first: - tmp |= ~0 << size; - if (tmp == ~0U) /* Are any bits zero? */ - return result + size; /* Nope. */ - -found_middle: - return result + ext2_ffz(tmp); -} - -#define find_first_zero_le_bit(addr, size) \ - find_next_zero_le_bit((addr), (size), 0) - -#define ext2_set_bit(nr,addr) \ - __test_and_set_le_bit((nr),(unsigned long*)addr) -#define ext2_clear_bit(nr, addr) \ - __test_and_clear_le_bit((nr),(unsigned long*)addr) - #define ext2_set_bit_atomic(lock, nr, addr) \ -({ \ - int ret; \ - spin_lock(lock); \ - ret = ext2_set_bit((nr), (addr)); \ - spin_unlock(lock); \ - ret; \ -}) - -#define ext2_clear_bit_atomic(lock, nr, addr) \ -({ \ - int ret; \ - spin_lock(lock); \ - ret = ext2_clear_bit((nr), (addr)); \ - spin_unlock(lock); \ - ret; \ -}) -#define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr) -#define ext2_find_first_zero_bit(addr, size) \ - find_first_zero_le_bit((unsigned long*)addr, size) -#define ext2_find_next_zero_bit(addr, size, off) \ - find_next_zero_le_bit((unsigned long*)addr, size, off) - -/* - * Bitmap functions for the minix filesystem. - * - * FIXME: These assume that Minix uses the native byte/bitorder. - * This limits the Minix filesystem's value for data exchange very much. - */ -#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_BITOPS_H */ diff --git a/include/asm-mips64/bootinfo.h b/include/asm-mips64/bootinfo.h deleted file mode 100644 index 16ebdd7d259..00000000000 --- a/include/asm-mips64/bootinfo.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996 by Ralf Baechle, Andreas Busse, - * Stoned Elipot and Paul M. Antoine. - */ -#ifndef _ASM_BOOTINFO_H -#define _ASM_BOOTINFO_H - -#include - -/* - * Values for machgroup - */ -#define MACH_GROUP_UNKNOWN 0 /* whatever... */ -#define MACH_GROUP_JAZZ 1 /* Jazz */ -#define MACH_GROUP_DEC 2 /* Digital Equipment */ -#define MACH_GROUP_ARC 3 /* Wreckstation Tyne, rPC44, possibly other */ -#define MACH_GROUP_SNI_RM 4 /* Siemens Nixdorf RM series */ -#define MACH_GROUP_ACN 5 -#define MACH_GROUP_SGI 6 /* Silicon Graphics */ -#define MACH_GROUP_COBALT 7 /* Cobalt servers */ -#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */ -#define MACH_GROUP_BAGET 9 /* Baget */ -#define MACH_GROUP_COSINE 10 /* CoSine Orion */ -#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */ -#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ -#define MACH_GROUP_ITE 13 /* ITE Semi Eval Boards */ -#define MACH_GROUP_PHILIPS 14 -#define MACH_GROUP_GLOBESPAN 15 /* Globespan PVR Referrence Board */ -#define MACH_GROUP_SIBYTE 16 /* Sibyte Eval Boards */ -#define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */ -#define MACH_GROUP_ALCHEMY 18 /* Alchemy Semi Eval Boards */ -#define MACH_GROUP_NEC_VR41XX 19 /* NEC Vr41xx based boards/gadgets */ -#define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */ -#define MACH_GROUP_LASAT 21 - -/* - * Valid machtype values for group unknown (low order halfword of mips_machtype) - */ -#define MACH_UNKNOWN 0 /* whatever... */ - -/* - * Valid machtype values for group JAZZ - */ -#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */ -#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ -#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ - -/* - * Valid machtype for group DEC - */ -#define MACH_DSUNKNOWN 0 -#define MACH_DS23100 1 /* DECstation 2100 or 3100 */ -#define MACH_DS5100 2 /* DECsystem 5100 */ -#define MACH_DS5000_200 3 /* DECstation 5000/200 */ -#define MACH_DS5000_1XX 4 /* DECstation 5000/120, 125, 133, 150 */ -#define MACH_DS5000_XX 5 /* DECstation 5000/20, 25, 33, 50 */ -#define MACH_DS5000_2X0 6 /* DECstation 5000/240, 260 */ -#define MACH_DS5400 7 /* DECsystem 5400 */ -#define MACH_DS5500 8 /* DECsystem 5500 */ -#define MACH_DS5800 9 /* DECsystem 5800 */ -#define MACH_DS5900 10 /* DECsystem 5900 */ - -/* - * Valid machtype for group ARC - */ -#define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */ -#define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */ - -/* - * Valid machtype for group SNI_RM - */ -#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ - -/* - * Valid machtype for group ACN - */ -#define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */ - -/* - * Valid machtype for group SGI - */ -#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ -#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ -#define MACH_SGI_IP28 2 /* Indigo2 Impact */ -#define MACH_SGI_IP32 3 /* O2 */ - -/* - * Valid machtype for group COBALT - */ -#define MACH_COBALT_27 0 /* Proto "27" hardware */ - -/* - * Valid machtype for group NEC DDB - */ -#define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */ -#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */ -#define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */ -#define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */ -#define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */ - -/* - * Valid machtype for group BAGET - */ -#define MACH_BAGET201 0 /* BT23-201 */ -#define MACH_BAGET202 1 /* BT23-202 */ - -/* - * Cosine boards. - */ -#define MACH_COSINE_ORION 0 - -/* - * Valid machtype for group GALILEO - */ -#define MACH_EV96100 0 /* EV96100 */ -#define MACH_EV64120A 1 /* EV64120A */ - -/* - * Valid machtype for group MOMENCO - */ -#define MACH_MOMENCO_OCELOT 0 -#define MACH_MOMENCO_OCELOT_G 1 -#define MACH_MOMENCO_OCELOT_C 2 - -/* - * Valid machtype for group ITE - */ -#define MACH_QED_4N_S01B 0 /* ITE8172 based eval board */ - -/* - * Valid machtype for group Globespan - */ -#define MACH_IVR 0 /* IVR eval board */ - -/* - * Valid machtype for group PHILIPS - */ -#define MACH_PHILIPS_NINO 0 /* Nino */ -#define MACH_PHILIPS_VELO 1 /* Velo */ - -/* - * Valid machtype for group SIBYTE - */ -#define MACH_SWARM 0 - -/* - * Valid machtypes for group Toshiba - */ -#define MACH_PALLAS 0 -#define MACH_TOPAS 1 -#define MACH_JMR 2 -#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ -#define MACH_TOSHIBA_RBTX4927 4 -#define MACH_TOSHIBA_RBTX4937 5 -#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ - "RBTX4927", "RBTX4937" } - -/* - * Valid machtype for group LASAT - */ -#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ -#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ - -/* - * Valid machtype for group Alchemy - */ -#define MACH_PB1000 0 /* Au1000-based eval board */ -#define MACH_PB1100 1 /* Au1100-based eval board */ -#define MACH_PB1500 2 /* Au1500-based eval board */ -#define MACH_DB1000 3 /* Au1000-based eval board */ -#define MACH_DB1100 4 /* Au1100-based eval board */ -#define MACH_DB1500 5 /* Au1500-based eval board */ - -/* - * Valid machtype for group NEC_VR41XX - */ -#define MACH_NEC_OSPREY 0 /* Osprey eval board */ -#define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */ -#define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */ -#define MACH_VICTOR_MPC30X 3 /* Victor MP-C303/304 */ -#define MACH_IBM_WORKPAD 4 /* IBM WorkPad z50 */ -#define MACH_CASIO_E55 5 /* CASIO CASSIOPEIA E-10/15/55/65 */ -#define MACH_TANBAC_TB0226 6 /* TANBAC TB0226 (Mbase) */ -#define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */ - -#define CL_SIZE (256) - -const char *get_system_type(void); - -extern unsigned long mips_machtype; -extern unsigned long mips_machgroup; - -#define BOOT_MEM_MAP_MAX 32 -#define BOOT_MEM_RAM 1 -#define BOOT_MEM_ROM_DATA 2 -#define BOOT_MEM_RESERVED 3 - -/* - * A memory map that's built upon what was determined - * or specified on the command line. - */ -struct boot_mem_map { - int nr_map; - struct { - phys_t addr; /* start of memory segment */ - phys_t size; /* size of memory segment */ - long type; /* type of memory segment */ - } map[BOOT_MEM_MAP_MAX]; -}; - -extern struct boot_mem_map boot_mem_map; - -extern void add_memory_region(phys_t start, phys_t size, long type); - -#endif /* _ASM_BOOTINFO_H */ diff --git a/include/asm-mips64/branch.h b/include/asm-mips64/branch.h deleted file mode 100644 index 37c6857c8d4..00000000000 --- a/include/asm-mips64/branch.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle - */ -#ifndef _ASM_BRANCH_H -#define _ASM_BRANCH_H - -#include - -static inline int delay_slot(struct pt_regs *regs) -{ - return regs->cp0_cause & CAUSEF_BD; -} - -static inline unsigned long exception_epc(struct pt_regs *regs) -{ - if (!delay_slot(regs)) - return regs->cp0_epc; - - return regs->cp0_epc + 4; -} - -extern int __compute_return_epc(struct pt_regs *regs); - -static inline int compute_return_epc(struct pt_regs *regs) -{ - if (!delay_slot(regs)) { - regs->cp0_epc += 4; - return 0; - } - - return __compute_return_epc(regs); -} - -#endif /* _ASM_BRANCH_H */ diff --git a/include/asm-mips64/break.h b/include/asm-mips64/break.h deleted file mode 100644 index c8d6ab34966..00000000000 --- a/include/asm-mips64/break.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 2003 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef __ASM_BREAK_H -#define __ASM_BREAK_H - -/* - * The following break codes are or were in use for specific purposes in - * other MIPS operating systems. Linux/MIPS doesn't use all of them. The - * unused ones are here as placeholders; we might encounter them in - * non-Linux/MIPS object files or make use of them in the future. - */ -#define BRK_USERBP 0 /* User bp (used by debuggers) */ -#define BRK_KERNELBP 1 /* Break in the kernel */ -#define BRK_ABORT 2 /* Sometimes used by abort(3) to SIGIOT */ -#define BRK_BD_TAKEN 3 /* For bd slot emulation - not implemented */ -#define BRK_BD_NOTTAKEN 4 /* For bd slot emulation - not implemented */ -#define BRK_SSTEPBP 5 /* User bp (used by debuggers) */ -#define BRK_OVERFLOW 6 /* Overflow check */ -#define BRK_DIVZERO 7 /* Divide by zero check */ -#define BRK_RANGE 8 /* Range error check */ -#define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */ -#define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */ -#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ -#define BRK_MULOVF 1023 /* Multiply overflow */ -#define BRK_BUG 512 /* Used by BUG() */ - -#endif /* __ASM_BREAK_H */ diff --git a/include/asm-mips64/bug.h b/include/asm-mips64/bug.h deleted file mode 100644 index d34c34f3028..00000000000 --- a/include/asm-mips64/bug.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __ASM_BUG_H -#define __ASM_BUG_H - -#include - -#define BUG() \ -do { \ - printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ - __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \ -} while (0) -#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) -#define PAGE_BUG(page) do { BUG(); } while (0) - -#define WARN_ON(condition) do { \ - if (unlikely((condition)!=0)) { \ - printk("Badness in %s at %s:%d\n", __FUNCTION__, __FILE__, __LINE__); \ - dump_stack(); \ - } \ -} while (0) - -#endif diff --git a/include/asm-mips64/bugs.h b/include/asm-mips64/bugs.h deleted file mode 100644 index 18cced19cca..00000000000 --- a/include/asm-mips64/bugs.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ -#ifndef _ASM_BUGS_H -#define _ASM_BUGS_H - -#include - -extern void check_bugs32(void); -extern void check_bugs64(void); - -static inline void check_bugs(void) -{ - check_bugs32(); -#ifdef CONFIG_MIPS64 - check_bugs64(); -#endif -} - -#endif /* _ASM_BUGS_H */ diff --git a/include/asm-mips64/byteorder.h b/include/asm-mips64/byteorder.h deleted file mode 100644 index 2a4383e64a7..00000000000 --- a/include/asm-mips64/byteorder.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1999 by Ralf Baechle - */ -#ifndef _ASM_BYTEORDER_H -#define _ASM_BYTEORDER_H - -#include - -#ifdef __GNUC__ - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -#endif - -#endif /* __GNUC__ */ - -#if defined (__MIPSEB__) -# include -#elif defined (__MIPSEL__) -# include -#else -# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" -#endif - -#endif /* _ASM_BYTEORDER_H */ diff --git a/include/asm-mips64/cache.h b/include/asm-mips64/cache.h deleted file mode 100644 index 4057cb45f74..00000000000 --- a/include/asm-mips64/cache.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -#include - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R6000) || \ - defined(CONFIG_CPU_TX39XX) -#define L1_CACHE_BYTES 16 -#define L1_CACHE_SHIFT_MAX 4 /* largest L1 which this arch supports */ -#else -#define L1_CACHE_BYTES 32 /* A guess */ -#define L1_CACHE_SHIFT_MAX 6 /* largest L1 which this arch supports */ -#endif - -#define SMP_CACHE_BYTES L1_CACHE_BYTES - -#endif /* _ASM_CACHE_H */ diff --git a/include/asm-mips64/cacheflush.h b/include/asm-mips64/cacheflush.h deleted file mode 100644 index 6090877e6f6..00000000000 --- a/include/asm-mips64/cacheflush.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_CACHEFLUSH_H -#define _ASM_CACHEFLUSH_H - -#include - -/* Keep includes the same across arches. */ -#include - -/* Cache flushing: - * - * - flush_cache_all() flushes entire cache - * - flush_cache_mm(mm) flushes the specified mm context's cache lines - * - flush_cache_page(mm, vmaddr) flushes a single page - * - flush_cache_range(vma, start, end) flushes a range of pages - * - flush_icache_range(start, end) flush a range of instructions - * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache - * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache - * - * MIPS specific flush operations: - * - * - flush_cache_sigtramp() flush signal trampoline - * - flush_icache_all() flush the entire instruction cache - * - flush_data_cache_page() flushes a page from the data cache - */ -extern void (*flush_cache_all)(void); -extern void (*__flush_cache_all)(void); -extern void (*flush_cache_mm)(struct mm_struct *mm); -extern void (*flush_cache_range)(struct vm_area_struct *vma, - unsigned long start, unsigned long end); -extern void (*flush_cache_page)(struct vm_area_struct *vma, - unsigned long page); -extern void flush_dcache_page(struct page *page); -extern void (*flush_icache_page)(struct vm_area_struct *vma, - struct page *page); -extern void (*flush_icache_range)(unsigned long start, unsigned long end); -#define flush_icache_user_range(vma, page, addr, len) \ - flush_icache_page(vma, page) - - -extern void (*flush_cache_sigtramp)(unsigned long addr); -extern void (*flush_icache_all)(void); -extern void (*flush_data_cache_page)(unsigned long addr); - -/* - * This flag is used to indicate that the page pointed to by a pte - * is dirty and requires cleaning before returning it to the user. - */ -#define PG_dcache_dirty PG_arch_1 - -#define Page_dcache_dirty(page) \ - test_bit(PG_dcache_dirty, &(page)->flags) -#define SetPageDcacheDirty(page) \ - set_bit(PG_dcache_dirty, &(page)->flags) -#define ClearPageDcacheDirty(page) \ - clear_bit(PG_dcache_dirty, &(page)->flags) - -#endif /* _ASM_CACHEFLUSH_H */ diff --git a/include/asm-mips64/cacheops.h b/include/asm-mips64/cacheops.h deleted file mode 100644 index c4a1ec31ff6..00000000000 --- a/include/asm-mips64/cacheops.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Cache operations for the cache instruction. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle - * (C) Copyright 1999 Silicon Graphics, Inc. - */ -#ifndef __ASM_CACHEOPS_H -#define __ASM_CACHEOPS_H - -/* - * Cache Operations available on all MIPS processors with R4000-style caches - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 - -/* - * R4000-specific cacheops - */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - -/* - * R4000SC and R4400SC-specific cacheops - */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -/* - * R5000-specific cacheops - */ -#define R5K_Page_Invalidate_S 0x17 - -/* - * RM7000-specific cacheops - */ -#define Page_Invalidate_T 0x16 - -/* - * R1000-specific cacheops - * - * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. - * Most of the _S cacheops are identical to the R4000SC _SD cacheops. - */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f - -#endif /* __ASM_CACHEOPS_H */ diff --git a/include/asm-mips64/checksum.h b/include/asm-mips64/checksum.h deleted file mode 100644 index 0e061e1df26..00000000000 --- a/include/asm-mips64/checksum.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1997, 1998, 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2001 Thiemo Seufer. - * Copyright (C) 2002 Maciej W. Rozycki - */ -#ifndef _ASM_CHECKSUM_H -#define _ASM_CHECKSUM_H - -#include -#include - -/* - * computes the checksum of a memory block at buff, length len, - * and adds in "sum" (32-bit) - * - * returns a 32-bit number suitable for feeding into itself - * or csum_tcpudp_magic - * - * this function must be called with even lengths, except - * for the last fragment, which may be odd - * - * it's best to have buff aligned on a 32-bit boundary - */ -unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum); - -/* - * this is a new version of the above that records errors it finds in *errp, - * but continues and zeros the rest of the buffer. - */ -unsigned int csum_partial_copy_from_user(const char *src, char *dst, int len, - unsigned int sum, int *errp); - -/* - * Copy and checksum to user - */ -#define HAVE_CSUM_COPY_USER -static inline unsigned int csum_and_copy_to_user (const char *src, char *dst, - int len, int sum, - int *err_ptr) -{ - sum = csum_partial(src, len, sum); - - if (copy_to_user(dst, src, len)) { - *err_ptr = -EFAULT; - return -1; - } - - return sum; -} - -/* - * the same as csum_partial, but copies from user space (but on MIPS - * we have just one address space, so this is identical to the above) - */ -unsigned int csum_partial_copy_nocheck(const char *src, char *dst, int len, - unsigned int sum); - -/* - * Fold a partial checksum without adding pseudo headers - */ -static inline unsigned short int csum_fold(unsigned int sum) -{ - __asm__( - ".set\tnoat\t\t\t# csum_fold\n\t" - "sll\t$1,%0,16\n\t" - "addu\t%0,$1\n\t" - "sltu\t$1,%0,$1\n\t" - "srl\t%0,%0,16\n\t" - "addu\t%0,$1\n\t" - "xori\t%0,0xffff\n\t" - ".set\tat" - : "=r" (sum) - : "0" (sum)); - - return sum; -} - -/* - * This is a version of ip_compute_csum() optimized for IP headers, - * which always checksum on 4 octet boundaries. - * - * By Jorge Cwik , adapted for linux by - * Arnt Gulbrandsen. - */ -static inline unsigned short ip_fast_csum(unsigned char *iph, - unsigned int ihl) -{ - unsigned int sum; - unsigned long dummy; - - /* - * This is for 32-bit processors ... but works just fine for 64-bit - * processors for now ... XXX - */ - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# ip_fast_csum\n\t" - ".set\tnoat\n\t" - "lw\t%0, (%1)\n\t" - "subu\t%2, 4\n\t" - "dsll\t%2, 2\n\t" - "lw\t%3, 4(%1)\n\t" - "daddu\t%2, %1\n\t" - "addu\t%0, %3\n\t" - "sltu\t$1, %0, %3\n\t" - "lw\t%3, 8(%1)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %3\n\t" - "sltu\t$1, %0, %3\n\t" - "lw\t%3, 12(%1)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %3\n\t" - "sltu\t$1, %0, %3\n\t" - "addu\t%0, $1\n" - - "1:\tlw\t%3, 16(%1)\n\t" - "daddiu\t%1, 4\n" - "addu\t%0, %3\n\t" - "sltu\t$1, %0, %3\n\t" - "bne\t%2, %1, 1b\n\t" - " addu\t%0, $1\n" - - "2:\t.set\tat\n\t" - ".set\treorder" - : "=&r" (sum), "=&r" (iph), "=&r" (ihl), "=&r" (dummy) - : "1" (iph), "2" (ihl)); - - return csum_fold(sum); -} - -/* - * computes the checksum of the TCP/UDP pseudo-header - * returns a 16-bit checksum, already complemented - * - * Cast unsigned short expressions to unsigned long explicitly - * to avoid surprises resulting from implicit promotions to - * signed int. --macro - */ -static inline unsigned long csum_tcpudp_nofold(unsigned long saddr, - unsigned long daddr, - unsigned short len, - unsigned short proto, - unsigned int sum) -{ - __asm__( - ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t" - "daddu\t%0, %2\n\t" - "daddu\t%0, %3\n\t" - "daddu\t%0, %4\n\t" - "dsll32\t$1, %0, 0\n\t" - "daddu\t%0, $1\n\t" - "dsrl32\t%0, %0, 0\n\t" - ".set\tat" - : "=&r" (sum) - : "0" (daddr), "r"(saddr), -#ifdef __MIPSEL__ - "r" (((unsigned long)ntohs(len)<<16)+proto*256), -#else - "r" (((unsigned long)(proto)<<16)+len), -#endif - "r" (sum)); - - return sum; -} - -/* - * computes the checksum of the TCP/UDP pseudo-header - * returns a 16-bit checksum, already complemented - */ -static inline unsigned short int csum_tcpudp_magic(unsigned long saddr, - unsigned long daddr, - unsigned short len, - unsigned short proto, - unsigned int sum) -{ - return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); -} - -/* - * this routine is used for miscellaneous IP-like checksums, mainly - * in icmp.c - */ -static inline unsigned short ip_compute_csum(unsigned char * buff, int len) -{ - return csum_fold(csum_partial(buff, len, 0)); -} - -#define _HAVE_ARCH_IPV6_CSUM -static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr, - struct in6_addr *daddr, - __u32 len, - unsigned short proto, - unsigned int sum) -{ - __asm__( - ".set\tpush\t\t\t# csum_ipv6_magic\n\t" - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "addu\t%0, %5\t\t\t# proto (long in network byte order)\n\t" - "sltu\t$1, %0, %5\n\t" - "addu\t%0, $1\n\t" - - "addu\t%0, %6\t\t\t# csum\n\t" - "sltu\t$1, %0, %6\n\t" - "lw\t%1, 0(%2)\t\t\t# four words source address\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 4(%2)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 8(%2)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 12(%2)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 0(%3)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 4(%3)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 8(%3)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "lw\t%1, 12(%3)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %1\n\t" - "sltu\t$1, %0, %1\n\t" - - "addu\t%0, $1\t\t\t# Add final carry\n\t" - ".set\tpop" - : "=&r" (sum), "=&r" (proto) - : "r" (saddr), "r" (daddr), - "0" (htonl(len)), "1" (htonl(proto)), "r" (sum)); - - return csum_fold(sum); -} - -#endif /* _ASM_CHECKSUM_H */ diff --git a/include/asm-mips64/cpu.h b/include/asm-mips64/cpu.h deleted file mode 100644 index 25dd6c1bfd0..00000000000 --- a/include/asm-mips64/cpu.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * cpu.h: Values of the PRId register used to match up - * various MIPS cpu types. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#ifndef _ASM_CPU_H -#define _ASM_CPU_H - -#include - -/* Assigned Company values for bits 23:16 of the PRId Register - (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from - MTI, the PRId register is defined in this (backwards compatible) - way: - - +----------------+----------------+----------------+----------------+ - | Company Options| Company ID | Processor ID | Revision | - +----------------+----------------+----------------+----------------+ - 31 24 23 16 15 8 7 - - I don't have docs for all the previous processors, but my impression is - that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 - spec. -*/ - -#define PRID_COMP_LEGACY 0x000000 -#define PRID_COMP_MIPS 0x010000 -#define PRID_COMP_BROADCOM 0x020000 -#define PRID_COMP_ALCHEMY 0x030000 -#define PRID_COMP_SIBYTE 0x040000 -#define PRID_COMP_SANDCRAFT 0x050000 - -/* - * Assigned values for the product ID register. In order to detect a - * certain CPU type exactly eventually additional registers may need to - * be examined. These are valid when 23:16 == PRID_COMP_LEGACY - */ -#define PRID_IMP_R2000 0x0100 -#define PRID_IMP_AU1_REV1 0x0100 -#define PRID_IMP_AU1_REV2 0x0200 -#define PRID_IMP_R3000 0x0200 /* Same as R2000A */ -#define PRID_IMP_R6000 0x0300 /* Same as R3000A */ -#define PRID_IMP_R4000 0x0400 -#define PRID_IMP_R6000A 0x0600 -#define PRID_IMP_R10000 0x0900 -#define PRID_IMP_R4300 0x0b00 -#define PRID_IMP_VR41XX 0x0c00 -#define PRID_IMP_R12000 0x0e00 -#define PRID_IMP_R8000 0x1000 -#define PRID_IMP_R4600 0x2000 -#define PRID_IMP_R4700 0x2100 -#define PRID_IMP_TX39 0x2200 -#define PRID_IMP_R4640 0x2200 -#define PRID_IMP_R4650 0x2200 /* Same as R4640 */ -#define PRID_IMP_R5000 0x2300 -#define PRID_IMP_TX49 0x2d00 -#define PRID_IMP_SONIC 0x2400 -#define PRID_IMP_MAGIC 0x2500 -#define PRID_IMP_RM7000 0x2700 -#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ -#define PRID_IMP_R5432 0x5400 -#define PRID_IMP_R5500 0x5500 -#define PRID_IMP_4KC 0x8000 -#define PRID_IMP_5KC 0x8100 -#define PRID_IMP_20KC 0x8200 -#define PRID_IMP_4KEC 0x8400 -#define PRID_IMP_4KSC 0x8600 - - -#define PRID_IMP_UNKNOWN 0xff00 - -/* - * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE - */ - -#define PRID_IMP_SB1 0x0100 - -/* - * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT - */ - -#define PRID_IMP_SR71000 0x0400 - -/* - * Definitions for 7:0 on legacy processors - */ - - -#define PRID_REV_TX4927 0x0022 -#define PRID_REV_TX4937 0x0030 -#define PRID_REV_R4400 0x0040 -#define PRID_REV_R3000A 0x0030 -#define PRID_REV_R3000 0x0020 -#define PRID_REV_R2000A 0x0010 -#define PRID_REV_TX3912 0x0010 -#define PRID_REV_TX3922 0x0030 -#define PRID_REV_TX3927 0x0040 -#define PRID_REV_VR4111 0x0050 -#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ -#define PRID_REV_VR4121 0x0060 -#define PRID_REV_VR4122 0x0070 -#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ -#define PRID_REV_VR4131 0x0080 - -/* - * FPU implementation/revision register (CP1 control register 0). - * - * +---------------------------------+----------------+----------------+ - * | 0 | Implementation | Revision | - * +---------------------------------+----------------+----------------+ - * 31 16 15 8 7 0 - */ - -#define FPIR_IMP_NONE 0x0000 - -#define CPU_UNKNOWN 0 -#define CPU_R2000 1 -#define CPU_R3000 2 -#define CPU_R3000A 3 -#define CPU_R3041 4 -#define CPU_R3051 5 -#define CPU_R3052 6 -#define CPU_R3081 7 -#define CPU_R3081E 8 -#define CPU_R4000PC 9 -#define CPU_R4000SC 10 -#define CPU_R4000MC 11 -#define CPU_R4200 12 -#define CPU_R4400PC 13 -#define CPU_R4400SC 14 -#define CPU_R4400MC 15 -#define CPU_R4600 16 -#define CPU_R6000 17 -#define CPU_R6000A 18 -#define CPU_R8000 19 -#define CPU_R10000 20 -#define CPU_R12000 21 -#define CPU_R4300 22 -#define CPU_R4650 23 -#define CPU_R4700 24 -#define CPU_R5000 25 -#define CPU_R5000A 26 -#define CPU_R4640 27 -#define CPU_NEVADA 28 -#define CPU_RM7000 29 -#define CPU_R5432 30 -#define CPU_4KC 31 -#define CPU_5KC 32 -#define CPU_R4310 33 -#define CPU_SB1 34 -#define CPU_TX3912 35 -#define CPU_TX3922 36 -#define CPU_TX3927 37 -#define CPU_AU1000 38 -#define CPU_4KEC 39 -#define CPU_4KSC 40 -#define CPU_VR41XX 41 -#define CPU_R5500 42 -#define CPU_TX49XX 43 -#define CPU_AU1500 44 -#define CPU_20KC 45 -#define CPU_VR4111 46 -#define CPU_VR4121 47 -#define CPU_VR4122 48 -#define CPU_VR4131 49 -#define CPU_VR4181 50 -#define CPU_VR4181A 51 -#define CPU_AU1100 52 -#define CPU_SR71000 53 -#define CPU_LAST 53 - -/* - * ISA Level encodings - * - */ -#define MIPS_CPU_ISA_I 0x00000001 -#define MIPS_CPU_ISA_II 0x00000002 -#define MIPS_CPU_ISA_III 0x00008003 -#define MIPS_CPU_ISA_IV 0x00008004 -#define MIPS_CPU_ISA_V 0x00008005 -#define MIPS_CPU_ISA_M32 0x00000020 -#define MIPS_CPU_ISA_M64 0x00008040 - -/* - * Bit 15 encodes if an ISA level supports 64-bit operations. - */ -#define MIPS_CPU_ISA_64BIT 0x00008000 - -/* - * CPU Option encodings - */ -#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ -/* Leave a spare bit for variant MMU types... */ -#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */ -#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */ -#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */ -#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */ -#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */ -#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */ -#define MIPS_CPU_MIPS16 0x00000100 /* code compression */ -#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ -#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ -#define MIPS_CPU_CACHE_CDEX 0x00000800 /* Create_Dirty_Exclusive CACHE op */ -#define MIPS_CPU_MCHECK 0x00001000 /* Machine check exception */ -#define MIPS_CPU_EJTAG 0x00002000 /* EJTAG exception */ -#define MIPS_CPU_NOFPUEX 0x00000000 /* no FPU exception; never set */ -#define MIPS_CPU_LLSC 0x00008000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_SUBSET_CACHES 0x00010000 /* P-cache subset enforced */ - -#endif /* _ASM_CPU_H */ diff --git a/include/asm-mips64/current.h b/include/asm-mips64/current.h deleted file mode 100644 index 559db66b979..00000000000 --- a/include/asm-mips64/current.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2002 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_CURRENT_H -#define _ASM_CURRENT_H - -#include - -struct task_struct; - -static inline struct task_struct * get_current(void) -{ - return current_thread_info()->task; -} - -#define current get_current() - -#endif /* _ASM_CURRENT_H */ diff --git a/include/asm-mips64/dec/ecc.h b/include/asm-mips64/dec/ecc.h deleted file mode 100644 index 8d83a3b60b3..00000000000 --- a/include/asm-mips64/dec/ecc.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * include/asm-mips/dec/ecc.h - * - * ECC handling logic definitions common to DECstation/DECsystem - * 5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and - * DECsystem 5900 (KN03), 5900/260 (KN05) systems. - * - * Copyright (C) 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_ECC_H -#define __ASM_MIPS_DEC_ECC_H - -/* - * Error Address Register bits. - * The register is r/wc -- any write clears it. - */ -#define KN0X_EAR_VALID (1<<31) /* error data valid, bus IRQ */ -#define KN0X_EAR_CPU (1<<30) /* CPU/DMA transaction */ -#define KN0X_EAR_WRITE (1<<29) /* write/read transaction */ -#define KN0X_EAR_ECCERR (1<<28) /* ECC/timeout or overrun */ -#define KN0X_EAR_RES_27 (1<<27) /* unused */ -#define KN0X_EAR_ADDRESS (0x7ffffff<<0) /* address involved */ - -/* - * Error Syndrome Register bits. - * The register is frozen when EAR.VALID is set, otherwise it records bits - * from the last memory read. The register is r/wc -- any write clears it. - */ -#define KN0X_ESR_VLDHI (1<<31) /* error data valid hi word */ -#define KN0X_ESR_CHKHI (0x7f<<24) /* check bits read from mem */ -#define KN0X_ESR_SNGHI (1<<23) /* single/double bit error */ -#define KN0X_ESR_SYNHI (0x7f<<16) /* syndrome from ECC logic */ -#define KN0X_ESR_VLDLO (1<<15) /* error data valid lo word */ -#define KN0X_ESR_CHKLO (0x7f<<8) /* check bits read from mem */ -#define KN0X_ESR_SNGLO (1<<7) /* single/double bit error */ -#define KN0X_ESR_SYNLO (0x7f<<0) /* syndrome from ECC logic */ - - -#ifndef __ASSEMBLY__ -struct pt_regs; -extern void dec_ecc_be_init(void); -extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup); -extern void dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs); -#endif - -#endif /* __ASM_MIPS_DEC_ECC_H */ diff --git a/include/asm-mips64/dec/interrupts.h b/include/asm-mips64/dec/interrupts.h deleted file mode 100644 index 273e4d65bfe..00000000000 --- a/include/asm-mips64/dec/interrupts.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Miscellaneous definitions used to initialise the interrupt vector table - * with the machine-specific interrupt routines. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997 by Paul M. Antoine. - * reworked 1998 by Harald Koerfgen. - * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki - */ - -#ifndef __ASM_DEC_INTERRUPTS_H -#define __ASM_DEC_INTERRUPTS_H - -#include - - -/* - * The list of possible system devices which provide an - * interrupt. Not all devices exist on a given system. - */ -#define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */ - -/* Ordinary interrupts */ -#define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */ -#define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */ -#define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */ -#define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */ -#define DEC_IRQ_FLOPPY 5 /* 82077 FDC */ -#define DEC_IRQ_FPU 6 /* R3k FPU */ -#define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */ -#define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */ -#define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */ -#define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */ -#define DEC_IRQ_PSU 11 /* power supply unit warning */ -#define DEC_IRQ_RTC 12 /* DS1287 RTC */ -#define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */ -#define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */ -#define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */ -#define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */ -#define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */ -#define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */ -#define DEC_IRQ_TIMER 19 /* ARC periodic timer */ -#define DEC_IRQ_VIDEO 20 /* framebuffer */ - -/* I/O ASIC DMA interrupts */ -#define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */ -#define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */ -#define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */ -#define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */ -#define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */ -#define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */ -#define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */ -#define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */ -#define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */ -#define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */ -#define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */ -#define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */ -#define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */ -#define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */ -#define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */ -#define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */ -#define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */ -#define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */ -#define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */ -#define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */ - -/* TC5 & TC6 are virtual slots for KN02's onboard devices */ -#define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */ -#define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */ - -#define DEC_NR_INTS 41 - - -/* Largest of cpu mask_nr tables. */ -#define DEC_MAX_CPU_INTS 6 -/* Largest of asic mask_nr tables. */ -#define DEC_MAX_ASIC_INTS 9 - - -/* - * CPU interrupt bits common to all systems. - */ -#define DEC_CPU_INR_FPU 7 /* R3k FPU */ -#define DEC_CPU_INR_SW1 1 /* software #1 */ -#define DEC_CPU_INR_SW0 0 /* software #0 */ - -#define DEC_CPU_IRQ_BASE 0 /* first IRQ assigned to CPU */ - -#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE) -#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP)) -#define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP) - - -#ifndef __ASSEMBLY__ - -/* - * Interrupt table structures to hide differences between systems. - */ -typedef union { int i; void *p; } int_ptr; -extern int dec_interrupt[DEC_NR_INTS]; -extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2]; -extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2]; -extern int cpu_fpu_mask; - - -/* - * Common interrupt routine prototypes for all DECStations - */ -extern void kn02_io_int(void); -extern void kn02xa_io_int(void); -extern void kn03_io_int(void); -extern void asic_dma_int(void); -extern void asic_all_int(void); -extern void kn02_all_int(void); -extern void cpu_all_int(void); - -extern void dec_intr_unimplemented(void); -extern void asic_intr_unimplemented(void); - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/include/asm-mips64/dec/io.h b/include/asm-mips64/dec/io.h deleted file mode 100644 index 011ba64de44..00000000000 --- a/include/asm-mips64/dec/io.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * include/asm-mips64/dec/io.h - * - * Copyright (C) 2002 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS64_DEC_IO_H -#define __ASM_MIPS64_DEC_IO_H - -#include - -#define IO_SPACE_BASE K1BASE - -#define IO_SPACE_LIMIT 0xffffffff - -#endif /* __ASM_MIPS64_DEC_IO_H */ diff --git a/include/asm-mips64/dec/ioasic.h b/include/asm-mips64/dec/ioasic.h deleted file mode 100644 index 486a5b0a130..00000000000 --- a/include/asm-mips64/dec/ioasic.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * include/asm-mips/dec/ioasic.h - * - * DEC I/O ASIC access operations. - * - * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef __ASM_DEC_IOASIC_H -#define __ASM_DEC_IOASIC_H - -#include -#include - -extern spinlock_t ioasic_ssr_lock; - -extern volatile u32 *ioasic_base; - -static inline void ioasic_write(unsigned int reg, u32 v) -{ - ioasic_base[reg / 4] = v; -} - -static inline u32 ioasic_read(unsigned int reg) -{ - return ioasic_base[reg / 4]; -} - -extern void init_ioasic_irqs(int base); - -#endif /* __ASM_DEC_IOASIC_H */ diff --git a/include/asm-mips64/dec/ioasic_addrs.h b/include/asm-mips64/dec/ioasic_addrs.h deleted file mode 100644 index 5e18a751059..00000000000 --- a/include/asm-mips64/dec/ioasic_addrs.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Definitions for the address map in the JUNKIO Asic - * - * Created with Information from: - * - * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual" - * - * and the Mach Sources - * - * Copyright (C) 199x the Anonymous - * Copyright (C) 2002, 2003 Maciej W. Rozycki - */ - -#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H -#define __ASM_MIPS_DEC_IOASIC_ADDRS_H - -#define IOASIC_SLOT_SIZE 0x00040000 - -/* - * Address ranges decoded by the I/O ASIC for onboard devices. - */ -#define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */ -#define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ -#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ -#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ -#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */ -#define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE) /* VDAC (maxine) */ -#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */ -#define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE) /* VDAC (maxine) */ -#define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */ -#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */ -#define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE) /* bus error address (3max+) */ -#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */ -#define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE) /* ACCESS.bus (maxine) */ -#define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */ -#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */ -#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ -#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */ -#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ -#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ - - -/* - * Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)). - */ - /* all systems */ -#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */ -#define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */ -#define IO_REG_LANCE_DMA_P 0x20 /* LANCE DMA Pointer */ -#define IO_REG_SCC0A_T_DMA_P 0x30 /* SCC0A Transmit DMA Pointer */ -#define IO_REG_SCC0A_R_DMA_P 0x40 /* SCC0A Receive DMA Pointer */ - - /* except Maxine */ -#define IO_REG_SCC1A_T_DMA_P 0x50 /* SCC1A Transmit DMA Pointer */ -#define IO_REG_SCC1A_R_DMA_P 0x60 /* SCC1A Receive DMA Pointer */ - - /* Maxine */ -#define IO_REG_AB_T_DMA_P 0x50 /* ACCESS.bus Transmit DMA Pointer */ -#define IO_REG_AB_R_DMA_P 0x60 /* ACCESS.bus Receive DMA Pointer */ -#define IO_REG_FLOPPY_DMA_P 0x70 /* Floppy DMA Pointer */ -#define IO_REG_ISDN_T_DMA_P 0x80 /* ISDN Transmit DMA Pointer */ -#define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */ -#define IO_REG_ISDN_R_DMA_P 0xa0 /* ISDN Receive DMA Pointer */ -#define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */ - - /* all systems */ -#define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */ -#define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */ -#define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */ -#define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */ - - /* all systems */ -#define IO_REG_SSR 0x100 /* System Support Register */ -#define IO_REG_SIR 0x110 /* System Interrupt Register */ -#define IO_REG_SIMR 0x120 /* System Interrupt Mask Reg. */ -#define IO_REG_SAR 0x130 /* System Address Register */ - - /* Maxine */ -#define IO_REG_ISDN_T_DATA 0x140 /* ISDN Xmit Data Register */ -#define IO_REG_ISDN_R_DATA 0x150 /* ISDN Receive Data Register */ - - /* all systems */ -#define IO_REG_LANCE_SLOT 0x160 /* LANCE I/O Slot Register */ -#define IO_REG_SCSI_SLOT 0x170 /* SCSI Slot Register */ -#define IO_REG_SCC0A_SLOT 0x180 /* SCC0A DMA Slot Register */ - - /* except Maxine */ -#define IO_REG_SCC1A_SLOT 0x190 /* SCC1A DMA Slot Register */ - - /* Maxine */ -#define IO_REG_AB_SLOT 0x190 /* ACCESS.bus DMA Slot Register */ -#define IO_REG_FLOPPY_SLOT 0x1a0 /* Floppy Slot Register */ - - /* all systems */ -#define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */ -#define IO_REG_SCSI_SDR0 0x1c0 /* SCSI DMA Partial Word 0 */ -#define IO_REG_SCSI_SDR1 0x1d0 /* SCSI DMA Partial Word 1 */ -#define IO_REG_FCTR 0x1e0 /* Free-Running Counter */ -#define IO_REG_RES_31 0x1f0 /* unused */ - - -/* - * The upper 16 bits of the System Support Register are a part of the - * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC - * machines. The exception is the Maxine, which makes use of the - * FLOPPY and ISDN bits (otherwise unused) and has a different SCC - * wiring. - */ - /* all systems */ -#define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */ -#define IO_SSR_SCC0A_RX_DMA_EN (1<<30) /* SCC0A receive DMA enable */ -#define IO_SSR_RES_27 (1<<27) /* unused */ -#define IO_SSR_RES_26 (1<<26) /* unused */ -#define IO_SSR_RES_25 (1<<25) /* unused */ -#define IO_SSR_RES_24 (1<<24) /* unused */ -#define IO_SSR_RES_23 (1<<23) /* unused */ -#define IO_SSR_SCSI_DMA_DIR (1<<18) /* SCSI DMA direction */ -#define IO_SSR_SCSI_DMA_EN (1<<17) /* SCSI DMA enable */ -#define IO_SSR_LANCE_DMA_EN (1<<16) /* LANCE DMA enable */ - - /* except Maxine */ -#define IO_SSR_SCC1A_TX_DMA_EN (1<<29) /* SCC1A transmit DMA enable */ -#define IO_SSR_SCC1A_RX_DMA_EN (1<<28) /* SCC1A receive DMA enable */ -#define IO_SSR_RES_22 (1<<22) /* unused */ -#define IO_SSR_RES_21 (1<<21) /* unused */ -#define IO_SSR_RES_20 (1<<20) /* unused */ -#define IO_SSR_RES_19 (1<<19) /* unused */ - - /* Maxine */ -#define IO_SSR_AB_TX_DMA_EN (1<<29) /* ACCESS.bus xmit DMA enable */ -#define IO_SSR_AB_RX_DMA_EN (1<<28) /* ACCESS.bus recv DMA enable */ -#define IO_SSR_FLOPPY_DMA_DIR (1<<22) /* Floppy DMA direction */ -#define IO_SSR_FLOPPY_DMA_EN (1<<21) /* Floppy DMA enable */ -#define IO_SSR_ISDN_TX_DMA_EN (1<<20) /* ISDN transmit DMA enable */ -#define IO_SSR_ISDN_RX_DMA_EN (1<<19) /* ISDN receive DMA enable */ - -/* - * The lower 16 bits are system-specific. Bits 15,11:8 are common and - * defined here. The rest is defined in system-specific headers. - */ -#define KN0X_IO_SSR_DIAGDN (1<<15) /* diagnostic jumper */ -#define KN0X_IO_SSR_SCC_RST (1<<11) /* ~SCC0,1 (Z85C30) reset */ -#define KN0X_IO_SSR_RTC_RST (1<<10) /* ~RTC (DS1287) reset */ -#define KN0X_IO_SSR_ASC_RST (1<<9) /* ~ASC (NCR53C94) reset */ -#define KN0X_IO_SSR_LANCE_RST (1<<8) /* ~LANCE (Am7990) reset */ - -#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */ diff --git a/include/asm-mips64/dec/ioasic_ints.h b/include/asm-mips64/dec/ioasic_ints.h deleted file mode 100644 index 9aaa9869615..00000000000 --- a/include/asm-mips64/dec/ioasic_ints.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Definitions for the interrupt related bits in the I/O ASIC - * interrupt status register (and the interrupt mask register, of course) - * - * Created with Information from: - * - * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual" - * - * and the Mach Sources - * - * Copyright (C) 199x the Anonymous - * Copyright (C) 2002 Maciej W. Rozycki - */ - -#ifndef __ASM_DEC_IOASIC_INTS_H -#define __ASM_DEC_IOASIC_INTS_H - -/* - * The upper 16 bits are a part of the I/O ASIC's internal DMA engine - * and thus are common to all I/O ASIC machines. The exception is - * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise - * unused) and has a different SCC wiring. - */ - /* all systems */ -#define IO_INR_SCC0A_TXDMA 31 /* SCC0A transmit page end */ -#define IO_INR_SCC0A_TXERR 30 /* SCC0A transmit memory read error */ -#define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */ -#define IO_INR_SCC0A_RXERR 28 /* SCC0A receive overrun */ -#define IO_INR_ASC_DMA 19 /* ASC buffer pointer loaded */ -#define IO_INR_ASC_ERR 18 /* ASC page overrun */ -#define IO_INR_ASC_MERR 17 /* ASC memory read error */ -#define IO_INR_LANCE_MERR 16 /* LANCE memory read error */ - - /* except Maxine */ -#define IO_INR_SCC1A_TXDMA 27 /* SCC1A transmit page end */ -#define IO_INR_SCC1A_TXERR 26 /* SCC1A transmit memory read error */ -#define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */ -#define IO_INR_SCC1A_RXERR 24 /* SCC1A receive overrun */ -#define IO_INR_RES_23 23 /* unused */ -#define IO_INR_RES_22 22 /* unused */ -#define IO_INR_RES_21 21 /* unused */ -#define IO_INR_RES_20 20 /* unused */ - - /* Maxine */ -#define IO_INR_AB_TXDMA 27 /* ACCESS.bus transmit page end */ -#define IO_INR_AB_TXERR 26 /* ACCESS.bus xmit memory read error */ -#define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */ -#define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */ -#define IO_INR_FLOPPY_ERR 23 /* FDC error */ -#define IO_INR_ISDN_TXDMA 22 /* ISDN xmit buffer pointer loaded */ -#define IO_INR_ISDN_RXDMA 21 /* ISDN recv buffer pointer loaded */ -#define IO_INR_ISDN_ERR 20 /* ISDN memory read/overrun error */ - -#define IO_INR_DMA 16 /* first DMA IRQ */ - -/* - * The lower 16 bits are system-specific and thus defined in - * system-specific headers. - */ - - -#define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */ -#define IO_IRQ_LINES 32 /* number of I/O ASIC interrupts */ - -#define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE) -#define IO_IRQ_MASK(n) (1 << (n)) -#define IO_IRQ_ALL 0x0000ffff -#define IO_IRQ_DMA 0xffff0000 - -#endif /* __ASM_DEC_IOASIC_INTS_H */ diff --git a/include/asm-mips64/dec/kn01.h b/include/asm-mips64/dec/kn01.h deleted file mode 100644 index 946943502f8..00000000000 --- a/include/asm-mips64/dec/kn01.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Hardware info about DECstation DS2100/3100 systems (otherwise known as - * pmin/pmax or KN01). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2002, 2003 Maciej W. Rozycki - */ -#ifndef __ASM_MIPS_DEC_KN01_H -#define __ASM_MIPS_DEC_KN01_H - -#include - -#define KN01_SLOT_BASE KSEG1ADDR(0x10000000) -#define KN01_SLOT_SIZE 0x01000000 - -/* - * Address ranges for devices. - */ -#define KN01_PMASK (0*KN01_SLOT_SIZE) /* color plane mask */ -#define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */ -#define KN01_VDAC (2*KN01_SLOT_SIZE) /* color map */ -#define KN01_RES_3 (3*KN01_SLOT_SIZE) /* unused */ -#define KN01_RES_4 (4*KN01_SLOT_SIZE) /* unused */ -#define KN01_RES_5 (5*KN01_SLOT_SIZE) /* unused */ -#define KN01_RES_6 (6*KN01_SLOT_SIZE) /* unused */ -#define KN01_ERRADDR (7*KN01_SLOT_SIZE) /* write error address */ -#define KN01_LANCE (8*KN01_SLOT_SIZE) /* LANCE (Am7990) Ethernet */ -#define KN01_LANCE_MEM (9*KN01_SLOT_SIZE) /* LANCE buffer memory */ -#define KN01_SII (10*KN01_SLOT_SIZE) /* SII (DC7061) SCSI */ -#define KN01_SII_MEM (11*KN01_SLOT_SIZE) /* SII buffer memory */ -#define KN01_DZ11 (12*KN01_SLOT_SIZE) /* DZ11 (DC7085) serial */ -#define KN01_RTC (13*KN01_SLOT_SIZE) /* DS1287 RTC (bytes #0) */ -#define KN01_ESAR (13*KN01_SLOT_SIZE) /* MAC address (bytes #1) */ -#define KN01_CSR (14*KN01_SLOT_SIZE) /* system ctrl & status reg */ -#define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */ - - -/* - * Some port addresses... - */ -#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */ -#define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */ -#define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */ - - -/* - * Frame buffer memory address. - */ -#define KN01_VFB_MEM KSEG1ADDR(0x0fc00000) - -/* - * CPU interrupt bits. - */ -#define KN01_CPU_INR_BUS 6 /* memory, I/O bus read/write errors */ -#define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */ -#define KN01_CPU_INR_RTC 5 /* DS1287 RTC */ -#define KN01_CPU_INR_DZ11 4 /* DZ11 (DC7085) serial */ -#define KN01_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */ -#define KN01_CPU_INR_SII 2 /* SII (DC7061) SCSI */ - - -/* - * System Control & Status Register bits. - */ -#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */ -#define KN01_CSR_STATUS (1<<14) /* self-test result status output */ -#define KN01_CSR_PARDIS (1<<13) /* parity error disable */ -#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */ -#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */ -#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/ -#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */ -#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */ -#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */ -#define KN01_CSR_VRGTRG (1<<1) /* red DAC voltage over green (r/o) */ -#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */ -#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ - -#endif /* __ASM_MIPS_DEC_KN01_H */ diff --git a/include/asm-mips64/dec/kn02.h b/include/asm-mips64/dec/kn02.h deleted file mode 100644 index f797f704592..00000000000 --- a/include/asm-mips64/dec/kn02.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Hardware info about DECstation 5000/200 systems (otherwise known as - * 3max or KN02). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2002, 2003 Maciej W. Rozycki - */ -#ifndef __ASM_MIPS_DEC_KN02_H -#define __ASM_MIPS_DEC_KN02_H - -#ifndef __ASSEMBLY__ -#include -#include -#endif - -#include -#include - - -#define KN02_SLOT_BASE KSEG1ADDR(0x1fc00000) -#define KN02_SLOT_SIZE 0x00080000 - -/* - * Address ranges decoded by the "system slot" logic for onboard devices. - */ -#define KN02_SYS_ROM (0*KN02_SLOT_SIZE) /* system board ROM */ -#define KN02_RES_1 (1*KN02_SLOT_SIZE) /* unused */ -#define KN02_CHKSYN (2*KN02_SLOT_SIZE) /* ECC syndrome */ -#define KN02_ERRADDR (3*KN02_SLOT_SIZE) /* bus error address */ -#define KN02_DZ11 (4*KN02_SLOT_SIZE) /* DZ11 (DC7085) serial */ -#define KN02_RTC (5*KN02_SLOT_SIZE) /* DS1287 RTC */ -#define KN02_CSR (6*KN02_SLOT_SIZE) /* system ctrl & status reg */ -#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */ - - -/* - * Some port addresses... - */ -#define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */ -#define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */ -#define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */ - - -/* - * System Control & Status Register bits. - */ -#define KN02_CSR_RES_28 (0xf<<28) /* unused */ -#define KN02_CSR_PSU (1<<27) /* power supply unit warning */ -#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */ -#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */ -#define KN03_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */ -#define KN03_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */ -#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ -#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ -#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */ -#define KN02_CSR_LEDIAG (1<<12) /* ECC diagn. latch strobe */ -#define KN02_CSR_TXDIS (1<<11) /* DZ11 transmit disable */ -#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */ -#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */ -#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */ -#define KN03_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */ -#define KN03_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */ - - -/* - * CPU interrupt bits. - */ -#define KN02_CPU_INR_RES_6 6 /* unused */ -#define KN02_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */ -#define KN02_CPU_INR_RES_4 4 /* unused */ -#define KN02_CPU_INR_RTC 3 /* DS1287 RTC */ -#define KN02_CPU_INR_CASCADE 2 /* CSR cascade */ - -/* - * CSR interrupt bits. - */ -#define KN02_CSR_INR_DZ11 7 /* DZ11 (DC7085) serial */ -#define KN02_CSR_INR_LANCE 6 /* LANCE (Am7990) Ethernet */ -#define KN02_CSR_INR_ASC 5 /* ASC (NCR53C94) SCSI */ -#define KN02_CSR_INR_RES_4 4 /* unused */ -#define KN02_CSR_INR_RES_3 3 /* unused */ -#define KN02_CSR_INR_TC2 2 /* TURBOchannel slot #2 */ -#define KN02_CSR_INR_TC1 1 /* TURBOchannel slot #1 */ -#define KN02_CSR_INR_TC0 0 /* TURBOchannel slot #0 */ - - -#define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */ -#define KN02_IRQ_LINES 8 /* number of CSR interrupts */ - -#define KN02_IRQ_NR(n) ((n) + KN02_IRQ_BASE) -#define KN02_IRQ_MASK(n) (1 << (n)) -#define KN02_IRQ_ALL 0xff - - -#ifndef __ASSEMBLY__ -extern u32 cached_kn02_csr; -extern spinlock_t kn02_lock; -extern void init_kn02_irqs(int base); -#endif - -#endif /* __ASM_MIPS_DEC_KN02_H */ diff --git a/include/asm-mips64/dec/kn02ba.h b/include/asm-mips64/dec/kn02ba.h deleted file mode 100644 index c957a4f1b32..00000000000 --- a/include/asm-mips64/dec/kn02ba.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * include/asm-mips/dec/kn02ba.h - * - * DECstation 5000/1xx (3min or KN02-BA) definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_KN02BA_H -#define __ASM_MIPS_DEC_KN02BA_H - -#include /* For common definitions. */ - -/* - * CPU interrupt bits. - */ -#define KN02BA_CPU_INR_HALT 6 /* HALT button */ -#define KN02BA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */ -#define KN02BA_CPU_INR_TC2 4 /* TURBOchannel slot #2 */ -#define KN02BA_CPU_INR_TC1 3 /* TURBOchannel slot #1 */ -#define KN02BA_CPU_INR_TC0 2 /* TURBOchannel slot #0 */ - -/* - * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. - */ -#define KN02BA_IO_INR_RES_15 15 /* unused */ -#define KN02BA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ -#define KN02BA_IO_INR_RES_13 13 /* unused */ -#define KN02BA_IO_INR_BUS 12 /* memory, I/O bus read/write errors */ -#define KN02BA_IO_INR_RES_11 11 /* unused */ -#define KN02BA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ -#define KN02BA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ -#define KN02BA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ -#define KN02BA_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */ -#define KN02BA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ -#define KN02BA_IO_INR_RTC 5 /* DS1287 RTC */ -#define KN02BA_IO_INR_PSU 4 /* power supply unit warning */ -#define KN02BA_IO_INR_RES_3 3 /* unused */ -#define KN02BA_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */ -#define KN02BA_IO_INR_PBNC 1 /* ~HALT button debouncer */ -#define KN02BA_IO_INR_PBNO 0 /* HALT button debouncer */ - - -/* - * Memory Error Register bits. - */ -#define KN02BA_MER_RES_27 (1<<27) /* unused */ - -/* - * Memory Size Register bits. - */ -#define KN02BA_MSR_RES_17 (0x3ff<<17) /* unused */ - -/* - * I/O ASIC System Support Register bits. - */ -#define KN02BA_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */ -#define KN02BA_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */ -#define KN02BA_IO_SSR_RES_12 (1<<12) /* unused */ - -#define KN02BA_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */ - -#endif /* __ASM_MIPS_DEC_KN02BA_H */ diff --git a/include/asm-mips64/dec/kn02ca.h b/include/asm-mips64/dec/kn02ca.h deleted file mode 100644 index 92c0fe25609..00000000000 --- a/include/asm-mips64/dec/kn02ca.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * include/asm-mips/dec/kn02ca.h - * - * Personal DECstation 5000/xx (Maxine or KN02-CA) definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_KN02CA_H -#define __ASM_MIPS_DEC_KN02CA_H - -#include /* For common definitions. */ - -/* - * CPU interrupt bits. - */ -#define KN02CA_CPU_INR_HALT 6 /* HALT from ACCESS.Bus */ -#define KN02CA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */ -#define KN02CA_CPU_INR_BUS 4 /* memory, I/O bus read/write errors */ -#define KN02CA_CPU_INR_RTC 3 /* DS1287 RTC */ -#define KN02CA_CPU_INR_TIMER 2 /* ARC periodic timer */ - -/* - * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. - */ -#define KN02CA_IO_INR_FLOPPY 15 /* 82077 FDC */ -#define KN02CA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ -#define KN02CA_IO_INR_POWERON 13 /* (*) ACCESS.Bus/power-on reset */ -#define KN02CA_IO_INR_TC0 12 /* TURBOchannel slot #0 */ -#define KN02CA_IO_INR_TIMER 12 /* ARC periodic timer (?) */ -#define KN02CA_IO_INR_ISDN 11 /* Am79C30A ISDN */ -#define KN02CA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ -#define KN02CA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ -#define KN02CA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ -#define KN02CA_IO_INR_HDFLOPPY 7 /* (*) HD (1.44MB) floppy status */ -#define KN02CA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ -#define KN02CA_IO_INR_TC1 5 /* TURBOchannel slot #1 */ -#define KN02CA_IO_INR_XDFLOPPY 4 /* (*) XD (2.88MB) floppy status */ -#define KN02CA_IO_INR_VIDEO 3 /* framebuffer */ -#define KN02CA_IO_INR_XVIDEO 2 /* ~framebuffer */ -#define KN02CA_IO_INR_AB_XMIT 1 /* ACCESS.bus transmit */ -#define KN02CA_IO_INR_AB_RECV 0 /* ACCESS.bus receive */ - - -/* - * Memory Error Register bits. - */ -#define KN02CA_MER_INTR (1<<27) /* ARC IRQ status & ack */ - -/* - * Memory Size Register bits. - */ -#define KN02CA_MSR_INTREN (1<<26) /* ARC periodic IRQ enable */ -#define KN02CA_MSR_MS10EN (1<<25) /* 10/1ms IRQ period select */ -#define KN02CA_MSR_PFORCE (0xf<<21) /* byte lane error force */ -#define KN02CA_MSR_MABEN (1<<20) /* A side VFB address enable */ -#define KN02CA_MSR_LASTBANK (0x7<<17) /* onboard RAM bank # */ - -/* - * I/O ASIC System Support Register bits. - */ -#define KN03CA_IO_SSR_RES_14 (1<<14) /* unused */ -#define KN03CA_IO_SSR_RES_13 (1<<13) /* unused */ -#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */ - -#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */ -#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */ -#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */ -#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */ -#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */ -#define KN03CA_IO_SSR_RES_2 (1<<2) /* unused */ -#define KN03CA_IO_SSR_RES_1 (1<<1) /* unused */ -#define KN03CA_IO_SSR_LED (1<<0) /* power LED */ - -#endif /* __ASM_MIPS_DEC_KN02CA_H */ diff --git a/include/asm-mips64/dec/kn02xa.h b/include/asm-mips64/dec/kn02xa.h deleted file mode 100644 index 648c4dcbba1..00000000000 --- a/include/asm-mips64/dec/kn02xa.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Hardware info common to DECstation 5000/1xx systems (otherwise - * known as 3min or kn02ba) and Personal DECstations 5000/xx ones - * (otherwise known as maxine or kn02ca). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki - * - * These are addresses which have to be known early in the boot process. - * For other addresses refer to tc.h, ioasic_addrs.h and friends. - */ -#ifndef __ASM_MIPS_DEC_KN02XA_H -#define __ASM_MIPS_DEC_KN02XA_H - -#include -#include - -#define KN02XA_SLOT_BASE KSEG1ADDR(0x1c000000) - -/* - * Some port addresses... - */ -#define KN02XA_IOASIC_BASE (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */ -#define KN02XA_RTC_BASE (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */ - - -/* - * Memory control ASIC registers. - */ -#define KN02XA_MER KSEG1ADDR(0x0c400000) /* memory error register */ -#define KN02XA_MSR KSEG1ADDR(0x0c800000) /* memory size register */ - -/* - * CPU control ASIC registers. - */ -#define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000) /* write timeout config */ -#define KN02XA_EAR KSEG1ADDR(0x0e000004) /* error address register */ -#define KN02XA_BOOT0 KSEG1ADDR(0x0e000008) /* boot 0 register */ -#define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */ - -/* - * Memory Error Register bits, common definitions. - * The rest is defined in system-specific headers. - */ -#define KN02XA_MER_RES_28 (0xf<<28) /* unused */ -#define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */ -#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */ -#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */ -#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */ -#define KN02XA_MER_RES_12 (0x3<<12) /* unused */ -#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask */ -#define KN02XA_MER_RES_0 (0xff<<0) /* unused */ - -/* - * Memory Size Register bits, common definitions. - * The rest is defined in system-specific headers. - */ -#define KN02XA_MSR_RES_27 (0x1f<<27) /* unused */ -#define KN02XA_MSR_RES_14 (0x7<<14) /* unused */ -#define KN02XA_MSR_SIZE (1<<13) /* 16M/4M stride */ -#define KN02XA_MSR_RES_0 (0x1fff<<0) /* unused */ - -/* - * Error Address Register bits. - */ -#define KN02XA_EAR_RES_29 (0x7<<29) /* unused */ -#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */ -#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */ - -#endif /* __ASM_MIPS_DEC_KN02XA_H */ diff --git a/include/asm-mips64/dec/kn03.h b/include/asm-mips64/dec/kn03.h deleted file mode 100644 index 676abd17c6a..00000000000 --- a/include/asm-mips64/dec/kn03.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Hardware info about DECstation 5000/2x0 systems (otherwise known as - * 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which - * differ mechanically but are otherwise identical (both are known as - * KN03). - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions - * are by courtesy of Chris Fraser. - * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki - */ -#ifndef __ASM_MIPS_DEC_KN03_H -#define __ASM_MIPS_DEC_KN03_H - -#include -#include -#include - -#define KN03_SLOT_BASE KSEG1ADDR(0x1f800000) - -/* - * Some port addresses... - */ -#define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */ -#define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */ -#define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */ - - -/* - * CPU interrupt bits. - */ -#define KN03_CPU_INR_HALT 6 /* HALT button */ -#define KN03_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */ -#define KN03_CPU_INR_RES_4 4 /* unused */ -#define KN03_CPU_INR_RTC 3 /* DS1287 RTC */ -#define KN03_CPU_INR_CASCADE 2 /* I/O ASIC cascade */ - -/* - * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. - */ -#define KN03_IO_INR_3MAXP 15 /* (*) 3max+/bigmax ID */ -#define KN03_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ -#define KN03_IO_INR_TC2 13 /* TURBOchannel slot #2 */ -#define KN03_IO_INR_TC1 12 /* TURBOchannel slot #1 */ -#define KN03_IO_INR_TC0 11 /* TURBOchannel slot #0 */ -#define KN03_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ -#define KN03_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ -#define KN03_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ -#define KN03_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */ -#define KN03_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ -#define KN03_IO_INR_RTC 5 /* DS1287 RTC */ -#define KN03_IO_INR_PSU 4 /* power supply unit warning */ -#define KN03_IO_INR_RES_3 3 /* unused */ -#define KN03_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */ -#define KN03_IO_INR_PBNC 1 /* ~HALT button debouncer */ -#define KN03_IO_INR_PBNO 0 /* HALT button debouncer */ - - -/* - * Memory Control Register bits. - */ -#define KN03_MCR_RES_16 (0xffff<<16) /* unused */ -#define KN03_MCR_DIAGCHK (1<<15) /* diagn/norml ECC reads */ -#define KN03_MCR_DIAGGEN (1<<14) /* diagn/norml ECC writes */ -#define KN03_MCR_CORRECT (1<<13) /* ECC correct/check */ -#define KN03_MCR_RES_11 (0x3<<12) /* unused */ -#define KN03_MCR_BNK32M (1<<10) /* 32M/8M stride */ -#define KN03_MCR_RES_7 (0x7<<7) /* unused */ -#define KN03_MCR_CHECK (0x7f<<0) /* diagnostic check bits */ - -/* - * I/O ASIC System Support Register bits. - */ -#define KN03_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */ -#define KN03_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */ -#define KN03_IO_SSR_RES_12 (1<<12) /* unused */ - -#define KN03_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */ - -#endif /* __ASM_MIPS_DEC_KN03_H */ diff --git a/include/asm-mips64/dec/kn05.h b/include/asm-mips64/dec/kn05.h deleted file mode 100644 index 71a2b8eeced..00000000000 --- a/include/asm-mips64/dec/kn05.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * include/asm-mips/dec/kn05.h - * - * DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260 - * definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * WARNING! All this information is pure guesswork based on the - * ROM. It is provided here in hope it will give someone some - * food for thought. No documentation for the KN05 module has - * been located so far. - */ -#ifndef __ASM_MIPS_DEC_KN05_H -#define __ASM_MIPS_DEC_KN05_H - -#include - -/* - * The oncard MB (Memory Buffer) ASIC provides an additional address - * decoder. Certain address ranges within the "high" 16 slots are - * passed to the I/O ASIC's decoder like with the KN03. Others are - * handled locally. "Low" slots are always passed. - */ -#define KN05_MB_ROM (16*IOASIC_SLOT_SIZE) /* KN05 card ROM */ -#define KN05_IOCTL (17*IOASIC_SLOT_SIZE) /* I/O ASIC */ -#define KN05_ESAR (18*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ -#define KN05_LANCE (19*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ -#define KN05_MB_INT (20*IOASIC_SLOT_SIZE) /* MB interrupt register */ -#define KN05_MB_EA (21*IOASIC_SLOT_SIZE) /* MB error address? */ -#define KN05_MB_EC (22*IOASIC_SLOT_SIZE) /* MB error ??? */ -#define KN05_MB_CSR (23*IOASIC_SLOT_SIZE) /* MB control & status */ -#define KN05_RES_24 (24*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_25 (25*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_26 (26*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_27 (27*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_SCSI (28*IOASIC_SLOT_SIZE) /* ASC SCSI */ -#define KN05_RES_29 (29*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_30 (30*IOASIC_SLOT_SIZE) /* unused? */ -#define KN05_RES_31 (31*IOASIC_SLOT_SIZE) /* unused? */ - -/* - * Bits for the MB interrupt register. - * The register appears read-only. - */ -#define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */ -#define KN05_MB_INT_RTC (1<<1) /* RTC? */ - -/* - * Bits for the MB control & status register. - * Set to 0x00bf8001 on my system by the ROM. - */ -#define KN05_MB_CSR_PF (1<<0) /* PreFetching enable? */ -#define KN05_MB_CSR_F (1<<1) /* ??? */ -#define KN05_MB_CSR_ECC (0xff<<2) /* ??? */ -#define KN05_MB_CSR_OD (1<<10) /* ??? */ -#define KN05_MB_CSR_CP (1<<11) /* ??? */ -#define KN05_MB_CSR_UNC (1<<12) /* ??? */ -#define KN05_MB_CSR_IM (1<<13) /* ??? */ -#define KN05_MB_CSR_NC (1<<14) /* ??? */ -#define KN05_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ -#define KN05_MB_CSR_MSK (0x1f<<16) /* ??? */ -#define KN05_MB_CSR_FW (1<<21) /* ??? */ - -#endif /* __ASM_MIPS_DEC_KN05_H */ diff --git a/include/asm-mips64/dec/kn230.h b/include/asm-mips64/dec/kn230.h deleted file mode 100644 index ff1bf17de8d..00000000000 --- a/include/asm-mips64/dec/kn230.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * include/asm-mips/dec/kn230.h - * - * DECsystem 5100 (MIPSmate or KN230) definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_KN230_H -#define __ASM_MIPS_DEC_KN230_H - -/* - * CPU interrupt bits. - */ -#define KN230_CPU_INR_HALT 6 /* HALT button */ -#define KN230_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */ -#define KN230_CPU_INR_RTC 4 /* DS1287 RTC */ -#define KN230_CPU_INR_SII 3 /* SII (DC7061) SCSI */ -#define KN230_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */ -#define KN230_CPU_INR_DZ11 2 /* DZ11 (DC7085) serial */ - -#endif /* __ASM_MIPS_DEC_KN230_H */ diff --git a/include/asm-mips64/dec/machtype.h b/include/asm-mips64/dec/machtype.h deleted file mode 100644 index a6ecdebc430..00000000000 --- a/include/asm-mips64/dec/machtype.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Various machine type macros - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1998, 2000 Harald Koerfgen - */ - -#ifndef __ASM_DEC_MACHTYPE_H -#define __ASM_DEC_MACHTYPE_H - -#include - -#define TURBOCHANNEL (mips_machtype == MACH_DS5000_200 || \ - mips_machtype == MACH_DS5000_1XX || \ - mips_machtype == MACH_DS5000_XX || \ - mips_machtype == MACH_DS5000_2X0 || \ - mips_machtype == MACH_DS5900) - -#define IOASIC (mips_machtype == MACH_DS5000_1XX || \ - mips_machtype == MACH_DS5000_XX || \ - mips_machtype == MACH_DS5000_2X0 || \ - mips_machtype == MACH_DS5900) - -#endif diff --git a/include/asm-mips64/dec/prom.h b/include/asm-mips64/dec/prom.h deleted file mode 100644 index 53d7848a73b..00000000000 --- a/include/asm-mips64/dec/prom.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * include/asm-mips64/dec/prom.h - * - * DECstation PROM interface. - * - * Copyright (C) 2002 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Based on arch/mips/dec/prom/prom.h by the Anonymous. - */ -#ifndef __ASM_MIPS64_DEC_PROM_H -#define __ASM_MIPS64_DEC_PROM_H - -#include - -#include - -/* - * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's. - * Many of these will work for MIPSen as well! - */ -#define VEC_RESET (u64 *)KSEG1ADDR(0x1fc00000) - /* Prom base address */ - -#define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */ - -#define PMAX_PROM_HALT PMAX_PROM_ENTRY(2) /* valid on MIPSen */ -#define PMAX_PROM_AUTOBOOT PMAX_PROM_ENTRY(5) /* valid on MIPSen */ -#define PMAX_PROM_OPEN PMAX_PROM_ENTRY(6) -#define PMAX_PROM_READ PMAX_PROM_ENTRY(7) -#define PMAX_PROM_CLOSE PMAX_PROM_ENTRY(10) -#define PMAX_PROM_LSEEK PMAX_PROM_ENTRY(11) -#define PMAX_PROM_GETCHAR PMAX_PROM_ENTRY(12) -#define PMAX_PROM_PUTCHAR PMAX_PROM_ENTRY(13) /* 12 on MIPSen */ -#define PMAX_PROM_GETS PMAX_PROM_ENTRY(15) -#define PMAX_PROM_PRINTF PMAX_PROM_ENTRY(17) -#define PMAX_PROM_GETENV PMAX_PROM_ENTRY(33) /* valid on MIPSen */ - - -/* - * Magic number indicating REX PROM available on DECstation. Found in - * register a2 on transfer of control to program from PROM. - */ -#define REX_PROM_MAGIC 0x30464354 - -#ifdef CONFIG_MIPS64 - -#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */ - -#else /* !CONFIG_MIPS64 */ - -#define prom_is_rex(magic) ((magic) == REX_PROM_MAGIC) - -#endif /* !CONFIG_MIPS64 */ - - -/* - * 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and - * DS5000/2x0. - */ -#define REX_PROM_GETBITMAP 0x84/4 /* get mem bitmap */ -#define REX_PROM_GETCHAR 0x24/4 /* getch() */ -#define REX_PROM_GETENV 0x64/4 /* get env. variable */ -#define REX_PROM_GETSYSID 0x80/4 /* get system id */ -#define REX_PROM_GETTCINFO 0xa4/4 -#define REX_PROM_PRINTF 0x30/4 /* printf() */ -#define REX_PROM_SLOTADDR 0x6c/4 /* slotaddr */ -#define REX_PROM_BOOTINIT 0x54/4 /* open() */ -#define REX_PROM_BOOTREAD 0x58/4 /* read() */ -#define REX_PROM_CLEARCACHE 0x7c/4 - - -/* - * Used by rex_getbitmap(). - */ -typedef struct { - int pagesize; - unsigned char bitmap[0]; -} memmap; - - -/* - * Function pointers as read from a PROM's callback vector. - */ -extern int (*__rex_bootinit)(void); -extern int (*__rex_bootread)(void); -extern int (*__rex_getbitmap)(memmap *); -extern unsigned long *(*__rex_slot_address)(int); -extern void *(*__rex_gettcinfo)(void); -extern int (*__rex_getsysid)(void); -extern void (*__rex_clear_cache)(void); - -extern int (*__prom_getchar)(void); -extern char *(*__prom_getenv)(char *); -extern int (*__prom_printf)(char *, ...); - -extern int (*__pmax_open)(char*, int); -extern int (*__pmax_lseek)(int, long, int); -extern int (*__pmax_read)(int, void *, int); -extern int (*__pmax_close)(int); - - -#ifdef CONFIG_MIPS64 - -/* - * On MIPS64 we have to call PROM functions via a helper - * dispatcher to accomodate ABI incompatibilities. - */ -#define __DEC_PROM_O32 __attribute__((alias("call_o32"))) - -int _rex_bootinit(int (*)(void)) __DEC_PROM_O32; -int _rex_bootread(int (*)(void)) __DEC_PROM_O32; -int _rex_getbitmap(int (*)(memmap *), memmap *) __DEC_PROM_O32; -unsigned long *_rex_slot_address(unsigned long *(*)(int), int) __DEC_PROM_O32; -void *_rex_gettcinfo(void *(*)(void)) __DEC_PROM_O32; -int _rex_getsysid(int (*)(void)) __DEC_PROM_O32; -void _rex_clear_cache(void (*)(void)) __DEC_PROM_O32; - -int _prom_getchar(int (*)(void)) __DEC_PROM_O32; -char *_prom_getenv(char *(*)(char *), char *) __DEC_PROM_O32; -int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32; - - -#define rex_bootinit() _rex_bootinit(__rex_bootinit) -#define rex_bootread() _rex_bootread(__rex_bootread) -#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, x) -#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, x) -#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo) -#define rex_getsysid() _rex_getsysid(__rex_getsysid) -#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache) - -#define prom_getchar() _prom_getchar(__prom_getchar) -#define prom_getenv(x) _prom_getenv(__prom_getenv, x) -#define prom_printf(x...) _prom_printf(__prom_printf, x) - -#else /* !CONFIG_MIPS64 */ - -/* - * On plain MIPS we just call PROM functions directly. - */ -#define rex_bootinit __rex_bootinit -#define rex_bootread __rex_bootread -#define rex_getbitmap __rex_getbitmap -#define rex_slot_address __rex_slot_address -#define rex_gettcinfo __rex_gettcinfo -#define rex_getsysid __rex_getsysid -#define rex_clear_cache __rex_clear_cache - -#define prom_getchar __prom_getchar -#define prom_getenv __prom_getenv -#define prom_printf __prom_printf - -#define pmax_open __pmax_open -#define pmax_lseek __pmax_lseek -#define pmax_read __pmax_read -#define pmax_close __pmax_close - -#endif /* !CONFIG_MIPS64 */ - - -extern void prom_meminit(u32); -extern void prom_identify_arch(u32); -extern void prom_init_cmdline(s32, s32 *, u32); - -#endif /* __ASM_MIPS64_DEC_PROM_H */ diff --git a/include/asm-mips64/dec/rtc-dec.h b/include/asm-mips64/dec/rtc-dec.h deleted file mode 100644 index 056da821ffe..00000000000 --- a/include/asm-mips64/dec/rtc-dec.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * include/asm-mips/dec/rtc-dec.h - * - * RTC definitions for DECstation style attached Dallas DS1287 chip. - * - * Copyright (C) 2002 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_RTC_DEC_H -#define __ASM_MIPS_DEC_RTC_DEC_H - -#include - -#include - -extern volatile u8 *dec_rtc_base; -extern unsigned long dec_kn_slot_size; - -extern struct rtc_ops dec_rtc_ops; - -#define RTC_PORT(x) CPHYSADDR(dec_rtc_base) -#define RTC_IO_EXTENT dec_kn_slot_size -#define RTC_IOMAPPED 0 -#define RTC_IRQ 0 - -#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */ - -#endif /* __ASM_MIPS_DEC_RTC_DEC_H */ diff --git a/include/asm-mips64/dec/tc.h b/include/asm-mips64/dec/tc.h deleted file mode 100644 index d7bba43f863..00000000000 --- a/include/asm-mips64/dec/tc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Interface to the TURBOchannel related routines - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1998 Harald Koerfgen - */ -#ifndef ASM_TC_H -#define ASM_TC_H - -extern unsigned long system_base; - -/* - * Search for a TURBOchannel Option Module - * with a certain name. Returns slot number - * of the first card not in use or -ENODEV - * if none found. - */ -extern int search_tc_card(const char *); -/* - * Marks the card in slot as used - */ -extern void claim_tc_card(int); -/* - * Marks the card in slot as free - */ -extern void release_tc_card(int); -/* - * Return base address of card in slot - */ -extern unsigned long get_tc_base_addr(int); -/* - * Return interrupt number of slot - */ -extern unsigned long get_tc_irq_nr(int); -/* - * Return TURBOchannel clock frequency in hz - */ -extern unsigned long get_tc_speed(void); - -#endif diff --git a/include/asm-mips64/dec/tcinfo.h b/include/asm-mips64/dec/tcinfo.h deleted file mode 100644 index cc23509ee77..00000000000 --- a/include/asm-mips64/dec/tcinfo.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Various TURBOchannel related stuff - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Information obtained through the get_tcinfo prom call - * created from: - * - * TURBOchannel Firmware Specification - * - * EK-TCAAD-FS-004 - * from Digital Equipment Corporation - * - * Copyright (c) 1998 Harald Koerfgen - */ - -typedef struct { - int revision; - int clk_period; - int slot_size; - int io_timeout; - int dma_range; - int max_dma_burst; - int parity; - int reserved[4]; -} tcinfo; - -#define MAX_SLOT 7 - -typedef struct { - unsigned long base_addr; - unsigned char name[9]; - unsigned char vendor[9]; - unsigned char firmware[9]; - int interrupt; - int flags; -} slot_info; - -/* - * Values for flags - */ -#define FREE 1<<0 -#define IN_USE 1<<1 - - diff --git a/include/asm-mips64/dec/tcmodule.h b/include/asm-mips64/dec/tcmodule.h deleted file mode 100644 index 6268e8915d8..00000000000 --- a/include/asm-mips64/dec/tcmodule.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Offsets for the ROM header locations for - * TURBOchannel cards - * - * created from: - * - * TURBOchannel Firmware Specification - * - * EK-TCAAD-FS-004 - * from Digital Equipment Corporation - * - * Jan.1998 Harald Koerfgen - */ -#ifndef __ASM_DEC_TCMODULE_H -#define __ASM_DEC_TCMODULE_H - -#define OLDCARD 0x3c0000 -#define NEWCARD 0x000000 - -#define TC_ROM_WIDTH 0x3e0 -#define TC_ROM_STRIDE 0x3e4 -#define TC_ROM_SIZE 0x3e8 -#define TC_SLOT_SIZE 0x3ec -#define TC_PATTERN0 0x3f0 -#define TC_PATTERN1 0x3f4 -#define TC_PATTERN2 0x3f8 -#define TC_PATTERN3 0x3fc -#define TC_FIRM_VER 0x400 -#define TC_VENDOR 0x420 -#define TC_MODULE 0x440 -#define TC_FIRM_TYPE 0x460 -#define TC_FLAGS 0x470 -#define TC_ROM_OBJECTS 0x480 - -#endif /* __ASM_DEC_TCMODULE_H */ diff --git a/include/asm-mips64/div64.h b/include/asm-mips64/div64.h deleted file mode 100644 index 3ec1fadcfd7..00000000000 --- a/include/asm-mips64/div64.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef _ASM_DIV64_H -#define _ASM_DIV64_H - -/* - * Don't use this one in new code - */ -#define do_div64_32(res, high, low, base) ({ \ - unsigned int __quot, __mod; \ - unsigned long __div; \ - unsigned int __low, __high, __base; \ - \ - __high = (high); \ - __low = (low); \ - __div = __high; \ - __div = __div << 32 | __low; \ - __base = (base); \ - \ - __mod = __div % __base; \ - __div = __div / __base; \ - \ - __quot = __div; \ - (res) = __quot; \ - __mod; }) - -/* - * Hey, we're already 64-bit, no - * need to play games.. - */ -#define do_div(n, base) ({ \ - unsigned long __quot; \ - unsigned int __mod; \ - unsigned long __div; \ - unsigned int __base; \ - \ - __div = (n); \ - __base = (base); \ - \ - __mod = __div % __base; \ - __quot = __div / __base; \ - \ - (n) = __quot; \ - __mod; }) - -#endif /* _ASM_DIV64_H */ diff --git a/include/asm-mips64/dma-mapping.h b/include/asm-mips64/dma-mapping.h deleted file mode 100644 index 7b6254324cc..00000000000 --- a/include/asm-mips64/dma-mapping.h +++ /dev/null @@ -1,228 +0,0 @@ -#ifndef _ASM_DMA_MAPPING_H -#define _ASM_DMA_MAPPING_H - -#include - -#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) -#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) - -void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, int flag); - -void dma_free_coherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle); - -#ifdef CONFIG_MAPPED_DMA_IO - -extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction direction); -extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, - size_t size, enum dma_data_direction direction); -extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction); -extern dma_addr_t dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, enum dma_data_direction direction); -extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address, - size_t size, enum dma_data_direction direction); -extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, - int nhwentries, enum dma_data_direction direction); -extern void dma_sync_single(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction); -extern void dma_sync_single_range(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, enum dma_data_direction direction); -extern void dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction); - -#else - -static inline dma_addr_t -dma_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction direction) -{ - unsigned long addr = (unsigned long) ptr; - - BUG_ON(direction == DMA_NONE); - - dma_cache_wback_inv(addr, size); - - return bus_to_baddr(hwdev->bus, __pa(ptr)); -} - -static inline void -dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - - if (direction != DMA_TO_DEVICE) { - unsigned long addr; - - addr = baddr_to_bus(hwdev->bus, dma_addr) + PAGE_OFFSET; - dma_cache_wback_inv(addr, size); - } -} - -static inline int -dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction) -{ - int i; - - BUG_ON(direction == DMA_NONE); - - for (i = 0; i < nents; i++, sg++) { - unsigned long addr; - - addr = (unsigned long) page_address(sg->page); - if (addr) - dma_cache_wback_inv(addr + sg->offset, sg->length); - sg->dma_address = (dma_addr_t) bus_to_baddr(hwdev->bus, - page_to_phys(sg->page) + sg->offset); - } - - return nents; -} - -static inline dma_addr_t -dma_map_page(struct device *dev, struct page *page, unsigned long offset, - size_t size, enum dma_data_direction direction) -{ - unsigned long addr; - - BUG_ON(direction == DMA_NONE); - addr = (unsigned long) page_address(page) + offset; - dma_cache_wback_inv(addr, size); - - return bus_to_baddr(hwdev->bus, page_to_phys(page) + offset); -} - -static inline void -dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - - if (direction != DMA_TO_DEVICE) { - unsigned long addr; - - addr = baddr_to_bus(hwdev->bus, dma_address) + PAGE_OFFSET; - dma_cache_wback_inv(addr, size); - } -} - -static inline void -dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, - enum dma_data_direction direction) -{ - int i; - - BUG_ON(direction == DMA_NONE); - - if (direction == DMA_TO_DEVICE) - return; - - for (i = 0; i < nhwentries; i++, sg++) { - unsigned long addr; - - if (!sg->page) - BUG(); - - addr = (unsigned long) page_address(sg->page); - if (addr) - dma_cache_wback_inv(addr + sg->offset, sg->length); - } -} - -static inline void -dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ - unsigned long addr; - - if (direction == DMA_NONE) - BUG(); - - addr = baddr_to_bus(hwdev->bus, dma_handle) + PAGE_OFFSET; - dma_cache_wback_inv(addr, size); -} - -static inline void -dma_sync_single_range(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) -{ - unsigned long addr; - - if (direction == DMA_NONE) - BUG(); - - addr = baddr_to_bus(hwdev->bus, dma_handle) + PAGE_OFFSET; - dma_cache_wback_inv(addr, size); -} - -static inline void -dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) -{ -#ifdef CONFIG_NONCOHERENT_IO - int i; -#endif - - if (direction == DMA_NONE) - BUG(); - - /* Make sure that gcc doesn't leave the empty loop body. */ -#ifdef CONFIG_NONCOHERENT_IO - for (i = 0; i < nelems; i++, sg++) - dma_cache_wback_inv((unsigned long)page_address(sg->page), - sg->length); -#endif -} -#endif /* CONFIG_MAPPED_DMA_IO */ - -static inline int -dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < 0x00ffffff) - return 0; - - return 1; -} - -static inline int -dma_set_mask(struct device *dev, u64 mask) -{ - if(!dev->dma_mask || !dma_supported(dev, mask)) - return -EIO; - - *dev->dma_mask = mask; - - return 0; -} - -static inline int -dma_get_cache_alignment(void) -{ - /* XXX Largest on any MIPS */ - return 128; -} - -#ifdef CONFIG_NONCOHERENT_IO -#define dma_is_consistent(d) (0) -#else -#define dma_is_consistent(d) (1) -#endif - -static inline void -dma_cache_sync(void *vaddr, size_t size, - enum dma_data_direction direction) -{ - dma_cache_wback_inv((unsigned long)vaddr, size); -} - -#endif /* _ASM_DMA_MAPPING_H */ diff --git a/include/asm-mips64/dma.h b/include/asm-mips64/dma.h deleted file mode 100644 index 6aaf9939a71..00000000000 --- a/include/asm-mips64/dma.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * linux/include/asm/dma.h: Defines for using and allocating dma channels. - * Written by Hennus Bergman, 1992. - * High DMA channel support & info by Hannu Savolainen - * and John Boyd, Nov. 1992. - * - * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards - * and can only be used for expansion cards. Onboard DMA controllers, such - * as the R4030 on Jazz boards behave totally different! - */ - -#ifndef _ASM_DMA_H -#define _ASM_DMA_H - -#include -#include /* need byte IO */ -#include /* And spinlocks */ -#include -#include - - -#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER -#define dma_outb outb_p -#else -#define dma_outb outb -#endif - -#define dma_inb inb - -/* - * NOTES about DMA transfers: - * - * controller 1: channels 0-3, byte operations, ports 00-1F - * controller 2: channels 4-7, word operations, ports C0-DF - * - * - ALL registers are 8 bits only, regardless of transfer size - * - channel 4 is not used - cascades 1 into 2. - * - channels 0-3 are byte - addresses/counts are for physical bytes - * - channels 5-7 are word - addresses/counts are for physical words - * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries - * - transfer count loaded to registers is 1 less than actual count - * - controller 2 offsets are all even (2x offsets for controller 1) - * - page registers for 5-7 don't use data bit 0, represent 128K pages - * - page registers for 0-3 use bit 0, represent 64K pages - * - * DMA transfers are limited to the lower 16MB of _physical_ memory. - * Note that addresses loaded into registers must be _physical_ addresses, - * not logical addresses (which may differ if paging is active). - * - * Address mapping for channels 0-3: - * - * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) - * | ... | | ... | | ... | - * | ... | | ... | | ... | - * | ... | | ... | | ... | - * P7 ... P0 A7 ... A0 A7 ... A0 - * | Page | Addr MSB | Addr LSB | (DMA registers) - * - * Address mapping for channels 5-7: - * - * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) - * | ... | \ \ ... \ \ \ ... \ \ - * | ... | \ \ ... \ \ \ ... \ (not used) - * | ... | \ \ ... \ \ \ ... \ - * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 - * | Page | Addr MSB | Addr LSB | (DMA registers) - * - * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses - * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at - * the hardware level, so odd-byte transfers aren't possible). - * - * Transfer count (_not # bytes_) is limited to 64K, represented as actual - * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, - * and up to 128K bytes may be transferred on channels 5-7 in one operation. - * - */ - -#define MAX_DMA_CHANNELS 8 - -/* - * The maximum address in KSEG0 that we can perform a DMA transfer to on this - * platform. This describes only the PC style part of the DMA logic like on - * Deskstations or Acer PICA but not the much more versatile DMA logic used - * for the local devices on Acer PICA or Magnums. - */ -#ifdef CONFIG_SGI_IP22 -/* Horrible hack to have a correct DMA window on IP22 */ -#include -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SGIMC_SEG0_BADDR + 0x01000000) -#else -#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) -#endif - -/* 8237 DMA controllers */ -#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ -#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ - -/* DMA controller registers */ -#define DMA1_CMD_REG 0x08 /* command register (w) */ -#define DMA1_STAT_REG 0x08 /* status register (r) */ -#define DMA1_REQ_REG 0x09 /* request register (w) */ -#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ -#define DMA1_MODE_REG 0x0B /* mode register (w) */ -#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ -#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ -#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ -#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ -#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ - -#define DMA2_CMD_REG 0xD0 /* command register (w) */ -#define DMA2_STAT_REG 0xD0 /* status register (r) */ -#define DMA2_REQ_REG 0xD2 /* request register (w) */ -#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ -#define DMA2_MODE_REG 0xD6 /* mode register (w) */ -#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ -#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ -#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ -#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ -#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ - -#define DMA_ADDR_0 0x00 /* DMA address registers */ -#define DMA_ADDR_1 0x02 -#define DMA_ADDR_2 0x04 -#define DMA_ADDR_3 0x06 -#define DMA_ADDR_4 0xC0 -#define DMA_ADDR_5 0xC4 -#define DMA_ADDR_6 0xC8 -#define DMA_ADDR_7 0xCC - -#define DMA_CNT_0 0x01 /* DMA count registers */ -#define DMA_CNT_1 0x03 -#define DMA_CNT_2 0x05 -#define DMA_CNT_3 0x07 -#define DMA_CNT_4 0xC2 -#define DMA_CNT_5 0xC6 -#define DMA_CNT_6 0xCA -#define DMA_CNT_7 0xCE - -#define DMA_PAGE_0 0x87 /* DMA page registers */ -#define DMA_PAGE_1 0x83 -#define DMA_PAGE_2 0x81 -#define DMA_PAGE_3 0x82 -#define DMA_PAGE_5 0x8B -#define DMA_PAGE_6 0x89 -#define DMA_PAGE_7 0x8A - -#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ -#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ -#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ - -#define DMA_AUTOINIT 0x10 - -extern spinlock_t dma_spin_lock; - -static __inline__ unsigned long claim_dma_lock(void) -{ - unsigned long flags; - spin_lock_irqsave(&dma_spin_lock, flags); - return flags; -} - -static __inline__ void release_dma_lock(unsigned long flags) -{ - spin_unlock_irqrestore(&dma_spin_lock, flags); -} - -/* enable/disable a specific DMA channel */ -static __inline__ void enable_dma(unsigned int dmanr) -{ - if (dmanr<=3) - dma_outb(dmanr, DMA1_MASK_REG); - else - dma_outb(dmanr & 3, DMA2_MASK_REG); -} - -static __inline__ void disable_dma(unsigned int dmanr) -{ - if (dmanr<=3) - dma_outb(dmanr | 4, DMA1_MASK_REG); - else - dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); -} - -/* Clear the 'DMA Pointer Flip Flop'. - * Write 0 for LSB/MSB, 1 for MSB/LSB access. - * Use this once to initialize the FF to a known state. - * After that, keep track of it. :-) - * --- In order to do that, the DMA routines below should --- - * --- only be used while holding the DMA lock ! --- - */ -static __inline__ void clear_dma_ff(unsigned int dmanr) -{ - if (dmanr<=3) - dma_outb(0, DMA1_CLEAR_FF_REG); - else - dma_outb(0, DMA2_CLEAR_FF_REG); -} - -/* set mode (above) for a specific DMA channel */ -static __inline__ void set_dma_mode(unsigned int dmanr, char mode) -{ - if (dmanr<=3) - dma_outb(mode | dmanr, DMA1_MODE_REG); - else - dma_outb(mode | (dmanr&3), DMA2_MODE_REG); -} - -/* Set only the page register bits of the transfer address. - * This is used for successive transfers when we know the contents of - * the lower 16 bits of the DMA current address register, but a 64k boundary - * may have been crossed. - */ -static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) -{ - switch(dmanr) { - case 0: - dma_outb(pagenr, DMA_PAGE_0); - break; - case 1: - dma_outb(pagenr, DMA_PAGE_1); - break; - case 2: - dma_outb(pagenr, DMA_PAGE_2); - break; - case 3: - dma_outb(pagenr, DMA_PAGE_3); - break; - case 5: - dma_outb(pagenr & 0xfe, DMA_PAGE_5); - break; - case 6: - dma_outb(pagenr & 0xfe, DMA_PAGE_6); - break; - case 7: - dma_outb(pagenr & 0xfe, DMA_PAGE_7); - break; - } -} - - -/* Set transfer address & page bits for specific DMA channel. - * Assumes dma flipflop is clear. - */ -static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) -{ - set_dma_page(dmanr, a>>16); - if (dmanr <= 3) { - dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - } else { - dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - } -} - - -/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for - * a specific DMA channel. - * You must ensure the parameters are valid. - * NOTE: from a manual: "the number of transfers is one more - * than the initial word count"! This is taken into account. - * Assumes dma flip-flop is clear. - * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. - */ -static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) -{ - count--; - if (dmanr <= 3) { - dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - } else { - dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - } -} - - -/* Get DMA residue count. After a DMA transfer, this - * should return zero. Reading this while a DMA transfer is - * still in progress will return unpredictable results. - * If called before the channel has been used, it may return 1. - * Otherwise, it returns the number of _bytes_ left to transfer. - * - * Assumes DMA flip-flop is clear. - */ -static __inline__ int get_dma_residue(unsigned int dmanr) -{ - unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE - : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; - - /* using short to get 16-bit wrap around */ - unsigned short count; - - count = 1 + dma_inb(io_port); - count += dma_inb(io_port) << 8; - - return (dmanr<=3)? count : (count<<1); -} - - -/* These are in kernel/dma.c: */ -extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ -extern void free_dma(unsigned int dmanr); /* release it again */ - -/* From PCI */ - -#ifdef CONFIG_PCI -extern int isa_dma_bridge_buggy; -#else -#define isa_dma_bridge_buggy (0) -#endif - -#endif /* _ASM_DMA_H */ diff --git a/include/asm-mips64/ds1286.h b/include/asm-mips64/ds1286.h deleted file mode 100644 index 56af9b10d01..00000000000 --- a/include/asm-mips64/ds1286.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM - * Copyright Torsten Duwe 1993 - * derived from Data Sheet, Copyright Motorola 1984 (!). - * It was written to be part of the Linux operating system. - * - * Copyright (C) 1998, 1999 Ralf Baechle - */ -#ifndef _ASM_DS1286_h -#define _ASM_DS1286_h - -#include - -/********************************************************************** - * register summary - **********************************************************************/ -#define RTC_HUNDREDTH_SECOND 0 -#define RTC_SECONDS 1 -#define RTC_MINUTES 2 -#define RTC_MINUTES_ALARM 3 -#define RTC_HOURS 4 -#define RTC_HOURS_ALARM 5 -#define RTC_DAY 6 -#define RTC_DAY_ALARM 7 -#define RTC_DATE 8 -#define RTC_MONTH 9 -#define RTC_YEAR 10 -#define RTC_CMD 11 -#define RTC_WHSEC 12 -#define RTC_WSEC 13 -#define RTC_UNUSED 14 - -/* RTC_*_alarm is always true if 2 MSBs are set */ -# define RTC_ALARM_DONT_CARE 0xC0 - - -/* - * Bits in the month register - */ -#define RTC_EOSC 0x80 -#define RTC_ESQW 0x40 - -/* - * Bits in the Command register - */ -#define RTC_TDF 0x01 -#define RTC_WAF 0x02 -#define RTC_TDM 0x04 -#define RTC_WAM 0x08 -#define RTC_PU_LVL 0x10 -#define RTC_IBH_LO 0x20 -#define RTC_IPSW 0x40 -#define RTC_TE 0x80 - -#endif /* _ASM_DS1286_h */ diff --git a/include/asm-mips64/elf.h b/include/asm-mips64/elf.h deleted file mode 100644 index afc9d01c04f..00000000000 --- a/include/asm-mips64/elf.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_ELF_H -#define __ASM_ELF_H - -#include -#include - -/* ELF header e_flags defines. */ -/* MIPS architecture level. */ -#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ -#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ - -/* The ABI of a file. */ -#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ -#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */ - -#define PT_MIPS_REGINFO 0x70000000 -#define PT_MIPS_OPTIONS 0x70000001 - -/* Flags in the e_flags field of the header */ -#define EF_MIPS_NOREORDER 0x00000001 -#define EF_MIPS_PIC 0x00000002 -#define EF_MIPS_CPIC 0x00000004 -#define EF_MIPS_ABI2 0x00000020 -#define EF_MIPS_OPTIONS_FIRST 0x00000080 -#define EF_MIPS_32BITMODE 0x00000100 -#define EF_MIPS_ABI 0x0000f000 -#define EF_MIPS_ARCH 0xf0000000 - -#define DT_MIPS_RLD_VERSION 0x70000001 -#define DT_MIPS_TIME_STAMP 0x70000002 -#define DT_MIPS_ICHECKSUM 0x70000003 -#define DT_MIPS_IVERSION 0x70000004 -#define DT_MIPS_FLAGS 0x70000005 - #define RHF_NONE 0 - #define RHF_HARDWAY 1 - #define RHF_NOTPOT 2 -#define DT_MIPS_BASE_ADDRESS 0x70000006 -#define DT_MIPS_CONFLICT 0x70000008 -#define DT_MIPS_LIBLIST 0x70000009 -#define DT_MIPS_LOCAL_GOTNO 0x7000000a -#define DT_MIPS_CONFLICTNO 0x7000000b -#define DT_MIPS_LIBLISTNO 0x70000010 -#define DT_MIPS_SYMTABNO 0x70000011 -#define DT_MIPS_UNREFEXTNO 0x70000012 -#define DT_MIPS_GOTSYM 0x70000013 -#define DT_MIPS_HIPAGENO 0x70000014 -#define DT_MIPS_RLD_MAP 0x70000016 - -#define R_MIPS_NONE 0 -#define R_MIPS_16 1 -#define R_MIPS_32 2 -#define R_MIPS_REL32 3 -#define R_MIPS_26 4 -#define R_MIPS_HI16 5 -#define R_MIPS_LO16 6 -#define R_MIPS_GPREL16 7 -#define R_MIPS_LITERAL 8 -#define R_MIPS_GOT16 9 -#define R_MIPS_PC16 10 -#define R_MIPS_CALL16 11 -#define R_MIPS_GPREL32 12 -/* The remaining relocs are defined on Irix, although they are not - in the MIPS ELF ABI. */ -#define R_MIPS_UNUSED1 13 -#define R_MIPS_UNUSED2 14 -#define R_MIPS_UNUSED3 15 -#define R_MIPS_SHIFT5 16 -#define R_MIPS_SHIFT6 17 -#define R_MIPS_64 18 -#define R_MIPS_GOT_DISP 19 -#define R_MIPS_GOT_PAGE 20 -#define R_MIPS_GOT_OFST 21 -/* - * The following two relocation types are specified in the MIPS ABI - * conformance guide version 1.2 but not yet in the psABI. - */ -#define R_MIPS_GOTHI16 22 -#define R_MIPS_GOTLO16 23 -#define R_MIPS_SUB 24 -#define R_MIPS_INSERT_A 25 -#define R_MIPS_INSERT_B 26 -#define R_MIPS_DELETE 27 -#define R_MIPS_HIGHER 28 -#define R_MIPS_HIGHEST 29 -/* - * The following two relocation types are specified in the MIPS ABI - * conformance guide version 1.2 but not yet in the psABI. - */ -#define R_MIPS_CALLHI16 30 -#define R_MIPS_CALLLO16 31 -/* - * This range is reserved for vendor specific relocations. - */ -#define R_MIPS_LOVENDOR 100 -#define R_MIPS_HIVENDOR 127 - -#define SHN_MIPS_ACCOMON 0xff00 - -#define SHT_MIPS_LIST 0x70000000 -#define SHT_MIPS_CONFLICT 0x70000002 -#define SHT_MIPS_GPTAB 0x70000003 -#define SHT_MIPS_UCODE 0x70000004 - -#define SHF_MIPS_GPREL 0x10000000 - -#ifndef ELF_ARCH -/* ELF register definitions */ -#define ELF_NGREG 45 -#define ELF_NFPREG 33 - -typedef unsigned long elf_greg_t; -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef double elf_fpreg_t; -typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(hdr) \ -({ \ - int __res = 1; \ - struct elfhdr *__h = (hdr); \ - \ - if (__h->e_machine != EM_MIPS) \ - __res = 0; \ - if (__h->e_ident[EI_CLASS] == ELFCLASS32) \ - __res = 0; \ - \ - __res; \ -}) - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS64 -#ifdef __MIPSEB__ -#define ELF_DATA ELFDATA2MSB -#elif __MIPSEL__ -#define ELF_DATA ELFDATA2LSB -#endif -#define ELF_ARCH EM_MIPS -#endif /* !defined(ELF_ARCH) */ - -#define USE_ELF_CORE_DUMP -#define ELF_EXEC_PAGESIZE 4096 - -#define ELF_CORE_COPY_REGS(_dest,_regs) \ - memcpy((char *) &_dest, (char *) _regs, \ - sizeof(struct pt_regs)); - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. This could be done in userspace, - but it's not easy, and we've already done it here. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. - - For the moment, we have only optimizations for the Intel generations, - but that could change... */ - -#define ELF_PLATFORM (NULL) - -/* - * See comments in asm-alpha/elf.h, this is the same thing - * on the MIPS. - */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0; \ - _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0; \ - _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0; \ - _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0; \ - _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0; \ - _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0; \ - _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0; \ - _r->regs[30] = _r->regs[31] = 0; \ -} while (0) - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#ifndef ELF_ET_DYN_BASE -#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) -#endif - -#ifdef __KERNEL__ -#define SET_PERSONALITY(ex, ibcs2) \ -do { current->thread.mflags &= ~MF_ABI_MASK; \ - if ((ex).e_ident[EI_CLASS] == ELFCLASS32) { \ - if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ - ((ex).e_flags & EF_MIPS_ABI) == 0) \ - current->thread.mflags |= MF_N32; \ - else \ - current->thread.mflags |= MF_O32; \ - } else \ - current->thread.mflags |= MF_N64; \ - if (ibcs2) \ - set_personality(PER_SVR4); \ - else if (current->personality != PER_LINUX32) \ - set_personality(PER_LINUX); \ -} while (0) -#endif - -#endif /* __ASM_ELF_H */ diff --git a/include/asm-mips64/errno.h b/include/asm-mips64/errno.h deleted file mode 100644 index 35d47a88280..00000000000 --- a/include/asm-mips64/errno.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle - */ -#ifndef _ASM_ERRNO_H -#define _ASM_ERRNO_H - -/* - * These error numbers are intended to be MIPS ABI compatible - */ - -#include - -#define ENOMSG 35 /* No message of desired type */ -#define EIDRM 36 /* Identifier removed */ -#define ECHRNG 37 /* Channel number out of range */ -#define EL2NSYNC 38 /* Level 2 not synchronized */ -#define EL3HLT 39 /* Level 3 halted */ -#define EL3RST 40 /* Level 3 reset */ -#define ELNRNG 41 /* Link number out of range */ -#define EUNATCH 42 /* Protocol driver not attached */ -#define ENOCSI 43 /* No CSI structure available */ -#define EL2HLT 44 /* Level 2 halted */ -#define EDEADLK 45 /* Resource deadlock would occur */ -#define ENOLCK 46 /* No record locks available */ -#define EBADE 50 /* Invalid exchange */ -#define EBADR 51 /* Invalid request descriptor */ -#define EXFULL 52 /* Exchange full */ -#define ENOANO 53 /* No anode */ -#define EBADRQC 54 /* Invalid request code */ -#define EBADSLT 55 /* Invalid slot */ -#define EDEADLOCK 56 /* File locking deadlock error */ -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EDOTDOT 73 /* RFS specific error */ -#define EMULTIHOP 74 /* Multihop attempted */ -#define EBADMSG 77 /* Not a data message */ -#define ENAMETOOLONG 78 /* File name too long */ -#define EOVERFLOW 79 /* Value too large for defined data type */ -#define ENOTUNIQ 80 /* Name not unique on network */ -#define EBADFD 81 /* File descriptor in bad state */ -#define EREMCHG 82 /* Remote address changed */ -#define ELIBACC 83 /* Can not access a needed shared library */ -#define ELIBBAD 84 /* Accessing a corrupted shared library */ -#define ELIBSCN 85 /* .lib section in a.out corrupted */ -#define ELIBMAX 86 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 87 /* Cannot exec a shared library directly */ -#define EILSEQ 88 /* Illegal byte sequence */ -#define ENOSYS 89 /* Function not implemented */ -#define ELOOP 90 /* Too many symbolic links encountered */ -#define ERESTART 91 /* Interrupted system call should be restarted */ -#define ESTRPIPE 92 /* Streams pipe error */ -#define ENOTEMPTY 93 /* Directory not empty */ -#define EUSERS 94 /* Too many users */ -#define ENOTSOCK 95 /* Socket operation on non-socket */ -#define EDESTADDRREQ 96 /* Destination address required */ -#define EMSGSIZE 97 /* Message too long */ -#define EPROTOTYPE 98 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 99 /* Protocol not available */ -#define EPROTONOSUPPORT 120 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 121 /* Socket type not supported */ -#define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 123 /* Protocol family not supported */ -#define EAFNOSUPPORT 124 /* Address family not supported by protocol */ -#define EADDRINUSE 125 /* Address already in use */ -#define EADDRNOTAVAIL 126 /* Cannot assign requested address */ -#define ENETDOWN 127 /* Network is down */ -#define ENETUNREACH 128 /* Network is unreachable */ -#define ENETRESET 129 /* Network dropped connection because of reset */ -#define ECONNABORTED 130 /* Software caused connection abort */ -#define ECONNRESET 131 /* Connection reset by peer */ -#define ENOBUFS 132 /* No buffer space available */ -#define EISCONN 133 /* Transport endpoint is already connected */ -#define ENOTCONN 134 /* Transport endpoint is not connected */ -#define EUCLEAN 135 /* Structure needs cleaning */ -#define ENOTNAM 137 /* Not a XENIX named type file */ -#define ENAVAIL 138 /* No XENIX semaphores available */ -#define EISNAM 139 /* Is a named type file */ -#define EREMOTEIO 140 /* Remote I/O error */ -#define EINIT 141 /* Reserved */ -#define EREMDEV 142 /* Error 142 */ -#define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 144 /* Too many references: cannot splice */ -#define ETIMEDOUT 145 /* Connection timed out */ -#define ECONNREFUSED 146 /* Connection refused */ -#define EHOSTDOWN 147 /* Host is down */ -#define EHOSTUNREACH 148 /* No route to host */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define EALREADY 149 /* Operation already in progress */ -#define EINPROGRESS 150 /* Operation now in progress */ -#define ESTALE 151 /* Stale NFS file handle */ -#define ECANCELED 158 /* AIO operation canceled */ - -/* - * These error are Linux extensions. - */ -#define ENOMEDIUM 159 /* No medium found */ -#define EMEDIUMTYPE 160 /* Wrong medium type */ - -#define EDQUOT 1133 /* Quota exceeded */ - -#ifdef __KERNEL__ - -/* The biggest error number defined here or in . */ -#define EMAXERRNO 1133 - -#endif /* __KERNEL__ */ - -#endif /* _ASM_ERRNO_H */ diff --git a/include/asm-mips64/fcntl.h b/include/asm-mips64/fcntl.h deleted file mode 100644 index e425a22f433..00000000000 --- a/include/asm-mips64/fcntl.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 by Ralf Baechle - */ -#ifndef _ASM_FCNTL_H -#define _ASM_FCNTL_H - -/* open/fcntl - O_SYNC is only implemented on blocks devices and on files - located on an ext2 file system */ -#define O_ACCMODE 0x0003 -#define O_RDONLY 0x0000 -#define O_WRONLY 0x0001 -#define O_RDWR 0x0002 -#define O_APPEND 0x0008 -#define O_SYNC 0x0010 -#define O_NONBLOCK 0x0080 -#define O_CREAT 0x0100 /* not fcntl */ -#define O_TRUNC 0x0200 /* not fcntl */ -#define O_EXCL 0x0400 /* not fcntl */ -#define O_NOCTTY 0x0800 /* not fcntl */ -#define FASYNC 0x1000 /* fcntl, for BSD compatibility */ -#define O_LARGEFILE 0x2000 /* allow large file opens */ -#define O_DIRECT 0x8000 /* direct disk access hint */ -#define O_DIRECTORY 0x10000 /* must be a directory */ -#define O_NOFOLLOW 0x20000 /* don't follow links */ - -#define O_NDELAY O_NONBLOCK - -#define F_DUPFD 0 /* dup */ -#define F_GETFD 1 /* get close_on_exec */ -#define F_SETFD 2 /* set/clear close_on_exec */ -#define F_GETFL 3 /* get file->f_flags */ -#define F_SETFL 4 /* set file->f_flags */ -#define F_GETLK 14 -#define F_SETLK 6 -#define F_SETLKW 7 - -#define F_SETOWN 24 /* for sockets. */ -#define F_GETOWN 23 /* for sockets. */ -#define F_SETSIG 10 /* for sockets. */ -#define F_GETSIG 11 /* for sockets. */ - -#ifdef __KERNEL__ -#define F_GETLK64 33 /* using 'struct flock64' */ -#define F_SETLK64 34 -#define F_SETLKW64 35 -#endif - -/* for F_[GET|SET]FL */ -#define FD_CLOEXEC 1 /* actually anything with low bit set goes */ - -/* for posix fcntl() and lockf() */ -#define F_RDLCK 0 -#define F_WRLCK 1 -#define F_UNLCK 2 - -/* for old implementation of bsd flock () */ -#define F_EXLCK 4 /* or 3 */ -#define F_SHLCK 8 /* or 4 */ - -/* for leases */ -#define F_INPROGRESS 16 - -/* operations for bsd flock(), also used by the kernel implementation */ -#define LOCK_SH 1 /* shared lock */ -#define LOCK_EX 2 /* exclusive lock */ -#define LOCK_NB 4 /* or'd with one of the above to prevent - blocking */ -#define LOCK_UN 8 /* remove lock */ - -#define LOCK_MAND 32 /* This is a mandatory flock */ -#define LOCK_READ 64 /* ... Which allows concurrent read operations */ -#define LOCK_WRITE 128 /* ... Which allows concurrent write operations */ -#define LOCK_RW 192 /* ... Which allows concurrent read & write ops */ - -typedef struct flock { - short l_type; - short l_whence; - __kernel_off_t l_start; - __kernel_off_t l_len; - __kernel_pid_t l_pid; -} flock_t; - -#ifdef __KERNEL__ -#define flock64 flock -#endif - -#define F_LINUX_SPECIFIC_BASE 1024 - -#endif /* _ASM_FCNTL_H */ diff --git a/include/asm-mips64/floppy.h b/include/asm-mips64/floppy.h deleted file mode 100644 index 29b7c27b13a..00000000000 --- a/include/asm-mips64/floppy.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Architecture specific parts of the Floppy driver - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 - 2000 Ralf Baechle - */ -#ifndef _ASM_FLOPPY_H -#define _ASM_FLOPPY_H - -struct fd_ops { - unsigned char (*fd_inb)(unsigned int port); - void (*fd_outb)(unsigned char value, unsigned int port); - - /* - * How to access the floppy DMA functions. - */ - void (*fd_enable_dma)(int channel); - void (*fd_disable_dma)(int channel); - int (*fd_request_dma)(int channel); - void (*fd_free_dma)(int channel); - void (*fd_clear_dma_ff)(int channel); - void (*fd_set_dma_mode)(int channel, char mode); - void (*fd_set_dma_addr)(int channel, unsigned int a); - void (*fd_set_dma_count)(int channel, unsigned int count); - int (*fd_get_dma_residue)(int channel); - void (*fd_enable_irq)(int irq); - void (*fd_disable_irq)(int irq); - unsigned long (*fd_getfdaddr1)(void); - unsigned long (*fd_dma_mem_alloc)(unsigned long size); - void (*fd_dma_mem_free)(unsigned long addr, unsigned long size); - unsigned long (*fd_drive_type)(unsigned long); -}; - -extern struct fd_ops *fd_ops; - -#define fd_inb(port) fd_ops->fd_inb(port) -#define fd_outb(value,port) fd_ops->fd_outb(value,port) - -#define fd_enable_dma() fd_ops->fd_enable_dma(FLOPPY_DMA) -#define fd_disable_dma() fd_ops->fd_disable_dma(FLOPPY_DMA) -#define fd_request_dma() fd_ops->fd_request_dma(FLOPPY_DMA) -#define fd_free_dma() fd_ops->fd_free_dma(FLOPPY_DMA) -#define fd_clear_dma_ff() fd_ops->fd_clear_dma_ff(FLOPPY_DMA) -#define fd_set_dma_mode(mode) fd_ops->fd_set_dma_mode(FLOPPY_DMA, mode) -#define fd_set_dma_addr(addr) fd_ops->fd_set_dma_addr(FLOPPY_DMA, \ - isa_virt_to_bus(addr)) -#define fd_set_dma_count(count) fd_ops->fd_set_dma_count(FLOPPY_DMA,count) -#define fd_get_dma_residue() fd_ops->fd_get_dma_residue(FLOPPY_DMA) - -#define fd_enable_irq() fd_ops->fd_enable_irq(FLOPPY_IRQ) -#define fd_disable_irq() fd_ops->fd_disable_irq(FLOPPY_IRQ) -#define fd_request_irq() request_irq(FLOPPY_IRQ, floppy_interrupt, \ - SA_INTERRUPT | SA_SAMPLE_RANDOM, \ - "floppy", NULL) -#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); -#define fd_dma_mem_alloc(size) fd_ops->fd_dma_mem_alloc(size) -#define fd_dma_mem_free(mem,size) fd_ops->fd_dma_mem_free(mem,size) -#define fd_drive_type(n) fd_ops->fd_drive_type(n) -#define fd_cacheflush(addr,size) \ - dma_cache_wback_inv((unsigned long)(addr),(size)) - -#define MAX_BUFFER_SECTORS 24 - - -/* - * And on Mips's the CMOS info fails also ... - * - * FIXME: This information should come from the ARC configuration tree - * or whereever a particular machine has stored this ... - */ -#define FLOPPY0_TYPE fd_drive_type(0) -#define FLOPPY1_TYPE fd_drive_type(1) - -#define FDC1 fd_ops->fd_getfdaddr1(); - -#define N_FDC 1 /* do you *really* want a second controller? */ -#define N_DRIVE 8 - -#define FLOPPY_MOTOR_MASK 0xf0 - -/* - * The DMA channel used by the floppy controller cannot access data at - * addresses >= 16MB - * - * Went back to the 1MB limit, as some people had problems with the floppy - * driver otherwise. It doesn't matter much for performance anyway, as most - * floppy accesses go through the track buffer. - * - * On MIPSes using vdma, this actually means that *all* transfers go thru - * the * track buffer since 0x1000000 is always smaller than KSEG0/1. - * Actually this needs to be a bit more complicated since the so much different - * hardware available with MIPS CPUs ... - */ -#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64) - -#define EXTRA_FLOPPY_PARAMS - -#endif /* _ASM_FLOPPY_H */ diff --git a/include/asm-mips64/fpregdef.h b/include/asm-mips64/fpregdef.h deleted file mode 100644 index 5437cf10924..00000000000 --- a/include/asm-mips64/fpregdef.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Definitions for the FPU register names - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999 Ralf Baechle - * Copyright (C) 1985 MIPS Computer Systems, Inc. - * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_FPREGDEF_H -#define _ASM_FPREGDEF_H - -#define fv0 $f0 /* return value */ -#define fv1 $f2 -#define fa0 $f12 /* argument registers */ -#define fa1 $f13 -#define fa2 $f14 -#define fa3 $f15 -#define fa4 $f16 -#define fa5 $f17 -#define fa6 $f18 -#define fa7 $f19 -#define ft0 $f4 /* caller saved */ -#define ft1 $f5 -#define ft2 $f6 -#define ft3 $f7 -#define ft4 $f8 -#define ft5 $f9 -#define ft6 $f10 -#define ft7 $f11 -#define ft8 $f20 -#define ft9 $f21 -#define ft10 $f22 -#define ft11 $f23 -#define ft12 $f1 -#define ft13 $f3 -#define fs0 $f24 /* callee saved */ -#define fs1 $f25 -#define fs2 $f26 -#define fs3 $f27 -#define fs4 $f28 -#define fs5 $f29 -#define fs6 $f30 -#define fs7 $f31 - -#define fcr31 $31 - -#endif /* _ASM_FPREGDEF_H */ diff --git a/include/asm-mips64/fpu.h b/include/asm-mips64/fpu.h deleted file mode 100644 index 1957677c451..00000000000 --- a/include/asm-mips64/fpu.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (C) 2002 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _ASM_FPU_H -#define _ASM_FPU_H - -#include -#include -#include - -#include -#include -#include -#include -#include - -struct sigcontext; -struct sigcontext32; - -extern asmlinkage int (*save_fp_context)(struct sigcontext *sc); -extern asmlinkage int (*restore_fp_context)(struct sigcontext *sc); - -extern asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc); -extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc); - -extern void fpu_emulator_init_fpu(void); -extern void _init_fpu(void); -extern void _save_fp(struct task_struct *); -extern void _restore_fp(struct task_struct *); - -#if defined(CONFIG_CPU_SB1) -#define __enable_fpu_hazard() \ -do { \ - asm(".set push \n\t" \ - ".set mips64 \n\t" \ - ".set noreorder \n\t" \ - "ssnop \n\t" \ - "bnezl $0, .+4 \n\t" \ - "ssnop \n\t" \ - ".set pop"); \ -} while (0) -#else -#define __enable_fpu_hazard() \ -do { \ - asm("nop;nop;nop;nop"); /* max. hazard */ \ -} while (0) -#endif - -#define __enable_fpu() \ -do { \ - set_c0_status(ST0_CU1); \ - __enable_fpu_hazard(); \ -} while (0) - -#define __disable_fpu() \ -do { \ - clear_c0_status(ST0_CU1); \ - /* We don't care about the c0 hazard here */ \ -} while (0) - -#define enable_fpu() \ -do { \ - if (cpu_has_fpu) \ - __enable_fpu(); \ -} while (0) - -#define disable_fpu() \ -do { \ - if (cpu_has_fpu) \ - __disable_fpu(); \ -} while (0) - - -#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) - -static inline int is_fpu_owner(void) -{ - return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); -} - -static inline void own_fpu(void) -{ - if (cpu_has_fpu) { - __enable_fpu(); - KSTK_STATUS(current) |= ST0_CU1; - set_thread_flag(TIF_USEDFPU); - } -} - -static inline void lose_fpu(void) -{ - if (cpu_has_fpu) { - KSTK_STATUS(current) &= ~ST0_CU1; - clear_thread_flag(TIF_USEDFPU); - __disable_fpu(); - } -} - -static inline void init_fpu(void) -{ - if (cpu_has_fpu) { - _init_fpu(); - } else { - fpu_emulator_init_fpu(); - } -} - -static inline void save_fp(struct task_struct *tsk) -{ - if (cpu_has_fpu) - _save_fp(tsk); -} - -static inline void restore_fp(struct task_struct *tsk) -{ - if (cpu_has_fpu) - _restore_fp(tsk); -} - -static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) -{ - if (cpu_has_fpu) { - if ((tsk == current) && is_fpu_owner()) - _save_fp(current); - return tsk->thread.fpu.hard.fpr; - } - - return tsk->thread.fpu.soft.fpr; -} - -#endif /* _ASM_FPU_H */ diff --git a/include/asm-mips64/fpu_emulator.h b/include/asm-mips64/fpu_emulator.h deleted file mode 100644 index 46972ae2b95..00000000000 --- a/include/asm-mips64/fpu_emulator.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Further private data for which no space exists in mips_fpu_soft_struct. - * This should be subsumed into the mips_fpu_soft_struct structure as - * defined in processor.h as soon as the absurd wired absolute assembler - * offsets become dynamic at compile time. - * - * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - */ -#ifndef _ASM_FPU_EMULATOR_H -#define _ASM_FPU_EMULATOR_H - -struct mips_fpu_emulator_private { - unsigned int eir; - struct { - unsigned int emulated; - unsigned int loads; - unsigned int stores; - unsigned int cp1ops; - unsigned int cp1xops; - unsigned int errors; - } stats; -}; - -#endif /* _ASM_FPU_EMULATOR_H */ diff --git a/include/asm-mips64/gcc/sgidefs.h b/include/asm-mips64/gcc/sgidefs.h deleted file mode 100644 index 05994371a2a..00000000000 --- a/include/asm-mips64/gcc/sgidefs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * include/sgidefs.h - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996 by Ralf Baechle - * - * This file is here to satisfy GCC's expectations. - */ -#ifndef __SGIDEFS_H -#define __SGIDEFS_H - -#include - -#endif /* __SGIDEFS_H */ diff --git a/include/asm-mips64/gdb-stub.h b/include/asm-mips64/gdb-stub.h deleted file mode 100644 index a3266c8957d..00000000000 --- a/include/asm-mips64/gdb-stub.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 Andreas Busse - */ -#ifndef __ASM_MIPS_GDB_STUB_H -#define __ASM_MIPS_GDB_STUB_H - - -/* - * important register numbers - */ - -#define REG_EPC 37 -#define REG_FP 72 -#define REG_SP 29 - -/* - * Stack layout for the GDB exception handler - * Derived from the stack layout described in asm-mips/stackframe.h - * - * The first PTRSIZE*5 bytes are argument save space for C subroutines. - */ -#define NUMREGS 90 - -#define GDB_FR_REG0 (PTRSIZE*5) /* 0 */ -#define GDB_FR_REG1 ((GDB_FR_REG0) + 8) /* 1 */ -#define GDB_FR_REG2 ((GDB_FR_REG1) + 8) /* 2 */ -#define GDB_FR_REG3 ((GDB_FR_REG2) + 8) /* 3 */ -#define GDB_FR_REG4 ((GDB_FR_REG3) + 8) /* 4 */ -#define GDB_FR_REG5 ((GDB_FR_REG4) + 8) /* 5 */ -#define GDB_FR_REG6 ((GDB_FR_REG5) + 8) /* 6 */ -#define GDB_FR_REG7 ((GDB_FR_REG6) + 8) /* 7 */ -#define GDB_FR_REG8 ((GDB_FR_REG7) + 8) /* 8 */ -#define GDB_FR_REG9 ((GDB_FR_REG8) + 8) /* 9 */ -#define GDB_FR_REG10 ((GDB_FR_REG9) + 8) /* 10 */ -#define GDB_FR_REG11 ((GDB_FR_REG10) + 8) /* 11 */ -#define GDB_FR_REG12 ((GDB_FR_REG11) + 8) /* 12 */ -#define GDB_FR_REG13 ((GDB_FR_REG12) + 8) /* 13 */ -#define GDB_FR_REG14 ((GDB_FR_REG13) + 8) /* 14 */ -#define GDB_FR_REG15 ((GDB_FR_REG14) + 8) /* 15 */ -#define GDB_FR_REG16 ((GDB_FR_REG15) + 8) /* 16 */ -#define GDB_FR_REG17 ((GDB_FR_REG16) + 8) /* 17 */ -#define GDB_FR_REG18 ((GDB_FR_REG17) + 8) /* 18 */ -#define GDB_FR_REG19 ((GDB_FR_REG18) + 8) /* 19 */ -#define GDB_FR_REG20 ((GDB_FR_REG19) + 8) /* 20 */ -#define GDB_FR_REG21 ((GDB_FR_REG20) + 8) /* 21 */ -#define GDB_FR_REG22 ((GDB_FR_REG21) + 8) /* 22 */ -#define GDB_FR_REG23 ((GDB_FR_REG22) + 8) /* 23 */ -#define GDB_FR_REG24 ((GDB_FR_REG23) + 8) /* 24 */ -#define GDB_FR_REG25 ((GDB_FR_REG24) + 8) /* 25 */ -#define GDB_FR_REG26 ((GDB_FR_REG25) + 8) /* 26 */ -#define GDB_FR_REG27 ((GDB_FR_REG26) + 8) /* 27 */ -#define GDB_FR_REG28 ((GDB_FR_REG27) + 8) /* 28 */ -#define GDB_FR_REG29 ((GDB_FR_REG28) + 8) /* 29 */ -#define GDB_FR_REG30 ((GDB_FR_REG29) + 8) /* 30 */ -#define GDB_FR_REG31 ((GDB_FR_REG30) + 8) /* 31 */ - -/* - * Saved special registers - */ -#define GDB_FR_STATUS ((GDB_FR_REG31) + 8) /* 32 */ -#define GDB_FR_LO ((GDB_FR_STATUS) + 8) /* 33 */ -#define GDB_FR_HI ((GDB_FR_LO) + 8) /* 34 */ -#define GDB_FR_BADVADDR ((GDB_FR_HI) + 8) /* 35 */ -#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + 8) /* 36 */ -#define GDB_FR_EPC ((GDB_FR_CAUSE) + 8) /* 37 */ - -/* - * Saved floating point registers - */ -#define GDB_FR_FPR0 ((GDB_FR_EPC) + 8) /* 38 */ -#define GDB_FR_FPR1 ((GDB_FR_FPR0) + 8) /* 39 */ -#define GDB_FR_FPR2 ((GDB_FR_FPR1) + 8) /* 40 */ -#define GDB_FR_FPR3 ((GDB_FR_FPR2) + 8) /* 41 */ -#define GDB_FR_FPR4 ((GDB_FR_FPR3) + 8) /* 42 */ -#define GDB_FR_FPR5 ((GDB_FR_FPR4) + 8) /* 43 */ -#define GDB_FR_FPR6 ((GDB_FR_FPR5) + 8) /* 44 */ -#define GDB_FR_FPR7 ((GDB_FR_FPR6) + 8) /* 45 */ -#define GDB_FR_FPR8 ((GDB_FR_FPR7) + 8) /* 46 */ -#define GDB_FR_FPR9 ((GDB_FR_FPR8) + 8) /* 47 */ -#define GDB_FR_FPR10 ((GDB_FR_FPR9) + 8) /* 48 */ -#define GDB_FR_FPR11 ((GDB_FR_FPR10) + 8) /* 49 */ -#define GDB_FR_FPR12 ((GDB_FR_FPR11) + 8) /* 50 */ -#define GDB_FR_FPR13 ((GDB_FR_FPR12) + 8) /* 51 */ -#define GDB_FR_FPR14 ((GDB_FR_FPR13) + 8) /* 52 */ -#define GDB_FR_FPR15 ((GDB_FR_FPR14) + 8) /* 53 */ -#define GDB_FR_FPR16 ((GDB_FR_FPR15) + 8) /* 54 */ -#define GDB_FR_FPR17 ((GDB_FR_FPR16) + 8) /* 55 */ -#define GDB_FR_FPR18 ((GDB_FR_FPR17) + 8) /* 56 */ -#define GDB_FR_FPR19 ((GDB_FR_FPR18) + 8) /* 57 */ -#define GDB_FR_FPR20 ((GDB_FR_FPR19) + 8) /* 58 */ -#define GDB_FR_FPR21 ((GDB_FR_FPR20) + 8) /* 59 */ -#define GDB_FR_FPR22 ((GDB_FR_FPR21) + 8) /* 60 */ -#define GDB_FR_FPR23 ((GDB_FR_FPR22) + 8) /* 61 */ -#define GDB_FR_FPR24 ((GDB_FR_FPR23) + 8) /* 62 */ -#define GDB_FR_FPR25 ((GDB_FR_FPR24) + 8) /* 63 */ -#define GDB_FR_FPR26 ((GDB_FR_FPR25) + 8) /* 64 */ -#define GDB_FR_FPR27 ((GDB_FR_FPR26) + 8) /* 65 */ -#define GDB_FR_FPR28 ((GDB_FR_FPR27) + 8) /* 66 */ -#define GDB_FR_FPR29 ((GDB_FR_FPR28) + 8) /* 67 */ -#define GDB_FR_FPR30 ((GDB_FR_FPR29) + 8) /* 68 */ -#define GDB_FR_FPR31 ((GDB_FR_FPR30) + 8) /* 69 */ - -#define GDB_FR_FSR ((GDB_FR_FPR31) + 8) /* 70 */ -#define GDB_FR_FIR ((GDB_FR_FSR) + 8) /* 71 */ -#define GDB_FR_FRP ((GDB_FR_FIR) + 8) /* 72 */ - -#define GDB_FR_DUMMY ((GDB_FR_FRP) + 8) /* 73, unused ??? */ - -/* - * Again, CP0 registers - */ -#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + 8) /* 74 */ -#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + 8) /* 75 */ -#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + 8) /* 76 */ -#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + 8) /* 77 */ -#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + 8) /* 78 */ -#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + 8) /* 79 */ -#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + 8) /* 80 */ -#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + 8) /* 81 */ -#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + 8) /* 82 */ -#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + 8) /* 83 */ -#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + 8) /* 84 */ -#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + 8) /* 85 */ -#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + 8) /* 86 */ -#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + 8) /* 87 */ -#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + 8) /* 88 */ -#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + 8) /* 89 */ - -#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + 8) + (PTRSIZE-1)) & ~(PTRSIZE-1)) - -#ifndef __ASSEMBLY__ - -/* - * This is the same as above, but for the high-level - * part of the GDB stub. - */ - -struct gdb_regs { - /* - * Pad bytes for argument save space on the stack - * 20/40 Bytes for 32/64 bit code - */ - unsigned long pad0[5]; - - /* - * saved main processor registers - */ - long reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; - long reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15; - long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23; - long reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31; - - /* - * Saved special registers - */ - long cp0_status; - long lo; - long hi; - long cp0_badvaddr; - long cp0_cause; - long cp0_epc; - - /* - * Saved floating point registers - */ - long fpr0, fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7; - long fpr8, fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15; - long fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23; - long fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31; - - long cp1_fsr; - long cp1_fir; - - /* - * Frame pointer - */ - long frame_ptr; - long dummy; /* unused */ - - /* - * saved cp0 registers - */ - long cp0_index; - long cp0_random; - long cp0_entrylo0; - long cp0_entrylo1; - long cp0_context; - long cp0_pagemask; - long cp0_wired; - long cp0_reg7; - long cp0_reg8; - long cp0_reg9; - long cp0_entryhi; - long cp0_reg11; - long cp0_reg12; - long cp0_reg13; - long cp0_reg14; - long cp0_prid; -}; - -/* - * Prototypes - */ - -void set_debug_traps(void); -void set_async_breakpoint(unsigned long *epc); - -#endif /* !__ASSEMBLY__ */ -#endif /* __ASM_MIPS_GDB_STUB_H */ diff --git a/include/asm-mips64/gfx.h b/include/asm-mips64/gfx.h deleted file mode 100644 index 37235e41a6f..00000000000 --- a/include/asm-mips64/gfx.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This is the user-visible SGI GFX interface. - * - * This must be used verbatim into the GNU libc. It does not include - * any kernel-only bits on it. - * - * miguel@nuclecu.unam.mx - */ -#ifndef _ASM_GFX_H -#define _ASM_GFX_H - -/* The iocls, yes, they do not make sense, but such is life */ -#define GFX_BASE 100 -#define GFX_GETNUM_BOARDS (GFX_BASE + 1) -#define GFX_GETBOARD_INFO (GFX_BASE + 2) -#define GFX_ATTACH_BOARD (GFX_BASE + 3) -#define GFX_DETACH_BOARD (GFX_BASE + 4) -#define GFX_IS_MANAGED (GFX_BASE + 5) - -#define GFX_MAPALL (GFX_BASE + 10) -#define GFX_LABEL (GFX_BASE + 11) - -#define GFX_INFO_NAME_SIZE 16 -#define GFX_INFO_LABEL_SIZE 16 - -struct gfx_info { - char name [GFX_INFO_NAME_SIZE]; /* board name */ - char label [GFX_INFO_LABEL_SIZE]; /* label name */ - unsigned short int xpmax, ypmax; /* screen resolution */ - unsigned int lenght; /* size of a complete gfx_info for this board */ -}; - -struct gfx_getboardinfo_args { - unsigned int board; /* board number. starting from zero */ - void *buf; /* pointer to gfx_info */ - unsigned int len; /* buffer size of buf */ -}; - -struct gfx_attach_board_args { - unsigned int board; /* board number, starting from zero */ - void *vaddr; /* address where the board registers should be mapped */ -}; - -#ifdef __KERNEL__ -/* umap.c */ -extern void remove_mapping (struct vm_area_struct *vma, struct task_struct *, unsigned long, unsigned long); -extern void *vmalloc_uncached (unsigned long size); -extern int vmap_page_range (struct vm_area_struct *vma, unsigned long from, unsigned long size, unsigned long vaddr); -#endif - -#endif /* _ASM_GFX_H */ diff --git a/include/asm-mips64/gt64120.h b/include/asm-mips64/gt64120.h deleted file mode 100644 index 9cf9edcdd54..00000000000 --- a/include/asm-mips64/gt64120.h +++ /dev/null @@ -1,399 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef _ASM_GT64120_H -#define _ASM_GT64120_H - -#define MSK(n) ((1 << (n)) - 1) - -/* - * Register offset addresses - */ -#define GT_CPU_OFS 0x000 - -/* - * Interrupt Registers - */ -#define GT_SCS10LD_OFS 0x008 -#define GT_SCS10HD_OFS 0x010 -#define GT_SCS32LD_OFS 0x018 -#define GT_SCS32HD_OFS 0x020 -#define GT_CS20LD_OFS 0x028 -#define GT_CS20HD_OFS 0x030 -#define GT_CS3BOOTLD_OFS 0x038 -#define GT_CS3BOOTHD_OFS 0x040 -#define GT_PCI0IOLD_OFS 0x048 -#define GT_PCI0IOHD_OFS 0x050 -#define GT_PCI0M0LD_OFS 0x058 -#define GT_PCI0M0HD_OFS 0x060 -#define GT_ISD_OFS 0x068 -#define GT_PCI0M1LD_OFS 0x080 -#define GT_PCI0M1HD_OFS 0x088 -#define GT_PCI1IOLD_OFS 0x090 -#define GT_PCI1IOHD_OFS 0x098 -#define GT_PCI1M0LD_OFS 0x0a0 -#define GT_PCI1M0HD_OFS 0x0a8 -#define GT_PCI1M1LD_OFS 0x0b0 -#define GT_PCI1M1HD_OFS 0x0b8 - -/* - * GT64120A only - */ -#define GT_PCI0IOREMAP_OFS 0x0f0 -#define GT_PCI0M0REMAP_OFS 0x0f8 -#define GT_PCI0M1REMAP_OFS 0x100 -#define GT_PCI1IOREMAP_OFS 0x108 -#define GT_PCI1M0REMAP_OFS 0x110 -#define GT_PCI1M1REMAP_OFS 0x118 - -#define GT_SCS0LD_OFS 0x400 -#define GT_SCS0HD_OFS 0x404 -#define GT_SCS1LD_OFS 0x408 -#define GT_SCS1HD_OFS 0x40c -#define GT_SCS2LD_OFS 0x410 -#define GT_SCS2HD_OFS 0x414 -#define GT_SCS3LD_OFS 0x418 -#define GT_SCS3HD_OFS 0x41c -#define GT_CS0LD_OFS 0x420 -#define GT_CS0HD_OFS 0x424 -#define GT_CS1LD_OFS 0x428 -#define GT_CS1HD_OFS 0x42c -#define GT_CS2LD_OFS 0x430 -#define GT_CS2HD_OFS 0x434 -#define GT_CS3LD_OFS 0x438 -#define GT_CS3HD_OFS 0x43c -#define GT_BOOTLD_OFS 0x440 -#define GT_BOOTHD_OFS 0x444 - -#define GT_SDRAM_B0_OFS 0x44c -#define GT_SDRAM_CFG_OFS 0x448 -#define GT_SDRAM_B2_OFS 0x454 -#define GT_SDRAM_OPMODE_OFS 0x474 -#define GT_SDRAM_BM_OFS 0x478 -#define GT_SDRAM_ADDRDECODE_OFS 0x47c - -#define GT_PCI0_CMD_OFS 0xc00 /* GT64120A only */ -#define GT_PCI0_TOR_OFS 0xc04 -#define GT_PCI0_BS_SCS10_OFS 0xc08 -#define GT_PCI0_BS_SCS32_OFS 0xc0c -#define GT_INTRCAUSE_OFS 0xc18 -#define GT_INTRMASK_OFS 0xc1c /* GT64120A only */ -#define GT_PCI0_IACK_OFS 0xc34 -#define GT_PCI0_BARE_OFS 0xc3c -#define GT_HINTRCAUSE_OFS 0xc98 /* GT64120A only */ -#define GT_HINTRMASK_OFS 0xc9c /* GT64120A only */ -#define GT_PCI1_CFGADDR_OFS 0xcf0 /* GT64120A only */ -#define GT_PCI1_CFGDATA_OFS 0xcf4 /* GT64120A only */ -#define GT_PCI0_CFGADDR_OFS 0xcf8 -#define GT_PCI0_CFGDATA_OFS 0xcfc - - -/* - * Timer/Counter. GT64120A only. - */ -#define GT_TC0_OFS 0x850 -#define GT_TC1_OFS 0x854 -#define GT_TC2_OFS 0x858 -#define GT_TC3_OFS 0x85C -#define GT_TC_CONTROL_OFS 0x864 - -/* - * I2O Support Registers - */ -#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 -#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 -#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 -#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c -#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 -#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 -#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c - -#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 -#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c -#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 -#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 -#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c - -/* - * Register encodings - */ -#define GT_CPU_ENDIAN_SHF 12 -#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) -#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK -#define GT_CPU_WR_SHF 16 -#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) -#define GT_CPU_WR_BIT GT_CPU_WR_MSK -#define GT_CPU_WR_DXDXDXDX 0 -#define GT_CPU_WR_DDDD 1 - - -#define GT_CFGADDR_CFGEN_SHF 31 -#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) -#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK - -#define GT_CFGADDR_BUSNUM_SHF 16 -#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) - -#define GT_CFGADDR_DEVNUM_SHF 11 -#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) - -#define GT_CFGADDR_FUNCNUM_SHF 8 -#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) - -#define GT_CFGADDR_REGNUM_SHF 2 -#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) - - -#define GT_SDRAM_BM_ORDER_SHF 2 -#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) -#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK -#define GT_SDRAM_BM_ORDER_SUB 1 -#define GT_SDRAM_BM_ORDER_LIN 0 - -#define GT_SDRAM_BM_RSVD_ALL1 0xffb - - -#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 -#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) -#define GT_SDRAM_ADDRDECODE_ADDR_0 0 -#define GT_SDRAM_ADDRDECODE_ADDR_1 1 -#define GT_SDRAM_ADDRDECODE_ADDR_2 2 -#define GT_SDRAM_ADDRDECODE_ADDR_3 3 -#define GT_SDRAM_ADDRDECODE_ADDR_4 4 -#define GT_SDRAM_ADDRDECODE_ADDR_5 5 -#define GT_SDRAM_ADDRDECODE_ADDR_6 6 -#define GT_SDRAM_ADDRDECODE_ADDR_7 7 - - -#define GT_SDRAM_B0_CASLAT_SHF 0 -#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) -#define GT_SDRAM_B0_CASLAT_2 1 -#define GT_SDRAM_B0_CASLAT_3 2 - -#define GT_SDRAM_B0_FTDIS_SHF 2 -#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) -#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK - -#define GT_SDRAM_B0_SRASPRCHG_SHF 3 -#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) -#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK -#define GT_SDRAM_B0_SRASPRCHG_2 0 -#define GT_SDRAM_B0_SRASPRCHG_3 1 - -#define GT_SDRAM_B0_B0COMPAB_SHF 4 -#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) -#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK - -#define GT_SDRAM_B0_64BITINT_SHF 5 -#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) -#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK -#define GT_SDRAM_B0_64BITINT_2 0 -#define GT_SDRAM_B0_64BITINT_4 1 - -#define GT_SDRAM_B0_BW_SHF 6 -#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) -#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK -#define GT_SDRAM_B0_BW_32 0 -#define GT_SDRAM_B0_BW_64 1 - -#define GT_SDRAM_B0_BLODD_SHF 7 -#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) -#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK - -#define GT_SDRAM_B0_PAR_SHF 8 -#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) -#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK - -#define GT_SDRAM_B0_BYPASS_SHF 9 -#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) -#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK - -#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 -#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) -#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK -#define GT_SDRAM_B0_SRAS2SCAS_2 0 -#define GT_SDRAM_B0_SRAS2SCAS_3 1 - -#define GT_SDRAM_B0_SIZE_SHF 11 -#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) -#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK -#define GT_SDRAM_B0_SIZE_16M 0 -#define GT_SDRAM_B0_SIZE_64M 1 - -#define GT_SDRAM_B0_EXTPAR_SHF 12 -#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) -#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK - -#define GT_SDRAM_B0_BLEN_SHF 13 -#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) -#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK -#define GT_SDRAM_B0_BLEN_8 0 -#define GT_SDRAM_B0_BLEN_4 1 - - -#define GT_SDRAM_CFG_REFINT_SHF 0 -#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) - -#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 -#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) -#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK - -#define GT_SDRAM_CFG_RMW_SHF 15 -#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) -#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK - -#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 -#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) -#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK - -#define GT_SDRAM_CFG_DUPCNTL_SHF 19 -#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) -#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK - -#define GT_SDRAM_CFG_DUPBA_SHF 20 -#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) -#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK - -#define GT_SDRAM_CFG_DUPEOT0_SHF 21 -#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) -#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK - -#define GT_SDRAM_CFG_DUPEOT1_SHF 22 -#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) -#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK - -#define GT_SDRAM_OPMODE_OP_SHF 0 -#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) -#define GT_SDRAM_OPMODE_OP_NORMAL 0 -#define GT_SDRAM_OPMODE_OP_NOP 1 -#define GT_SDRAM_OPMODE_OP_PRCHG 2 -#define GT_SDRAM_OPMODE_OP_MODE 3 -#define GT_SDRAM_OPMODE_OP_CBR 4 - - -#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 -#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) -#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK - -#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 -#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) -#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK - -#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 -#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) -#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK - -#define GT_PCI0_BARE_INTIODIS_SHF 3 -#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) -#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK - -#define GT_PCI0_BARE_INTMEMDIS_SHF 4 -#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) -#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK - -#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 -#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) -#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK - -#define GT_PCI0_BARE_CS20DIS_SHF 6 -#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) -#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK - -#define GT_PCI0_BARE_SCS32DIS_SHF 7 -#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) -#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK - -#define GT_PCI0_BARE_SCS10DIS_SHF 8 -#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) -#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK - - -#define GT_INTRCAUSE_MASABORT0_SHF 18 -#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) -#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK - -#define GT_INTRCAUSE_TARABORT0_SHF 19 -#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) -#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK - - -#define GT_PCI0_CFGADDR_REGNUM_SHF 2 -#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) -#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 -#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) -#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 -#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) -#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 -#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 -#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK - -#define GT_PCI0_CMD_MBYTESWAP_SHF 0 -#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) -#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK -#define GT_PCI0_CMD_MWORDSWAP_SHF 10 -#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) -#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK -#define GT_PCI0_CMD_SBYTESWAP_SHF 16 -#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) -#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK -#define GT_PCI0_CMD_SWORDSWAP_SHF 11 -#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) -#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK - -/* - * Misc - */ -#define GT_DEF_BASE 0x14000000 -#define GT_DEF_PCI0_MEM0_BASE 0x12000000 -#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ -#define GT_LATTIM_MIN 6 /* Minimum lat */ - -#endif /* _ASM_GT64120_H */ diff --git a/include/asm-mips64/hardirq.h b/include/asm-mips64/hardirq.h deleted file mode 100644 index b6fa5ddc8ff..00000000000 --- a/include/asm-mips64/hardirq.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1998, 1999, 2000, 2001 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef _ASM_HARDIRQ_H -#define _ASM_HARDIRQ_H - -#include -#include -#include - -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include /* Standard mappings for irq_cpustat_t above */ - -/* - * We put the hardirq and softirq counter into the preemption - * counter. The bitmask has the following meaning: - * - * - bits 0-7 are the preemption count (max preemption depth: 256) - * - bits 8-15 are the softirq count (max # of softirqs: 256) - * - bits 16-23 are the hardirq count (max # of hardirqs: 256) - * - * - ( bit 26 is the PREEMPT_ACTIVE flag. ) - * - * PREEMPT_MASK: 0x000000ff - * SOFTIRQ_MASK: 0x0000ff00 - * HARDIRQ_MASK: 0x00ff0000 - */ - -#define PREEMPT_BITS 8 -#define SOFTIRQ_BITS 8 -#define HARDIRQ_BITS 8 - -#define PREEMPT_SHIFT 0 -#define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS) -#define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS) - -#define __MASK(x) ((1UL << (x))-1) - -#define PREEMPT_MASK (__MASK(PREEMPT_BITS) << PREEMPT_SHIFT) -#define HARDIRQ_MASK (__MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT) -#define SOFTIRQ_MASK (__MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT) - -#define hardirq_count() (preempt_count() & HARDIRQ_MASK) -#define softirq_count() (preempt_count() & SOFTIRQ_MASK) -#define irq_count() (preempt_count() & (HARDIRQ_MASK | SOFTIRQ_MASK)) - -#define PREEMPT_OFFSET (1UL << PREEMPT_SHIFT) -#define SOFTIRQ_OFFSET (1UL << SOFTIRQ_SHIFT) -#define HARDIRQ_OFFSET (1UL << HARDIRQ_SHIFT) - -/* - * The hardirq mask has to be large enough to have - * space for potentially all IRQ sources in the system - * nesting on a single CPU: - */ -#if (1 << HARDIRQ_BITS) < NR_IRQS -# error HARDIRQ_BITS is too low! -#endif - -/* - * Are we doing bottom half or hardware interrupt processing? - * Are we in a softirq context? Interrupt context? - */ -#define in_irq() (hardirq_count()) -#define in_softirq() (softirq_count()) -#define in_interrupt() (irq_count()) - -#define hardirq_trylock() (!in_interrupt()) -#define hardirq_endlock() do { } while (0) - -#define irq_enter() (preempt_count() += HARDIRQ_OFFSET) - -#if CONFIG_PREEMPT -# define in_atomic() (preempt_count() != kernel_locked()) -# define IRQ_EXIT_OFFSET (HARDIRQ_OFFSET-1) -#else -# define in_atomic() (preempt_count() != 0) -# define IRQ_EXIT_OFFSET HARDIRQ_OFFSET -#endif -#define irq_exit() \ -do { \ - preempt_count() -= IRQ_EXIT_OFFSET; \ - if (!in_interrupt() && softirq_pending(smp_processor_id())) \ - do_softirq(); \ - preempt_enable_no_resched(); \ -} while (0) - -#ifndef CONFIG_SMP -# define synchronize_irq(irq) barrier() -#else - extern void synchronize_irq(unsigned int irq); -#endif /* CONFIG_SMP */ - -#endif /* _ASM_HARDIRQ_H */ diff --git a/include/asm-mips64/hdreg.h b/include/asm-mips64/hdreg.h deleted file mode 100644 index ed8c0d4a500..00000000000 --- a/include/asm-mips64/hdreg.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This file contains the MIPS architecture specific IDE code. - * - * Copyright (C) 1994-1996 Linus Torvalds & authors - * Copyright (C) 2001 Ralf Baechle - */ - -#ifndef _ASM_HDREG_H -#define _ASM_HDREG_H - -typedef unsigned long ide_ioreg_t; - -#endif /* _ASM_HDREG_H */ - diff --git a/include/asm-mips64/hw_irq.h b/include/asm-mips64/hw_irq.h deleted file mode 100644 index 6996095113d..00000000000 --- a/include/asm-mips64/hw_irq.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000, 2001, 2002 by Ralf Baechle - */ -#ifndef __ASM_HW_IRQ_H -#define __ASM_HW_IRQ_H - -#include -#include - -extern void mask_irq(unsigned int irq); -extern void unmask_irq(unsigned int irq); -extern void disable_8259A_irq(unsigned int irq); -extern void enable_8259A_irq(unsigned int irq); -extern int i8259A_irq_pending(unsigned int irq); -extern void make_8259A_irq(unsigned int irq); -extern void init_8259A(int aeoi); - -#include - -extern atomic_t irq_err_count; - -/* This may not be apropriate for all machines, we'll see ... */ -static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) -{ -} - -#endif /* __ASM_HW_IRQ_H */ diff --git a/include/asm-mips64/i8259.h b/include/asm-mips64/i8259.h deleted file mode 100644 index a1126e14e6a..00000000000 --- a/include/asm-mips64/i8259.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * include/asm-mips/i8259.h - * - * i8259A interrupt definitions. - * - * Copyright (C) 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS64_I8259_H -#define __ASM_MIPS64_I8259_H - -#include - -#include -#include - -extern void init_i8259_irqs(void); - -#endif /* __ASM_MIPS64_I8259_H */ diff --git a/include/asm-mips64/ide.h b/include/asm-mips64/ide.h deleted file mode 100644 index f377adcfb1a..00000000000 --- a/include/asm-mips64/ide.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This file contains the MIPS architecture specific IDE code. - * - * Copyright (C) 1994-1996 Linus Torvalds & authors - */ - -#ifndef __ASM_IDE_H -#define __ASM_IDE_H - -#ifdef __KERNEL__ - -#include -#include -#include - -#ifndef MAX_HWIFS -# ifdef CONFIG_PCI -#define MAX_HWIFS 10 -# else -#define MAX_HWIFS 6 -# endif -#endif - -struct ide_ops { - int (*ide_default_irq)(ide_ioreg_t base); - ide_ioreg_t (*ide_default_io_base)(int index); - void (*ide_init_hwif_ports)(hw_regs_t *hw, ide_ioreg_t data_port, - ide_ioreg_t ctrl_port, int *irq); -}; - -extern struct ide_ops *ide_ops; - -static __inline__ int ide_default_irq(ide_ioreg_t base) -{ - return ide_ops->ide_default_irq(base); -} - -static __inline__ ide_ioreg_t ide_default_io_base(int index) -{ - return ide_ops->ide_default_io_base(index); -} - -static inline void ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, - ide_ioreg_t ctrl_port, int *irq) -{ - ide_ops->ide_init_hwif_ports(hw, data_port, ctrl_port, irq); -} - -static __inline__ void ide_init_default_hwifs(void) -{ -#ifndef CONFIG_PCI - hw_regs_t hw; - int index; - - for(index = 0; index < MAX_HWIFS; index++) { - ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL); - hw.irq = ide_default_irq(ide_default_io_base(index)); - ide_register_hw(&hw, NULL); - } -#endif -} - -#define __ide_mm_insw ide_insw -#define __ide_mm_insl ide_insl -#define __ide_mm_outsw ide_outsw -#define __ide_mm_outsl ide_outsl - -#endif /* __KERNEL__ */ - -#endif /* __ASM_IDE_H */ diff --git a/include/asm-mips64/init.h b/include/asm-mips64/init.h deleted file mode 100644 index 17d21557418..00000000000 --- a/include/asm-mips64/init.h +++ /dev/null @@ -1 +0,0 @@ -#error " should never be used - use instead" diff --git a/include/asm-mips64/inst.h b/include/asm-mips64/inst.h deleted file mode 100644 index 6ad51724176..00000000000 --- a/include/asm-mips64/inst.h +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Format of an instruction in memory. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 2000 by Ralf Baechle - */ -#ifndef _ASM_INST_H -#define _ASM_INST_H - -/* - * Major opcodes; before MIPS IV cop1x was called cop3. - */ -enum major_op { - spec_op, bcond_op, j_op, jal_op, - beq_op, bne_op, blez_op, bgtz_op, - addi_op, addiu_op, slti_op, sltiu_op, - andi_op, ori_op, xori_op, lui_op, - cop0_op, cop1_op, cop2_op, cop1x_op, - beql_op, bnel_op, blezl_op, bgtzl_op, - daddi_op, daddiu_op, ldl_op, ldr_op, - major_1c_op, jalx_op, major_1e_op, major_1f_op, - lb_op, lh_op, lwl_op, lw_op, - lbu_op, lhu_op, lwr_op, lwu_op, - sb_op, sh_op, swl_op, sw_op, - sdl_op, sdr_op, swr_op, cache_op, - ll_op, lwc1_op, lwc2_op, pref_op, - lld_op, ldc1_op, ldc2_op, ld_op, - sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */ - scd_op, sdc1_op, sdc2_op, sd_op -}; - -/* - * func field of spec opcode. - */ -enum spec_op { - sll_op, movc_op, srl_op, sra_op, - sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */ - jr_op, jalr_op, movz_op, movn_op, - syscall_op, break_op, spim_op, sync_op, - mfhi_op, mthi_op, mflo_op, mtlo_op, - dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, - mult_op, multu_op, div_op, divu_op, - dmult_op, dmultu_op, ddiv_op, ddivu_op, - add_op, addu_op, sub_op, subu_op, - and_op, or_op, xor_op, nor_op, - spec3_unused_op, spec4_unused_op, slt_op, sltu_op, - dadd_op, daddu_op, dsub_op, dsubu_op, - tge_op, tgeu_op, tlt_op, tltu_op, - teq_op, spec5_unused_op, tne_op, spec6_unused_op, - dsll_op, spec7_unused_op, dsrl_op, dsra_op, - dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op -}; - -/* - * rt field of bcond opcodes. - */ -enum rt_op { - bltz_op, bgez_op, bltzl_op, bgezl_op, - spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, - tgei_op, tgeiu_op, tlti_op, tltiu_op, - teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, - bltzal_op, bgezal_op, bltzall_op, bgezall_op - /* - * The others (0x14 - 0x1f) are unused. - */ -}; - -/* - * rs field of cop opcodes. - */ -enum cop_op { - mfc_op = 0x00, dmfc_op = 0x01, - cfc_op = 0x02, mtc_op = 0x04, - dmtc_op = 0x05, ctc_op = 0x06, - bc_op = 0x08, cop_op = 0x10, - copm_op = 0x18 -}; - -/* - * rt field of cop.bc_op opcodes - */ -enum bcop_op { - bcf_op, bct_op, bcfl_op, bctl_op -}; - -/* - * func field of cop0 coi opcodes. - */ -enum cop0_coi_func { - tlbr_op = 0x01, tlbwi_op = 0x02, - tlbwr_op = 0x06, tlbp_op = 0x08, - rfe_op = 0x10, eret_op = 0x18 -}; - -/* - * func field of cop0 com opcodes. - */ -enum cop0_com_func { - tlbr1_op = 0x01, tlbw_op = 0x02, - tlbp1_op = 0x08, dctr_op = 0x09, - dctw_op = 0x0a -}; - -/* - * fmt field of cop1 opcodes. - */ -enum cop1_fmt { - s_fmt, d_fmt, e_fmt, q_fmt, - w_fmt, l_fmt -}; - -/* - * func field of cop1 instructions using d, s or w format. - */ -enum cop1_sdw_func { - fadd_op = 0x00, fsub_op = 0x01, - fmul_op = 0x02, fdiv_op = 0x03, - fsqrt_op = 0x04, fabs_op = 0x05, - fmov_op = 0x06, fneg_op = 0x07, - froundl_op = 0x08, ftruncl_op = 0x09, - fceill_op = 0x0a, ffloorl_op = 0x0b, - fround_op = 0x0c, ftrunc_op = 0x0d, - fceil_op = 0x0e, ffloor_op = 0x0f, - fmovc_op = 0x11, fmovz_op = 0x12, - fmovn_op = 0x13, frecip_op = 0x15, - frsqrt_op = 0x16, fcvts_op = 0x20, - fcvtd_op = 0x21, fcvte_op = 0x22, - fcvtw_op = 0x24, fcvtl_op = 0x25, - fcmp_op = 0x30 -}; - -/* - * func field of cop1x opcodes (MIPS IV). - */ -enum cop1x_func { - lwxc1_op = 0x00, ldxc1_op = 0x01, - pfetch_op = 0x07, swxc1_op = 0x08, - sdxc1_op = 0x09, madd_s_op = 0x20, - madd_d_op = 0x21, madd_e_op = 0x22, - msub_s_op = 0x28, msub_d_op = 0x29, - msub_e_op = 0x2a, nmadd_s_op = 0x30, - nmadd_d_op = 0x31, nmadd_e_op = 0x32, - nmsub_s_op = 0x38, nmsub_d_op = 0x39, - nmsub_e_op = 0x3a -}; - -/* - * func field for mad opcodes (MIPS IV). - */ -enum mad_func { - madd_op = 0x08, msub_op = 0x0a, - nmadd_op = 0x0c, nmsub_op = 0x0e -}; - -/* - * Damn ... bitfields depend from byteorder :-( - */ -#ifdef __MIPSEB__ -struct j_format { /* Jump format */ - unsigned int opcode : 6; - unsigned int target : 26; -}; - -struct i_format { /* Immediate format (addi, lw, ...) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - signed int simmediate : 16; -}; - -struct u_format { /* Unsigned immediate format (ori, xori, ...) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int uimmediate : 16; -}; - -struct c_format { /* Cache (>= R6000) format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int c_op : 3; - unsigned int cache : 2; - unsigned int simmediate : 16; -}; - -struct r_format { /* Register format */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct p_format { /* Performance counter format (R10000) */ - unsigned int opcode : 6; - unsigned int rs : 5; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct f_format { /* FPU register format */ - unsigned int opcode : 6; - unsigned int : 1; - unsigned int fmt : 4; - unsigned int rt : 5; - unsigned int rd : 5; - unsigned int re : 5; - unsigned int func : 6; -}; - -struct ma_format { /* FPU multipy and add format (MIPS IV) */ - unsigned int opcode : 6; - unsigned int fr : 5; - unsigned int ft : 5; - unsigned int fs : 5; - unsigned int fd : 5; - unsigned int func : 4; - unsigned int fmt : 2; -}; - -#elif defined(__MIPSEL__) - -struct j_format { /* Jump format */ - unsigned int target : 26; - unsigned int opcode : 6; -}; - -struct i_format { /* Immediate format */ - signed int simmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct u_format { /* Unsigned immediate format */ - unsigned int uimmediate : 16; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct c_format { /* Cache (>= R6000) format */ - unsigned int simmediate : 16; - unsigned int cache : 2; - unsigned int c_op : 3; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct r_format { /* Register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct p_format { /* Performance counter format (R10000) */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int rs : 5; - unsigned int opcode : 6; -}; - -struct f_format { /* FPU register format */ - unsigned int func : 6; - unsigned int re : 5; - unsigned int rd : 5; - unsigned int rt : 5; - unsigned int fmt : 4; - unsigned int : 1; - unsigned int opcode : 6; -}; - -struct ma_format { /* FPU multipy and add format (MIPS IV) */ - unsigned int fmt : 2; - unsigned int func : 4; - unsigned int fd : 5; - unsigned int fs : 5; - unsigned int ft : 5; - unsigned int fr : 5; - unsigned int opcode : 6; -}; - -#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ -#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" -#endif - -union mips_instruction { - unsigned int word; - unsigned short halfword[2]; - unsigned char byte[4]; - struct j_format j_format; - struct i_format i_format; - struct u_format u_format; - struct c_format c_format; - struct r_format r_format; - struct f_format f_format; - struct ma_format ma_format; -}; - -/* HACHACHAHCAHC ... */ - -/* In case some other massaging is needed, keep MIPSInst as wrapper */ - -#define MIPSInst(x) x - -#define I_OPCODE_SFT 26 -#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT) - -#define I_JTARGET_SFT 0 -#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff) - -#define I_RS_SFT 21 -#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT) - -#define I_RT_SFT 16 -#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT) - -#define I_IMM_SFT 0 -#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff))) -#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff) - -#define I_CACHEOP_SFT 18 -#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT) - -#define I_CACHESEL_SFT 16 -#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT) - -#define I_RD_SFT 11 -#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT) - -#define I_RE_SFT 6 -#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT) - -#define I_FUNC_SFT 0 -#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f) - -#define I_FFMT_SFT 21 -#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT) - -#define I_FT_SFT 16 -#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT) - -#define I_FS_SFT 11 -#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT) - -#define I_FD_SFT 6 -#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT) - -#define I_FR_SFT 21 -#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT) - -#define I_FMA_FUNC_SFT 2 -#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT) - -#define I_FMA_FFMT_SFT 0 -#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003) - -typedef unsigned int mips_instruction; - -#endif /* _ASM_INST_H */ diff --git a/include/asm-mips64/io.h b/include/asm-mips64/io.h deleted file mode 100644 index d8975250633..00000000000 --- a/include/asm-mips64/io.h +++ /dev/null @@ -1,515 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995 Waldorf GmbH - * Copyright (C) 1994 - 2000 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_IO_H -#define _ASM_IO_H - -#include -#include -#include -#include - -#ifdef CONFIG_DECSTATION -#include -#endif - -#ifdef CONFIG_MIPS_ATLAS -#include -#endif - -#ifdef CONFIG_MIPS_MALTA -#include -#endif - -#ifdef CONFIG_MIPS_SEAD -#include -#endif - -#ifdef CONFIG_SGI_IP22 -#include -#endif - -#ifdef CONFIG_SGI_IP27 -#include -#endif - -#ifdef CONFIG_SGI_IP32 -#include -#endif - -#ifdef CONFIG_SIBYTE_SB1xxx_SOC -#include -#endif - -#ifdef CONFIG_SNI_RM200_PCI -#include -#endif - -#ifdef CONFIG_SGI_IP27 -extern unsigned long bus_to_baddr[256]; - -#define bus_to_baddr(bus, addr) (bus_to_baddr[(bus)->number] + (addr)) -#define baddr_to_bus(bus, addr) ((addr) - bus_to_baddr[(bus)->number]) -#else -#define bus_to_baddr(bus, addr) (addr) -#define baddr_to_bus(bus, addr) (addr) -#endif - -/* - * Slowdown I/O port space accesses for antique hardware. - */ -#undef CONF_SLOWDOWN_IO - -/* - * Sane hardware offers swapping of I/O space accesses in hardware; less - * sane hardware forces software to fiddle with this ... - */ -#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__) - -#define __ioswab8(x) (x) - -#ifdef CONFIG_SGI_IP22 -/* - * IP22 seems braindead enough to swap 16bits values in hardware, but - * not 32bits. Go figure... Can't tell without documentation. - */ -#define __ioswab16(x) (x) -#else -#define __ioswab16(x) swab16(x) -#endif -#define __ioswab32(x) swab32(x) -#define __ioswab64(x) swab64(x) - -#else - -#define __ioswab8(x) (x) -#define __ioswab16(x) (x) -#define __ioswab32(x) (x) -#define __ioswab64(x) (x) - -#endif - -/* - * Change "struct page" to physical address. - */ -#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) - -/* - * ioremap - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map - * - * ioremap performs a platform specific sequence of operations to - * make bus memory CPU accessible via the readb/readw/readl/writeb/ - * writew/writel functions and the other mmio helpers. The returned - * address is not guaranteed to be usable directly as a virtual - * address. - */ -static inline void * ioremap(unsigned long offset, unsigned long size) -{ - return (void *) (IO_SPACE_BASE | offset); -} - -/* - * ioremap_nocache - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map - * - * ioremap_nocache performs a platform specific sequence of operations to - * make bus memory CPU accessible via the readb/readw/readl/writeb/ - * writew/writel functions and the other mmio helpers. The returned - * address is not guaranteed to be usable directly as a virtual - * address. - * - * This version of ioremap ensures that the memory is marked uncachable - * on the CPU as well as honouring existing caching rules from things like - * the PCI bus. Note that there are other caches and buffers on many - * busses. In paticular driver authors should read up on PCI writes - * - * It's useful if some control registers are in such an area and - * write combining or read caching is not desirable: - */ -static inline void * ioremap_nocache (unsigned long offset, unsigned long size) -{ - return (void *) (IO_SPACE_BASE | offset); -} - -static inline void iounmap(void *addr) -{ -} - -#define readb(addr) (*(volatile unsigned char *)(addr)) -#define readw(addr) __ioswab16((*(volatile unsigned short *)(addr))) -#define readl(addr) __ioswab32((*(volatile unsigned int *)(addr))) -#define readq(addr) __ioswab64((*(volatile unsigned long *)(addr))) - -#define __raw_readb(addr) (*(volatile unsigned char *)(addr)) -#define __raw_readw(addr) (*(volatile unsigned short *)(addr)) -#define __raw_readl(addr) (*(volatile unsigned int *)(addr)) -#define ____raw_readq(addr) (*(volatile unsigned long *)(addr)) -#define __raw_readq(addr) (____raw_readq(addr)) - -#define writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (__ioswab8(b))) -#define writew(b,addr) ((*(volatile unsigned short *)(addr)) = (__ioswab16(b))) -#define writel(b,addr) ((*(volatile unsigned int *)(addr)) = (__ioswab32(b))) -#define writeq(b,addr) ((*(volatile unsigned long *)(addr)) = (__ioswab64(b))) - -#define __raw_writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (b)) -#define __raw_writew(w,addr) ((*(volatile unsigned short *)(addr)) = (w)) -#define __raw_writel(l,addr) ((*(volatile unsigned int *)(addr)) = (l)) -#define ____raw_writeq(q,addr) ((*(volatile unsigned long *)(addr)) = (q)) -#define __raw_writeq(q,addr) (____raw_writeq((q),(addr))) - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -/* The ISA versions are supplied by system specific code */ - -/* - * On MIPS I/O ports are memory mapped, so we access them using normal - * load/store instructions. mips_io_port_base is the virtual address to - * which all ports are being mapped. For sake of efficiency some code - * assumes that this is an address that can be loaded with a single lui - * instruction, so the lower 16 bits must be zero. Should be true on - * on any sane architecture; generic code does not use this assumption. - */ -extern const unsigned long mips_io_port_base; - -#define set_io_port_base(base) \ - do { * (unsigned long *) &mips_io_port_base = (base); } while (0) - -#define __SLOW_DOWN_IO \ - __asm__ __volatile__( \ - "sb\t$0,0x80(%0)" \ - : : "r" (mips_io_port_base)); - -#ifdef CONF_SLOWDOWN_IO -#ifdef REALLY_SLOW_IO -#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } -#else -#define SLOW_DOWN_IO __SLOW_DOWN_IO -#endif -#else -#define SLOW_DOWN_IO -#endif - -/* - * virt_to_phys - map virtual addresses to physical - * @address: address to remap - * - * The returned physical address is the physical (CPU) mapping for - * the memory address given. It is only valid to use this function on - * addresses directly mapped or allocated via kmalloc. - * - * This function does not give bus mappings for DMA transfers. In - * almost all conceivable cases a device driver should not be using - * this function - */ -static inline unsigned long virt_to_phys(volatile void * address) -{ - return (unsigned long)address - PAGE_OFFSET; -} - -/* - * phys_to_virt - map physical address to virtual - * @address: address to remap - * - * The returned virtual address is a current CPU mapping for - * the memory address given. It is only valid to use this function on - * addresses that have a kernel mapping - * - * This function does not handle bus mappings for DMA transfers. In - * almost all conceivable cases a device driver should not be using - * this function - */ -static inline void * phys_to_virt(unsigned long address) -{ - return (void *)(address + PAGE_OFFSET); -} - -/* - * ISA I/O bus memory addresses are 1:1 with the physical address. - */ -static inline unsigned long isa_virt_to_bus(volatile void * address) -{ - return PHYSADDR(address); -} - -static inline void * isa_bus_to_virt(unsigned long address) -{ - return (void *)KSEG0ADDR(address); -} - -/* - * However PCI ones are not necessarily 1:1 and therefore these interfaces - * are forbidden in portable PCI drivers. - * - * Allow them for x86 for legacy drivers, though. - */ -#define virt_to_bus virt_to_phys -#define bus_to_virt phys_to_virt - -/* This is too simpleminded for more sophisticated than dumb hardware ... */ -#define page_to_bus page_to_phys - -/* - * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. This implies the assumption that there is only - * one of these busses. - */ -extern unsigned long isa_slot_offset; - -/* - * ISA space is 'always mapped' on currently supported MIPS systems, no need - * to explicitly ioremap() it. The fact that the ISA IO space is mapped - * to PAGE_OFFSET is pure coincidence - it does not mean ISA values - * are physical addresses. The following constant pointer can be - * used as the IO-area pointer (it can be iounmapped as well, so the - * analogy with PCI is quite large): - */ -#define __ISA_IO_base ((char *)(isa_slot_offset)) - -#define isa_readb(a) readb(__ISA_IO_base + (a)) -#define isa_readw(a) readw(__ISA_IO_base + (a)) -#define isa_readl(a) readl(__ISA_IO_base + (a)) -#define isa_readq(a) readq(__ISA_IO_base + (a)) -#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a)) -#define isa_writew(w,a) writew(w,__ISA_IO_base + (a)) -#define isa_writel(l,a) writel(l,__ISA_IO_base + (a)) -#define isa_writeq(q,a) writeq(q,__ISA_IO_base + (a)) -#define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c)) -#define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c)) - -/* - * We don't have csum_partial_copy_fromio() yet, so we cheat here and - * just copy it. The net code will then do the checksum later. - */ -#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len)) - -/** - * check_signature - find BIOS signatures - * @io_addr: mmio address to check - * @signature: signature block - * @length: length of signature - * - * Perform a signature comparison with the mmio address io_addr. This - * address should have been obtained by ioremap. - * Returns 1 on a match. - */ -static inline int check_signature(unsigned long io_addr, - const unsigned char *signature, int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -/* - * isa_check_signature - find BIOS signatures - * @io_addr: mmio address to check - * @signature: signature block - * @length: length of signature - * - * Perform a signature comparison with the ISA mmio address io_addr. - * Returns 1 on a match. - * - * This function is deprecated. New drivers should use ioremap and - * check_signature. - */ -#define isa_check_signature(io, s, l) check_signature(i,s,l) - -#define outb(val,port) \ -do { \ - *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \ -} while(0) - -#define outw(val,port) \ -do { \ - *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\ -} while(0) - -#define outl(val,port) \ -do { \ - *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\ -} while(0) - -#define outb_p(val,port) \ -do { \ - *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \ - SLOW_DOWN_IO; \ -} while(0) - -#define outw_p(val,port) \ -do { \ - *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\ - SLOW_DOWN_IO; \ -} while(0) - -#define outl_p(val,port) \ -do { \ - *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\ - SLOW_DOWN_IO; \ -} while(0) - -static inline unsigned char inb(unsigned long port) -{ - return __ioswab8(*(volatile u8 *)(mips_io_port_base + port)); -} - -static inline unsigned short inw(unsigned long port) -{ - return __ioswab16(*(volatile u16 *)(mips_io_port_base + port)); -} - -static inline unsigned int inl(unsigned long port) -{ - return __ioswab32(*(volatile u32 *)(mips_io_port_base + port)); -} - -static inline unsigned char inb_p(unsigned long port) -{ - u8 __val; - - __val = *(volatile u8 *)(mips_io_port_base + port); - SLOW_DOWN_IO; - - return __ioswab8(__val); -} - -static inline unsigned short inw_p(unsigned long port) -{ - u16 __val; - - __val = *(volatile u16 *)(mips_io_port_base + port); - SLOW_DOWN_IO; - - return __ioswab16(__val); -} - -static inline unsigned int inl_p(unsigned long port) -{ - u32 __val; - - __val = *(volatile u32 *)(mips_io_port_base + port); - SLOW_DOWN_IO; - return __ioswab32(__val); -} - -static inline void outsb(unsigned long port, void *addr, unsigned int count) -{ - while (count--) { - outb(*(u8 *)addr, port); - addr++; - } -} - -static inline void insb(unsigned long port, void *addr, unsigned int count) -{ - while (count--) { - *(u8 *)addr = inb(port); - addr++; - } -} - -static inline void outsw(unsigned long port, void *addr, unsigned int count) -{ - while (count--) { - outw(*(u16 *)addr, port); - addr += 2; - } -} - -static inline void insw(unsigned long port, void *addr, unsigned int count) -{ - while (count--) { - *(u16 *)addr = inw(port); - addr += 2; - } -} - -static inline void outsl(unsigned long port, void *addr, unsigned int count) -{ - while (count--) { - outl(*(u32 *)addr, port); - addr += 4; - } -} - -static inline void insl(unsigned long port, void *addr, unsigned int count) -{ - while (count--) { - *(u32 *)addr = inl(port); - addr += 4; - } -} - -/* - * The caches on some architectures aren't dma-coherent and have need to - * handle this in software. There are three types of operations that - * can be applied to dma buffers. - * - * - dma_cache_wback_inv(start, size) makes caches and coherent by - * writing the content of the caches back to memory, if necessary. - * The function also invalidates the affected part of the caches as - * necessary before DMA transfers from outside to memory. - * - dma_cache_wback(start, size) makes caches and coherent by - * writing the content of the caches back to memory, if necessary. - * The function also invalidates the affected part of the caches as - * necessary before DMA transfers from outside to memory. - * - dma_cache_inv(start, size) invalidates the affected parts of the - * caches. Dirty lines of the caches may be written back or simply - * be discarded. This operation is necessary before dma operations - * to the memory. - */ -#ifdef CONFIG_NONCOHERENT_IO - -extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); -extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); -extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); - -#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size) -#define dma_cache_wback(start,size) _dma_cache_wback(start,size) -#define dma_cache_inv(start,size) _dma_cache_inv(start,size) - -#else /* Sane hardware */ - -#define dma_cache_wback_inv(start,size) \ - do { (void) (start); (void) (size); } while (0) -#define dma_cache_wback(start,size) \ - do { (void) (start); (void) (size); } while (0) -#define dma_cache_inv(start,size) \ - do { (void) (start); (void) (size); } while (0) - -#endif /* CONFIG_NONCOHERENT_IO */ - -/* - * Read a 32-bit register that requires a 64-bit read cycle on the bus. - * Avoid interrupt mucking, just adjust the address for 4-byte access. - * Assume the addresses are 8-byte aligned. - */ -#ifdef __MIPSEB__ -#define __CSR_32_ADJUST 4 -#else -#define __CSR_32_ADJUST 0 -#endif - -#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) -#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) - -#endif /* _ASM_IO_H */ diff --git a/include/asm-mips64/ioctl.h b/include/asm-mips64/ioctl.h deleted file mode 100644 index 5b55a75856e..00000000000 --- a/include/asm-mips64/ioctl.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1999, 2001 by Ralf Baechle - */ -#ifndef _ASM_IOCTL_H -#define _ASM_IOCTL_H - -/* - * The original linux ioctl numbering scheme was just a general - * "anything goes" setup, where more or less random numbers were - * assigned. Sorry, I was clueless when I started out on this. - * - * On the alpha, we'll try to clean it up a bit, using a more sane - * ioctl numbering, and also trying to be compatible with OSF/1 in - * the process. I'd like to clean it up for the i386 as well, but - * it's so painful recognizing both the new and the old numbers.. - * - * The same applies for for the MIPS ABI; in fact even the macros - * from Linux/Alpha fit almost perfectly. - */ - -#define _IOC_NRBITS 8 -#define _IOC_TYPEBITS 8 -#define _IOC_SIZEBITS 13 -#define _IOC_DIRBITS 3 - -#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) -#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) -#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) -#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) - -#define _IOC_NRSHIFT 0 -#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) -#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) -#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) - -/* - * We to additionally limit parameters to a maximum 255 bytes. - */ -#define _IOC_SLMASK 0xff - -/* - * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. - * And this turns out useful to catch old ioctl numbers in header - * files for us. - */ -#define _IOC_NONE 1U -#define _IOC_READ 2U -#define _IOC_WRITE 4U - -/* - * The following are included for compatibility - */ -#define _IOC_VOID 0x20000000 -#define _IOC_OUT 0x40000000 -#define _IOC_IN 0x80000000 -#define _IOC_INOUT (IOC_IN|IOC_OUT) - -#define _IOC(dir,type,nr,size) \ - (((dir) << _IOC_DIRSHIFT) | \ - ((type) << _IOC_TYPESHIFT) | \ - ((nr) << _IOC_NRSHIFT) | \ - ((size) << _IOC_SIZESHIFT)) - -/* used to create numbers */ -#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) -#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) -#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) -#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) - -/* used to decode them.. */ -#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) -#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) -#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) -#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) - -/* ...and for the drivers/sound files... */ - -#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) -#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) -#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) -#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) -#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) - -#endif /* _ASM_IOCTL_H */ diff --git a/include/asm-mips64/ioctls.h b/include/asm-mips64/ioctls.h deleted file mode 100644 index 92f6c36aac4..00000000000 --- a/include/asm-mips64/ioctls.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 2001 Ralf Baechle - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef __ASM_IOCTLS_H -#define __ASM_IOCTLS_H - -#include - -#define TCGETA 0x5401 -#define TCSETA 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */ -#define TCSETAW 0x5403 -#define TCSETAF 0x5404 - -#define TCSBRK 0x5405 -#define TCXONC 0x5406 -#define TCFLSH 0x5407 - -#define TCGETS 0x540d -#define TCSETS 0x540e -#define TCSETSW 0x540f -#define TCSETSF 0x5410 - -#define TIOCEXCL 0x740d /* set exclusive use of tty */ -#define TIOCNXCL 0x740e /* reset exclusive use of tty */ -#define TIOCOUTQ 0x7472 /* output queue size */ -#define TIOCSTI 0x5472 /* simulate terminal input */ -#define TIOCMGET 0x741d /* get all modem bits */ -#define TIOCMBIS 0x741b /* bis modem bits */ -#define TIOCMBIC 0x741c /* bic modem bits */ -#define TIOCMSET 0x741a /* set all modem bits */ -#define TIOCPKT 0x5470 /* pty: set/clear packet mode */ -#define TIOCPKT_DATA 0x00 /* data packet */ -#define TIOCPKT_FLUSHREAD 0x01 /* flush packet */ -#define TIOCPKT_FLUSHWRITE 0x02 /* flush packet */ -#define TIOCPKT_STOP 0x04 /* stop output */ -#define TIOCPKT_START 0x08 /* start output */ -#define TIOCPKT_NOSTOP 0x10 /* no more ^S, ^Q */ -#define TIOCPKT_DOSTOP 0x20 /* now do ^S ^Q */ -/* #define TIOCPKT_IOCTL 0x40 state change of pty driver */ -#define TIOCSWINSZ _IOW('t', 103, struct winsize) /* set window size */ -#define TIOCGWINSZ _IOR('t', 104, struct winsize) /* get window size */ -#define TIOCNOTTY 0x5471 /* void tty association */ -#define TIOCSETD 0x7401 -#define TIOCGETD 0x7400 - -#define FIOCLEX 0x6601 -#define FIONCLEX 0x6602 -#define FIOASYNC 0x667d -#define FIONBIO 0x667e -#define FIOQSIZE 0x667f - -#define TIOCGLTC 0x7474 /* get special local chars */ -#define TIOCSLTC 0x7475 /* set special local chars */ -#define TIOCSPGRP _IOW('t', 118, int) /* set pgrp of tty */ -#define TIOCGPGRP _IOR('t', 119, int) /* get pgrp of tty */ -#define TIOCCONS _IOW('t', 120, int) /* become virtual console */ - -#define FIONREAD 0x467f -#define TIOCINQ FIONREAD - -#define TIOCGETP 0x7408 -#define TIOCSETP 0x7409 -#define TIOCSETN 0x740a /* TIOCSETP wo flush */ - -/* #define TIOCSETA _IOW('t', 20, struct termios) set termios struct */ -/* #define TIOCSETAW _IOW('t', 21, struct termios) drain output, set */ -/* #define TIOCSETAF _IOW('t', 22, struct termios) drn out, fls in, set */ -/* #define TIOCGETD _IOR('t', 26, int) get line discipline */ -/* #define TIOCSETD _IOW('t', 27, int) set line discipline */ - /* 127-124 compat */ - -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x7416 /* Return the session ID of FD */ -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ - -/* I hope the range from 0x5480 on is free ... */ -#define TIOCSCTTY 0x5480 /* become controlling tty */ -#define TIOCGSOFTCAR 0x5481 -#define TIOCSSOFTCAR 0x5482 -#define TIOCLINUX 0x5483 -#define TIOCGSERIAL 0x5484 -#define TIOCSSERIAL 0x5485 -#define TCSBRKP 0x5486 /* Needed for POSIX tcsendbreak() */ -#define TIOCSERCONFIG 0x5488 -#define TIOCSERGWILD 0x5489 -#define TIOCSERSWILD 0x548a -#define TIOCGLCKTRMIOS 0x548b -#define TIOCSLCKTRMIOS 0x548c -#define TIOCSERGSTRUCT 0x548d /* For debugging only */ -#define TIOCSERGETLSR 0x548e /* Get line status register */ -#define TIOCSERGETMULTI 0x548f /* Get multiport config */ -#define TIOCSERSETMULTI 0x5490 /* Set multiport config */ -#define TIOCMIWAIT 0x5491 /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x5492 /* read serial port inline interrupt counts */ -#define TIOCGHAYESESP 0x5493 /* Get Hayes ESP configuration */ -#define TIOCSHAYESESP 0x5494 /* Set Hayes ESP configuration */ - -#endif /* __ASM_IOCTLS_H */ diff --git a/include/asm-mips64/ip32/io.h b/include/asm-mips64/ip32/io.h deleted file mode 100644 index 0232ae6e933..00000000000 --- a/include/asm-mips64/ip32/io.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef __ASM_IP32_IO_H__ -#define __ASM_IP32_IO_H__ - -#include - -/*#ifdef CONFIG_MIPS_UNCACHED*/ -#define UNCACHEDADDR(x) (0x9000000000000000UL | (u64)(x)) -/*#else -#define UNCACHEDADDR(x) (x) -#endif*/ -/*#define UNCACHEDADDR(x) (KSEG1ADDR (x)) */ -#define IO_SPACE_BASE UNCACHEDADDR (MACEPCI_HI_MEMORY) -#define IO_SPACE_LIMIT 0xffffffffUL - -#endif diff --git a/include/asm-mips64/ipc.h b/include/asm-mips64/ipc.h deleted file mode 100644 index 47f95a7d1c4..00000000000 --- a/include/asm-mips64/ipc.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef _ASM_IPC_H -#define _ASM_IPC_H - -/* - * These are used to wrap system calls on MIPS32. - * - * See arch/mips/kernel/sysmips.c for ugly details.. - * FIXME: split up into ordinary syscalls ... - */ -struct ipc_kludge { - struct msgbuf *msgp; - long msgtyp; -}; - -#define SEMOP 1 -#define SEMGET 2 -#define SEMCTL 3 -#define SEMTIMEDOP 4 -#define MSGSND 11 -#define MSGRCV 12 -#define MSGGET 13 -#define MSGCTL 14 -#define SHMAT 21 -#define SHMDT 22 -#define SHMGET 23 -#define SHMCTL 24 - -/* Used by the DIPC package, try and avoid reusing it */ -#define DIPC 25 - -#define IPCCALL(version,op) ((version)<<16 | (op)) - -#endif /* _ASM_IPC_H */ diff --git a/include/asm-mips64/ipcbuf.h b/include/asm-mips64/ipcbuf.h deleted file mode 100644 index d47d08f264e..00000000000 --- a/include/asm-mips64/ipcbuf.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _ASM_IPCBUF_H -#define _ASM_IPCBUF_H - -/* - * The ipc64_perm structure for alpha architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 32-bit seq - * - 2 miscellaneous 64-bit values - */ - -struct ipc64_perm -{ - __kernel_key_t key; - __kernel_uid_t uid; - __kernel_gid_t gid; - __kernel_uid_t cuid; - __kernel_gid_t cgid; - __kernel_mode_t mode; - unsigned short seq; - unsigned short __pad1; - unsigned long __unused1; - unsigned long __unused2; -}; - -#endif /* _ASM_IPCBUF_H */ diff --git a/include/asm-mips64/irq.h b/include/asm-mips64/irq.h deleted file mode 100644 index 8ecdd06f018..00000000000 --- a/include/asm-mips64/irq.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle - * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2001 Kanoj Sarcar - */ -#ifndef _ASM_IRQ_H -#define _ASM_IRQ_H - -#include -#include -#include - -#define NR_IRQS 256 - -/* - * Number of levels in INT_PEND0. Can be set to 128 if we also - * consider INT_PEND1. - */ -#define PERNODE_LEVELS 64 - -extern int node_level_to_irq[MAX_COMPACT_NODES][PERNODE_LEVELS]; - -/* - * we need to map irq's up to at least bit 7 of the INT_MASK0_A register - * since bits 0-6 are pre-allocated for other purposes. - */ -#define LEAST_LEVEL 7 -#define FAST_IRQ_TO_LEVEL(i) ((i) + LEAST_LEVEL) -#define LEVEL_TO_IRQ(c, l) \ - (node_level_to_irq[CPUID_TO_COMPACT_NODEID(c)][(l)]) - -#ifdef CONFIG_I8259 -static inline int irq_canonicalize(int irq) -{ - return ((irq == 2) ? 9 : irq); -} -#else -#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ -#endif - -extern void disable_irq(unsigned int); -extern void disable_irq_nosync(unsigned int); -extern void enable_irq(unsigned int); - -struct pt_regs; -extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs); - -/* Machine specific interrupt initialization */ -extern void (*irq_setup)(void); - -extern void init_generic_irq(void); - -#endif /* _ASM_IRQ_H */ diff --git a/include/asm-mips64/irq_cpu.h b/include/asm-mips64/irq_cpu.h deleted file mode 100644 index 30bf784a485..00000000000 --- a/include/asm-mips64/irq_cpu.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * include/asm-mips/irq_cpu.h - * - * MIPS CPU interrupt definitions. - * - * Copyright (C) 2002 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS64_IRQ_CPU_H -#define __ASM_MIPS64_IRQ_CPU_H - -extern void mips_cpu_irq_init(int irq_base); - -#endif /* __ASM_MIPS64_IRQ_CPU_H */ diff --git a/include/asm-mips64/isadep.h b/include/asm-mips64/isadep.h deleted file mode 100644 index 7bb003511d9..00000000000 --- a/include/asm-mips64/isadep.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Various ISA level dependent constants. - * Most of the following constants reflect the different layout - * of Coprocessor 0 registers. - * - * Copyright (c) 1998 Harald Koerfgen - */ -#include - -#ifndef __ASM_ISADEP_H -#define __ASM_ISADEP_H - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) -/* - * R2000 or R3000 - */ - -/* - * kernel or user mode? (CP0_STATUS) - */ -#define KU_MASK 0x08 -#define KU_USER 0x08 -#define KU_KERN 0x00 - -#else -/* - * kernel or user mode? - */ -#define KU_MASK 0x18 -#define KU_USER 0x10 -#define KU_KERN 0x00 - -#endif - -#endif /* __ASM_ISADEP_H */ diff --git a/include/asm-mips64/keyboard.h b/include/asm-mips64/keyboard.h deleted file mode 100644 index b80dd875e71..00000000000 --- a/include/asm-mips64/keyboard.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999 Ralf Baechle - */ -#ifndef _ASM_KEYBOARD_H -#define _ASM_KEYBOARD_H - -#ifdef __KERNEL__ - -#include -#include -#include -#include -#include - -#define DISABLE_KBD_DURING_INTERRUPTS 0 - -#ifdef CONFIG_PC_KEYB - -extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode); -extern int pckbd_getkeycode(unsigned int scancode); -extern int pckbd_translate(unsigned char scancode, unsigned char *keycode, - char raw_mode); -extern char pckbd_unexpected_up(unsigned char keycode); -extern void pckbd_leds(unsigned char leds); -extern void pckbd_init_hw(void); -extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *); -extern pm_callback pm_kbd_request_override; -extern unsigned char pckbd_sysrq_xlate[128]; -extern void kbd_forward_char (int ch); - -#define kbd_setkeycode pckbd_setkeycode -#define kbd_getkeycode pckbd_getkeycode -#define kbd_translate pckbd_translate -#define kbd_unexpected_up pckbd_unexpected_up -#define kbd_leds pckbd_leds -#define kbd_init_hw pckbd_init_hw -#define kbd_sysrq_xlate pckbd_sysrq_xlate - -#define SYSRQ_KEY 0x54 - -/* Some stoneage hardware needs delays after some operations. */ -#define kbd_pause() do { } while(0) - -struct kbd_ops { - /* Keyboard driver resource allocation */ - void (*kbd_request_region)(void); - int (*kbd_request_irq)(void (*handler)(int, void *, struct pt_regs *)); - - /* PSaux driver resource management */ - int (*aux_request_irq)(void (*handler)(int, void *, struct pt_regs *)); - void (*aux_free_irq)(void); - - /* Methods to access the keyboard processor's I/O registers */ - unsigned char (*kbd_read_input)(void); - void (*kbd_write_output)(unsigned char val); - void (*kbd_write_command)(unsigned char val); - unsigned char (*kbd_read_status)(void); -}; - -extern struct kbd_ops *kbd_ops; - -/* Do the actual calls via kbd_ops vector */ -#define kbd_request_region() kbd_ops->kbd_request_region() -#define kbd_request_irq(handler) kbd_ops->kbd_request_irq(handler) - -#define aux_request_irq(hand, dev_id) kbd_ops->aux_request_irq(hand) -#define aux_free_irq(dev_id) kbd_ops->aux_free_irq() - -#define kbd_read_input() kbd_ops->kbd_read_input() -#define kbd_write_output(val) kbd_ops->kbd_write_output(val) -#define kbd_write_command(val) kbd_ops->kbd_write_command(val) -#define kbd_read_status() kbd_ops->kbd_read_status() - -#else - -extern int kbd_setkeycode(unsigned int scancode, unsigned int keycode); -extern int kbd_getkeycode(unsigned int scancode); -extern int kbd_translate(unsigned char scancode, unsigned char *keycode, - char raw_mode); -extern char kbd_unexpected_up(unsigned char keycode); -extern void kbd_leds(unsigned char leds); -extern void kbd_init_hw(void); -extern unsigned char *kbd_sysrq_xlate; - -extern unsigned char kbd_sysrq_key; -#define SYSRQ_KEY kbd_sysrq_key - -#endif - -#endif /* __KERNEL */ - -#endif /* _ASM_KEYBOARD_H */ diff --git a/include/asm-mips64/kmap_types.h b/include/asm-mips64/kmap_types.h deleted file mode 100644 index fc0bd1245c5..00000000000 --- a/include/asm-mips64/kmap_types.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copy of the 32-bit kmap_types.h file just to keep things building ... - */ -#ifndef _ASM_KMAP_TYPES_H -#define _ASM_KMAP_TYPES_H - -#include - -#ifdef CONFIG_DEBUG_HIGHMEM -# define D(n) __KM_FENCE_##n , -#else -# define D(n) -#endif - -enum km_type { -D(0) KM_BOUNCE_READ, -D(1) KM_SKB_SUNRPC_DATA, -D(2) KM_SKB_DATA_SOFTIRQ, -D(3) KM_USER0, -D(4) KM_USER1, -D(5) KM_BIO_SRC_IRQ, -D(6) KM_BIO_DST_IRQ, -D(7) KM_PTE0, -D(8) KM_PTE1, -D(9) KM_PTE2, -D(10) KM_IRQ0, -D(11) KM_IRQ1, -D(12) KM_SOFTIRQ0, -D(13) KM_SOFTIRQ1, -D(14) KM_TYPE_NR -}; - -#undef D - -#endif diff --git a/include/asm-mips64/linkage.h b/include/asm-mips64/linkage.h deleted file mode 100644 index 291c2d01c44..00000000000 --- a/include/asm-mips64/linkage.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H - -/* Nothing to see here... */ - -#endif diff --git a/include/asm-mips64/mc146818rtc.h b/include/asm-mips64/mc146818rtc.h deleted file mode 100644 index 73cdde556e2..00000000000 --- a/include/asm-mips64/mc146818rtc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Machine dependent access functions for RTC registers. - * - * Copyright (C) 1996, 1997, 1998 Ralf Baechle - * Copyright (C) 2002 Maciej W. Rozycki - */ -#ifndef _ASM_MC146818RTC_H -#define _ASM_MC146818RTC_H - -#include - -#include - - -/* - * This structure defines how to access various features of - * different machine types and how to access them. - */ -struct rtc_ops { - /* How to access the RTC register in a DS1287. */ - unsigned char (*rtc_read_data)(unsigned long addr); - void (*rtc_write_data)(unsigned char data, unsigned long addr); - int (*rtc_bcd_mode)(void); -}; - -extern struct rtc_ops *rtc_ops; - -/* - * Most supported machines access the RTC index register via an ISA - * port access but the way to access the date register differs ... - * The DECstation directly maps the RTC memory in the CPU's address - * space with the chipset generating necessary index write/data access - * cycles automagically. - */ -#define CMOS_READ(addr) ({ \ -rtc_ops->rtc_read_data(addr); \ -}) -#define CMOS_WRITE(val, addr) ({ \ -rtc_ops->rtc_write_data(val, addr); \ -}) -#define RTC_ALWAYS_BCD \ -rtc_ops->rtc_bcd_mode() - - -#ifdef CONFIG_DECSTATION - -#include - -#else - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_IRQ 8 - -#endif - -#endif /* _ASM_MC146818RTC_H */ diff --git a/include/asm-mips64/mips-boards/atlas.h b/include/asm-mips64/mips-boards/atlas.h deleted file mode 100644 index 07d2e6f1c14..00000000000 --- a/include/asm-mips64/mips-boards/atlas.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines of the Atlas board specific address-MAP, registers, etc. - * - */ -#ifndef _MIPS_ATLAS_H -#define _MIPS_ATLAS_H - -#include - -/* - * Atlas RTC-device indirect register access. - */ -#define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800)) -#define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808)) - - -/* - * Atlas interrupt controller register base. - */ -#define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) - -/* - * Atlas UART register base. - */ -#define ATLAS_UART_REGS_BASE (0x1f000900) -#define ATLAS_BASE_BAUD ( 3686400 / 16 ) - -/* - * Atlas PSU standby register. - */ -#define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600)) -#define ATLAS_GOSTBY 0x4d - -/* - * We make a universal assumption about the way the bootloader (YAMON) - * have located the Philips SAA9730 chip. - * This is not ideal, but is needed for setting up remote debugging as - * soon as possible. - */ -#define ATLAS_SAA9730_REG (KSEG1ADDR(0x08800000)) - -#endif /* !(_MIPS_ATLAS_H) */ diff --git a/include/asm-mips64/mips-boards/atlasint.h b/include/asm-mips64/mips-boards/atlasint.h deleted file mode 100644 index 0a4715c772d..00000000000 --- a/include/asm-mips64/mips-boards/atlasint.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines for the Atlas interrupt controller. - * - */ -#ifndef _MIPS_ATLASINT_H -#define _MIPS_ATLASINT_H - -/* Number of IRQ supported on hw interrupt 0. */ -#define ATLASINT_UART 0 -#define ATLASINT_END 32 - -/* - * Atlas registers are memory mapped on 64-bit aligned boundaries and - * only word access are allowed. - */ -struct atlas_ictrl_regs { - volatile unsigned long intraw; - long dummy1; - volatile unsigned long intseten; - long dummy2; - volatile unsigned long intrsten; - long dummy3; - volatile unsigned long intenable; - long dummy4; - volatile unsigned long intstatus; - long dummy5; -}; - -extern void atlasint_init(void); - -#endif /* !(_MIPS_ATLASINT_H) */ diff --git a/include/asm-mips64/mips-boards/bonito64.h b/include/asm-mips64/mips-boards/bonito64.h deleted file mode 100644 index f2fdf9c4e9b..00000000000 --- a/include/asm-mips64/mips-boards/bonito64.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - * bonito.h - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2001 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This file is the original bonito.h from Algorithmics with minor changes - * to fit into linux. - */ - -/* - * Bonito Register Map - * Copyright (c) 1999 Algorithmics Ltd - * - * Algorithmics gives permission for anyone to use and modify this file - * without any obligation or license condition except that you retain - * this copyright message in any source redistribution in whole or part. - * - * Updated copies of this and other files can be found at - * ftp://ftp.algor.co.uk/pub/bonito/ - * - * Users of the Bonito controller are warmly recommended to contribute - * any useful changes back to Algorithmics (mail to bonito@algor.co.uk). - */ - -/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */ -/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */ - -#ifndef _ASM_MIPS_BOARDS_BONITO64_H -#define _ASM_MIPS_BOARDS_BONITO64_H - -#ifdef __ASSEMBLY__ - -/* offsets from base register */ -#define BONITO(x) (x) - -#else /* !__ASSEMBLY__ */ - -/* offsets from base pointer, this construct allows optimisation */ -/* static char * const _bonito = PA_TO_KVA1(BONITO_BASE); */ -#define BONITO(x) *(volatile u32 *)(_bonito + (x)) - -#endif /* __ASSEMBLY__ */ - - -#define BONITO_BOOT_BASE 0x1fc00000 -#define BONITO_BOOT_SIZE 0x00100000 -#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) -#define BONITO_FLASH_BASE 0x1c000000 -#define BONITO_FLASH_SIZE 0x03000000 -#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) -#define BONITO_SOCKET_BASE 0x1f800000 -#define BONITO_SOCKET_SIZE 0x00400000 -#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) -#define BONITO_REG_BASE 0x1fe00000 -#define BONITO_REG_SIZE 0x00040000 -#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) -#define BONITO_DEV_BASE 0x1ff00000 -#define BONITO_DEV_SIZE 0x00100000 -#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) -#define BONITO_PCILO_BASE 0x10000000 -#define BONITO_PCILO_SIZE 0x0c000000 -#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) -#define BONITO_PCILO0_BASE 0x10000000 -#define BONITO_PCILO1_BASE 0x14000000 -#define BONITO_PCILO2_BASE 0x18000000 -#define BONITO_PCIHI_BASE 0x20000000 -#define BONITO_PCIHI_SIZE 0x20000000 -#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) -#define BONITO_PCIIO_BASE 0x1fd00000 -#define BONITO_PCIIO_SIZE 0x00100000 -#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) -#define BONITO_PCICFG_BASE 0x1fe80000 -#define BONITO_PCICFG_SIZE 0x00080000 -#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) - - -/* Bonito Register Bases */ - -#define BONITO_PCICONFIGBASE 0x00 -#define BONITO_REGBASE 0x100 - - -/* PCI Configuration Registers */ - -#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) -#define BONITO_PCIDID BONITO_PCI_REG(0x00) -#define BONITO_PCICMD BONITO_PCI_REG(0x04) -#define BONITO_PCICLASS BONITO_PCI_REG(0x08) -#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c) -#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) -#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) -#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) -#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30) -#define BONITO_PCIINT BONITO_PCI_REG(0x3c) - -#define BONITO_PCICMD_PERR_CLR 0x80000000 -#define BONITO_PCICMD_SERR_CLR 0x40000000 -#define BONITO_PCICMD_MABORT_CLR 0x20000000 -#define BONITO_PCICMD_MTABORT_CLR 0x10000000 -#define BONITO_PCICMD_TABORT_CLR 0x08000000 -#define BONITO_PCICMD_MPERR_CLR 0x01000000 -#define BONITO_PCICMD_PERRRESPEN 0x00000040 -#define BONITO_PCICMD_ASTEPEN 0x00000080 -#define BONITO_PCICMD_SERREN 0x00000100 -#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00 -#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8 - - - - -/* 1. Bonito h/w Configuration */ -/* Power on register */ - -#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00) - -#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000 -#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000 -#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000 -#define BONITO_BONPONCFG_CPUBIGEND 0x00004000 -/* Added by RPF 11-9-00 */ -#define BONITO_BONPONCFG_BURSTORDER 0x00001000 -/* --- */ -#define BONITO_BONPONCFG_CPUPARITY 0x00002000 -#define BONITO_BONPONCFG_CPUTYPE 0x00000007 -#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0 -#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008 -#define BONITO_BONPONCFG_IS_ARBITER 0x00000010 -#define BONITO_BONPONCFG_ROMBOOT 0x000000c0 -#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6 - -#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) - -#define BONITO_PCIMAP_WINSIZE (1<<26) -#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) -#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) - -/* pcimembaseCfg */ - -#define BONITO_PCIMEMBASECFG_MASK 0xf0000000 -#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f -#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0 -#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0 -#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5 -#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400 -#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800 - -#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000 -#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12 -#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000 -#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17 -#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000 -#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000 - -#define BONITO_PCIMEMBASECFG_ASHIFT 23 -#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff -#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) -#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) - -#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) - - -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) -#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) - -#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ - (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ - (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ - ) - -/* PCICmd */ - -#define BONITO_PCICMD_MEMEN 0x00000002 -#define BONITO_PCICMD_MSTREN 0x00000004 - - -#endif /* _ASM_MIPS_BOARDS_BONITO64_H */ diff --git a/include/asm-mips64/mips-boards/generic.h b/include/asm-mips64/mips-boards/generic.h deleted file mode 100644 index ef146b32e60..00000000000 --- a/include/asm-mips64/mips-boards/generic.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines of the MIPS boards specific address-MAP, registers, etc. - * - */ -#ifndef _MIPS_GENERIC_H -#define _MIPS_GENERIC_H - -#include -#include -#include -#include - -/* - * Display register base. - */ -#if defined(CONFIG_MIPS_SEAD) -#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f0005c0)) -#else -#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410)) -#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418)) -#endif - - -/* - * Yamon Prom print address. - */ -#define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504)) - - -/* - * Reset register. - */ -#if defined(CONFIG_MIPS_SEAD) -#define SOFTRES_REG (KSEG1ADDR(0x1e800050)) -#define GORESET 0x4d -#else -#define SOFTRES_REG (KSEG1ADDR(0x1f000500)) -#define GORESET 0x42 -#endif - -/* - * Revision register. - */ -#define MIPS_REVISION_REG (KSEG1ADDR(0x1fc00010)) -#define MIPS_REVISION_CORID_QED_RM5261 0 -#define MIPS_REVISION_CORID_CORE_LV 1 -#define MIPS_REVISION_CORID_BONITO64 2 -#define MIPS_REVISION_CORID_CORE_20K 3 -#define MIPS_REVISION_CORID_CORE_FPGA 4 -#define MIPS_REVISION_CORID_CORE_MSC 5 - -#define MIPS_REVISION_CORID (((*(volatile u32 *)(MIPS_REVISION_REG)) >> 10) & 0x3f) - -extern unsigned int mips_revision_corid; - - -/* - * Galileo GT64120 system controller register base. - */ -#define MIPS_GT_BASE (KSEG1ADDR(0x1be00000)) - -/* - * Because of the way the internal register works on the Galileo chip, - * we need to swap the bytes when running bigendian. - */ -#define GT_WRITE(ofs, data) \ - *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data) -#define GT_READ(ofs, data) \ - data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs)) - -#define GT_PCI_WRITE(ofs, data) \ - *(volatile u32 *)(MIPS_GT_BASE+ofs) = data -#define GT_PCI_READ(ofs, data) \ - data = *(volatile u32 *)(MIPS_GT_BASE+ofs) - -/* - * Algorithmics Bonito64 system controller register base. - */ -static char * const _bonito = (char *)KSEG1ADDR(BONITO_REG_BASE); - -/* - * MIPS System controller PCI register base. - */ -#define MSC01_PCI_REG_BASE (KSEG1ADDR(0x1bd00000)) - -#define MSC_WRITE(reg, data) \ - *(volatile u32 *)(reg) = data -#define MSC_READ(reg, data) \ - data = *(volatile u32 *)(reg) - -#endif /* !(_MIPS_GENERIC_H) */ diff --git a/include/asm-mips64/mips-boards/gt64120.h b/include/asm-mips64/mips-boards/gt64120.h deleted file mode 100644 index 23413ba2736..00000000000 --- a/include/asm-mips64/mips-boards/gt64120.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Register definitions for Galileo 64120 system controller. - * - */ -#ifndef GT64120_H -#define GT64120_H - -#define MSK(n) ((1 << (n)) - 1) - -/************************************************************************ - * Register offset addresses - ************************************************************************/ - -#define GT_CPU_OFS 0x000 - -#define GT_CPU_OFS 0x000 -#define GT_SCS10LD_OFS 0x008 -#define GT_SCS10HD_OFS 0x010 -#define GT_SCS32LD_OFS 0x018 -#define GT_SCS32HD_OFS 0x020 -#define GT_CS20LD_OFS 0x028 -#define GT_CS20HD_OFS 0x030 -#define GT_CS3BOOTLD_OFS 0x038 -#define GT_CS3BOOTHD_OFS 0x040 -#define GT_PCI0IOLD_OFS 0x048 -#define GT_PCI0IOHD_OFS 0x050 -#define GT_PCI0M0LD_OFS 0x058 -#define GT_PCI0M0HD_OFS 0x060 -#define GT_ISD_OFS 0x068 -#define GT_PCI0M1LD_OFS 0x080 -#define GT_PCI0M1HD_OFS 0x088 -#define GT_PCI1IOLD_OFS 0x090 -#define GT_PCI1IOHD_OFS 0x098 -#define GT_PCI1M0LD_OFS 0x0a0 -#define GT_PCI1M0HD_OFS 0x0a8 -#define GT_PCI1M1LD_OFS 0x0b0 -#define GT_PCI1M1HD_OFS 0x0b8 - -#define GT_SCS0LD_OFS 0x400 -#define GT_SCS0HD_OFS 0x404 -#define GT_SCS1LD_OFS 0x408 -#define GT_SCS1HD_OFS 0x40c -#define GT_SCS2LD_OFS 0x410 -#define GT_SCS2HD_OFS 0x414 -#define GT_SCS3LD_OFS 0x418 -#define GT_SCS3HD_OFS 0x41c -#define GT_CS0LD_OFS 0x420 -#define GT_CS0HD_OFS 0x424 -#define GT_CS1LD_OFS 0x428 -#define GT_CS1HD_OFS 0x42c -#define GT_CS2LD_OFS 0x430 -#define GT_CS2HD_OFS 0x434 -#define GT_CS3LD_OFS 0x438 -#define GT_CS3HD_OFS 0x43c -#define GT_BOOTLD_OFS 0x440 -#define GT_BOOTHD_OFS 0x444 - -#define GT_SDRAM_B0_OFS 0x44c -#define GT_SDRAM_CFG_OFS 0x448 -#define GT_SDRAM_B2_OFS 0x454 -#define GT_SDRAM_OPMODE_OFS 0x474 -#define GT_SDRAM_BM_OFS 0x478 -#define GT_SDRAM_ADDRDECODE_OFS 0x47c - -#define GT_PCI0_CMD_OFS 0xc00 -#define GT_PCI0_TOR_OFS 0xc04 -#define GT_PCI0_BS_SCS10_OFS 0xc08 -#define GT_PCI0_BS_SCS32_OFS 0xc0c -#define GT_INTRCAUSE_OFS 0xc18 -#define GT_PCI0_IACK_OFS 0xc34 -#define GT_PCI0_BARE_OFS 0xc3c -#define GT_PCI0_CFGADDR_OFS 0xcf8 -#define GT_PCI0_CFGDATA_OFS 0xcfc - - - - -/************************************************************************ - * Register encodings - ************************************************************************/ - -#define GT_CPU_ENDIAN_SHF 12 -#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) -#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK -#define GT_CPU_WR_SHF 16 -#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) -#define GT_CPU_WR_BIT GT_CPU_WR_MSK -#define GT_CPU_WR_DXDXDXDX 0 -#define GT_CPU_WR_DDDD 1 - - -#define GT_CFGADDR_CFGEN_SHF 31 -#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) -#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK - -#define GT_CFGADDR_BUSNUM_SHF 16 -#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) - -#define GT_CFGADDR_DEVNUM_SHF 11 -#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) - -#define GT_CFGADDR_FUNCNUM_SHF 8 -#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) - -#define GT_CFGADDR_REGNUM_SHF 2 -#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) - - -#define GT_SDRAM_BM_ORDER_SHF 2 -#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) -#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK -#define GT_SDRAM_BM_ORDER_SUB 1 -#define GT_SDRAM_BM_ORDER_LIN 0 - -#define GT_SDRAM_BM_RSVD_ALL1 0xFFB - - -#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 -#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) -#define GT_SDRAM_ADDRDECODE_ADDR_0 0 -#define GT_SDRAM_ADDRDECODE_ADDR_1 1 -#define GT_SDRAM_ADDRDECODE_ADDR_2 2 -#define GT_SDRAM_ADDRDECODE_ADDR_3 3 -#define GT_SDRAM_ADDRDECODE_ADDR_4 4 -#define GT_SDRAM_ADDRDECODE_ADDR_5 5 -#define GT_SDRAM_ADDRDECODE_ADDR_6 6 -#define GT_SDRAM_ADDRDECODE_ADDR_7 7 - - -#define GT_SDRAM_B0_CASLAT_SHF 0 -#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) -#define GT_SDRAM_B0_CASLAT_2 1 -#define GT_SDRAM_B0_CASLAT_3 2 - -#define GT_SDRAM_B0_FTDIS_SHF 2 -#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) -#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK - -#define GT_SDRAM_B0_SRASPRCHG_SHF 3 -#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) -#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK -#define GT_SDRAM_B0_SRASPRCHG_2 0 -#define GT_SDRAM_B0_SRASPRCHG_3 1 - -#define GT_SDRAM_B0_B0COMPAB_SHF 4 -#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) -#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK - -#define GT_SDRAM_B0_64BITINT_SHF 5 -#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) -#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK -#define GT_SDRAM_B0_64BITINT_2 0 -#define GT_SDRAM_B0_64BITINT_4 1 - -#define GT_SDRAM_B0_BW_SHF 6 -#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) -#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK -#define GT_SDRAM_B0_BW_32 0 -#define GT_SDRAM_B0_BW_64 1 - -#define GT_SDRAM_B0_BLODD_SHF 7 -#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) -#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK - -#define GT_SDRAM_B0_PAR_SHF 8 -#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) -#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK - -#define GT_SDRAM_B0_BYPASS_SHF 9 -#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) -#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK - -#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 -#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) -#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK -#define GT_SDRAM_B0_SRAS2SCAS_2 0 -#define GT_SDRAM_B0_SRAS2SCAS_3 1 - -#define GT_SDRAM_B0_SIZE_SHF 11 -#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) -#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK -#define GT_SDRAM_B0_SIZE_16M 0 -#define GT_SDRAM_B0_SIZE_64M 1 - -#define GT_SDRAM_B0_EXTPAR_SHF 12 -#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) -#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK - -#define GT_SDRAM_B0_BLEN_SHF 13 -#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) -#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK -#define GT_SDRAM_B0_BLEN_8 0 -#define GT_SDRAM_B0_BLEN_4 1 - - -#define GT_SDRAM_CFG_REFINT_SHF 0 -#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) - -#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 -#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) -#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK - -#define GT_SDRAM_CFG_RMW_SHF 15 -#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) -#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK - -#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 -#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) -#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK - -#define GT_SDRAM_CFG_DUPCNTL_SHF 19 -#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) -#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK - -#define GT_SDRAM_CFG_DUPBA_SHF 20 -#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) -#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK - -#define GT_SDRAM_CFG_DUPEOT0_SHF 21 -#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) -#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK - -#define GT_SDRAM_CFG_DUPEOT1_SHF 22 -#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) -#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK - -#define GT_SDRAM_OPMODE_OP_SHF 0 -#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) -#define GT_SDRAM_OPMODE_OP_NORMAL 0 -#define GT_SDRAM_OPMODE_OP_NOP 1 -#define GT_SDRAM_OPMODE_OP_PRCHG 2 -#define GT_SDRAM_OPMODE_OP_MODE 3 -#define GT_SDRAM_OPMODE_OP_CBR 4 - - -#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 -#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) -#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK - -#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 -#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) -#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK - -#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 -#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) -#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK - -#define GT_PCI0_BARE_INTIODIS_SHF 3 -#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) -#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK - -#define GT_PCI0_BARE_INTMEMDIS_SHF 4 -#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) -#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK - -#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 -#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) -#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK - -#define GT_PCI0_BARE_CS20DIS_SHF 6 -#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) -#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK - -#define GT_PCI0_BARE_SCS32DIS_SHF 7 -#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) -#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK - -#define GT_PCI0_BARE_SCS10DIS_SHF 8 -#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) -#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK - - -#define GT_INTRCAUSE_MASABORT0_SHF 18 -#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) -#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK - -#define GT_INTRCAUSE_TARABORT0_SHF 19 -#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) -#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK - - -#define GT_PCI0_CFGADDR_REGNUM_SHF 2 -#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) -#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 -#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) -#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 -#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) -#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 -#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 -#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK - -#define GT_PCI0_CMD_MBYTESWAP_SHF 0 -#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) -#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK -#define GT_PCI0_CMD_MWORDSWAP_SHF 10 -#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) -#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK -#define GT_PCI0_CMD_SBYTESWAP_SHF 16 -#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) -#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK -#define GT_PCI0_CMD_SWORDSWAP_SHF 11 -#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) -#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK - - -/************************************************************************ - * Misc - ************************************************************************/ - -#define GT_DEF_BASE 0x14000000 -#define GT_DEF_PCI0_MEM0_BASE 0x12000000 -#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ -#define GT_LATTIM_MIN 6 /* Minimum lat */ - -#endif /* #ifndef GT64120_H */ diff --git a/include/asm-mips64/mips-boards/io.h b/include/asm-mips64/mips-boards/io.h deleted file mode 100644 index 06822110db5..00000000000 --- a/include/asm-mips64/mips-boards/io.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines of the MIPS boards specific IO address-MAP. - * - */ -#ifndef _ASM_MIPS_BOARDS_IO_H -#define _ASM_MIPS_BOARDS_IO_H - -#include - -#define IO_SPACE_BASE K1BASE - -#define IO_SPACE_LIMIT 0xffffffff - -#endif /* _ASM_MIPS_BOARDS_IO_H */ diff --git a/include/asm-mips64/mips-boards/malta.h b/include/asm-mips64/mips-boards/malta.h deleted file mode 100644 index 48126b3e101..00000000000 --- a/include/asm-mips64/mips-boards/malta.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines of the Malta board specific address-MAP, registers, etc. - * - */ -#ifndef _MIPS_MALTA_H -#define _MIPS_MALTA_H - -#include -#include - -/* - * Malta I/O ports base address for the Galileo GT64120 and Algorithmics - * Bonito system controllers. - */ -#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) -#define MALTA_BONITO_PORT_BASE (KSEG1ADDR(0x1fd00000)) -#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) - -static inline unsigned long get_gt_port_base(unsigned long reg) -{ - unsigned long addr; - GT_READ(reg, addr); - return KSEG1ADDR((addr & 0xffff) << 21); -} - -static inline unsigned long get_msc_port_base(unsigned long reg) -{ - unsigned long addr; - MSC_READ(reg, addr); - return KSEG1ADDR(addr); -} - -/* - * Malta RTC-device indirect register access. - */ -#define MALTA_RTC_ADR_REG 0x70 -#define MALTA_RTC_DAT_REG 0x71 - -/* - * Malta SMSC FDC37M817 Super I/O Controller register. - */ -#define SMSC_CONFIG_REG 0x3f0 -#define SMSC_DATA_REG 0x3f1 - -#define SMSC_CONFIG_DEVNUM 0x7 -#define SMSC_CONFIG_ACTIVATE 0x30 -#define SMSC_CONFIG_ENTER 0x55 -#define SMSC_CONFIG_EXIT 0xaa - -#define SMSC_CONFIG_DEVNUM_FLOPPY 0 - -#define SMSC_CONFIG_ACTIVATE_ENABLE 1 - -#define SMSC_WRITE(x,a) outb(x,a) - -#define MALTA_JMPRS_REG (KSEG1ADDR(0x1f000210)) - -#endif /* !(_MIPS_MALTA_H) */ diff --git a/include/asm-mips64/mips-boards/maltaint.h b/include/asm-mips64/mips-boards/maltaint.h deleted file mode 100644 index 376181882e8..00000000000 --- a/include/asm-mips64/mips-boards/maltaint.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines for the Malta interrupt controller. - * - */ -#ifndef _MIPS_MALTAINT_H -#define _MIPS_MALTAINT_H - -/* Number of IRQ supported on hw interrupt 0. */ -#define MALTAINT_END 16 - -extern void maltaint_init(void); - -#endif /* !(_MIPS_MALTAINT_H) */ diff --git a/include/asm-mips64/mips-boards/msc01_pci.h b/include/asm-mips64/mips-boards/msc01_pci.h deleted file mode 100644 index e9dce14de50..00000000000 --- a/include/asm-mips64/mips-boards/msc01_pci.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * mcs01_pci.h - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * PCI Register definitions for the MIPS System Controller. - */ -#ifndef MSC01_PCI_H -#define MSC01_PCI_H - -/***************************************************************************** - * Register offset addresses - ****************************************************************************/ - -#define MSC01_PCI_ID_OFS 0x0000 -#define MSC01_PCI_SC2PMBASL_OFS 0x0208 -#define MSC01_PCI_SC2PMMSKL_OFS 0x0218 -#define MSC01_PCI_SC2PMMAPL_OFS 0x0228 -#define MSC01_PCI_SC2PIOBASL_OFS 0x0248 -#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 -#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 -#define MSC01_PCI_P2SCMSKL_OFS 0x0308 -#define MSC01_PCI_P2SCMAPL_OFS 0x0318 -#define MSC01_PCI_INTCFG_OFS 0x0600 -#define MSC01_PCI_INTSTAT_OFS 0x0608 -#define MSC01_PCI_CFGADDR_OFS 0x0610 -#define MSC01_PCI_CFGDATA_OFS 0x0618 -#define MSC01_PCI_IACK_OFS 0x0620 -#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */ -#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */ -#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */ -#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */ -#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */ -#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */ -#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */ -#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */ -#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */ -#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */ -#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */ -#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */ -#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */ -#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */ -#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */ -#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */ -#define MSC01_PCI_BAR0_OFS 0x2220 -#define MSC01_PCI_CFG_OFS 0x2380 -#define MSC01_PCI_SWAP_OFS 0x2388 - - -/***************************************************************************** - * Register encodings - ****************************************************************************/ - -#define MSC01_PCI_ID_ID_SHF 16 -#define MSC01_PCI_ID_ID_MSK 0x00ff0000 -#define MSC01_PCI_ID_ID_HOSTBRIDGE 82 -#define MSC01_PCI_ID_MAR_SHF 8 -#define MSC01_PCI_ID_MAR_MSK 0x0000ff00 -#define MSC01_PCI_ID_MIR_SHF 0 -#define MSC01_PCI_ID_MIR_MSK 0x000000ff - -#define MSC01_PCI_SC2PMBASL_BAS_SHF 24 -#define MSC01_PCI_SC2PMBASL_BAS_MSK 0xff000000 - -#define MSC01_PCI_SC2PMMSKL_MSK_SHF 24 -#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 - -#define MSC01_PCI_SC2PMMAPL_MAP_SHF 24 -#define MSC01_PCI_SC2PMMAPL_MAP_MSK 0xff000000 - -#define MSC01_PCI_SC2PIOBASL_BAS_SHF 24 -#define MSC01_PCI_SC2PIOBASL_BAS_MSK 0xff000000 - -#define MSC01_PCI_SC2PIOMSKL_MSK_SHF 24 -#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 - -#define MSC01_PCI_SC2PIOMAPL_MAP_SHF 24 -#define MSC01_PCI_SC2PIOMAPL_MAP_MSK 0xff000000 - -#define MSC01_PCI_P2SCMSKL_MSK_SHF 24 -#define MSC01_PCI_P2SCMSKL_MSK_MSK 0xff000000 - -#define MSC01_PCI_P2SCMAPL_MAP_SHF 24 -#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000 - -#define MSC01_PCI_INTCFG_RST_SHF 10 -#define MSC01_PCI_INTCFG_RST_MSK 0x00000400 -#define MSC01_PCI_INTCFG_RST_BIT 0x00000400 -#define MSC01_PCI_INTCFG_MWE_SHF 9 -#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 -#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 -#define MSC01_PCI_INTCFG_DTO_SHF 8 -#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 -#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 -#define MSC01_PCI_INTCFG_MA_SHF 7 -#define MSC01_PCI_INTCFG_MA_MSK 0x00000080 -#define MSC01_PCI_INTCFG_MA_BIT 0x00000080 -#define MSC01_PCI_INTCFG_TA_SHF 6 -#define MSC01_PCI_INTCFG_TA_MSK 0x00000040 -#define MSC01_PCI_INTCFG_TA_BIT 0x00000040 -#define MSC01_PCI_INTCFG_RTY_SHF 5 -#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 -#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 -#define MSC01_PCI_INTCFG_MWP_SHF 4 -#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 -#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 -#define MSC01_PCI_INTCFG_MRP_SHF 3 -#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 -#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 -#define MSC01_PCI_INTCFG_SWP_SHF 2 -#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 -#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 -#define MSC01_PCI_INTCFG_SRP_SHF 1 -#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 -#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 -#define MSC01_PCI_INTCFG_SE_SHF 0 -#define MSC01_PCI_INTCFG_SE_MSK 0x00000001 -#define MSC01_PCI_INTCFG_SE_BIT 0x00000001 - -#define MSC01_PCI_INTSTAT_RST_SHF 10 -#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 -#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 -#define MSC01_PCI_INTSTAT_MWE_SHF 9 -#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 -#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 -#define MSC01_PCI_INTSTAT_DTO_SHF 8 -#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 -#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 -#define MSC01_PCI_INTSTAT_MA_SHF 7 -#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 -#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 -#define MSC01_PCI_INTSTAT_TA_SHF 6 -#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 -#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 -#define MSC01_PCI_INTSTAT_RTY_SHF 5 -#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 -#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 -#define MSC01_PCI_INTSTAT_MWP_SHF 4 -#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 -#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 -#define MSC01_PCI_INTSTAT_MRP_SHF 3 -#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 -#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 -#define MSC01_PCI_INTSTAT_SWP_SHF 2 -#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 -#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 -#define MSC01_PCI_INTSTAT_SRP_SHF 1 -#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 -#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 -#define MSC01_PCI_INTSTAT_SE_SHF 0 -#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 -#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 - -#define MSC01_PCI_CFGADDR_BNUM_SHF 16 -#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000 -#define MSC01_PCI_CFGADDR_DNUM_SHF 11 -#define MSC01_PCI_CFGADDR_DNUM_MSK 0x0000f800 -#define MSC01_PCI_CFGADDR_FNUM_SHF 8 -#define MSC01_PCI_CFGADDR_FNUM_MSK 0x00000700 -#define MSC01_PCI_CFGADDR_RNUM_SHF 2 -#define MSC01_PCI_CFGADDR_RNUM_MSK 0x000000fc - -#define MSC01_PCI_CFGDATA_DATA_SHF 0 -#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff - -/* The defines below are ONLY valid for a MEM bar! */ -#define MSC01_PCI_BAR0_SIZE_SHF 4 -#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 -#define MSC01_PCI_BAR0_P_SHF 3 -#define MSC01_PCI_BAR0_P_MSK 0x00000008 -#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK -#define MSC01_PCI_BAR0_D_SHF 1 -#define MSC01_PCI_BAR0_D_MSK 0x00000006 -#define MSC01_PCI_BAR0_T_SHF 0 -#define MSC01_PCI_BAR0_T_MSK 0x00000001 -#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK - - -#define MSC01_PCI_CFG_RA_SHF 17 -#define MSC01_PCI_CFG_RA_MSK 0x00020000 -#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK -#define MSC01_PCI_CFG_G_SHF 16 -#define MSC01_PCI_CFG_G_MSK 0x00010000 -#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK -#define MSC01_PCI_CFG_EN_SHF 15 -#define MSC01_PCI_CFG_EN_MSK 0x00008000 -#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK -#define MSC01_PCI_CFG_MAXRTRY_SHF 0 -#define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff - -#define MSC01_PCI_SWAP_IO_SHF 18 -#define MSC01_PCI_SWAP_IO_MSK 0x000c0000 -#define MSC01_PCI_SWAP_MEM_SHF 16 -#define MSC01_PCI_SWAP_MEM_MSK 0x00030000 -#define MSC01_PCI_SWAP_BAR0_SHF 0 -#define MSC01_PCI_SWAP_BAR0_MSK 0x00000003 -#define MSC01_PCI_SWAP_NOSWAP 0 -#define MSC01_PCI_SWAP_BYTESWAP 1 - -/***************************************************************************** - * Registers absolute addresses - ****************************************************************************/ - -#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) -#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) -#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) -#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) -#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) -#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) -#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) -#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) -#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) -#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) -#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) -#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) -#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) -#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS) -#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS) -#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS) -#define MSC01_PCI_HEAD2 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS) -#define MSC01_PCI_HEAD3 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS) -#define MSC01_PCI_HEAD4 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS) -#define MSC01_PCI_HEAD5 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS) -#define MSC01_PCI_HEAD6 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS) -#define MSC01_PCI_HEAD7 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS) -#define MSC01_PCI_HEAD8 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS) -#define MSC01_PCI_HEAD9 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS) -#define MSC01_PCI_HEAD10 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS) -#define MSC01_PCI_HEAD11 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) -#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS) -#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) -#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) - -#endif -/***************************************************************************** - * End of msc01_pci.h - *****************************************************************************/ diff --git a/include/asm-mips64/mips-boards/piix4.h b/include/asm-mips64/mips-boards/piix4.h deleted file mode 100644 index 1136314a7e3..00000000000 --- a/include/asm-mips64/mips-boards/piix4.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Register definitions for Intel PIIX4 South Bridge Device. - * - */ - -#ifndef PIIX4_H -#define PIIX4_H - -/************************************************************************ - * IO register offsets - ************************************************************************/ -#define PIIX4_ICTLR1_ICW1 0x20 -#define PIIX4_ICTLR1_ICW2 0x21 -#define PIIX4_ICTLR1_ICW3 0x21 -#define PIIX4_ICTLR1_ICW4 0x21 -#define PIIX4_ICTLR2_ICW1 0xa0 -#define PIIX4_ICTLR2_ICW2 0xa1 -#define PIIX4_ICTLR2_ICW3 0xa1 -#define PIIX4_ICTLR2_ICW4 0xa1 -#define PIIX4_ICTLR1_OCW1 0x21 -#define PIIX4_ICTLR1_OCW2 0x20 -#define PIIX4_ICTLR1_OCW3 0x20 -#define PIIX4_ICTLR1_OCW4 0x20 -#define PIIX4_ICTLR2_OCW1 0xa1 -#define PIIX4_ICTLR2_OCW2 0xa0 -#define PIIX4_ICTLR2_OCW3 0xa0 -#define PIIX4_ICTLR2_OCW4 0xa0 - - -/************************************************************************ - * Register encodings. - ************************************************************************/ -#define PIIX4_OCW2_NSEOI (0x1 << 5) -#define PIIX4_OCW2_SEOI (0x3 << 5) -#define PIIX4_OCW2_RNSEOI (0x5 << 5) -#define PIIX4_OCW2_RAEOIS (0x4 << 5) -#define PIIX4_OCW2_RAEOIC (0x0 << 5) -#define PIIX4_OCW2_RSEOI (0x7 << 5) -#define PIIX4_OCW2_SP (0x6 << 5) -#define PIIX4_OCW2_NOP (0x2 << 5) - -#define PIIX4_OCW2_SEL (0x0 << 3) - -#define PIIX4_OCW2_ILS_0 0 -#define PIIX4_OCW2_ILS_1 1 -#define PIIX4_OCW2_ILS_2 2 -#define PIIX4_OCW2_ILS_3 3 -#define PIIX4_OCW2_ILS_4 4 -#define PIIX4_OCW2_ILS_5 5 -#define PIIX4_OCW2_ILS_6 6 -#define PIIX4_OCW2_ILS_7 7 -#define PIIX4_OCW2_ILS_8 0 -#define PIIX4_OCW2_ILS_9 1 -#define PIIX4_OCW2_ILS_10 2 -#define PIIX4_OCW2_ILS_11 3 -#define PIIX4_OCW2_ILS_12 4 -#define PIIX4_OCW2_ILS_13 5 -#define PIIX4_OCW2_ILS_14 6 -#define PIIX4_OCW2_ILS_15 7 - -#define PIIX4_OCW3_SEL (0x1 << 3) - -#define PIIX4_OCW3_IRR 0x2 -#define PIIX4_OCW3_ISR 0x3 - -#endif /* !(PIIX4_H) */ diff --git a/include/asm-mips64/mips-boards/saa9730_uart.h b/include/asm-mips64/mips-boards/saa9730_uart.h deleted file mode 100644 index c913143d58e..00000000000 --- a/include/asm-mips64/mips-boards/saa9730_uart.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Register definitions for the UART part of the Philips SAA9730 chip. - * - */ - -#ifndef SAA9730_UART_H -#define SAA9730_UART_H - -/* The SAA9730 UART register map, as seen via the PCI bus */ - -#define SAA9730_UART_REGS_ADDR 0x21800 - -struct uart_saa9730_regmap { - volatile unsigned char Thr_Rbr; - volatile unsigned char Ier; - volatile unsigned char Iir_Fcr; - volatile unsigned char Lcr; - volatile unsigned char Mcr; - volatile unsigned char Lsr; - volatile unsigned char Msr; - volatile unsigned char Scr; - volatile unsigned char BaudDivLsb; - volatile unsigned char BaudDivMsb; - volatile unsigned char Junk0; - volatile unsigned char Junk1; - volatile unsigned int Config; /* 0x2180c */ - volatile unsigned int TxStart; /* 0x21810 */ - volatile unsigned int TxLength; /* 0x21814 */ - volatile unsigned int TxCounter; /* 0x21818 */ - volatile unsigned int RxStart; /* 0x2181c */ - volatile unsigned int RxLength; /* 0x21820 */ - volatile unsigned int RxCounter; /* 0x21824 */ -}; -typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap; - -/* - * Only a subset of the UART control bits are defined here, - * enough to make the serial debug port work. - */ - -#define SAA9730_LCR_DATA8 0x03 - -#define SAA9730_MCR_DTR 0x01 -#define SAA9730_MCR_RTS 0x02 - -#define SAA9730_LSR_DR 0x01 -#define SAA9730_LSR_THRE 0x20 - -#endif /* !(SAA9730_UART_H) */ diff --git a/include/asm-mips64/mips-boards/sead.h b/include/asm-mips64/mips-boards/sead.h deleted file mode 100644 index 68c69de0b66..00000000000 --- a/include/asm-mips64/mips-boards/sead.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines of the SEAD board specific address-MAP, registers, etc. - * - */ -#ifndef _MIPS_SEAD_H -#define _MIPS_SEAD_H - -#include - -/* - * SEAD UART register base. - */ -#define SEAD_UART0_REGS_BASE (0x1f000800) -#define SEAD_BASE_BAUD ( 3686400 / 16 ) - -#endif /* !(_MIPS_SEAD_H) */ diff --git a/include/asm-mips64/mips-boards/seadint.h b/include/asm-mips64/mips-boards/seadint.h deleted file mode 100644 index 138ff0b2426..00000000000 --- a/include/asm-mips64/mips-boards/seadint.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines for the SEAD interrupt controller. - * - */ -#ifndef _MIPS_SEADINT_H -#define _MIPS_SEADINT_H - -/* Number of IRQ supported */ -#define SEADINT_UART0 0 -#define SEADINT_UART1 1 -#define SEADINT_END 2 - -extern void seadint_init(void); - -#endif /* !(_MIPS_SEADINT_H) */ diff --git a/include/asm-mips64/mipsregs.h b/include/asm-mips64/mipsregs.h deleted file mode 100644 index 62e7d85c393..00000000000 --- a/include/asm-mips64/mipsregs.h +++ /dev/null @@ -1,904 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - * Modified for further R[236]000 support by Paul M. Antoine, 1996. - * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2003 Maciej W. Rozycki - */ -#ifndef _ASM_MIPSREGS_H -#define _ASM_MIPSREGS_H - -#include -#include - -/* - * The following macros are especially useful for __asm__ - * inline assembler. - */ -#ifndef __STR -#define __STR(x) #x -#endif -#ifndef STR -#define STR(x) __STR(x) -#endif - -/* - * Configure language - */ -#ifdef __ASSEMBLY__ -#define _ULCAST_ -#else -#define _ULCAST_ (unsigned long) -#endif - -/* - * Coprocessor 0 register names - */ -#define CP0_INDEX $0 -#define CP0_RANDOM $1 -#define CP0_ENTRYLO0 $2 -#define CP0_ENTRYLO1 $3 -#define CP0_CONF $3 -#define CP0_CONTEXT $4 -#define CP0_PAGEMASK $5 -#define CP0_WIRED $6 -#define CP0_INFO $7 -#define CP0_BADVADDR $8 -#define CP0_COUNT $9 -#define CP0_ENTRYHI $10 -#define CP0_COMPARE $11 -#define CP0_STATUS $12 -#define CP0_CAUSE $13 -#define CP0_EPC $14 -#define CP0_PRID $15 -#define CP0_CONFIG $16 -#define CP0_LLADDR $17 -#define CP0_WATCHLO $18 -#define CP0_WATCHHI $19 -#define CP0_XCONTEXT $20 -#define CP0_FRAMEMASK $21 -#define CP0_DIAGNOSTIC $22 -#define CP0_DEBUG $23 -#define CP0_DEPC $24 -#define CP0_PERFORMANCE $25 -#define CP0_ECC $26 -#define CP0_CACHEERR $27 -#define CP0_TAGLO $28 -#define CP0_TAGHI $29 -#define CP0_ERROREPC $30 -#define CP0_DESAVE $31 - -/* - * R4640/R4650 cp0 register names. These registers are listed - * here only for completeness; without MMU these CPUs are not useable - * by Linux. A future ELKS port might take make Linux run on them - * though ... - */ -#define CP0_IBASE $0 -#define CP0_IBOUND $1 -#define CP0_DBASE $2 -#define CP0_DBOUND $3 -#define CP0_CALG $17 -#define CP0_IWATCH $18 -#define CP0_DWATCH $19 - -/* - * Coprocessor 0 Set 1 register names - */ -#define CP0_S1_DERRADDR0 $26 -#define CP0_S1_DERRADDR1 $27 -#define CP0_S1_INTCONTROL $20 - -/* - * TX39 Series - */ -#define CP0_TX39_CACHE $7 - -/* - * Coprocessor 1 (FPU) register names - */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 - -/* - * FPU Status Register Values - */ -/* - * Status Register Values - */ - -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ - -/* - * X the exception cause indicator - * E the exception enable - * S the sticky/flag bit -*/ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 - -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 - -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 - -/* rounding mode */ -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ - - -/* - * Values for PageMask register - */ -#ifdef CONFIG_CPU_VR41XX - -/* Why doesn't stupidity hurt ... */ - -#define PM_1K 0x00000000 -#define PM_4K 0x00001800 -#define PM_16K 0x00007800 -#define PM_64K 0x0001f800 -#define PM_256K 0x0007f800 - -#else - -#define PM_4K 0x00000000 -#define PM_16K 0x00006000 -#define PM_64K 0x0001e000 -#define PM_256K 0x0007e000 -#define PM_1M 0x001fe000 -#define PM_4M 0x007fe000 -#define PM_16M 0x01ffe000 -#define PM_64M 0x07ffe000 -#define PM_256M 0x1fffe000 - -#endif - -/* - * Values used for computation of new tlb entries - */ -#define PL_4K 12 -#define PL_16K 14 -#define PL_64K 16 -#define PL_256K 18 -#define PL_1M 20 -#define PL_4M 22 -#define PL_16M 24 -#define PL_64M 26 -#define PL_256M 28 - -/* - * R4x00 interrupt enable / cause bits - */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) -#define IE_IRQ0 (_ULCAST_(1) << 10) -#define IE_IRQ1 (_ULCAST_(1) << 11) -#define IE_IRQ2 (_ULCAST_(1) << 12) -#define IE_IRQ3 (_ULCAST_(1) << 13) -#define IE_IRQ4 (_ULCAST_(1) << 14) -#define IE_IRQ5 (_ULCAST_(1) << 15) - -/* - * R4x00 interrupt cause bits - */ -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) -#define C_IRQ0 (_ULCAST_(1) << 10) -#define C_IRQ1 (_ULCAST_(1) << 11) -#define C_IRQ2 (_ULCAST_(1) << 12) -#define C_IRQ3 (_ULCAST_(1) << 13) -#define C_IRQ4 (_ULCAST_(1) << 14) -#define C_IRQ5 (_ULCAST_(1) << 15) - -/* - * Bitfields in the R4xx0 cp0 status register - */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_KSU 0x00000018 -# define KSU_USER 0x00000010 -# define KSU_SUPERVISOR 0x00000008 -# define KSU_KERNEL 0x00000000 -#define ST0_UX 0x00000020 -#define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 -#define ST0_DE 0x00010000 -#define ST0_CE 0x00020000 - -/* - * Bitfields in the R[23]000 cp0 status register. - */ -#define ST0_IEC 0x00000001 -#define ST0_KUC 0x00000002 -#define ST0_IEP 0x00000004 -#define ST0_KUP 0x00000008 -#define ST0_IEO 0x00000010 -#define ST0_KUO 0x00000020 -/* bits 6 & 7 are reserved on R[23]000 */ -#define ST0_ISC 0x00010000 -#define ST0_SWC 0x00020000 -#define ST0_CM 0x00080000 - -/* - * Bits specific to the R4640/R4650 - */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) - -/* - * Bitfields in the TX39 family CP0 Configuration Register 3 - */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 - -/* - * Status register bits available in all MIPS CPUs. - */ -#define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) -#define ST0_CH 0x00040000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_FR 0x04000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#define ST0_XX 0x80000000 /* MIPS IV naming */ - -/* - * Bitfields and bit numbers in the coprocessor 0 cause register. - * - * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. - */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) - -/* - * Bits in the coprocessor 0 config register. - */ -/* Generic bits. */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) - -/* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) - -/* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) - -/* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) - -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) - -/* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) - -/* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) - -/* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) - -/* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) - -/* - * R10000 performance counter definitions. - * - * FIXME: The R10000 performance counter opens a nice way to implement CPU - * time accounting with a precission of one cycle. I don't have - * R10000 silicon but just a manual, so ... - */ - -/* - * Events counted by counter #0 - */ -#define CE0_CYCLES 0 -#define CE0_INSN_ISSUED 1 -#define CE0_LPSC_ISSUED 2 -#define CE0_S_ISSUED 3 -#define CE0_SC_ISSUED 4 -#define CE0_SC_FAILED 5 -#define CE0_BRANCH_DECODED 6 -#define CE0_QW_WB_SECONDARY 7 -#define CE0_CORRECTED_ECC_ERRORS 8 -#define CE0_ICACHE_MISSES 9 -#define CE0_SCACHE_I_MISSES 10 -#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 -#define CE0_EXT_INTERVENTIONS_REQ 12 -#define CE0_EXT_INVALIDATE_REQ 13 -#define CE0_VIRTUAL_COHERENCY_COND 14 -#define CE0_INSN_GRADUATED 15 - -/* - * Events counted by counter #1 - */ -#define CE1_CYCLES 0 -#define CE1_INSN_GRADUATED 1 -#define CE1_LPSC_GRADUATED 2 -#define CE1_S_GRADUATED 3 -#define CE1_SC_GRADUATED 4 -#define CE1_FP_INSN_GRADUATED 5 -#define CE1_QW_WB_PRIMARY 6 -#define CE1_TLB_REFILL 7 -#define CE1_BRANCH_MISSPREDICTED 8 -#define CE1_DCACHE_MISS 9 -#define CE1_SCACHE_D_MISSES 10 -#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 -#define CE1_EXT_INTERVENTION_HITS 12 -#define CE1_EXT_INVALIDATE_REQ 13 -#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 -#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 - -/* - * These flags define in which privilege mode the counters count events - */ -#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ -#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ -#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ -#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ - -#ifndef __ASSEMBLY__ - -/* - * Functions to access the r10k performance counter and control registers - */ -#define read_r10k_perf_cntr(counter) \ -({ unsigned int __res; \ - __asm__ __volatile__( \ - "mfpc\t%0, "STR(counter) \ - : "=r" (__res)); \ - __res;}) - -#define write_r10k_perf_cntr(counter,val) \ - __asm__ __volatile__( \ - "mtpc\t%0, "STR(counter) \ - : : "r" (val)); - -#define read_r10k_perf_cntl(counter) \ -({ unsigned int __res; \ - __asm__ __volatile__( \ - "mfps\t%0, "STR(counter) \ - : "=r" (__res)); \ - __res;}) - -#define write_r10k_perf_cntl(counter,val) \ - __asm__ __volatile__( \ - "mtps\t%0, "STR(counter) \ - : : "r" (val)); - -/* - * Macros to access the system control coprocessor - */ - -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __read_64bit_c0_register(source, sel) \ -({ unsigned long __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ -} while (0) - -#define __write_64bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ -} while (0) - -#define __read_ulong_c0_register(reg, sel) \ - ((sizeof(unsigned long) == 4) ? \ - __read_32bit_c0_register(reg, sel) : \ - __read_64bit_c0_register(reg, sel)) - -#define __write_ulong_c0_register(reg, sel, val) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_32bit_c0_register(reg, sel, val); \ - else \ - __write_64bit_c0_register(reg, sel, val); \ -} while (0) - -/* - * These versions are only needed for systems with more than 38 bits of - * physical address space running the 32-bit kernel. That's none atm :-) - */ -#define __read_64bit_c0_split(source, sel) \ -({ \ - unsigned long long val; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - local_irq_restore(flags); \ - \ - val; \ -}) - -#define __write_64bit_c0_split(source, sel, val) \ -do { \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - local_irq_restore(flags); \ -} while (0) - -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) - -#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) - -#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) - -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) - -#define read_c0_context() __read_ulong_c0_register($4, 0) -#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) - -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) - -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) - -#define read_c0_info() __read_32bit_c0_register($7, 0) - -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) - -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) - -#define read_c0_entryhi() __read_ulong_c0_register($10, 0) -#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) - -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) - -#define read_c0_status() __read_32bit_c0_register($12, 0) -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) - -#define read_c0_epc() __read_ulong_c0_register($14, 0) -#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) - -#define read_c0_prid() __read_32bit_c0_register($15, 0) - -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) - -/* - * The WatchLo register. There may be upto 8 of them. - */ -#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) -#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) -#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) -#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) -#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) -#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) -#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) -#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) -#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) -#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) -#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) -#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) -#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) -#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) -#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) -#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) - -/* - * The WatchHi register. There may be upto 8 of them. - */ -#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) -#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) -#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) -#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) -#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) -#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) -#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) -#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) - -#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) -#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) -#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) -#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) -#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) -#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) -#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) -#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) - -#define read_c0_xcontext() __read_ulong_c0_register($20, 0) -#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) - -#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) -#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) - -#define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) - -#define read_c0_debug() __read_32bit_c0_register($23, 0) -#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) - -#define read_c0_depc() __read_ulong_c0_register($24, 0) -#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) - -#define read_c0_ecc() __read_32bit_c0_register($26, 0) -#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) - -#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) - -#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) - -#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) - -#define read_c0_taglo() __read_32bit_c0_register($28, 0) -#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) - -#define read_c0_taghi() __read_32bit_c0_register($29, 0) -#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) - -#define read_c0_errorepc() __read_ulong_c0_register($30, 0) -#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) - -/* - * Macros to access the floating point coprocessor control registers - */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) - -/* TLB operations. */ -static inline void tlb_probe(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbp\n\t" - ".set reorder"); -} - -static inline void tlb_read(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbr\n\t" - ".set reorder"); -} - -static inline void tlb_write_indexed(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwi\n\t" - ".set reorder"); -} - -static inline void tlb_write_random(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwr\n\t" - ".set reorder"); -} - -/* - * Manipulate bits in a c0 register. - */ -#define __BUILD_SET_C0(name,register) \ -static inline unsigned int \ -set_c0_##name(unsigned int set) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ - \ - return res; \ -} - -__BUILD_SET_C0(status,CP0_STATUS) -__BUILD_SET_C0(cause,CP0_CAUSE) -__BUILD_SET_C0(config,CP0_CONFIG) - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_MIPSREGS_H */ diff --git a/include/asm-mips64/mman.h b/include/asm-mips64/mman.h deleted file mode 100644 index 54b7fb1cb8f..00000000000 --- a/include/asm-mips64/mman.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999, 2002 by Ralf Baechle - */ -#ifndef _ASM_MMAN_H -#define _ASM_MMAN_H - -/* - * Protections are chosen from these bits, OR'd together. The - * implementation does not necessarily support PROT_EXEC or PROT_WRITE - * without PROT_READ. The only guarantees are that no writing will be - * allowed without PROT_WRITE and no access will be allowed for PROT_NONE. - */ -#define PROT_NONE 0x00 /* page can not be accessed */ -#define PROT_READ 0x01 /* page can be read */ -#define PROT_WRITE 0x02 /* page can be written */ -#define PROT_EXEC 0x04 /* page can be executed */ -/* 0x08 reserved for PROT_EXEC_NOFLUSH */ -#define PROT_SEM 0x10 /* page may be used for atomic ops */ - -/* - * Flags for mmap - */ -#define MAP_SHARED 0x001 /* Share changes */ -#define MAP_PRIVATE 0x002 /* Changes are private */ -#define MAP_TYPE 0x00f /* Mask for type of mapping */ -#define MAP_FIXED 0x010 /* Interpret addr exactly */ - -/* not used by linux, but here to make sure we don't clash with ABI defines */ -#define MAP_RENAME 0x020 /* Assign page to file */ -#define MAP_AUTOGROW 0x040 /* File may grow by writing */ -#define MAP_LOCAL 0x080 /* Copy on fork/sproc */ -#define MAP_AUTORSRV 0x100 /* Logical swap reserved on demand */ - -/* These are linux-specific */ -#define MAP_NORESERVE 0x0400 /* don't check for reservations */ -#define MAP_ANONYMOUS 0x0800 /* don't use a file */ -#define MAP_GROWSDOWN 0x1000 /* stack-like segment */ -#define MAP_DENYWRITE 0x2000 /* ETXTBSY */ -#define MAP_EXECUTABLE 0x4000 /* mark it as an executable */ -#define MAP_LOCKED 0x8000 /* pages are locked */ -#define MAP_POPULATE 0x10000 /* populate (prefault) pagetables */ -#define MAP_NONBLOCK 0x20000 /* do not block on IO */ - -/* - * Flags for msync - */ -#define MS_ASYNC 0x0001 /* sync memory asynchronously */ -#define MS_INVALIDATE 0x0002 /* invalidate mappings & caches */ -#define MS_SYNC 0x0004 /* synchronous memory sync */ - -/* - * Flags for mlockall - */ -#define MCL_CURRENT 1 /* lock all current mappings */ -#define MCL_FUTURE 2 /* lock all future mappings */ - -#define MADV_NORMAL 0x0 /* default page-in behavior */ -#define MADV_RANDOM 0x1 /* page-in minimum required */ -#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */ -#define MADV_WILLNEED 0x3 /* pre-fault pages */ -#define MADV_DONTNEED 0x4 /* discard these pages */ - -/* compatibility flags */ -#define MAP_ANON MAP_ANONYMOUS -#define MAP_FILE 0 - -#endif /* _ASM_MMAN_H */ diff --git a/include/asm-mips64/mmu.h b/include/asm-mips64/mmu.h deleted file mode 100644 index 4063edd7962..00000000000 --- a/include/asm-mips64/mmu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_MMU_H -#define __ASM_MMU_H - -typedef unsigned long mm_context_t[NR_CPUS]; - -#endif /* __ASM_MMU_H */ diff --git a/include/asm-mips64/mmu_context.h b/include/asm-mips64/mmu_context.h deleted file mode 100644 index 05cd8dba96a..00000000000 --- a/include/asm-mips64/mmu_context.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Switch a MMU context. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_MMU_CONTEXT_H -#define _ASM_MMU_CONTEXT_H - -#include -#include -#include -#include -#include -#include - -/* - * For the fast tlb miss handlers, we currently keep a per cpu array - * of pointers to the current pgd for each processor. Also, the proc. - * id is stuffed into the context register. This should be changed to - * use the processor id via current->processor, where current is stored - * in watchhi/lo. The context register should be used to contiguously - * map the page tables. - */ -#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ - pgd_current[smp_processor_id()] = (unsigned long)(pgd) -#define TLBMISS_HANDLER_SETUP() \ - write_c0_context(((long)(&pgd_current[smp_processor_id()])) << 23); \ - TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) -extern unsigned long pgd_current[]; - -#define ASID_INC 0x1 -#define ASID_MASK 0xff - -#define cpu_context(cpu, mm) ((mm)->context[cpu]) -#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) -#define asid_cache(cpu) (cpu_data[cpu].asid_cache) - -static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - -/* - * All unused by hardware upper bits will be considered - * as a software asid extension. - */ -#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) -#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) - -static inline void -get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) -{ - unsigned long asid = asid_cache(cpu); - - if (! ((asid += ASID_INC) & ASID_MASK) ) { -#ifdef CONFIG_VTAG_ICACHE - flush_icache_all(); -#endif - local_flush_tlb_all(); /* start new asid cycle */ - if (!asid) /* fix version if needed */ - asid = ASID_FIRST_VERSION; - } - cpu_context(cpu, mm) = asid_cache(cpu) = asid; -} - -/* - * Initialize the context related info for a new mm_struct - * instance. - */ -static inline int -init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - int i; - - for (i = 0; i < num_online_cpus(); i++) - cpu_context(i, mm) = 0; - - return 0; -} - -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - int cpu = smp_processor_id(); - unsigned long flags; - - local_irq_save(flags); - - /* Check if our ASID is of an older version and thus invalid */ - if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) - get_new_mmu_context(next, cpu); - - write_c0_entryhi(cpu_context(cpu, next)); - TLBMISS_HANDLER_SETUP_PGD(next->pgd); - - /* - * Mark current->active_mm as not "active" anymore. - * We don't want to mislead possible IPI tlb flush routines. - */ - clear_bit(cpu, &prev->cpu_vm_mask); - set_bit(cpu, &next->cpu_vm_mask); - - local_irq_restore(flags); -} - -/* - * Destroy context related info for an mm_struct that is about - * to be put to rest. - */ -static inline void destroy_context(struct mm_struct *mm) -{ -} - -#define deactivate_mm(tsk,mm) do { } while (0) - -/* - * After we have set current->mm to a new value, this activates - * the context for the new mm so we see the new mappings. - */ -static inline void -activate_mm(struct mm_struct *prev, struct mm_struct *next) -{ - unsigned long flags; - int cpu = smp_processor_id(); - - local_irq_save(flags); - - /* Unconditionally get a new ASID. */ - get_new_mmu_context(next, cpu); - - write_c0_entryhi(cpu_context(cpu, next)); - TLBMISS_HANDLER_SETUP_PGD(next->pgd); - - /* mark mmu ownership change */ - clear_bit(cpu, &prev->cpu_vm_mask); - set_bit(cpu, &next->cpu_vm_mask); - - local_irq_restore(flags); -} - -/* - * If mm is currently active_mm, we can't really drop it. Instead, - * we will get a new one for it. - */ -static inline void -drop_mmu_context(struct mm_struct *mm, unsigned cpu) -{ - unsigned long flags; - - local_irq_save(flags); - - if (test_bit(cpu, &mm->cpu_vm_mask)) { - get_new_mmu_context(mm, cpu); - write_c0_entryhi(cpu_asid(cpu, mm)); - } else { - /* will get a new context next time */ - cpu_context(cpu, mm) = 0; - } - - local_irq_restore(flags); -} - -#endif /* _ASM_MMU_CONTEXT_H */ diff --git a/include/asm-mips64/module.h b/include/asm-mips64/module.h deleted file mode 100644 index 39bcec8134e..00000000000 --- a/include/asm-mips64/module.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _ASM_MODULE_H -#define _ASM_MODULE_H - -struct mod_arch_specific { - /* Data Bus Error exception tables */ - const struct exception_table_entry *dbe_table_start; - const struct exception_table_entry *dbe_table_end; -}; - -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr - -#endif /* _ASM_MODULE_H */ diff --git a/include/asm-mips64/msgbuf.h b/include/asm-mips64/msgbuf.h deleted file mode 100644 index 1d4d90fb4a5..00000000000 --- a/include/asm-mips64/msgbuf.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef _ASM_MSGBUF_H -#define _ASM_MSGBUF_H - -/* - * The msqid64_ds structure for alpha architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 2 miscellaneous 64-bit values - */ - -struct msqid64_ds { - struct ipc64_perm msg_perm; - __kernel_time_t msg_stime; /* last msgsnd time */ - unsigned long __unused1; - __kernel_time_t msg_rtime; /* last msgrcv time */ - unsigned long __unused2; - __kernel_time_t msg_ctime; /* last change time */ - unsigned long __unused3; - unsigned long msg_cbytes; /* current number of bytes on queue */ - unsigned long msg_qnum; /* number of messages in queue */ - unsigned long msg_qbytes; /* max number of bytes on queue */ - __kernel_pid_t msg_lspid; /* pid of last msgsnd */ - __kernel_pid_t msg_lrpid; /* last receive pid */ - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* _ASM_MSGBUF_H */ diff --git a/include/asm-mips64/mv64340.h b/include/asm-mips64/mv64340.h deleted file mode 100644 index d7d89bf0f6d..00000000000 --- a/include/asm-mips64/mv64340.h +++ /dev/null @@ -1,1037 +0,0 @@ -/******************************************************************************* -* mv64340.h - MV-64340 Internal registers definition file. -* -* Copyright 2002 Momentum Computer, Inc. -* Copyright 2002 GALILEO TECHNOLOGY, LTD. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -*******************************************************************************/ - -#ifndef __MV64340_H__ -#define __MV64340_H__ - -#include - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64340_CS_0_BASE_ADDR 0x008 -#define MV64340_CS_0_SIZE 0x010 -#define MV64340_CS_1_BASE_ADDR 0x208 -#define MV64340_CS_1_SIZE 0x210 -#define MV64340_CS_2_BASE_ADDR 0x018 -#define MV64340_CS_2_SIZE 0x020 -#define MV64340_CS_3_BASE_ADDR 0x218 -#define MV64340_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64340_DEV_CS0_BASE_ADDR 0x028 -#define MV64340_DEV_CS0_SIZE 0x030 -#define MV64340_DEV_CS1_BASE_ADDR 0x228 -#define MV64340_DEV_CS1_SIZE 0x230 -#define MV64340_DEV_CS2_BASE_ADDR 0x248 -#define MV64340_DEV_CS2_SIZE 0x250 -#define MV64340_DEV_CS3_BASE_ADDR 0x038 -#define MV64340_DEV_CS3_SIZE 0x040 -#define MV64340_BOOTCS_BASE_ADDR 0x238 -#define MV64340_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64340_PCI_0_IO_BASE_ADDR 0x048 -#define MV64340_PCI_0_IO_SIZE 0x050 -#define MV64340_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64340_PCI_0_MEMORY0_SIZE 0x060 -#define MV64340_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64340_PCI_0_MEMORY1_SIZE 0x088 -#define MV64340_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64340_PCI_0_MEMORY2_SIZE 0x260 -#define MV64340_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64340_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64340_PCI_1_IO_BASE_ADDR 0x090 -#define MV64340_PCI_1_IO_SIZE 0x098 -#define MV64340_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64340_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64340_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64340_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64340_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64340_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64340_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64340_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64340_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64340_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64340_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64340_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64340_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64340_CPU_CONFIG 0x000 -#define MV64340_CPU_MODE 0x120 -#define MV64340_CPU_MASTER_CONTROL 0x160 -#define MV64340_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64340_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64340_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64340_SMP_WHO_AM_I 0x200 -#define MV64340_SMP_CPU0_DOORBELL 0x214 -#define MV64340_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64340_SMP_CPU1_DOORBELL 0x224 -#define MV64340_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64340_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64340_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64340_SMP_SEMAPHOR0 0x244 -#define MV64340_SMP_SEMAPHOR1 0x24c -#define MV64340_SMP_SEMAPHOR2 0x254 -#define MV64340_SMP_SEMAPHOR3 0x25c -#define MV64340_SMP_SEMAPHOR4 0x264 -#define MV64340_SMP_SEMAPHOR5 0x26c -#define MV64340_SMP_SEMAPHOR6 0x274 -#define MV64340_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64340_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64340_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64340_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64340_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64340_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64340_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64340_CPU_ERROR_ADDR_LOW 0x070 -#define MV64340_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64340_CPU_ERROR_DATA_LOW 0x128 -#define MV64340_CPU_ERROR_DATA_HIGH 0x130 -#define MV64340_CPU_ERROR_PARITY 0x138 -#define MV64340_CPU_ERROR_CAUSE 0x140 -#define MV64340_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64340_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64340_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64340_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64340_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64340_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64340_SRAM_CONFIG 0x380 -#define MV64340_SRAM_TEST_MODE 0X3F4 -#define MV64340_SRAM_ERROR_CAUSE 0x388 -#define MV64340_SRAM_ERROR_ADDR 0x390 -#define MV64340_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64340_SRAM_ERROR_DATA_LOW 0x398 -#define MV64340_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64340_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64340_SDRAM_CONFIG 0x1400 -#define MV64340_D_UNIT_CONTROL_LOW 0x1404 -#define MV64340_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64340_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64340_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64340_SDRAM_ADDR_CONTROL 0x1410 -#define MV64340_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64340_SDRAM_OPERATION 0x1418 -#define MV64340_SDRAM_MODE 0x141c -#define MV64340_EXTENDED_DRAM_MODE 0x1420 -#define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64340_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64340_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64340_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64340_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64340_SDRAM_ERROR_ADDR 0x1450 -#define MV64340_SDRAM_RECEIVED_ECC 0x1448 -#define MV64340_SDRAM_CALCULATED_ECC 0x144c -#define MV64340_SDRAM_ECC_CONTROL 0x1454 -#define MV64340_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64340_DFCDL_CONFIG0 0x1480 -#define MV64340_DFCDL_CONFIG1 0x1484 -#define MV64340_DLL_WRITE 0x1488 -#define MV64340_DLL_READ 0x148c -#define MV64340_SRAM_ADDR 0x1490 -#define MV64340_SRAM_DATA0 0x1494 -#define MV64340_SRAM_DATA1 0x1498 -#define MV64340_SRAM_DATA2 0x149c -#define MV64340_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64340_DUNIT_DEBUG_LOW 0x1460 -#define MV64340_DUNIT_DEBUG_HIGH 0x1464 -#define MV64340_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64340_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64340_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64340_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64340_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64340_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64340_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64340_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64340_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64340_DEVICE_ERROR_ADDR 0x4d8 -#define MV64340_DEVICE_ERROR_DATA 0x4dc -#define MV64340_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64340_DEVICE_DEBUG_LOW 0x4e4 -#define MV64340_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64340_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64340_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64340_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64340_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64340_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64340_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64340_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64340_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64340_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64340_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64340_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64340_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64340_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64340_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64340_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64340_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64340_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64340_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64340_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64340_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64340_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64340_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64340_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64340_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64340_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64340_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64340_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64340_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64340_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64340_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64340_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64340_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64340_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64340_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64340_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64340_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64340_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64340_PCI_0_COMMAND 0xc00 -#define MV64340_PCI_1_COMMAND 0xc80 -#define MV64340_PCI_0_MODE 0xd00 -#define MV64340_PCI_1_MODE 0xd80 -#define MV64340_PCI_0_RETRY 0xc04 -#define MV64340_PCI_1_RETRY 0xc84 -#define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64340_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64340_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64340_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64340_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64340_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64340_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64340_PCI_0_P2P_CONFIG 0x1d14 -#define MV64340_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64340_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64340_PCI_1_CONFIG_ADDR 0xc78 -#define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64340_PCI_0_SERR_MASK 0xc28 -#define MV64340_PCI_1_SERR_MASK 0xca8 -#define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64340_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64340_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64340_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64340_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64340_PCI_0_ERROR_MASK 0x1d5c -#define MV64340_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64340_PCI_0_MMASK 0X1D24 -#define MV64340_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64340_PCI_STATUS_AND_COMMAND 0x004 -#define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64340_PCI_VPD_ADDR 0x048 -#define MV64340_PCI_VPD_DATA 0x04c -#define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64340_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64340_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64340_PCI_X_COMMAND 0x060 -#define MV64340_PCI_X_STATUS 0x064 -#define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64340_ETH_PHY_ADDR_REG 0x2000 -#define MV64340_ETH_SMI_REG 0x2004 -#define MV64340_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64340_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64340_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64340_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64340_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64340_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64340_ETH_BAR_0 0x2200 -#define MV64340_ETH_BAR_1 0x2208 -#define MV64340_ETH_BAR_2 0x2210 -#define MV64340_ETH_BAR_3 0x2218 -#define MV64340_ETH_BAR_4 0x2220 -#define MV64340_ETH_BAR_5 0x2228 -#define MV64340_ETH_SIZE_REG_0 0x2204 -#define MV64340_ETH_SIZE_REG_1 0x220c -#define MV64340_ETH_SIZE_REG_2 0x2214 -#define MV64340_ETH_SIZE_REG_3 0x221c -#define MV64340_ETH_SIZE_REG_4 0x2224 -#define MV64340_ETH_SIZE_REG_5 0x222c -#define MV64340_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64340_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64340_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64340_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64340_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64340_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64340_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64340_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64340_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64340_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64340_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64340_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64340_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64340_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64340_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64340_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64340_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64340_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64340_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64340_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64340_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64340_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64340_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64340_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64340_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64340_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64340_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64340_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64340_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64340_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64340_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64340_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64340_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64340_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64340_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64340_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64340_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64340_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64340_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64340_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64340_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64340_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64340_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64340_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64340_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64340_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64340_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64340_CUNIT_SIZE0 0xf204 -#define MV64340_CUNIT_SIZE1 0xf20c -#define MV64340_CUNIT_SIZE2 0xf214 -#define MV64340_CUNIT_SIZE3 0xf21c -#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64340_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64340_CUNIT_CONFIG_REG 0xb40c -#define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64340_CUNIT_DEBUG_LOW 0xf340 -#define MV64340_CUNIT_DEBUG_HIGH 0xf344 -#define MV64340_CUNIT_MMASK 0xf380 - - /* MPSCs Clocks Routing Registers */ - -#define MV64340_MPSC_ROUTING_REG 0xb400 -#define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64340_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64340_SDMA_CAUSE_REG 0xb800 -#define MV64340_SDMA_MASK_REG 0xb880 - -/* BRG Interrupts */ - -#define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3)) -#define MV64340_BRG_CAUSE_REG 0xb834 -#define MV64340_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64340_DMA_CHANNEL0_CONTROL 0x840 -#define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64340_DMA_CHANNEL1_CONTROL 0x844 -#define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64340_DMA_CHANNEL2_CONTROL 0x848 -#define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64340_DMA_CHANNEL3_CONTROL 0x84C -#define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64340_DMA_BASE_ADDR_REG0 0xa00 -#define MV64340_DMA_BASE_ADDR_REG1 0xa08 -#define MV64340_DMA_BASE_ADDR_REG2 0xa10 -#define MV64340_DMA_BASE_ADDR_REG3 0xa18 -#define MV64340_DMA_BASE_ADDR_REG4 0xa20 -#define MV64340_DMA_BASE_ADDR_REG5 0xa28 -#define MV64340_DMA_BASE_ADDR_REG6 0xa30 -#define MV64340_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64340_DMA_SIZE_REG0 0xa04 -#define MV64340_DMA_SIZE_REG1 0xa0c -#define MV64340_DMA_SIZE_REG2 0xa14 -#define MV64340_DMA_SIZE_REG3 0xa1c -#define MV64340_DMA_SIZE_REG4 0xa24 -#define MV64340_DMA_SIZE_REG5 0xa2c -#define MV64340_DMA_SIZE_REG6 0xa34 -#define MV64340_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64340_DMA_ARBITER_CONTROL 0x860 -#define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64340_DMA_ERROR_ADDR 0x8c8 -#define MV64340_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64340_DMA_DEBUG_LOW 0x8e0 -#define MV64340_DMA_DEBUG_HIGH 0x8e4 -#define MV64340_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64340_TIMER_COUNTER0 0x850 -#define MV64340_TIMER_COUNTER1 0x854 -#define MV64340_TIMER_COUNTER2 0x858 -#define MV64340_TIMER_COUNTER3 0x85C -#define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64340_WATCHDOG_CONFIG_REG 0xb410 -#define MV64340_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64340_I2C_SLAVE_ADDR 0xc000 -#define MV64340_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64340_I2C_DATA 0xc004 -#define MV64340_I2C_CONTROL 0xc008 -#define MV64340_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64340_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64340_GPP_IO_CONTROL 0xf100 -#define MV64340_GPP_LEVEL_CONTROL 0xf110 -#define MV64340_GPP_VALUE 0xf104 -#define MV64340_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64340_GPP_INTERRUPT_MASK0 0xf10c -#define MV64340_GPP_INTERRUPT_MASK1 0xf114 -#define MV64340_GPP_VALUE_SET 0xf118 -#define MV64340_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64340_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64340_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64340_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64340_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64340_MPP_CONTROL0 0xf000 -#define MV64340_MPP_CONTROL1 0xf004 -#define MV64340_MPP_CONTROL2 0xf008 -#define MV64340_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64340_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64340_SERIAL_INIT_CONTROL 0xf328 -#define MV64340_SERIAL_INIT_STATUS 0xf32c - -#endif diff --git a/include/asm-mips64/mv64340_dep.h b/include/asm-mips64/mv64340_dep.h deleted file mode 100644 index f550fdfba7f..00000000000 --- a/include/asm-mips64/mv64340_dep.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm - * - * include/asm-mips/mv64340-dep.h - * Board-dependent definitions for MV-64340 chip. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __MV64340_DEP_H__ -#define __MV64340_DEP_H__ - -#include /* for KSEG1ADDR() */ -#include /* for cpu_to_le32() */ - -extern unsigned long mv64340_base; - -#define MV64340_BASE (mv64340_base) - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. - */ - -#define MV_WRITE(ofs, data) \ - *(volatile u32 *)(MV64340_BASE+(ofs)) = cpu_to_le32(data) -#define MV_READ(ofs, data) \ - *(data) = le32_to_cpu(*(volatile u32 *)(MV64340_BASE+(ofs))) -#define MV_READ_DATA(ofs) \ - le32_to_cpu(*(volatile u32 *)(MV64340_BASE+(ofs))) - -#define MV_WRITE_16(ofs, data) \ - *(volatile u16 *)(MV64340_BASE+(ofs)) = cpu_to_le16(data) -#define MV_READ_16(ofs, data) \ - *(data) = le16_to_cpu(*(volatile u16 *)(MV64340_BASE+(ofs))) - -#define MV_WRITE_8(ofs, data) \ - *(volatile u8 *)(MV64340_BASE+(ofs)) = data -#define MV_READ_8(ofs, data) \ - *(data) = *(volatile u8 *)(MV64340_BASE+(ofs)) - -#define MV_SET_REG_BITS(ofs,bits) \ - (*((volatile u32 *)(MV64340_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits)) -#define MV_RESET_REG_BITS(ofs,bits) \ - (*((volatile u32 *)(MV64340_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits)) - -#endif diff --git a/include/asm-mips64/namei.h b/include/asm-mips64/namei.h deleted file mode 100644 index aeca14fde5e..00000000000 --- a/include/asm-mips64/namei.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef _ASM_NAMEI_H -#define _ASM_NAMEI_H - -/* - * This dummy routine maybe changed to something useful - * for /usr/gnemul/ emulation stuff. - * Look at asm-sparc/namei.h for details. - */ - -#define __emul_prefix() NULL - -#endif /* _ASM_NAMEI_H */ diff --git a/include/asm-mips64/ng1.h b/include/asm-mips64/ng1.h deleted file mode 100644 index 8c980fed63a..00000000000 --- a/include/asm-mips64/ng1.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * SGI/Newport video card ioctl definitions - */ -#ifndef _ASM_NG1_H -#define _ASM_NG1_H - -typedef struct { - int flags; - __u16 w, h; - __u16 fields_sec; -} ng1_vof_info_t; - -struct ng1_info { - struct gfx_info gfx_info; - __u8 boardrev; - __u8 rex3rev; - __u8 vc2rev; - __u8 monitortype; - __u8 videoinstalled; - __u8 mcrev; - __u8 bitplanes; - __u8 xmap9rev; - __u8 cmaprev; - ng1_vof_info_t ng1_vof_info; - __u8 bt445rev; - __u8 paneltype; -}; - -#define GFX_NAME_NEWPORT "NG1" - -/* ioctls */ -#define NG1_SET_CURSOR_HOTSPOT 21001 -struct ng1_set_cursor_hotspot { - unsigned short xhot; - unsigned short yhot; -}; - -#define NG1_SETDISPLAYMODE 21006 -struct ng1_setdisplaymode_args { - int wid; - unsigned int mode; -}; - -#define NG1_SETGAMMARAMP0 21007 -struct ng1_setgammaramp_args { - unsigned char red [256]; - unsigned char green [256]; - unsigned char blue [256]; -}; - -#endif /* _ASM_NG1_H */ diff --git a/include/asm-mips64/paccess.h b/include/asm-mips64/paccess.h deleted file mode 100644 index 1a0b4a0ec96..00000000000 --- a/include/asm-mips64/paccess.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * - * Protected memory access. Used for everything that might take revenge - * by sending a DBE error like accessing possibly non-existant memory or - * devices. - */ -#ifndef _ASM_PACCESS_H -#define _ASM_PACCESS_H - -#include - -extern asmlinkage void handle_ibe(void); -extern asmlinkage void handle_dbe(void); - -#define put_dbe(x,ptr) __put_dbe((x),(ptr),sizeof(*(ptr))) -#define get_dbe(x,ptr) __get_dbe((x),(ptr),sizeof(*(ptr))) - -struct __large_pstruct { unsigned long buf[100]; }; -#define __mp(x) (*(struct __large_pstruct *)(x)) - -#define __get_dbe(x,ptr,size) ({ \ -long __gu_err; \ -__typeof(*(ptr)) __gu_val; \ -long __gu_addr; \ -__asm__("":"=r" (__gu_val)); \ -__gu_addr = (long) (ptr); \ -__asm__("":"=r" (__gu_err)); \ -switch (size) { \ -case 1: __get_dbe_asm("lb"); break; \ -case 2: __get_dbe_asm("lh"); break; \ -case 4: __get_dbe_asm("lw"); break; \ -case 8: __get_dbe_asm("ld"); break; \ -default: __get_dbe_unknown(); break; \ -} x = (__typeof__(*(ptr))) __gu_val; __gu_err; }) - -#define __get_dbe_asm(insn) \ -({ \ -__asm__ __volatile__( \ - "1:\t" insn "\t%1,%2\n\t" \ - "move\t%0,$0\n" \ - "2:\n\t" \ - ".section\t.fixup,\"ax\"\n" \ - "3:\tli\t%0,%3\n\t" \ - "move\t%1,$0\n\t" \ - "j\t2b\n\t" \ - ".previous\n\t" \ - ".section\t__dbe_table,\"a\"\n\t" \ - ".dword\t1b,3b\n\t" \ - ".previous" \ - :"=r" (__gu_err), "=r" (__gu_val) \ - :"o" (__mp(__gu_addr)), "i" (-EFAULT)); }) - -extern void __get_dbe_unknown(void); - -#define __put_dbe(x,ptr,size) ({ \ -long __pu_err; \ -__typeof__(*(ptr)) __pu_val; \ -long __pu_addr; \ -__pu_val = (x); \ -__pu_addr = (long) (ptr); \ -__asm__("":"=r" (__pu_err)); \ -switch (size) { \ -case 1: __put_dbe_asm("sb"); break; \ -case 2: __put_dbe_asm("sh"); break; \ -case 4: __put_dbe_asm("sw"); break; \ -case 8: __put_dbe_asm("sd"); break; \ -default: __put_dbe_unknown(); break; \ -} __pu_err; }) - -#define __put_dbe_asm(insn) \ -({ \ -__asm__ __volatile__( \ - "1:\t" insn "\t%1,%2\n\t" \ - "move\t%0,$0\n" \ - "2:\n\t" \ - ".section\t.fixup,\"ax\"\n" \ - "3:\tli\t%0,%3\n\t" \ - "j\t2b\n\t" \ - ".previous\n\t" \ - ".section\t__dbe_table,\"a\"\n\t" \ - ".dword\t1b,3b\n\t" \ - ".previous" \ - :"=r" (__pu_err) \ - :"r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT)); }) - -extern void __put_dbe_unknown(void); - -extern asmlinkage void handle_ibe(void); -extern asmlinkage void handle_dbe(void); - -extern unsigned long search_dbe_table(unsigned long addr); - -#endif /* _ASM_PACCESS_H */ diff --git a/include/asm-mips64/page.h b/include/asm-mips64/page.h deleted file mode 100644 index 7cedbea04a6..00000000000 --- a/include/asm-mips64/page.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PAGE_H -#define _ASM_PAGE_H - -#include - -/* PAGE_SHIFT determines the page size */ -#define PAGE_SHIFT 12 -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -extern void (*_clear_page)(void * page); -extern void (*_copy_page)(void * to, void * from); - -#define clear_page(page) _clear_page((void *)(page)) -#define copy_page(to, from) _copy_page((void *)(to), (void *)(from)) - -extern unsigned long shm_align_mask; - -static inline unsigned long pages_do_alias(unsigned long addr1, - unsigned long addr2) -{ - return (addr1 ^ addr2) & shm_align_mask; -} - -struct page; - -static inline void clear_user_page(void *addr, unsigned long vaddr, - struct page *page) -{ - extern void (*flush_data_cache_page)(unsigned long addr); - - clear_page(addr); - if (pages_do_alias((unsigned long) addr, vaddr)) - flush_data_cache_page((unsigned long)addr); -} - -static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, - struct page *to) -{ - extern void (*flush_data_cache_page)(unsigned long addr); - - copy_page(vto, vfrom); - if (pages_do_alias((unsigned long)vto, vaddr)) - flush_data_cache_page((unsigned long)vto); -} - -/* - * These are used to make use of C type-checking.. - */ -typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pmd; } pmd_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((x).pmd) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t))) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -/* Pure 2^n version of get_order */ -static __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -#endif /* !__ASSEMBLY__ */ - -/* to align the pointer to the (next) page boundary */ -#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) - -/* - * This handles the memory map. - */ -#ifdef CONFIG_NONCOHERENT_IO -#define PAGE_OFFSET 0x9800000000000000UL -#else -#define PAGE_OFFSET 0xa800000000000000UL -#endif - -#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) -#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) - -#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) - -#ifndef CONFIG_DISCONTIGMEM -#define pfn_to_page(pfn) (mem_map + (pfn)) -#define page_to_pfn(page) ((unsigned long)((page) - mem_map)) -#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) - -#define pfn_valid(pfn) ((pfn) < max_mapnr) -#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) -#endif - -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) -#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) - -/* - * Memory above this physical address will be considered highmem. - * Fixme: 59 bits is a fictive number and makes assumptions about processors - * in the distant future. Nobody will care for a few years :-) - */ -#define HIGHMEM_START (1UL << 59UL) - -#endif /* defined (__KERNEL__) */ - -#endif /* _ASM_PAGE_H */ diff --git a/include/asm-mips64/param.h b/include/asm-mips64/param.h deleted file mode 100644 index 854088bb18b..00000000000 --- a/include/asm-mips64/param.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright 1994 - 2000, 2002 Ralf Baechle (ralf@gnu.org) - * Copyright 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PARAM_H -#define _ASM_PARAM_H - -#ifdef __KERNEL__ - -#include - -#ifdef CONFIG_DECSTATION - /* - * log2(HZ), change this here if you want another HZ value. This is also - * used in dec_time_init. Minimum is 1, Maximum is 15. - */ -# define LOG_2_HZ 7 -# define HZ (1 << LOG_2_HZ) -#else -# define HZ 1000 /* Internal kernel timer frequency */ -#endif -# define USER_HZ 100 /* .. some user interfaces are in "ticks" */ -# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ -#endif - -#ifndef HZ -#define HZ 100 -#endif - -#define EXEC_PAGESIZE 4096 - -#ifndef NGROUPS -#define NGROUPS 32 -#endif - -#ifndef NOGROUP -#define NOGROUP (-1) -#endif - -#define MAXHOSTNAMELEN 64 /* max length of hostname */ - -#endif /* _ASM_PARAM_H */ diff --git a/include/asm-mips64/parport.h b/include/asm-mips64/parport.h deleted file mode 100644 index a742e04e82d..00000000000 --- a/include/asm-mips64/parport.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 1999, 2000 Tim Waugh - * - * This file should only be included by drivers/parport/parport_pc.c. - */ -#ifndef _ASM_PARPORT_H -#define _ASM_PARPORT_H - -static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); -static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) -{ - return parport_pc_find_isa_ports (autoirq, autodma); -} - -#endif /* _ASM_PARPORT_H */ diff --git a/include/asm-mips64/pci.h b/include/asm-mips64/pci.h deleted file mode 100644 index 56e01db6f45..00000000000 --- a/include/asm-mips64/pci.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef _ASM_PCI_H -#define _ASM_PCI_H - -#include -#include - -#ifdef __KERNEL__ - -/* Can be used to override the logic in pci_scan_bus for skipping - already-configured bus numbers - to be used for buggy BIOSes - or architectures with incomplete PCI setup by the loader */ - -#ifdef CONFIG_PCI -extern unsigned int pcibios_assign_all_busses(void); -#else -#define pcibios_assign_all_busses() 0 -#endif - -#define PCIBIOS_MIN_IO 0x1000 -#define PCIBIOS_MIN_MEM 0x10000000 - -static inline void pcibios_set_master(struct pci_dev *dev) -{ - /* No special bus mastering setup handling */ -} - -static inline void pcibios_penalize_isa_irq(int irq) -{ - /* We don't do dynamic PCI IRQ allocation */ -} - -/* - * Dynamic DMA mapping stuff. - * MIPS has everything mapped statically. - */ - -#include -#include -#include -#include -#include - -#if defined(CONFIG_DDB5074) || defined(CONFIG_DDB5476) -#undef PCIBIOS_MIN_IO -#undef PCIBIOS_MIN_MEM -#define PCIBIOS_MIN_IO 0x0100000 -#define PCIBIOS_MIN_MEM 0x1000000 -#endif - -struct pci_dev; - -/* - * The PCI address space does equal the physical memory address space. The - * networking and block device layers use this boolean for bounce buffer - * decisions. - */ -#define PCI_DMA_BUS_IS_PHYS (1) - -#ifdef CONFIG_MAPPED_DMA_IO - -/* pci_unmap_{single,page} is not a nop, thus... */ -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME; -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME; -#define pci_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) -#define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) - -#else /* CONFIG_MAPPED_DMA_IO */ - -/* pci_unmap_{page,single} is a nop so... */ -#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) -#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) -#define pci_unmap_addr(PTR, ADDR_NAME) (0) -#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) -#define pci_unmap_len(PTR, LEN_NAME) (0) -#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) - -#endif /* CONFIG_MAPPED_DMA_IO */ - -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - -static inline dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev, - struct page *page, unsigned long offset, int direction) -{ - dma64_addr_t addr = page_to_phys(page) + offset; - - return (dma64_addr_t) bus_to_baddr(pdev->bus, addr); -} - -static inline struct page *pci_dac_dma_to_page(struct pci_dev *pdev, - dma64_addr_t dma_addr) -{ - unsigned long poff = baddr_to_bus(pdev->bus, dma_addr) >> PAGE_SHIFT; - - return mem_map + poff; -} - -static inline unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev, - dma64_addr_t dma_addr) -{ - return dma_addr & ~PAGE_MASK; -} - -static inline void pci_dac_dma_sync_single(struct pci_dev *pdev, - dma64_addr_t dma_addr, size_t len, int direction) -{ - unsigned long addr; - - if (direction == PCI_DMA_NONE) - BUG(); - - addr = baddr_to_bus(pdev->bus, dma_addr) + PAGE_OFFSET; - dma_cache_wback_inv(addr, len); -} - -#endif /* __KERNEL__ */ - -/* implement the pci_ DMA API in terms of the generic device dma_ one */ -#include - -/* generic pci stuff */ -#include - -#endif /* _ASM_PCI_H */ diff --git a/include/asm-mips64/percpu.h b/include/asm-mips64/percpu.h deleted file mode 100644 index 844e763e933..00000000000 --- a/include/asm-mips64/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_PERCPU_H -#define __ASM_PERCPU_H - -#include - -#endif /* __ASM_PERCPU_H */ diff --git a/include/asm-mips64/pgtable-bits.h b/include/asm-mips64/pgtable-bits.h deleted file mode 100644 index fd79206b2fa..00000000000 --- a/include/asm-mips64/pgtable-bits.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 2002 by Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. - * Copyright (C) 2002 Maciej W. Rozycki - */ -#ifndef _ASM_PGTABLE_BITS_H -#define _ASM_PGTABLE_BITS_H - -#include - -/* - * Note that we shift the lower 32bits of each EntryLo[01] entry - * 6 bits to the left. That way we can convert the PFN into the - * physical address by a single 'and' operation and gain 6 additional - * bits for storing information which isn't present in a normal - * MIPS page table. - * - * Similar to the Alpha port, we need to keep track of the ref - * and mod bits in software. We have a software "yeah you can read - * from this page" bit, and a hardware one which actually lets the - * process read from the page. On the same token we have a software - * writable bit and the real hardware one which actually lets the - * process write to the page, this keeps a mod bit via the hardware - * dirty bit. - * - * Certain revisions of the R4000 and R5000 have a bug where if a - * certain sequence occurs in the last 3 instructions of an executable - * page, and the following page is not mapped, the cpu can do - * unpredictable things. The code (when it is written) to deal with - * this problem will be in the update_mmu_cache() code for the r4k. - */ -#define _PAGE_PRESENT (1<<0) /* implemented in software */ -#define _PAGE_READ (1<<1) /* implemented in software */ -#define _PAGE_WRITE (1<<2) /* implemented in software */ -#define _PAGE_ACCESSED (1<<3) /* implemented in software */ -#define _PAGE_MODIFIED (1<<4) /* implemented in software */ -#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - -#define _PAGE_GLOBAL (1<<8) -#define _PAGE_VALID (1<<9) -#define _PAGE_SILENT_READ (1<<9) /* synonym */ -#define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */ -#define _PAGE_SILENT_WRITE (1<<10) -#define _CACHE_UNCACHED (1<<11) -#define _CACHE_MASK (1<<11) -#define _CACHE_CACHABLE_NONCOHERENT 0 - -#else -#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ -#define _PAGE_GLOBAL (1<<6) -#define _PAGE_VALID (1<<7) -#define _PAGE_SILENT_READ (1<<7) /* synonym */ -#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ -#define _PAGE_SILENT_WRITE (1<<8) -#define _CACHE_MASK (7<<9) - -#if defined(CONFIG_CPU_SB1) - -/* No penalty for being coherent on the SB1, so just - use it for "noncoherent" spaces, too. Shouldn't hurt. */ - -#define _CACHE_UNCACHED (2<<9) -#define _CACHE_CACHABLE_COW (5<<9) -#define _CACHE_CACHABLE_NONCOHERENT (5<<9) -#define _CACHE_UNCACHED_ACCELERATED (7<<9) - -#else - -#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ -#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ -#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */ -#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */ -#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ - -#endif -#endif - -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) - -#ifdef CONFIG_MIPS_UNCACHED -#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED -#elif defined(CONFIG_NONCOHERENT_IO) -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT -#else -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW -#endif - -#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) - -#endif /* _ASM_PGTABLE_BITS_H */ diff --git a/include/asm-mips64/pgtable.h b/include/asm-mips64/pgtable.h deleted file mode 100644 index 8ec8c3bcd67..00000000000 --- a/include/asm-mips64/pgtable.h +++ /dev/null @@ -1,476 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 2001 by Ralf Baechle at alii - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_PGTABLE_H -#define _ASM_PGTABLE_H - -#include -#include -#include - -#ifndef __ASSEMBLY__ - -#include -#include -#include - -/* - * This flag is used to indicate that the page pointed to by a pte - * is dirty and requires cleaning before returning it to the user. - */ -#define PG_dcache_dirty PG_arch_1 - -#define Page_dcache_dirty(page) \ - test_bit(PG_dcache_dirty, &(page)->flags) -#define SetPageDcacheDirty(page) \ - set_bit(PG_dcache_dirty, &(page)->flags) -#define ClearPageDcacheDirty(page) \ - clear_bit(PG_dcache_dirty, &(page)->flags) - - -/* - * Each address space has 2 4K pages as its page directory, giving 1024 - * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a - * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to - * page tables. Each page table is a single 4K page, giving 512 (== - * PTRS_PER_PTE) 8 byte ptes. Each pgde is initialized to point to - * invalid_pmd_table, each pmde is initialized to point to - * invalid_pte_table, each pte is initialized to 0. When memory is low, - * and a pmd table or a page table allocation fails, empty_bad_pmd_table - * and empty_bad_page_table is returned back to higher layer code, so - * that the failure is recognized later on. Linux does not seem to - * handle these failures very well though. The empty_bad_page_table has - * invalid pte entries in it, to force page faults. - * Vmalloc handling: vmalloc uses swapper_pg_dir[0] (returned by - * pgd_offset_k), which is initalized to point to kpmdtbl. kpmdtbl is - * the only single page pmd in the system. kpmdtbl entries point into - * kptbl[] array. We reserve 1 << PGD_ORDER pages to hold the - * vmalloc range translations, which the fault handler looks at. - */ - -#endif /* !__ASSEMBLY__ */ - -/* PMD_SHIFT determines the size of the area a second-level page table can map */ -#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3)) -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + 1 - 3)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* Entries per page directory level: we use two-level, so we don't really - have any PMD directory physically. */ -#define PTRS_PER_PGD 1024 -#define PTRS_PER_PMD 1024 -#define PTRS_PER_PTE 512 -#define PGD_ORDER 1 -#define PMD_ORDER 1 -#define PTE_ORDER 0 - -#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) -#define FIRST_USER_PGD_NR 0 - -#define VMALLOC_START XKSEG -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) -#define VMALLOC_END \ - (VMALLOC_START + ((1 << PGD_ORDER) * PTRS_PER_PTE * PAGE_SIZE)) - -#include - -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - PAGE_CACHABLE_DEFAULT) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - PAGE_CACHABLE_DEFAULT) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - PAGE_CACHABLE_DEFAULT) -#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ - _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT) -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ - PAGE_CACHABLE_DEFAULT) -#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ - __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) - -/* - * MIPS can't do page protection for execute, and considers that the same like - * read. Also, write permissions imply read permissions. This is the closest - * we can get by reasonable means.. - */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED - -#ifndef __ASSEMBLY__ - -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) -#define pmd_ERROR(e) \ - printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) -#define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) - -/* - * ZERO_PAGE is a global shared page that is always zero; used - * for zero-mapped memory areas etc.. - */ - -extern unsigned long empty_zero_page; -extern unsigned long zero_page_mask; - -#define ZERO_PAGE(vaddr) \ - (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))) - -extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; -extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)]; -extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; -extern pmd_t empty_bad_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ -#define page_pte(page) page_pte_prot(page, __pgprot(0)) -#define pmd_phys(pmd) (pmd_val(pmd) - PAGE_OFFSET) -#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) -#define pmd_page_kernel(pmd) pmd_val(pmd) - -static inline unsigned long pgd_page(pgd_t pgd) -{ - return pgd_val(pgd); -} - -static inline int pte_none(pte_t pte) -{ - return !(pte_val(pte) & ~_PAGE_GLOBAL); -} - -static inline int pte_present(pte_t pte) -{ - return pte_val(pte) & _PAGE_PRESENT; -} - -/* - * Certain architectures need to do special things when pte's - * within a page table are directly modified. Thus, the following - * hook is made available. - */ -static inline void set_pte(pte_t *ptep, pte_t pteval) -{ - *ptep = pteval; -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) - if (pte_val(pteval) & _PAGE_GLOBAL) { - pte_t *buddy = ptep_buddy(ptep); - /* - * Make sure the buddy is global too (if it's !none, - * it better already be global) - */ - if (pte_none(*buddy)) - pte_val(*buddy) = pte_val(*buddy) | _PAGE_GLOBAL; - } -#endif -} - -static inline void pte_clear(pte_t *ptep) -{ -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) - /* Preserve global status for the pair */ - if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) - set_pte(ptep, __pte(_PAGE_GLOBAL)); - else -#endif - set_pte(ptep, __pte(0)); -} - -/* - * (pmds are folded into pgds so this doesn't get actually called, - * but the define is needed for a generic inline function.) - */ -#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0) -#define set_pgd(pgdptr, pgdval) do { *(pgdptr) = (pgdval); } while(0) - -/* - * Empty pmd entries point to the invalid_pte_table. - */ -static inline int pmd_none(pmd_t pmd) -{ - return pmd_val(pmd) == (unsigned long) invalid_pte_table; -} - -#define pmd_bad(pmd) (pmd_val(pmd) &~ PAGE_MASK) - -static inline int pmd_present(pmd_t pmd) -{ - return pmd_val(pmd) != (unsigned long) invalid_pte_table; -} - -static inline void pmd_clear(pmd_t *pmdp) -{ - pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); -} - -/* - * Empty pgd entries point to the invalid_pmd_table. - */ -static inline int pgd_none(pgd_t pgd) -{ - return pgd_val(pgd) == (unsigned long) invalid_pmd_table; -} - -#define pgd_bad(pgd) (pgd_val(pgd) &~ PAGE_MASK) - -static inline int pgd_present(pgd_t pgd) -{ - return pgd_val(pgd) != (unsigned long) invalid_pmd_table; -} - -static inline void pgd_clear(pgd_t *pgdp) -{ - pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table); -} - -#ifdef CONFIG_DISCONTIGMEM - -#define pte_page(x) (NODE_MEM_MAP(PHYSADDR_TO_NID(pte_val(x))) + \ - PLAT_NODE_DATA_LOCALNR(pte_val(x), PHYSADDR_TO_NID(pte_val(x)))) - -#else -#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT))) -#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) -#endif - -#define PTE_FILE_MAX_BITS 27 - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - -/* - * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset - * into this range: - */ - -#define pte_to_pgoff(_pte) \ - ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 )) - -#define pgoff_to_pte(off) \ - ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE }) - -#else - -/* - * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset - * into this range: - */ -#define pte_to_pgoff(_pte) \ - ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) - -#define pgoff_to_pte(off) \ - ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE }) - -#endif - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ -static inline int pte_user(pte_t pte) { BUG(); return 0; } -static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } -static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } -static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } -static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } -static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } - -static inline pte_t pte_wrprotect(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); - return pte; -} - -static inline pte_t pte_rdprotect(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); - return pte; -} - -static inline pte_t pte_mkclean(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); - return pte; -} - -static inline pte_t pte_mkold(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ); - return pte; -} - -static inline pte_t pte_mkwrite(pte_t pte) -{ - pte_val(pte) |= _PAGE_WRITE; - if (pte_val(pte) & _PAGE_MODIFIED) - pte_val(pte) |= _PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkread(pte_t pte) -{ - pte_val(pte) |= _PAGE_READ; - if (pte_val(pte) & _PAGE_ACCESSED) - pte_val(pte) |= _PAGE_SILENT_READ; - return pte; -} - -static inline pte_t pte_mkdirty(pte_t pte) -{ - pte_val(pte) |= _PAGE_MODIFIED; - if (pte_val(pte) & _PAGE_WRITE) - pte_val(pte) |= _PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkyoung(pte_t pte) -{ - pte_val(pte) |= _PAGE_ACCESSED; - if (pte_val(pte) & _PAGE_READ) - pte_val(pte) |= _PAGE_SILENT_READ; - return pte; -} - -/* - * Macro to make mark a page protection value as "uncacheable". Note - * that "protection" is really a misnomer here as the protection value - * contains the memory attribute bits, dirty bits, and various other - * bits as well. - */ -#define pgprot_noncached pgprot_noncached - -static inline pgprot_t pgprot_noncached(pgprot_t _prot) -{ - unsigned long prot = pgprot_val(_prot); - - prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; - - return __pgprot(prot); -} - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ -#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) - -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ - return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); -} - -#define __pgd_offset(address) pgd_index(address) -#define page_pte(page) page_pte_prot(page, __pgprot(0)) - -/* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(address) pgd_offset(&init_mm, 0) - -#define pgd_index(address) ((address) >> PGDIR_SHIFT) - -/* to find an entry in a page-table-directory */ -#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr)) - -/* Find an entry in the second-level page table.. */ -static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address) -{ - return (pmd_t *) pgd_page(*dir) + - ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1)); -} - -/* Find an entry in the third-level page table.. */ -#define __pte_offset(address) \ - (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) -#define pte_offset(dir, address) \ - ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address)) -#define pte_offset_kernel(dir, address) \ - ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address)) -#define pte_offset_map(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) -#define pte_offset_map_nested(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) -#define pte_unmap(pte) ((void)(pte)) -#define pte_unmap_nested(pte) ((void)(pte)) - -/* - * Initialize a new pgd / pmd table with invalid pointers. - */ -extern void pgd_init(unsigned long page); -extern void pmd_init(unsigned long page, unsigned long pagetable); - -extern pgd_t swapper_pg_dir[1024]; -extern void paging_init(void); - -extern void __update_tlb(struct vm_area_struct *vma, unsigned long address, - pte_t pte); -extern void __update_cache(struct vm_area_struct *vma, unsigned long address, - pte_t pte); - -static inline void update_mmu_cache(struct vm_area_struct *vma, - unsigned long address, pte_t pte) -{ - __update_tlb(vma, address, pte); - __update_cache(vma, address, pte); -} - -/* - * Non-present pages: high 24 bits are offset, next 8 bits type, - * low 32 bits zero. - */ -static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) -{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; } - -#define __swp_type(x) (((x).val >> 32) & 0xff) -#define __swp_offset(x) ((x).val >> 40) -#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) - -#ifndef CONFIG_DISCONTIGMEM -#define kern_addr_valid(addr) (1) -#endif - -/* - * No page table caches to initialise - */ -#define pgtable_cache_init() do { } while (0) - -#include - -typedef pte_t *pte_addr_t; - -/* - * We provide our own get_unmapped area to cope with the virtual aliasing - * constraints placed on us by the cache architecture. - */ -#define HAVE_ARCH_UNMAPPED_AREA - -#define io_remap_page_range remap_page_range - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_PGTABLE_H */ diff --git a/include/asm-mips64/poll.h b/include/asm-mips64/poll.h deleted file mode 100644 index a000f1f789e..00000000000 --- a/include/asm-mips64/poll.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __ASM_POLL_H -#define __ASM_POLL_H - -#define POLLIN 0x0001 -#define POLLPRI 0x0002 -#define POLLOUT 0x0004 - -#define POLLERR 0x0008 -#define POLLHUP 0x0010 -#define POLLNVAL 0x0020 - -#define POLLRDNORM 0x0040 -#define POLLRDBAND 0x0080 -#define POLLWRNORM POLLOUT -#define POLLWRBAND 0x0100 - -/* These seem to be more or less nonstandard ... */ -#define POLLMSG 0x0400 -#define POLLREMOVE 0x1000 - -struct pollfd { - int fd; - short events; - short revents; -}; - -#endif /* __ASM_POLL_H */ diff --git a/include/asm-mips64/posix_types.h b/include/asm-mips64/posix_types.h deleted file mode 100644 index dd541acc85a..00000000000 --- a/include/asm-mips64/posix_types.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_POSIX_TYPES_H -#define _ASM_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned int __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned int __kernel_mode_t; -typedef unsigned int __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef int __kernel_ipc_pid_t; -typedef int __kernel_uid_t; -typedef int __kernel_gid_t; -typedef unsigned long __kernel_size_t; -typedef long __kernel_ssize_t; -typedef long __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef long __kernel_daddr_t; -typedef char * __kernel_caddr_t; - -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef int __kernel_uid32_t; -typedef int __kernel_gid32_t; -typedef __kernel_uid_t __kernel_old_uid_t; -typedef __kernel_gid_t __kernel_old_gid_t; -typedef unsigned int __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { - int val[2]; -} __kernel_fsid_t; - -/* Now 32bit compatibility types */ -typedef unsigned int __kernel_dev_t32; -typedef unsigned int __kernel_ino_t32; -typedef unsigned int __kernel_mode_t32; -typedef unsigned int __kernel_nlink_t32; -typedef int __kernel_off_t32; -typedef int __kernel_pid_t32; -typedef int __kernel_ipc_pid_t32; -typedef int __kernel_uid_t32; -typedef int __kernel_gid_t32; -typedef int __kernel_ptrdiff_t32; -typedef int __kernel_suseconds_t32; -typedef int __kernel_clock_t32; -typedef int __kernel_daddr_t32; -typedef unsigned int __kernel_caddr_t32; -typedef __kernel_fsid_t __kernel_fsid_t32; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); -} - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *__p) -{ - unsigned long *__tmp = __p->fds_bits; - int __i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 16: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - __tmp[ 8] = 0; __tmp[ 9] = 0; - __tmp[10] = 0; __tmp[11] = 0; - __tmp[12] = 0; __tmp[13] = 0; - __tmp[14] = 0; __tmp[15] = 0; - return; - - case 8: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - return; - - case 4: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - return; - } - } - __i = __FDSET_LONGS; - while (__i) { - __i--; - *__tmp = 0; - __tmp++; - } -} - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ - -#endif /* _ASM_POSIX_TYPES_H */ diff --git a/include/asm-mips64/processor.h b/include/asm-mips64/processor.h deleted file mode 100644 index 49ec7f31bfd..00000000000 --- a/include/asm-mips64/processor.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 Waldorf GMBH - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle - * Copyright (C) 1996 Paul M. Antoine - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PROCESSOR_H -#define _ASM_PROCESSOR_H - -#include - -/* - * Return current * instruction pointer ("program counter"). - */ -#define current_text_addr() \ -({ \ - void *_a; \ - \ - __asm__ ("bal\t1f\t\t\t# current_text_addr\n" \ - "1:\tmove\t%0, $31" \ - : "=r" (_a) \ - : \ - : "$31"); \ - \ - _a; \ -}) - -#ifndef __ASSEMBLY__ -#include -#include - -#include -#include -#include -#include - -#if defined(CONFIG_SGI_IP27) -#include -#include -#endif - -/* - * Descriptor for a cache - */ -struct cache_desc { - unsigned short linesz; /* Size of line in bytes */ - unsigned short ways; /* Number of ways */ - unsigned int sets; /* Number of lines per set */ - unsigned int waysize; /* Bytes per way */ - unsigned int waybit; /* Bits to select in a cache set */ - unsigned int flags; /* Flags describing cache properties */ -}; - -/* - * Flag definitions - */ -#define MIPS_CACHE_NOT_PRESENT 0x00000001 -#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */ -#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ -#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ - -struct cpuinfo_mips { - unsigned long udelay_val; - unsigned long asid_cache; -#if defined(CONFIG_SGI_IP27) - cpuid_t p_cpuid; /* PROM assigned cpuid */ - cnodeid_t p_nodeid; /* my node ID in compact-id-space */ - nasid_t p_nasid; /* my node ID in numa-as-id-space */ - unsigned char p_slice; /* Physical position on node board */ - hub_intmasks_t p_intmasks; /* SN0 per-CPU interrupt masks */ -#endif -#if 0 - unsigned long loops_per_sec; - unsigned long ipi_count; - unsigned long irq_attempt[NR_IRQS]; - unsigned long smp_local_irq_count; - unsigned long prof_multiplier; - unsigned long prof_counter; -#endif - - /* - * Capability and feature descriptor structure for MIPS CPU - */ - unsigned long options; - unsigned int processor_id; - unsigned int fpu_id; - unsigned int cputype; - int isa_level; - int tlbsize; - struct cache_desc icache; /* Primary I-cache */ - struct cache_desc dcache; /* Primary D or combined I/D cache */ - struct cache_desc scache; /* Secondary cache */ - struct cache_desc tcache; /* Tertiary/split secondary cache */ -} __attribute__((aligned(SMP_CACHE_BYTES))); - -/* - * Assumption: Options of CPU 0 are a superset of all processors. - * This is true for all known MIPS systems. - */ -#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) -#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) -#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB) -#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU) -#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) -#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) -#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) -#define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16) -#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) -#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) -#define cpu_has_cache_cdex (cpu_data[0].options & MIPS_CPU_CACHE_CDEX) -#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) -#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) -#define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) -#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) -#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) -#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) -#define cpu_has_ic_fills_f_dc (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC) -#define cpu_has_64bits 1 -#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) - -extern struct cpuinfo_mips cpu_data[]; -#define current_cpu_data cpu_data[smp_processor_id()] - -extern void cpu_probe(void); -extern void cpu_report(void); - -/* - * System setup and hardware flags.. - */ -extern void (*cpu_wait)(void); - -extern unsigned int vced_count, vcei_count; - -/* - * Bus types (default is ISA, but people can check others with these..) - */ -#ifdef CONFIG_EISA -extern int EISA_bus; -#else -#define EISA_bus (0) -#endif - -#define MCA_bus 0 -#define MCA_bus__is_a_macro /* for versions in ksyms.c */ - -/* - * User space process size: 1TB. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. TASK_SIZE - * is limited to 1TB by the R4000 architecture; R10000 and better can - * support 16TB. - */ -#define TASK_SIZE32 0x7fff8000UL -#define TASK_SIZE 0x10000000000UL - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE ((current->thread.mflags & MF_32BIT_ADDR) ? \ - PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) - -/* - * Size of io_bitmap in longwords: 32 is ports 0-0x3ff. - */ -#define IO_BITMAP_SIZE 32 - -#define NUM_FPU_REGS 32 - -typedef u64 fpureg_t; - -struct mips_fpu_hard_struct { - fpureg_t fpr[NUM_FPU_REGS]; - unsigned int fcr31; -}; - -/* - * It would be nice to add some more fields for emulator statistics, but there - * are a number of fixed offsets in offset.h and elsewhere that would have to - * be recalculated by hand. So the additional information will be private to - * the FPU emulator for now. See asm-mips/fpu_emulator.h. - */ - -struct mips_fpu_soft_struct { - fpureg_t fpr[NUM_FPU_REGS]; - unsigned int fcr31; -}; - -union mips_fpu_union { - struct mips_fpu_hard_struct hard; - struct mips_fpu_soft_struct soft; -}; - -#define INIT_FPU { \ - {{0,},} \ -} - -typedef struct { - unsigned long seg; -} mm_segment_t; - -/* - * If you change thread_struct remember to change the #defines below too! - */ -struct thread_struct { - /* Saved main processor registers. */ - unsigned long reg16; - unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; - unsigned long reg29, reg30, reg31; - - /* Saved cp0 stuff. */ - unsigned long cp0_status; - - /* Saved fpu/fpu emulator stuff. */ - union mips_fpu_union fpu; - - /* Other stuff associated with the thread. */ - unsigned long cp0_badvaddr; /* Last user fault */ - unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ - unsigned long error_code; - unsigned long trap_no; -#define MF_FIXADE 1 /* Fix address errors in software */ -#define MF_LOGADE 2 /* Log address errors to syslog */ -#define MF_32BIT_REGS 4 /* also implies 16/32 fprs */ -#define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */ - unsigned long mflags; - unsigned long irix_trampoline; /* Wheee... */ - unsigned long irix_oldctx; -}; - -#define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR) -#define MF_O32 (MF_32BIT_REGS | MF_32BIT_ADDR) -#define MF_N32 MF_32BIT_ADDR -#define MF_N64 0 - -#endif /* !__ASSEMBLY__ */ - -#define INIT_THREAD { \ - /* \ - * saved main processor registers \ - */ \ - 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, \ - /* \ - * saved cp0 stuff \ - */ \ - 0, \ - /* \ - * saved fpu/fpu emulator stuff \ - */ \ - INIT_FPU, \ - /* \ - * Other stuff associated with the process \ - */ \ - 0, 0, 0, 0, \ - /* \ - * For now the default is to fix address errors \ - */ \ - MF_FIXADE, 0, 0 \ -} - -#ifdef __KERNEL__ -#ifndef __ASSEMBLY__ - -struct task_struct; - -/* Free all resources held by a thread. */ -#define release_thread(thread) do { } while(0) - -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while (0) - -extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); - -extern unsigned long thread_saved_pc(struct task_struct *tsk); - -#define user_mode(regs) (((regs)->cp0_status & ST0_KSU) == KSU_USER) - -/* - * Do necessary setup to start up a newly executed thread. - */ -extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp); - -unsigned long get_wchan(struct task_struct *p); - -#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs)) -#define __KSTK_TOS(tsk) ((unsigned long)(tsk->thread_info) + THREAD_SIZE - 32) -#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc))) -#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29]))) -#define KSTK_STATUS(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_status))) - -#define cpu_relax() barrier() - -#endif /* !__ASSEMBLY__ */ -#endif /* __KERNEL__ */ - -/* - * Return_address is a replacement for __builtin_return_address(count) - * which on certain architectures cannot reasonably be implemented in GCC - * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). - * Note that __builtin_return_address(x>=1) is forbidden because GCC - * aborts compilation on some CPUs. It's simply not possible to unwind - * some CPU's stackframes. - * - * __builtin_return_address works only for non-leaf functions. We avoid the - * overhead of a function call by forcing the compiler to save the return - * address register on the stack. - */ -#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) - -#endif /* _ASM_PROCESSOR_H */ diff --git a/include/asm-mips64/ptrace.h b/include/asm-mips64/ptrace.h deleted file mode 100644 index 36c9f329133..00000000000 --- a/include/asm-mips64/ptrace.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PTRACE_H -#define _ASM_PTRACE_H - -/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ -#define FPR_BASE 32 -#define PC 64 -#define CAUSE 65 -#define BADVADDR 66 -#define MMHI 67 -#define MMLO 68 -#define FPC_CSR 69 -#define FPC_EIR 70 - -#ifndef __ASSEMBLY__ - -/* - * This struct defines the way the registers are stored on the stack during a - * system call/exception. As usual the registers k0/k1 aren't being saved. - */ -struct pt_regs { - /* Saved main processor registers. */ - unsigned long regs[32]; - - /* Other saved registers. */ - unsigned long lo; - unsigned long hi; - - /* - * saved cp0 registers - */ - unsigned long cp0_epc; - unsigned long cp0_badvaddr; - unsigned long cp0_status; - unsigned long cp0_cause; -}; - -#define __str2(x) #x -#define __str(x) __str2(x) - -/* Used in declaration of save_static functions. */ -#define static_unused static __attribute__((unused)) - -#define save_static_function(symbol) \ -__asm__ ( \ - ".text\n\t" \ - ".globl\t" #symbol "\n\t" \ - ".align\t2\n\t" \ - ".type\t" #symbol ", @function\n\t" \ - ".ent\t" #symbol ", 0\n" \ - #symbol":\n\t" \ - ".frame\t$29, 0, $31\n\t" \ - ".end\t" #symbol "\n\t" \ - ".size\t" #symbol",. - " #symbol) - -#define save_static(frame) \ - __asm__ __volatile__( \ - "sd\t$16,"__str(PT_R16)"(%0)\n\t" \ - "sd\t$17,"__str(PT_R17)"(%0)\n\t" \ - "sd\t$18,"__str(PT_R18)"(%0)\n\t" \ - "sd\t$19,"__str(PT_R19)"(%0)\n\t" \ - "sd\t$20,"__str(PT_R20)"(%0)\n\t" \ - "sd\t$21,"__str(PT_R21)"(%0)\n\t" \ - "sd\t$22,"__str(PT_R22)"(%0)\n\t" \ - "sd\t$23,"__str(PT_R23)"(%0)\n\t" \ - "sd\t$30,"__str(PT_R30)"(%0)\n\t" \ - : /* No outputs */ \ - : "r" (frame)) - -#define nabi_no_regargs \ - unsigned long __dummy0, \ - unsigned long __dummy1, \ - unsigned long __dummy2, \ - unsigned long __dummy3, \ - unsigned long __dummy4, \ - unsigned long __dummy5, \ - unsigned long __dummy6, \ - unsigned long __dummy7, - -#endif /* !__ASSEMBLY__ */ - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -/* #define PTRACE_GETREGS 12 */ -/* #define PTRACE_SETREGS 13 */ -/* #define PTRACE_GETFPREGS 14 */ -/* #define PTRACE_SETFPREGS 15 */ -/* #define PTRACE_GETFPXREGS 18 */ -/* #define PTRACE_SETFPXREGS 19 */ - -#define PTRACE_OLDSETOPTIONS 21 - -#define PTRACE_GET_THREAD_AREA 25 -#define PTRACE_SET_THREAD_AREA 26 - -#ifdef __ASSEMBLY__ -#include -#endif /* !__ASSEMBLY__ */ - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -#define instruction_pointer(regs) ((regs)->cp0_epc) - -extern void show_regs(struct pt_regs *); -#endif /* !__ASSEMBLY__ */ - -#endif - -#endif /* _ASM_PTRACE_H */ diff --git a/include/asm-mips64/r4kcache.h b/include/asm-mips64/r4kcache.h deleted file mode 100644 index 84aa8535bc2..00000000000 --- a/include/asm-mips64/r4kcache.h +++ /dev/null @@ -1,569 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Inline assembly cache operations. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org) - */ -#ifndef __ASM_R4KCACHE_H -#define __ASM_R4KCACHE_H - -#include -#include - -#define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set mips0 \n" \ - " .set reorder" \ - : \ - : "i" (op), "m" (*(unsigned char *)(addr))) - -static inline void flush_icache_line_indexed(unsigned long addr) -{ - cache_op(Index_Invalidate_I, addr); -} - -static inline void flush_dcache_line_indexed(unsigned long addr) -{ - cache_op(Index_Writeback_Inv_D, addr); -} - -static inline void flush_scache_line_indexed(unsigned long addr) -{ - cache_op(Index_Writeback_Inv_SD, addr); -} - -static inline void flush_icache_line(unsigned long addr) -{ - cache_op(Hit_Invalidate_I, addr); -} - -static inline void flush_dcache_line(unsigned long addr) -{ - cache_op(Hit_Writeback_Inv_D, addr); -} - -static inline void invalidate_dcache_line(unsigned long addr) -{ - cache_op(Hit_Invalidate_D, addr); -} - -static inline void invalidate_scache_line(unsigned long addr) -{ - cache_op(Hit_Invalidate_SD, addr); -} - -static inline void flush_scache_line(unsigned long addr) -{ - cache_op(Hit_Writeback_Inv_SD, addr); -} - -/* - * The next two are for badland addresses like signal trampolines. - */ -static inline void protected_flush_icache_line(unsigned long addr) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n" - "1:\tcache %0,(%1)\n" - "2:\t.set mips0\n\t" - ".set reorder\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,2b\n\t" - ".previous" - : - : "i" (Hit_Invalidate_I), "r" (addr)); -} - -/* - * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D - * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style - * caches. We're talking about one cacheline unnecessarily getting invalidated - * here so the penaltiy isn't overly hard. - */ -static inline void protected_writeback_dcache_line(unsigned long addr) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n" - "1:\tcache %0,(%1)\n" - "2:\t.set mips0\n\t" - ".set reorder\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,2b\n\t" - ".previous" - : - : "i" (Hit_Writeback_Inv_D), "r" (addr)); -} - -/* - * This one is RM7000-specific - */ -static inline void invalidate_tcache_page(unsigned long addr) -{ - cache_op(Page_Invalidate_T, addr); -} - -#define cache16_unroll32(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0x000(%0); cache %1, 0x010(%0); \ - cache %1, 0x020(%0); cache %1, 0x030(%0); \ - cache %1, 0x040(%0); cache %1, 0x050(%0); \ - cache %1, 0x060(%0); cache %1, 0x070(%0); \ - cache %1, 0x080(%0); cache %1, 0x090(%0); \ - cache %1, 0x0a0(%0); cache %1, 0x0b0(%0); \ - cache %1, 0x0c0(%0); cache %1, 0x0d0(%0); \ - cache %1, 0x0e0(%0); cache %1, 0x0f0(%0); \ - cache %1, 0x100(%0); cache %1, 0x110(%0); \ - cache %1, 0x120(%0); cache %1, 0x130(%0); \ - cache %1, 0x140(%0); cache %1, 0x150(%0); \ - cache %1, 0x160(%0); cache %1, 0x170(%0); \ - cache %1, 0x180(%0); cache %1, 0x190(%0); \ - cache %1, 0x1a0(%0); cache %1, 0x1b0(%0); \ - cache %1, 0x1c0(%0); cache %1, 0x1d0(%0); \ - cache %1, 0x1e0(%0); cache %1, 0x1f0(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -static inline void blast_dcache16(void) -{ - unsigned long start = KSEG0; - unsigned long end = start + current_cpu_data.dcache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_dcache16_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - while (start < end) { - cache16_unroll32(start,Hit_Writeback_Inv_D); - start += 0x200; - } -} - -static inline void blast_dcache16_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_icache16(void) -{ - unsigned long start = KSEG0; - unsigned long end = start + current_cpu_data.icache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_icache16_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - while (start < end) { - cache16_unroll32(start,Hit_Invalidate_I); - start += 0x200; - } -} - -static inline void blast_icache16_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_scache16(void) -{ - unsigned long start = KSEG0; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache16_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - while (start < end) { - cache16_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x200; - } -} - -static inline void blast_scache16_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -#define cache32_unroll32(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0x000(%0); cache %1, 0x020(%0); \ - cache %1, 0x040(%0); cache %1, 0x060(%0); \ - cache %1, 0x080(%0); cache %1, 0x0a0(%0); \ - cache %1, 0x0c0(%0); cache %1, 0x0e0(%0); \ - cache %1, 0x100(%0); cache %1, 0x120(%0); \ - cache %1, 0x140(%0); cache %1, 0x160(%0); \ - cache %1, 0x180(%0); cache %1, 0x1a0(%0); \ - cache %1, 0x1c0(%0); cache %1, 0x1e0(%0); \ - cache %1, 0x200(%0); cache %1, 0x220(%0); \ - cache %1, 0x240(%0); cache %1, 0x260(%0); \ - cache %1, 0x280(%0); cache %1, 0x2a0(%0); \ - cache %1, 0x2c0(%0); cache %1, 0x2e0(%0); \ - cache %1, 0x300(%0); cache %1, 0x320(%0); \ - cache %1, 0x340(%0); cache %1, 0x360(%0); \ - cache %1, 0x380(%0); cache %1, 0x3a0(%0); \ - cache %1, 0x3c0(%0); cache %1, 0x3e0(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -static inline void blast_dcache32(void) -{ - unsigned long start = KSEG0; - unsigned long end = start + current_cpu_data.dcache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_dcache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - while (start < end) { - cache32_unroll32(start,Hit_Writeback_Inv_D); - start += 0x400; - } -} - -static inline void blast_dcache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_icache32(void) -{ - unsigned long start = KSEG0; - unsigned long end = start + current_cpu_data.icache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_icache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - while (start < end) { - cache32_unroll32(start,Hit_Invalidate_I); - start += 0x400; - } -} - -static inline void blast_icache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_scache32(void) -{ - unsigned long start = KSEG0; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - while (start < end) { - cache32_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x400; - } -} - -static inline void blast_scache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -#define cache64_unroll32(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0x000(%0); cache %1, 0x040(%0); \ - cache %1, 0x080(%0); cache %1, 0x0c0(%0); \ - cache %1, 0x100(%0); cache %1, 0x140(%0); \ - cache %1, 0x180(%0); cache %1, 0x1c0(%0); \ - cache %1, 0x200(%0); cache %1, 0x240(%0); \ - cache %1, 0x280(%0); cache %1, 0x2c0(%0); \ - cache %1, 0x300(%0); cache %1, 0x340(%0); \ - cache %1, 0x380(%0); cache %1, 0x3c0(%0); \ - cache %1, 0x400(%0); cache %1, 0x440(%0); \ - cache %1, 0x480(%0); cache %1, 0x4c0(%0); \ - cache %1, 0x500(%0); cache %1, 0x540(%0); \ - cache %1, 0x580(%0); cache %1, 0x5c0(%0); \ - cache %1, 0x600(%0); cache %1, 0x640(%0); \ - cache %1, 0x680(%0); cache %1, 0x6c0(%0); \ - cache %1, 0x700(%0); cache %1, 0x740(%0); \ - cache %1, 0x780(%0); cache %1, 0x7c0(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -static inline void blast_icache64(void) -{ - unsigned long start = KSEG0; - unsigned long end = start + current_cpu_data.icache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_icache64_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - while (start < end) { - cache64_unroll32(start,Hit_Invalidate_I); - start += 0x800; - } -} - -static inline void blast_icache64_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_scache64(void) -{ - unsigned long start = KSEG0; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache64_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - while (start < end) { - cache64_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x800; - } -} - -static inline void blast_scache64_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -#define cache128_unroll32(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0x000(%0); cache %1, 0x080(%0); \ - cache %1, 0x100(%0); cache %1, 0x180(%0); \ - cache %1, 0x200(%0); cache %1, 0x280(%0); \ - cache %1, 0x300(%0); cache %1, 0x380(%0); \ - cache %1, 0x400(%0); cache %1, 0x480(%0); \ - cache %1, 0x500(%0); cache %1, 0x580(%0); \ - cache %1, 0x600(%0); cache %1, 0x680(%0); \ - cache %1, 0x700(%0); cache %1, 0x780(%0); \ - cache %1, 0x800(%0); cache %1, 0x880(%0); \ - cache %1, 0x900(%0); cache %1, 0x980(%0); \ - cache %1, 0xa00(%0); cache %1, 0xa80(%0); \ - cache %1, 0xb00(%0); cache %1, 0xb80(%0); \ - cache %1, 0xc00(%0); cache %1, 0xc80(%0); \ - cache %1, 0xd00(%0); cache %1, 0xd80(%0); \ - cache %1, 0xe00(%0); cache %1, 0xe80(%0); \ - cache %1, 0xf00(%0); cache %1, 0xf80(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -static inline void blast_scache128(void) -{ - unsigned long start = KSEG0; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x1000) - cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache128_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - while (start < end) { - cache128_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x1000; - } -} - -static inline void blast_scache128_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x1000) - cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -#endif /* __ASM_R4KCACHE_H */ diff --git a/include/asm-mips64/reboot.h b/include/asm-mips64/reboot.h deleted file mode 100644 index 2f10ebcbe14..00000000000 --- a/include/asm-mips64/reboot.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1999, 2001 by Ralf Baechle - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef _ASM_REBOOT_H -#define _ASM_REBOOT_H - -extern void (*_machine_restart)(char *command); -extern void (*_machine_halt)(void); -extern void (*_machine_power_off)(void); - -#endif /* _ASM_REBOOT_H */ diff --git a/include/asm-mips64/reg.h b/include/asm-mips64/reg.h deleted file mode 100644 index 92731e9a8a0..00000000000 --- a/include/asm-mips64/reg.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Various register offset definitions for debuggers, core file - * examiners and whatnot. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999 Ralf Baechle - * Copyright (C) 1995, 1999 Silicon Graphics - */ -#ifndef _ASM_REG_H -#define _ASM_REG_H - -/* - * This defines/structures correspond to the register layout on stack - - * if the order here is changed, it needs to be updated in - * include/asm-mips/stackframe.h - */ -#define EF_REG0 0 -#define EF_REG1 1 -#define EF_REG2 2 -#define EF_REG3 3 -#define EF_REG4 4 -#define EF_REG5 5 -#define EF_REG6 6 -#define EF_REG7 7 -#define EF_REG8 8 -#define EF_REG9 9 -#define EF_REG10 10 -#define EF_REG11 11 -#define EF_REG12 12 -#define EF_REG13 13 -#define EF_REG14 14 -#define EF_REG15 15 -#define EF_REG16 16 -#define EF_REG17 17 -#define EF_REG18 18 -#define EF_REG19 19 -#define EF_REG20 20 -#define EF_REG21 21 -#define EF_REG22 22 -#define EF_REG23 23 -#define EF_REG24 24 -#define EF_REG25 25 -/* - * k0/k1 unsaved - */ -#define EF_REG28 28 -#define EF_REG29 29 -#define EF_REG30 30 -#define EF_REG31 31 - -/* - * Saved special registers - */ -#define EF_LO 32 -#define EF_HI 33 - -#define EF_CP0_EPC 34 -#define EF_CP0_BADVADDR 35 -#define EF_CP0_STATUS 36 -#define EF_CP0_CAUSE 37 - -#define EF_SIZE 304 /* size in bytes */ - -#endif /* _ASM_REG_H */ diff --git a/include/asm-mips64/regdef.h b/include/asm-mips64/regdef.h deleted file mode 100644 index 41de95484f5..00000000000 --- a/include/asm-mips64/regdef.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1985 MIPS Computer Systems, Inc. - * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. - * Copyright (C) 1999 Ralf Baechle - */ -#ifndef _ASM_REGDEF_H -#define _ASM_REGDEF_H - -#define zero $0 /* wired zero */ -#define AT $at /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value - caller saved */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ -#define ta0 $8 -#define a5 $9 -#define ta1 $9 -#define a6 $10 -#define ta2 $10 -#define a7 $11 -#define ta3 $11 -#define t0 $12 /* caller saved */ -#define t1 $13 -#define t2 $14 -#define t3 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 /* callee address for PIC/temp */ -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel temporary */ -#define k1 $27 -#define gp $28 /* global pointer - caller saved for PIC */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* callee saved */ -#define ra $31 /* return address */ - -#endif /* _ASM_REGDEF_H */ diff --git a/include/asm-mips64/resource.h b/include/asm-mips64/resource.h deleted file mode 100644 index 8c924621e89..00000000000 --- a/include/asm-mips64/resource.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1998, 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_RESOURCE_H -#define _ASM_RESOURCE_H - -/* - * Resource limits - */ -#define RLIMIT_CPU 0 /* CPU time in ms */ -#define RLIMIT_FSIZE 1 /* Maximum filesize */ -#define RLIMIT_DATA 2 /* max data size */ -#define RLIMIT_STACK 3 /* max stack size */ -#define RLIMIT_CORE 4 /* max core file size */ -#define RLIMIT_NOFILE 5 /* max number of open files */ -#define RLIMIT_AS 6 /* mapped memory */ -#define RLIMIT_RSS 7 /* max resident set size */ -#define RLIMIT_NPROC 8 /* max number of processes */ -#define RLIMIT_MEMLOCK 9 /* max locked-in-memory address space */ -#define RLIMIT_LOCKS 10 /* maximum file locks held */ - -#define RLIM_NLIMITS 11 /* Number of limit flavors. */ - -#ifdef __KERNEL__ - -/* - * SuS says limits have to be unsigned. - * Which makes a ton more sense anyway. - */ -#define RLIM_INFINITY (~0UL) - -#define INIT_RLIMITS \ -{ \ - { RLIM_INFINITY, RLIM_INFINITY }, \ - { RLIM_INFINITY, RLIM_INFINITY }, \ - { RLIM_INFINITY, RLIM_INFINITY }, \ - { _STK_LIM, RLIM_INFINITY }, \ - { 0, RLIM_INFINITY }, \ - { INR_OPEN, INR_OPEN }, \ - { RLIM_INFINITY, RLIM_INFINITY }, \ - { RLIM_INFINITY, RLIM_INFINITY }, \ - { 0, 0 }, \ - { RLIM_INFINITY, RLIM_INFINITY }, \ - { RLIM_INFINITY, RLIM_INFINITY }, \ -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_RESOURCE_H */ diff --git a/include/asm-mips64/riscos-syscall.h b/include/asm-mips64/riscos-syscall.h deleted file mode 100644 index 4d8eb15461e..00000000000 --- a/include/asm-mips64/riscos-syscall.h +++ /dev/null @@ -1,979 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle - */ -#ifndef _ASM_RISCOS_SYSCALL_H -#define _ASM_RISCOS_SYSCALL_H - -/* - * The syscalls 0 - 3999 are reserved for a down to the root syscall - * compatibility with RISC/os and IRIX. We'll see how to deal with the - * various "real" BSD variants like Ultrix, NetBSD ... - */ - -/* - * SVR4 syscalls are in the range from 1 to 999 - */ -#define __NR_SVR4 0 -#define __NR_SVR4_syscall (__NR_SVR4 + 0) -#define __NR_SVR4_exit (__NR_SVR4 + 1) -#define __NR_SVR4_fork (__NR_SVR4 + 2) -#define __NR_SVR4_read (__NR_SVR4 + 3) -#define __NR_SVR4_write (__NR_SVR4 + 4) -#define __NR_SVR4_open (__NR_SVR4 + 5) -#define __NR_SVR4_close (__NR_SVR4 + 6) -#define __NR_SVR4_wait (__NR_SVR4 + 7) -#define __NR_SVR4_creat (__NR_SVR4 + 8) -#define __NR_SVR4_link (__NR_SVR4 + 9) -#define __NR_SVR4_unlink (__NR_SVR4 + 10) -#define __NR_SVR4_exec (__NR_SVR4 + 11) -#define __NR_SVR4_chdir (__NR_SVR4 + 12) -#define __NR_SVR4_gtime (__NR_SVR4 + 13) -#define __NR_SVR4_mknod (__NR_SVR4 + 14) -#define __NR_SVR4_chmod (__NR_SVR4 + 15) -#define __NR_SVR4_chown (__NR_SVR4 + 16) -#define __NR_SVR4_sbreak (__NR_SVR4 + 17) -#define __NR_SVR4_stat (__NR_SVR4 + 18) -#define __NR_SVR4_lseek (__NR_SVR4 + 19) -#define __NR_SVR4_getpid (__NR_SVR4 + 20) -#define __NR_SVR4_mount (__NR_SVR4 + 21) -#define __NR_SVR4_umount (__NR_SVR4 + 22) -#define __NR_SVR4_setuid (__NR_SVR4 + 23) -#define __NR_SVR4_getuid (__NR_SVR4 + 24) -#define __NR_SVR4_stime (__NR_SVR4 + 25) -#define __NR_SVR4_ptrace (__NR_SVR4 + 26) -#define __NR_SVR4_alarm (__NR_SVR4 + 27) -#define __NR_SVR4_fstat (__NR_SVR4 + 28) -#define __NR_SVR4_pause (__NR_SVR4 + 29) -#define __NR_SVR4_utime (__NR_SVR4 + 30) -#define __NR_SVR4_stty (__NR_SVR4 + 31) -#define __NR_SVR4_gtty (__NR_SVR4 + 32) -#define __NR_SVR4_access (__NR_SVR4 + 33) -#define __NR_SVR4_nice (__NR_SVR4 + 34) -#define __NR_SVR4_statfs (__NR_SVR4 + 35) -#define __NR_SVR4_sync (__NR_SVR4 + 36) -#define __NR_SVR4_kill (__NR_SVR4 + 37) -#define __NR_SVR4_fstatfs (__NR_SVR4 + 38) -#define __NR_SVR4_setpgrp (__NR_SVR4 + 39) -#define __NR_SVR4_cxenix (__NR_SVR4 + 40) -#define __NR_SVR4_dup (__NR_SVR4 + 41) -#define __NR_SVR4_pipe (__NR_SVR4 + 42) -#define __NR_SVR4_times (__NR_SVR4 + 43) -#define __NR_SVR4_profil (__NR_SVR4 + 44) -#define __NR_SVR4_plock (__NR_SVR4 + 45) -#define __NR_SVR4_setgid (__NR_SVR4 + 46) -#define __NR_SVR4_getgid (__NR_SVR4 + 47) -#define __NR_SVR4_sig (__NR_SVR4 + 48) -#define __NR_SVR4_msgsys (__NR_SVR4 + 49) -#define __NR_SVR4_sysmips (__NR_SVR4 + 50) -#define __NR_SVR4_sysacct (__NR_SVR4 + 51) -#define __NR_SVR4_shmsys (__NR_SVR4 + 52) -#define __NR_SVR4_semsys (__NR_SVR4 + 53) -#define __NR_SVR4_ioctl (__NR_SVR4 + 54) -#define __NR_SVR4_uadmin (__NR_SVR4 + 55) -#define __NR_SVR4_exch (__NR_SVR4 + 56) -#define __NR_SVR4_utssys (__NR_SVR4 + 57) -#define __NR_SVR4_fsync (__NR_SVR4 + 58) -#define __NR_SVR4_exece (__NR_SVR4 + 59) -#define __NR_SVR4_umask (__NR_SVR4 + 60) -#define __NR_SVR4_chroot (__NR_SVR4 + 61) -#define __NR_SVR4_fcntl (__NR_SVR4 + 62) -#define __NR_SVR4_ulimit (__NR_SVR4 + 63) -#define __NR_SVR4_reserved1 (__NR_SVR4 + 64) -#define __NR_SVR4_reserved2 (__NR_SVR4 + 65) -#define __NR_SVR4_reserved3 (__NR_SVR4 + 66) -#define __NR_SVR4_reserved4 (__NR_SVR4 + 67) -#define __NR_SVR4_reserved5 (__NR_SVR4 + 68) -#define __NR_SVR4_reserved6 (__NR_SVR4 + 69) -#define __NR_SVR4_advfs (__NR_SVR4 + 70) -#define __NR_SVR4_unadvfs (__NR_SVR4 + 71) -#define __NR_SVR4_unused1 (__NR_SVR4 + 72) -#define __NR_SVR4_unused2 (__NR_SVR4 + 73) -#define __NR_SVR4_rfstart (__NR_SVR4 + 74) -#define __NR_SVR4_unused3 (__NR_SVR4 + 75) -#define __NR_SVR4_rdebug (__NR_SVR4 + 76) -#define __NR_SVR4_rfstop (__NR_SVR4 + 77) -#define __NR_SVR4_rfsys (__NR_SVR4 + 78) -#define __NR_SVR4_rmdir (__NR_SVR4 + 79) -#define __NR_SVR4_mkdir (__NR_SVR4 + 80) -#define __NR_SVR4_getdents (__NR_SVR4 + 81) -#define __NR_SVR4_libattach (__NR_SVR4 + 82) -#define __NR_SVR4_libdetach (__NR_SVR4 + 83) -#define __NR_SVR4_sysfs (__NR_SVR4 + 84) -#define __NR_SVR4_getmsg (__NR_SVR4 + 85) -#define __NR_SVR4_putmsg (__NR_SVR4 + 86) -#define __NR_SVR4_poll (__NR_SVR4 + 87) -#define __NR_SVR4_lstat (__NR_SVR4 + 88) -#define __NR_SVR4_symlink (__NR_SVR4 + 89) -#define __NR_SVR4_readlink (__NR_SVR4 + 90) -#define __NR_SVR4_setgroups (__NR_SVR4 + 91) -#define __NR_SVR4_getgroups (__NR_SVR4 + 92) -#define __NR_SVR4_fchmod (__NR_SVR4 + 93) -#define __NR_SVR4_fchown (__NR_SVR4 + 94) -#define __NR_SVR4_sigprocmask (__NR_SVR4 + 95) -#define __NR_SVR4_sigsuspend (__NR_SVR4 + 96) -#define __NR_SVR4_sigaltstack (__NR_SVR4 + 97) -#define __NR_SVR4_sigaction (__NR_SVR4 + 98) -#define __NR_SVR4_sigpending (__NR_SVR4 + 99) -#define __NR_SVR4_setcontext (__NR_SVR4 + 100) -#define __NR_SVR4_evsys (__NR_SVR4 + 101) -#define __NR_SVR4_evtrapret (__NR_SVR4 + 102) -#define __NR_SVR4_statvfs (__NR_SVR4 + 103) -#define __NR_SVR4_fstatvfs (__NR_SVR4 + 104) -#define __NR_SVR4_reserved7 (__NR_SVR4 + 105) -#define __NR_SVR4_nfssys (__NR_SVR4 + 106) -#define __NR_SVR4_waitid (__NR_SVR4 + 107) -#define __NR_SVR4_sigsendset (__NR_SVR4 + 108) -#define __NR_SVR4_hrtsys (__NR_SVR4 + 109) -#define __NR_SVR4_acancel (__NR_SVR4 + 110) -#define __NR_SVR4_async (__NR_SVR4 + 111) -#define __NR_SVR4_priocntlset (__NR_SVR4 + 112) -#define __NR_SVR4_pathconf (__NR_SVR4 + 113) -#define __NR_SVR4_mincore (__NR_SVR4 + 114) -#define __NR_SVR4_mmap (__NR_SVR4 + 115) -#define __NR_SVR4_mprotect (__NR_SVR4 + 116) -#define __NR_SVR4_munmap (__NR_SVR4 + 117) -#define __NR_SVR4_fpathconf (__NR_SVR4 + 118) -#define __NR_SVR4_vfork (__NR_SVR4 + 119) -#define __NR_SVR4_fchdir (__NR_SVR4 + 120) -#define __NR_SVR4_readv (__NR_SVR4 + 121) -#define __NR_SVR4_writev (__NR_SVR4 + 122) -#define __NR_SVR4_xstat (__NR_SVR4 + 123) -#define __NR_SVR4_lxstat (__NR_SVR4 + 124) -#define __NR_SVR4_fxstat (__NR_SVR4 + 125) -#define __NR_SVR4_xmknod (__NR_SVR4 + 126) -#define __NR_SVR4_clocal (__NR_SVR4 + 127) -#define __NR_SVR4_setrlimit (__NR_SVR4 + 128) -#define __NR_SVR4_getrlimit (__NR_SVR4 + 129) -#define __NR_SVR4_lchown (__NR_SVR4 + 130) -#define __NR_SVR4_memcntl (__NR_SVR4 + 131) -#define __NR_SVR4_getpmsg (__NR_SVR4 + 132) -#define __NR_SVR4_putpmsg (__NR_SVR4 + 133) -#define __NR_SVR4_rename (__NR_SVR4 + 134) -#define __NR_SVR4_nuname (__NR_SVR4 + 135) -#define __NR_SVR4_setegid (__NR_SVR4 + 136) -#define __NR_SVR4_sysconf (__NR_SVR4 + 137) -#define __NR_SVR4_adjtime (__NR_SVR4 + 138) -#define __NR_SVR4_sysinfo (__NR_SVR4 + 139) -#define __NR_SVR4_reserved8 (__NR_SVR4 + 140) -#define __NR_SVR4_seteuid (__NR_SVR4 + 141) -#define __NR_SVR4_PYRAMID_statis (__NR_SVR4 + 142) -#define __NR_SVR4_PYRAMID_tuning (__NR_SVR4 + 143) -#define __NR_SVR4_PYRAMID_forcerr (__NR_SVR4 + 144) -#define __NR_SVR4_PYRAMID_mpcntl (__NR_SVR4 + 145) -#define __NR_SVR4_reserved9 (__NR_SVR4 + 146) -#define __NR_SVR4_reserved10 (__NR_SVR4 + 147) -#define __NR_SVR4_reserved11 (__NR_SVR4 + 148) -#define __NR_SVR4_reserved12 (__NR_SVR4 + 149) -#define __NR_SVR4_reserved13 (__NR_SVR4 + 150) -#define __NR_SVR4_reserved14 (__NR_SVR4 + 151) -#define __NR_SVR4_reserved15 (__NR_SVR4 + 152) -#define __NR_SVR4_reserved16 (__NR_SVR4 + 153) -#define __NR_SVR4_reserved17 (__NR_SVR4 + 154) -#define __NR_SVR4_reserved18 (__NR_SVR4 + 155) -#define __NR_SVR4_reserved19 (__NR_SVR4 + 156) -#define __NR_SVR4_reserved20 (__NR_SVR4 + 157) -#define __NR_SVR4_reserved21 (__NR_SVR4 + 158) -#define __NR_SVR4_reserved22 (__NR_SVR4 + 159) -#define __NR_SVR4_reserved23 (__NR_SVR4 + 160) -#define __NR_SVR4_reserved24 (__NR_SVR4 + 161) -#define __NR_SVR4_reserved25 (__NR_SVR4 + 162) -#define __NR_SVR4_reserved26 (__NR_SVR4 + 163) -#define __NR_SVR4_reserved27 (__NR_SVR4 + 164) -#define __NR_SVR4_reserved28 (__NR_SVR4 + 165) -#define __NR_SVR4_reserved29 (__NR_SVR4 + 166) -#define __NR_SVR4_reserved30 (__NR_SVR4 + 167) -#define __NR_SVR4_reserved31 (__NR_SVR4 + 168) -#define __NR_SVR4_reserved32 (__NR_SVR4 + 169) -#define __NR_SVR4_reserved33 (__NR_SVR4 + 170) -#define __NR_SVR4_reserved34 (__NR_SVR4 + 171) -#define __NR_SVR4_reserved35 (__NR_SVR4 + 172) -#define __NR_SVR4_reserved36 (__NR_SVR4 + 173) -#define __NR_SVR4_reserved37 (__NR_SVR4 + 174) -#define __NR_SVR4_reserved38 (__NR_SVR4 + 175) -#define __NR_SVR4_reserved39 (__NR_SVR4 + 176) -#define __NR_SVR4_reserved40 (__NR_SVR4 + 177) -#define __NR_SVR4_reserved41 (__NR_SVR4 + 178) -#define __NR_SVR4_reserved42 (__NR_SVR4 + 179) -#define __NR_SVR4_reserved43 (__NR_SVR4 + 180) -#define __NR_SVR4_reserved44 (__NR_SVR4 + 181) -#define __NR_SVR4_reserved45 (__NR_SVR4 + 182) -#define __NR_SVR4_reserved46 (__NR_SVR4 + 183) -#define __NR_SVR4_reserved47 (__NR_SVR4 + 184) -#define __NR_SVR4_reserved48 (__NR_SVR4 + 185) -#define __NR_SVR4_reserved49 (__NR_SVR4 + 186) -#define __NR_SVR4_reserved50 (__NR_SVR4 + 187) -#define __NR_SVR4_reserved51 (__NR_SVR4 + 188) -#define __NR_SVR4_reserved52 (__NR_SVR4 + 189) -#define __NR_SVR4_reserved53 (__NR_SVR4 + 190) -#define __NR_SVR4_reserved54 (__NR_SVR4 + 191) -#define __NR_SVR4_reserved55 (__NR_SVR4 + 192) -#define __NR_SVR4_reserved56 (__NR_SVR4 + 193) -#define __NR_SVR4_reserved57 (__NR_SVR4 + 194) -#define __NR_SVR4_reserved58 (__NR_SVR4 + 195) -#define __NR_SVR4_reserved59 (__NR_SVR4 + 196) -#define __NR_SVR4_reserved60 (__NR_SVR4 + 197) -#define __NR_SVR4_reserved61 (__NR_SVR4 + 198) -#define __NR_SVR4_reserved62 (__NR_SVR4 + 199) -#define __NR_SVR4_reserved63 (__NR_SVR4 + 200) -#define __NR_SVR4_aread (__NR_SVR4 + 201) -#define __NR_SVR4_awrite (__NR_SVR4 + 202) -#define __NR_SVR4_listio (__NR_SVR4 + 203) -#define __NR_SVR4_mips_acancel (__NR_SVR4 + 204) -#define __NR_SVR4_astatus (__NR_SVR4 + 205) -#define __NR_SVR4_await (__NR_SVR4 + 206) -#define __NR_SVR4_areadv (__NR_SVR4 + 207) -#define __NR_SVR4_awritev (__NR_SVR4 + 208) -#define __NR_SVR4_MIPS_reserved1 (__NR_SVR4 + 209) -#define __NR_SVR4_MIPS_reserved2 (__NR_SVR4 + 210) -#define __NR_SVR4_MIPS_reserved3 (__NR_SVR4 + 211) -#define __NR_SVR4_MIPS_reserved4 (__NR_SVR4 + 212) -#define __NR_SVR4_MIPS_reserved5 (__NR_SVR4 + 213) -#define __NR_SVR4_MIPS_reserved6 (__NR_SVR4 + 214) -#define __NR_SVR4_MIPS_reserved7 (__NR_SVR4 + 215) -#define __NR_SVR4_MIPS_reserved8 (__NR_SVR4 + 216) -#define __NR_SVR4_MIPS_reserved9 (__NR_SVR4 + 217) -#define __NR_SVR4_MIPS_reserved10 (__NR_SVR4 + 218) -#define __NR_SVR4_MIPS_reserved11 (__NR_SVR4 + 219) -#define __NR_SVR4_MIPS_reserved12 (__NR_SVR4 + 220) -#define __NR_SVR4_CDC_reserved1 (__NR_SVR4 + 221) -#define __NR_SVR4_CDC_reserved2 (__NR_SVR4 + 222) -#define __NR_SVR4_CDC_reserved3 (__NR_SVR4 + 223) -#define __NR_SVR4_CDC_reserved4 (__NR_SVR4 + 224) -#define __NR_SVR4_CDC_reserved5 (__NR_SVR4 + 225) -#define __NR_SVR4_CDC_reserved6 (__NR_SVR4 + 226) -#define __NR_SVR4_CDC_reserved7 (__NR_SVR4 + 227) -#define __NR_SVR4_CDC_reserved8 (__NR_SVR4 + 228) -#define __NR_SVR4_CDC_reserved9 (__NR_SVR4 + 229) -#define __NR_SVR4_CDC_reserved10 (__NR_SVR4 + 230) -#define __NR_SVR4_CDC_reserved11 (__NR_SVR4 + 231) -#define __NR_SVR4_CDC_reserved12 (__NR_SVR4 + 232) -#define __NR_SVR4_CDC_reserved13 (__NR_SVR4 + 233) -#define __NR_SVR4_CDC_reserved14 (__NR_SVR4 + 234) -#define __NR_SVR4_CDC_reserved15 (__NR_SVR4 + 235) -#define __NR_SVR4_CDC_reserved16 (__NR_SVR4 + 236) -#define __NR_SVR4_CDC_reserved17 (__NR_SVR4 + 237) -#define __NR_SVR4_CDC_reserved18 (__NR_SVR4 + 238) -#define __NR_SVR4_CDC_reserved19 (__NR_SVR4 + 239) -#define __NR_SVR4_CDC_reserved20 (__NR_SVR4 + 240) - -/* - * SYS V syscalls are in the range from 1000 to 1999 - */ -#define __NR_SYSV 1000 -#define __NR_SYSV_syscall (__NR_SYSV + 0) -#define __NR_SYSV_exit (__NR_SYSV + 1) -#define __NR_SYSV_fork (__NR_SYSV + 2) -#define __NR_SYSV_read (__NR_SYSV + 3) -#define __NR_SYSV_write (__NR_SYSV + 4) -#define __NR_SYSV_open (__NR_SYSV + 5) -#define __NR_SYSV_close (__NR_SYSV + 6) -#define __NR_SYSV_wait (__NR_SYSV + 7) -#define __NR_SYSV_creat (__NR_SYSV + 8) -#define __NR_SYSV_link (__NR_SYSV + 9) -#define __NR_SYSV_unlink (__NR_SYSV + 10) -#define __NR_SYSV_execv (__NR_SYSV + 11) -#define __NR_SYSV_chdir (__NR_SYSV + 12) -#define __NR_SYSV_time (__NR_SYSV + 13) -#define __NR_SYSV_mknod (__NR_SYSV + 14) -#define __NR_SYSV_chmod (__NR_SYSV + 15) -#define __NR_SYSV_chown (__NR_SYSV + 16) -#define __NR_SYSV_brk (__NR_SYSV + 17) -#define __NR_SYSV_stat (__NR_SYSV + 18) -#define __NR_SYSV_lseek (__NR_SYSV + 19) -#define __NR_SYSV_getpid (__NR_SYSV + 20) -#define __NR_SYSV_mount (__NR_SYSV + 21) -#define __NR_SYSV_umount (__NR_SYSV + 22) -#define __NR_SYSV_setuid (__NR_SYSV + 23) -#define __NR_SYSV_getuid (__NR_SYSV + 24) -#define __NR_SYSV_stime (__NR_SYSV + 25) -#define __NR_SYSV_ptrace (__NR_SYSV + 26) -#define __NR_SYSV_alarm (__NR_SYSV + 27) -#define __NR_SYSV_fstat (__NR_SYSV + 28) -#define __NR_SYSV_pause (__NR_SYSV + 29) -#define __NR_SYSV_utime (__NR_SYSV + 30) -#define __NR_SYSV_stty (__NR_SYSV + 31) -#define __NR_SYSV_gtty (__NR_SYSV + 32) -#define __NR_SYSV_access (__NR_SYSV + 33) -#define __NR_SYSV_nice (__NR_SYSV + 34) -#define __NR_SYSV_statfs (__NR_SYSV + 35) -#define __NR_SYSV_sync (__NR_SYSV + 36) -#define __NR_SYSV_kill (__NR_SYSV + 37) -#define __NR_SYSV_fstatfs (__NR_SYSV + 38) -#define __NR_SYSV_setpgrp (__NR_SYSV + 39) -#define __NR_SYSV_syssgi (__NR_SYSV + 40) -#define __NR_SYSV_dup (__NR_SYSV + 41) -#define __NR_SYSV_pipe (__NR_SYSV + 42) -#define __NR_SYSV_times (__NR_SYSV + 43) -#define __NR_SYSV_profil (__NR_SYSV + 44) -#define __NR_SYSV_plock (__NR_SYSV + 45) -#define __NR_SYSV_setgid (__NR_SYSV + 46) -#define __NR_SYSV_getgid (__NR_SYSV + 47) -#define __NR_SYSV_sig (__NR_SYSV + 48) -#define __NR_SYSV_msgsys (__NR_SYSV + 49) -#define __NR_SYSV_sysmips (__NR_SYSV + 50) -#define __NR_SYSV_acct (__NR_SYSV + 51) -#define __NR_SYSV_shmsys (__NR_SYSV + 52) -#define __NR_SYSV_semsys (__NR_SYSV + 53) -#define __NR_SYSV_ioctl (__NR_SYSV + 54) -#define __NR_SYSV_uadmin (__NR_SYSV + 55) -#define __NR_SYSV_sysmp (__NR_SYSV + 56) -#define __NR_SYSV_utssys (__NR_SYSV + 57) -#define __NR_SYSV_USG_reserved1 (__NR_SYSV + 58) -#define __NR_SYSV_execve (__NR_SYSV + 59) -#define __NR_SYSV_umask (__NR_SYSV + 60) -#define __NR_SYSV_chroot (__NR_SYSV + 61) -#define __NR_SYSV_fcntl (__NR_SYSV + 62) -#define __NR_SYSV_ulimit (__NR_SYSV + 63) -#define __NR_SYSV_SAFARI4_reserved1 (__NR_SYSV + 64) -#define __NR_SYSV_SAFARI4_reserved2 (__NR_SYSV + 65) -#define __NR_SYSV_SAFARI4_reserved3 (__NR_SYSV + 66) -#define __NR_SYSV_SAFARI4_reserved4 (__NR_SYSV + 67) -#define __NR_SYSV_SAFARI4_reserved5 (__NR_SYSV + 68) -#define __NR_SYSV_SAFARI4_reserved6 (__NR_SYSV + 69) -#define __NR_SYSV_advfs (__NR_SYSV + 70) -#define __NR_SYSV_unadvfs (__NR_SYSV + 71) -#define __NR_SYSV_rmount (__NR_SYSV + 72) -#define __NR_SYSV_rumount (__NR_SYSV + 73) -#define __NR_SYSV_rfstart (__NR_SYSV + 74) -#define __NR_SYSV_getrlimit64 (__NR_SYSV + 75) -#define __NR_SYSV_setrlimit64 (__NR_SYSV + 76) -#define __NR_SYSV_nanosleep (__NR_SYSV + 77) -#define __NR_SYSV_lseek64 (__NR_SYSV + 78) -#define __NR_SYSV_rmdir (__NR_SYSV + 79) -#define __NR_SYSV_mkdir (__NR_SYSV + 80) -#define __NR_SYSV_getdents (__NR_SYSV + 81) -#define __NR_SYSV_sginap (__NR_SYSV + 82) -#define __NR_SYSV_sgikopt (__NR_SYSV + 83) -#define __NR_SYSV_sysfs (__NR_SYSV + 84) -#define __NR_SYSV_getmsg (__NR_SYSV + 85) -#define __NR_SYSV_putmsg (__NR_SYSV + 86) -#define __NR_SYSV_poll (__NR_SYSV + 87) -#define __NR_SYSV_sigreturn (__NR_SYSV + 88) -#define __NR_SYSV_accept (__NR_SYSV + 89) -#define __NR_SYSV_bind (__NR_SYSV + 90) -#define __NR_SYSV_connect (__NR_SYSV + 91) -#define __NR_SYSV_gethostid (__NR_SYSV + 92) -#define __NR_SYSV_getpeername (__NR_SYSV + 93) -#define __NR_SYSV_getsockname (__NR_SYSV + 94) -#define __NR_SYSV_getsockopt (__NR_SYSV + 95) -#define __NR_SYSV_listen (__NR_SYSV + 96) -#define __NR_SYSV_recv (__NR_SYSV + 97) -#define __NR_SYSV_recvfrom (__NR_SYSV + 98) -#define __NR_SYSV_recvmsg (__NR_SYSV + 99) -#define __NR_SYSV_select (__NR_SYSV + 100) -#define __NR_SYSV_send (__NR_SYSV + 101) -#define __NR_SYSV_sendmsg (__NR_SYSV + 102) -#define __NR_SYSV_sendto (__NR_SYSV + 103) -#define __NR_SYSV_sethostid (__NR_SYSV + 104) -#define __NR_SYSV_setsockopt (__NR_SYSV + 105) -#define __NR_SYSV_shutdown (__NR_SYSV + 106) -#define __NR_SYSV_socket (__NR_SYSV + 107) -#define __NR_SYSV_gethostname (__NR_SYSV + 108) -#define __NR_SYSV_sethostname (__NR_SYSV + 109) -#define __NR_SYSV_getdomainname (__NR_SYSV + 110) -#define __NR_SYSV_setdomainname (__NR_SYSV + 111) -#define __NR_SYSV_truncate (__NR_SYSV + 112) -#define __NR_SYSV_ftruncate (__NR_SYSV + 113) -#define __NR_SYSV_rename (__NR_SYSV + 114) -#define __NR_SYSV_symlink (__NR_SYSV + 115) -#define __NR_SYSV_readlink (__NR_SYSV + 116) -#define __NR_SYSV_lstat (__NR_SYSV + 117) -#define __NR_SYSV_nfsmount (__NR_SYSV + 118) -#define __NR_SYSV_nfssvc (__NR_SYSV + 119) -#define __NR_SYSV_getfh (__NR_SYSV + 120) -#define __NR_SYSV_async_daemon (__NR_SYSV + 121) -#define __NR_SYSV_exportfs (__NR_SYSV + 122) -#define __NR_SYSV_setregid (__NR_SYSV + 123) -#define __NR_SYSV_setreuid (__NR_SYSV + 124) -#define __NR_SYSV_getitimer (__NR_SYSV + 125) -#define __NR_SYSV_setitimer (__NR_SYSV + 126) -#define __NR_SYSV_adjtime (__NR_SYSV + 127) -#define __NR_SYSV_BSD_getime (__NR_SYSV + 128) -#define __NR_SYSV_sproc (__NR_SYSV + 129) -#define __NR_SYSV_prctl (__NR_SYSV + 130) -#define __NR_SYSV_procblk (__NR_SYSV + 131) -#define __NR_SYSV_sprocsp (__NR_SYSV + 132) -#define __NR_SYSV_sgigsc (__NR_SYSV + 133) -#define __NR_SYSV_mmap (__NR_SYSV + 134) -#define __NR_SYSV_munmap (__NR_SYSV + 135) -#define __NR_SYSV_mprotect (__NR_SYSV + 136) -#define __NR_SYSV_msync (__NR_SYSV + 137) -#define __NR_SYSV_madvise (__NR_SYSV + 138) -#define __NR_SYSV_pagelock (__NR_SYSV + 139) -#define __NR_SYSV_getpagesize (__NR_SYSV + 140) -#define __NR_SYSV_quotactl (__NR_SYSV + 141) -#define __NR_SYSV_libdetach (__NR_SYSV + 142) -#define __NR_SYSV_BSDgetpgrp (__NR_SYSV + 143) -#define __NR_SYSV_BSDsetpgrp (__NR_SYSV + 144) -#define __NR_SYSV_vhangup (__NR_SYSV + 145) -#define __NR_SYSV_fsync (__NR_SYSV + 146) -#define __NR_SYSV_fchdir (__NR_SYSV + 147) -#define __NR_SYSV_getrlimit (__NR_SYSV + 148) -#define __NR_SYSV_setrlimit (__NR_SYSV + 149) -#define __NR_SYSV_cacheflush (__NR_SYSV + 150) -#define __NR_SYSV_cachectl (__NR_SYSV + 151) -#define __NR_SYSV_fchown (__NR_SYSV + 152) -#define __NR_SYSV_fchmod (__NR_SYSV + 153) -#define __NR_SYSV_wait3 (__NR_SYSV + 154) -#define __NR_SYSV_socketpair (__NR_SYSV + 155) -#define __NR_SYSV_sysinfo (__NR_SYSV + 156) -#define __NR_SYSV_nuname (__NR_SYSV + 157) -#define __NR_SYSV_xstat (__NR_SYSV + 158) -#define __NR_SYSV_lxstat (__NR_SYSV + 159) -#define __NR_SYSV_fxstat (__NR_SYSV + 160) -#define __NR_SYSV_xmknod (__NR_SYSV + 161) -#define __NR_SYSV_ksigaction (__NR_SYSV + 162) -#define __NR_SYSV_sigpending (__NR_SYSV + 163) -#define __NR_SYSV_sigprocmask (__NR_SYSV + 164) -#define __NR_SYSV_sigsuspend (__NR_SYSV + 165) -#define __NR_SYSV_sigpoll (__NR_SYSV + 166) -#define __NR_SYSV_swapctl (__NR_SYSV + 167) -#define __NR_SYSV_getcontext (__NR_SYSV + 168) -#define __NR_SYSV_setcontext (__NR_SYSV + 169) -#define __NR_SYSV_waitsys (__NR_SYSV + 170) -#define __NR_SYSV_sigstack (__NR_SYSV + 171) -#define __NR_SYSV_sigaltstack (__NR_SYSV + 172) -#define __NR_SYSV_sigsendset (__NR_SYSV + 173) -#define __NR_SYSV_statvfs (__NR_SYSV + 174) -#define __NR_SYSV_fstatvfs (__NR_SYSV + 175) -#define __NR_SYSV_getpmsg (__NR_SYSV + 176) -#define __NR_SYSV_putpmsg (__NR_SYSV + 177) -#define __NR_SYSV_lchown (__NR_SYSV + 178) -#define __NR_SYSV_priocntl (__NR_SYSV + 179) -#define __NR_SYSV_ksigqueue (__NR_SYSV + 180) -#define __NR_SYSV_readv (__NR_SYSV + 181) -#define __NR_SYSV_writev (__NR_SYSV + 182) -#define __NR_SYSV_truncate64 (__NR_SYSV + 183) -#define __NR_SYSV_ftruncate64 (__NR_SYSV + 184) -#define __NR_SYSV_mmap64 (__NR_SYSV + 185) -#define __NR_SYSV_dmi (__NR_SYSV + 186) -#define __NR_SYSV_pread (__NR_SYSV + 187) -#define __NR_SYSV_pwrite (__NR_SYSV + 188) - -/* - * BSD 4.3 syscalls are in the range from 2000 to 2999 - */ -#define __NR_BSD43 2000 -#define __NR_BSD43_syscall (__NR_BSD43 + 0) -#define __NR_BSD43_exit (__NR_BSD43 + 1) -#define __NR_BSD43_fork (__NR_BSD43 + 2) -#define __NR_BSD43_read (__NR_BSD43 + 3) -#define __NR_BSD43_write (__NR_BSD43 + 4) -#define __NR_BSD43_open (__NR_BSD43 + 5) -#define __NR_BSD43_close (__NR_BSD43 + 6) -#define __NR_BSD43_wait (__NR_BSD43 + 7) -#define __NR_BSD43_creat (__NR_BSD43 + 8) -#define __NR_BSD43_link (__NR_BSD43 + 9) -#define __NR_BSD43_unlink (__NR_BSD43 + 10) -#define __NR_BSD43_exec (__NR_BSD43 + 11) -#define __NR_BSD43_chdir (__NR_BSD43 + 12) -#define __NR_BSD43_time (__NR_BSD43 + 13) -#define __NR_BSD43_mknod (__NR_BSD43 + 14) -#define __NR_BSD43_chmod (__NR_BSD43 + 15) -#define __NR_BSD43_chown (__NR_BSD43 + 16) -#define __NR_BSD43_sbreak (__NR_BSD43 + 17) -#define __NR_BSD43_oldstat (__NR_BSD43 + 18) -#define __NR_BSD43_lseek (__NR_BSD43 + 19) -#define __NR_BSD43_getpid (__NR_BSD43 + 20) -#define __NR_BSD43_oldmount (__NR_BSD43 + 21) -#define __NR_BSD43_umount (__NR_BSD43 + 22) -#define __NR_BSD43_setuid (__NR_BSD43 + 23) -#define __NR_BSD43_getuid (__NR_BSD43 + 24) -#define __NR_BSD43_stime (__NR_BSD43 + 25) -#define __NR_BSD43_ptrace (__NR_BSD43 + 26) -#define __NR_BSD43_alarm (__NR_BSD43 + 27) -#define __NR_BSD43_oldfstat (__NR_BSD43 + 28) -#define __NR_BSD43_pause (__NR_BSD43 + 29) -#define __NR_BSD43_utime (__NR_BSD43 + 30) -#define __NR_BSD43_stty (__NR_BSD43 + 31) -#define __NR_BSD43_gtty (__NR_BSD43 + 32) -#define __NR_BSD43_access (__NR_BSD43 + 33) -#define __NR_BSD43_nice (__NR_BSD43 + 34) -#define __NR_BSD43_ftime (__NR_BSD43 + 35) -#define __NR_BSD43_sync (__NR_BSD43 + 36) -#define __NR_BSD43_kill (__NR_BSD43 + 37) -#define __NR_BSD43_stat (__NR_BSD43 + 38) -#define __NR_BSD43_oldsetpgrp (__NR_BSD43 + 39) -#define __NR_BSD43_lstat (__NR_BSD43 + 40) -#define __NR_BSD43_dup (__NR_BSD43 + 41) -#define __NR_BSD43_pipe (__NR_BSD43 + 42) -#define __NR_BSD43_times (__NR_BSD43 + 43) -#define __NR_BSD43_profil (__NR_BSD43 + 44) -#define __NR_BSD43_msgsys (__NR_BSD43 + 45) -#define __NR_BSD43_setgid (__NR_BSD43 + 46) -#define __NR_BSD43_getgid (__NR_BSD43 + 47) -#define __NR_BSD43_ssig (__NR_BSD43 + 48) -#define __NR_BSD43_reserved1 (__NR_BSD43 + 49) -#define __NR_BSD43_reserved2 (__NR_BSD43 + 50) -#define __NR_BSD43_sysacct (__NR_BSD43 + 51) -#define __NR_BSD43_phys (__NR_BSD43 + 52) -#define __NR_BSD43_lock (__NR_BSD43 + 53) -#define __NR_BSD43_ioctl (__NR_BSD43 + 54) -#define __NR_BSD43_reboot (__NR_BSD43 + 55) -#define __NR_BSD43_mpxchan (__NR_BSD43 + 56) -#define __NR_BSD43_symlink (__NR_BSD43 + 57) -#define __NR_BSD43_readlink (__NR_BSD43 + 58) -#define __NR_BSD43_execve (__NR_BSD43 + 59) -#define __NR_BSD43_umask (__NR_BSD43 + 60) -#define __NR_BSD43_chroot (__NR_BSD43 + 61) -#define __NR_BSD43_fstat (__NR_BSD43 + 62) -#define __NR_BSD43_reserved3 (__NR_BSD43 + 63) -#define __NR_BSD43_getpagesize (__NR_BSD43 + 64) -#define __NR_BSD43_mremap (__NR_BSD43 + 65) -#define __NR_BSD43_vfork (__NR_BSD43 + 66) -#define __NR_BSD43_vread (__NR_BSD43 + 67) -#define __NR_BSD43_vwrite (__NR_BSD43 + 68) -#define __NR_BSD43_sbrk (__NR_BSD43 + 69) -#define __NR_BSD43_sstk (__NR_BSD43 + 70) -#define __NR_BSD43_mmap (__NR_BSD43 + 71) -#define __NR_BSD43_vadvise (__NR_BSD43 + 72) -#define __NR_BSD43_munmap (__NR_BSD43 + 73) -#define __NR_BSD43_mprotect (__NR_BSD43 + 74) -#define __NR_BSD43_madvise (__NR_BSD43 + 75) -#define __NR_BSD43_vhangup (__NR_BSD43 + 76) -#define __NR_BSD43_vlimit (__NR_BSD43 + 77) -#define __NR_BSD43_mincore (__NR_BSD43 + 78) -#define __NR_BSD43_getgroups (__NR_BSD43 + 79) -#define __NR_BSD43_setgroups (__NR_BSD43 + 80) -#define __NR_BSD43_getpgrp (__NR_BSD43 + 81) -#define __NR_BSD43_setpgrp (__NR_BSD43 + 82) -#define __NR_BSD43_setitimer (__NR_BSD43 + 83) -#define __NR_BSD43_wait3 (__NR_BSD43 + 84) -#define __NR_BSD43_swapon (__NR_BSD43 + 85) -#define __NR_BSD43_getitimer (__NR_BSD43 + 86) -#define __NR_BSD43_gethostname (__NR_BSD43 + 87) -#define __NR_BSD43_sethostname (__NR_BSD43 + 88) -#define __NR_BSD43_getdtablesize (__NR_BSD43 + 89) -#define __NR_BSD43_dup2 (__NR_BSD43 + 90) -#define __NR_BSD43_getdopt (__NR_BSD43 + 91) -#define __NR_BSD43_fcntl (__NR_BSD43 + 92) -#define __NR_BSD43_select (__NR_BSD43 + 93) -#define __NR_BSD43_setdopt (__NR_BSD43 + 94) -#define __NR_BSD43_fsync (__NR_BSD43 + 95) -#define __NR_BSD43_setpriority (__NR_BSD43 + 96) -#define __NR_BSD43_socket (__NR_BSD43 + 97) -#define __NR_BSD43_connect (__NR_BSD43 + 98) -#define __NR_BSD43_oldaccept (__NR_BSD43 + 99) -#define __NR_BSD43_getpriority (__NR_BSD43 + 100) -#define __NR_BSD43_send (__NR_BSD43 + 101) -#define __NR_BSD43_recv (__NR_BSD43 + 102) -#define __NR_BSD43_sigreturn (__NR_BSD43 + 103) -#define __NR_BSD43_bind (__NR_BSD43 + 104) -#define __NR_BSD43_setsockopt (__NR_BSD43 + 105) -#define __NR_BSD43_listen (__NR_BSD43 + 106) -#define __NR_BSD43_vtimes (__NR_BSD43 + 107) -#define __NR_BSD43_sigvec (__NR_BSD43 + 108) -#define __NR_BSD43_sigblock (__NR_BSD43 + 109) -#define __NR_BSD43_sigsetmask (__NR_BSD43 + 110) -#define __NR_BSD43_sigpause (__NR_BSD43 + 111) -#define __NR_BSD43_sigstack (__NR_BSD43 + 112) -#define __NR_BSD43_oldrecvmsg (__NR_BSD43 + 113) -#define __NR_BSD43_oldsendmsg (__NR_BSD43 + 114) -#define __NR_BSD43_vtrace (__NR_BSD43 + 115) -#define __NR_BSD43_gettimeofday (__NR_BSD43 + 116) -#define __NR_BSD43_getrusage (__NR_BSD43 + 117) -#define __NR_BSD43_getsockopt (__NR_BSD43 + 118) -#define __NR_BSD43_reserved4 (__NR_BSD43 + 119) -#define __NR_BSD43_readv (__NR_BSD43 + 120) -#define __NR_BSD43_writev (__NR_BSD43 + 121) -#define __NR_BSD43_settimeofday (__NR_BSD43 + 122) -#define __NR_BSD43_fchown (__NR_BSD43 + 123) -#define __NR_BSD43_fchmod (__NR_BSD43 + 124) -#define __NR_BSD43_oldrecvfrom (__NR_BSD43 + 125) -#define __NR_BSD43_setreuid (__NR_BSD43 + 126) -#define __NR_BSD43_setregid (__NR_BSD43 + 127) -#define __NR_BSD43_rename (__NR_BSD43 + 128) -#define __NR_BSD43_truncate (__NR_BSD43 + 129) -#define __NR_BSD43_ftruncate (__NR_BSD43 + 130) -#define __NR_BSD43_flock (__NR_BSD43 + 131) -#define __NR_BSD43_semsys (__NR_BSD43 + 132) -#define __NR_BSD43_sendto (__NR_BSD43 + 133) -#define __NR_BSD43_shutdown (__NR_BSD43 + 134) -#define __NR_BSD43_socketpair (__NR_BSD43 + 135) -#define __NR_BSD43_mkdir (__NR_BSD43 + 136) -#define __NR_BSD43_rmdir (__NR_BSD43 + 137) -#define __NR_BSD43_utimes (__NR_BSD43 + 138) -#define __NR_BSD43_sigcleanup (__NR_BSD43 + 139) -#define __NR_BSD43_adjtime (__NR_BSD43 + 140) -#define __NR_BSD43_oldgetpeername (__NR_BSD43 + 141) -#define __NR_BSD43_gethostid (__NR_BSD43 + 142) -#define __NR_BSD43_sethostid (__NR_BSD43 + 143) -#define __NR_BSD43_getrlimit (__NR_BSD43 + 144) -#define __NR_BSD43_setrlimit (__NR_BSD43 + 145) -#define __NR_BSD43_killpg (__NR_BSD43 + 146) -#define __NR_BSD43_shmsys (__NR_BSD43 + 147) -#define __NR_BSD43_quota (__NR_BSD43 + 148) -#define __NR_BSD43_qquota (__NR_BSD43 + 149) -#define __NR_BSD43_oldgetsockname (__NR_BSD43 + 150) -#define __NR_BSD43_sysmips (__NR_BSD43 + 151) -#define __NR_BSD43_cacheflush (__NR_BSD43 + 152) -#define __NR_BSD43_cachectl (__NR_BSD43 + 153) -#define __NR_BSD43_debug (__NR_BSD43 + 154) -#define __NR_BSD43_reserved5 (__NR_BSD43 + 155) -#define __NR_BSD43_reserved6 (__NR_BSD43 + 156) -#define __NR_BSD43_nfs_mount (__NR_BSD43 + 157) -#define __NR_BSD43_nfs_svc (__NR_BSD43 + 158) -#define __NR_BSD43_getdirentries (__NR_BSD43 + 159) -#define __NR_BSD43_statfs (__NR_BSD43 + 160) -#define __NR_BSD43_fstatfs (__NR_BSD43 + 161) -#define __NR_BSD43_unmount (__NR_BSD43 + 162) -#define __NR_BSD43_async_daemon (__NR_BSD43 + 163) -#define __NR_BSD43_nfs_getfh (__NR_BSD43 + 164) -#define __NR_BSD43_getdomainname (__NR_BSD43 + 165) -#define __NR_BSD43_setdomainname (__NR_BSD43 + 166) -#define __NR_BSD43_pcfs_mount (__NR_BSD43 + 167) -#define __NR_BSD43_quotactl (__NR_BSD43 + 168) -#define __NR_BSD43_oldexportfs (__NR_BSD43 + 169) -#define __NR_BSD43_smount (__NR_BSD43 + 170) -#define __NR_BSD43_mipshwconf (__NR_BSD43 + 171) -#define __NR_BSD43_exportfs (__NR_BSD43 + 172) -#define __NR_BSD43_nfsfh_open (__NR_BSD43 + 173) -#define __NR_BSD43_libattach (__NR_BSD43 + 174) -#define __NR_BSD43_libdetach (__NR_BSD43 + 175) -#define __NR_BSD43_accept (__NR_BSD43 + 176) -#define __NR_BSD43_reserved7 (__NR_BSD43 + 177) -#define __NR_BSD43_reserved8 (__NR_BSD43 + 178) -#define __NR_BSD43_recvmsg (__NR_BSD43 + 179) -#define __NR_BSD43_recvfrom (__NR_BSD43 + 180) -#define __NR_BSD43_sendmsg (__NR_BSD43 + 181) -#define __NR_BSD43_getpeername (__NR_BSD43 + 182) -#define __NR_BSD43_getsockname (__NR_BSD43 + 183) -#define __NR_BSD43_aread (__NR_BSD43 + 184) -#define __NR_BSD43_awrite (__NR_BSD43 + 185) -#define __NR_BSD43_listio (__NR_BSD43 + 186) -#define __NR_BSD43_acancel (__NR_BSD43 + 187) -#define __NR_BSD43_astatus (__NR_BSD43 + 188) -#define __NR_BSD43_await (__NR_BSD43 + 189) -#define __NR_BSD43_areadv (__NR_BSD43 + 190) -#define __NR_BSD43_awritev (__NR_BSD43 + 191) - -/* - * POSIX syscalls are in the range from 3000 to 3999 - */ -#define __NR_POSIX 3000 -#define __NR_POSIX_syscall (__NR_POSIX + 0) -#define __NR_POSIX_exit (__NR_POSIX + 1) -#define __NR_POSIX_fork (__NR_POSIX + 2) -#define __NR_POSIX_read (__NR_POSIX + 3) -#define __NR_POSIX_write (__NR_POSIX + 4) -#define __NR_POSIX_open (__NR_POSIX + 5) -#define __NR_POSIX_close (__NR_POSIX + 6) -#define __NR_POSIX_wait (__NR_POSIX + 7) -#define __NR_POSIX_creat (__NR_POSIX + 8) -#define __NR_POSIX_link (__NR_POSIX + 9) -#define __NR_POSIX_unlink (__NR_POSIX + 10) -#define __NR_POSIX_exec (__NR_POSIX + 11) -#define __NR_POSIX_chdir (__NR_POSIX + 12) -#define __NR_POSIX_gtime (__NR_POSIX + 13) -#define __NR_POSIX_mknod (__NR_POSIX + 14) -#define __NR_POSIX_chmod (__NR_POSIX + 15) -#define __NR_POSIX_chown (__NR_POSIX + 16) -#define __NR_POSIX_sbreak (__NR_POSIX + 17) -#define __NR_POSIX_stat (__NR_POSIX + 18) -#define __NR_POSIX_lseek (__NR_POSIX + 19) -#define __NR_POSIX_getpid (__NR_POSIX + 20) -#define __NR_POSIX_mount (__NR_POSIX + 21) -#define __NR_POSIX_umount (__NR_POSIX + 22) -#define __NR_POSIX_setuid (__NR_POSIX + 23) -#define __NR_POSIX_getuid (__NR_POSIX + 24) -#define __NR_POSIX_stime (__NR_POSIX + 25) -#define __NR_POSIX_ptrace (__NR_POSIX + 26) -#define __NR_POSIX_alarm (__NR_POSIX + 27) -#define __NR_POSIX_fstat (__NR_POSIX + 28) -#define __NR_POSIX_pause (__NR_POSIX + 29) -#define __NR_POSIX_utime (__NR_POSIX + 30) -#define __NR_POSIX_stty (__NR_POSIX + 31) -#define __NR_POSIX_gtty (__NR_POSIX + 32) -#define __NR_POSIX_access (__NR_POSIX + 33) -#define __NR_POSIX_nice (__NR_POSIX + 34) -#define __NR_POSIX_statfs (__NR_POSIX + 35) -#define __NR_POSIX_sync (__NR_POSIX + 36) -#define __NR_POSIX_kill (__NR_POSIX + 37) -#define __NR_POSIX_fstatfs (__NR_POSIX + 38) -#define __NR_POSIX_getpgrp (__NR_POSIX + 39) -#define __NR_POSIX_syssgi (__NR_POSIX + 40) -#define __NR_POSIX_dup (__NR_POSIX + 41) -#define __NR_POSIX_pipe (__NR_POSIX + 42) -#define __NR_POSIX_times (__NR_POSIX + 43) -#define __NR_POSIX_profil (__NR_POSIX + 44) -#define __NR_POSIX_lock (__NR_POSIX + 45) -#define __NR_POSIX_setgid (__NR_POSIX + 46) -#define __NR_POSIX_getgid (__NR_POSIX + 47) -#define __NR_POSIX_sig (__NR_POSIX + 48) -#define __NR_POSIX_msgsys (__NR_POSIX + 49) -#define __NR_POSIX_sysmips (__NR_POSIX + 50) -#define __NR_POSIX_sysacct (__NR_POSIX + 51) -#define __NR_POSIX_shmsys (__NR_POSIX + 52) -#define __NR_POSIX_semsys (__NR_POSIX + 53) -#define __NR_POSIX_ioctl (__NR_POSIX + 54) -#define __NR_POSIX_uadmin (__NR_POSIX + 55) -#define __NR_POSIX_exch (__NR_POSIX + 56) -#define __NR_POSIX_utssys (__NR_POSIX + 57) -#define __NR_POSIX_USG_reserved1 (__NR_POSIX + 58) -#define __NR_POSIX_exece (__NR_POSIX + 59) -#define __NR_POSIX_umask (__NR_POSIX + 60) -#define __NR_POSIX_chroot (__NR_POSIX + 61) -#define __NR_POSIX_fcntl (__NR_POSIX + 62) -#define __NR_POSIX_ulimit (__NR_POSIX + 63) -#define __NR_POSIX_SAFARI4_reserved1 (__NR_POSIX + 64) -#define __NR_POSIX_SAFARI4_reserved2 (__NR_POSIX + 65) -#define __NR_POSIX_SAFARI4_reserved3 (__NR_POSIX + 66) -#define __NR_POSIX_SAFARI4_reserved4 (__NR_POSIX + 67) -#define __NR_POSIX_SAFARI4_reserved5 (__NR_POSIX + 68) -#define __NR_POSIX_SAFARI4_reserved6 (__NR_POSIX + 69) -#define __NR_POSIX_advfs (__NR_POSIX + 70) -#define __NR_POSIX_unadvfs (__NR_POSIX + 71) -#define __NR_POSIX_rmount (__NR_POSIX + 72) -#define __NR_POSIX_rumount (__NR_POSIX + 73) -#define __NR_POSIX_rfstart (__NR_POSIX + 74) -#define __NR_POSIX_reserved1 (__NR_POSIX + 75) -#define __NR_POSIX_rdebug (__NR_POSIX + 76) -#define __NR_POSIX_rfstop (__NR_POSIX + 77) -#define __NR_POSIX_rfsys (__NR_POSIX + 78) -#define __NR_POSIX_rmdir (__NR_POSIX + 79) -#define __NR_POSIX_mkdir (__NR_POSIX + 80) -#define __NR_POSIX_getdents (__NR_POSIX + 81) -#define __NR_POSIX_sginap (__NR_POSIX + 82) -#define __NR_POSIX_sgikopt (__NR_POSIX + 83) -#define __NR_POSIX_sysfs (__NR_POSIX + 84) -#define __NR_POSIX_getmsg (__NR_POSIX + 85) -#define __NR_POSIX_putmsg (__NR_POSIX + 86) -#define __NR_POSIX_poll (__NR_POSIX + 87) -#define __NR_POSIX_sigreturn (__NR_POSIX + 88) -#define __NR_POSIX_accept (__NR_POSIX + 89) -#define __NR_POSIX_bind (__NR_POSIX + 90) -#define __NR_POSIX_connect (__NR_POSIX + 91) -#define __NR_POSIX_gethostid (__NR_POSIX + 92) -#define __NR_POSIX_getpeername (__NR_POSIX + 93) -#define __NR_POSIX_getsockname (__NR_POSIX + 94) -#define __NR_POSIX_getsockopt (__NR_POSIX + 95) -#define __NR_POSIX_listen (__NR_POSIX + 96) -#define __NR_POSIX_recv (__NR_POSIX + 97) -#define __NR_POSIX_recvfrom (__NR_POSIX + 98) -#define __NR_POSIX_recvmsg (__NR_POSIX + 99) -#define __NR_POSIX_select (__NR_POSIX + 100) -#define __NR_POSIX_send (__NR_POSIX + 101) -#define __NR_POSIX_sendmsg (__NR_POSIX + 102) -#define __NR_POSIX_sendto (__NR_POSIX + 103) -#define __NR_POSIX_sethostid (__NR_POSIX + 104) -#define __NR_POSIX_setsockopt (__NR_POSIX + 105) -#define __NR_POSIX_shutdown (__NR_POSIX + 106) -#define __NR_POSIX_socket (__NR_POSIX + 107) -#define __NR_POSIX_gethostname (__NR_POSIX + 108) -#define __NR_POSIX_sethostname (__NR_POSIX + 109) -#define __NR_POSIX_getdomainname (__NR_POSIX + 110) -#define __NR_POSIX_setdomainname (__NR_POSIX + 111) -#define __NR_POSIX_truncate (__NR_POSIX + 112) -#define __NR_POSIX_ftruncate (__NR_POSIX + 113) -#define __NR_POSIX_rename (__NR_POSIX + 114) -#define __NR_POSIX_symlink (__NR_POSIX + 115) -#define __NR_POSIX_readlink (__NR_POSIX + 116) -#define __NR_POSIX_lstat (__NR_POSIX + 117) -#define __NR_POSIX_nfs_mount (__NR_POSIX + 118) -#define __NR_POSIX_nfs_svc (__NR_POSIX + 119) -#define __NR_POSIX_nfs_getfh (__NR_POSIX + 120) -#define __NR_POSIX_async_daemon (__NR_POSIX + 121) -#define __NR_POSIX_exportfs (__NR_POSIX + 122) -#define __NR_POSIX_SGI_setregid (__NR_POSIX + 123) -#define __NR_POSIX_SGI_setreuid (__NR_POSIX + 124) -#define __NR_POSIX_getitimer (__NR_POSIX + 125) -#define __NR_POSIX_setitimer (__NR_POSIX + 126) -#define __NR_POSIX_adjtime (__NR_POSIX + 127) -#define __NR_POSIX_SGI_bsdgettime (__NR_POSIX + 128) -#define __NR_POSIX_SGI_sproc (__NR_POSIX + 129) -#define __NR_POSIX_SGI_prctl (__NR_POSIX + 130) -#define __NR_POSIX_SGI_blkproc (__NR_POSIX + 131) -#define __NR_POSIX_SGI_reserved1 (__NR_POSIX + 132) -#define __NR_POSIX_SGI_sgigsc (__NR_POSIX + 133) -#define __NR_POSIX_SGI_mmap (__NR_POSIX + 134) -#define __NR_POSIX_SGI_munmap (__NR_POSIX + 135) -#define __NR_POSIX_SGI_mprotect (__NR_POSIX + 136) -#define __NR_POSIX_SGI_msync (__NR_POSIX + 137) -#define __NR_POSIX_SGI_madvise (__NR_POSIX + 138) -#define __NR_POSIX_SGI_mpin (__NR_POSIX + 139) -#define __NR_POSIX_SGI_getpagesize (__NR_POSIX + 140) -#define __NR_POSIX_SGI_libattach (__NR_POSIX + 141) -#define __NR_POSIX_SGI_libdetach (__NR_POSIX + 142) -#define __NR_POSIX_SGI_getpgrp (__NR_POSIX + 143) -#define __NR_POSIX_SGI_setpgrp (__NR_POSIX + 144) -#define __NR_POSIX_SGI_reserved2 (__NR_POSIX + 145) -#define __NR_POSIX_SGI_reserved3 (__NR_POSIX + 146) -#define __NR_POSIX_SGI_reserved4 (__NR_POSIX + 147) -#define __NR_POSIX_SGI_reserved5 (__NR_POSIX + 148) -#define __NR_POSIX_SGI_reserved6 (__NR_POSIX + 149) -#define __NR_POSIX_cacheflush (__NR_POSIX + 150) -#define __NR_POSIX_cachectl (__NR_POSIX + 151) -#define __NR_POSIX_fchown (__NR_POSIX + 152) -#define __NR_POSIX_fchmod (__NR_POSIX + 153) -#define __NR_POSIX_wait3 (__NR_POSIX + 154) -#define __NR_POSIX_mmap (__NR_POSIX + 155) -#define __NR_POSIX_munmap (__NR_POSIX + 156) -#define __NR_POSIX_madvise (__NR_POSIX + 157) -#define __NR_POSIX_BSD_getpagesize (__NR_POSIX + 158) -#define __NR_POSIX_setreuid (__NR_POSIX + 159) -#define __NR_POSIX_setregid (__NR_POSIX + 160) -#define __NR_POSIX_setpgid (__NR_POSIX + 161) -#define __NR_POSIX_getgroups (__NR_POSIX + 162) -#define __NR_POSIX_setgroups (__NR_POSIX + 163) -#define __NR_POSIX_gettimeofday (__NR_POSIX + 164) -#define __NR_POSIX_getrusage (__NR_POSIX + 165) -#define __NR_POSIX_getrlimit (__NR_POSIX + 166) -#define __NR_POSIX_setrlimit (__NR_POSIX + 167) -#define __NR_POSIX_waitpid (__NR_POSIX + 168) -#define __NR_POSIX_dup2 (__NR_POSIX + 169) -#define __NR_POSIX_reserved2 (__NR_POSIX + 170) -#define __NR_POSIX_reserved3 (__NR_POSIX + 171) -#define __NR_POSIX_reserved4 (__NR_POSIX + 172) -#define __NR_POSIX_reserved5 (__NR_POSIX + 173) -#define __NR_POSIX_reserved6 (__NR_POSIX + 174) -#define __NR_POSIX_reserved7 (__NR_POSIX + 175) -#define __NR_POSIX_reserved8 (__NR_POSIX + 176) -#define __NR_POSIX_reserved9 (__NR_POSIX + 177) -#define __NR_POSIX_reserved10 (__NR_POSIX + 178) -#define __NR_POSIX_reserved11 (__NR_POSIX + 179) -#define __NR_POSIX_reserved12 (__NR_POSIX + 180) -#define __NR_POSIX_reserved13 (__NR_POSIX + 181) -#define __NR_POSIX_reserved14 (__NR_POSIX + 182) -#define __NR_POSIX_reserved15 (__NR_POSIX + 183) -#define __NR_POSIX_reserved16 (__NR_POSIX + 184) -#define __NR_POSIX_reserved17 (__NR_POSIX + 185) -#define __NR_POSIX_reserved18 (__NR_POSIX + 186) -#define __NR_POSIX_reserved19 (__NR_POSIX + 187) -#define __NR_POSIX_reserved20 (__NR_POSIX + 188) -#define __NR_POSIX_reserved21 (__NR_POSIX + 189) -#define __NR_POSIX_reserved22 (__NR_POSIX + 190) -#define __NR_POSIX_reserved23 (__NR_POSIX + 191) -#define __NR_POSIX_reserved24 (__NR_POSIX + 192) -#define __NR_POSIX_reserved25 (__NR_POSIX + 193) -#define __NR_POSIX_reserved26 (__NR_POSIX + 194) -#define __NR_POSIX_reserved27 (__NR_POSIX + 195) -#define __NR_POSIX_reserved28 (__NR_POSIX + 196) -#define __NR_POSIX_reserved29 (__NR_POSIX + 197) -#define __NR_POSIX_reserved30 (__NR_POSIX + 198) -#define __NR_POSIX_reserved31 (__NR_POSIX + 199) -#define __NR_POSIX_reserved32 (__NR_POSIX + 200) -#define __NR_POSIX_reserved33 (__NR_POSIX + 201) -#define __NR_POSIX_reserved34 (__NR_POSIX + 202) -#define __NR_POSIX_reserved35 (__NR_POSIX + 203) -#define __NR_POSIX_reserved36 (__NR_POSIX + 204) -#define __NR_POSIX_reserved37 (__NR_POSIX + 205) -#define __NR_POSIX_reserved38 (__NR_POSIX + 206) -#define __NR_POSIX_reserved39 (__NR_POSIX + 207) -#define __NR_POSIX_reserved40 (__NR_POSIX + 208) -#define __NR_POSIX_reserved41 (__NR_POSIX + 209) -#define __NR_POSIX_reserved42 (__NR_POSIX + 210) -#define __NR_POSIX_reserved43 (__NR_POSIX + 211) -#define __NR_POSIX_reserved44 (__NR_POSIX + 212) -#define __NR_POSIX_reserved45 (__NR_POSIX + 213) -#define __NR_POSIX_reserved46 (__NR_POSIX + 214) -#define __NR_POSIX_reserved47 (__NR_POSIX + 215) -#define __NR_POSIX_reserved48 (__NR_POSIX + 216) -#define __NR_POSIX_reserved49 (__NR_POSIX + 217) -#define __NR_POSIX_reserved50 (__NR_POSIX + 218) -#define __NR_POSIX_reserved51 (__NR_POSIX + 219) -#define __NR_POSIX_reserved52 (__NR_POSIX + 220) -#define __NR_POSIX_reserved53 (__NR_POSIX + 221) -#define __NR_POSIX_reserved54 (__NR_POSIX + 222) -#define __NR_POSIX_reserved55 (__NR_POSIX + 223) -#define __NR_POSIX_reserved56 (__NR_POSIX + 224) -#define __NR_POSIX_reserved57 (__NR_POSIX + 225) -#define __NR_POSIX_reserved58 (__NR_POSIX + 226) -#define __NR_POSIX_reserved59 (__NR_POSIX + 227) -#define __NR_POSIX_reserved60 (__NR_POSIX + 228) -#define __NR_POSIX_reserved61 (__NR_POSIX + 229) -#define __NR_POSIX_reserved62 (__NR_POSIX + 230) -#define __NR_POSIX_reserved63 (__NR_POSIX + 231) -#define __NR_POSIX_reserved64 (__NR_POSIX + 232) -#define __NR_POSIX_reserved65 (__NR_POSIX + 233) -#define __NR_POSIX_reserved66 (__NR_POSIX + 234) -#define __NR_POSIX_reserved67 (__NR_POSIX + 235) -#define __NR_POSIX_reserved68 (__NR_POSIX + 236) -#define __NR_POSIX_reserved69 (__NR_POSIX + 237) -#define __NR_POSIX_reserved70 (__NR_POSIX + 238) -#define __NR_POSIX_reserved71 (__NR_POSIX + 239) -#define __NR_POSIX_reserved72 (__NR_POSIX + 240) -#define __NR_POSIX_reserved73 (__NR_POSIX + 241) -#define __NR_POSIX_reserved74 (__NR_POSIX + 242) -#define __NR_POSIX_reserved75 (__NR_POSIX + 243) -#define __NR_POSIX_reserved76 (__NR_POSIX + 244) -#define __NR_POSIX_reserved77 (__NR_POSIX + 245) -#define __NR_POSIX_reserved78 (__NR_POSIX + 246) -#define __NR_POSIX_reserved79 (__NR_POSIX + 247) -#define __NR_POSIX_reserved80 (__NR_POSIX + 248) -#define __NR_POSIX_reserved81 (__NR_POSIX + 249) -#define __NR_POSIX_reserved82 (__NR_POSIX + 250) -#define __NR_POSIX_reserved83 (__NR_POSIX + 251) -#define __NR_POSIX_reserved84 (__NR_POSIX + 252) -#define __NR_POSIX_reserved85 (__NR_POSIX + 253) -#define __NR_POSIX_reserved86 (__NR_POSIX + 254) -#define __NR_POSIX_reserved87 (__NR_POSIX + 255) -#define __NR_POSIX_reserved88 (__NR_POSIX + 256) -#define __NR_POSIX_reserved89 (__NR_POSIX + 257) -#define __NR_POSIX_reserved90 (__NR_POSIX + 258) -#define __NR_POSIX_reserved91 (__NR_POSIX + 259) -#define __NR_POSIX_netboot (__NR_POSIX + 260) -#define __NR_POSIX_netunboot (__NR_POSIX + 261) -#define __NR_POSIX_rdump (__NR_POSIX + 262) -#define __NR_POSIX_setsid (__NR_POSIX + 263) -#define __NR_POSIX_getmaxsig (__NR_POSIX + 264) -#define __NR_POSIX_sigpending (__NR_POSIX + 265) -#define __NR_POSIX_sigprocmask (__NR_POSIX + 266) -#define __NR_POSIX_sigsuspend (__NR_POSIX + 267) -#define __NR_POSIX_sigaction (__NR_POSIX + 268) -#define __NR_POSIX_MIPS_reserved1 (__NR_POSIX + 269) -#define __NR_POSIX_MIPS_reserved2 (__NR_POSIX + 270) -#define __NR_POSIX_MIPS_reserved3 (__NR_POSIX + 271) -#define __NR_POSIX_MIPS_reserved4 (__NR_POSIX + 272) -#define __NR_POSIX_MIPS_reserved5 (__NR_POSIX + 273) -#define __NR_POSIX_MIPS_reserved6 (__NR_POSIX + 274) -#define __NR_POSIX_MIPS_reserved7 (__NR_POSIX + 275) -#define __NR_POSIX_MIPS_reserved8 (__NR_POSIX + 276) -#define __NR_POSIX_MIPS_reserved9 (__NR_POSIX + 277) -#define __NR_POSIX_MIPS_reserved10 (__NR_POSIX + 278) -#define __NR_POSIX_MIPS_reserved11 (__NR_POSIX + 279) -#define __NR_POSIX_TANDEM_reserved1 (__NR_POSIX + 280) -#define __NR_POSIX_TANDEM_reserved2 (__NR_POSIX + 281) -#define __NR_POSIX_TANDEM_reserved3 (__NR_POSIX + 282) -#define __NR_POSIX_TANDEM_reserved4 (__NR_POSIX + 283) -#define __NR_POSIX_TANDEM_reserved5 (__NR_POSIX + 284) -#define __NR_POSIX_TANDEM_reserved6 (__NR_POSIX + 285) -#define __NR_POSIX_TANDEM_reserved7 (__NR_POSIX + 286) -#define __NR_POSIX_TANDEM_reserved8 (__NR_POSIX + 287) -#define __NR_POSIX_TANDEM_reserved9 (__NR_POSIX + 288) -#define __NR_POSIX_TANDEM_reserved10 (__NR_POSIX + 289) -#define __NR_POSIX_TANDEM_reserved11 (__NR_POSIX + 290) -#define __NR_POSIX_TANDEM_reserved12 (__NR_POSIX + 291) -#define __NR_POSIX_TANDEM_reserved13 (__NR_POSIX + 292) -#define __NR_POSIX_TANDEM_reserved14 (__NR_POSIX + 293) -#define __NR_POSIX_TANDEM_reserved15 (__NR_POSIX + 294) -#define __NR_POSIX_TANDEM_reserved16 (__NR_POSIX + 295) -#define __NR_POSIX_TANDEM_reserved17 (__NR_POSIX + 296) -#define __NR_POSIX_TANDEM_reserved18 (__NR_POSIX + 297) -#define __NR_POSIX_TANDEM_reserved19 (__NR_POSIX + 298) -#define __NR_POSIX_TANDEM_reserved20 (__NR_POSIX + 299) -#define __NR_POSIX_SGI_reserved7 (__NR_POSIX + 300) -#define __NR_POSIX_SGI_reserved8 (__NR_POSIX + 301) -#define __NR_POSIX_SGI_reserved9 (__NR_POSIX + 302) -#define __NR_POSIX_SGI_reserved10 (__NR_POSIX + 303) -#define __NR_POSIX_SGI_reserved11 (__NR_POSIX + 304) -#define __NR_POSIX_SGI_reserved12 (__NR_POSIX + 305) -#define __NR_POSIX_SGI_reserved13 (__NR_POSIX + 306) -#define __NR_POSIX_SGI_reserved14 (__NR_POSIX + 307) -#define __NR_POSIX_SGI_reserved15 (__NR_POSIX + 308) -#define __NR_POSIX_SGI_reserved16 (__NR_POSIX + 309) -#define __NR_POSIX_SGI_reserved17 (__NR_POSIX + 310) -#define __NR_POSIX_SGI_reserved18 (__NR_POSIX + 311) -#define __NR_POSIX_SGI_reserved19 (__NR_POSIX + 312) -#define __NR_POSIX_SGI_reserved20 (__NR_POSIX + 313) -#define __NR_POSIX_SGI_reserved21 (__NR_POSIX + 314) -#define __NR_POSIX_SGI_reserved22 (__NR_POSIX + 315) -#define __NR_POSIX_SGI_reserved23 (__NR_POSIX + 316) -#define __NR_POSIX_SGI_reserved24 (__NR_POSIX + 317) -#define __NR_POSIX_SGI_reserved25 (__NR_POSIX + 318) -#define __NR_POSIX_SGI_reserved26 (__NR_POSIX + 319) - -#endif /* _ASM_RISCOS_SYSCALL_H */ diff --git a/include/asm-mips64/rmap.h b/include/asm-mips64/rmap.h deleted file mode 100644 index c9efd7b9874..00000000000 --- a/include/asm-mips64/rmap.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_RMAP_H -#define __ASM_RMAP_H - -/* nothing to see, move along */ -#include - -#endif /* __ASM_RMAP_H */ diff --git a/include/asm-mips64/rtc.h b/include/asm-mips64/rtc.h deleted file mode 100644 index ffd02109a0e..00000000000 --- a/include/asm-mips64/rtc.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _I386_RTC_H -#define _I386_RTC_H - -/* - * x86 uses the default access methods for the RTC. - */ - -#include - -#endif diff --git a/include/asm-mips64/scatterlist.h b/include/asm-mips64/scatterlist.h deleted file mode 100644 index 22634706e9d..00000000000 --- a/include/asm-mips64/scatterlist.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ASM_SCATTERLIST_H -#define __ASM_SCATTERLIST_H - -struct scatterlist { - struct page * page; - unsigned int offset; - dma_addr_t dma_address; - unsigned int length; -}; - -/* - * These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns, or alternatively stop on the first sg_dma_len(sg) which - * is 0. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) - -#define ISA_DMA_THRESHOLD (0x00ffffffUL) - -#endif /* __ASM_SCATTERLIST_H */ diff --git a/include/asm-mips64/sections.h b/include/asm-mips64/sections.h deleted file mode 100644 index faf483251c2..00000000000 --- a/include/asm-mips64/sections.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _ASM_SECTIONS_H -#define _ASM_SECTIONS_H - -#include - -extern char _stext; -extern char _fdata; -extern char _end; - -#endif /* _ASM_SECTIONS_H */ diff --git a/include/asm-mips64/segment.h b/include/asm-mips64/segment.h deleted file mode 100644 index 92ac001fc48..00000000000 --- a/include/asm-mips64/segment.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_SEGMENT_H -#define _ASM_SEGMENT_H - -/* Only here because we have some old header files that expect it.. */ - -#endif /* _ASM_SEGMENT_H */ diff --git a/include/asm-mips64/semaphore-helper.h b/include/asm-mips64/semaphore-helper.h deleted file mode 100644 index 1151c37e1a1..00000000000 --- a/include/asm-mips64/semaphore-helper.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * SMP- and interrupt-safe semaphores helper functions. - * - * Copyright (C) 1996 Linus Torvalds - * Copyright (C) 1999 Andrea Arcangeli - * Copyright (C) 1999, 2001, 2002 Ralf Baechle - * Copyright (C) 1999, 2001 Silicon Graphics, Inc. - * Copyright (C) 2000 MIPS Technologies, Inc. - */ -#ifndef _ASM_SEMAPHORE_HELPER_H -#define _ASM_SEMAPHORE_HELPER_H - -#include -#include - -#define sem_read(a) ((a)->counter) -#define sem_inc(a) (((a)->counter)++) -#define sem_dec(a) (((a)->counter)--) -/* - * These two _must_ execute atomically wrt each other. - */ -static inline void wake_one_more(struct semaphore * sem) -{ - atomic_inc(&sem->waking); -} - -#ifdef CONFIG_CPU_HAS_LLSC - -static inline int waking_non_zero(struct semaphore *sem) -{ - int ret, tmp; - - __asm__ __volatile__( - "1:\tll\t%1, %2\t\t\t# waking_non_zero\n\t" - "blez\t%1, 2f\n\t" - "subu\t%0, %1, 1\n\t" - "sc\t%0, %2\n\t" - "beqz\t%0, 1b\n" - "2:" - : "=r" (ret), "=r" (tmp), "+m" (sem->waking) - : "0" (0)); - - return ret; -} - -#else /* !CONFIG_CPU_HAS_LLSC */ - -/* - * It doesn't make sense, IMHO, to endlessly turn interrupts off and on again. - * Do it once and that's it. ll/sc *has* it's advantages. HK - */ - -static inline int waking_non_zero(struct semaphore *sem) -{ - unsigned long flags; - int ret = 0; - - local_irq_save(flags); - if (sem_read(&sem->waking) > 0) { - sem_dec(&sem->waking); - ret = 1; - } - local_irq_restore(flags); - return ret; -} -#endif /* !CONFIG_CPU_HAS_LLSC */ - -#ifdef CONFIG_CPU_HAS_LLDSCD - -/* - * waking_non_zero_interruptible: - * 1 got the lock - * 0 go to sleep - * -EINTR interrupted - * - * We must undo the sem->count down_interruptible decrement - * simultaneously and atomically with the sem->waking adjustment, - * otherwise we can race with wake_one_more. - * - * This is accomplished by doing a 64-bit lld/scd on the 2 32-bit words. - * - * This is crazy. Normally it's strictly forbidden to use 64-bit operations - * in the 32-bit MIPS kernel. In this case it's however ok because if an - * interrupt has destroyed the upper half of registers sc will fail. - * Note also that this will not work for MIPS32 CPUs! - * - * Pseudocode: - * - * If(sem->waking > 0) { - * Decrement(sem->waking) - * Return(SUCCESS) - * } else If(signal_pending(tsk)) { - * Increment(sem->count) - * Return(-EINTR) - * } else { - * Return(SLEEP) - * } - */ - -static inline int -waking_non_zero_interruptible(struct semaphore *sem, struct task_struct *tsk) -{ - long ret, tmp; - - __asm__ __volatile__( - ".set\tpush\t\t\t# waking_non_zero_interruptible\n\t" - ".set\tmips3\n\t" - ".set\tnoat\n" - "0:\tlld\t%1, %2\n\t" - "li\t%0, 0\n\t" - "sll\t$1, %1, 0\n\t" - "blez\t$1, 1f\n\t" - "daddiu\t%1, %1, -1\n\t" - "li\t%0, 1\n\t" - "b\t2f\n" - "1:\tbeqz\t%3, 2f\n\t" - "li\t%0, %4\n\t" - "dli\t$1, 0x0000000100000000\n\t" - "daddu\t%1, %1, $1\n" - "2:\tscd\t%1, %2\n\t" - "beqz\t%1, 0b\n\t" - ".set\tpop" - : "=&r" (ret), "=&r" (tmp), "=m" (*sem) - : "r" (signal_pending(tsk)), "i" (-EINTR)); - - return ret; -} - -/* - * waking_non_zero_trylock is unused. we do everything in - * down_trylock and let non-ll/sc hosts bounce around. - */ - -static inline int waking_non_zero_trylock(struct semaphore *sem) -{ -#if WAITQUEUE_DEBUG - CHECK_MAGIC(sem->__magic); -#endif - - return 0; -} - -#else /* !CONFIG_CPU_HAS_LLDSCD */ - -static inline int waking_non_zero_interruptible(struct semaphore *sem, - struct task_struct *tsk) -{ - int ret = 0; - unsigned long flags; - - local_irq_save(flags); - if (sem_read(&sem->waking) > 0) { - sem_dec(&sem->waking); - ret = 1; - } else if (signal_pending(tsk)) { - sem_inc(&sem->count); - ret = -EINTR; - } - local_irq_restore(flags); - return ret; -} - -static inline int waking_non_zero_trylock(struct semaphore *sem) -{ - int ret = 1; - unsigned long flags; - - local_irq_save(flags); - if (sem_read(&sem->waking) <= 0) - sem_inc(&sem->count); - else { - sem_dec(&sem->waking); - ret = 0; - } - local_irq_restore(flags); - - return ret; -} - -#endif /* !CONFIG_CPU_HAS_LLDSCD */ - -#endif /* _ASM_SEMAPHORE_HELPER_H */ diff --git a/include/asm-mips64/semaphore.h b/include/asm-mips64/semaphore.h deleted file mode 100644 index 34fc00d6046..00000000000 --- a/include/asm-mips64/semaphore.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996 Linus Torvalds - * Copyright (C) 1998, 99, 2000, 01 Ralf Baechle - * Copyright (C) 1999, 2000, 01 Silicon Graphics, Inc. - * Copyright (C) 2000, 01 MIPS Technologies, Inc. - */ -#ifndef _ASM_SEMAPHORE_H -#define _ASM_SEMAPHORE_H - -#include -#include -#include -#include -#include -#include - -struct semaphore { -#ifdef __MIPSEB__ - atomic_t count; - atomic_t waking; -#else - atomic_t waking; - atomic_t count; -#endif - wait_queue_head_t wait; -#if WAITQUEUE_DEBUG - long __magic; -#endif -} __attribute__((aligned(8))); - -#if WAITQUEUE_DEBUG -# define __SEM_DEBUG_INIT(name) \ - , (long)&(name).__magic -#else -# define __SEM_DEBUG_INIT(name) -#endif - -#ifdef __MIPSEB__ -#define __SEMAPHORE_INITIALIZER(name,count) \ -{ ATOMIC_INIT(count), ATOMIC_INIT(0), __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \ - __SEM_DEBUG_INIT(name) } -#else -#define __SEMAPHORE_INITIALIZER(name,count) \ -{ ATOMIC_INIT(0), ATOMIC_INIT(count), __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \ - __SEM_DEBUG_INIT(name) } -#endif - -#define __MUTEX_INITIALIZER(name) \ - __SEMAPHORE_INITIALIZER(name,1) - -#define __DECLARE_SEMAPHORE_GENERIC(name,count) \ - struct semaphore name = __SEMAPHORE_INITIALIZER(name,count) - -#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1) -#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0) - -static inline void sema_init (struct semaphore *sem, int val) -{ - atomic_set(&sem->count, val); - atomic_set(&sem->waking, 0); - init_waitqueue_head(&sem->wait); -#if WAITQUEUE_DEBUG - sem->__magic = (long)&sem->__magic; -#endif -} - -static inline void init_MUTEX (struct semaphore *sem) -{ - sema_init(sem, 1); -} - -static inline void init_MUTEX_LOCKED (struct semaphore *sem) -{ - sema_init(sem, 0); -} - -asmlinkage void __down(struct semaphore * sem); -asmlinkage int __down_interruptible(struct semaphore * sem); -asmlinkage int __down_trylock(struct semaphore * sem); -asmlinkage void __up(struct semaphore * sem); - -static inline void down(struct semaphore * sem) -{ -#if WAITQUEUE_DEBUG - CHECK_MAGIC(sem->__magic); -#endif - if (atomic_dec_return(&sem->count) < 0) - __down(sem); -} - -/* - * Interruptible try to acquire a semaphore. If we obtained - * it, return zero. If we were interrupted, returns -EINTR - */ -static inline int down_interruptible(struct semaphore * sem) -{ - int ret = 0; - -#if WAITQUEUE_DEBUG - CHECK_MAGIC(sem->__magic); -#endif - if (atomic_dec_return(&sem->count) < 0) - ret = __down_interruptible(sem); - return ret; -} - -#ifndef CONFIG_CPU_HAS_LLDSCD - -/* - * Non-blockingly attempt to down() a semaphore. - * Returns zero if we acquired it - */ -static inline int down_trylock(struct semaphore * sem) -{ - int ret = 0; - if (atomic_dec_return(&sem->count) < 0) - ret = __down_trylock(sem); - return ret; -} - -#else - -/* - * down_trylock returns 0 on success, 1 if we failed to get the lock. - * - * We must manipulate count and waking simultaneously and atomically. - * Here, we do this by using lld/scd on the pair of 32-bit words. - * - * Pseudocode: - * - * Decrement(sem->count) - * If(sem->count >=0) { - * Return(SUCCESS) // resource is free - * } else { - * If(sem->waking <= 0) { // if no wakeup pending - * Increment(sem->count) // undo decrement - * Return(FAILURE) - * } else { - * Decrement(sem->waking) // otherwise "steal" wakeup - * Return(SUCCESS) - * } - * } - */ -static inline int down_trylock(struct semaphore * sem) -{ - long ret, tmp, tmp2, sub; - -#if WAITQUEUE_DEBUG - CHECK_MAGIC(sem->__magic); -#endif - - __asm__ __volatile__( - ".set\tmips3\t\t\t# down_trylock\n" - "0:\tlld\t%1, %4\n\t" - "dli\t%3, 0x0000000100000000\n\t" - "dsubu\t%1, %3\n\t" - "li\t%0, 0\n\t" - "bgez\t%1, 2f\n\t" - "sll\t%2, %1, 0\n\t" - "blez\t%2, 1f\n\t" - "daddiu\t%1, %1, -1\n\t" - "b\t2f\n" - "1:\tdaddu\t%1, %1, %3\n\t" - "li\t%0, 1\n" - "2:\tscd\t%1, %4\n\t" - "beqz\t%1, 0b\n\t" - ".set\tmips0" - : "=&r"(ret), "=&r"(tmp), "=&r"(tmp2), "=&r"(sub) - : "m"(*sem) - : "memory"); - - return ret; -} - -#endif /* CONFIG_CPU_HAS_LLDSCD */ - -/* - * Note! This is subtle. We jump to wake people up only if - * the semaphore was negative (== somebody was waiting on it). - */ -static inline void up(struct semaphore * sem) -{ -#if WAITQUEUE_DEBUG - CHECK_MAGIC(sem->__magic); -#endif - if (atomic_inc_return(&sem->count) <= 0) - __up(sem); -} - -#endif /* _ASM_SEMAPHORE_H */ diff --git a/include/asm-mips64/sembuf.h b/include/asm-mips64/sembuf.h deleted file mode 100644 index 7281a4decaa..00000000000 --- a/include/asm-mips64/sembuf.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _ASM_SEMBUF_H -#define _ASM_SEMBUF_H - -/* - * The semid64_ds structure for the MIPS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 2 miscellaneous 64-bit values - */ - -struct semid64_ds { - struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t sem_otime; /* last semop time */ - __kernel_time_t sem_ctime; /* last change time */ - unsigned long sem_nsems; /* no. of semaphores in array */ - unsigned long __unused1; - unsigned long __unused2; -}; - -#endif /* _ASM_SEMBUF_H */ diff --git a/include/asm-mips64/serial.h b/include/asm-mips64/serial.h deleted file mode 100644 index 2f3284ffb2d..00000000000 --- a/include/asm-mips64/serial.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_SERIAL_H -#define _ASM_SERIAL_H - -#include - -/* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD (1843200 / 16) - -#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT - -/* Standard COM flags (except for COM4, because of the 8514 problem) */ -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF -#endif - -#define STD_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ - { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ - { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ - -#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ -#define STD_SERIAL_PORT_DEFNS -#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ - -#ifdef CONFIG_MIPS_SEAD -#include -#include -#define SEAD_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, SEAD_BASE_BAUD, SEAD_UART0_REGS_BASE, SEADINT_UART0, STD_COM_FLAGS }, /* ttyS0 */ -#else -#define SEAD_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_MOMENCO_OCELOT_C -/* Ordinary NS16552 duart with a 20MHz crystal. */ -#define OCELOT_C_BASE_BAUD ( 20000000 / 16 ) - -#define OCELOT_C_SERIAL1_IRQ 80 -#define OCELOT_C_SERIAL1_BASE 0xfd000020 - -#define OCELOT_C_SERIAL2_IRQ 81 -#define OCELOT_C_SERIAL2_BASE 0xfd000000 - -#define _OCELOT_C_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_C_BASE_BAUD, \ - .irq = (int), \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM \ - } -#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ - _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \ - _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE) -#else -#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_SGI_IP27 - -/* - * Note about serial ports and consoles: - * For console output, everyone uses the IOC3 UARTA (offset 0x178) - * connected to the master node (look in ip27_setup_console() and - * ip27prom_console_write()). - * - * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port - * addresses on a partitioned machine. Since we currently use the ioc3 - * serial ports, we use dynamic serial port discovery that the serial.c - * driver uses for pci/pnp ports (there is an entry for the SGI ioc3 - * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater - * than UARTB's, although UARTA on o200s has traditionally been known as - * port 0. So, we just use one serial port from each ioc3 (since the - * serial driver adds addresses to get to higher ports). - * - * The first one to do a register_console becomes the preferred console - * (if there is no kernel command line console= directive). /dev/console - * (ie 5, 1) is then "aliased" into the device number returned by the - * "device" routine referred to in this console structure - * (ip27prom_console_dev). - * - * Also look in ip27-pci.c:pci_fixuop_ioc3() for some comments on working - * around ioc3 oddities in this respect. - * - * The IOC3 serials use a 22MHz clock rate with an additional divider by 3. - * (IOC3_BAUD = (22000000 / (3*16))) - * - * At the moment this is only a skeleton definition as we register all serials - * at runtime. - */ - -#define IP27_SERIAL_PORT_DEFNS -#else -#define IP27_SERIAL_PORT_DEFNS -#endif /* CONFIG_SGI_IP27 */ - -#ifdef CONFIG_SGI_IP32 - -#include - -/* - * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory - */ - -/* Standard COM flags (except for COM4, because of the 8514 problem) */ -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF/* | ASYNC_SKIP_TEST*/) -#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF -#endif - -#define IP32_SERIAL_PORT_DEFNS \ - { .baud_base = BASE_BAUD, \ - .irq = MACEISA_SERIAL1_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8*)MACE_BASE+MACEISA_SER1_BASE, \ - .iomem_reg_shift = 8, \ - .io_type = SERIAL_IO_MEM}, \ - { .baud_base = BASE_BAUD, \ - .irq = MACEISA_SERIAL2_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8*)MACE_BASE+MACEISA_SER2_BASE, \ - .iomem_reg_shift = 8, \ - .io_type = SERIAL_IO_MEM}, -#else -#define IP32_SERIAL_PORT_DEFNS -#endif /* CONFIG_SGI_IP31 */ - -#define SERIAL_PORT_DFNS \ - IP27_SERIAL_PORT_DEFNS \ - IP32_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ - SEAD_SERIAL_PORT_DEFNS \ - STD_SERIAL_PORT_DEFNS - -#define RS_TABLE_SIZE 64 - -#endif /* _ASM_SERIAL_H */ diff --git a/include/asm-mips64/sfp-machine.h b/include/asm-mips64/sfp-machine.h deleted file mode 100644 index 730deae8723..00000000000 --- a/include/asm-mips64/sfp-machine.h +++ /dev/null @@ -1,47 +0,0 @@ -#define _FP_W_TYPE_SIZE 64 -#define _FP_W_TYPE unsigned long -#define _FP_WS_TYPE signed long -#define _FP_I_TYPE long - -#define _FP_MUL_MEAT_S(R,X,Y) \ - _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y) -#define _FP_MUL_MEAT_D(R,X,Y) \ - _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) -#define _FP_MUL_MEAT_Q(R,X,Y) \ - _FP_MUL_MEAT_2_wide_3mul(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) - -#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm) -#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y) -#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y) - -#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) -#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1) -#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1 -#define _FP_NANSIGN_S 0 -#define _FP_NANSIGN_D 0 -#define _FP_NANSIGN_Q 0 - -#define _FP_KEEPNANFRACP 1 -/* From my experiments it seems X is chosen unless one of the - NaNs is sNaN, in which case the result is NANSIGN/NANFRAC. */ -#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ - do { \ - if ((_FP_FRAC_HIGH_RAW_##fs(X) | \ - _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs) \ - { \ - R##_s = _FP_NANSIGN_##fs; \ - _FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \ - } \ - else \ - { \ - R##_s = X##_s; \ - _FP_FRAC_COPY_##wc(R,X); \ - } \ - R##_c = FP_CLS_NAN; \ - } while (0) - -#define FP_EX_INVALID (1 << 4) -#define FP_EX_DIVZERO (1 << 3) -#define FP_EX_OVERFLOW (1 << 2) -#define FP_EX_UNDERFLOW (1 << 1) -#define FP_EX_INEXACT (1 << 0) diff --git a/include/asm-mips64/sgi/gio.h b/include/asm-mips64/sgi/gio.h deleted file mode 100644 index a38d66f9987..00000000000 --- a/include/asm-mips64/sgi/gio.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * gio.h: Definitions for SGI GIO bus - * - * Copyright (C) 2002 Ladislav Michl - */ - -#ifndef _SGI_GIO_H -#define _SGI_GIO_H - -/* - * GIO bus addresses - * - * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have - * three physical connectors, but only two slots, GFX and EXP0. - * - * There is 10MB of GIO address space for GIO64 slot devices - * slot# slot type address range size - * ----- --------- ----------------------- ----- - * 0 GFX 0x1f000000 - 0x1f3fffff 4MB - * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB - * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB - * - * There are un-slotted devices, HPC, I/O and misc devices, which are grouped - * into the HPC address space. - * - MISC 0x1fb00000 - 0x1fbfffff 1MB - * - * Following space is reserved and unused - * - RESERVED 0x18000000 - 0x1effffff 112MB - * - * GIO bus IDs - * - * Each GIO bus device identifies itself to the system by answering a - * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less - * than 128 are 8 bits long, with the most significant 24 bits read from - * the slot undefined. - * - * 32-bit IDs are divided into - * bits 0:6 the product ID; ranges from 0x00 to 0x7F. - * bit 7 0=GIO Product ID is 8 bits wide - * 1=GIO Product ID is 32 bits wide. - * bits 8:15 manufacturer version for the product. - * bit 16 0=GIO32 and GIO32-bis, 1=GIO64. - * bit 17 0=no ROM present - * 1=ROM present on this board AND next three words - * space define the ROM. - * bits 18:31 up to manufacturer. - * - * IDs above 0x50/0xd0 are of 3rd party boards. - * - * 8-bit IDs - * 0x01 XPI low cost FDDI - * 0x02 GTR TokenRing - * 0x04 Synchronous ISDN - * 0x05 ATM board [*] - * 0x06 Canon Interface - * 0x07 16 bit SCSI Card [*] - * 0x08 JPEG (Double Wide) - * 0x09 JPEG (Single Wide) - * 0x0a XPI mez. FDDI device 0 - * 0x0b XPI mez. FDDI device 1 - * 0x0c SMPTE 259M Video [*] - * 0x0d Babblefish Compression [*] - * 0x0e E-Plex 8-port Ethernet - * 0x30 Lyon Lamb IVAS - * 0xb8 GIO 100BaseTX Fast Ethernet (gfe) - * - * [*] Device provide 32-bit ID. - * - */ - -#define GIO_ID(x) (x & 0x7f) -#define GIO_32BIT_ID 0x80 -#define GIO_REV(x) ((x >> 8) & 0xff) -#define GIO_64BIT_IFACE 0x10000 -#define GIO_ROM_PRESENT 0x20000 -#define GIO_VENDOR_CODE(x) ((x >> 18) & 0x3fff) - -#define GIO_SLOT_GFX_BASE 0x1f000000 -#define GIO_SLOT_EXP0_BASE 0x1f400000 -#define GIO_SLOT_EXP1_BASE 0x1f600000 - -#endif /* _SGI_GIO_H */ diff --git a/include/asm-mips64/sgi/hpc3.h b/include/asm-mips64/sgi/hpc3.h deleted file mode 100644 index a5b988d7327..00000000000 --- a/include/asm-mips64/sgi/hpc3.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * hpc3.h: Definitions for SGI HPC3 controller - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1998 Ralf Baechle - */ - -#ifndef _SGI_HPC3_H -#define _SGI_HPC3_H - -#include -#include - -/* An HPC DMA descriptor. */ -struct hpc_dma_desc { - u32 pbuf; /* physical address of data buffer */ - u32 cntinfo; /* counter and info bits */ -#define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */ -#define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */ -#define HPCDMA_EOXP 0x40000000 /* end of packet for tx */ -#define HPCDMA_EORP 0x40000000 /* end of packet for rx */ -#define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */ -#define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */ -#define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */ -#define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */ -#define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */ -#define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */ - - u32 pnext; /* paddr of next hpc_dma_desc if any */ -}; - -/* The set of regs for each HPC3 PBUS DMA channel. */ -struct hpc3_pbus_dmacregs { - volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */ - volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */ - u32 _unused0[0x1000/4 - 2]; /* padding */ - volatile u32 pbdma_ctrl; /* pbus dma channel control register has - * copletely different meaning for read - * compared with write */ - /* read */ -#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */ -#define HPC3_PDMACTRL_ISACT 0x00000002 /* channel active */ - /* write */ -#define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */ -#define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */ -#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */ -#define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */ -#define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */ -#define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */ -#define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */ -#define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */ -#define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */ - - u32 _unused1[0x1000/4 - 1]; /* padding */ -}; - -/* The HPC3 SCSI registers, this does not include external ones. */ -struct hpc3_scsiregs { - volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */ - volatile u32 ndptr; /* next dma descriptor ptr */ - u32 _unused0[0x1000/4 - 2]; /* padding */ - volatile u32 bcd; /* byte count info */ -#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */ -#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */ -#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */ - - volatile u32 ctrl; /* control register */ -#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */ -#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */ -#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */ -#define HPC3_SCTRL_FLUSH 0x08 /* Tells HPC3 to flush scsi fifos */ -#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */ -#define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */ -#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */ -#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */ - - volatile u32 gfptr; /* current GIO fifo ptr */ - volatile u32 dfptr; /* current device fifo ptr */ - volatile u32 dconfig; /* DMA configuration register */ -#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */ -#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */ -#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */ -#define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */ -#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */ -#define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */ -#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */ -#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */ -#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */ -#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */ - - volatile u32 pconfig; /* PIO configuration register */ -#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */ -#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */ -#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */ -#define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */ -#define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */ -#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */ -#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */ -#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */ - - u32 _unused1[0x1000/4 - 6]; /* padding */ -}; - -/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */ -struct hpc3_ethregs { - /* Receiver registers. */ - volatile u32 rx_cbptr; /* current dma buffer ptr, diagnostic use only */ - volatile u32 rx_ndptr; /* next dma descriptor ptr */ - u32 _unused0[0x1000/4 - 2]; /* padding */ - volatile u32 rx_bcd; /* byte count info */ -#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */ -#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */ -#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */ - - volatile u32 rx_ctrl; /* control register */ -#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */ -#define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */ -#define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */ -#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */ -#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */ -#define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */ -#define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */ - - volatile u32 rx_gfptr; /* current GIO fifo ptr */ - volatile u32 rx_dfptr; /* current device fifo ptr */ - u32 _unused1; /* padding */ - volatile u32 rx_reset; /* reset register */ -#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */ -#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */ -#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ - - volatile u32 rx_dconfig; /* DMA configuration register */ -#define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ -#define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ -#define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */ -#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */ -#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */ -#define HPC3_ERXDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */ -#define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ -#define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */ - - volatile u32 rx_pconfig; /* PIO configuration register */ -#define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ -#define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ -#define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ -#define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ - - u32 _unused2[0x1000/4 - 8]; /* padding */ - - /* Transmitter registers. */ - volatile u32 tx_cbptr; /* current dma buffer ptr, diagnostic use only */ - volatile u32 tx_ndptr; /* next dma descriptor ptr */ - u32 _unused3[0x1000/4 - 2]; /* padding */ - volatile u32 tx_bcd; /* byte count info */ -#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */ -#define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */ -#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */ -#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */ -#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */ - - volatile u32 tx_ctrl; /* control register */ -#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */ -#define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */ -#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */ -#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* DMA channel endian mode, 1=little 0=big */ -#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */ -#define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */ - - volatile u32 tx_gfptr; /* current GIO fifo ptr */ - volatile u32 tx_dfptr; /* current device fifo ptr */ - u32 _unused4[0x1000/4 - 4]; /* padding */ -}; - -struct hpc3_regs { - /* First regs for the PBUS 8 dma channels. */ - struct hpc3_pbus_dmacregs pbdma[8]; - - /* Now the HPC scsi registers, we get two scsi reg sets. */ - struct hpc3_scsiregs scsi_chan0, scsi_chan1; - - /* The SEEQ hpc3 ethernet dma/control registers. */ - struct hpc3_ethregs ethregs; - - /* Here are where the hpc3 fifo's can be directly accessed - * via PIO accesses. Under normal operation we never stick - * our grubby paws in here so it's just padding. */ - u32 _unused0[0x18000/4]; - - /* HPC3 irq status regs. Due to a peculiar bug you need to - * look at two different register addresses to get at all of - * the status bits. The first reg can only reliably report - * bits 4:0 of the status, and the second reg can only - * reliably report bits 9:5 of the hpc3 irq status. I told - * you it was a peculiar bug. ;-) - */ - volatile u32 istat0; /* Irq status, only bits <4:0> reliable. */ -#define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */ -#define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */ -#define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */ - - volatile u32 gio_misc; /* GIO misc control bits. */ -#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */ -#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */ - - volatile u32 eeprom; /* EEPROM data reg. */ -#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */ -#define HPC3_EEPROM_CSEL 0x02 /* Chip select */ -#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */ -#define HPC3_EEPROM_DATO 0x08 /* Data out */ -#define HPC3_EEPROM_DATI 0x10 /* Data in */ - - volatile u32 istat1; /* Irq status, only bits <9:5> reliable. */ - volatile u32 bestat; /* Bus error interrupt status reg. */ -#define HPC3_BESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */ -#define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */ -#define HPC3_BESTAT_PIDSHIFT 9 -#define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ - - u32 _unused1[0x14000/4 - 5]; /* padding */ - - /* Now direct PIO per-HPC3 peripheral access to external regs. */ - volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */ - u32 _unused2[0x7c00/4]; - volatile u32 scsi1_ext[256]; /* SCSI channel 1 external regs */ - u32 _unused3[0x7c00/4]; - volatile u32 eth_ext[320]; /* Ethernet external registers */ - u32 _unused4[0x3b00/4]; - - /* Per-peripheral device external registers and DMA/PIO control. */ - volatile u32 pbus_extregs[16][256]; - volatile u32 pbus_dmacfg[8][128]; - /* Cycles to spend in D3 for reads */ -#define HPC3_DMACFG_D3R_MASK 0x00000001 -#define HPC3_DMACFG_D3R_SHIFT 0 - /* Cycles to spend in D4 for reads */ -#define HPC3_DMACFG_D4R_MASK 0x0000001e -#define HPC3_DMACFG_D4R_SHIFT 1 - /* Cycles to spend in D5 for reads */ -#define HPC3_DMACFG_D5R_MASK 0x000001e0 -#define HPC3_DMACFG_D5R_SHIFT 5 - /* Cycles to spend in D3 for writes */ -#define HPC3_DMACFG_D3W_MASK 0x00000200 -#define HPC3_DMACFG_D3W_SHIFT 9 - /* Cycles to spend in D4 for writes */ -#define HPC3_DMACFG_D4W_MASK 0x00003c00 -#define HPC3_DMACFG_D4W_SHIFT 10 - /* Cycles to spend in D5 for writes */ -#define HPC3_DMACFG_D5W_MASK 0x0003c000 -#define HPC3_DMACFG_D5W_SHIFT 14 - /* Enable 16-bit DMA access mode */ -#define HPC3_DMACFG_DS16 0x00040000 - /* Places halfwords on high 16 bits of bus */ -#define HPC3_DMACFG_EVENHI 0x00080000 - /* Make this device real time */ -#define HPC3_DMACFG_RTIME 0x00200000 - /* 5 bit burst count for DMA device */ -#define HPC3_DMACFG_BURST_MASK 0x07c00000 -#define HPC3_DMACFG_BURST_SHIFT 22 - /* Use live pbus_dreq unsynchronized signal */ -#define HPC3_DMACFG_DRQLIVE 0x08000000 - volatile u32 pbus_piocfg[16][64]; - /* Cycles to spend in P2 state for reads */ -#define HPC3_PIOCFG_P2R_MASK 0x00001 -#define HPC3_PIOCFG_P2R_SHIFT 0 - /* Cycles to spend in P3 state for reads */ -#define HPC3_PIOCFG_P3R_MASK 0x0001e -#define HPC3_PIOCFG_P3R_SHIFT 1 - /* Cycles to spend in P4 state for reads */ -#define HPC3_PIOCFG_P4R_MASK 0x001e0 -#define HPC3_PIOCFG_P4R_SHIFT 5 - /* Cycles to spend in P2 state for writes */ -#define HPC3_PIOCFG_P2W_MASK 0x00200 -#define HPC3_PIOCFG_P2W_SHIFT 9 - /* Cycles to spend in P3 state for writes */ -#define HPC3_PIOCFG_P3W_MASK 0x03c00 -#define HPC3_PIOCFG_P3W_SHIFT 10 - /* Cycles to spend in P4 state for writes */ -#define HPC3_PIOCFG_P4W_MASK 0x3c000 -#define HPC3_PIOCFG_P4W_SHIFT 14 - /* Enable 16-bit PIO accesses */ -#define HPC3_PIOCFG_DS16 0x40000 - /* Place even address bits in bits <15:8> */ -#define HPC3_PIOCFG_EVENHI 0x80000 - - /* PBUS PROM control regs. */ - volatile u32 pbus_promwe; /* PROM write enable register */ -#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */ - - u32 _unused5[0x0800/4 - 1]; - volatile u32 pbus_promswap; /* Chip select swap reg */ -#define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */ - - u32 _unused6[0x0800/4 - 1]; - volatile u32 pbus_gout; /* PROM general purpose output reg */ -#define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */ - - u32 _unused7[0x1000/4 - 1]; - volatile u32 rtcregs[14]; /* Dallas clock registers */ - u32 _unused8[50]; - volatile u32 bbram[8192-50-14]; /* Battery backed ram */ -}; - -/* - * It is possible to have two HPC3's within the address space on - * one machine, though only having one is more likely on an Indy. - */ -extern struct hpc3_regs *hpc3c0, *hpc3c1; -#define HPC3_CHIP0_BASE 0x1fb80000 /* physical */ -#define HPC3_CHIP1_BASE 0x1fb00000 /* physical */ - -extern void sgihpc_init(void); - -#endif /* _SGI_HPC3_H */ diff --git a/include/asm-mips64/sgi/io.h b/include/asm-mips64/sgi/io.h deleted file mode 100644 index 66f379c8bbb..00000000000 --- a/include/asm-mips64/sgi/io.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_SGI_IO_H -#define _ASM_SGI_IO_H - -#include - -#define IO_SPACE_BASE K1BASE - -/* For Indigo2. */ -#define IO_SPACE_LIMIT 0xffff - -/* XXX ISA specific functions go here here. */ - -#endif /* _ASM_SGI_IO_H */ diff --git a/include/asm-mips64/sgi/ioc.h b/include/asm-mips64/sgi/ioc.h deleted file mode 100644 index 1cad06cda8f..00000000000 --- a/include/asm-mips64/sgi/ioc.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * ioc.h: Definitions for SGI I/O Controller - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle - * Copyright (C) 2001, 2003 Ladislav Michl - */ - -#ifndef _SGI_IOC_H -#define _SGI_IOC_H - -#include - -/* - * All registers are 8-bit wide alligned on 32-bit boundary. Bad things - * happen if you try word access them. You have been warned. - */ - -struct sgioc_pport_regs { - u8 _data[3]; - volatile u8 data; - u8 _ctrl[3]; - volatile u8 ctrl; -#define SGIOC_PCTRL_STROBE 0x01 -#define SGIOC_PCTRL_AFD 0x02 -#define SGIOC_PCTRL_INIT 0x04 -#define SGIOC_PCTRL_SLIN 0x08 -#define SGIOC_PCTRL_DIRECTION 0x20 -#define SGIOC_PCTRL_SEL 0x40 - u8 _status[3]; - volatile u8 status; -#define SGIOC_PSTAT_DEVID 0x03 -#define SGIOC_PSTAT_NOINK 0x04 -#define SGIOC_PSTAT_ERROR 0x08 -#define SGIOC_PSTAT_ONLINE 0x10 -#define SGIOC_PSTAT_PE 0x20 -#define SGIOC_PSTAT_ACK 0x40 -#define SGIOC_PSTAT_BUSY 0x80 - u8 _dmactrl[3]; - volatile u8 dmactrl; - u8 _intrstat[3]; - volatile u8 intrstat; - u8 _intrmask[3]; - volatile u8 intrmask; - u8 _timer1[3]; - volatile u8 timer1; - u8 _timer2[3]; - volatile u8 timer2; - u8 _timer3[3]; - volatile u8 timer3; - u8 _timer4[3]; - volatile u8 timer4; -}; - -struct sgioc_uart_regs { - u8 _ctrl1[3]; - volatile u8 ctrl1; - u8 _data1[3]; - volatile u8 data1; - u8 _ctrl2[3]; - volatile u8 ctrl2; - u8 _data2[3]; - volatile u8 data2; -}; - -struct sgioc_keyb_regs { - u8 _data[3]; - volatile u8 data; - u8 _command[3]; - volatile u8 command; -}; - -struct sgint_regs { - u8 _istat0[3]; - volatile u8 istat0; /* Interrupt status zero */ -#define SGINT_ISTAT0_FFULL 0x01 -#define SGINT_ISTAT0_SCSI0 0x02 -#define SGINT_ISTAT0_SCSI1 0x04 -#define SGINT_ISTAT0_ENET 0x08 -#define SGINT_ISTAT0_GFXDMA 0x10 -#define SGINT_ISTAT0_PPORT 0x20 -#define SGINT_ISTAT0_HPC2 0x40 -#define SGINT_ISTAT0_LIO2 0x80 - u8 _imask0[3]; - volatile u8 imask0; /* Interrupt mask zero */ - u8 _istat1[3]; - volatile u8 istat1; /* Interrupt status one */ -#define SGINT_ISTAT1_ISDNI 0x01 -#define SGINT_ISTAT1_PWR 0x02 -#define SGINT_ISTAT1_ISDNH 0x04 -#define SGINT_ISTAT1_LIO3 0x08 -#define SGINT_ISTAT1_HPC3 0x10 -#define SGINT_ISTAT1_AFAIL 0x20 -#define SGINT_ISTAT1_VIDEO 0x40 -#define SGINT_ISTAT1_GIO2 0x80 - u8 _imask1[3]; - volatile u8 imask1; /* Interrupt mask one */ - u8 _vmeistat[3]; - volatile u8 vmeistat; /* VME interrupt status */ - u8 _cmeimask0[3]; - volatile u8 cmeimask0; /* VME interrupt mask zero */ - u8 _cmeimask1[3]; - volatile u8 cmeimask1; /* VME interrupt mask one */ - u8 _cmepol[3]; - volatile u8 cmepol; /* VME polarity */ - u8 _tclear[3]; - volatile u8 tclear; - u8 _errstat[3]; - volatile u8 errstat; /* Error status reg, reserved on INT2 */ - u32 _unused0[2]; - u8 _tcnt0[3]; - volatile u8 tcnt0; /* counter 0 */ - u8 _tcnt1[3]; - volatile u8 tcnt1; /* counter 1 */ - u8 _tcnt2[3]; - volatile u8 tcnt2; /* counter 2 */ - u8 _tcword[3]; - volatile u8 tcword; /* control word */ -#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */ -#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */ -#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */ -#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */ -#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */ -#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */ -#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */ -#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */ -#define SGINT_TCWORD_CMASK 0x30 /* Command mask */ -#define SGINT_TCWORD_CLAT 0x00 /* Latch command */ -#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */ -#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */ -#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */ -#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */ -#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */ -#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */ -#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */ -}; - -/* - * The timer is the good old 8254. Unlike in PCs it's clocked at exactly 1MHz - */ -#define SGINT_TIMER_CLOCK 1000000 - -/* - * This is the constant we're using for calibrating the counter. - */ -#define SGINT_TCSAMP_COUNTER ((SGINT_TIMER_CLOCK / HZ) + 255) - -/* We need software copies of these because they are write only. */ -extern u8 sgi_ioc_reset, sgi_ioc_write; - -struct sgioc_regs { - struct sgioc_pport_regs pport; - u32 _unused0[2]; - struct sgioc_uart_regs serport; - struct sgioc_keyb_regs kbdmouse; - u8 _gcsel[3]; - volatile u8 gcsel; - u8 _genctrl[3]; - volatile u8 genctrl; - u8 _panel[3]; - volatile u8 panel; -#define SGIOC_PANEL_POWERON 0x01 -#define SGIOC_PANEL_POWERINTR 0x02 -#define SGIOC_PANEL_VOLDNINTR 0x10 -#define SGIOC_PANEL_VOLDNHOLD 0x20 -#define SGIOC_PANEL_VOLUPINTR 0x40 -#define SGIOC_PANEL_VOLUPHOLD 0x80 - u32 _unused1; - u8 _sysid[3]; - volatile u8 sysid; -#define SGIOC_SYSID_FULLHOUSE 0x01 -#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) -#define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1) - u32 _unused2; - u8 _read[3]; - volatile u8 read; - u32 _unused3; - u8 _dmasel[3]; - volatile u8 dmasel; -#define SGIOC_DMASEL_SCLK10MHZ 0x00 /* use 10MHZ serial clock */ -#define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */ -#define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */ -#define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */ -#define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */ -#define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */ - u32 _unused4; - u8 _reset[3]; - volatile u8 reset; -#define SGIOC_RESET_PPORT 0x01 /* 0=parport reset, 1=nornal */ -#define SGIOC_RESET_KBDMOUSE 0x02 /* 0=kbdmouse reset, 1=normal */ -#define SGIOC_RESET_EISA 0x04 /* 0=eisa reset, 1=normal */ -#define SGIOC_RESET_ISDN 0x08 /* 0=isdn reset, 1=normal */ -#define SGIOC_RESET_LC0OFF 0x10 /* guiness: turn led off (red, else green) */ -#define SGIOC_RESET_LC1OFF 0x20 /* guiness: turn led off (green, else amber) */ - u32 _unused5; - u8 _write[3]; - volatile u8 write; -#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */ -#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */ -#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ -#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ -#define SGIOC_WRITE_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */ -#define SGIOC_WRITE_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */ -#define SGIOC_WRITE_MLO 0x40 /* 1=4.75V 0=+5V */ -#define SGIOC_WRITE_MHI 0x80 /* 1=5.25V 0=+5V */ - u32 _unused6; - struct sgint_regs int3; - u32 _unused7[16]; - volatile u32 extio; /* FullHouse only */ -#define EXTIO_S0_IRQ_3 0x8000 /* S0: vid.vsync */ -#define EXTIO_S0_IRQ_2 0x4000 /* S0: gfx.fifofull */ -#define EXTIO_S0_IRQ_1 0x2000 /* S0: gfx.int */ -#define EXTIO_S0_RETRACE 0x1000 -#define EXTIO_SG_IRQ_3 0x0800 /* SG: vid.vsync */ -#define EXTIO_SG_IRQ_2 0x0400 /* SG: gfx.fifofull */ -#define EXTIO_SG_IRQ_1 0x0200 /* SG: gfx.int */ -#define EXTIO_SG_RETRACE 0x0100 -#define EXTIO_GIO_33MHZ 0x0080 -#define EXTIO_EISA_BUSERR 0x0040 -#define EXTIO_MC_BUSERR 0x0020 -#define EXTIO_HPC3_BUSERR 0x0010 -#define EXTIO_S0_STAT_1 0x0008 -#define EXTIO_S0_STAT_0 0x0004 -#define EXTIO_SG_STAT_1 0x0002 -#define EXTIO_SG_STAT_0 0x0001 -}; - -extern struct sgioc_regs *sgioc; -extern struct sgint_regs *sgint; - -#endif diff --git a/include/asm-mips64/sgi/ip22.h b/include/asm-mips64/sgi/ip22.h deleted file mode 100644 index 97d73adb4e4..00000000000 --- a/include/asm-mips64/sgi/ip22.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * ip22.h: Definitions for SGI IP22 machines - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle - */ - -#ifndef _SGI_IP22_H -#define _SGI_IP22_H - -/* - * These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups - * are not supported this way. Driver is supposed to allocate HPC/MC - * interrupt as shareable and then look to proper status bit (see - * HAL2 driver). This will prevent many complications, trust me ;-) - */ - -#include - -#define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */ -#define SGINT_CPU 16 /* MIPS CPU define 8 interrupt sources */ -#define SGINT_LOCAL0 24 /* 8 local0 irq levels */ -#define SGINT_LOCAL1 32 /* 8 local1 irq levels */ -#define SGINT_LOCAL2 40 /* 8 local2 vectored irq levels */ -#define SGINT_LOCAL3 48 /* 8 local3 vectored irq levels */ -#define SGINT_END 56 /* End of 'spaces' */ - -/* - * Individual interrupt definitions for the Indy and Indigo2 - */ - -#define SGI_SOFT_0_IRQ SGINT_CPU + 0 -#define SGI_SOFT_1_IRQ SGINT_CPU + 1 -#define SGI_LOCAL_0_IRQ SGINT_CPU + 2 -#define SGI_LOCAL_1_IRQ SGINT_CPU + 3 -#define SGI_8254_0_IRQ SGINT_CPU + 4 -#define SGI_8254_1_IRQ SGINT_CPU + 5 -#define SGI_BUSERR_IRQ SGINT_CPU + 6 -#define SGI_TIMER_IRQ SGINT_CPU + 7 - -#define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */ -#define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */ -#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ -#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ -#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ -#define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */ -#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */ -#define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */ -#define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */ - -#define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */ -#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ -#define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */ -#define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */ -#define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */ -#define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */ -#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */ -#define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */ - -/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */ -#define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */ -#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ -#define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ -#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ - -#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE) - -extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg); -extern unsigned short ip22_nvram_read(int reg); - -#endif diff --git a/include/asm-mips64/sgi/mc.h b/include/asm-mips64/sgi/mc.h deleted file mode 100644 index fd98f930607..00000000000 --- a/include/asm-mips64/sgi/mc.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * mc.h: Definitions for SGI Memory Controller - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1999 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ - -#ifndef _SGI_MC_H -#define _SGI_MC_H - -struct sgimc_regs { - u32 _unused0; - volatile u32 cpuctrl0; /* CPU control register 0, readwrite */ -#define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */ -#define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */ -#define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */ -#define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */ -#define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */ -#define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */ -#define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */ -#define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */ -#define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */ -#define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */ -#define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */ -#define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */ -#define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */ -#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */ -#define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */ -#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */ -#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */ -#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */ -#define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */ - u32 _unused1; - volatile u32 cpuctrl1; /* CPU control register 1, readwrite */ -#define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */ -#define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */ -#define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */ -#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */ -#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */ -#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */ -#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */ - - u32 _unused2; - volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */ - - u32 _unused3; - volatile u32 systemid; /* MC system ID register, readonly */ -#define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */ -#define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */ - - u32 _unused4[3]; - volatile u32 divider; /* Divider reg for RPSS */ - - u32 _unused5; - volatile u32 eeprom; /* EEPROM byte reg for r4k */ -#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */ -#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */ -#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */ -#define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */ -#define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */ - - u32 _unused6[3]; - volatile u32 rcntpre; /* Preload refresh counter */ - - u32 _unused7; - volatile u32 rcounter; /* Readonly refresh counter */ - - u32 _unused8[13]; - volatile u32 giopar; /* Parameter word for GIO64 */ -#define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */ -#define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */ -#define SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */ -#define SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */ -#define SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */ -#define SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */ -#define SGIMC_GIOPAR_RTIMEGFX 0x00000040 /* GFX device has realtime attr */ -#define SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */ -#define SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */ -#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */ -#define SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */ -#define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */ -#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */ -#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */ -#define SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */ -#define SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */ - - u32 _unused9; - volatile u32 cputp; /* CPU bus arb time period */ - - u32 _unused10[3]; - volatile u32 lbursttp; /* Time period for long bursts */ - - /* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must - * be the same size. The size encoding for supported SIMMs is bellow */ - u32 _unused11[9]; - volatile u32 mconfig0; /* Memory config register zero */ - u32 _unused12; - volatile u32 mconfig1; /* Memory config register one */ -#define SGIMC_MCONFIG_BASEADDR 0x000000ff /* Base address of bank*/ -#define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */ -#define SGIMC_MCONFIG_BVALID 0x00002000 /* Bank is valid */ -#define SGIMC_MCONFIG_SBANKS 0x00004000 /* Number of subbanks */ - - u32 _unused13; - volatile u32 cmacc; /* Mem access config for CPU */ - u32 _unused14; - volatile u32 gmacc; /* Mem access config for GIO */ - - /* This define applies to both cmacc and gmacc registers above. */ -#define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */ - - /* Error address/status regs from GIO and CPU perspectives. */ - u32 _unused15; - volatile u32 cerr; /* Error address reg for CPU */ - u32 _unused16; - volatile u32 cstat; /* Status reg for CPU */ -#define SGIMC_CSTAT_RD 0x00000100 /* read parity error */ -#define SGIMC_CSTAT_PAR 0x00000200 /* CPU parity error */ -#define SGIMC_CSTAT_ADDR 0x00000400 /* memory bus error bad addr */ -#define SGIMC_CSTAT_SYSAD_PAR 0x00000800 /* sysad parity error */ -#define SGIMC_CSTAT_SYSCMD_PAR 0x00001000 /* syscmd parity error */ -#define SGIMC_CSTAT_BAD_DATA 0x00002000 /* bad data identifier */ -#define SGIMC_CSTAT_PAR_MASK 0x00001f00 /* parity error mask */ -#define SGIMC_CSTAT_RD_PAR (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR) - - u32 _unused17; - volatile u32 gerr; /* Error address reg for GIO */ - u32 _unused18; - volatile u32 gstat; /* Status reg for GIO */ -#define SGIMC_GSTAT_RD 0x00000100 /* read parity error */ -#define SGIMC_GSTAT_WR 0x00000200 /* write parity error */ -#define SGIMC_GSTAT_TIME 0x00000400 /* GIO bus timed out */ -#define SGIMC_GSTAT_PROM 0x00000800 /* write to PROM when PROM_EN not set */ -#define SGIMC_GSTAT_ADDR 0x00001000 /* parity error on addr cycle */ -#define SGIMC_GSTAT_BC 0x00002000 /* parity error on byte count cycle */ -#define SGIMC_GSTAT_PIO_RD 0x00004000 /* read data parity on pio */ -#define SGIMC_GSTAT_PIO_WR 0x00008000 /* write data parity on pio */ - - /* Special hard bus locking registers. */ - u32 _unused19; - volatile u32 syssembit; /* Uni-bit system semaphore */ - u32 _unused20; - volatile u32 mlock; /* Global GIO memory access lock */ - u32 _unused21; - volatile u32 elock; /* Locks EISA from GIO accesses */ - - /* GIO dma control registers. */ - u32 _unused22[15]; - volatile u32 gio_dma_trans; /* DMA mask to translation GIO addrs */ - u32 _unused23; - volatile u32 gio_dma_sbits; /* DMA GIO addr substitution bits */ - u32 _unused24; - volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */ - u32 _unused25; - volatile u32 dma_ctrl; /* Main DMA control reg */ - - /* DMA TLB entry 0 */ - u32 _unused26[5]; - volatile u32 dtlb_hi0; - u32 _unused27; - volatile u32 dtlb_lo0; - - /* DMA TLB entry 1 */ - u32 _unused28; - volatile u32 dtlb_hi1; - u32 _unused29; - volatile u32 dtlb_lo1; - - /* DMA TLB entry 2 */ - u32 _unused30; - volatile u32 dtlb_hi2; - u32 _unused31; - volatile u32 dtlb_lo2; - - /* DMA TLB entry 3 */ - u32 _unused32; - volatile u32 dtlb_hi3; - u32 _unused33; - volatile u32 dtlb_lo3; - - u32 _unused34[0x0392]; - - u32 _unused35; - volatile u32 rpsscounter; /* Chirps at 100ns */ - - u32 _unused36[0x1000/4-2*4]; - - u32 _unused37; - volatile u32 maddronly; /* Address DMA goes at */ - u32 _unused38; - volatile u32 maddrpdeflts; /* Same as above, plus set defaults */ - u32 _unused39; - volatile u32 dmasz; /* DMA count */ - u32 _unused40; - volatile u32 ssize; /* DMA stride size */ - u32 _unused41; - volatile u32 gmaddronly; /* Set GIO DMA but don't start trans */ - u32 _unused42; - volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */ - u32 _unused43; - volatile u32 dmamode; /* DMA mode config bit settings */ - u32 _unused44; - volatile u32 dmaccount; /* Zoom and byte count for DMA */ - u32 _unused45; - volatile u32 dmastart; /* Pedal to the metal. */ - u32 _unused46; - volatile u32 dmarunning; /* DMA op is in progress */ - u32 _unused47; - volatile u32 maddrdefstart; /* Set dma addr, defaults, and kick it */ -}; - -extern struct sgimc_regs *sgimc; -#define SGIMC_BASE 0x1fa00000 /* physical */ - -/* Base location of the two ram banks found in IP2[0268] machines. */ -#define SGIMC_SEG0_BADDR 0x08000000 -#define SGIMC_SEG1_BADDR 0x20000000 - -/* Maximum size of the above banks are per machine. */ -#define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */ -#define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */ -#define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */ - -extern void sgimc_init(void); - -#endif /* _SGI_MC_H */ diff --git a/include/asm-mips64/sgi/sgi.h b/include/asm-mips64/sgi/sgi.h deleted file mode 100644 index ace2b34df56..00000000000 --- a/include/asm-mips64/sgi/sgi.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * sgi.h: Definitions specific to SGI machines. - * - * Copyright (C) 1996 David S. Miller (dm@sgi.com) - */ -#ifndef _ASM_SGI_SGI_H -#define _ASM_SGI_SGI_H - -/* UP=UniProcessor MP=MultiProcessor(capable) */ -enum sgi_mach { - ip4, /* R2k UP */ - ip5, /* R2k MP */ - ip6, /* R3k UP */ - ip7, /* R3k MP */ - ip9, /* R3k UP */ - ip12, /* R3kA UP, Indigo */ - ip15, /* R3kA MP */ - ip17, /* R4K UP */ - ip19, /* R4K MP */ - ip20, /* R4K UP, Indigo */ - ip21, /* TFP MP */ - ip22, /* R4x00 UP, Indigo2 */ - ip25, /* R10k MP */ - ip26, /* TFP UP, Indigo2 */ - ip27, /* R10k MP, R12k MP, Origin */ - ip28, /* R10k UP, Indigo2 */ - ip30, - ip32, -}; - -extern enum sgi_mach sgimach; -extern void sgi_sysinit(void); - -/* Many I/O space registers are byte sized and are contained within - * one byte per word, specifically the MSB, this macro helps out. - */ -#ifdef __MIPSEL__ -#define SGI_MSB(regaddr) (regaddr) -#else -#define SGI_MSB(regaddr) ((regaddr) | 0x3) -#endif - -#endif /* _ASM_SGI_SGI_H */ diff --git a/include/asm-mips64/sgialib.h b/include/asm-mips64/sgialib.h deleted file mode 100644 index e012e31afc6..00000000000 --- a/include/asm-mips64/sgialib.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * SGI ARCS firmware interface library for the Linux kernel. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 2001, 2002 Ralf Baechle (ralf@gnu.org) - */ -#ifndef _ASM_SGIALIB_H -#define _ASM_SGIALIB_H - -#include - -extern struct linux_romvec *romvec; -extern int prom_argc; - -extern LONG *_prom_argv, *_prom_envp; - -/* A 32-bit ARC PROM pass arguments and environment as 32-bit pointer. - These macros take care of sign extension. */ -#define prom_argv(index) ((char *) (long) _prom_argv[(index)]) -#define prom_argc(index) ((char *) (long) _prom_argc[(index)]) - -extern int prom_flags; -#define PROM_FLAG_ARCS 1 -#define PROM_FLAG_USE_AS_CONSOLE 2 - -/* Init the PROM library and it's internal data structures. */ -extern void prom_init(int argc, char **argv, char **envp, int *prom_vec); - -/* Simple char-by-char console I/O. */ -extern void prom_putchar(char c); -extern char prom_getchar(void); - -/* Generic printf() using ARCS console I/O. */ -extern void prom_printf(char *fmt, ...); - -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 32 -struct prom_pmemblock { - LONG base; /* Within KSEG0 or XKPHYS. */ - ULONG size; /* In bytes. */ - ULONG type; /* free or prom memory */ -}; - -/* Get next memory descriptor after CURR, returns first descriptor - * in chain is CURR is NULL. - */ -extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr); -#define PROM_NULL_MDESC ((struct linux_mdesc *) 0) - -/* Called by prom_init to setup the physical memory pmemblock - * array. - */ -extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); - -/* PROM device tree library routines. */ -#define PROM_NULL_COMPONENT ((pcomponent *) 0) - -/* Get sibling component of THIS. */ -extern pcomponent *ArcGetPeer(pcomponent *this); - -/* Get child component of THIS. */ -extern pcomponent *ArcGetChild(pcomponent *this); - -/* Get parent component of CHILD. */ -extern pcomponent *prom_getparent(pcomponent *child); - -/* Copy component opaque data of component THIS into BUFFER - * if component THIS has opaque data. Returns success or - * failure status. - */ -extern long prom_getcdata(void *buffer, pcomponent *this); - -/* Other misc. component routines. */ -extern pcomponent *prom_childadd(pcomponent *this, pcomponent *tmp, void *data); -extern long prom_delcomponent(pcomponent *this); -extern pcomponent *prom_componentbypath(char *path); - -/* This is called at prom_init time to identify the - * ARC architecture we are running on - */ -extern void prom_identify_arch(void); - -/* Environment variable routines. */ -extern PCHAR ArcGetEnvironmentVariable(PCHAR name); -extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value); - -/* ARCS command line acquisition and parsing. */ -extern char *prom_getcmdline(void); -extern void prom_init_cmdline(void); - -/* Acquiring info about the current time, etc. */ -extern struct linux_tinfo *prom_gettinfo(void); -extern unsigned long prom_getrtime(void); - -/* File operations. */ -extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt); -extern long prom_open(char *name, enum linux_omode md, unsigned long *fd); -extern long prom_close(unsigned long fd); -extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt); -extern long prom_getrstatus(unsigned long fd); -extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt); -extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm); -extern long prom_mount(char *name, enum linux_mountops op); -extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf); -extern long prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk); - -/* Running stand-along programs. */ -extern long prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr); -extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp); -extern long prom_exec(char *name, long argc, char **argv, char **envp); - -/* Misc. routines. */ -extern VOID prom_halt(VOID) __attribute__((noreturn)); -extern VOID prom_powerdown(VOID) __attribute__((noreturn)); -extern VOID prom_restart(VOID) __attribute__((noreturn)); -extern VOID ArcReboot(VOID) __attribute__((noreturn)); -extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn)); -extern long prom_cfgsave(VOID); -extern struct linux_sysid *prom_getsysid(VOID); -extern VOID ArcFlushAllCaches(VOID); - -#endif /* _ASM_SGIALIB_H */ diff --git a/include/asm-mips64/sgiarcs.h b/include/asm-mips64/sgiarcs.h deleted file mode 100644 index 48325845ab7..00000000000 --- a/include/asm-mips64/sgiarcs.h +++ /dev/null @@ -1,547 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * ARC firmware interface defines. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1999, 2001 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_SGIARCS_H -#define _ASM_SGIARCS_H - -#include -#include -#include - -/* Various ARCS error codes. */ -#define PROM_ESUCCESS 0x00 -#define PROM_E2BIG 0x01 -#define PROM_EACCESS 0x02 -#define PROM_EAGAIN 0x03 -#define PROM_EBADF 0x04 -#define PROM_EBUSY 0x05 -#define PROM_EFAULT 0x06 -#define PROM_EINVAL 0x07 -#define PROM_EIO 0x08 -#define PROM_EISDIR 0x09 -#define PROM_EMFILE 0x0a -#define PROM_EMLINK 0x0b -#define PROM_ENAMETOOLONG 0x0c -#define PROM_ENODEV 0x0d -#define PROM_ENOENT 0x0e -#define PROM_ENOEXEC 0x0f -#define PROM_ENOMEM 0x10 -#define PROM_ENOSPC 0x11 -#define PROM_ENOTDIR 0x12 -#define PROM_ENOTTY 0x13 -#define PROM_ENXIO 0x14 -#define PROM_EROFS 0x15 -/* SGI ARCS specific errno's. */ -#define PROM_EADDRNOTAVAIL 0x1f -#define PROM_ETIMEDOUT 0x20 -#define PROM_ECONNABORTED 0x21 -#define PROM_ENOCONNECT 0x22 - -/* Device classes, types, and identifiers for prom - * device inventory queries. - */ -enum linux_devclass { - system, processor, cache, adapter, controller, peripheral, memory -}; - -enum linux_devtypes { - /* Generic stuff. */ - Arc, Cpu, Fpu, - - /* Primary insn and data caches. */ - picache, pdcache, - - /* Secondary insn, data, and combined caches. */ - sicache, sdcache, sccache, - - memdev, eisa_adapter, tc_adapter, scsi_adapter, dti_adapter, - multifunc_adapter, dsk_controller, tp_controller, cdrom_controller, - worm_controller, serial_controller, net_controller, disp_controller, - parallel_controller, ptr_controller, kbd_controller, audio_controller, - misc_controller, disk_peripheral, flpy_peripheral, tp_peripheral, - modem_peripheral, monitor_peripheral, printer_peripheral, - ptr_peripheral, kbd_peripheral, term_peripheral, line_peripheral, - net_peripheral, misc_peripheral, anon -}; - -enum linux_identifier { - bogus, ronly, removable, consin, consout, input, output -}; - -/* A prom device tree component. */ -struct linux_component { - enum linux_devclass class; /* node class */ - enum linux_devtypes type; /* node type */ - enum linux_identifier iflags; /* node flags */ - USHORT vers; /* node version */ - USHORT rev; /* node revision */ - ULONG key; /* completely magic */ - ULONG amask; /* XXX affinity mask??? */ - ULONG cdsize; /* size of configuration data */ - ULONG ilen; /* length of string identifier */ - _PULONG iname; /* string identifier */ -}; -typedef struct linux_component pcomponent; - -struct linux_sysid { - char vend[8], prod[8]; -}; - -/* ARCS prom memory descriptors. */ -enum arcs_memtypes { - arcs_eblock, /* exception block */ - arcs_rvpage, /* ARCS romvec page */ - arcs_fcontig, /* Contiguous and free */ - arcs_free, /* Generic free memory */ - arcs_bmem, /* Borken memory, don't use */ - arcs_prog, /* A loaded program resides here */ - arcs_atmp, /* ARCS temporary storage area, wish Sparc OpenBoot told this */ - arcs_aperm, /* ARCS permanent storage... */ -}; - -/* ARC has slightly different types than ARCS */ -enum arc_memtypes { - arc_eblock, /* exception block */ - arc_rvpage, /* romvec page */ - arc_free, /* Generic free memory */ - arc_bmem, /* Borken memory, don't use */ - arc_prog, /* A loaded program resides here */ - arc_atmp, /* temporary storage area */ - arc_aperm, /* permanent storage */ - arc_fcontig, /* Contiguous and free */ -}; - -union linux_memtypes { - enum arcs_memtypes arcs; - enum arc_memtypes arc; -}; - -struct linux_mdesc { - union linux_memtypes type; - ULONG base; - ULONG pages; -}; - -/* Time of day descriptor. */ -struct linux_tinfo { - unsigned short yr; - unsigned short mnth; - unsigned short day; - unsigned short hr; - unsigned short min; - unsigned short sec; - unsigned short msec; -}; - -/* ARCS virtual dirents. */ -struct linux_vdirent { - ULONG namelen; - unsigned char attr; - char fname[32]; /* XXX imperical, should be a define */ -}; - -/* Other stuff for files. */ -enum linux_omode { - rdonly, wronly, rdwr, wronly_creat, rdwr_creat, - wronly_ssede, rdwr_ssede, dirent, dirent_creat -}; - -enum linux_seekmode { - absolute, relative -}; - -enum linux_mountops { - media_load, media_unload -}; - -/* This prom has a bolixed design. */ -struct linux_bigint { -#ifdef __MIPSEL__ - u32 lo; - s32 hi; -#else /* !(__MIPSEL__) */ - s32 hi; - u32 lo; -#endif -}; - -struct linux_finfo { - struct linux_bigint begin; - struct linux_bigint end; - struct linux_bigint cur; - enum linux_devtypes dtype; - unsigned long namelen; - unsigned char attr; - char name[32]; /* XXX imperical, should be define */ -}; - -/* This describes the vector containing function pointers to the ARC - firmware functions. */ -struct linux_romvec { - LONG load; /* Load an executable image. */ - LONG invoke; /* Invoke a standalong image. */ - LONG exec; /* Load and begin execution of a - standalone image. */ - LONG halt; /* Halt the machine. */ - LONG pdown; /* Power down the machine. */ - LONG restart; /* XXX soft reset??? */ - LONG reboot; /* Reboot the machine. */ - LONG imode; /* Enter PROM interactive mode. */ - LONG _unused1; /* Was ReturnFromMain(). */ - - /* PROM device tree interface. */ - LONG next_component; - LONG child_component; - LONG parent_component; - LONG component_data; - LONG child_add; - LONG comp_del; - LONG component_by_path; - - /* Misc. stuff. */ - LONG cfg_save; - LONG get_sysid; - - /* Probing for memory. */ - LONG get_mdesc; - LONG _unused2; /* was Signal() */ - - LONG get_tinfo; - LONG get_rtime; - - /* File type operations. */ - LONG get_vdirent; - LONG open; - LONG close; - LONG read; - LONG get_rstatus; - LONG write; - LONG seek; - LONG mount; - - /* Dealing with firmware environment variables. */ - LONG get_evar; - LONG set_evar; - - LONG get_finfo; - LONG set_finfo; - - /* Miscellaneous. */ - LONG cache_flush; -}; - -/* The SGI ARCS parameter block is in a fixed location for standalone - * programs to access PROM facilities easily. - */ -typedef struct _SYSTEM_PARAMETER_BLOCK { - ULONG magic; /* magic cookie */ -#define PROMBLOCK_MAGIC 0x53435241 - - ULONG len; /* length of parm block */ - USHORT ver; /* ARCS firmware version */ - USHORT rev; /* ARCS firmware revision */ - _PLONG rs_block; /* Restart block. */ - _PLONG dbg_block; /* Debug block. */ - _PLONG gevect; /* XXX General vector??? */ - _PLONG utlbvect; /* XXX UTLB vector??? */ - ULONG rveclen; /* Size of romvec struct. */ - _PVOID romvec; /* Function interface. */ - ULONG pveclen; /* Length of private vector. */ - _PVOID pvector; /* Private vector. */ - ULONG adap_cnt; /* Adapter count. */ - ULONG adap_typ0; /* First adapter type. */ - ULONG adap_vcnt0; /* Adapter 0 vector count. */ - _PVOID adap_vector; /* Adapter 0 vector ptr. */ - ULONG adap_typ1; /* Second adapter type. */ - ULONG adap_vcnt1; /* Adapter 1 vector count. */ - _PVOID adap_vector1; /* Adapter 1 vector ptr. */ - /* More adapter vectors go here... */ -} SYSTEM_PARAMETER_BLOCK, *PSYSTEM_PARAMETER_BLOCK; - -#define PROMBLOCK ((PSYSTEM_PARAMETER_BLOCK) (int)0xA0001000) -#define ROMVECTOR ((struct linux_romvec *) (long)(PROMBLOCK)->romvec) - -/* Cache layout parameter block. */ -union linux_cache_key { - struct param { -#ifdef __MIPSEL__ - unsigned short size; - unsigned char lsize; - unsigned char bsize; -#else /* !(__MIPSEL__) */ - unsigned char bsize; - unsigned char lsize; - unsigned short size; -#endif - } info; - unsigned long allinfo; -}; - -/* Configuration data. */ -struct linux_cdata { - char *name; - int mlen; - enum linux_devtypes type; -}; - -/* Common SGI ARCS firmware file descriptors. */ -#define SGIPROM_STDIN 0 -#define SGIPROM_STDOUT 1 - -/* Common SGI ARCS firmware file types. */ -#define SGIPROM_ROFILE 0x01 /* read-only file */ -#define SGIPROM_HFILE 0x02 /* hidden file */ -#define SGIPROM_SFILE 0x04 /* System file */ -#define SGIPROM_AFILE 0x08 /* Archive file */ -#define SGIPROM_DFILE 0x10 /* Directory file */ -#define SGIPROM_DELFILE 0x20 /* Deleted file */ - -/* SGI ARCS boot record information. */ -struct sgi_partition { - unsigned char flag; -#define SGIPART_UNUSED 0x00 -#define SGIPART_ACTIVE 0x80 - - unsigned char shead, ssect, scyl; /* unused */ - unsigned char systype; /* OS type, Irix or NT */ - unsigned char ehead, esect, ecyl; /* unused */ - unsigned char rsect0, rsect1, rsect2, rsect3; - unsigned char tsect0, tsect1, tsect2, tsect3; -}; - -#define SGIBBLOCK_MAGIC 0xaa55 -#define SGIBBLOCK_MAXPART 0x0004 - -struct sgi_bootblock { - unsigned char _unused[446]; - struct sgi_partition partitions[SGIBBLOCK_MAXPART]; - unsigned short magic; -}; - -/* BIOS parameter block. */ -struct sgi_bparm_block { - unsigned short bytes_sect; /* bytes per sector */ - unsigned char sect_clust; /* sectors per cluster */ - unsigned short sect_resv; /* reserved sectors */ - unsigned char nfats; /* # of allocation tables */ - unsigned short nroot_dirents; /* # of root directory entries */ - unsigned short sect_volume; /* sectors in volume */ - unsigned char media_type; /* media descriptor */ - unsigned short sect_fat; /* sectors per allocation table */ - unsigned short sect_track; /* sectors per track */ - unsigned short nheads; /* # of heads */ - unsigned short nhsects; /* # of hidden sectors */ -}; - -struct sgi_bsector { - unsigned char jmpinfo[3]; - unsigned char manuf_name[8]; - struct sgi_bparm_block info; -}; - -/* Debugging block used with SGI symmon symbolic debugger. */ -#define SMB_DEBUG_MAGIC 0xfeeddead -struct linux_smonblock { - unsigned long magic; - void (*handler)(void); /* Breakpoint routine. */ - unsigned long dtable_base; /* Base addr of dbg table. */ - int (*printf)(const char *fmt, ...); - unsigned long btable_base; /* Breakpoint table. */ - unsigned long mpflushreqs; /* SMP cache flush request list. */ - unsigned long ntab; /* Name table. */ - unsigned long stab; /* Symbol table. */ - int smax; /* Max # of symbols. */ -}; - -/* - * Macros for calling a 32-bit ARC implementation from 64-bit code - */ - -#if defined(CONFIG_MIPS64) && defined(CONFIG_ARC32) - -#define __arc_clobbers \ - "$2","$3" /* ... */, "$8","$9","$10","$11", \ - "$12","$13","$14","$15","$16","$24","25","$31" - -#define ARC_CALL0(dest) \ -({ long __res; \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec) \ - : __arc_clobbers, "$4","$5","$6","$7"); \ - (unsigned long) __res; \ -}) - -#define ARC_CALL1(dest,a1) \ -({ long __res; \ - register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), "r" (__a1) \ - : __arc_clobbers, "$5","$6","$7"); \ - (unsigned long) __res; \ -}) - -#define ARC_CALL2(dest,a1,a2) \ -({ long __res; \ - register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - register signed int __a2 __asm__("$5") = (int) (long) (a2); \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), "r" (__a1), "r" (__a2) \ - : __arc_clobbers, "$6","$7"); \ - __res; \ -}) - -#define ARC_CALL3(dest,a1,a2,a3) \ -({ long __res; \ - register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - register signed int __a2 __asm__("$5") = (int) (long) (a2); \ - register signed int __a3 __asm__("$6") = (int) (long) (a3); \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3) \ - : __arc_clobbers, "$7"); \ - __res; \ -}) - -#define ARC_CALL4(dest,a1,a2,a3,a4) \ -({ long __res; \ - register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - register signed int __a2 __asm__("$5") = (int) (long) (a2); \ - register signed int __a3 __asm__("$6") = (int) (long) (a3); \ - register signed int __a4 __asm__("$7") = (int) (long) (a4); \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3), \ - "r" (__a4) \ - : __arc_clobbers); \ - __res; \ -}) - -#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ -({ long __res; \ - register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - register signed int __a2 __asm__("$5") = (int) (long) (a2); \ - register signed int __a3 __asm__("$6") = (int) (long) (a3); \ - register signed int __a4 __asm__("$7") = (int) (long) (a4); \ - register signed int __a5 = (a5); \ - long __vec = (long) romvec->dest; \ - __asm__ __volatile__( \ - "dsubu\t$29, 32\n\t" \ - "sw\t%6, 16($29)\n\t" \ - "jalr\t%1\n\t" \ - "daddu\t$29, 32\n\t" \ - "move\t%0, $2" \ - : "=r" (__res), "=r" (__vec) \ - : "1" (__vec), \ - "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \ - "r" (__a5) \ - : __arc_clobbers); \ - __res; \ -}) - -#endif /* defined(CONFIG_MIPS64) && defined(CONFIG_ARC32) */ - -#if (defined(CONFIG_MIPS32) && defined(CONFIG_ARC32)) || \ - (defined(CONFIG_MIPS64) && defined(CONFIG_ARC64)) - -#define ARC_CALL0(dest) \ -({ long __res; \ - long (*__vec)(void) = (void *) romvec->dest; \ - \ - __res = __vec(); \ - __res; \ -}) - -#define ARC_CALL1(dest,a1) \ -({ long __res; \ - long __a1 = (long) (a1); \ - long (*__vec)(long) = (void *) romvec->dest; \ - \ - __res = __vec(__a1); \ - __res; \ -}) - -#define ARC_CALL2(dest,a1,a2) \ -({ long __res; \ - long __a1 = (long) (a1); \ - long __a2 = (long) (a2); \ - long (*__vec)(long, long) = (void *) romvec->dest; \ - \ - __res = __vec(__a1, __a2); \ - __res; \ -}) - -#define ARC_CALL3(dest,a1,a2,a3) \ -({ long __res; \ - long __a1 = (long) (a1); \ - long __a2 = (long) (a2); \ - long __a3 = (long) (a3); \ - long (*__vec)(long, long, long) = (void *) romvec->dest; \ - \ - __res = __vec(__a1, __a2, __a3); \ - __res; \ -}) - -#define ARC_CALL4(dest,a1,a2,a3,a4) \ -({ long __res; \ - long __a1 = (long) (a1); \ - long __a2 = (long) (a2); \ - long __a3 = (long) (a3); \ - long __a4 = (long) (a4); \ - long (*__vec)(long, long, long, long) = (void *) romvec->dest; \ - \ - __res = __vec(__a1, __a2, __a3, __a4); \ - __res; \ -}) - -#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \ -({ long __res; \ - long __a1 = (long) (a1); \ - long __a2 = (long) (a2); \ - long __a3 = (long) (a3); \ - long __a4 = (long) (a4); \ - long __a5 = (long) (a5); \ - long (*__vec)(long, long, long, long, long); \ - __vec = (void *) romvec->dest; \ - \ - __res = __vec(__a1, __a2, __a3, __a4, __a5); \ - __res; \ -}) -#endif /* both kernel and ARC either 32-bit or 64-bit */ - -#endif /* _ASM_SGIARCS_H */ diff --git a/include/asm-mips64/sgidefs.h b/include/asm-mips64/sgidefs.h deleted file mode 100644 index 876442fcfb3..00000000000 --- a/include/asm-mips64/sgidefs.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1999, 2001 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef __ASM_SGIDEFS_H -#define __ASM_SGIDEFS_H - -/* - * Using a Linux compiler for building Linux seems logic but not to - * everybody. - */ -#ifndef __linux__ -#error Use a Linux compiler or give up. -#endif - -/* - * Definitions for the ISA levels - * - * With the introduction of MIPS32 / MIPS64 instruction sets definitions - * MIPS ISAs are no longer subsets of each other. Therefore comparisons - * on these symbols except with == may result in unexpected results and - * are forbidden! - */ -#define _MIPS_ISA_MIPS1 1 -#define _MIPS_ISA_MIPS2 2 -#define _MIPS_ISA_MIPS3 3 -#define _MIPS_ISA_MIPS4 4 -#define _MIPS_ISA_MIPS5 5 -#define _MIPS_ISA_MIPS32 6 -#define _MIPS_ISA_MIPS64 7 - -/* - * Subprogram calling convention - */ -#define _MIPS_SIM_ABI32 1 -#define _MIPS_SIM_NABI32 2 -#define _MIPS_SIM_ABI64 3 - -#endif /* __ASM_SGIDEFS_H */ diff --git a/include/asm-mips64/shmbuf.h b/include/asm-mips64/shmbuf.h deleted file mode 100644 index 0a834f15e25..00000000000 --- a/include/asm-mips64/shmbuf.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef _ASM_SHMBUF_H -#define _ASM_SHMBUF_H - -/* - * The shmid64_ds structure for the MIPS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 2 miscellaneous 64-bit values - */ - -struct shmid64_ds { - struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ - __kernel_time_t shm_atime; /* last attach time */ - __kernel_time_t shm_dtime; /* last detach time */ - __kernel_time_t shm_ctime; /* last change time */ - __kernel_pid_t shm_cpid; /* pid of creator */ - __kernel_pid_t shm_lpid; /* pid of last operator */ - unsigned long shm_nattch; /* no. of current attaches */ - unsigned long __unused1; - unsigned long __unused2; -}; - -struct shminfo64 { - unsigned long shmmax; - unsigned long shmmin; - unsigned long shmmni; - unsigned long shmseg; - unsigned long shmall; - unsigned long __unused1; - unsigned long __unused2; - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _ASM_SHMBUF_H */ diff --git a/include/asm-mips64/shmiq.h b/include/asm-mips64/shmiq.h deleted file mode 100644 index 56c9716a601..00000000000 --- a/include/asm-mips64/shmiq.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Please note that the comments on this file may be out of date - * and that they represent what I have figured about the shmiq device - * so far in IRIX. - * - * This also contains some streams and idev bits. - * - * They may contain errors, please, refer to the source code of the Linux - * kernel for a definitive answer on what we have implemented - * - * Miguel. - */ -#ifndef _ASM_SHMIQ_H -#define _ASM_SHMIQ_H - -/* STREAMs ioctls */ -#define STRIOC ('S' << 8) -#define I_STR (STRIOC | 010) -#define I_PUSH (STRIOC | 02) -#define I_LINK (STRIOC | 014) -#define I_UNLINK (STRIOC | 015) - -/* Data structure passed on I_STR ioctls */ -struct strioctl { - int ic_cmd; /* streams ioctl command */ - int ic_timout; /* timeout */ - int ic_len; /* lenght of data */ - void *ic_dp; /* data */ -}; - -/* - * For mapping the shared memory input queue, you have to: - * - * 1. Map /dev/zero for the number of bytes you want to use - * for your shared memory input queue plus the size of the - * sharedMemoryInputQueue structure + 4 (I still have not figured - * what this one is for - * - * 2. Open /dev/shmiq - * - * 3. Open /dev/qcntlN N is [0..Nshmiqs] - * - * 4. Fill a shmiqreq structure. user_vaddr should point to the return - * address from the /dev/zero mmap. Arg is the number of shmqevents - * that fit into the /dev/zero region (remember that at the beginning there - * is a sharedMemoryInputQueue header). - * - * 5. Issue the ioctl (qcntlfd, QIOCATTACH, &your_shmiqreq); - */ - -struct shmiqreq { - char *user_vaddr; - int arg; -}; - -/* map the shmiq into the process address space */ -#define QIOCATTACH _IOW('Q',1,struct shmiqreq) - -/* remove mappings */ -#define QIOCDETACH _IO('Q',2) - -/* - * A shared memory input queue event. - */ -struct shmqdata { - unsigned char device; /* device major */ - unsigned char which; /* device minor */ - unsigned char type; /* event type */ - unsigned char flags; /* little event data */ - union { - int pos; /* big event data */ - short ptraxis [2]; /* event data for PTR events */ - } un; -}; - -/* indetifies the shmiq and the device */ -struct shmiqlinkid { - short int devminor; - short int index; -}; - -struct shmqevent { - union { - int time; - struct shmiqlinkid id; - } un ; - struct shmqdata data ; -}; - -/* - * sharedMemoryInputQueue: this describes the shared memory input queue. - * - * head is the user index into the events, user can modify this one. - * tail is managed by the kernel. - * flags is one of SHMIQ_OVERFLOW or SHMIQ_CORRUPTED - * if OVERFLOW is set it seems ioctl QUIOCSERVICED should be called - * to notify the kernel. - * events where the kernel sticks the events. - */ -struct sharedMemoryInputQueue { - volatile int head; /* user's index into events */ - volatile int tail; /* kernel's index into events */ - volatile unsigned int flags; /* place for out-of-band data */ -#define SHMIQ_OVERFLOW 1 -#define SHMIQ_CORRUPTED 2 - struct shmqevent events[1]; /* input event buffer */ -}; - -/* have to figure this one out */ -#define QIOCGETINDX _IOWR('Q', 8, int) - - -/* acknowledge shmiq overflow */ -#define QIOCSERVICED _IO('Q', 3) - -/* Double indirect I_STR ioctl, yeah, fun fun fun */ - -struct muxioctl { - int index; /* lower stream index */ - int realcmd; /* the actual command for the subdevice */ -}; -/* Double indirect ioctl */ -#define QIOCIISTR _IOW('Q', 7, struct muxioctl) - -/* Cursor ioclts: */ - -/* set cursor tracking mode */ -#define QIOCURSTRK _IOW('Q', 4, int) - -/* set cursor filter box */ -#define QIOCURSIGN _IOW('Q', 5, int [4]) - -/* set cursor axes */ -struct shmiqsetcurs { - short index; - short axes; -}; - -#define QIOCSETCURS _IOWR('Q', 9, struct shmiqsetcurs) - -/* set cursor position */ -struct shmiqsetcpos { - short x; - short y; -}; -#define QIOCSETCPOS _IOWR('Q', 10, struct shmiqsetcpos) - -/* get time since last event */ -#define QIOCGETITIME _IOR('Q', 11, time_t) - -/* set current screen */ -#define QIOCSETSCRN _IOW('Q',6,int) - - -/* -------------------- iDev stuff -------------------- */ - -#define IDEV_MAX_NAME_LEN 15 -#define IDEV_MAX_TYPE_LEN 15 - -typedef struct { - char devName[IDEV_MAX_NAME_LEN+1]; - char devType[IDEV_MAX_TYPE_LEN+1]; - unsigned short nButtons; - unsigned short nValuators; - unsigned short nLEDs; - unsigned short nStrDpys; - unsigned short nIntDpys; - unsigned char nBells; - unsigned char flags; -#define IDEV_HAS_KEYMAP 0x01 -#define IDEV_HAS_PROXIMITY 0x02 -#define IDEV_HAS_PCKBD 0x04 -} idevDesc; - -typedef struct { - char *nothing_for_now; -} idevInfo; - -#define IDEV_KEYMAP_NAME_LEN 15 - -typedef struct { - char name[IDEV_KEYMAP_NAME_LEN+1]; -} idevKeymapDesc; - -/* The valuator definition */ -typedef struct { - unsigned hwMinRes; - unsigned hwMaxRes; - int hwMinVal; - int hwMaxVal; - - unsigned char possibleModes; -#define IDEV_ABSOLUTE 0x0 -#define IDEV_RELATIVE 0x1 -#define IDEV_EITHER 0x2 - - unsigned char mode; /* One of: IDEV_ABSOLUTE, IDEV_RELATIVE */ - - unsigned short resolution; - int minVal; - int maxVal; -} idevValuatorDesc; - -/* This is used to query a specific valuator with the IDEVGETVALUATORDESC ioctl */ -typedef struct { - short valNum; - unsigned short flags; - idevValuatorDesc desc; -} idevGetSetValDesc; - -#define IDEVGETDEVICEDESC _IOWR('i', 0, idevDesc) -#define IDEVGETVALUATORDESC _IOWR('i', 1, idevGetSetValDesc) -#define IDEVGETKEYMAPDESC _IOWR('i', 2, idevKeymapDesc) -#define IDEVINITDEVICE _IOW ('i', 51, unsigned int) - - -#ifdef __KERNEL__ - -/* These are only interpreted by SHMIQ-attacheable devices and are internal - * to the kernel - */ -#define SHMIQ_OFF _IO('Q',1) -#define SHMIQ_ON _IO('Q',2) - -void shmiq_push_event (struct shmqevent *e); -int get_sioc (struct strioctl *sioc, unsigned long arg); -#endif - -#endif /* _ASM_SHMIQ_H */ diff --git a/include/asm-mips64/shmparam.h b/include/asm-mips64/shmparam.h deleted file mode 100644 index 305a08b6b64..00000000000 --- a/include/asm-mips64/shmparam.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef _ASM_SHMPARAM_H -#define _ASM_SHMPARAM_H - -#define SHMLBA 0x40000 /* attach addr a multiple of this */ - -#endif /* _ASM_SHMPARAM_H */ diff --git a/include/asm-mips64/sibyte/board.h b/include/asm-mips64/sibyte/board.h deleted file mode 100644 index 57473ab5c6f..00000000000 --- a/include/asm-mips64/sibyte/board.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2000, 2001 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef _SIBYTE_BOARD_H -#define _SIBYTE_BOARD_H - -#ifdef CONFIG_SIBYTE_BOARD - -#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \ - defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) -#include -#endif - -#if defined(CONFIG_SIBYTE_SENTOSA) || defined(CONFIG_SIBYTE_RHONE) -#include -#endif - -#ifdef CONFIG_SIBYTE_CARMEL -#include -#endif - -#ifdef __ASSEMBLY__ - -#ifdef LEDS_PHYS -#define setleds(t0,t1,c0,c1,c2,c3) \ - li t0, (LEDS_PHYS|0xa0000000); \ - li t1, c0; \ - sb t1, 0x18(t0); \ - li t1, c1; \ - sb t1, 0x10(t0); \ - li t1, c2; \ - sb t1, 0x08(t0); \ - li t1, c3; \ - sb t1, 0x00(t0) -#else -#define setleds(t0,t1,c0,c1,c2,c3) -#endif /* LEDS_PHYS */ - -#else - -void swarm_setup(void); - -#ifdef LEDS_PHYS -extern void setleds(char *str); -#else -#define setleds(s) do { } while (0) -#endif /* LEDS_PHYS */ - -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_SIBYTE_BOARD */ - -#endif /* _SIBYTE_BOARD_H */ diff --git a/include/asm-mips64/sibyte/carmel.h b/include/asm-mips64/sibyte/carmel.h deleted file mode 100644 index e691b6dadba..00000000000 --- a/include/asm-mips64/sibyte/carmel.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2002 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#ifndef __ASM_SIBYTE_CARMEL_H -#define __ASM_SIBYTE_CARMEL_H - -#include -#include - -#define SIBYTE_BOARD_NAME "Carmel" - -#define GPIO_PHY_INTERRUPT 2 -#define GPIO_NONMASKABLE_INT 3 -#define GPIO_CF_INSERTED 6 -#define GPIO_MONTEREY_RESET 7 -#define GPIO_QUADUART_INT 8 -#define GPIO_CF_INT 9 -#define GPIO_FPGA_CCLK 10 -#define GPIO_FPGA_DOUT 11 -#define GPIO_FPGA_DIN 12 -#define GPIO_FPGA_PGM 13 -#define GPIO_FPGA_DONE 14 -#define GPIO_FPGA_INIT 15 - -#define LEDS_CS 2 -#define LEDS_PHYS 0x100C0000 -#define MLEDS_CS 3 -#define MLEDS_PHYS 0x100A0000 -#define UART_CS 4 -#define UART_PHYS 0x100D0000 -#define ARAVALI_CS 5 -#define ARAVALI_PHYS 0x11000000 -#define IDE_CS 6 -#define IDE_PHYS 0x100B0000 -#define ARAVALI2_CS 7 -#define ARAVALI2_PHYS 0x100E0000 - -#if defined(CONFIG_SIBYTE_CARMEL) -#define K_GPIO_GB_IDE 9 -#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) -#endif - - -#endif /* __ASM_SIBYTE_CARMEL_H */ diff --git a/include/asm-mips64/sibyte/io.h b/include/asm-mips64/sibyte/io.h deleted file mode 100644 index b2b8b8be616..00000000000 --- a/include/asm-mips64/sibyte/io.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_SIBYTE_IO_H -#define _ASM_SIBYTE_IO_H - -#include - -#define IO_SPACE_BASE K1BASE - -/* For Indigo2. */ -#define IO_SPACE_LIMIT 0xffff - -/* XXX ISA specific functions go here here. */ - -#endif /* _ASM_SIBYTE_IO_H */ diff --git a/include/asm-mips64/sibyte/sb1250.h b/include/asm-mips64/sibyte/sb1250.h deleted file mode 100644 index f28e14d7de3..00000000000 --- a/include/asm-mips64/sibyte/sb1250.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef _ASM_SIBYTE_SB1250_H -#define _ASM_SIBYTE_SB1250_H - -/* - * yymmddpp: year, month, day, patch. - * should sync with Makefile EXTRAVERSION - */ -#define SIBYTE_RELEASE 0x02111403 - -#define SB1250_NR_IRQS 64 - -#define SB1250_DUART_MINOR_BASE 64 - -#ifndef __ASSEMBLY__ - -#include - -/* For revision/pass information */ -#include -extern unsigned int sb1_pass; -extern unsigned int soc_pass; -extern unsigned int soc_type; -extern unsigned int periph_rev; -extern unsigned int zbbus_mhz; - -extern void sb1250_time_init(void); -extern unsigned long sb1250_gettimeoffset(void); -extern void sb1250_mask_irq(int cpu, int irq); -extern void sb1250_unmask_irq(int cpu, int irq); -extern void sb1250_smp_finish(void); -extern void prom_printf(char *fmt, ...); - -#define AT_spin \ - __asm__ __volatile__ ( \ - ".set noat\n" \ - "li $at, 0\n" \ - "1: beqz $at, 1b\n" \ - ".set at\n" \ - ) - -#endif - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_defs.h b/include/asm-mips64/sibyte/sb1250_defs.h deleted file mode 100644 index 96088fb074a..00000000000 --- a/include/asm-mips64/sibyte/sb1250_defs.h +++ /dev/null @@ -1,242 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Global constants and macros File: sb1250_defs.h - * - * This file contains macros and definitions used by the other - * include files. - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - -#ifndef _SB1250_DEFS_H -#define _SB1250_DEFS_H - -/* - * These headers require ANSI C89 string concatenation, and GCC or other - * 'long long' (64-bit integer) support. - */ -#if !defined(__STDC__) && !defined(_MSC_VER) -#error SiByte headers require ANSI C89 support -#endif - - -/* ********************************************************************* - * Macros for feature tests, used to enable include file features - * for chip features only present in certain chip revisions. - * - * SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision - * which is to be exposed by the headers. If undefined, it defaults to - * "all features." - * - * Use like: - * - * #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_112x_PASS1 - * - * Generate defines only for that revision of chip. - * - * #if SIBYTE_HDR_FEATURE(chip,pass) - * - * True if header features for that revision or later of - * that particular chip type are enabled in SIBYTE_HDR_FEATURES. - * (Use this to bracket #defines for features present in a given - * revision and later.) - * - * Note that there is no implied ordering between chip types. - * - * Note also that 'chip' and 'pass' must textually exactly - * match the defines below. So, for example, - * SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but - * SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons). - * - * #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass) - * - * Same as SIBYTE_HDR_FEATURE, but true for the named revision - * and earlier revisions of the named chip type. - * - * #if SIBYTE_HDR_FEATURE_EXACT(chip,pass) - * - * Same as SIBYTE_HDR_FEATURE, but only true for the named - * revision of the named chip type. (Note that this CANNOT - * be used to verify that you're compiling only for that - * particular chip/revision. It will be true any time this - * chip/revision is included in SIBYTE_HDR_FEATURES.) - * - * #if SIBYTE_HDR_FEATURE_CHIP(chip) - * - * True if header features for (any revision of) that chip type - * are enabled in SIBYTE_HDR_FEATURES. (Use this to bracket - * #defines for features specific to a given chip type.) - * - * Mask values currently include room for additional revisions of each - * chip type, but can be renumbered at will. Note that they MUST fit - * into 31 bits and may not include C type constructs, for safe use in - * CPP conditionals. Bit positions within chip types DO indicate - * ordering, so be careful when adding support for new minor revs. - ********************************************************************* */ - -#define SIBYTE_HDR_FMASK_1250_ALL 0x00000ff -#define SIBYTE_HDR_FMASK_1250_PASS1 0x0000001 -#define SIBYTE_HDR_FMASK_1250_PASS2 0x0000002 -#define SIBYTE_HDR_FMASK_1250_PASS3 0x0000004 - -#define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00 -#define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100 - -/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ -#define SIBYTE_HDR_FMASK(chip, pass) \ - (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass) -#define SIBYTE_HDR_FMASK_ALLREVS(chip) \ - (SIBYTE_HDR_FMASK_ ## chip ## _ALL) - -#define SIBYTE_HDR_FMASK_ALL \ - (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL) - -#ifndef SIBYTE_HDR_FEATURES -#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL -#endif - - -/* Bit mask for revisions of chip exclusively before the named revision. */ -#define SIBYTE_HDR_FMASK_BEFORE(chip, pass) \ - ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip)) - -/* Bit mask for revisions of chip exclusively after the named revision. */ -#define SIBYTE_HDR_FMASK_AFTER(chip, pass) \ - (~(SIBYTE_HDR_FMASK(chip, pass) \ - | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip)) - - -/* True if header features enabled for (any revision of) that chip type. */ -#define SIBYTE_HDR_FEATURE_CHIP(chip) \ - (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES)) - -/* True if header features enabled for that rev or later, inclusive. */ -#define SIBYTE_HDR_FEATURE(chip, pass) \ - (!! ((SIBYTE_HDR_FMASK(chip, pass) \ - | SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES)) - -/* True if header features enabled for exactly that rev. */ -#define SIBYTE_HDR_FEATURE_EXACT(chip, pass) \ - (!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES)) - -/* True if header features enabled for that rev or before, inclusive. */ -#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass) \ - (!! ((SIBYTE_HDR_FMASK(chip, pass) \ - | SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES)) - - -/* ********************************************************************* - * Naming schemes for constants in these files: - * - * M_xxx MASK constant (identifies bits in a register). - * For multi-bit fields, all bits in the field will - * be set. - * - * K_xxx "Code" constant (value for data in a multi-bit - * field). The value is right justified. - * - * V_xxx "Value" constant. This is the same as the - * corresponding "K_xxx" constant, except it is - * shifted to the correct position in the register. - * - * S_xxx SHIFT constant. This is the number of bits that - * a field value (code) needs to be shifted - * (towards the left) to put the value in the right - * position for the register. - * - * A_xxx ADDRESS constant. This will be a physical - * address. Use the PHYS_TO_K1 macro to generate - * a K1SEG address. - * - * R_xxx RELATIVE offset constant. This is an offset from - * an A_xxx constant (usually the first register in - * a group). - * - * G_xxx(X) GET value. This macro obtains a multi-bit field - * from a register, masks it, and shifts it to - * the bottom of the register (retrieving a K_xxx - * value, for example). - * - * V_xxx(X) VALUE. This macro computes the value of a - * K_xxx constant shifted to the correct position - * in the register. - ********************************************************************* */ - - - - -/* - * Cast to 64-bit number. Presumably the syntax is different in - * assembly language. - * - * Note: you'll need to define uint32_t and uint64_t in your headers. - */ - -#if !defined(__ASSEMBLER__) -#define _SB_MAKE64(x) ((uint64_t)(x)) -#define _SB_MAKE32(x) ((uint32_t)(x)) -#else -#define _SB_MAKE64(x) (x) -#define _SB_MAKE32(x) (x) -#endif - - -/* - * Make a mask for 1 bit at position 'n' - */ - -#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n)) -#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n)) - -/* - * Make a mask for 'v' bits at position 'n' - */ - -#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) -#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) - -/* - * Make a value at 'v' at bit position 'n' - */ - -#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n)) -#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n)) - -#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) -#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) - -/* - * Macros to read/write on-chip registers - * XXX should we do the PHYS_TO_K1 here? - */ - - -#if defined(__mips64) && !defined(__ASSEMBLER__) -#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) -#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) -#endif /* __ASSEMBLER__ */ - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_dma.h b/include/asm-mips64/sibyte/sb1250_dma.h deleted file mode 100644 index f1b08d32338..00000000000 --- a/include/asm-mips64/sibyte/sb1250_dma.h +++ /dev/null @@ -1,594 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * DMA definitions File: sb1250_dma.h - * - * This module contains constants and macros useful for - * programming the SB1250's DMA controllers, both the data mover - * and the Ethernet DMA. - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_DMA_H -#define _SB1250_DMA_H - - -#include "sb1250_defs.h" - -/* ********************************************************************* - * DMA Registers - ********************************************************************* */ - -/* - * Ethernet and Serial DMA Configuration Register 0 (Table 7-4) - * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 - * Registers: DMA_CONFIG0_MAC_x_TX_CH_0 - * Registers: DMA_CONFIG0_SER_x_RX - * Registers: DMA_CONFIG0_SER_x_TX - */ - - -#define M_DMA_DROP _SB_MAKEMASK1(0) - -#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1) -#define M_DMA_RESERVED1 _SB_MAKEMASK1(2) - -#define S_DMA_DESC_TYPE _SB_MAKE64(1) -#define M_DMA_DESC_TYPE _SB_MAKE64(2,S_DMA_DESC_TYPE) -#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE) -#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE) - -#define K_DMA_DESC_TYPE_RING_AL 0 -#define K_DMA_DESC_TYPE_CHAIN_AL 1 - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define K_DMA_DESC_TYPE_RING_UAL_WI 2 -#define K_DMA_DESC_TYPE_RING_UAL_RMW 3 -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) -#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) -#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5) -#define M_DMA_TBX_EN _SB_MAKEMASK1(6) -#define M_DMA_TDX_EN _SB_MAKEMASK1(7) - -#define S_DMA_INT_PKTCNT _SB_MAKE64(8) -#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT) -#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT) -#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT) - -#define S_DMA_RINGSZ _SB_MAKE64(16) -#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ) -#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ) -#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ) - -#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) -#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK) -#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK) -#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK) - -#define S_DMA_LOW_WATERMARK _SB_MAKE64(48) -#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK) -#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK) -#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK) - -/* - * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) - * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 - * Registers: DMA_CONFIG1_DMA_x_TX_CH_0 - * Registers: DMA_CONFIG1_SER_x_RX - * Registers: DMA_CONFIG1_SER_x_TX - */ - -#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0) -#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1) -#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2) -#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3) -#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) -#define M_DMA_L2CA _SB_MAKEMASK1(5) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) -#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) -#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define M_DMA_MBZ1 _SB_MAKEMASK(6,15) - -#define S_DMA_HDR_SIZE _SB_MAKE64(21) -#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE) -#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE) -#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE) - -#define M_DMA_MBZ2 _SB_MAKEMASK(5,32) - -#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) -#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE) -#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE) -#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE) - -#define S_DMA_INT_TIMEOUT _SB_MAKE64(48) -#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT) -#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT) -#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT) - -/* - * Ethernet and Serial DMA Descriptor base address (Table 7-6) - */ - -#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0) - - -/* - * ASIC Mode Base Address (Table 7-7) - */ - -#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0) - -/* - * DMA Descriptor Count Registers (Table 7-8) - */ - -/* No bitfields */ - - -/* - * Current Descriptor Address Register (Table 7-11) - */ - -#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) -#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR) -#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) -#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) -#endif /* 1250 PASS3 || 112x PASS1 */ - -/* - * Receive Packet Drop Registers - */ -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_DMA_OODLOST_RX _SB_MAKE64(0) -#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX) -#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX) - -#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) -#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX) -#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX) -#endif /* 1250 PASS3 || 112x PASS1 */ - -/* ********************************************************************* - * DMA Descriptors - ********************************************************************* */ - -/* - * Descriptor doubleword "A" (Table 7-12) - */ - -#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) -#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET) -#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET) -#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET) - -/* Note: Don't shift the address over, just mask it with the mask below */ -#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR) - -#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) -#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE) -#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE) -#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) -#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT) -#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) -#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) - -#define S_DMA_DSCRA_STATUS _SB_MAKE64(51) -#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS) -#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS) -#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS) - -/* - * Descriptor doubleword "B" (Table 7-13) - */ - - -#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) -#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS) -#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS) -#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) -#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE) -#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE) -#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) - -/* Note: Don't shift the address over, just mask it with the mask below */ -#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) -#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR) - -#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) -#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE) -#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE) -#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE) - -#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) -#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB) -#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB) -#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) -#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE) -#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE) -#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE) - -/* - * from pass2 some bits in dscr_b are also used for rx status - */ -#define S_DMA_DSCRB_STATUS _SB_MAKE64(0) -#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS) -#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS) -#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS) - -/* - * Ethernet Descriptor Status Bits (Table 7-15) - */ - -#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) -#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* Note: BADTCPCS is actually in DSCR_B options field */ -#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) -#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define S_DMA_ETHRX_RXCH 53 -#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH) -#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH) -#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH) - -#define S_DMA_ETHRX_PKTTYPE 55 -#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE) -#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE) -#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE) - -#define K_DMA_ETHRX_PKTTYPE_IPV4 0 -#define K_DMA_ETHRX_PKTTYPE_ARPV4 1 -#define K_DMA_ETHRX_PKTTYPE_802 2 -#define K_DMA_ETHRX_PKTTYPE_OTHER 3 -#define K_DMA_ETHRX_PKTTYPE_USER0 4 -#define K_DMA_ETHRX_PKTTYPE_USER1 5 -#define K_DMA_ETHRX_PKTTYPE_USER2 6 -#define K_DMA_ETHRX_PKTTYPE_USER3 7 - -#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58) -#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59) -#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60) -#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61) -#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62) -#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63) - -/* - * Ethernet Transmit Status Bits (Table 7-16) - */ - -#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) - -/* - * Ethernet Transmit Options (Table 7-17) - */ - -#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00) -#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01) -#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02) -#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03) -#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04) -#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05) -#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6) -#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07) -#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08) -#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09) -#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A) -#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B) -#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C) -#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D) -#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E) -#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F) - -/* - * Serial Receive Options (Table 7-18) - */ -#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56) -#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57) -#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58) -#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59) -#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60) -#define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61) -#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62) -#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63) - -/* - * Serial Transmit Status Bits (Table 7-20) - */ - -#define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63) - -/* - * Serial Transmit Options (Table 7-21) - */ - -#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0) -#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1) -#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2) -#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3) - - -/* ********************************************************************* - * Data Mover Registers - ********************************************************************* */ - -/* - * Data Mover Descriptor Base Address Register (Table 7-22) - * Register: DM_DSCR_BASE_0 - * Register: DM_DSCR_BASE_1 - * Register: DM_DSCR_BASE_2 - * Register: DM_DSCR_BASE_3 - */ - -#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4,0) - -/* Note: Just mask the base address and then OR it in. */ -#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) -#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR) - -#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) -#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ) -#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ) -#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ) - -#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) -#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY) -#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY) -#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY) - -#define K_DM_DSCR_BASE_PRIORITY_1 0 -#define K_DM_DSCR_BASE_PRIORITY_2 1 -#define K_DM_DSCR_BASE_PRIORITY_4 2 -#define K_DM_DSCR_BASE_PRIORITY_8 3 -#define K_DM_DSCR_BASE_PRIORITY_16 4 - -#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59) -#define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60) -#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */ -#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */ -#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) -#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) - -/* - * Data Mover Descriptor Count Register (Table 7-25) - */ - -/* no bitfields */ - -/* - * Data Mover Current Descriptor Address (Table 7-24) - * Register: DM_CUR_DSCR_ADDR_0 - * Register: DM_CUR_DSCR_ADDR_1 - * Register: DM_CUR_DSCR_ADDR_2 - * Register: DM_CUR_DSCR_ADDR_3 - */ - -#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) -#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR) - -#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) -#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT) -#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT) -#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\ - M_DM_CUR_DSCR_DSCR_COUNT) - - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* - * Data Mover Channel Partial Result Registers - * Register: DM_PARTIAL_0 - * Register: DM_PARTIAL_1 - * Register: DM_PARTIAL_2 - * Register: DM_PARTIAL_3 - */ -#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) -#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL) -#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL) -#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\ - M_DM_PARTIAL_CRC_PARTIAL) - -#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) -#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL) -#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL) -#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\ - M_DM_PARTIAL_TCPCS_PARTIAL) - -#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) -#endif /* 1250 PASS3 || 112x PASS1 */ - - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* - * Data Mover CRC Definition Registers - * Register: CRC_DEF_0 - * Register: CRC_DEF_1 - */ -#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) -#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT) -#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT) -#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\ - M_CRC_DEF_CRC_INIT) - -#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) -#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY) -#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY) -#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\ - M_CRC_DEF_CRC_POLY) -#endif /* 1250 PASS3 || 112x PASS1 */ - - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* - * Data Mover CRC/Checksum Definition Registers - * Register: CTCP_DEF_0 - * Register: CTCP_DEF_1 - */ -#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) -#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR) -#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR) -#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\ - M_CTCP_DEF_CRC_TXOR) - -#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) -#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT) -#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT) -#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\ - M_CTCP_DEF_TCPCS_INIT) - -#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) -#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH) -#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH) -#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\ - M_CTCP_DEF_CRC_WIDTH) - -#define K_CTCP_DEF_CRC_WIDTH_4 0 -#define K_CTCP_DEF_CRC_WIDTH_2 1 -#define K_CTCP_DEF_CRC_WIDTH_1 2 - -#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) -#endif /* 1250 PASS3 || 112x PASS1 */ - - -/* - * Data Mover Descriptor Doubleword "A" (Table 7-26) - */ - -#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) -#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR) - -#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) -#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) -#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42) -#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43) -#endif /* up to 1250 PASS1 */ - -#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) -#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST) -#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST) - -#define K_DM_DSCRA_DIR_DEST_INCR 0 -#define K_DM_DSCRA_DIR_DEST_DECR 1 -#define K_DM_DSCRA_DIR_DEST_CONST 2 - -#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST) -#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST) - -#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) -#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC) -#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC) - -#define K_DM_DSCRA_DIR_SRC_INCR 0 -#define K_DM_DSCRA_DIR_SRC_DECR 1 -#define K_DM_DSCRA_DIR_SRC_CONST 2 - -#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC) -#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC) - - -#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) -#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49) -#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) -#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) -#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) -#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) -#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) -#define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57) -#define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58) -#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) -#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) -#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61) - -/* - * Data Mover Descriptor Doubleword "B" (Table 7-25) - */ - -#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) -#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR) - -#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) -#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH) -#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH) -#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH) - - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_genbus.h b/include/asm-mips64/sibyte/sb1250_genbus.h deleted file mode 100644 index 0d9dfac3d7d..00000000000 --- a/include/asm-mips64/sibyte/sb1250_genbus.h +++ /dev/null @@ -1,276 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Generic Bus Constants File: sb1250_genbus.h - * - * This module contains constants and macros useful for - * manipulating the SB1250's Generic Bus interface - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_GENBUS_H -#define _SB1250_GENBUS_H - -#include "sb1250_defs.h" - -/* - * Generic Bus Region Configuration Registers (Table 11-4) - */ - -#define S_IO_RDY_ACTIVE 0 -#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) - -#define S_IO_ENA_RDY 1 -#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) - -#define S_IO_WIDTH_SEL 2 -#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL) -#define K_IO_WIDTH_SEL_1 0 -#define K_IO_WIDTH_SEL_2 1 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define K_IO_WIDTH_SEL_1L 2 -#endif /* 1250 PASS2 || 112x PASS1 */ -#define K_IO_WIDTH_SEL_4 3 -#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL) -#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL) - -#define S_IO_PARITY_ENA 4 -#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_IO_BURST_EN 5 -#define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) -#endif /* 1250 PASS2 || 112x PASS1 */ -#define S_IO_PARITY_ODD 6 -#define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) -#define S_IO_NONMUX 7 -#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) - -#define S_IO_TIMEOUT 8 -#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT) -#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT) -#define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT) - -/* - * Generic Bus Region Size register (Table 11-5) - */ - -#define S_IO_MULT_SIZE 0 -#define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE) -#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE) -#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE) - -#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ - -/* - * Generic Bus Region Address (Table 11-6) - */ - -#define S_IO_START_ADDR 0 -#define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR) -#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR) -#define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR) - -#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ - -/* - * Generic Bus Region 0 Timing Registers (Table 11-7) - */ - -#define S_IO_ALE_WIDTH 0 -#define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH) -#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH) -#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_IO_EARLY_CS _SB_MAKEMASK1(3) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#define S_IO_ALE_TO_CS 4 -#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS) -#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS) -#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_IO_BURST_WIDTH _SB_MAKE64(6) -#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH) -#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH) -#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#define S_IO_CS_WIDTH 8 -#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH) -#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH) -#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH) - -#define S_IO_RDY_SMPLE 13 -#define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE) -#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE) -#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE) - - -/* - * Generic Bus Timing 1 Registers (Table 11-8) - */ - -#define S_IO_ALE_TO_WRITE 0 -#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE) -#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE) -#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_IO_RDY_SYNC _SB_MAKEMASK1(3) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#define S_IO_WRITE_WIDTH 4 -#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH) -#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH) -#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH) - -#define S_IO_IDLE_CYCLE 8 -#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE) -#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE) -#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE) - -#define S_IO_OE_TO_CS 12 -#define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS) -#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS) -#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS) - -#define S_IO_CS_TO_OE 14 -#define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE) -#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE) -#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE) - -/* - * Generic Bus Interrupt Status Register (Table 11-9) - */ - -#define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8) -#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) -#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) -#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) -#define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3) -#define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4) -#define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5) -#define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6) -#define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7) - -#define M_IO_RD_PAR_INT _SB_MAKEMASK1(9) -#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) -#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) -#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_IO_COH_ERR _SB_MAKEMASK1(14) -#endif /* 1250 PASS2 || 112x PASS1 */ - -/* - * PCMCIA configuration register (Table 12-6) - */ - -#define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0) -#define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1) -#define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2) -#define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3) -#define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4) -#define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5) -#define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6) -#define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7) -#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) -#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) - -/* - * PCMCIA status register (Table 12-7) - */ - -#define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0) -#define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1) -#define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2) -#define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3) -#define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4) -#define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5) -#define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6) -#define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7) -#define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8) -#define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9) -#define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10) - -/* - * GPIO Interrupt Type Register (table 13-3) - */ - -#define K_GPIO_INTR_DISABLE 0 -#define K_GPIO_INTR_EDGE 1 -#define K_GPIO_INTR_LEVEL 2 -#define K_GPIO_INTR_SPLIT 3 - -#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) -#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n)) -#define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n)) -#define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n)) - -#define S_GPIO_INTR_TYPE0 0 -#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0) -#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0) -#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0) - -#define S_GPIO_INTR_TYPE2 2 -#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2) -#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2) -#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2) - -#define S_GPIO_INTR_TYPE4 4 -#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4) -#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4) -#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4) - -#define S_GPIO_INTR_TYPE6 6 -#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6) -#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6) -#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6) - -#define S_GPIO_INTR_TYPE8 8 -#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8) -#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8) -#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8) - -#define S_GPIO_INTR_TYPE10 10 -#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10) -#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10) -#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10) - -#define S_GPIO_INTR_TYPE12 12 -#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12) -#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12) -#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12) - -#define S_GPIO_INTR_TYPE14 14 -#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14) -#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14) -#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14) - - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_int.h b/include/asm-mips64/sibyte/sb1250_int.h deleted file mode 100644 index c3f74df211f..00000000000 --- a/include/asm-mips64/sibyte/sb1250_int.h +++ /dev/null @@ -1,247 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Interrupt Mapper definitions File: sb1250_int.h - * - * This module contains constants for manipulating the SB1250's - * interrupt mapper and definitions for the interrupt sources. - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_INT_H -#define _SB1250_INT_H - -#include "sb1250_defs.h" - -/* ********************************************************************* - * Interrupt Mapper Constants - ********************************************************************* */ - -/* - * Interrupt sources (Table 4-8, UM 0.2) - * - * First, the interrupt numbers. - */ - -#define K_INT_WATCHDOG_TIMER_0 0 -#define K_INT_WATCHDOG_TIMER_1 1 -#define K_INT_TIMER_0 2 -#define K_INT_TIMER_1 3 -#define K_INT_TIMER_2 4 -#define K_INT_TIMER_3 5 -#define K_INT_SMB_0 6 -#define K_INT_SMB_1 7 -#define K_INT_UART_0 8 -#define K_INT_UART_1 9 -#define K_INT_SER_0 10 -#define K_INT_SER_1 11 -#define K_INT_PCMCIA 12 -#define K_INT_ADDR_TRAP 13 -#define K_INT_PERF_CNT 14 -#define K_INT_TRACE_FREEZE 15 -#define K_INT_BAD_ECC 16 -#define K_INT_COR_ECC 17 -#define K_INT_IO_BUS 18 -#define K_INT_MAC_0 19 -#define K_INT_MAC_1 20 -#define K_INT_MAC_2 21 -#define K_INT_DM_CH_0 22 -#define K_INT_DM_CH_1 23 -#define K_INT_DM_CH_2 24 -#define K_INT_DM_CH_3 25 -#define K_INT_MBOX_0 26 -#define K_INT_MBOX_1 27 -#define K_INT_MBOX_2 28 -#define K_INT_MBOX_3 29 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define K_INT_CYCLE_CP0_INT 30 -#define K_INT_CYCLE_CP1_INT 31 -#endif /* 1250 PASS2 || 112x PASS1 */ -#define K_INT_GPIO_0 32 -#define K_INT_GPIO_1 33 -#define K_INT_GPIO_2 34 -#define K_INT_GPIO_3 35 -#define K_INT_GPIO_4 36 -#define K_INT_GPIO_5 37 -#define K_INT_GPIO_6 38 -#define K_INT_GPIO_7 39 -#define K_INT_GPIO_8 40 -#define K_INT_GPIO_9 41 -#define K_INT_GPIO_10 42 -#define K_INT_GPIO_11 43 -#define K_INT_GPIO_12 44 -#define K_INT_GPIO_13 45 -#define K_INT_GPIO_14 46 -#define K_INT_GPIO_15 47 -#define K_INT_LDT_FATAL 48 -#define K_INT_LDT_NONFATAL 49 -#define K_INT_LDT_SMI 50 -#define K_INT_LDT_NMI 51 -#define K_INT_LDT_INIT 52 -#define K_INT_LDT_STARTUP 53 -#define K_INT_LDT_EXT 54 -#define K_INT_PCI_ERROR 55 -#define K_INT_PCI_INTA 56 -#define K_INT_PCI_INTB 57 -#define K_INT_PCI_INTC 58 -#define K_INT_PCI_INTD 59 -#define K_INT_SPARE_2 60 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define K_INT_MAC_0_CH1 61 -#define K_INT_MAC_1_CH1 62 -#define K_INT_MAC_2_CH1 63 -#endif /* 1250 PASS2 || 112x PASS1 */ - -/* - * Mask values for each interrupt - */ - -#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0) -#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1) -#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0) -#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1) -#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2) -#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3) -#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0) -#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1) -#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0) -#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1) -#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0) -#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1) -#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA) -#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP) -#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT) -#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE) -#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC) -#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC) -#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS) -#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0) -#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1) -#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2) -#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0) -#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1) -#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2) -#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3) -#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0) -#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) -#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) -#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) -#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) -#endif /* 1250 PASS2 || 112x PASS1 */ -#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0) -#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1) -#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2) -#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3) -#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4) -#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5) -#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6) -#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7) -#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8) -#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9) -#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10) -#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11) -#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12) -#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13) -#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14) -#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15) -#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL) -#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL) -#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI) -#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI) -#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT) -#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP) -#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT) -#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR) -#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA) -#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB) -#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC) -#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD) -#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1) -#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1) -#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1) -#endif /* 1250 PASS2 || 112x PASS1 */ - -/* - * Interrupt mappings - */ - -#define K_INT_MAP_I0 0 /* interrupt pins on processor */ -#define K_INT_MAP_I1 1 -#define K_INT_MAP_I2 2 -#define K_INT_MAP_I3 3 -#define K_INT_MAP_I4 4 -#define K_INT_MAP_I5 5 -#define K_INT_MAP_NMI 6 /* nonmaskable */ -#define K_INT_MAP_DINT 7 /* debug interrupt */ - -/* - * LDT Interrupt Set Register (table 4-5) - */ - -#define S_INT_LDT_INTMSG 0 -#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG) -#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG) -#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG) - -#define K_INT_LDT_INTMSG_FIXED 0 -#define K_INT_LDT_INTMSG_ARBITRATED 1 -#define K_INT_LDT_INTMSG_SMI 2 -#define K_INT_LDT_INTMSG_NMI 3 -#define K_INT_LDT_INTMSG_INIT 4 -#define K_INT_LDT_INTMSG_STARTUP 5 -#define K_INT_LDT_INTMSG_EXTINT 6 -#define K_INT_LDT_INTMSG_RESERVED 7 - -#define M_INT_LDT_EDGETRIGGER 0 -#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3) - -#define M_INT_LDT_PHYSICALDEST 0 -#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) - -#define S_INT_LDT_INTDEST 5 -#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST) -#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST) -#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST) - -#define S_INT_LDT_VECTOR 13 -#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR) -#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR) -#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR) - -/* - * Vector format (Table 4-6) - */ - -#define M_LDTVECT_RAISEINT 0x00 -#define M_LDTVECT_RAISEMBOX 0x40 - - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_l2c.h b/include/asm-mips64/sibyte/sb1250_l2c.h deleted file mode 100644 index 799db828d96..00000000000 --- a/include/asm-mips64/sibyte/sb1250_l2c.h +++ /dev/null @@ -1,128 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * L2 Cache constants and macros File: sb1250_l2c.h - * - * This module contains constants useful for manipulating the - * level 2 cache. - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_L2C_H -#define _SB1250_L2C_H - -#include "sb1250_defs.h" - -/* - * Level 2 Cache Tag register (Table 5-3) - */ - -#define S_L2C_TAG_MBZ 0 -#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ) - -#define S_L2C_TAG_INDEX 5 -#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX) -#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX) -#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX) - -#define S_L2C_TAG_TAG 17 -#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG) -#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG) -#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG) - -#define S_L2C_TAG_ECC 40 -#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC) -#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC) -#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC) - -#define S_L2C_TAG_WAY 46 -#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY) -#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY) -#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY) - -#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) -#define M_L2C_TAG_VALID _SB_MAKEMASK1(49) - -/* - * Format of level 2 cache management address (table 5-2) - */ - -#define S_L2C_MGMT_INDEX 5 -#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX) -#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX) -#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX) - -#define S_L2C_MGMT_QUADRANT 15 -#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2,S_L2C_MGMT_QUADRANT) -#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x,S_L2C_MGMT_QUADRANT) -#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x,S_L2C_MGMT_QUADRANT,M_L2C_MGMT_QUADRANT) - -#define S_L2C_MGMT_HALF 16 -#define M_L2C_MGMT_HALF _SB_MAKEMASK(1,S_L2C_MGMT_HALF) - -#define S_L2C_MGMT_WAY 17 -#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY) -#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY) -#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY) - -#define S_L2C_MGMT_TAG 21 -#define M_L2C_MGMT_TAG _SB_MAKEMASK(6,S_L2C_MGMT_TAG) -#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG) -#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG) - -#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) -#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) - -#define A_L2C_MGMT_TAG_BASE 0x00D0000000 - -#define L2C_ENTRIES_PER_WAY 4096 -#define L2C_NUM_WAYS 4 - - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* - * L2 Read Misc. register (A_L2_READ_MISC) - */ -#define S_L2C_MISC_NO_WAY 10 -#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4,S_L2C_MISC_NO_WAY) -#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x,S_L2C_MISC_NO_WAY) -#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x,S_L2C_MISC_NO_WAY,M_L2C_MISC_NO_WAY) - -#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9) -#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8) -#define M_L2C_MISC_SOFT_DISABLE_T _SB_MAKEMASK1(7) -#define M_L2C_MISC_SOFT_DISABLE_B _SB_MAKEMASK1(6) -#define M_L2C_MISC_SOFT_DISABLE_R _SB_MAKEMASK1(5) -#define M_L2C_MISC_SOFT_DISABLE_L _SB_MAKEMASK1(4) -#define M_L2C_MISC_SCACHE_DISABLE_T _SB_MAKEMASK1(3) -#define M_L2C_MISC_SCACHE_DISABLE_B _SB_MAKEMASK1(2) -#define M_L2C_MISC_SCACHE_DISABLE_R _SB_MAKEMASK1(1) -#define M_L2C_MISC_SCACHE_DISABLE_L _SB_MAKEMASK1(0) -#endif /* 1250 PASS3 || 112x PASS1 */ - - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_ldt.h b/include/asm-mips64/sibyte/sb1250_ldt.h deleted file mode 100644 index d8753885df1..00000000000 --- a/include/asm-mips64/sibyte/sb1250_ldt.h +++ /dev/null @@ -1,425 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * LDT constants File: sb1250_ldt.h - * - * This module contains constants and macros to describe - * the LDT interface on the SB1250. - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_LDT_H -#define _SB1250_LDT_H - -#include "sb1250_defs.h" - -#define K_LDT_VENDOR_SIBYTE 0x166D -#define K_LDT_DEVICE_SB1250 0x0002 - -/* - * LDT Interface Type 1 (bridge) configuration header - */ - -#define R_LDT_TYPE1_DEVICEID 0x0000 -#define R_LDT_TYPE1_CMDSTATUS 0x0004 -#define R_LDT_TYPE1_CLASSREV 0x0008 -#define R_LDT_TYPE1_DEVHDR 0x000C -#define R_LDT_TYPE1_BAR0 0x0010 /* not used */ -#define R_LDT_TYPE1_BAR1 0x0014 /* not used */ - -#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */ -#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */ -#define R_LDT_TYPE1_MEMLIMIT 0x0020 -#define R_LDT_TYPE1_PREFETCH 0x0024 -#define R_LDT_TYPE1_PREF_BASE 0x0028 -#define R_LDT_TYPE1_PREF_LIMIT 0x002C -#define R_LDT_TYPE1_IOLIMIT 0x0030 -#define R_LDT_TYPE1_CAPPTR 0x0034 -#define R_LDT_TYPE1_ROMADDR 0x0038 -#define R_LDT_TYPE1_BRCTL 0x003C -#define R_LDT_TYPE1_CMD 0x0040 -#define R_LDT_TYPE1_LINKCTRL 0x0044 -#define R_LDT_TYPE1_LINKFREQ 0x0048 -#define R_LDT_TYPE1_RESERVED1 0x004C -#define R_LDT_TYPE1_SRICMD 0x0050 -#define R_LDT_TYPE1_SRITXNUM 0x0054 -#define R_LDT_TYPE1_SRIRXNUM 0x0058 -#define R_LDT_TYPE1_ERRSTATUS 0x0068 -#define R_LDT_TYPE1_SRICTRL 0x006C -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define R_LDT_TYPE1_ADDSTATUS 0x0070 -#endif /* 1250 PASS2 || 112x PASS1 */ -#define R_LDT_TYPE1_TXBUFCNT 0x00C8 -#define R_LDT_TYPE1_EXPCRC 0x00DC -#define R_LDT_TYPE1_RXCRC 0x00F0 - - -/* - * LDT Device ID register - */ - -#define S_LDT_DEVICEID_VENDOR 0 -#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR) -#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR) -#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR) - -#define S_LDT_DEVICEID_DEVICEID 16 -#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID) -#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID) -#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID) - - -/* - * LDT Command Register (Table 8-13) - */ - -#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0) -#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1) -#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2) -#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3) -#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4) -#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5) -#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6) -#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7) -#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8) -#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9) - -/* - * LDT class and revision registers - */ - -#define S_LDT_CLASSREV_REV 0 -#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV) -#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV) -#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV) - -#define S_LDT_CLASSREV_CLASS 8 -#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS) -#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS) -#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS) - -#define K_LDT_REV 0x01 -#define K_LDT_CLASS 0x060000 - -/* - * Device Header (offset 0x0C) - */ - -#define S_LDT_DEVHDR_CLINESZ 0 -#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ) -#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ) -#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ) - -#define S_LDT_DEVHDR_LATTMR 8 -#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR) -#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR) -#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR) - -#define S_LDT_DEVHDR_HDRTYPE 16 -#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE) -#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE) -#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE) - -#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1 - -#define S_LDT_DEVHDR_BIST 24 -#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST) -#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST) -#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST) - - - -/* - * LDT Status Register (Table 8-14). Note that these constants - * assume you've read the command and status register - * together (32-bit read at offset 0x04) - * - * These bits also apply to the secondary status - * register (Table 8-15), offset 0x1C - */ - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3) -#endif /* 1250 PASS2 || 112x PASS1 */ -#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20) -#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21) -#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22) -#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23) -#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) - -#define S_LDT_STATUS_DEVSELTIMING 25 -#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING) -#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING) -#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING) - -#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) -#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) -#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29) -#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30) -#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31) - -/* - * Bridge Control Register (Table 8-16). Note that these - * constants assume you've read the register as a 32-bit - * read (offset 0x3C) - */ - -#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16) -#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17) -#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18) -#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19) -#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21) -#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22) -#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23) -#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24) -#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25) -#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26) -#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27) - -/* - * LDT Command Register (Table 8-17). Note that these constants - * assume you've read the command and status register together - * 32-bit read at offset 0x40 - */ - -#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16) -#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) - -#define S_LDT_CMD_CAPTYPE 29 -#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE) -#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE) -#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE) - -/* - * LDT link control register (Table 8-18), and (Table 8-19) - */ - -#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1) -#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2) -#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3) -#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4) -#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5) -#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6) -#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7) - -#define S_LDT_LINKCTRL_CRCERR 8 -#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR) -#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR) -#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR) - -#define S_LDT_LINKCTRL_MAXIN 16 -#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN) -#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN) -#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN) - -#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19) - -#define S_LDT_LINKCTRL_MAXOUT 20 -#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT) -#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT) -#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT) - -#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23) - -#define S_LDT_LINKCTRL_WIDTHIN 24 -#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN) -#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN) -#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN) - -#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27) - -#define S_LDT_LINKCTRL_WIDTHOUT 28 -#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT) -#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT) -#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT) - -#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) - -/* - * LDT Link frequency register (Table 8-20) offset 0x48 - */ - -#define S_LDT_LINKFREQ_FREQ 8 -#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ) -#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ) -#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ) - -#define K_LDT_LINKFREQ_200MHZ 0 -#define K_LDT_LINKFREQ_300MHZ 1 -#define K_LDT_LINKFREQ_400MHZ 2 -#define K_LDT_LINKFREQ_500MHZ 3 -#define K_LDT_LINKFREQ_600MHZ 4 -#define K_LDT_LINKFREQ_800MHZ 5 -#define K_LDT_LINKFREQ_1000MHZ 6 - -/* - * LDT SRI Command Register (Table 8-21). Note that these constants - * assume you've read the command and status register together - * 32-bit read at offset 0x50 - */ - -#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16) -#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17) -#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18) -#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */ -#endif /* up to 1250 PASS1 */ -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19) -#define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26) -#endif /* 1250 PASS2 || 112x PASS1 */ - - -#define S_LDT_SRICMD_RXMARGIN 20 -#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN) -#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN) -#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN) - -#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25) - -#define S_LDT_SRICMD_TXINITIALOFFSET 28 -#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET) -#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET) -#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET) - -#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) - -/* - * LDT Error control and status register (Table 8-22) (Table 8-23) - */ - -#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0) -#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1) -#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2) -#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3) -#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4) -#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5) -#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6) -#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7) -#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8) -#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9) -#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10) -#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11) -#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12) -#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13) -#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14) -#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15) -#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16) -#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17) - -#define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24) -#define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25) -#define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26) -#define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27) -#define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28) - -/* - * SRI Control register (Table 8-24, 8-25) Offset 0x6C - */ - -#define S_LDT_SRICTRL_NEEDRESP 0 -#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDRESP) -#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDRESP) -#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDRESP,M_LDT_SRICTRL_NEEDRESP) - -#define S_LDT_SRICTRL_NEEDNPREQ 2 -#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDNPREQ) -#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ) -#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ,M_LDT_SRICTRL_NEEDNPREQ) - -#define S_LDT_SRICTRL_NEEDPREQ 4 -#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDPREQ) -#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ) -#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ,M_LDT_SRICTRL_NEEDPREQ) - -#define S_LDT_SRICTRL_WANTRESP 8 -#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTRESP) -#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTRESP) -#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTRESP,M_LDT_SRICTRL_WANTRESP) - -#define S_LDT_SRICTRL_WANTNPREQ 10 -#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTNPREQ) -#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ) -#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ,M_LDT_SRICTRL_WANTNPREQ) - -#define S_LDT_SRICTRL_WANTPREQ 12 -#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTPREQ) -#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTPREQ) -#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTPREQ,M_LDT_SRICTRL_WANTPREQ) - -#define S_LDT_SRICTRL_BUFRELSPACE 16 -#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4,S_LDT_SRICTRL_BUFRELSPACE) -#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE) -#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE,M_LDT_SRICTRL_BUFRELSPACE) - -/* - * LDT SRI Transmit Buffer Count register (Table 8-26) - */ - -#define S_LDT_TXBUFCNT_PCMD 0 -#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PCMD) -#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PCMD) -#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PCMD,M_LDT_TXBUFCNT_PCMD) - -#define S_LDT_TXBUFCNT_PDATA 4 -#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PDATA) -#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PDATA) -#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PDATA,M_LDT_TXBUFCNT_PDATA) - -#define S_LDT_TXBUFCNT_NPCMD 8 -#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPCMD) -#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPCMD) -#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPCMD,M_LDT_TXBUFCNT_NPCMD) - -#define S_LDT_TXBUFCNT_NPDATA 12 -#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPDATA) -#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPDATA) -#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPDATA,M_LDT_TXBUFCNT_NPDATA) - -#define S_LDT_TXBUFCNT_RCMD 16 -#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RCMD) -#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RCMD) -#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RCMD,M_LDT_TXBUFCNT_RCMD) - -#define S_LDT_TXBUFCNT_RDATA 20 -#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RDATA) -#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RDATA) -#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RDATA,M_LDT_TXBUFCNT_RDATA) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* - * Additional Status Register - */ - -#define S_LDT_ADDSTATUS_TGTDONE 0 -#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8,S_LDT_ADDSTATUS_TGTDONE) -#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE) -#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE,M_LDT_ADDSTATUS_TGTDONE) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#endif - diff --git a/include/asm-mips64/sibyte/sb1250_mac.h b/include/asm-mips64/sibyte/sb1250_mac.h deleted file mode 100644 index 81f603f03a9..00000000000 --- a/include/asm-mips64/sibyte/sb1250_mac.h +++ /dev/null @@ -1,643 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * MAC constants and macros File: sb1250_mac.h - * - * This module contains constants and macros for the SB1250's - * ethernet controllers. - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_MAC_H -#define _SB1250_MAC_H - -#include "sb1250_defs.h" - -/* ********************************************************************* - * Ethernet MAC Registers - ********************************************************************* */ - -/* - * MAC Configuration Register (Table 9-13) - * Register: MAC_CFG_0 - * Register: MAC_CFG_1 - * Register: MAC_CFG_2 - */ - - -#define M_MAC_RESERVED0 _SB_MAKEMASK1(0) -#define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) -#define M_MAC_RETRY_EN _SB_MAKEMASK1(2) -#define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) -#define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) -#define M_MAC_BURST_EN _SB_MAKEMASK1(5) - -#define S_MAC_TX_PAUSE _SB_MAKE64(6) -#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) -#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) - -#define K_MAC_TX_PAUSE_CNT_512 0 -#define K_MAC_TX_PAUSE_CNT_1K 1 -#define K_MAC_TX_PAUSE_CNT_2K 2 -#define K_MAC_TX_PAUSE_CNT_4K 3 -#define K_MAC_TX_PAUSE_CNT_8K 4 -#define K_MAC_TX_PAUSE_CNT_16K 5 -#define K_MAC_TX_PAUSE_CNT_32K 6 -#define K_MAC_TX_PAUSE_CNT_64K 7 - -#define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) -#define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) -#define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) -#define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) -#define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) -#define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) -#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) -#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) - -#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) - -#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) -#define M_MAC_RESERVED2 _SB_MAKEMASK1(18) -#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) -#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) -#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) -#define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) -#define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) -#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) -#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) - -#define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) - -#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) -#define M_MAC_HDX_EN _SB_MAKEMASK1(33) - -#define S_MAC_SPEED_SEL _SB_MAKE64(34) -#define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) -#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) -#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) - -#define K_MAC_SPEED_SEL_10MBPS 0 -#define K_MAC_SPEED_SEL_100MBPS 1 -#define K_MAC_SPEED_SEL_1000MBPS 2 -#define K_MAC_SPEED_SEL_RESERVED 3 - -#define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) -#define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) -#define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) -#define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) - -#define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) -#define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) -#define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) -#define M_MAC_SS_EN _SB_MAKEMASK1(39) - -#define S_MAC_BYPASS_CFG _SB_MAKE64(40) -#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) -#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) -#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) - -#define K_MAC_BYPASS_GMII 0 -#define K_MAC_BYPASS_ENCODED 1 -#define K_MAC_BYPASS_SOP 2 -#define K_MAC_BYPASS_EOP 3 - -#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) -#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define S_MAC_BYPASS_IFG _SB_MAKE64(46) -#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) -#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) -#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) - -#define K_MAC_FC_CMD_DISABLED 0 -#define K_MAC_FC_CMD_ENABLED 1 -#define K_MAC_FC_CMD_ENAB_FALSECARR 2 - -#define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) -#define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) -#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) - -#define M_MAC_FC_SEL _SB_MAKEMASK1(54) - -#define S_MAC_FC_CMD _SB_MAKE64(55) -#define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) -#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) -#define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) - -#define S_MAC_RX_CH_SEL _SB_MAKE64(57) -#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) -#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) -#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) - - -/* - * MAC Enable Registers - * Register: MAC_ENABLE_0 - * Register: MAC_ENABLE_1 - * Register: MAC_ENABLE_2 - */ - -#define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) -#define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) -#define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) -#define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) - -#define M_MAC_PORT_RESET _SB_MAKEMASK1(8) - -#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) -#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) -#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) -#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) - -/* - * MAC DMA Control Register - * Register: MAC_TXD_CTL_0 - * Register: MAC_TXD_CTL_1 - * Register: MAC_TXD_CTL_2 - */ - -#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) -#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) -#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) -#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) - -#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) -#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) -#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) -#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) - -/* - * MAC Fifo Threshhold registers (Table 9-14) - * Register: MAC_THRSH_CFG_0 - * Register: MAC_THRSH_CFG_1 - * Register: MAC_THRSH_CFG_2 - */ - -#define S_MAC_TX_WR_THRSH _SB_MAKE64(0) -#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ -#endif /* up to 1250 PASS1 */ -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) -#endif /* 1250 PASS2 || 112x PASS1 */ -#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) -#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) - -#define S_MAC_TX_RD_THRSH _SB_MAKE64(8) -#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) -/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ -/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ -#endif /* up to 1250 PASS1 */ -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) -#endif /* 1250 PASS2 || 112x PASS1 */ -#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) -#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) - -#define S_MAC_TX_RL_THRSH _SB_MAKE64(16) -#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) -#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) -#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) - -#define S_MAC_RX_PL_THRSH _SB_MAKE64(24) -#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) -#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) -#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) - -#define S_MAC_RX_RD_THRSH _SB_MAKE64(32) -#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) -#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) -#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) - -#define S_MAC_RX_RL_THRSH _SB_MAKE64(40) -#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) -#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) -#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) -#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) -#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) -#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) -#endif /* 1250 PASS2 || 112x PASS1 */ - -/* - * MAC Frame Configuration Registers (Table 9-15) - * Register: MAC_FRAME_CFG_0 - * Register: MAC_FRAME_CFG_1 - * Register: MAC_FRAME_CFG_2 - */ - -/* XXXCGD: ??? Unused in pass2? */ -#define S_MAC_IFG_RX _SB_MAKE64(0) -#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) -#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) -#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_MAC_PRE_LEN _SB_MAKE64(0) -#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) -#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) -#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define S_MAC_IFG_TX _SB_MAKE64(6) -#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) -#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) -#define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) - -#define S_MAC_IFG_THRSH _SB_MAKE64(12) -#define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) -#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) -#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) - -#define S_MAC_BACKOFF_SEL _SB_MAKE64(18) -#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) -#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) -#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) - -#define S_MAC_LFSR_SEED _SB_MAKE64(22) -#define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) -#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) -#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) - -#define S_MAC_SLOT_SIZE _SB_MAKE64(30) -#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) -#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) -#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) - -#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) -#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) -#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) -#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) - -#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) -#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) -#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) -#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) - -/* - * These constants are used to configure the fields within the Frame - * Configuration Register. - */ - -#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ -#define K_MAC_IFG_RX_100 _SB_MAKE64(0) -#define K_MAC_IFG_RX_1000 _SB_MAKE64(0) - -#define K_MAC_IFG_TX_10 _SB_MAKE64(20) -#define K_MAC_IFG_TX_100 _SB_MAKE64(20) -#define K_MAC_IFG_TX_1000 _SB_MAKE64(8) - -#define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) -#define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) -#define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) - -#define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) -#define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) -#define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) - -#define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) -#define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) -#define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) - -#define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) -#define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) -#define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) - -#define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) -#define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) -#define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) - -#define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) -#define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) -#define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) - -#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) -#define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) -#define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) -#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) - -#define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) -#define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) -#define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) -#define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) - -/* - * MAC VLAN Tag Registers (Table 9-16) - * Register: MAC_VLANTAG_0 - * Register: MAC_VLANTAG_1 - * Register: MAC_VLANTAG_2 - */ - -#define S_MAC_VLAN_TAG _SB_MAKE64(0) -#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) -#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) -#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) -#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) -#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) -#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) - -#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) -#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) -#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) -#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) - -#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) -#endif /* 1250 PASS3 || 112x PASS1 */ - -/* - * MAC Status Registers (Table 9-17) - * Also used for the MAC Interrupt Mask Register (Table 9-18) - * Register: MAC_STATUS_0 - * Register: MAC_STATUS_1 - * Register: MAC_STATUS_2 - * Register: MAC_INT_MASK_0 - * Register: MAC_INT_MASK_1 - * Register: MAC_INT_MASK_2 - */ - -/* - * Use these constants to shift the appropriate channel - * into the CH0 position so the same tests can be used - * on each channel. - */ - -#define S_MAC_RX_CH0 _SB_MAKE64(0) -#define S_MAC_RX_CH1 _SB_MAKE64(8) -#define S_MAC_TX_CH0 _SB_MAKE64(16) -#define S_MAC_TX_CH1 _SB_MAKE64(24) - -#define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ -#define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ - -/* - * These are the same as RX channel 0. The idea here - * is that you'll use one of the "S_" things above - * and pass just the six bits to a DMA-channel-specific ISR - */ -#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) -#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) -#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) -#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) -#define M_MAC_INT_HWM _SB_MAKEMASK1(3) -#define M_MAC_INT_LWM _SB_MAKEMASK1(4) -#define M_MAC_INT_DSCR _SB_MAKEMASK1(5) -#define M_MAC_INT_ERR _SB_MAKEMASK1(6) -#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ -#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ - -/* - * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see - * also DMA_TX/DMA_RX in sb_regs.h). - */ -#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) - -#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) -#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) - - -#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) -#define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) -#define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) -#define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) -#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) -#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) -#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ -#endif /* 1250 PASS2 || 112x PASS1 */ - -#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) -#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) -#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) -#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) -#endif /* 1250 PASS3 || 112x PASS1 */ - -/* - * MAC Fifo Pointer Registers (Table 9-19) [Debug register] - * Register: MAC_FIFO_PTRS_0 - * Register: MAC_FIFO_PTRS_1 - * Register: MAC_FIFO_PTRS_2 - */ - -#define S_MAC_TX_WRPTR _SB_MAKE64(0) -#define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) -#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) -#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) - -#define S_MAC_TX_RDPTR _SB_MAKE64(8) -#define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) -#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) -#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) - -#define S_MAC_RX_WRPTR _SB_MAKE64(16) -#define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) -#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) -#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) - -#define S_MAC_RX_RDPTR _SB_MAKE64(24) -#define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) -#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) -#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) - -/* - * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] - * Register: MAC_EOPCNT_0 - * Register: MAC_EOPCNT_1 - * Register: MAC_EOPCNT_2 - */ - -#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) -#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) -#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) -#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) - -#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) -#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) -#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) -#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) - -/* - * MAC Recieve Address Filter Exact Match Registers (Table 9-21) - * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 - * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 - * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 - */ - -/* No bitfields */ - -/* - * MAC Receive Address Filter Mask Registers - * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 - * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 - * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 - */ - -/* No bitfields */ - -/* - * MAC Recieve Address Filter Hash Match Registers (Table 9-22) - * Registers: MAC_HASH0_0 through MAC_HASH7_0 - * Registers: MAC_HASH0_1 through MAC_HASH7_1 - * Registers: MAC_HASH0_2 through MAC_HASH7_2 - */ - -/* No bitfields */ - -/* - * MAC Transmit Source Address Registers (Table 9-23) - * Register: MAC_ETHERNET_ADDR_0 - * Register: MAC_ETHERNET_ADDR_1 - * Register: MAC_ETHERNET_ADDR_2 - */ - -/* No bitfields */ - -/* - * MAC Packet Type Configuration Register - * Register: MAC_TYPE_CFG_0 - * Register: MAC_TYPE_CFG_1 - * Register: MAC_TYPE_CFG_2 - */ - -#define S_TYPECFG_TYPESIZE _SB_MAKE64(16) - -#define S_TYPECFG_TYPE0 _SB_MAKE64(0) -#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) -#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) -#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) - -#define S_TYPECFG_TYPE1 _SB_MAKE64(0) -#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) -#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) -#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) - -#define S_TYPECFG_TYPE2 _SB_MAKE64(0) -#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) -#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) -#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) - -#define S_TYPECFG_TYPE3 _SB_MAKE64(0) -#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) -#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) -#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) - -/* - * MAC Receive Address Filter Control Registers (Table 9-24) - * Register: MAC_ADFILTER_CFG_0 - * Register: MAC_ADFILTER_CFG_1 - * Register: MAC_ADFILTER_CFG_2 - */ - -#define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) -#define M_MAC_UCAST_EN _SB_MAKEMASK1(1) -#define M_MAC_UCAST_INV _SB_MAKEMASK1(2) -#define M_MAC_MCAST_EN _SB_MAKEMASK1(3) -#define M_MAC_MCAST_INV _SB_MAKEMASK1(4) -#define M_MAC_BCAST_EN _SB_MAKEMASK1(5) -#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) -#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) -#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) -#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) -#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) -#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) -#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) - -#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) -#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) -#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) -#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) - -#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) -#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) - -#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) -#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) -#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) -#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) -#endif /* 1250 PASS3 || 112x PASS1 */ - -/* - * MAC Receive Channel Select Registers (Table 9-25) - */ - -/* no bitfields */ - -/* - * MAC MII Management Interface Registers (Table 9-26) - * Register: MAC_MDIO_0 - * Register: MAC_MDIO_1 - * Register: MAC_MDIO_2 - */ - -#define S_MAC_MDC 0 -#define S_MAC_MDIO_DIR 1 -#define S_MAC_MDIO_OUT 2 -#define S_MAC_GENC 3 -#define S_MAC_MDIO_IN 4 - -#define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) -#define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) -#define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) -#define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) -#define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) -#define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_mc.h b/include/asm-mips64/sibyte/sb1250_mc.h deleted file mode 100644 index 93a48334b87..00000000000 --- a/include/asm-mips64/sibyte/sb1250_mc.h +++ /dev/null @@ -1,548 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Memory Controller constants File: sb1250_mc.h - * - * This module contains constants and macros useful for - * programming the memory controller. - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_MC_H -#define _SB1250_MC_H - -#include "sb1250_defs.h" - -/* - * Memory Channel Config Register (table 6-14) - */ - -#define S_MC_RESERVED0 0 -#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) - -#define S_MC_CHANNEL_SEL 8 -#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) -#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) -#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) - -#define S_MC_BANK0_MAP 16 -#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) -#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) -#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) - -#define K_MC_BANK0_MAP_DEFAULT 0x00 -#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) - -#define S_MC_BANK1_MAP 20 -#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) -#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) -#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) - -#define K_MC_BANK1_MAP_DEFAULT 0x08 -#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) - -#define S_MC_BANK2_MAP 24 -#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) -#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) -#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) - -#define K_MC_BANK2_MAP_DEFAULT 0x09 -#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) - -#define S_MC_BANK3_MAP 28 -#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) -#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) -#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) - -#define K_MC_BANK3_MAP_DEFAULT 0x0C -#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) - -#define M_MC_RESERVED1 _SB_MAKEMASK(8,32) - -#define S_MC_QUEUE_SIZE 40 -#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) -#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) -#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) - -#define S_MC_AGE_LIMIT 44 -#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) -#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) -#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) - -#define S_MC_WR_LIMIT 48 -#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) -#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) -#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) -#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) - -#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) - -#define M_MC_RESERVED2 _SB_MAKEMASK(3,53) - -#define S_MC_CS_MODE 56 -#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) -#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) -#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) - -#define K_MC_CS_MODE_MSB_CS 0 -#define K_MC_CS_MODE_INTLV_CS 15 -#define K_MC_CS_MODE_MIXED_CS_10 12 -#define K_MC_CS_MODE_MIXED_CS_30 6 -#define K_MC_CS_MODE_MIXED_CS_32 3 - -#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) -#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) -#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10) -#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30) -#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32) - -#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) -#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) -#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) -#define M_MC_DEBUG _SB_MAKEMASK1(63) - -#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \ - V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \ - V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \ - M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT - - -/* - * Memory clock config register (Table 6-15) - * - * Note: this field has been updated to be consistent with the errata to 0.2 - */ - -#define S_MC_CLK_RATIO 0 -#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) -#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) -#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) - -#define K_MC_CLK_RATIO_2X 4 -#define K_MC_CLK_RATIO_25X 5 -#define K_MC_CLK_RATIO_3X 6 -#define K_MC_CLK_RATIO_35X 7 -#define K_MC_CLK_RATIO_4X 8 -#define K_MC_CLK_RATIO_45X 9 - -#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X) -#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) -#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) -#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) -#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) -#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) -#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X - -#define S_MC_REF_RATE 8 -#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) -#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) -#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) - -#define K_MC_REF_RATE_100MHz 0x62 -#define K_MC_REF_RATE_133MHz 0x81 -#define K_MC_REF_RATE_200MHz 0xC4 - -#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) -#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) -#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) -#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz - -#define S_MC_CLOCK_DRIVE 16 -#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) -#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) -#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) -#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) - -#define S_MC_DATA_DRIVE 20 -#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) -#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) -#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) - -#define S_MC_ADDR_DRIVE 24 -#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) -#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) -#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MC_REF_DISABLE _SB_MAKEMASK1(30) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) - -#define S_MC_DQI_SKEW 32 -#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) -#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) -#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) -#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) - -#define S_MC_DQO_SKEW 40 -#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) -#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) -#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) -#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) - -#define S_MC_ADDR_SKEW 48 -#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) -#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) -#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) - -#define S_MC_DLL_DEFAULT 56 -#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) -#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) -#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) -#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) - -#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ - V_MC_ADDR_SKEW_DEFAULT | \ - V_MC_DQO_SKEW_DEFAULT | \ - V_MC_DQI_SKEW_DEFAULT | \ - V_MC_ADDR_DRIVE_DEFAULT | \ - V_MC_DATA_DRIVE_DEFAULT | \ - V_MC_CLOCK_DRIVE_DEFAULT | \ - V_MC_REF_RATE_DEFAULT - - - -/* - * DRAM Command Register (Table 6-13) - */ - -#define S_MC_COMMAND 0 -#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) -#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) -#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) - -#define K_MC_COMMAND_EMRS 0 -#define K_MC_COMMAND_MRS 1 -#define K_MC_COMMAND_PRE 2 -#define K_MC_COMMAND_AR 3 -#define K_MC_COMMAND_SETRFSH 4 -#define K_MC_COMMAND_CLRRFSH 5 -#define K_MC_COMMAND_SETPWRDN 6 -#define K_MC_COMMAND_CLRPWRDN 7 - -#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) -#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) -#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) -#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) -#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) -#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) -#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) -#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) - -#define M_MC_CS0 _SB_MAKEMASK1(4) -#define M_MC_CS1 _SB_MAKEMASK1(5) -#define M_MC_CS2 _SB_MAKEMASK1(6) -#define M_MC_CS3 _SB_MAKEMASK1(7) - -/* - * DRAM Mode Register (Table 6-14) - */ - -#define S_MC_EMODE 0 -#define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) -#define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) -#define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) -#define V_MC_EMODE_DEFAULT V_MC_EMODE(0) - -#define S_MC_MODE 16 -#define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) -#define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) -#define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) -#define V_MC_MODE_DEFAULT V_MC_MODE(0x22) - -#define S_MC_DRAM_TYPE 32 -#define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) -#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) -#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) - -#define K_MC_DRAM_TYPE_JEDEC 0 -#define K_MC_DRAM_TYPE_FCRAM 1 -#define K_MC_DRAM_TYPE_SGRAM 2 - -#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) -#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) -#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) - -#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35) - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) -#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(38) -#endif /* 1250 PASS3 || 112x PASS1 */ - - - -/* - * SDRAM Timing Register (Table 6-15) - */ - -#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60) -#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61) -#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) - -#define S_MC_tFIFO 56 -#define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) -#define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) -#define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO) -#define K_MC_tFIFO_DEFAULT 1 -#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) - -#define S_MC_tRFC 52 -#define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) -#define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) -#define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC) -#define K_MC_tRFC_DEFAULT 12 -#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) - -#define S_MC_tCwCr 40 -#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) -#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) -#define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr) -#define K_MC_tCwCr_DEFAULT 4 -#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) - -#define S_MC_tRCr 28 -#define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) -#define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) -#define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr) -#define K_MC_tRCr_DEFAULT 9 -#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) - -#define S_MC_tRCw 24 -#define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) -#define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) -#define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw) -#define K_MC_tRCw_DEFAULT 10 -#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) - -#define S_MC_tRRD 20 -#define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) -#define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) -#define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD) -#define K_MC_tRRD_DEFAULT 2 -#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) - -#define S_MC_tRP 16 -#define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) -#define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) -#define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP) -#define K_MC_tRP_DEFAULT 4 -#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) - -#define S_MC_tCwD 8 -#define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) -#define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) -#define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD) -#define K_MC_tCwD_DEFAULT 1 -#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) - -#define M_tCrDh _SB_MAKEMASK1(7) -#define M_MC_tCrDh M_tCrDh - -#define S_MC_tCrD 4 -#define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) -#define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) -#define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD) -#define K_MC_tCrD_DEFAULT 2 -#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) - -#define S_MC_tRCD 0 -#define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) -#define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) -#define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD) -#define K_MC_tRCD_DEFAULT 3 -#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) - -#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ - V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ - V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ - V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ - V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ - V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ - V_MC_tRP(K_MC_tRP_DEFAULT) | \ - V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ - V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ - V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ - M_MC_r2rIDLE_TWOCYCLES - -/* - * Errata says these are not the default - * M_MC_w2rIDLE_TWOCYCLES | \ - * M_MC_r2wIDLE_TWOCYCLES | \ - */ - - -/* - * Chip Select Start Address Register (Table 6-17) - */ - -#define S_MC_CS0_START 0 -#define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) -#define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) -#define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) - -#define S_MC_CS1_START 16 -#define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) -#define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) -#define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) - -#define S_MC_CS2_START 32 -#define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) -#define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) -#define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) - -#define S_MC_CS3_START 48 -#define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) -#define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) -#define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) - -/* - * Chip Select End Address Register (Table 6-18) - */ - -#define S_MC_CS0_END 0 -#define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) -#define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) -#define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) - -#define S_MC_CS1_END 16 -#define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) -#define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) -#define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) - -#define S_MC_CS2_END 32 -#define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) -#define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) -#define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) - -#define S_MC_CS3_END 48 -#define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) -#define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) -#define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) - -/* - * Chip Select Interleave Register (Table 6-19) - */ - -#define S_MC_INTLV_RESERVED 0 -#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) - -#define S_MC_INTERLEAVE 7 -#define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) -#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) - -#define S_MC_INTLV_MBZ 25 -#define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) - -/* - * Row Address Bits Register (Table 6-20) - */ - -#define S_MC_RAS_RESERVED 0 -#define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) - -#define S_MC_RAS_SELECT 12 -#define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) -#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) - -#define S_MC_RAS_MBZ 37 -#define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) - - -/* - * Column Address Bits Register (Table 6-21) - */ - -#define S_MC_CAS_RESERVED 0 -#define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) - -#define S_MC_CAS_SELECT 5 -#define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) -#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) - -#define S_MC_CAS_MBZ 23 -#define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) - - -/* - * Bank Address Address Bits Register (Table 6-22) - */ - -#define S_MC_BA_RESERVED 0 -#define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) - -#define S_MC_BA_SELECT 5 -#define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) -#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) - -#define S_MC_BA_MBZ 25 -#define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) - -/* - * Chip Select Attribute Register (Table 6-23) - */ - -#define K_MC_CS_ATTR_CLOSED 0 -#define K_MC_CS_ATTR_CASCHECK 1 -#define K_MC_CS_ATTR_HINT 2 -#define K_MC_CS_ATTR_OPEN 3 - -#define S_MC_CS0_PAGE 0 -#define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) -#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) -#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) - -#define S_MC_CS1_PAGE 16 -#define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) -#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) -#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) - -#define S_MC_CS2_PAGE 32 -#define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) -#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) -#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) - -#define S_MC_CS3_PAGE 48 -#define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) -#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) -#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) - -/* - * ECC Test ECC Register (Table 6-25) - */ - -#define S_MC_ECC_INVERT 0 -#define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) - - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_regs.h b/include/asm-mips64/sibyte/sb1250_regs.h deleted file mode 100644 index 5d496c6faba..00000000000 --- a/include/asm-mips64/sibyte/sb1250_regs.h +++ /dev/null @@ -1,836 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Register Definitions File: sb1250_regs.h - * - * This module contains the addresses of the on-chip peripherals - * on the SB1250. - * - * SB1250 specification level: 01/02/2002 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_REGS_H -#define _SB1250_REGS_H - -#include "sb1250_defs.h" - - -/* ********************************************************************* - * Some general notes: - * - * For the most part, when there is more than one peripheral - * of the same type on the SOC, the constants below will be - * offsets from the base of each peripheral. For example, - * the MAC registers are described as offsets from the first - * MAC register, and there will be a MAC_REGISTER() macro - * to calculate the base address of a given MAC. - * - * The information in this file is based on the SB1250 SOC - * manual version 0.2, July 2000. - ********************************************************************* */ - - -/* ********************************************************************* - * Memory Controller Registers - ********************************************************************* */ - -/* - * XXX: can't remove MC base 0 if 112x, since it's used by other macros, - * since there is one reg there (but it could get its addr/offset constant). - */ -#define A_MC_BASE_0 0x0010051000 -#define A_MC_BASE_1 0x0010052000 -#define MC_REGISTER_SPACING 0x1000 - -#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) -#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) - -#define R_MC_CONFIG 0x0000000100 -#define R_MC_DRAMCMD 0x0000000120 -#define R_MC_DRAMMODE 0x0000000140 -#define R_MC_TIMING1 0x0000000160 -#define R_MC_TIMING2 0x0000000180 -#define R_MC_CS_START 0x00000001A0 -#define R_MC_CS_END 0x00000001C0 -#define R_MC_CS_INTERLEAVE 0x00000001E0 -#define S_MC_CS_STARTEND 16 - -#define R_MC_CSX_BASE 0x0000000200 -#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ -#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ -#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ -#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ - -#define R_MC_CS0_ROW 0x0000000200 -#define R_MC_CS0_COL 0x0000000220 -#define R_MC_CS0_BA 0x0000000240 -#define R_MC_CS1_ROW 0x0000000260 -#define R_MC_CS1_COL 0x0000000280 -#define R_MC_CS1_BA 0x00000002A0 -#define R_MC_CS2_ROW 0x00000002C0 -#define R_MC_CS2_COL 0x00000002E0 -#define R_MC_CS2_BA 0x0000000300 -#define R_MC_CS3_ROW 0x0000000320 -#define R_MC_CS3_COL 0x0000000340 -#define R_MC_CS3_BA 0x0000000360 -#define R_MC_CS_ATTR 0x0000000380 -#define R_MC_TEST_DATA 0x0000000400 -#define R_MC_TEST_ECC 0x0000000420 -#define R_MC_MCLK_CFG 0x0000000500 - -/* ********************************************************************* - * L2 Cache Control Registers - ********************************************************************* */ - -#define A_L2_READ_TAG 0x0010040018 -#define A_L2_ECC_TAG 0x0010040038 -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_L2_READ_MISC 0x0010040058 -#endif /* 1250 PASS3 || 112x PASS1 */ -#define A_L2_WAY_DISABLE 0x0010041000 -#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) -#define A_L2_MGMT_TAG_BASE 0x00D0000000 - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_L2_CACHE_DISABLE 0x0010042000 -#define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) -#define A_L2_MISC_CONFIG 0x0010043000 -#endif /* 1250 PASS2 || 112x PASS1 */ - -/* Backward-compatibility definitions. */ -/* XXX: discourage people from using these constants. */ -#define A_L2_READ_ADDRESS A_L2_READ_TAG -#define A_L2_EEC_ADDRESS A_L2_ECC_TAG - - -/* ********************************************************************* - * PCI Interface Registers - ********************************************************************* */ - -#define A_PCI_TYPE00_HEADER 0x00DE000000 -#define A_PCI_TYPE01_HEADER 0x00DE000800 - - -/* ********************************************************************* - * Ethernet DMA and MACs - ********************************************************************* */ - -#define A_MAC_BASE_0 0x0010064000 -#define A_MAC_BASE_1 0x0010065000 -#if SIBYTE_HDR_FEATURE_CHIP(1250) -#define A_MAC_BASE_2 0x0010066000 -#endif /* 1250 */ - -#define MAC_SPACING 0x1000 -#define MAC_DMA_TXRX_SPACING 0x0400 -#define MAC_DMA_CHANNEL_SPACING 0x0100 -#define DMA_RX 0 -#define DMA_TX 1 -#define MAC_NUM_DMACHAN 2 /* channels per direction */ - -/* XXX: not correct; depends on SOC type. */ -#define MAC_NUM_PORTS 3 - -#define A_MAC_CHANNEL_BASE(macnum) \ - (A_MAC_BASE_0 + \ - MAC_SPACING*(macnum)) - -#define A_MAC_REGISTER(macnum,reg) \ - (A_MAC_BASE_0 + \ - MAC_SPACING*(macnum) + (reg)) - - -#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ - -#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ - ((A_MAC_CHANNEL_BASE(macnum)) + \ - R_MAC_DMA_CHANNELS + \ - (MAC_DMA_TXRX_SPACING*(txrx)) + \ - (MAC_DMA_CHANNEL_SPACING*(chan))) - -#define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ - (R_MAC_DMA_CHANNELS + \ - (MAC_DMA_TXRX_SPACING*(txrx)) + \ - (MAC_DMA_CHANNEL_SPACING*(chan))) - -#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ - (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ - (reg)) - -#define R_MAC_DMA_REGISTER(txrx,chan,reg) \ - (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ - (reg)) - -/* - * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE - */ - -#define R_MAC_DMA_CONFIG0 0x00000000 -#define R_MAC_DMA_CONFIG1 0x00000008 -#define R_MAC_DMA_DSCR_BASE 0x00000010 -#define R_MAC_DMA_DSCR_CNT 0x00000018 -#define R_MAC_DMA_CUR_DSCRA 0x00000020 -#define R_MAC_DMA_CUR_DSCRB 0x00000028 -#define R_MAC_DMA_CUR_DSCRADDR 0x00000030 -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ -#endif /* 1250 PASS3 || 112x PASS1 */ - -/* - * RMON Counters - */ - -#define R_MAC_RMON_TX_BYTES 0x00000000 -#define R_MAC_RMON_COLLISIONS 0x00000008 -#define R_MAC_RMON_LATE_COL 0x00000010 -#define R_MAC_RMON_EX_COL 0x00000018 -#define R_MAC_RMON_FCS_ERROR 0x00000020 -#define R_MAC_RMON_TX_ABORT 0x00000028 -/* Counter #6 (0x30) now reserved */ -#define R_MAC_RMON_TX_BAD 0x00000038 -#define R_MAC_RMON_TX_GOOD 0x00000040 -#define R_MAC_RMON_TX_RUNT 0x00000048 -#define R_MAC_RMON_TX_OVERSIZE 0x00000050 -#define R_MAC_RMON_RX_BYTES 0x00000080 -#define R_MAC_RMON_RX_MCAST 0x00000088 -#define R_MAC_RMON_RX_BCAST 0x00000090 -#define R_MAC_RMON_RX_BAD 0x00000098 -#define R_MAC_RMON_RX_GOOD 0x000000A0 -#define R_MAC_RMON_RX_RUNT 0x000000A8 -#define R_MAC_RMON_RX_OVERSIZE 0x000000B0 -#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 -#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 -#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 -#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 - -/* Updated to spec 0.2 */ -#define R_MAC_CFG 0x00000100 -#define R_MAC_THRSH_CFG 0x00000108 -#define R_MAC_VLANTAG 0x00000110 -#define R_MAC_FRAMECFG 0x00000118 -#define R_MAC_EOPCNT 0x00000120 -#define R_MAC_FIFO_PTRS 0x00000130 -#define R_MAC_ADFILTER_CFG 0x00000200 -#define R_MAC_ETHERNET_ADDR 0x00000208 -#define R_MAC_PKT_TYPE 0x00000210 -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define R_MAC_ADMASK0 0x00000218 -#define R_MAC_ADMASK1 0x00000220 -#endif /* 1250 PASS3 || 112x PASS1 */ -#define R_MAC_HASH_BASE 0x00000240 -#define R_MAC_ADDR_BASE 0x00000280 -#define R_MAC_CHLO0_BASE 0x00000300 -#define R_MAC_CHUP0_BASE 0x00000320 -#define R_MAC_ENABLE 0x00000400 -#define R_MAC_STATUS 0x00000408 -#define R_MAC_INT_MASK 0x00000410 -#define R_MAC_TXD_CTL 0x00000420 -#define R_MAC_MDIO 0x00000428 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define R_MAC_STATUS1 0x00000430 -#endif /* 1250 PASS2 || 112x PASS1 */ -#define R_MAC_DEBUG_STATUS 0x00000448 - -#define MAC_HASH_COUNT 8 -#define MAC_ADDR_COUNT 8 -#define MAC_CHMAP_COUNT 4 - - -/* ********************************************************************* - * DUART Registers - ********************************************************************* */ - - -#define R_DUART_NUM_PORTS 2 - -#define A_DUART 0x0010060000 - -#define A_DUART_REG(r) - -#define DUART_CHANREG_SPACING 0x100 -#define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) -#define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) - -#define R_DUART_MODE_REG_1 0x100 -#define R_DUART_MODE_REG_2 0x110 -#define R_DUART_STATUS 0x120 -#define R_DUART_CLK_SEL 0x130 -#define R_DUART_CMD 0x150 -#define R_DUART_RX_HOLD 0x160 -#define R_DUART_TX_HOLD 0x170 - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define R_DUART_FULL_CTL 0x140 -#define R_DUART_OPCR_X 0x180 -#define R_DUART_AUXCTL_X 0x190 -#endif /* 1250 PASS2 || 112x PASS1 */ - - -/* - * The IMR and ISR can't be addressed with A_DUART_CHANREG, - * so use this macro instead. - */ - -#define R_DUART_AUX_CTRL 0x310 -#define R_DUART_ISR_A 0x320 -#define R_DUART_IMR_A 0x330 -#define R_DUART_ISR_B 0x340 -#define R_DUART_IMR_B 0x350 -#define R_DUART_OUT_PORT 0x360 -#define R_DUART_OPCR 0x370 - -#define R_DUART_SET_OPR 0x3B0 -#define R_DUART_CLEAR_OPR 0x3C0 - -#define DUART_IMRISR_SPACING 0x20 - -#define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) -#define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) - -#define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) -#define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) - - - - -/* - * These constants are the absolute addresses. - */ - -#define A_DUART_MODE_REG_1_A 0x0010060100 -#define A_DUART_MODE_REG_2_A 0x0010060110 -#define A_DUART_STATUS_A 0x0010060120 -#define A_DUART_CLK_SEL_A 0x0010060130 -#define A_DUART_CMD_A 0x0010060150 -#define A_DUART_RX_HOLD_A 0x0010060160 -#define A_DUART_TX_HOLD_A 0x0010060170 - -#define A_DUART_MODE_REG_1_B 0x0010060200 -#define A_DUART_MODE_REG_2_B 0x0010060210 -#define A_DUART_STATUS_B 0x0010060220 -#define A_DUART_CLK_SEL_B 0x0010060230 -#define A_DUART_CMD_B 0x0010060250 -#define A_DUART_RX_HOLD_B 0x0010060260 -#define A_DUART_TX_HOLD_B 0x0010060270 - -#define A_DUART_INPORT_CHNG 0x0010060300 -#define A_DUART_AUX_CTRL 0x0010060310 -#define A_DUART_ISR_A 0x0010060320 -#define A_DUART_IMR_A 0x0010060330 -#define A_DUART_ISR_B 0x0010060340 -#define A_DUART_IMR_B 0x0010060350 -#define A_DUART_OUT_PORT 0x0010060360 -#define A_DUART_OPCR 0x0010060370 -#define A_DUART_IN_PORT 0x0010060380 -#define A_DUART_ISR 0x0010060390 -#define A_DUART_IMR 0x00100603A0 -#define A_DUART_SET_OPR 0x00100603B0 -#define A_DUART_CLEAR_OPR 0x00100603C0 -#define A_DUART_INPORT_CHNG_A 0x00100603D0 -#define A_DUART_INPORT_CHNG_B 0x00100603E0 - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_DUART_FULL_CTL_A 0x0010060140 -#define A_DUART_FULL_CTL_B 0x0010060240 - -#define A_DUART_OPCR_A 0x0010060180 -#define A_DUART_OPCR_B 0x0010060280 - -#define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 -#endif /* 1250 PASS2 || 112x PASS1 */ - - -/* ********************************************************************* - * Synchronous Serial Registers - ********************************************************************* */ - - -#define A_SER_BASE_0 0x0010060400 -#define A_SER_BASE_1 0x0010060800 -#define SER_SPACING 0x400 - -#define SER_DMA_TXRX_SPACING 0x80 - -#define SER_NUM_PORTS 2 - -#define A_SER_CHANNEL_BASE(sernum) \ - (A_SER_BASE_0 + \ - SER_SPACING*(sernum)) - -#define A_SER_REGISTER(sernum,reg) \ - (A_SER_BASE_0 + \ - SER_SPACING*(sernum) + (reg)) - - -#define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ - -#define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ - ((A_SER_CHANNEL_BASE(sernum)) + \ - R_SER_DMA_CHANNELS + \ - (SER_DMA_TXRX_SPACING*(txrx))) - -#define A_SER_DMA_REGISTER(sernum,txrx,reg) \ - (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ - (reg)) - - -/* - * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE - */ - -#define R_SER_DMA_CONFIG0 0x00000000 -#define R_SER_DMA_CONFIG1 0x00000008 -#define R_SER_DMA_DSCR_BASE 0x00000010 -#define R_SER_DMA_DSCR_CNT 0x00000018 -#define R_SER_DMA_CUR_DSCRA 0x00000020 -#define R_SER_DMA_CUR_DSCRB 0x00000028 -#define R_SER_DMA_CUR_DSCRADDR 0x00000030 - -#define R_SER_DMA_CONFIG0_RX 0x00000000 -#define R_SER_DMA_CONFIG1_RX 0x00000008 -#define R_SER_DMA_DSCR_BASE_RX 0x00000010 -#define R_SER_DMA_DSCR_COUNT_RX 0x00000018 -#define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 -#define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 -#define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 - -#define R_SER_DMA_CONFIG0_TX 0x00000080 -#define R_SER_DMA_CONFIG1_TX 0x00000088 -#define R_SER_DMA_DSCR_BASE_TX 0x00000090 -#define R_SER_DMA_DSCR_COUNT_TX 0x00000098 -#define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 -#define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 -#define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 - -#define R_SER_MODE 0x00000100 -#define R_SER_MINFRM_SZ 0x00000108 -#define R_SER_MAXFRM_SZ 0x00000110 -#define R_SER_ADDR 0x00000118 -#define R_SER_USR0_ADDR 0x00000120 -#define R_SER_USR1_ADDR 0x00000128 -#define R_SER_USR2_ADDR 0x00000130 -#define R_SER_USR3_ADDR 0x00000138 -#define R_SER_CMD 0x00000140 -#define R_SER_TX_RD_THRSH 0x00000160 -#define R_SER_TX_WR_THRSH 0x00000168 -#define R_SER_RX_RD_THRSH 0x00000170 -#define R_SER_LINE_MODE 0x00000178 -#define R_SER_DMA_ENABLE 0x00000180 -#define R_SER_INT_MASK 0x00000190 -#define R_SER_STATUS 0x00000188 -#define R_SER_STATUS_DEBUG 0x000001A8 -#define R_SER_RX_TABLE_BASE 0x00000200 -#define SER_RX_TABLE_COUNT 16 -#define R_SER_TX_TABLE_BASE 0x00000300 -#define SER_TX_TABLE_COUNT 16 - -/* RMON Counters */ -#define R_SER_RMON_TX_BYTE_LO 0x000001C0 -#define R_SER_RMON_TX_BYTE_HI 0x000001C8 -#define R_SER_RMON_RX_BYTE_LO 0x000001D0 -#define R_SER_RMON_RX_BYTE_HI 0x000001D8 -#define R_SER_RMON_TX_UNDERRUN 0x000001E0 -#define R_SER_RMON_RX_OVERFLOW 0x000001E8 -#define R_SER_RMON_RX_ERRORS 0x000001F0 -#define R_SER_RMON_RX_BADADDR 0x000001F8 - -/* ********************************************************************* - * Generic Bus Registers - ********************************************************************* */ - -#define IO_EXT_CFG_COUNT 8 - -#define A_IO_EXT_BASE 0x0010061000 -#define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) - -#define A_IO_EXT_CFG_BASE 0x0010061000 -#define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 -#define A_IO_EXT_START_ADDR_BASE 0x0010061200 -#define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 -#define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 - -#define IO_EXT_REGISTER_SPACING 8 -#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) -#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) - -#define R_IO_EXT_CFG 0x0000 -#define R_IO_EXT_MULT_SIZE 0x0100 -#define R_IO_EXT_START_ADDR 0x0200 -#define R_IO_EXT_TIME_CFG0 0x0600 -#define R_IO_EXT_TIME_CFG1 0x0700 - - -#define A_IO_INTERRUPT_STATUS 0x0010061A00 -#define A_IO_INTERRUPT_DATA0 0x0010061A10 -#define A_IO_INTERRUPT_DATA1 0x0010061A18 -#define A_IO_INTERRUPT_DATA2 0x0010061A20 -#define A_IO_INTERRUPT_DATA3 0x0010061A28 -#define A_IO_INTERRUPT_ADDR0 0x0010061A30 -#define A_IO_INTERRUPT_ADDR1 0x0010061A40 -#define A_IO_INTERRUPT_PARITY 0x0010061A50 -#define A_IO_PCMCIA_CFG 0x0010061A60 -#define A_IO_PCMCIA_STATUS 0x0010061A70 -#define A_IO_DRIVE_0 0x0010061300 -#define A_IO_DRIVE_1 0x0010061308 -#define A_IO_DRIVE_2 0x0010061310 -#define A_IO_DRIVE_3 0x0010061318 -#define A_IO_DRIVE_BASE A_IO_DRIVE_0 -#define IO_DRIVE_REGISTER_SPACING 8 -#define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) -#define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) - -#define R_IO_INTERRUPT_STATUS 0x0A00 -#define R_IO_INTERRUPT_DATA0 0x0A10 -#define R_IO_INTERRUPT_DATA1 0x0A18 -#define R_IO_INTERRUPT_DATA2 0x0A20 -#define R_IO_INTERRUPT_DATA3 0x0A28 -#define R_IO_INTERRUPT_ADDR0 0x0A30 -#define R_IO_INTERRUPT_ADDR1 0x0A40 -#define R_IO_INTERRUPT_PARITY 0x0A50 -#define R_IO_PCMCIA_CFG 0x0A60 -#define R_IO_PCMCIA_STATUS 0x0A70 - -/* ********************************************************************* - * GPIO Registers - ********************************************************************* */ - -#define A_GPIO_CLR_EDGE 0x0010061A80 -#define A_GPIO_INT_TYPE 0x0010061A88 -#define A_GPIO_INPUT_INVERT 0x0010061A90 -#define A_GPIO_GLITCH 0x0010061A98 -#define A_GPIO_READ 0x0010061AA0 -#define A_GPIO_DIRECTION 0x0010061AA8 -#define A_GPIO_PIN_CLR 0x0010061AB0 -#define A_GPIO_PIN_SET 0x0010061AB8 - -#define A_GPIO_BASE 0x0010061A80 - -#define R_GPIO_CLR_EDGE 0x00 -#define R_GPIO_INT_TYPE 0x08 -#define R_GPIO_INPUT_INVERT 0x10 -#define R_GPIO_GLITCH 0x18 -#define R_GPIO_READ 0x20 -#define R_GPIO_DIRECTION 0x28 -#define R_GPIO_PIN_CLR 0x30 -#define R_GPIO_PIN_SET 0x38 - -/* ********************************************************************* - * SMBus Registers - ********************************************************************* */ - -#define A_SMB_XTRA_0 0x0010060000 -#define A_SMB_XTRA_1 0x0010060008 -#define A_SMB_FREQ_0 0x0010060010 -#define A_SMB_FREQ_1 0x0010060018 -#define A_SMB_STATUS_0 0x0010060020 -#define A_SMB_STATUS_1 0x0010060028 -#define A_SMB_CMD_0 0x0010060030 -#define A_SMB_CMD_1 0x0010060038 -#define A_SMB_START_0 0x0010060040 -#define A_SMB_START_1 0x0010060048 -#define A_SMB_DATA_0 0x0010060050 -#define A_SMB_DATA_1 0x0010060058 -#define A_SMB_CONTROL_0 0x0010060060 -#define A_SMB_CONTROL_1 0x0010060068 -#define A_SMB_PEC_0 0x0010060070 -#define A_SMB_PEC_1 0x0010060078 - -#define A_SMB_0 0x0010060000 -#define A_SMB_1 0x0010060008 -#define SMB_REGISTER_SPACING 0x8 -#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) -#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) - -#define R_SMB_XTRA 0x0000000000 -#define R_SMB_FREQ 0x0000000010 -#define R_SMB_STATUS 0x0000000020 -#define R_SMB_CMD 0x0000000030 -#define R_SMB_START 0x0000000040 -#define R_SMB_DATA 0x0000000050 -#define R_SMB_CONTROL 0x0000000060 -#define R_SMB_PEC 0x0000000070 - -/* ********************************************************************* - * Timer Registers - ********************************************************************* */ - -/* - * Watchdog timers - */ - -#define A_SCD_WDOG_0 0x0010020050 -#define A_SCD_WDOG_1 0x0010020150 -#define SCD_WDOG_SPACING 0x100 -#define SCD_NUM_WDOGS 2 -#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) -#define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) - -#define R_SCD_WDOG_INIT 0x0000000000 -#define R_SCD_WDOG_CNT 0x0000000008 -#define R_SCD_WDOG_CFG 0x0000000010 - -#define A_SCD_WDOG_INIT_0 0x0010020050 -#define A_SCD_WDOG_CNT_0 0x0010020058 -#define A_SCD_WDOG_CFG_0 0x0010020060 - -#define A_SCD_WDOG_INIT_1 0x0010020150 -#define A_SCD_WDOG_CNT_1 0x0010020158 -#define A_SCD_WDOG_CFG_1 0x0010020160 - -/* - * Generic timers - */ - -#define A_SCD_TIMER_0 0x0010020070 -#define A_SCD_TIMER_1 0x0010020078 -#define A_SCD_TIMER_2 0x0010020170 -#define A_SCD_TIMER_3 0x0010020178 -#define SCD_NUM_TIMERS 4 -#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) -#define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) - -#define R_SCD_TIMER_INIT 0x0000000000 -#define R_SCD_TIMER_CNT 0x0000000010 -#define R_SCD_TIMER_CFG 0x0000000020 - -#define A_SCD_TIMER_INIT_0 0x0010020070 -#define A_SCD_TIMER_CNT_0 0x0010020080 -#define A_SCD_TIMER_CFG_0 0x0010020090 - -#define A_SCD_TIMER_INIT_1 0x0010020078 -#define A_SCD_TIMER_CNT_1 0x0010020088 -#define A_SCD_TIMER_CFG_1 0x0010020098 - -#define A_SCD_TIMER_INIT_2 0x0010020170 -#define A_SCD_TIMER_CNT_2 0x0010020180 -#define A_SCD_TIMER_CFG_2 0x0010020190 - -#define A_SCD_TIMER_INIT_3 0x0010020178 -#define A_SCD_TIMER_CNT_3 0x0010020188 -#define A_SCD_TIMER_CFG_3 0x0010020198 - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_SCD_SCRATCH 0x0010020C10 - -#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 -#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 -#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 -#endif /* 1250 PASS2 || 112x PASS1 */ - - -/* ********************************************************************* - * System Control Registers - ********************************************************************* */ - -#define A_SCD_SYSTEM_REVISION 0x0010020000 -#define A_SCD_SYSTEM_CFG 0x0010020008 -#define A_SCD_SYSTEM_MANUF 0x0010038000 - -/* ********************************************************************* - * System Address Trap Registers - ********************************************************************* */ - -#define A_ADDR_TRAP_INDEX 0x00100200B0 -#define A_ADDR_TRAP_REG 0x00100200B8 -#define A_ADDR_TRAP_UP_0 0x0010020400 -#define A_ADDR_TRAP_UP_1 0x0010020408 -#define A_ADDR_TRAP_UP_2 0x0010020410 -#define A_ADDR_TRAP_UP_3 0x0010020418 -#define A_ADDR_TRAP_DOWN_0 0x0010020420 -#define A_ADDR_TRAP_DOWN_1 0x0010020428 -#define A_ADDR_TRAP_DOWN_2 0x0010020430 -#define A_ADDR_TRAP_DOWN_3 0x0010020438 -#define A_ADDR_TRAP_CFG_0 0x0010020440 -#define A_ADDR_TRAP_CFG_1 0x0010020448 -#define A_ADDR_TRAP_CFG_2 0x0010020450 -#define A_ADDR_TRAP_CFG_3 0x0010020458 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_ADDR_TRAP_REG_DEBUG 0x0010020460 -#endif /* 1250 PASS2 || 112x PASS1 */ - - -/* ********************************************************************* - * System Interrupt Mapper Registers - ********************************************************************* */ - -#define A_IMR_CPU0_BASE 0x0010020000 -#define A_IMR_CPU1_BASE 0x0010022000 -#define IMR_REGISTER_SPACING 0x2000 -#define IMR_REGISTER_SPACING_SHIFT 13 - -#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) -#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) - -#define R_IMR_INTERRUPT_DIAG 0x0010 -#define R_IMR_INTERRUPT_MASK 0x0028 -#define R_IMR_INTERRUPT_TRACE 0x0038 -#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 -#define R_IMR_LDT_INTERRUPT_SET 0x0048 -#define R_IMR_LDT_INTERRUPT 0x0018 -#define R_IMR_LDT_INTERRUPT_CLR 0x0020 -#define R_IMR_MAILBOX_CPU 0x00c0 -#define R_IMR_ALIAS_MAILBOX_CPU 0x1000 -#define R_IMR_MAILBOX_SET_CPU 0x00C8 -#define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 -#define R_IMR_MAILBOX_CLR_CPU 0x00D0 -#define R_IMR_INTERRUPT_STATUS_BASE 0x0100 -#define R_IMR_INTERRUPT_STATUS_COUNT 7 -#define R_IMR_INTERRUPT_MAP_BASE 0x0200 -#define R_IMR_INTERRUPT_MAP_COUNT 64 - -/* ********************************************************************* - * System Performance Counter Registers - ********************************************************************* */ - -#define A_SCD_PERF_CNT_CFG 0x00100204C0 -#define A_SCD_PERF_CNT_0 0x00100204D0 -#define A_SCD_PERF_CNT_1 0x00100204D8 -#define A_SCD_PERF_CNT_2 0x00100204E0 -#define A_SCD_PERF_CNT_3 0x00100204E8 - -/* ********************************************************************* - * System Bus Watcher Registers - ********************************************************************* */ - -#define A_SCD_BUS_ERR_STATUS 0x0010020880 -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 -#endif /* 1250 PASS2 || 112x PASS1 */ -#define A_BUS_ERR_DATA_0 0x00100208A0 -#define A_BUS_ERR_DATA_1 0x00100208A8 -#define A_BUS_ERR_DATA_2 0x00100208B0 -#define A_BUS_ERR_DATA_3 0x00100208B8 -#define A_BUS_L2_ERRORS 0x00100208C0 -#define A_BUS_MEM_IO_ERRORS 0x00100208C8 - -/* ********************************************************************* - * System Debug Controller Registers - ********************************************************************* */ - -#define A_SCD_JTAG_BASE 0x0010000000 - -/* ********************************************************************* - * System Trace Buffer Registers - ********************************************************************* */ - -#define A_SCD_TRACE_CFG 0x0010020A00 -#define A_SCD_TRACE_READ 0x0010020A08 -#define A_SCD_TRACE_EVENT_0 0x0010020A20 -#define A_SCD_TRACE_EVENT_1 0x0010020A28 -#define A_SCD_TRACE_EVENT_2 0x0010020A30 -#define A_SCD_TRACE_EVENT_3 0x0010020A38 -#define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 -#define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 -#define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 -#define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 -#define A_SCD_TRACE_EVENT_4 0x0010020A60 -#define A_SCD_TRACE_EVENT_5 0x0010020A68 -#define A_SCD_TRACE_EVENT_6 0x0010020A70 -#define A_SCD_TRACE_EVENT_7 0x0010020A78 -#define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 -#define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 -#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 -#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 - -/* ********************************************************************* - * System Generic DMA Registers - ********************************************************************* */ - -#define A_DM_0 0x0010020B00 -#define A_DM_1 0x0010020B20 -#define A_DM_2 0x0010020B40 -#define A_DM_3 0x0010020B60 -#define DM_REGISTER_SPACING 0x20 -#define DM_NUM_CHANNELS 4 -#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) -#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) - -#define R_DM_DSCR_BASE 0x0000000000 -#define R_DM_DSCR_COUNT 0x0000000008 -#define R_DM_CUR_DSCR_ADDR 0x0000000010 -#define R_DM_DSCR_BASE_DEBUG 0x0000000018 - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_DM_PARTIAL_0 0x0010020ba0 -#define A_DM_PARTIAL_1 0x0010020ba8 -#define A_DM_PARTIAL_2 0x0010020bb0 -#define A_DM_PARTIAL_3 0x0010020bb8 -#define DM_PARTIAL_REGISTER_SPACING 0x8 -#define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING)) -#endif /* 1250 PASS3 || 112x PASS1 */ - -#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define A_DM_CRC_0 0x0010020b80 -#define A_DM_CRC_1 0x0010020b90 -#define DM_CRC_REGISTER_SPACING 0x10 -#define DM_CRC_NUM_CHANNELS 2 -#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) -#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) - -#define R_CRC_DEF_0 0x00 -#define R_CTCP_DEF_0 0x08 -#endif /* 1250 PASS3 || 112x PASS1 */ - -/* ********************************************************************* - * Physical Address Map - ********************************************************************* */ - -#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) -#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) -#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) -#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) -#define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) -#define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) -#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) -#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) -#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) -#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) -#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) -#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) -#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) -#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) -#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) -#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) -#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) -#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) -#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) -#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) -#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) -#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) -#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) -#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) -#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) - -#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) -#define PHYS_L2CACHE_NUM_WAYS 4 -#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) -#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) -#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) -#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) -#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) - - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_scd.h b/include/asm-mips64/sibyte/sb1250_scd.h deleted file mode 100644 index 22e8041959e..00000000000 --- a/include/asm-mips64/sibyte/sb1250_scd.h +++ /dev/null @@ -1,582 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * SCD Constants and Macros File: sb1250_scd.h - * - * This module contains constants and macros useful for - * manipulating the System Control and Debug module on the 1250. - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - -#ifndef _SB1250_SCD_H -#define _SB1250_SCD_H - -#include "sb1250_defs.h" - -/* ********************************************************************* - * System control/debug registers - ********************************************************************* */ - -/* - * System Revision Register (Table 4-1) - */ - -#define M_SYS_RESERVED _SB_MAKEMASK(8,0) - -#define S_SYS_REVISION _SB_MAKE64(8) -#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) -#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) -#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) - -#if SIBYTE_HDR_FEATURE_CHIP(1250) -#define K_SYS_REVISION_BCM1250_PASS1 1 -#define K_SYS_REVISION_BCM1250_PASS2 3 -#define K_SYS_REVISION_BCM1250_A10 11 -#define K_SYS_REVISION_BCM1250_PASS2_2 16 -#define K_SYS_REVISION_BCM1250_B2 17 -#define K_SYS_REVISION_BCM1250_PASS3 32 -#define K_SYS_REVISION_BCM1250_C1 33 - -/* XXX: discourage people from using these constants. */ -#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 -#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 -#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 -#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 -#endif /* 1250 */ - -#if SIBYTE_HDR_FEATURE_CHIP(112x) -#define K_SYS_REVISION_BCM112x_A1 32 -#define K_SYS_REVISION_BCM112x_A2 33 -#endif /* 112x */ - -/* XXX: discourage people from using these constants. */ -#define S_SYS_PART _SB_MAKE64(16) -#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) -#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) -#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) - -/* XXX: discourage people from using these constants. */ -#define K_SYS_PART_SB1250 0x1250 -#define K_SYS_PART_BCM1120 0x1121 -#define K_SYS_PART_BCM1125 0x1123 -#define K_SYS_PART_BCM1125H 0x1124 - -/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ -#define S_SYS_SOC_TYPE _SB_MAKE64(16) -#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) -#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) -#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) - -#define K_SYS_SOC_TYPE_BCM1250 0x0 -#define K_SYS_SOC_TYPE_BCM1120 0x1 -#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ -#define K_SYS_SOC_TYPE_BCM1125 0x3 -#define K_SYS_SOC_TYPE_BCM1125H 0x4 -#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ - -/* - * Calculate correct SOC type given a copy of system revision register. - * - * (For the assembler version, sysrev and dest may be the same register. - * Also, it clobbers AT.) - */ -#ifdef __ASSEMBLER__ -#define SYS_SOC_TYPE(dest, sysrev) \ - .set push ; \ - .set reorder ; \ - dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ - andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ - beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ - beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ - b 992f ; \ -991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ -992: \ - .set pop -#else -#define SYS_SOC_TYPE(sysrev) \ - ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ - || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ - ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) -#endif - -#define S_SYS_WID _SB_MAKE64(32) -#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) -#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) -#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) - -/* System Manufacturing Register -* Register: SCD_SYSTEM_MANUF -*/ - -/* Wafer ID: bits 31:0 */ -#define S_SYS_WAFERID1_200 _SB_MAKE64(0) -#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) -#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) -#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) - -#define S_SYS_BIN _SB_MAKE64(32) -#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) -#define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) -#define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) - -/* Wafer ID: bits 39:36 */ -#define S_SYS_WAFERID2_200 _SB_MAKE64(36) -#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) -#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) -#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) - -/* Wafer ID: bits 39:0 */ -#define S_SYS_WAFERID_300 _SB_MAKE64(0) -#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) -#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) -#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) - -#define S_SYS_XPOS _SB_MAKE64(40) -#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) -#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) -#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) - -#define S_SYS_YPOS _SB_MAKE64(46) -#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) -#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) -#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) - -/* - * System Config Register (Table 4-2) - * Register: SCD_SYSTEM_CFG - */ - -#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) -#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) -#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) -#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) - -#define S_SYS_PLL_DIV _SB_MAKE64(7) -#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) -#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) -#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) - -#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) -#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) -#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) -#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) -#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) - -#define S_SYS_BOOT_MODE _SB_MAKE64(17) -#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) -#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) -#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) -#define K_SYS_BOOT_MODE_ROM32 0 -#define K_SYS_BOOT_MODE_ROM8 1 -#define K_SYS_BOOT_MODE_SMBUS_SMALL 2 -#define K_SYS_BOOT_MODE_SMBUS_BIG 3 - -#define M_SYS_PCI_HOST _SB_MAKEMASK1(19) -#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) -#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) -#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) -#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) -#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) -#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) - -#define S_SYS_CONFIG 26 -#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) -#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) -#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) - -/* The following bits are writeable by JTAG only. */ - -#define M_SYS_CLKSTOP _SB_MAKEMASK1(32) -#define M_SYS_CLKSTEP _SB_MAKEMASK1(33) - -#define S_SYS_CLKCOUNT 34 -#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) -#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) -#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) - -#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) - -#define S_SYS_PLL_IREF 43 -#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) - -#define S_SYS_PLL_VCO 45 -#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) - -#define S_SYS_PLL_VREG 47 -#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) - -#define M_SYS_MEM_RESET _SB_MAKEMASK1(49) -#define M_SYS_L2C_RESET _SB_MAKEMASK1(50) -#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) -#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) -#define M_SYS_SCD_RESET _SB_MAKEMASK1(53) - -/* End of bits writable by JTAG only. */ - -#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) -#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) - -#define M_SYS_UNICPU0 _SB_MAKEMASK1(56) -#define M_SYS_UNICPU1 _SB_MAKEMASK1(57) - -#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) -#define M_SYS_EXT_RESET _SB_MAKEMASK1(59) -#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) - -#define M_SYS_MISR_MODE _SB_MAKEMASK1(61) -#define M_SYS_MISR_RESET _SB_MAKEMASK1(62) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_SYS_SW_FLAG _SB_MAKEMASK1(63) -#endif /* 1250 PASS2 || 112x PASS1 */ - - -/* - * Mailbox Registers (Table 4-3) - * Registers: SCD_MBOX_CPU_x - */ - -#define S_MBOX_INT_3 0 -#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) -#define S_MBOX_INT_2 16 -#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) -#define S_MBOX_INT_1 32 -#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) -#define S_MBOX_INT_0 48 -#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) - -/* - * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) - * Registers: SCD_WDOG_INIT_CNT_x - */ - -#define V_SCD_WDOG_FREQ 1000000 - -#define S_SCD_WDOG_INIT 0 -#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) - -#define S_SCD_WDOG_CNT 0 -#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) - -#define S_SCD_WDOG_ENABLE 0 -#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) - -#define S_SCD_WDOG_RESET_TYPE 2 -#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) -#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) -#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) - -#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ -#define K_SCD_WDOG_RESET_SOFT 1 -#define K_SCD_WDOG_RESET_CPU0 3 -#define K_SCD_WDOG_RESET_CPU1 5 -#define K_SCD_WDOG_RESET_BOTH_CPUS 7 - -/* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ -#if SIBYTE_HDR_FEATURE(1250, PASS3) -#define S_SCD_WDOG_HAS_RESET 8 -#define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) -#endif - - -/* - * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) - */ - -#define V_SCD_TIMER_FREQ 1000000 - -#define S_SCD_TIMER_INIT 0 -#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) -#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) -#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) - -#define S_SCD_TIMER_CNT 0 -#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) -#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) -#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) - -#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) -#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) -#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE - -/* - * System Performance Counters - */ - -#define S_SPC_CFG_SRC0 0 -#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) -#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) -#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) - -#define S_SPC_CFG_SRC1 8 -#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) -#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) -#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) - -#define S_SPC_CFG_SRC2 16 -#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) -#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) -#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) - -#define S_SPC_CFG_SRC3 24 -#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) -#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) -#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) - -#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) -#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) - - -/* - * Bus Watcher - */ - -#define S_SCD_BERR_TID 8 -#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) -#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) -#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) - -#define S_SCD_BERR_RID 18 -#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) -#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) -#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) - -#define S_SCD_BERR_DCODE 22 -#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) -#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) -#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) - -#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) - - -#define S_SCD_L2ECC_CORR_D 0 -#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) -#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) -#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) - -#define S_SCD_L2ECC_BAD_D 8 -#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) -#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) -#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) - -#define S_SCD_L2ECC_CORR_T 16 -#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) -#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) -#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) - -#define S_SCD_L2ECC_BAD_T 24 -#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) -#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) -#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) - -#define S_SCD_MEM_ECC_CORR 0 -#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) -#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) -#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) - -#define S_SCD_MEM_ECC_BAD 8 -#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) -#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) -#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) - -#define S_SCD_MEM_BUSERR 16 -#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) -#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) -#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) - - -/* - * Address Trap Registers - */ - -#define M_ATRAP_INDEX _SB_MAKEMASK(4,0) -#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) - -#define S_ATRAP_CFG_CNT 0 -#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) -#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) -#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) - -#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) -#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) -#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) -#define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) -#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) - -#define S_ATRAP_CFG_AGENTID 8 -#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) -#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) -#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) - -#define K_BUS_AGENT_CPU0 0 -#define K_BUS_AGENT_CPU1 1 -#define K_BUS_AGENT_IOB0 2 -#define K_BUS_AGENT_IOB1 3 -#define K_BUS_AGENT_SCD 4 -#define K_BUS_AGENT_RESERVED 5 -#define K_BUS_AGENT_L2C 6 -#define K_BUS_AGENT_MC 7 - -#define S_ATRAP_CFG_CATTR 12 -#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) -#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) -#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) - -#define K_ATRAP_CFG_CATTR_IGNORE 0 -#define K_ATRAP_CFG_CATTR_UNC 1 -#define K_ATRAP_CFG_CATTR_CACHEABLE 2 -#define K_ATRAP_CFG_CATTR_NONCOH 3 -#define K_ATRAP_CFG_CATTR_COHERENT 4 -#define K_ATRAP_CFG_CATTR_NOTUNC 5 -#define K_ATRAP_CFG_CATTR_NOTNONCOH 6 -#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 - -/* - * Trace Buffer Config register - */ - -#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) -#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) -#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) -#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) -#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) -#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) -#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) -#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) -#endif /* 1250 PASS2 || 112x PASS1 */ - -#define S_SCD_TRACE_CFG_CUR_ADDR 10 -#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) -#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) -#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) - -/* - * Trace Event registers - */ - -#define S_SCD_TREVT_ADDR_MATCH 0 -#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) -#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) -#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) - -#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) -#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) -#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) -#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) -#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) -#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) -#define M_SCD_TREVT_READ _SB_MAKEMASK1(11) - -#define S_SCD_TREVT_REQID 12 -#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) -#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) -#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) - -#define S_SCD_TREVT_RESPID 16 -#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) -#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) -#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) - -#define S_SCD_TREVT_DATAID 20 -#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) -#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) -#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) - -#define S_SCD_TREVT_COUNT 24 -#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) -#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) -#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) - -/* - * Trace Sequence registers - */ - -#define S_SCD_TRSEQ_EVENT4 0 -#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) -#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) -#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) - -#define S_SCD_TRSEQ_EVENT3 4 -#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) -#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) -#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) - -#define S_SCD_TRSEQ_EVENT2 8 -#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) -#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) -#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) - -#define S_SCD_TRSEQ_EVENT1 12 -#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) -#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) -#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) - -#define K_SCD_TRSEQ_E0 0 -#define K_SCD_TRSEQ_E1 1 -#define K_SCD_TRSEQ_E2 2 -#define K_SCD_TRSEQ_E3 3 -#define K_SCD_TRSEQ_E0_E1 4 -#define K_SCD_TRSEQ_E1_E2 5 -#define K_SCD_TRSEQ_E2_E3 6 -#define K_SCD_TRSEQ_E0_E1_E2 7 -#define K_SCD_TRSEQ_E0_E1_E2_E3 8 -#define K_SCD_TRSEQ_E0E1 9 -#define K_SCD_TRSEQ_E0E1E2 10 -#define K_SCD_TRSEQ_E0E1E2E3 11 -#define K_SCD_TRSEQ_E0E1_E2 12 -#define K_SCD_TRSEQ_E0E1_E2E3 13 -#define K_SCD_TRSEQ_E0E1_E2_E3 14 -#define K_SCD_TRSEQ_IGNORED 15 - -#define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ - V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ - V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ - V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) - -#define S_SCD_TRSEQ_FUNCTION 16 -#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) -#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) -#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) - -#define K_SCD_TRSEQ_FUNC_NOP 0 -#define K_SCD_TRSEQ_FUNC_START 1 -#define K_SCD_TRSEQ_FUNC_STOP 2 -#define K_SCD_TRSEQ_FUNC_FREEZE 3 - -#define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) -#define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) -#define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) -#define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) - -#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) -#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) -#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) -#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) -#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_smbus.h b/include/asm-mips64/sibyte/sb1250_smbus.h deleted file mode 100644 index 287cbfe9efa..00000000000 --- a/include/asm-mips64/sibyte/sb1250_smbus.h +++ /dev/null @@ -1,170 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * SMBUS Constants File: sb1250_smbus.h - * - * This module contains constants and macros useful for - * manipulating the SB1250's SMbus devices. - * - * SB1250 specification level: 01/02/2002 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_SMBUS_H -#define _SB1250_SMBUS_H - -#include "sb1250_defs.h" - -/* - * SMBus Clock Frequency Register (Table 14-2) - */ - -#define S_SMB_FREQ_DIV 0 -#define M_SMB_FREQ_DIV _SB_MAKEMASK(13,S_SMB_FREQ_DIV) -#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x,S_SMB_FREQ_DIV) - -#define K_SMB_FREQ_400KHZ 0x1F -#define K_SMB_FREQ_100KHZ 0x7D - -#define S_SMB_CMD 0 -#define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD) -#define V_SMB_CMD(x) _SB_MAKEVALUE(x,S_SMB_CMD) - -/* - * SMBus control register (Table 14-4) - */ - -#define M_SMB_ERR_INTR _SB_MAKEMASK1(0) -#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1) -#define M_SMB_DATA_OUT _SB_MAKEMASK1(4) -#define M_SMB_DATA_DIR _SB_MAKEMASK1(5) -#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR -#define M_SMB_CLK_OUT _SB_MAKEMASK1(6) -#define M_SMB_DIRECT_ENABLE _SB_MAKEMASK1(7) - -/* - * SMBus status registers (Table 14-5) - */ - -#define M_SMB_BUSY _SB_MAKEMASK1(0) -#define M_SMB_ERROR _SB_MAKEMASK1(1) -#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2) -#define M_SMB_REF _SB_MAKEMASK1(6) -#define M_SMB_DATA_IN _SB_MAKEMASK1(7) - -/* - * SMBus Start/Command registers (Table 14-9) - */ - -#define S_SMB_ADDR 0 -#define M_SMB_ADDR _SB_MAKEMASK(7,S_SMB_ADDR) -#define V_SMB_ADDR(x) _SB_MAKEVALUE(x,S_SMB_ADDR) -#define G_SMB_ADDR(x) _SB_GETVALUE(x,S_SMB_ADDR,M_SMB_ADDR) - -#define M_SMB_QDATA _SB_MAKEMASK1(7) - -#define S_SMB_TT 8 -#define M_SMB_TT _SB_MAKEMASK(3,S_SMB_TT) -#define V_SMB_TT(x) _SB_MAKEVALUE(x,S_SMB_TT) -#define G_SMB_TT(x) _SB_GETVALUE(x,S_SMB_TT,M_SMB_TT) - -#define K_SMB_TT_WR1BYTE 0 -#define K_SMB_TT_WR2BYTE 1 -#define K_SMB_TT_WR3BYTE 2 -#define K_SMB_TT_CMD_RD1BYTE 3 -#define K_SMB_TT_CMD_RD2BYTE 4 -#define K_SMB_TT_RD1BYTE 5 -#define K_SMB_TT_QUICKCMD 6 -#define K_SMB_TT_EEPROMREAD 7 - -#define V_SMB_TT_WR1BYTE V_SMB_TT(K_SMB_TT_WR1BYTE) -#define V_SMB_TT_WR2BYTE V_SMB_TT(K_SMB_TT_WR2BYTE) -#define V_SMB_TT_WR3BYTE V_SMB_TT(K_SMB_TT_WR3BYTE) -#define V_SMB_TT_CMD_RD1BYTE V_SMB_TT(K_SMB_TT_CMD_RD1BYTE) -#define V_SMB_TT_CMD_RD2BYTE V_SMB_TT(K_SMB_TT_CMD_RD2BYTE) -#define V_SMB_TT_RD1BYTE V_SMB_TT(K_SMB_TT_RD1BYTE) -#define V_SMB_TT_QUICKCMD V_SMB_TT(K_SMB_TT_QUICKCMD) -#define V_SMB_TT_EEPROMREAD V_SMB_TT(K_SMB_TT_EEPROMREAD) - -#define M_SMB_PEC _SB_MAKEMASK1(15) - -/* - * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7) - */ - -#define S_SMB_LB 0 -#define M_SMB_LB _SB_MAKEMASK(8,S_SMB_LB) -#define V_SMB_LB(x) _SB_MAKEVALUE(x,S_SMB_LB) - -#define S_SMB_MB 8 -#define M_SMB_MB _SB_MAKEMASK(8,S_SMB_MB) -#define V_SMB_MB(x) _SB_MAKEVALUE(x,S_SMB_MB) - - -/* - * SMBus Packet Error Check register (Table 14-8) - */ - -#define S_SPEC_PEC 0 -#define M_SPEC_PEC _SB_MAKEMASK(8,S_SPEC_PEC) -#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC) - - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) - -#define S_SMB_CMDH 8 -#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMBH_CMD) -#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMBH_CMD) - -#define M_SMB_EXTEND _SB_MAKEMASK1(14) - -#define M_SMB_DIR _SB_MAKEMASK1(13) - -#define S_SMB_DFMT 8 -#define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT) -#define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT) -#define G_SMB_DFMT(x) _SB_GETVALUE(x,S_SMB_DFMT,M_SMB_DFMT) - -#define K_SMB_DFMT_1BYTE 0 -#define K_SMB_DFMT_2BYTE 1 -#define K_SMB_DFMT_3BYTE 2 -#define K_SMB_DFMT_4BYTE 3 -#define K_SMB_DFMT_NODATA 4 -#define K_SMB_DFMT_CMD4BYTE 5 -#define K_SMB_DFMT_CMD5BYTE 6 -#define K_SMB_DFMT_RESERVED 7 - -#define V_SMB_DFMT_1BYTE V_SMB_DFMT(K_SMB_DFMT_1BYTE) -#define V_SMB_DFMT_2BYTE V_SMB_DFMT(K_SMB_DFMT_2BYTE) -#define V_SMB_DFMT_3BYTE V_SMB_DFMT(K_SMB_DFMT_3BYTE) -#define V_SMB_DFMT_4BYTE V_SMB_DFMT(K_SMB_DFMT_4BYTE) -#define V_SMB_DFMT_NODATA V_SMB_DFMT(K_SMB_DFMT_NODATA) -#define V_SMB_DFMT_CMD4BYTE V_SMB_DFMT(K_SMB_DFMT_CMD4BYTE) -#define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE) -#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) - -#endif /* 1250 PASS2 || 112x PASS1 */ - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_syncser.h b/include/asm-mips64/sibyte/sb1250_syncser.h deleted file mode 100644 index 8d5e8edd3c4..00000000000 --- a/include/asm-mips64/sibyte/sb1250_syncser.h +++ /dev/null @@ -1,148 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * Synchronous Serial Constants File: sb1250_syncser.h - * - * This module contains constants and macros useful for - * manipulating the SB1250's Synchronous Serial - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_SYNCSER_H -#define _SB1250_SYNCSER_H - -#include "sb1250_defs.h" - -/* - * Serial Mode Configuration Register - */ - -#define M_SYNCSER_CRC_MODE _SB_MAKEMASK1(0) -#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1) - -#define S_SYNCSER_FLAG_NUM 2 -#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4,S_SYNCSER_FLAG_NUM) -#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x,S_SYNCSER_FLAG_NUM) - -#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6) -#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7) -#define M_SYNCSER_LOOP_MODE _SB_MAKEMASK1(8) -#define M_SYNCSER_LOOPBACK _SB_MAKEMASK1(9) - -/* - * Serial Clock Source and Line Interface Mode Register - */ - -#define M_SYNCSER_RXCLK_INV _SB_MAKEMASK1(0) -#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1) - -#define S_SYNCSER_RXSYNC_DLY 2 -#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_RXSYNC_DLY) -#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_RXSYNC_DLY) - -#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4) -#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5) - -#define M_SYNCSER_RXSYNC_EDGE _SB_MAKEMASK1(6) -#define M_SYNCSER_RXSYNC_INT _SB_MAKEMASK1(7) - -#define M_SYNCSER_TXCLK_INV _SB_MAKEMASK1(8) -#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9) - -#define S_SYNCSER_TXSYNC_DLY 10 -#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_TXSYNC_DLY) -#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_TXSYNC_DLY) - -#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12) -#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13) - -#define M_SYNCSER_TXSYNC_EDGE _SB_MAKEMASK1(14) -#define M_SYNCSER_TXSYNC_INT _SB_MAKEMASK1(15) - -/* - * Serial Command Register - */ - -#define M_SYNCSER_CMD_RX_EN _SB_MAKEMASK1(0) -#define M_SYNCSER_CMD_TX_EN _SB_MAKEMASK1(1) -#define M_SYNCSER_CMD_RX_RESET _SB_MAKEMASK1(2) -#define M_SYNCSER_CMD_TX_RESET _SB_MAKEMASK1(3) -#define M_SYNCSER_CMD_TX_PAUSE _SB_MAKEMASK1(5) - -/* - * Serial DMA Enable Register - */ - -#define M_SYNCSER_DMA_RX_EN _SB_MAKEMASK1(0) -#define M_SYNCSER_DMA_TX_EN _SB_MAKEMASK1(4) - -/* - * Serial Status Register - */ - -#define M_SYNCSER_RX_CRCERR _SB_MAKEMASK1(0) -#define M_SYNCSER_RX_ABORT _SB_MAKEMASK1(1) -#define M_SYNCSER_RX_OCTET _SB_MAKEMASK1(2) -#define M_SYNCSER_RX_LONGFRM _SB_MAKEMASK1(3) -#define M_SYNCSER_RX_SHORTFRM _SB_MAKEMASK1(4) -#define M_SYNCSER_RX_OVERRUN _SB_MAKEMASK1(5) -#define M_SYNCSER_RX_SYNC_ERR _SB_MAKEMASK1(6) -#define M_SYNCSER_TX_CRCERR _SB_MAKEMASK1(8) -#define M_SYNCSER_TX_UNDERRUN _SB_MAKEMASK1(9) -#define M_SYNCSER_TX_SYNC_ERR _SB_MAKEMASK1(10) -#define M_SYNCSER_TX_PAUSE_COMPLETE _SB_MAKEMASK1(11) -#define M_SYNCSER_RX_EOP_COUNT _SB_MAKEMASK1(16) -#define M_SYNCSER_RX_EOP_TIMER _SB_MAKEMASK1(17) -#define M_SYNCSER_RX_EOP_SEEN _SB_MAKEMASK1(18) -#define M_SYNCSER_RX_HWM _SB_MAKEMASK1(19) -#define M_SYNCSER_RX_LWM _SB_MAKEMASK1(20) -#define M_SYNCSER_RX_DSCR _SB_MAKEMASK1(21) -#define M_SYNCSER_RX_DERR _SB_MAKEMASK1(22) -#define M_SYNCSER_TX_EOP_COUNT _SB_MAKEMASK1(24) -#define M_SYNCSER_TX_EOP_TIMER _SB_MAKEMASK1(25) -#define M_SYNCSER_TX_EOP_SEEN _SB_MAKEMASK1(26) -#define M_SYNCSER_TX_HWM _SB_MAKEMASK1(27) -#define M_SYNCSER_TX_LWM _SB_MAKEMASK1(28) -#define M_SYNCSER_TX_DSCR _SB_MAKEMASK1(29) -#define M_SYNCSER_TX_DERR _SB_MAKEMASK1(30) -#define M_SYNCSER_TX_DZERO _SB_MAKEMASK1(31) - -/* - * Sequencer Table Entry format - */ - -#define M_SYNCSER_SEQ_LAST _SB_MAKEMASK1(0) -#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1) - -#define S_SYNCSER_SEQ_COUNT 2 -#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4,S_SYNCSER_SEQ_COUNT) -#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x,S_SYNCSER_SEQ_COUNT) - -#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6) -#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7) - -#endif diff --git a/include/asm-mips64/sibyte/sb1250_uart.h b/include/asm-mips64/sibyte/sb1250_uart.h deleted file mode 100644 index 7655d6945cc..00000000000 --- a/include/asm-mips64/sibyte/sb1250_uart.h +++ /dev/null @@ -1,354 +0,0 @@ -/* ********************************************************************* - * SB1250 Board Support Package - * - * UART Constants File: sb1250_uart.h - * - * This module contains constants and macros useful for - * manipulating the SB1250's UARTs - * - * SB1250 specification level: User's manual 1/02/02 - * - * Author: Mitch Lichtenberg - * - ********************************************************************* - * - * Copyright 2000,2001,2002,2003 - * Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ********************************************************************* */ - - -#ifndef _SB1250_UART_H -#define _SB1250_UART_H - -#include "sb1250_defs.h" - -/* ********************************************************************** - * DUART Registers - ********************************************************************** */ - -/* - * DUART Mode Register #1 (Table 10-3) - * Register: DUART_MODE_REG_1_A - * Register: DUART_MODE_REG_1_B - */ - -#define S_DUART_BITS_PER_CHAR 0 -#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) -#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) - -#define K_DUART_BITS_PER_CHAR_RSV0 0 -#define K_DUART_BITS_PER_CHAR_RSV1 1 -#define K_DUART_BITS_PER_CHAR_7 2 -#define K_DUART_BITS_PER_CHAR_8 3 - -#define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) -#define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) -#define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) -#define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) - - -#define M_DUART_PARITY_TYPE_EVEN 0x00 -#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) - -#define S_DUART_PARITY_MODE 3 -#define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) -#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) - -#define K_DUART_PARITY_MODE_ADD 0 -#define K_DUART_PARITY_MODE_ADD_FIXED 1 -#define K_DUART_PARITY_MODE_NONE 2 - -#define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) -#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) -#define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) - -#define M_DUART_ERR_MODE _SB_MAKEMASK1(5) /* must be zero */ - -#define M_DUART_RX_IRQ_SEL_RXRDY 0 -#define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) - -#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) - -/* - * DUART Mode Register #2 (Table 10-4) - * Register: DUART_MODE_REG_2_A - * Register: DUART_MODE_REG_2_B - */ - -#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ - -#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) -#define M_DUART_STOP_BIT_LEN_1 0 - -#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) - - -#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ - -#define S_DUART_CHAN_MODE 6 -#define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) -#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) - -#define K_DUART_CHAN_MODE_NORMAL 0 -#define K_DUART_CHAN_MODE_LCL_LOOP 2 -#define K_DUART_CHAN_MODE_REM_LOOP 3 - -#define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL) -#define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP) -#define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP) - -/* - * DUART Command Register (Table 10-5) - * Register: DUART_CMD_A - * Register: DUART_CMD_B - */ - -#define M_DUART_RX_EN _SB_MAKEMASK1(0) -#define M_DUART_RX_DIS _SB_MAKEMASK1(1) -#define M_DUART_TX_EN _SB_MAKEMASK1(2) -#define M_DUART_TX_DIS _SB_MAKEMASK1(3) - -#define S_DUART_MISC_CMD 4 -#define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) -#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) - -#define K_DUART_MISC_CMD_NOACTION0 0 -#define K_DUART_MISC_CMD_NOACTION1 1 -#define K_DUART_MISC_CMD_RESET_RX 2 -#define K_DUART_MISC_CMD_RESET_TX 3 -#define K_DUART_MISC_CMD_NOACTION4 4 -#define K_DUART_MISC_CMD_RESET_BREAK_INT 5 -#define K_DUART_MISC_CMD_START_BREAK 6 -#define K_DUART_MISC_CMD_STOP_BREAK 7 - -#define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) -#define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) -#define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) -#define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) -#define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) -#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) -#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) -#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) - -#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) - -/* - * DUART Status Register (Table 10-6) - * Register: DUART_STATUS_A - * Register: DUART_STATUS_B - * READ-ONLY - */ - -#define M_DUART_RX_RDY _SB_MAKEMASK1(0) -#define M_DUART_RX_FFUL _SB_MAKEMASK1(1) -#define M_DUART_TX_RDY _SB_MAKEMASK1(2) -#define M_DUART_TX_EMT _SB_MAKEMASK1(3) -#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) -#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) -#define M_DUART_FRM_ERR _SB_MAKEMASK1(6) -#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) - -/* - * DUART Baud Rate Register (Table 10-7) - * Register: DUART_CLK_SEL_A - * Register: DUART_CLK_SEL_B - */ - -#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) -#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) - -/* - * DUART Data Registers (Table 10-8 and 10-9) - * Register: DUART_RX_HOLD_A - * Register: DUART_RX_HOLD_B - * Register: DUART_TX_HOLD_A - * Register: DUART_TX_HOLD_B - */ - -#define M_DUART_RX_DATA _SB_MAKEMASK(8,0) -#define M_DUART_TX_DATA _SB_MAKEMASK(8,0) - -/* - * DUART Input Port Register (Table 10-10) - * Register: DUART_IN_PORT - */ - -#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) -#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) -#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) -#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) -#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) -#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) -#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) -#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) - -/* - * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) - * Register: DUART_INPORT_CHNG - */ - -#define S_DUART_IN_PIN_VAL 0 -#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) - -#define S_DUART_IN_PIN_CHNG 4 -#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) - - -/* - * DUART Output port control register (Table 10-14) - * Register: DUART_OPCR - */ - -#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ -#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) -#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ -#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ - -/* - * DUART Aux Control Register (Table 10-15) - * Register: DUART_AUX_CTRL - */ - -#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) -#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) -#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) -#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) -#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) - -#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) -#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) - -/* - * DUART Interrupt Status Register (Table 10-16) - * Register: DUART_ISR - */ - -#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) -#define M_DUART_ISR_RX_A _SB_MAKEMASK1(1) -#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) -#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) -#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) -#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) -#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) -#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) - -/* - * DUART Channel A Interrupt Status Register (Table 10-17) - * DUART Channel B Interrupt Status Register (Table 10-18) - * Register: DUART_ISR_A - * Register: DUART_ISR_B - */ - -#define M_DUART_ISR_TX _SB_MAKEMASK1(0) -#define M_DUART_ISR_RX _SB_MAKEMASK1(1) -#define M_DUART_ISR_BRK _SB_MAKEMASK1(2) -#define M_DUART_ISR_IN _SB_MAKEMASK1(3) -#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) - -/* - * DUART Interrupt Mask Register (Table 10-19) - * Register: DUART_IMR - */ - -#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) -#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) -#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) -#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) -#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) - -#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) -#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) -#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) -#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) -#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) - -/* - * DUART Channel A Interrupt Mask Register (Table 10-20) - * DUART Channel B Interrupt Mask Register (Table 10-21) - * Register: DUART_IMR_A - * Register: DUART_IMR_B - */ - -#define M_DUART_IMR_TX _SB_MAKEMASK1(0) -#define M_DUART_IMR_RX _SB_MAKEMASK1(1) -#define M_DUART_IMR_BRK _SB_MAKEMASK1(2) -#define M_DUART_IMR_IN _SB_MAKEMASK1(3) -#define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) -#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) - - -/* - * DUART Output Port Set Register (Table 10-22) - * Register: DUART_SET_OPR - */ - -#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) -#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) -#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) -#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) - -/* - * DUART Output Port Clear Register (Table 10-23) - * Register: DUART_CLEAR_OPR - */ - -#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) -#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) -#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) -#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) -#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) - -/* - * DUART Output Port RTS Register (Table 10-24) - * Register: DUART_OUT_PORT - */ - -#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) -#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) -#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) -#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) -#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) - -#define M_DUART_OUT_PIN_SET(chan) \ - (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) -#define M_DUART_OUT_PIN_CLR(chan) \ - (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) - -#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) -/* - * Full Interrupt Control Register - */ - -#define S_DUART_SIG_FULL _SB_MAKE64(0) -#define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) -#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) -#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) - -#define S_DUART_INT_TIME _SB_MAKE64(4) -#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) -#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) -#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) -#endif /* 1250 PASS2 || 112x PASS1 */ - - -/* ********************************************************************** */ - - -#endif diff --git a/include/asm-mips64/sibyte/sentosa.h b/include/asm-mips64/sibyte/sentosa.h deleted file mode 100644 index 64c47874f32..00000000000 --- a/include/asm-mips64/sibyte/sentosa.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2000, 2001 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#ifndef __ASM_SIBYTE_SENTOSA_H -#define __ASM_SIBYTE_SENTOSA_H - -#include -#include - -#ifdef CONFIG_SIBYTE_SENTOSA -#define SIBYTE_BOARD_NAME "BCM91250E (Sentosa)" -#endif -#ifdef CONFIG_SIBYTE_RHONE -#define SIBYTE_BOARD_NAME "BCM91125E (Rhone)" -#endif - -/* Generic bus chip selects */ -#ifdef CONFIG_SIBYTE_RHONE -#define LEDS_CS 6 -#define LEDS_PHYS 0x1d0a0000 -#endif - -/* GPIOs */ -#define K_GPIO_DBG_LED 0 - -#endif /* __ASM_SIBYTE_SENTOSA_H */ diff --git a/include/asm-mips64/sibyte/swarm.h b/include/asm-mips64/sibyte/swarm.h deleted file mode 100644 index 9a460fe32b5..00000000000 --- a/include/asm-mips64/sibyte/swarm.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2000, 2001 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -#ifndef __ASM_SIBYTE_SWARM_H -#define __ASM_SIBYTE_SWARM_H - -#include -#include - -#ifdef CONFIG_SIBYTE_SWARM -#define SIBYTE_BOARD_NAME "BCM91250A (SWARM)" -#endif -#ifdef CONFIG_SIBYTE_PTSWARM -#define SIBYTE_BOARD_NAME "PTSWARM" -#endif -#ifdef CONFIG_SIBYTE_CRHONE -#define SIBYTE_BOARD_NAME "BCM91125C (CRhone)" -#endif -#ifdef CONFIG_SIBYTE_CRHINE -#define SIBYTE_BOARD_NAME "BCM91120C (CRhine)" -#endif - -/* Generic bus chip selects */ -#define LEDS_CS 3 -#define LEDS_PHYS 0x100a0000 -#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) -#define IDE_CS 4 -#define IDE_PHYS 0x100b0000 -#define PCMCIA_CS 6 -#define PCMCIA_PHYS 0x11000000 -#endif - -/* GPIOs */ -#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) -#define K_GPIO_GB_IDE 4 -#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) -#define K_GPIO_PC_READY 9 -#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) -#endif - -#endif /* __ASM_SIBYTE_SWARM_H */ diff --git a/include/asm-mips64/sibyte/trace_prof.h b/include/asm-mips64/sibyte/trace_prof.h deleted file mode 100644 index 38157a9e400..00000000000 --- a/include/asm-mips64/sibyte/trace_prof.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (C) 2001 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef __ASM_SIBYTE_TRACE_PROF_H -#define __ASM_SIBYTE_TRACE_PROF_H - -#if SBPROF_TB_DEBUG -#define DBG(a) a -#else -#define DBG(a) -#endif - -#define SBPROF_TB_MAJOR 240 -#define DEVNAME "bcm1250_tbprof" - -typedef u_int64_t tb_sample_t[6*256]; - -struct sbprof_tb { - int open; - tb_sample_t *sbprof_tbbuf; - int next_tb_sample; - - volatile int tb_enable; - volatile int tb_armed; - - wait_queue_head_t tb_sync; - wait_queue_head_t tb_read; -}; - -#define MAX_SAMPLE_BYTES (24*1024*1024) -#define MAX_TBSAMPLE_BYTES (12*1024*1024) - -#define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t)) -#define TB_SAMPLE_SIZE (sizeof(tb_sample_t)) -#define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE) - -/* IOCTLs */ -#define SBPROF_ZBSTART _IOW('s', 0, int) -#define SBPROF_ZBSTOP _IOW('s', 1, int) -#define SBPROF_ZBWAITFULL _IOW('s', 2, int) - -/*************************************************************************** - * Routines for gathering ZBbus profiles using trace buffer - ***************************************************************************/ - -/* Requires: Already called zclk_timer_init with a value that won't - saturate 40 bits. No subsequent use of SCD performance counters - or trace buffer. - Effect: Starts gathering random ZBbus profiles using trace buffer. */ -static int sbprof_zbprof_start(struct file *filp); - -/* Effect: Stops collection of ZBbus profiles */ -static int sbprof_zbprof_stop(void); - - -/*************************************************************************** - * Routines for using 40-bit SCD cycle counter - * - * Client responsible for either handling interrupts or making sure - * the cycles counter never saturates, e.g., by doing - * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs. - ***************************************************************************/ - -/* Configures SCD counter 0 to count ZCLKs starting from val; - Configures SCD counters1,2,3 to count nothing. - Must not be called while gathering ZBbus profiles. - -unsigned long long val; */ -#define zclk_timer_init(val) \ - __asm__ __volatile__ (".set push;" \ - ".set mips64;" \ - "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \ - "sd %0, 0x10($8);" /* write val to counter0 */ \ - "sd %1, 0($8);" /* config counter0 for zclks*/ \ - ".set pop" \ - : /* no outputs */ \ - /* enable, counter0 */ \ - : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \ - : /* modifies */ "$8" ) - - -/* Reads SCD counter 0 and puts result in value - unsigned long long val; */ -#define zclk_get(val) \ - __asm__ __volatile__ (".set push;" \ - ".set mips64;" \ - "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \ - "ld %0, 0x10($8);" /* write val to counter0 */ \ - ".set pop" \ - : /* outputs */ "=r"(val) \ - : /* inputs */ \ - : /* modifies */ "$8" ) - -#endif /* __ASM_SIBYTE_TRACE_PROF_H */ diff --git a/include/asm-mips64/sigcontext.h b/include/asm-mips64/sigcontext.h deleted file mode 100644 index a84df563c32..00000000000 --- a/include/asm-mips64/sigcontext.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_SIGCONTEXT_H -#define _ASM_SIGCONTEXT_H - -/* - * Keep this struct definition in sync with the sigcontext fragment - * in arch/mips/tools/offset.c - */ -struct sigcontext { - unsigned long long sc_regs[32]; - unsigned long long sc_fpregs[32]; - unsigned long long sc_mdhi; - unsigned long long sc_mdlo; - unsigned long long sc_pc; - unsigned int sc_status; - unsigned int sc_fpc_csr; - unsigned int sc_fpc_eir; - unsigned int sc_used_math; - unsigned int sc_cause; - unsigned int sc_badvaddr; -}; - -struct sigcontext32 { - u32 sc_regmask; /* Unused */ - u32 sc_status; - u64 sc_pc; - u64 sc_regs[32]; - u64 sc_fpregs[32]; - u32 sc_ownedfp; /* Unused */ - u32 sc_fpc_csr; - u32 sc_fpc_eir; /* Unused */ - u32 sc_used_math; - u32 sc_ssflags; /* Unused */ - u64 sc_mdhi; - u64 sc_mdlo; - - u32 sc_cause; /* Unused */ - u32 sc_badvaddr; /* Unused */ - - u32 sc_sigset[4]; /* kernel's sigset_t */ -}; - -#endif /* _ASM_SIGCONTEXT_H */ diff --git a/include/asm-mips64/siginfo.h b/include/asm-mips64/siginfo.h deleted file mode 100644 index af5ea7fb287..00000000000 --- a/include/asm-mips64/siginfo.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 1999, 2001 Ralf Baechle - * Copyright (C) 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_SIGINFO_H -#define _ASM_SIGINFO_H - -/* This structure matches IRIX 32/n32 ABIs for binary compatibility but - has Linux extensions. */ - -#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4) -#define SI_PAD_SIZE ((SI_MAX_SIZE/sizeof(int)) - 4) -#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3) - -#define HAVE_ARCH_SIGINFO_T -#define HAVE_ARCH_SIGEVENT_T - -/* - * We duplicate the generic versions - is just borked - * by design ... - */ -#define HAVE_ARCH_COPY_SIGINFO -struct siginfo; - -#include - -typedef struct siginfo { - int si_signo; - int si_code; - int si_errno; - - union { - int _pad[SI_PAD_SIZE]; - - /* kill() */ - struct { - pid_t _pid; /* sender's pid */ - uid_t _uid; /* sender's uid */ - } _kill; - - /* SIGCHLD */ - struct { - pid_t _pid; /* which child */ - uid_t _uid; /* sender's uid */ - clock_t _utime; - int _status; /* exit code */ - clock_t _stime; - } _sigchld; - - /* IRIX SIGCHLD */ - struct { - pid_t _pid; /* which child */ - clock_t _utime; - int _status; /* exit code */ - clock_t _stime; - } _irix_sigchld; - - /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ - struct { - void *_addr; /* faulting insn/memory ref. */ - } _sigfault; - - /* SIGPOLL, SIGXFSZ (To do ...) */ - struct { - long _band; /* POLL_IN, POLL_OUT, POLL_MSG */ - int _fd; - } _sigpoll; - - /* POSIX.1b timers */ - struct { - timer_t _tid; /* timer id */ - int _overrun; /* overrun count */ - char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)]; - sigval_t _sigval; /* same as below */ - int _sys_private; /* not to be passed to user */ - } _timer; - - /* POSIX.1b signals */ - struct { - pid_t _pid; /* sender's pid */ - uid_t _uid; /* sender's uid */ - sigval_t _sigval; - } _rt; - - } _sifields; -} siginfo_t; - -#ifdef __KERNEL__ - -typedef union sigval32 { - int sival_int; - s32 sival_ptr; -} sigval_t32; - -typedef struct siginfo32 { - int si_signo; - int si_code; - int si_errno; - - union { - int _pad[SI_PAD_SIZE32]; - - /* kill() */ - struct { - __kernel_pid_t32 _pid; /* sender's pid */ - __kernel_uid_t32 _uid; /* sender's uid */ - } _kill; - - /* SIGCHLD */ - struct { - __kernel_pid_t32 _pid; /* which child */ - __kernel_uid_t32 _uid; /* sender's uid */ - __kernel_clock_t32 _utime; - int _status; /* exit code */ - __kernel_clock_t32 _stime; - } _sigchld; - - /* IRIX SIGCHLD */ - struct { - __kernel_pid_t32 _pid; /* which child */ - __kernel_clock_t32 _utime; - int _status; /* exit code */ - __kernel_clock_t32 _stime; - } _irix_sigchld; - - /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ - struct { - s32 _addr; /* faulting insn/memory ref. */ - } _sigfault; - - /* SIGPOLL, SIGXFSZ (To do ...) */ - struct { - int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ - int _fd; - } _sigpoll; - - /* POSIX.1b timers */ - struct { - unsigned int _timer1; - unsigned int _timer2; - } _timer; - - /* POSIX.1b signals */ - struct { - __kernel_pid_t32 _pid; /* sender's pid */ - __kernel_uid_t32 _uid; /* sender's uid */ - sigval_t32 _sigval; - } _rt; - - } _sifields; -} siginfo_t32; - -#endif /* __KERNEL__ */ - -/* - * si_code values - * Again these have been choosen to be IRIX compatible. - */ -#undef SI_ASYNCIO -#undef SI_TIMER -#undef SI_MESGQ -#define SI_ASYNCIO -2 /* sent by AIO completion */ -#define SI_TIMER __SI_CODE(__SI_TIMER,-3) /* sent by timer expiration */ -#define SI_MESGQ -4 /* sent by real time mesq state change */ - -/* - * sigevent definitions - * - * It seems likely that SIGEV_THREAD will have to be handled from - * userspace, libpthread transmuting it to SIGEV_SIGNAL, which the - * thread manager then catches and does the appropriate nonsense. - * However, everything is written out here so as to not get lost. - */ -#undef SIGEV_NONE -#undef SIGEV_SIGNAL -#undef SIGEV_THREAD -#define SIGEV_NONE 128 /* other notification: meaningless */ -#define SIGEV_SIGNAL 129 /* notify via signal */ -#define SIGEV_CALLBACK 130 /* ??? */ -#define SIGEV_THREAD 131 /* deliver via thread creation */ - -/* XXX This one isn't yet IRIX / ABI compatible. */ -typedef struct sigevent { - int sigev_notify; - sigval_t sigev_value; - int sigev_signo; - union { - int _pad[SIGEV_PAD_SIZE]; - int _tid; - - struct { - void (*_function)(sigval_t); - void *_attribute; /* really pthread_attr_t */ - } _sigev_thread; - } _sigev_un; -} sigevent_t; - -#ifdef __KERNEL__ - -/* - * Duplicated here because of braindamage ... - */ -#include - -static inline void copy_siginfo(struct siginfo *to, struct siginfo *from) -{ - if (from->si_code < 0) - memcpy(to, from, sizeof(*to)); - else - /* _sigchld is currently the largest know union member */ - memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld)); -} - -#endif - -#endif /* _ASM_SIGINFO_H */ diff --git a/include/asm-mips64/signal.h b/include/asm-mips64/signal.h deleted file mode 100644 index 9cb39bacb28..00000000000 --- a/include/asm-mips64/signal.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995 - 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_SIGNAL_H -#define _ASM_SIGNAL_H - -#include - -#define _NSIG 128 -#define _NSIG_BPW 64 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -#define SIGHUP 1 /* Hangup (POSIX). */ -#define SIGINT 2 /* Interrupt (ANSI). */ -#define SIGQUIT 3 /* Quit (POSIX). */ -#define SIGILL 4 /* Illegal instruction (ANSI). */ -#define SIGTRAP 5 /* Trace trap (POSIX). */ -#define SIGIOT 6 /* IOT trap (4.2 BSD). */ -#define SIGABRT SIGIOT /* Abort (ANSI). */ -#define SIGEMT 7 -#define SIGFPE 8 /* Floating-point exception (ANSI). */ -#define SIGKILL 9 /* Kill, unblockable (POSIX). */ -#define SIGBUS 10 /* BUS error (4.2 BSD). */ -#define SIGSEGV 11 /* Segmentation violation (ANSI). */ -#define SIGSYS 12 -#define SIGPIPE 13 /* Broken pipe (POSIX). */ -#define SIGALRM 14 /* Alarm clock (POSIX). */ -#define SIGTERM 15 /* Termination (ANSI). */ -#define SIGUSR1 16 /* User-defined signal 1 (POSIX). */ -#define SIGUSR2 17 /* User-defined signal 2 (POSIX). */ -#define SIGCHLD 18 /* Child status has changed (POSIX). */ -#define SIGCLD SIGCHLD /* Same as SIGCHLD (System V). */ -#define SIGPWR 19 /* Power failure restart (System V). */ -#define SIGWINCH 20 /* Window size change (4.3 BSD, Sun). */ -#define SIGURG 21 /* Urgent condition on socket (4.2 BSD). */ -#define SIGIO 22 /* I/O now possible (4.2 BSD). */ -#define SIGPOLL SIGIO /* Pollable event occurred (System V). */ -#define SIGSTOP 23 /* Stop, unblockable (POSIX). */ -#define SIGTSTP 24 /* Keyboard stop (POSIX). */ -#define SIGCONT 25 /* Continue (POSIX). */ -#define SIGTTIN 26 /* Background read from tty (POSIX). */ -#define SIGTTOU 27 /* Background write to tty (POSIX). */ -#define SIGVTALRM 28 /* Virtual alarm clock (4.2 BSD). */ -#define SIGPROF 29 /* Profiling alarm clock (4.2 BSD). */ -#define SIGXCPU 30 /* CPU limit exceeded (4.2 BSD). */ -#define SIGXFSZ 31 /* File size limit exceeded (4.2 BSD). */ - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX (_NSIG-1) - -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_ONSTACK 0x08000000 -#define SA_RESETHAND 0x80000000 -#define SA_RESTART 0x10000000 -#define SA_SIGINFO 0x00000008 -#define SA_NODEFER 0x40000000 -#define SA_NOCLDWAIT 0x00010000 -#define SA_NOCLDSTOP 0x00000001 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND -#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */ - -#define SA_RESTORER 0x04000000 /* Only for o32 compat code */ - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ flag is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x02000000 - -#endif /* __KERNEL__ */ - -#define SIG_BLOCK 1 /* for blocking signals */ -#define SIG_UNBLOCK 2 /* for unblocking signals */ -#define SIG_SETMASK 3 /* for setting the signal mask */ -#define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility: - set only the low 32 bit of the sigset. */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -/* Fake signal functions */ -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ - -struct sigaction { - unsigned int sa_flags; - __sighandler_t sa_handler; - sigset_t sa_mask; -}; - -struct k_sigaction { - struct sigaction sa; -}; - -/* IRIX compatible stack_t */ -typedef struct sigaltstack { - void *ss_sp; - size_t ss_size; - int ss_flags; -} stack_t; - -#ifdef __KERNEL__ -#include - -#define ptrace_signal_deliver(regs, cookie) do { } while (0) - -#endif /* __KERNEL__ */ - -#endif /* !defined (_ASM_SIGNAL_H) */ diff --git a/include/asm-mips64/smp.h b/include/asm-mips64/smp.h deleted file mode 100644 index f2cc964ff42..00000000000 --- a/include/asm-mips64/smp.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file "COPYING" in the main directory of this - * archive for more details. - * - * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com) - * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc. - * Copyright (C) 2000, 2001, 2002 Ralf Baechle - * Copyright (C) 2000, 2001 Broadcom Corporation - */ -#ifndef __ASM_SMP_H -#define __ASM_SMP_H - -#include - -#ifdef CONFIG_SMP - -#include -#include -#include - -#define smp_processor_id() (current_thread_info()->cpu) - -/* Map from cpu id to sequential logical cpu number. This will only - not be idempotent when cpus failed to come on-line. */ -extern int __cpu_number_map[NR_CPUS]; -#define cpu_number_map(cpu) __cpu_number_map[cpu] - -/* The reverse map from sequential logical cpu number to cpu id. */ -extern int __cpu_logical_map[NR_CPUS]; -#define cpu_logical_map(cpu) __cpu_logical_map[cpu] - -#define NO_PROC_ID (-1) - -struct call_data_struct { - void (*func)(void *); - void *info; - atomic_t started; - atomic_t finished; - int wait; -}; - -extern struct call_data_struct *call_data; - -#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ -#define SMP_CALL_FUNCTION 0x2 - -#if (NR_CPUS <= _MIPS_SZLONG) - -typedef unsigned long cpumask_t; - -#define CPUMASK_CLRALL(p) (p) = 0 -#define CPUMASK_SETB(p, bit) (p) |= 1UL << (bit) -#define CPUMASK_CLRB(p, bit) (p) &= ~(1UL << (bit)) -#define CPUMASK_TSTB(p, bit) ((p) & (1UL << (bit))) - -#elif (NR_CPUS <= 128) - -/* - * The foll should work till 128 cpus. - */ -#define CPUMASK_SIZE (NR_CPUS/_MIPS_SZLONG) -#define CPUMASK_INDEX(bit) ((bit) >> 6) -#define CPUMASK_SHFT(bit) ((bit) & 0x3f) - -typedef struct { - unsigned long _bits[CPUMASK_SIZE]; -} cpumask_t; - -#define CPUMASK_CLRALL(p) (p)._bits[0] = 0, (p)._bits[1] = 0 -#define CPUMASK_SETB(p, bit) (p)._bits[CPUMASK_INDEX(bit)] |= \ - (1UL << CPUMASK_SHFT(bit)) -#define CPUMASK_CLRB(p, bit) (p)._bits[CPUMASK_INDEX(bit)] &= \ - ~(1UL << CPUMASK_SHFT(bit)) -#define CPUMASK_TSTB(p, bit) ((p)._bits[CPUMASK_INDEX(bit)] & \ - (1UL << CPUMASK_SHFT(bit))) - -#else -#error cpumask macros only defined for 128p kernels -#endif - -extern cpumask_t phys_cpu_present_map; -extern cpumask_t cpu_online_map; - -#define cpu_possible(cpu) (phys_cpu_present_map & (1<<(cpu))) -#define cpu_online(cpu) (cpu_online_map & (1<<(cpu))) - -static inline unsigned int num_online_cpus(void) -{ - return hweight32(cpu_online_map); -} - -extern volatile unsigned long cpu_callout_map; -/* We don't mark CPUs online until __cpu_up(), so we need another measure */ -static inline int num_booting_cpus(void) -{ - return hweight32(cpu_callout_map); -} - -#endif /* CONFIG_SMP */ - -#endif /* __ASM_SMP_H */ diff --git a/include/asm-mips64/smplock.h b/include/asm-mips64/smplock.h deleted file mode 100644 index 86127491004..00000000000 --- a/include/asm-mips64/smplock.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Default SMP lock implementation - */ -#include -#include -#include - -extern spinlock_t kernel_flag; - -#ifdef CONFIG_SMP -#define kernel_locked() spin_is_locked(&kernel_flag) -#else -#ifdef CONFIG_PREEMPT -#define kernel_locked() preempt_count() -#else -#define kernel_locked() 1 -#endif -#endif - -/* - * Release global kernel lock and global interrupt lock - */ -#define release_kernel_lock(task) \ -do { \ - if (unlikely(task->lock_depth >= 0)) \ - spin_unlock(&kernel_flag); \ -} while (0) - -/* - * Re-acquire the kernel lock - */ -#define reacquire_kernel_lock(task) \ -do { \ - if (unlikely(task->lock_depth >= 0)) \ - spin_lock(&kernel_flag); \ -} while (0) - - -/* - * Getting the big kernel lock. - * - * This cannot happen asynchronously, - * so we only need to worry about other - * CPU's. - */ -static __inline__ void lock_kernel(void) -{ -#ifdef CONFIG_PREEMPT - if (current->lock_depth == -1) - spin_lock(&kernel_flag); - ++current->lock_depth; -#else - - if (!++current->lock_depth) - spin_lock(&kernel_flag); -#endif -} - -static __inline__ void unlock_kernel(void) -{ - if (--current->lock_depth < 0) - spin_unlock(&kernel_flag); -} diff --git a/include/asm-mips64/sni.h b/include/asm-mips64/sni.h deleted file mode 100644 index 9c9fcdd2220..00000000000 --- a/include/asm-mips64/sni.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * SNI specific definitions - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1998 by Ralf Baechle - */ -#ifndef __ASM_SNI_H -#define __ASM_SNI_H - -#define SNI_PORT_BASE 0xb4000000 -#define IO_SPACE_BASE 0x9000000000000000 -#define IO_SPACE_LIMIT 0xffffffff - -/* - * ASIC PCI registers for little endian configuration. - */ -#ifndef __MIPSEL__ -#error "Fix me for big endian" -#endif -#define PCIMT_UCONF 0xbfff0000 -#define PCIMT_IOADTIMEOUT2 0xbfff0008 -#define PCIMT_IOMEMCONF 0xbfff0010 -#define PCIMT_IOMMU 0xbfff0018 -#define PCIMT_IOADTIMEOUT1 0xbfff0020 -#define PCIMT_DMAACCESS 0xbfff0028 -#define PCIMT_DMAHIT 0xbfff0030 -#define PCIMT_ERRSTATUS 0xbfff0038 -#define PCIMT_ERRADDR 0xbfff0040 -#define PCIMT_SYNDROME 0xbfff0048 -#define PCIMT_ITPEND 0xbfff0050 -#define IT_INT2 0x01 -#define IT_INTD 0x02 -#define IT_INTC 0x04 -#define IT_INTB 0x08 -#define IT_INTA 0x10 -#define IT_EISA 0x20 -#define IT_SCSI 0x40 -#define IT_ETH 0x80 -#define PCIMT_IRQSEL 0xbfff0058 -#define PCIMT_TESTMEM 0xbfff0060 -#define PCIMT_ECCREG 0xbfff0068 -#define PCIMT_CONFIG_ADDRESS 0xbfff0070 -#define PCIMT_ASIC_ID 0xbfff0078 /* read */ -#define PCIMT_SOFT_RESET 0xbfff0078 /* write */ -#define PCIMT_PIA_OE 0xbfff0080 -#define PCIMT_PIA_DATAOUT 0xbfff0088 -#define PCIMT_PIA_DATAIN 0xbfff0090 -#define PCIMT_CACHECONF 0xbfff0098 -#define PCIMT_INVSPACE 0xbfff00a0 -#define PCIMT_PCI_CONF 0xbfff0100 - -/* - * Data port for the PCI bus. - */ -#define PCIMT_CONFIG_DATA 0xb4000cfc - -/* - * Board specific registers - */ -#define PCIMT_CSMSR 0xbfd00000 -#define PCIMT_CSSWITCH 0xbfd10000 -#define PCIMT_CSITPEND 0xbfd20000 -#define PCIMT_AUTO_PO_EN 0xbfd30000 -#define PCIMT_CLR_TEMP 0xbfd40000 -#define PCIMT_AUTO_PO_DIS 0xbfd50000 -#define PCIMT_EXMSR 0xbfd60000 -#define PCIMT_UNUSED1 0xbfd70000 -#define PCIMT_CSWCSM 0xbfd80000 -#define PCIMT_UNUSED2 0xbfd90000 -#define PCIMT_CSLED 0xbfda0000 -#define PCIMT_CSMAPISA 0xbfdb0000 -#define PCIMT_CSRSTBP 0xbfdc0000 -#define PCIMT_CLRPOFF 0xbfdd0000 -#define PCIMT_CSTIMER 0xbfde0000 -#define PCIMT_PWDN 0xbfdf0000 - -/* - * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned - * to the other interrupts generated by ASIC PCI. - */ -#define PCIMT_KEYBOARD_IRQ 1 -#define PCIMT_IRQ_INT2 16 /* What is that? */ -#define PCIMT_IRQ_INTD 17 -#define PCIMT_IRQ_INTC 18 -#define PCIMT_IRQ_INTB 19 -#define PCIMT_IRQ_INTA 20 -#define PCIMT_IRQ_EISA 21 -#define PCIMT_IRQ_SCSI 22 -#define PCIMT_IRQ_ETHERNET 23 -#define PCIMT_IRQ_TEMPERATURE 24 -#define PCIMT_IRQ_EISA_NMI 25 -#define PCIMT_IRQ_POWER_OFF 26 -#define PCIMT_IRQ_BUTTON 27 - -/* - * Base address for the mapped 16mb EISA bus segment. - */ -#define PCIMT_EISA_BASE 0xb0000000 - -/* PCI EISA Interrupt acknowledge */ -#define PCIMT_INT_ACKNOWLEDGE 0xba000000 - -#endif /* __ASM_SNI_H */ diff --git a/include/asm-mips64/socket.h b/include/asm-mips64/socket.h deleted file mode 100644 index df9fcb53d71..00000000000 --- a/include/asm-mips64/socket.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1999, 2000, 2001 Ralf Baechle - * Copyright (C) 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_SOCKET_H -#define _ASM_SOCKET_H - -#include - -/* - * For setsockopt(2) - * - * This defines are ABI conformant as far as Linux supports these ... - */ -#define SOL_SOCKET 0xffff - -#define SO_DEBUG 0x0001 /* Record debugging information. */ -#define SO_REUSEADDR 0x0004 /* Allow reuse of local addresses. */ -#define SO_KEEPALIVE 0x0008 /* Keep connections alive and send - SIGPIPE when they die. */ -#define SO_DONTROUTE 0x0010 /* Don't do local routing. */ -#define SO_BROADCAST 0x0020 /* Allow transmission of - broadcast messages. */ -#define SO_LINGER 0x0080 /* Block on close of a reliable - socket to transmit pending data. */ -#define SO_OOBINLINE 0x0100 /* Receive out-of-band data in-band. */ -#if 0 -To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ -#endif - -#define SO_TYPE 0x1008 /* Compatible name for SO_STYLE. */ -#define SO_STYLE SO_TYPE /* Synonym */ -#define SO_ERROR 0x1007 /* get error status and clear */ -#define SO_SNDBUF 0x1001 /* Send buffer size. */ -#define SO_RCVBUF 0x1002 /* Receive buffer. */ -#define SO_SNDLOWAT 0x1003 /* send low-water mark */ -#define SO_RCVLOWAT 0x1004 /* receive low-water mark */ -#define SO_SNDTIMEO 0x1005 /* send timeout */ -#define SO_RCVTIMEO 0x1006 /* receive timeout */ -#define SO_ACCEPTCONN 0x1009 - -/* linux-specific, might as well be the same as on i386 */ -#define SO_NO_CHECK 11 -#define SO_PRIORITY 12 -#define SO_BSDCOMPAT 14 - -#define SO_PASSCRED 17 -#define SO_PEERCRED 18 - -/* Security levels - as per NRL IPv6 - don't actually do anything */ -#define SO_SECURITY_AUTHENTICATION 22 -#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -#define SO_SECURITY_ENCRYPTION_NETWORK 24 - -#define SO_BINDTODEVICE 25 - -/* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 - -#define SO_PEERNAME 28 -#define SO_TIMESTAMP 29 -#define SCM_TIMESTAMP SO_TIMESTAMP - -/* Nast libc5 fixup - bletch */ -#if defined(__KERNEL__) -/* Socket types. */ -#define SOCK_DGRAM 1 /* datagram (conn.less) socket */ -#define SOCK_STREAM 2 /* stream (connection) socket */ -#define SOCK_RAW 3 /* raw socket */ -#define SOCK_RDM 4 /* reliably-delivered message */ -#define SOCK_SEQPACKET 5 /* sequential packet socket */ -#define SOCK_PACKET 10 /* linux specific way of */ - /* getting packets at the dev */ - /* level. For writing rarp and */ - /* other similar things on the */ - /* user level. */ -#define SOCK_MAX (SOCK_PACKET+1) -#endif - -#endif /* _ASM_SOCKET_H */ diff --git a/include/asm-mips64/sockios.h b/include/asm-mips64/sockios.h deleted file mode 100644 index d691c0bcee5..00000000000 --- a/include/asm-mips64/sockios.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999 by Ralf Baechle - */ -#ifndef _ASM_SOCKIOS_H -#define _ASM_SOCKIOS_H - -#include - -/* Socket-level I/O control calls. */ -#define FIOGETOWN _IOR('f', 123, int) -#define FIOSETOWN _IOW('f', 124, int) - -#define SIOCATMARK _IOR('s', 7, int) -#define SIOCSPGRP _IOW('s', 8, pid_t) -#define SIOCGPGRP _IOR('s', 9, pid_t) - -#define SIOCGSTAMP 0x8906 /* Get stamp - linux-specific */ - -#endif /* _ASM_SOCKIOS_H */ diff --git a/include/asm-mips64/softirq.h b/include/asm-mips64/softirq.h deleted file mode 100644 index d944be956a2..00000000000 --- a/include/asm-mips64/softirq.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __ASM_SOFTIRQ_H -#define __ASM_SOFTIRQ_H - -#include -#include - -#define local_bh_disable() \ - do { preempt_count() += SOFTIRQ_OFFSET; barrier(); } while (0) -#define __local_bh_enable() \ - do { barrier(); preempt_count() -= SOFTIRQ_OFFSET; } while (0) - -#define local_bh_enable() \ -do { \ - __local_bh_enable(); \ - if (unlikely(!in_interrupt() && softirq_pending(smp_processor_id()))) \ - do_softirq(); \ - preempt_check_resched(); \ -} while (0) - -#endif /* __ASM_SOFTIRQ_H */ diff --git a/include/asm-mips64/spinlock.h b/include/asm-mips64/spinlock.h deleted file mode 100644 index 4a46e61ba37..00000000000 --- a/include/asm-mips64/spinlock.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_SPINLOCK_H -#define _ASM_SPINLOCK_H - -/* - * Your basic SMP spinlocks, allowing only a single CPU anywhere - */ - -typedef struct { - volatile unsigned int lock; -} spinlock_t; - -#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } - -#define spin_lock_init(x) do { (x)->lock = 0; } while(0) - -#define spin_is_locked(x) ((x)->lock != 0) -#define spin_unlock_wait(x) do { barrier(); } while ((x)->lock) - -/* - * Simple spin lock operations. There are two variants, one clears IRQ's - * on the local processor, one does not. - * - * We make no fairness assumptions. They have a cost. - */ - -static inline void _raw_spin_lock(spinlock_t *lock) -{ - unsigned int tmp; - - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# spin_lock\n" - "1:\tll\t%1, %2\n\t" - "bnez\t%1, 1b\n\t" - " li\t%1, 1\n\t" - "sc\t%1, %0\n\t" - "beqz\t%1, 1b\n\t" - " sync\n\t" - ".set\treorder" - : "=m" (lock->lock), "=&r" (tmp) - : "m" (lock->lock) - : "memory"); -} - -static inline void _raw_spin_unlock(spinlock_t *lock) -{ - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# spin_unlock\n\t" - "sync\n\t" - "sw\t$0, %0\n\t" - ".set\treorder" - : "=m" (lock->lock) - : "m" (lock->lock) - : "memory"); -} - -static inline unsigned int _raw_spin_trylock(spinlock_t *lock) -{ - unsigned int temp, res; - - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# spin_trylock\n\t" - "1:\tll\t%0, %3\n\t" - "ori\t%2, %0, 1\n\t" - "sc\t%2, %1\n\t" - "beqz\t%2, 1b\n\t" - " andi\t%2, %0, 1\n\t" - ".set\treorder" - : "=&r" (temp), "=m" (lock->lock), "=&r" (res) - : "m" (lock->lock) - : "memory"); - - return res == 0; -} - -/* - * Read-write spinlocks, allowing multiple readers but only one writer. - * - * NOTE! it is quite common to have readers in interrupts but no interrupt - * writers. For those circumstances we can "mix" irq-safe locks - any writer - * needs to get a irq-safe write-lock, but readers can get non-irqsafe - * read-locks. - */ - -typedef struct { - volatile unsigned int lock; -} rwlock_t; - -#define RW_LOCK_UNLOCKED (rwlock_t) { 0 } - -#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0) - -#define rwlock_is_locked(x) ((x)->lock) - -static inline void _raw_read_lock(rwlock_t *rw) -{ - unsigned int tmp; - - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# read_lock\n" - "1:\tll\t%1, %2\n\t" - "bltz\t%1, 1b\n\t" - " addu\t%1, 1\n\t" - "sc\t%1, %0\n\t" - "beqz\t%1, 1b\n\t" - " sync\n\t" - ".set\treorder" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); -} - -/* Note the use of sub, not subu which will make the kernel die with an - overflow exception if we ever try to unlock an rwlock that is already - unlocked or is being held by a writer. */ -static inline void _raw_read_unlock(rwlock_t *rw) -{ - unsigned int tmp; - - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# read_unlock\n" - "1:\tll\t%1, %2\n\t" - "sub\t%1, 1\n\t" - "sc\t%1, %0\n\t" - "beqz\t%1, 1b\n\t" - " sync\n\t" - ".set\treorder" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); -} - -static inline void _raw_write_lock(rwlock_t *rw) -{ - unsigned int tmp; - - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# write_lock\n" - "1:\tll\t%1, %2\n\t" - "bnez\t%1, 1b\n\t" - " lui\t%1, 0x8000\n\t" - "sc\t%1, %0\n\t" - "beqz\t%1, 1b\n\t" - " sync\n\t" - ".set\treorder" - : "=m" (rw->lock), "=&r" (tmp) - : "m" (rw->lock) - : "memory"); -} - -static inline void _raw_write_unlock(rwlock_t *rw) -{ - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# write_unlock\n\t" - "sync\n\t" - "sw\t$0, %0\n\t" - ".set\treorder" - : "=m" (rw->lock) - : "m" (rw->lock) - : "memory"); -} - -#endif /* _ASM_SPINLOCK_H */ diff --git a/include/asm-mips64/stackframe.h b/include/asm-mips64/stackframe.h deleted file mode 100644 index 4f2d87cdd52..00000000000 --- a/include/asm-mips64/stackframe.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle - * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef __ASM_STACKFRAME_H -#define __ASM_STACKFRAME_H - -#include -#include - -#include -#include -#include -#include - -#ifdef __ASSEMBLY__ - - .macro SAVE_AT - .set push - .set noat - sd $1, PT_R1(sp) - .set pop - .endm - - .macro SAVE_TEMP - mfhi v1 - sd $8, PT_R8(sp) - sd $9, PT_R9(sp) - sd v1, PT_HI(sp) - mflo v1 - sd $10, PT_R10(sp) - sd $11, PT_R11(sp) - sd v1, PT_LO(sp) - sd $12, PT_R12(sp) - sd $13, PT_R13(sp) - sd $14, PT_R14(sp) - sd $15, PT_R15(sp) - sd $24, PT_R24(sp) - .endm - - .macro SAVE_STATIC - sd $16, PT_R16(sp) - sd $17, PT_R17(sp) - sd $18, PT_R18(sp) - sd $19, PT_R19(sp) - sd $20, PT_R20(sp) - sd $21, PT_R21(sp) - sd $22, PT_R22(sp) - sd $23, PT_R23(sp) - sd $30, PT_R30(sp) - .endm - -#ifdef CONFIG_SMP - .macro get_saved_sp /* SMP variation */ - dmfc0 k1, CP0_CONTEXT - dsra k1, 23 - lui k0, %hi(pgd_current) - daddiu k0, %lo(pgd_current) - dsubu k1, k0 - lui k0, %hi(kernelsp) - daddu k1, k0 - ld k1, %lo(kernelsp)(k1) - .endm - - .macro set_saved_sp stackp temp temp2 - lw \temp, TI_CPU(gp) - dsll \temp, 3 - lui \temp2, %hi(kernelsp) - daddu \temp, \temp2 - sd \stackp, %lo(kernelsp)(\temp) - .endm -#else - .macro get_saved_sp /* Uniprocessor variation */ - lui k1, %hi(kernelsp) - ld k1, %lo(kernelsp)(k1) - .endm - - .macro set_saved_sp stackp temp temp2 - sd \stackp, kernelsp - .endm -#endif - -#ifdef CONFIG_PREEMPT - .macro bump_lock_count - lw t0, TI_PRE_COUNT($28) - addiu t0, t0, 1 - sw t0, TI_PRE_COUNT($28) - .endm -#else - .macro bump_lock_count - .endm -#endif - - .macro SAVE_SOME - .set push - .set reorder - mfc0 k0, CP0_STATUS - sll k0, 3 /* extract cu0 bit */ - .set noreorder - bltz k0, 8f - move k1, sp - .set reorder - /* Called from user mode, new stack. */ - get_saved_sp -8: move k0, sp - dsubu sp, k1, PT_SIZE - sd k0, PT_R29(sp) - sd $3, PT_R3(sp) - sd $0, PT_R0(sp) - mfc0 v1, CP0_STATUS - sd $2, PT_R2(sp) - sd v1, PT_STATUS(sp) - sd $4, PT_R4(sp) - mfc0 v1, CP0_CAUSE - sd $5, PT_R5(sp) - sd v1, PT_CAUSE(sp) - sd $6, PT_R6(sp) - dmfc0 v1, CP0_EPC - sd $7, PT_R7(sp) - sd v1, PT_EPC(sp) - sd $25, PT_R25(sp) - sd $28, PT_R28(sp) - sd $31, PT_R31(sp) - ori $28, sp, 0x3fff - xori $28, 0x3fff - bump_lock_count - .set pop - .endm - - .macro SAVE_ALL - SAVE_SOME - SAVE_AT - SAVE_TEMP - SAVE_STATIC - .endm - - .macro RESTORE_AT - .set push - .set noat - ld $1, PT_R1(sp) - .set pop - .endm - - .macro RESTORE_SP - ld sp, PT_R29(sp) - .endm - - .macro RESTORE_TEMP - ld $24, PT_LO(sp) - ld $8, PT_R8(sp) - ld $9, PT_R9(sp) - mtlo $24 - ld $24, PT_HI(sp) - ld $10, PT_R10(sp) - ld $11, PT_R11(sp) - mthi $24 - ld $12, PT_R12(sp) - ld $13, PT_R13(sp) - ld $14, PT_R14(sp) - ld $15, PT_R15(sp) - ld $24, PT_R24(sp) - .endm - - .macro RESTORE_STATIC - ld $16, PT_R16(sp) - ld $17, PT_R17(sp) - ld $18, PT_R18(sp) - ld $19, PT_R19(sp) - ld $20, PT_R20(sp) - ld $21, PT_R21(sp) - ld $22, PT_R22(sp) - ld $23, PT_R23(sp) - ld $30, PT_R30(sp) - .endm - - .macro RESTORE_SOME - .set push - .set reorder - mfc0 t0, CP0_STATUS - .set pop - ori t0, 0x1f - xori t0, 0x1f - mtc0 t0, CP0_STATUS - li v1, 0xff00 - and t0, v1 - ld v0, PT_STATUS(sp) - nor v1, $0, v1 - and v0, v1 - or v0, t0 - mtc0 v0, CP0_STATUS - ld v1, PT_EPC(sp) - dmtc0 v1, CP0_EPC - ld $31, PT_R31(sp) - ld $28, PT_R28(sp) - ld $25, PT_R25(sp) - ld $7, PT_R7(sp) - ld $6, PT_R6(sp) - ld $5, PT_R5(sp) - ld $4, PT_R4(sp) - ld $3, PT_R3(sp) - ld $2, PT_R2(sp) - .endm - - .macro RESTORE_SP_AND_RET - ld sp, PT_R29(sp) - .set mips3 - eret - .set mips0 - .endm - - .macro RESTORE_ALL - RESTORE_SOME - RESTORE_AT - RESTORE_TEMP - RESTORE_STATIC - RESTORE_SP - .endm - - .macro RESTORE_ALL_AND_RET - RESTORE_SOME - RESTORE_AT - RESTORE_TEMP - RESTORE_STATIC - RESTORE_SP_AND_RET - .endm - -/* - * Move to kernel mode and disable interrupts. - * Set cp0 enable bit as sign that we're running on the kernel stack - */ - .macro CLI - mfc0 t0, CP0_STATUS - li t1, ST0_CU0|0x1f - or t0, t1 - xori t0, 0x1f - mtc0 t0, CP0_STATUS - .endm - -/* - * Move to kernel mode and enable interrupts. - * Set cp0 enable bit as sign that we're running on the kernel stack - */ - .macro STI - mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | 0x1f - or t0, t1 - xori t0, 0x1e - mtc0 t0, CP0_STATUS - .endm - -/* - * Just move to kernel mode and leave interrupts as they are. - * Set cp0 enable bit as sign that we're running on the kernel stack - */ - .macro KMODE - mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | 0x1e - or t0, t1 - xori t0, 0x1e - mtc0 t0, CP0_STATUS - .endm - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_STACKFRAME_H */ diff --git a/include/asm-mips64/stat.h b/include/asm-mips64/stat.h deleted file mode 100644 index 30699d409a7..00000000000 --- a/include/asm-mips64/stat.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999, 2000 Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_STAT_H -#define _ASM_STAT_H - -#include - -/* The memory layout is the same as of struct stat64 of the 32-bit kernel. */ -struct stat { - dev_t st_dev; - unsigned int st_pad0[3]; /* Reserved for st_dev expansion */ - - unsigned long st_ino; - - mode_t st_mode; - nlink_t st_nlink; - - uid_t st_uid; - gid_t st_gid; - - dev_t st_rdev; - unsigned int st_pad1[3]; /* Reserved for st_rdev expansion */ - - off_t st_size; - - /* - * Actually this should be timestruc_t st_atime, st_mtime and st_ctime - * but we don't have it under Linux. - */ - unsigned int st_atime; - unsigned int st_atime_nsec; - - unsigned int st_mtime; - unsigned int st_mtime_nsec; - - unsigned int st_ctime; - unsigned int st_ctime_nsec; - - unsigned int st_blksize; - unsigned int st_pad2; - - unsigned long st_blocks; -}; - -#define STAT_HAVE_NSEC 1 - -#endif /* _ASM_STAT_H */ diff --git a/include/asm-mips64/statfs.h b/include/asm-mips64/statfs.h deleted file mode 100644 index ae1d46966d2..00000000000 --- a/include/asm-mips64/statfs.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999 by Ralf Baechle - */ -#ifndef _ASM_STATFS_H -#define _ASM_STATFS_H - -#include - -#ifndef __KERNEL_STRICT_NAMES - -#include - -typedef __kernel_fsid_t fsid_t; - -#endif - -struct statfs { - long f_type; -#define f_fstyp f_type - long f_bsize; - long f_frsize; /* Fragment size - unsupported */ - long f_blocks; - long f_bfree; - long f_files; - long f_ffree; - - /* Linux specials */ - long f_bavail; - __kernel_fsid_t f_fsid; - long f_namelen; - long f_spare[6]; -}; - -struct statfs64 { /* Same as struct statfs */ - long f_type; - long f_bsize; - long f_frsize; /* Fragment size - unsupported */ - long f_blocks; - long f_bfree; - long f_files; - long f_ffree; - - /* Linux specials */ - long f_bavail; - __kernel_fsid_t f_fsid; - long f_namelen; - long f_spare[6]; -}; - -#endif /* _ASM_STATFS_H */ diff --git a/include/asm-mips64/string.h b/include/asm-mips64/string.h deleted file mode 100644 index 6fe105f985f..00000000000 --- a/include/asm-mips64/string.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1994 - 2000 by Ralf Baechle - * Copyright (c) 2000 by Silicon Graphics, Inc. - */ -#ifndef _ASM_STRING_H -#define _ASM_STRING_H - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *__s, int __c, size_t __count); - -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *__to, __const__ void *__from, size_t __n); - -#define __HAVE_ARCH_MEMMOVE -extern void *memmove(void *__dest, __const__ void *__src, size_t __n); - -/* Don't build bcopy at all ... */ -#define __HAVE_ARCH_BCOPY - -#endif /* _ASM_STRING_H */ diff --git a/include/asm-mips64/suspend.h b/include/asm-mips64/suspend.h deleted file mode 100644 index 2562f8f9be0..00000000000 --- a/include/asm-mips64/suspend.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_SUSPEND_H -#define __ASM_SUSPEND_H - -/* Somewhen... Maybe :-) */ - -#endif /* __ASM_SUSPEND_H */ diff --git a/include/asm-mips64/sysmips.h b/include/asm-mips64/sysmips.h deleted file mode 100644 index 75744d5a74f..00000000000 --- a/include/asm-mips64/sysmips.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1999 by Ralf Baechle - * Copyright 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_SYSMIPS_H -#define _ASM_SYSMIPS_H - -/* - * Commands for the sysmips(2) call - * - * sysmips(2) is deprecated - though some existing software uses it. - * We only support the following commands. - */ -#define SETNAME 1 /* set hostname */ -#define FLUSH_CACHE 3 /* writeback and invalidate caches */ -#define MIPS_FIXADE 7 /* control address error fixing */ -#define MIPS_RDNVRAM 10 /* read NVRAM */ -#define MIPS_ATOMIC_SET 2001 /* atomically set variable */ - -#endif /* _ASM_SYSMIPS_H */ diff --git a/include/asm-mips64/system.h b/include/asm-mips64/system.h deleted file mode 100644 index f718d181f6a..00000000000 --- a/include/asm-mips64/system.h +++ /dev/null @@ -1,356 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999 by Ralf Baechle - * Modified further for R[236]000 by Paul M. Antoine, 1996 - * Copyright (C) 1999 Silicon Graphics - */ -#ifndef _ASM_SYSTEM_H -#define _ASM_SYSTEM_H - -#include -#include - -#include - -#include -#include - -__asm__ ( - ".macro\tlocal_irq_enable\n\t" - ".set\tpush\n\t" - ".set\treorder\n\t" - ".set\tnoat\n\t" - "mfc0\t$1,$12\n\t" - "ori\t$1,0x1f\n\t" - "xori\t$1,0x1e\n\t" - "mtc0\t$1,$12\n\t" - ".set\tpop\n\t" - ".endm"); - -static inline void local_irq_enable(void) -{ - __asm__ __volatile__( - "local_irq_enable" - : /* no outputs */ - : /* no inputs */ - : "memory"); -} - -/* - * For cli() we have to insert nops to make sure that the new value - * has actually arrived in the status register before the end of this - * macro. - * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs - * no nops at all. - */ -__asm__ ( - ".macro\tlocal_irq_disable\n\t" - ".set\tpush\n\t" - ".set\tnoat\n\t" - "mfc0\t$1,$12\n\t" - "ori\t$1,1\n\t" - "xori\t$1,1\n\t" - ".set\tnoreorder\n\t" - "mtc0\t$1,$12\n\t" - "sll\t$0, $0, 1\t\t\t# nop\n\t" - "sll\t$0, $0, 1\t\t\t# nop\n\t" - "sll\t$0, $0, 1\t\t\t# nop\n\t" - ".set\tpop\n\t" - ".endm"); - -static inline void local_irq_disable(void) -{ - __asm__ __volatile__( - "local_irq_disable" - : /* no outputs */ - : /* no inputs */ - : "memory"); -} - -__asm__ ( - ".macro\tlocal_save_flags flags\n\t" - ".set\tpush\n\t" - ".set\treorder\n\t" - "mfc0\t\\flags, $12\n\t" - ".set\tpop\n\t" - ".endm"); - -#define local_save_flags(x) \ -__asm__ __volatile__( \ - "local_save_flags %0" \ - : "=r" (x)) - -__asm__ ( - ".macro\tlocal_irq_save result\n\t" - ".set\tpush\n\t" - ".set\treorder\n\t" - ".set\tnoat\n\t" - "mfc0\t\\result, $12\n\t" - "ori\t$1, \\result, 1\n\t" - "xori\t$1, 1\n\t" - ".set\tnoreorder\n\t" - "mtc0\t$1, $12\n\t" - "sll\t$0, $0, 1\t\t\t# nop\n\t" - "sll\t$0, $0, 1\t\t\t# nop\n\t" - "sll\t$0, $0, 1\t\t\t# nop\n\t" - ".set\tpop\n\t" - ".endm"); - -#define local_irq_save(x) \ -__asm__ __volatile__( \ - "local_irq_save\t%0" \ - : "=r" (x) \ - : /* no inputs */ \ - : "memory") - -__asm__(".macro\tlocal_irq_restore flags\n\t" - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "mfc0\t$1, $12\n\t" - "andi\t\\flags, 1\n\t" - "ori\t$1, 1\n\t" - "xori\t$1, 1\n\t" - "or\t\\flags, $1\n\t" - "mtc0\t\\flags, $12\n\t" - "sll\t$0, $0, 1\t\t\t# nop\n\t" - "sll\t$0, $0, 1\t\t\t# nop\n\t" - "sll\t$0, $0, 1\t\t\t# nop\n\t" - ".set\tat\n\t" - ".set\treorder\n\t" - ".endm"); - -#define local_irq_restore(flags) \ -do { \ - unsigned long __tmp1; \ - \ - __asm__ __volatile__( \ - "local_irq_restore\t%0" \ - : "=r" (__tmp1) \ - : "0" (flags) \ - : "memory"); \ -} while(0) - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - !(flags & 1); \ -}) - -/* - * read_barrier_depends - Flush all pending reads that subsequents reads - * depend on. - * - * No data-dependent reads from memory-like regions are ever reordered - * over this barrier. All reads preceding this primitive are guaranteed - * to access memory (but not necessarily other CPUs' caches) before any - * reads following this primitive that depend on the data return by - * any of the preceding reads. This primitive is much lighter weight than - * rmb() on most CPUs, and is never heavier weight than is - * rmb(). - * - * These ordering constraints are respected by both the local CPU - * and the compiler. - * - * Ordering is not guaranteed by anything other than these primitives, - * not even by data dependencies. See the documentation for - * memory_barrier() for examples and URLs to more information. - * - * For example, the following code would force ordering (the initial - * value of "a" is zero, "b" is one, and "p" is "&a"): - * - * - * CPU 0 CPU 1 - * - * b = 2; - * memory_barrier(); - * p = &b; q = p; - * read_barrier_depends(); - * d = *q; - * - * - * because the read of "*q" depends on the read of "p" and these - * two reads are separated by a read_barrier_depends(). However, - * the following code, with the same initial values for "a" and "b": - * - * - * CPU 0 CPU 1 - * - * a = 2; - * memory_barrier(); - * b = 3; y = b; - * read_barrier_depends(); - * x = a; - * - * - * does not enforce ordering, since there is no data dependency between - * the read of "a" and the read of "b". Therefore, on some CPUs, such - * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() - * in cases like thiswhere there are no data dependencies. - */ - -#define read_barrier_depends() do { } while(0) - -#ifdef CONFIG_CPU_HAS_SYNC -#define __sync() \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - "sync\n\t" \ - ".set pop" \ - : /* no output */ \ - : /* no input */ \ - : "memory") -#else -#define __sync() do { } while(0) -#endif - -#define __fast_iob() \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - "lw $0,%0\n\t" \ - "nop\n\t" \ - ".set pop" \ - : /* no output */ \ - : "m" (*(int *)KSEG1) \ - : "memory") - -#define fast_wmb() __sync() -#define fast_rmb() __sync() -#define fast_mb() __sync() -#define fast_iob() \ - do { \ - __sync(); \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - "lw $0,%0\n\t" \ - "nop\n\t" \ - ".set pop" \ - : /* no output */ \ - : "m" (*(int *)KSEG1) \ - : "memory"); \ - } while (0) - -#define wmb() fast_wmb() -#define rmb() fast_rmb() -#define mb() fast_mb() -#define iob() fast_iob() - -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_read_barrier_depends() read_barrier_depends() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) -#endif - -#define set_mb(var, value) \ -do { var = value; mb(); } while (0) - -#define set_wmb(var, value) \ -do { var = value; wmb(); } while (0) - -/* - * switch_to(n) should switch tasks to task nr n, first - * checking that n isn't the current task, in which case it does nothing. - */ -extern asmlinkage void *resume(void *last, void *next, void *next_ti); - -struct task_struct; - -#define switch_to(prev,next,last) \ -do { \ - (last) = resume(prev, next, next->thread_info); \ -} while(0) - -static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) -{ - unsigned long dummy; - - __asm__ __volatile__( - ".set\tpush\t\t\t\t# xchg_u32\n\t" - ".set\tnoreorder\n\t" - ".set\tnomacro\n\t" - "ll\t%0, %3\n" - "1:\tmove\t%2, %z4\n\t" - "sc\t%2, %1\n\t" - "beqzl\t%2, 1b\n\t" - " ll\t%0, %3\n\t" - "sync\n\t" - ".set\tpop" - : "=&r" (val), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - - return val; -} - -static __inline__ unsigned long xchg_u64(volatile int * m, unsigned long val) -{ - unsigned long dummy; - - __asm__ __volatile__( - ".set\tpush\t\t\t\t# xchg_u64\n\t" - ".set\tnoreorder\n\t" - ".set\tnomacro\n\t" - "lld\t%0, %3\n" - "1:\tmove\t%2, %z4\n\t" - "scd\t%2, %1\n\t" - "beqzl\t%2, 1b\n\t" - " lld\t%0, %3\n\t" - "sync\n\t" - ".set\tpop" - : "=&r" (val), "=m" (*m), "=&r" (dummy) - : "R" (*m), "Jr" (val) - : "memory"); - - return val; -} - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -#define tas(ptr) (xchg((ptr),1)) - - -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, - int size) -{ - switch (size) { - case 4: - return xchg_u32(ptr, x); - case 8: - return xchg_u64(ptr, x); - } - return x; -} - -extern void *set_except_vector(int n, void *addr); -extern void per_cpu_trap_init(void); - -extern void __die(const char *, struct pt_regs *, const char *file, - const char *func, unsigned long line) __attribute__((noreturn)); -extern void __die_if_kernel(const char *, struct pt_regs *, const char *file, - const char *func, unsigned long line); - -#define die(msg, regs) \ - __die(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__) -#define die_if_kernel(msg, regs) \ - __die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__) - -extern int serial_console; -extern int stop_a_enabled; - -static __inline__ int con_is_present(void) -{ - return serial_console ? 0 : 1; -} - -#endif /* _ASM_SYSTEM_H */ diff --git a/include/asm-mips64/termbits.h b/include/asm-mips64/termbits.h deleted file mode 100644 index 71b712b9c9a..00000000000 --- a/include/asm-mips64/termbits.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1999, 2001 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - */ -#ifndef _ASM_TERMBITS_H -#define _ASM_TERMBITS_H - -#include - -typedef unsigned char cc_t; -#if (_MIPS_SZLONG == 32) -typedef unsigned long speed_t; -typedef unsigned long tcflag_t; -#endif -#if (_MIPS_SZLONG == 64) -typedef __u32 speed_t; -typedef __u32 tcflag_t; -#endif - -/* - * The ABI says nothing about NCC but seems to use NCCS as - * replacement for it in struct termio - */ -#define NCCS 23 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -/* c_cc characters */ -#define VINTR 0 /* Interrupt character [ISIG]. */ -#define VQUIT 1 /* Quit character [ISIG]. */ -#define VERASE 2 /* Erase character [ICANON]. */ -#define VKILL 3 /* Kill-line character [ICANON]. */ -#define VMIN 4 /* Minimum number of bytes read at once [!ICANON]. */ -#define VTIME 5 /* Time-out value (tenths of a second) [!ICANON]. */ -#define VEOL2 6 /* Second EOL character [ICANON]. */ -#define VSWTC 7 /* ??? */ -#define VSWTCH VSWTC -#define VSTART 8 /* Start (X-ON) character [IXON, IXOFF]. */ -#define VSTOP 9 /* Stop (X-OFF) character [IXON, IXOFF]. */ -#define VSUSP 10 /* Suspend character [ISIG]. */ -#if 0 -/* - * VDSUSP is not supported - */ -#define VDSUSP 11 /* Delayed suspend character [ISIG]. */ -#endif -#define VREPRINT 12 /* Reprint-line character [ICANON]. */ -#define VDISCARD 13 /* Discard character [IEXTEN]. */ -#define VWERASE 14 /* Word-erase character [ICANON]. */ -#define VLNEXT 15 /* Literal-next character [IEXTEN]. */ -#define VEOF 16 /* End-of-file character [ICANON]. */ -#define VEOL 17 /* End-of-line character [ICANON]. */ - -/* c_iflag bits */ -#define IGNBRK 0000001 /* Ignore break condition. */ -#define BRKINT 0000002 /* Signal interrupt on break. */ -#define IGNPAR 0000004 /* Ignore characters with parity errors. */ -#define PARMRK 0000010 /* Mark parity and framing errors. */ -#define INPCK 0000020 /* Enable input parity check. */ -#define ISTRIP 0000040 /* Strip 8th bit off characters. */ -#define INLCR 0000100 /* Map NL to CR on input. */ -#define IGNCR 0000200 /* Ignore CR. */ -#define ICRNL 0000400 /* Map CR to NL on input. */ -#define IUCLC 0001000 /* Map upper case to lower case on input. */ -#define IXON 0002000 /* Enable start/stop output control. */ -#define IXANY 0004000 /* Any character will restart after stop. */ -#define IXOFF 0010000 /* Enable start/stop input control. */ -#define IMAXBEL 0020000 /* Ring bell when input queue is full. */ - -/* c_oflag bits */ -#define OPOST 0000001 /* Perform output processing. */ -#define OLCUC 0000002 /* Map lower case to upper case on output. */ -#define ONLCR 0000004 /* Map NL to CR-NL on output. */ -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 -/* -#define PAGEOUT ??? -#define WRAP ??? - */ - -/* c_cflag bit meaning */ -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 /* Number of bits per byte (mask). */ -#define CS5 0000000 /* 5 bits per byte. */ -#define CS6 0000020 /* 6 bits per byte. */ -#define CS7 0000040 /* 7 bits per byte. */ -#define CS8 0000060 /* 8 bits per byte. */ -#define CSTOPB 0000100 /* Two stop bits instead of one. */ -#define CREAD 0000200 /* Enable receiver. */ -#define PARENB 0000400 /* Parity enable. */ -#define PARODD 0001000 /* Odd parity instead of even. */ -#define HUPCL 0002000 /* Hang up on last close. */ -#define CLOCAL 0004000 /* Ignore modem status lines. */ -#define CBAUDEX 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 -#define B500000 0010005 -#define B576000 0010006 -#define B921600 0010007 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 -#define CIBAUD 002003600000 /* input baud rate (not used) */ -#define CMSPAR 010000000000 /* mark or space (stick) parity */ -#define CRTSCTS 020000000000 /* flow control */ - -/* c_lflag bits */ -#define ISIG 0000001 /* Enable signals. */ -#define ICANON 0000002 /* Do erase and kill processing. */ -#define XCASE 0000004 -#define ECHO 0000010 /* Enable echo. */ -#define ECHOE 0000020 /* Visual erase for ERASE. */ -#define ECHOK 0000040 /* Echo NL after KILL. */ -#define ECHONL 0000100 /* Echo NL even if ECHO is off. */ -#define NOFLSH 0000200 /* Disable flush after interrupt. */ -#define IEXTEN 0000400 /* Enable DISCARD and LNEXT. */ -#define ECHOCTL 0001000 /* Echo control characters as ^X. */ -#define ECHOPRT 0002000 /* Hardcopy visual erase. */ -#define ECHOKE 0004000 /* Visual erase for KILL. */ -#define FLUSHO 0020000 -#define PENDIN 0040000 /* Retype pending input (state). */ -#define TOSTOP 0100000 /* Send SIGTTOU for background output. */ -#define ITOSTOP TOSTOP - -/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 /* Suspend output. */ -#define TCOON 1 /* Restart suspended output. */ -#define TCIOFF 2 /* Send a STOP character. */ -#define TCION 3 /* Send a START character. */ - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 /* Discard data received but not yet read. */ -#define TCOFLUSH 1 /* Discard data written but not yet sent. */ -#define TCIOFLUSH 2 /* Discard all pending data. */ - -/* tcsetattr uses these */ -#define TCSANOW TCSETS /* Change immediately. */ -#define TCSADRAIN TCSETSW /* Change when pending output is written. */ -#define TCSAFLUSH TCSETSF /* Flush pending input before changing. */ - -#endif /* _ASM_TERMBITS_H */ diff --git a/include/asm-mips64/termios.h b/include/asm-mips64/termios.h deleted file mode 100644 index 3bf796a975d..00000000000 --- a/include/asm-mips64/termios.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 2000, 2001 by Ralf Baechle - * Copyright (C) 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_TERMIOS_H -#define _ASM_TERMIOS_H - -#include -#include - -struct sgttyb { - char sg_ispeed; - char sg_ospeed; - char sg_erase; - char sg_kill; - int sg_flags; /* SGI special - int, not short */ -}; - -struct tchars { - char t_intrc; - char t_quitc; - char t_startc; - char t_stopc; - char t_eofc; - char t_brkc; -}; - -struct ltchars { - char t_suspc; /* stop process signal */ - char t_dsuspc; /* delayed stop process signal */ - char t_rprntc; /* reprint line */ - char t_flushc; /* flush output (toggles) */ - char t_werasc; /* word erase */ - char t_lnextc; /* literal next character */ -}; - -/* TIOCGSIZE, TIOCSSIZE not defined yet. Only needed for SunOS source - compatibility anyway ... */ - -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - char c_line; /* line discipline */ - unsigned char c_cc[NCCS]; /* control characters */ -}; - -#ifdef __KERNEL__ -/* - * intr=^C quit=^\ erase=del kill=^U - * vmin=\1 vtime=\0 eol2=\0 swtc=\0 - * start=^Q stop=^S susp=^Z vdsusp= - * reprint=^R discard=^U werase=^W lnext=^V - * eof=^D eol=\0 - */ -#define INIT_C_CC "\003\034\177\025\1\0\0\0\021\023\032\0\022\017\027\026\004\0" -#endif - -/* modem lines */ -#define TIOCM_LE 0x001 /* line enable */ -#define TIOCM_DTR 0x002 /* data terminal ready */ -#define TIOCM_RTS 0x004 /* request to send */ -#define TIOCM_ST 0x010 /* secondary transmit */ -#define TIOCM_SR 0x020 /* secondary receive */ -#define TIOCM_CTS 0x040 /* clear to send */ -#define TIOCM_CAR 0x100 /* carrier detect */ -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RNG 0x200 /* ring */ -#define TIOCM_RI TIOCM_RNG -#define TIOCM_DSR 0x400 /* data set ready */ -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -/* line disciplines */ -#define N_TTY 0 -#define N_SLIP 1 -#define N_MOUSE 2 -#define N_PPP 3 -#define N_STRIP 4 -#define N_AX25 5 -#define N_X25 6 /* X.25 async */ -#define N_6PACK 7 -#define N_MASC 8 /* Reserved fo Mobitex module */ -#define N_R3964 9 /* Reserved for Simatic R3964 module */ -#define N_PROFIBUS_FDL 10 /* Reserved for Profibus */ -#define N_IRDA 11 /* Linux IrDa - http://irda.sourceforge.net/ */ -#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */ -#define N_HDLC 13 /* synchronous HDLC */ -#define N_SYNC_PPP 14 /* synchronous PPP */ -#define N_HCI 15 /* Bluetooth HCI UART */ - -#ifdef __KERNEL__ - -#include - -/* - * Translate a "termio" structure into a "termios". Ugh. - */ -#define user_termio_to_kernel_termios(termios, termio) \ -({ \ - unsigned short tmp; \ - get_user(tmp, &(termio)->c_iflag); \ - (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ - get_user(tmp, &(termio)->c_oflag); \ - (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ - get_user(tmp, &(termio)->c_cflag); \ - (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ - get_user(tmp, &(termio)->c_lflag); \ - (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ - get_user((termios)->c_line, &(termio)->c_line); \ - copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -}) - -/* - * Translate a "termios" structure into a "termio". Ugh. - */ -#define kernel_termios_to_user_termio(termio, termios) \ -({ \ - put_user((termios)->c_iflag, &(termio)->c_iflag); \ - put_user((termios)->c_oflag, &(termio)->c_oflag); \ - put_user((termios)->c_cflag, &(termio)->c_cflag); \ - put_user((termios)->c_lflag, &(termio)->c_lflag); \ - put_user((termios)->c_line, &(termio)->c_line); \ - copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -}) - -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) - -#endif /* defined(__KERNEL__) */ - -#endif /* _ASM_TERMIOS_H */ diff --git a/include/asm-mips64/thread_info.h b/include/asm-mips64/thread_info.h deleted file mode 100644 index 8846cba545c..00000000000 --- a/include/asm-mips64/thread_info.h +++ /dev/null @@ -1,103 +0,0 @@ -/* thread_info.h: i386 low-level thread information - * - * Copyright (C) 2002 David Howells (dhowells@redhat.com) - * - Incorporating suggestions made by Linus Torvalds and Dave Miller - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -#include - -/* - * low level task data that entry.S needs immediate access to - * - this struct should fit entirely inside of one cache line - * - this struct shares the supervisor stack pages - * - if the contents of this structure are changed, the assembly constants - * must also be changed - */ -struct thread_info { - struct task_struct *task; /* main task structure */ - struct exec_domain *exec_domain; /* execution domain */ - unsigned long flags; /* low level flags */ - __u32 cpu; /* current CPU */ - __s32 preempt_count; /* 0 => preemptable, <0 => BUG */ - - mm_segment_t addr_limit; /* thread address space: - 0-0xBFFFFFFF for user-thead - 0-0xFFFFFFFF for kernel-thread - */ - struct restart_block restart_block; -}; - -#define PREEMPT_ACTIVE 0x4000000 - -/* - * macros/functions for gaining access to the thread information structure - * - * preempt_count needs to be 1 initially, until the scheduler is functional. - */ -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .exec_domain = &default_exec_domain, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = 1, \ - .addr_limit = KERNEL_DS, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ -} - -#define init_thread_info (init_thread_union.thread_info) -#define init_stack (init_thread_union.stack) - -/* How to get the thread information struct from C. */ -register struct thread_info *__current_thread_info __asm__("$28"); -#define current_thread_info() __current_thread_info - -/* thread information allocation */ -#define THREAD_SIZE_ORDER (2) -#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) -#define alloc_thread_info(tsk) ((struct thread_info *) \ - __get_free_pages(GFP_KERNEL,THREAD_SIZE_ORDER)) -#define free_thread_info(ti) free_pages((unsigned long) (ti), THREAD_SIZE_ORDER) -#define get_thread_info(ti) get_task_struct((ti)->task) -#define put_thread_info(ti) put_task_struct((ti)->task) - -#endif /* !__ASSEMBLY__ */ - -/* - * thread information flags - * - these are process state flags that various assembly files may need to - * access - * - pending work-to-be-done flags are in LSW - * - other flags in MSW - */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ -#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ - -#define _TIF_SYSCALL_TRACE (1< -#include -#include -#include - -/* - * RTC ops. By default, they point to no-RTC functions. - * rtc_get_time - mktime(year, mon, day, hour, min, sec) in seconds. - * rtc_set_time - reverse the above translation and set time to RTC. - * rtc_set_mmss - similar to rtc_set_time, but only min and sec need - * to be set. Used by RTC sync-up. - */ -extern unsigned long (*rtc_get_time)(void); -extern int (*rtc_set_time)(unsigned long); -extern int (*rtc_set_mmss)(unsigned long); - -/* - * to_tm() converts system time back to (year, mon, day, hour, min, sec). - * It is intended to help implement rtc_set_time() functions. - * Copied from PPC implementation. - */ -extern void to_tm(unsigned long tim, struct rtc_time *tm); - -/* - * do_gettimeoffset(). By default, this func pointer points to - * do_null_gettimeoffset(), which leads to the same resolution as HZ. - * Higher resolution versions are available, which give ~1us resolution. - */ -extern unsigned long (*do_gettimeoffset)(void); - -extern unsigned long null_gettimeoffset(void); -extern unsigned long fixed_rate_gettimeoffset(void); -extern unsigned long calibrate_div32_gettimeoffset(void); -extern unsigned long calibrate_div64_gettimeoffset(void); - -/* - * high-level timer interrupt routines. - */ -extern irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs); - -/* - * the corresponding low-level timer interrupt routine. - */ -extern asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs); - -/* - * profiling and process accouting is done separately in local_timer_interrupt - */ -extern void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs); -extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs); - -/* - * board specific routines required by time_init(). - * board_time_init is defaulted to NULL and can remain so. - * board_timer_setup must be setup properly in machine setup routine. - */ -struct irqaction; -extern void (*board_time_init)(void); -extern void (*board_timer_setup)(struct irqaction *irq); - -/* - * mips_counter_frequency - must be set if you intend to use - * counter as timer interrupt source or use fixed_rate_gettimeoffset. - */ -extern unsigned int mips_counter_frequency; - -#endif /* _ASM_TIME_H */ diff --git a/include/asm-mips64/timex.h b/include/asm-mips64/timex.h deleted file mode 100644 index 623e2e8d604..00000000000 --- a/include/asm-mips64/timex.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 1999, 2003 by Ralf Baechle - */ -#ifndef _ASM_TIMEX_H -#define _ASM_TIMEX_H - -#include -#include - -/* - * This is the frequency of the timer used for Linux's timer interrupt. - * The value should be defined as accurate as possible or under certain - * circumstances Linux timekeeping might become inaccurate or fail. - * - * For IP22 we cheat and pretend to have a 1MHz timer whic isn't strictly - * true - we only use the 8259 timer to calibrate the actual interrupt - * timer, so after all it's the master clock source of the system. - * - * The obscure number 1193182 is the same as used by the original i8254 - * time in legacy PC hardware; the chip unfortunately also found in a - * bunch of MIPS systems. - */ -#ifdef CONFIG_ACER_PICA_61 -#define CLOCK_TICK_RATE 1193182 -#elif defined(CONFIG_MIPS_MAGNUM_4000) -#define CLOCK_TICK_RATE 1193182 -#elif defined(CONFIG_OLIVETTI_M700) -#define CLOCK_TICK_RATE 1193182 -#elif defined(CONFIG_SGI_IP22) -#define CLOCK_TICK_RATE 1000000 -#elif defined(CONFIG_SNI_RM200_PCI) -#define CLOCK_TICK_RATE 1193182 -#endif - -/* - * Standard way to access the cycle counter. - * Currently only used on SMP for scheduling. - * - * Only the low 32 bits are available as a continuously counting entity. - * But this only means we'll force a reschedule every 8 seconds or so, - * which isn't an evil thing. - * - * We know that all SMP capable CPUs have cycle counters. - */ - -typedef unsigned int cycles_t; -extern cycles_t cacheflush_time; - -static inline cycles_t get_cycles (void) -{ - return read_c0_count(); -} - -#endif /* _ASM_TIMEX_H */ diff --git a/include/asm-mips64/tlb.h b/include/asm-mips64/tlb.h deleted file mode 100644 index 9376fd6fffc..00000000000 --- a/include/asm-mips64/tlb.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __ASM_TLB_H -#define __ASM_TLB_H - -/* - * MIPS doesn't need any special per-pte or per-vma handling.. - */ -#define tlb_start_vma(tlb, vma) do { } while (0) -#define tlb_end_vma(tlb, vma) do { } while (0) -#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) - -/* - * .. because we flush the whole mm when it fills up. - */ -#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) - -#include - -#endif /* __ASM_TLB_H */ diff --git a/include/asm-mips64/tlbdebug.h b/include/asm-mips64/tlbdebug.h deleted file mode 100644 index fff7a73e22d..00000000000 --- a/include/asm-mips64/tlbdebug.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002 by Ralf Baechle - */ -#ifndef __ASM_TLBDEBUG_H -#define __ASM_TLBDEBUG_H - -/* - * TLB debugging functions: - */ -extern void dump_tlb(int first, int last); -extern void dump_tlb_all(void); -extern void dump_tlb_wired(void); -extern void dump_tlb_addr(unsigned long addr); -extern void dump_tlb_nonwired(void); - -#endif /* __ASM_TLBDEBUG_H */ diff --git a/include/asm-mips64/tlbflush.h b/include/asm-mips64/tlbflush.h deleted file mode 100644 index 4bb8a8c9860..00000000000 --- a/include/asm-mips64/tlbflush.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef __ASM_TLBFLUSH_H -#define __ASM_TLBFLUSH_H - -#include -#include - -/* - * TLB flushing: - * - * - flush_tlb_all() flushes all processes TLB entries - * - flush_tlb_mm(mm) flushes the specified mm context TLB entries - * - flush_tlb_page(vma, vmaddr) flushes a single page - * - flush_tlb_range(vma, start, end) flushes a range of pages - * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages - * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables - */ -extern void local_flush_tlb_all(void); -extern void local_flush_tlb_mm(struct mm_struct *mm); -extern void local_flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end); -extern void local_flush_tlb_kernel_range(unsigned long start, - unsigned long end); -extern void local_flush_tlb_page(struct vm_area_struct *vma, - unsigned long page); - -#ifdef CONFIG_SMP - -extern void flush_tlb_all(void); -extern void flush_tlb_mm(struct mm_struct *mm); -extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end); -extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); -extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long); - -#else /* CONFIG_SMP */ - -#define flush_tlb_all() local_flush_tlb_all() -#define flush_tlb_mm(mm) local_flush_tlb_mm(mm) -#define flush_tlb_range(vma,vmaddr,end) local_flush_tlb_range(vma, vmaddr, end) -#define flush_tlb_kernel_range(vmaddr,end) \ - local_flush_tlb_kernel_range(vmaddr, end) -#define flush_tlb_page(vma,page) local_flush_tlb_page(vma, page) - -#endif /* CONFIG_SMP */ - -static inline void flush_tlb_pgtables(struct mm_struct *mm, - unsigned long start, unsigned long end) -{ - /* Nothing to do on MIPS. */ -} - -#endif /* __ASM_TLBFLUSH_H */ diff --git a/include/asm-mips64/topology.h b/include/asm-mips64/topology.h deleted file mode 100644 index b383688c4ea..00000000000 --- a/include/asm-mips64/topology.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ASM_TOPOLOGY_H -#define __ASM_TOPOLOGY_H - -#if CONFIG_SGI_IP27 - -#include - -#define cpu_to_node(cpu) (cputocnode(cpu)) -#endif - -#include - -#endif /* __ASM_TOPOLOGY_H */ diff --git a/include/asm-mips64/traps.h b/include/asm-mips64/traps.h deleted file mode 100644 index ec2b0b2d733..00000000000 --- a/include/asm-mips64/traps.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * include/asm-mips64/traps.h - * - * Trap handling definitions. - * - * Copyright (C) 2002, 2003 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS64_TRAPS_H -#define __ASM_MIPS64_TRAPS_H - -/* - * Possible status responses for a board_be_handler backend. - */ -#define MIPS_BE_DISCARD 0 /* return with no action */ -#define MIPS_BE_FIXUP 1 /* return to the fixup code */ -#define MIPS_BE_FATAL 2 /* treat as an unrecoverable error */ - -extern void (*board_be_init)(void); -extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup); - -#endif /* __ASM_MIPS64_TRAPS_H */ diff --git a/include/asm-mips64/types.h b/include/asm-mips64/types.h deleted file mode 100644 index f72a120b33c..00000000000 --- a/include/asm-mips64/types.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_TYPES_H -#define _ASM_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned int umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if (_MIPS_SZLONG == 64) - -typedef __signed__ long __s64; -typedef unsigned long __u64; - -#else - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG _MIPS_SZLONG - -#ifndef __ASSEMBLY__ - -typedef __signed char s8; -typedef unsigned char u8; - -typedef __signed short s16; -typedef unsigned short u16; - -typedef __signed int s32; -typedef unsigned int u32; - -#if (_MIPS_SZLONG == 64) - -typedef __signed__ long s64; -typedef unsigned long u64; - -#else - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long s64; -typedef unsigned long long u64; -#endif - -#endif - -typedef u64 dma_addr_t; -typedef u64 dma64_addr_t; - -typedef unsigned long phys_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_TYPES_H */ diff --git a/include/asm-mips64/ucontext.h b/include/asm-mips64/ucontext.h deleted file mode 100644 index 8a4b20e88b8..00000000000 --- a/include/asm-mips64/ucontext.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Low level exception handling - * - * Copyright (C) 1998, 1999 by Ralf Baechle - */ -#ifndef _ASM_UCONTEXT_H -#define _ASM_UCONTEXT_H - -struct ucontext { - unsigned long uc_flags; - struct ucontext *uc_link; - stack_t uc_stack; - struct sigcontext uc_mcontext; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif /* _ASM_UCONTEXT_H */ diff --git a/include/asm-mips64/unaligned.h b/include/asm-mips64/unaligned.h deleted file mode 100644 index 9aaf2e446ff..00000000000 --- a/include/asm-mips64/unaligned.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1999, 2000, 2001 by Ralf Baechle - * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. - */ -#ifndef _ASM_UNALIGNED_H -#define _ASM_UNALIGNED_H - -extern void __get_unaligned_bad_length(void); -extern void __put_unaligned_bad_length(void); - -/* - * Load quad unaligned. - */ -static inline unsigned long __ldq_u(const unsigned long * __addr) -{ - unsigned long __res; - - __asm__("uld\t%0,%1" - : "=&r" (__res) - : "m" (*__addr)); - - return __res; -} - -/* - * Load long unaligned. - */ -static inline unsigned long __ldl_u(const unsigned int * __addr) -{ - unsigned long __res; - - __asm__("ulw\t%0,%1" - : "=&r" (__res) - : "m" (*__addr)); - - return __res; -} - -/* - * Load word unaligned. - */ -static inline unsigned long __ldw_u(const unsigned short * __addr) -{ - unsigned long __res; - - __asm__("ulh\t%0,%1" - : "=&r" (__res) - : "m" (*__addr)); - - return __res; -} - -/* - * Store quad unaligned. - */ -static inline void __stq_u(unsigned long __val, unsigned long * __addr) -{ - __asm__("usd\t%1, %0" - : "=m" (*__addr) - : "r" (__val)); -} - -/* - * Store long unaligned. - */ -static inline void __stl_u(unsigned long __val, unsigned int * __addr) -{ - __asm__("usw\t%1, %0" - : "=m" (*__addr) - : "r" (__val)); -} - -/* - * Store word unaligned. - */ -static inline void __stw_u(unsigned long __val, unsigned short * __addr) -{ - __asm__("ush\t%1, %0" - : "=m" (*__addr) - : "r" (__val)); -} - -/* - * get_unaligned - get value from possibly mis-aligned location - * @ptr: pointer to value - * - * This macro should be used for accessing values larger in size than - * single bytes at locations that are expected to be improperly aligned, - * e.g. retrieving a u16 value from a location not u16-aligned. - * - * Note that unaligned accesses can be very expensive on some architectures. - */ -#define get_unaligned(ptr) \ -({ \ - __typeof__(*(ptr)) __val; \ - \ - switch (sizeof(*(ptr))) { \ - case 1: \ - __val = *(const unsigned char *)(ptr); \ - break; \ - case 2: \ - __val = __ldw_u((const unsigned short *)(ptr)); \ - break; \ - case 4: \ - __val = __ldl_u((const unsigned int *)(ptr)); \ - break; \ - case 8: \ - __val = __ldq_u((const unsigned long *)(ptr)); \ - break; \ - default: \ - __get_unaligned_bad_length(); \ - break; \ - } \ - \ - __val; \ -}) - -/* - * put_unaligned - put value to a possibly mis-aligned location - * @val: value to place - * @ptr: pointer to location - * - * This macro should be used for placing values larger in size than - * single bytes at locations that are expected to be improperly aligned, - * e.g. writing a u16 value to a location not u16-aligned. - * - * Note that unaligned accesses can be very expensive on some architectures. - */ -#define put_unaligned(val,ptr) \ -do { \ - switch (sizeof(*(ptr))) { \ - case 1: \ - *(unsigned char *)(ptr) = (val); \ - break; \ - case 2: \ - __stw_u((val), (unsigned short *)(ptr)); \ - break; \ - case 4: \ - __stl_u((val), (unsigned int *)(ptr)); \ - break; \ - case 8: \ - __stq_u((val), (unsigned long long *)(ptr)); \ - break; \ - default: \ - __put_unaligned_bad_length(); \ - break; \ - } \ -} while(0) - -#endif /* _ASM_UNALIGNED_H */ diff --git a/include/asm-mips64/unistd.h b/include/asm-mips64/unistd.h deleted file mode 100644 index 27eeb860276..00000000000 --- a/include/asm-mips64/unistd.h +++ /dev/null @@ -1,1067 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * - * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto - * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A - */ -#ifndef _ASM_UNISTD_H -#define _ASM_UNISTD_H - -/* - * Linux o32 style syscalls are in the range from 4000 to 4999. - */ -#define __NR_O32_Linux 4000 -#define __NR_O32_syscall (__NR_O32_Linux + 0) -#define __NR_O32_exit (__NR_O32_Linux + 1) -#define __NR_O32_fork (__NR_O32_Linux + 2) -#define __NR_O32_read (__NR_O32_Linux + 3) -#define __NR_O32_write (__NR_O32_Linux + 4) -#define __NR_O32_open (__NR_O32_Linux + 5) -#define __NR_O32_close (__NR_O32_Linux + 6) -#define __NR_O32_waitpid (__NR_O32_Linux + 7) -#define __NR_O32_creat (__NR_O32_Linux + 8) -#define __NR_O32_link (__NR_O32_Linux + 9) -#define __NR_O32_unlink (__NR_O32_Linux + 10) -#define __NR_O32_execve (__NR_O32_Linux + 11) -#define __NR_O32_chdir (__NR_O32_Linux + 12) -#define __NR_O32_time (__NR_O32_Linux + 13) -#define __NR_O32_mknod (__NR_O32_Linux + 14) -#define __NR_O32_chmod (__NR_O32_Linux + 15) -#define __NR_O32_lchown (__NR_O32_Linux + 16) -#define __NR_O32_break (__NR_O32_Linux + 17) -#define __NR_O32_unused18 (__NR_O32_Linux + 18) -#define __NR_O32_lseek (__NR_O32_Linux + 19) -#define __NR_O32_getpid (__NR_O32_Linux + 20) -#define __NR_O32_mount (__NR_O32_Linux + 21) -#define __NR_O32_umount (__NR_O32_Linux + 22) -#define __NR_O32_setuid (__NR_O32_Linux + 23) -#define __NR_O32_getuid (__NR_O32_Linux + 24) -#define __NR_O32_stime (__NR_O32_Linux + 25) -#define __NR_O32_ptrace (__NR_O32_Linux + 26) -#define __NR_O32_alarm (__NR_O32_Linux + 27) -#define __NR_O32_unused28 (__NR_O32_Linux + 28) -#define __NR_O32_pause (__NR_O32_Linux + 29) -#define __NR_O32_utime (__NR_O32_Linux + 30) -#define __NR_O32_stty (__NR_O32_Linux + 31) -#define __NR_O32_gtty (__NR_O32_Linux + 32) -#define __NR_O32_access (__NR_O32_Linux + 33) -#define __NR_O32_nice (__NR_O32_Linux + 34) -#define __NR_O32_ftime (__NR_O32_Linux + 35) -#define __NR_O32_sync (__NR_O32_Linux + 36) -#define __NR_O32_kill (__NR_O32_Linux + 37) -#define __NR_O32_rename (__NR_O32_Linux + 38) -#define __NR_O32_mkdir (__NR_O32_Linux + 39) -#define __NR_O32_rmdir (__NR_O32_Linux + 40) -#define __NR_O32_dup (__NR_O32_Linux + 41) -#define __NR_O32_pipe (__NR_O32_Linux + 42) -#define __NR_O32_times (__NR_O32_Linux + 43) -#define __NR_O32_prof (__NR_O32_Linux + 44) -#define __NR_O32_brk (__NR_O32_Linux + 45) -#define __NR_O32_setgid (__NR_O32_Linux + 46) -#define __NR_O32_getgid (__NR_O32_Linux + 47) -#define __NR_O32_signal (__NR_O32_Linux + 48) -#define __NR_O32_geteuid (__NR_O32_Linux + 49) -#define __NR_O32_getegid (__NR_O32_Linux + 50) -#define __NR_O32_acct (__NR_O32_Linux + 51) -#define __NR_O32_umount2 (__NR_O32_Linux + 52) -#define __NR_O32_lock (__NR_O32_Linux + 53) -#define __NR_O32_ioctl (__NR_O32_Linux + 54) -#define __NR_O32_fcntl (__NR_O32_Linux + 55) -#define __NR_O32_mpx (__NR_O32_Linux + 56) -#define __NR_O32_setpgid (__NR_O32_Linux + 57) -#define __NR_O32_ulimit (__NR_O32_Linux + 58) -#define __NR_O32_unused59 (__NR_O32_Linux + 59) -#define __NR_O32_umask (__NR_O32_Linux + 60) -#define __NR_O32_chroot (__NR_O32_Linux + 61) -#define __NR_O32_ustat (__NR_O32_Linux + 62) -#define __NR_O32_dup2 (__NR_O32_Linux + 63) -#define __NR_O32_getppid (__NR_O32_Linux + 64) -#define __NR_O32_getpgrp (__NR_O32_Linux + 65) -#define __NR_O32_setsid (__NR_O32_Linux + 66) -#define __NR_O32_sigaction (__NR_O32_Linux + 67) -#define __NR_O32_sgetmask (__NR_O32_Linux + 68) -#define __NR_O32_ssetmask (__NR_O32_Linux + 69) -#define __NR_O32_setreuid (__NR_O32_Linux + 70) -#define __NR_O32_setregid (__NR_O32_Linux + 71) -#define __NR_O32_sigsuspend (__NR_O32_Linux + 72) -#define __NR_O32_sigpending (__NR_O32_Linux + 73) -#define __NR_O32_sethostname (__NR_O32_Linux + 74) -#define __NR_O32_setrlimit (__NR_O32_Linux + 75) -#define __NR_O32_getrlimit (__NR_O32_Linux + 76) -#define __NR_O32_getrusage (__NR_O32_Linux + 77) -#define __NR_O32_gettimeofday (__NR_O32_Linux + 78) -#define __NR_O32_settimeofday (__NR_O32_Linux + 79) -#define __NR_O32_getgroups (__NR_O32_Linux + 80) -#define __NR_O32_setgroups (__NR_O32_Linux + 81) -#define __NR_O32_reserved82 (__NR_O32_Linux + 82) -#define __NR_O32_symlink (__NR_O32_Linux + 83) -#define __NR_O32_unused84 (__NR_O32_Linux + 84) -#define __NR_O32_readlink (__NR_O32_Linux + 85) -#define __NR_O32_uselib (__NR_O32_Linux + 86) -#define __NR_O32_swapon (__NR_O32_Linux + 87) -#define __NR_O32_reboot (__NR_O32_Linux + 88) -#define __NR_O32_readdir (__NR_O32_Linux + 89) -#define __NR_O32_mmap (__NR_O32_Linux + 90) -#define __NR_O32_munmap (__NR_O32_Linux + 91) -#define __NR_O32_truncate (__NR_O32_Linux + 92) -#define __NR_O32_ftruncate (__NR_O32_Linux + 93) -#define __NR_O32_fchmod (__NR_O32_Linux + 94) -#define __NR_O32_fchown (__NR_O32_Linux + 95) -#define __NR_O32_getpriority (__NR_O32_Linux + 96) -#define __NR_O32_setpriority (__NR_O32_Linux + 97) -#define __NR_O32_profil (__NR_O32_Linux + 98) -#define __NR_O32_statfs (__NR_O32_Linux + 99) -#define __NR_O32_fstatfs (__NR_O32_Linux + 100) -#define __NR_O32_ioperm (__NR_O32_Linux + 101) -#define __NR_O32_socketcall (__NR_O32_Linux + 102) -#define __NR_O32_syslog (__NR_O32_Linux + 103) -#define __NR_O32_setitimer (__NR_O32_Linux + 104) -#define __NR_O32_getitimer (__NR_O32_Linux + 105) -#define __NR_O32_stat (__NR_O32_Linux + 106) -#define __NR_O32_lstat (__NR_O32_Linux + 107) -#define __NR_O32_fstat (__NR_O32_Linux + 108) -#define __NR_O32_unused109 (__NR_O32_Linux + 109) -#define __NR_O32_iopl (__NR_O32_Linux + 110) -#define __NR_O32_vhangup (__NR_O32_Linux + 111) -#define __NR_O32_idle (__NR_O32_Linux + 112) -#define __NR_O32_vm86 (__NR_O32_Linux + 113) -#define __NR_O32_wait4 (__NR_O32_Linux + 114) -#define __NR_O32_swapoff (__NR_O32_Linux + 115) -#define __NR_O32_sysinfo (__NR_O32_Linux + 116) -#define __NR_O32_ipc (__NR_O32_Linux + 117) -#define __NR_O32_fsync (__NR_O32_Linux + 118) -#define __NR_O32_sigreturn (__NR_O32_Linux + 119) -#define __NR_O32_clone (__NR_O32_Linux + 120) -#define __NR_O32_setdomainname (__NR_O32_Linux + 121) -#define __NR_O32_uname (__NR_O32_Linux + 122) -#define __NR_O32_modify_ldt (__NR_O32_Linux + 123) -#define __NR_O32_adjtimex (__NR_O32_Linux + 124) -#define __NR_O32_mprotect (__NR_O32_Linux + 125) -#define __NR_O32_sigprocmask (__NR_O32_Linux + 126) -#define __NR_O32_create_module (__NR_O32_Linux + 127) -#define __NR_O32_init_module (__NR_O32_Linux + 128) -#define __NR_O32_delete_module (__NR_O32_Linux + 129) -#define __NR_O32_get_kernel_syms (__NR_O32_Linux + 130) -#define __NR_O32_quotactl (__NR_O32_Linux + 131) -#define __NR_O32_getpgid (__NR_O32_Linux + 132) -#define __NR_O32_fchdir (__NR_O32_Linux + 133) -#define __NR_O32_bdflush (__NR_O32_Linux + 134) -#define __NR_O32_sysfs (__NR_O32_Linux + 135) -#define __NR_O32_personality (__NR_O32_Linux + 136) -#define __NR_O32_afs_syscall (__NR_O32_Linux + 137) /* Syscall for Andrew File System */ -#define __NR_O32_setfsuid (__NR_O32_Linux + 138) -#define __NR_O32_setfsgid (__NR_O32_Linux + 139) -#define __NR_O32__llseek (__NR_O32_Linux + 140) -#define __NR_O32_getdents (__NR_O32_Linux + 141) -#define __NR_O32__newselect (__NR_O32_Linux + 142) -#define __NR_O32_flock (__NR_O32_Linux + 143) -#define __NR_O32_msync (__NR_O32_Linux + 144) -#define __NR_O32_readv (__NR_O32_Linux + 145) -#define __NR_O32_writev (__NR_O32_Linux + 146) -#define __NR_O32_cacheflush (__NR_O32_Linux + 147) -#define __NR_O32_cachectl (__NR_O32_Linux + 148) -#define __NR_O32_sysmips (__NR_O32_Linux + 149) -#define __NR_O32_unused150 (__NR_O32_Linux + 150) -#define __NR_O32_getsid (__NR_O32_Linux + 151) -#define __NR_O32_fdatasync (__NR_O32_Linux + 152) -#define __NR_O32__sysctl (__NR_O32_Linux + 153) -#define __NR_O32_mlock (__NR_O32_Linux + 154) -#define __NR_O32_munlock (__NR_O32_Linux + 155) -#define __NR_O32_mlockall (__NR_O32_Linux + 156) -#define __NR_O32_munlockall (__NR_O32_Linux + 157) -#define __NR_O32_sched_setparam (__NR_O32_Linux + 158) -#define __NR_O32_sched_getparam (__NR_O32_Linux + 159) -#define __NR_O32_sched_setscheduler (__NR_O32_Linux + 160) -#define __NR_O32_sched_getscheduler (__NR_O32_Linux + 161) -#define __NR_O32_sched_yield (__NR_O32_Linux + 162) -#define __NR_O32_sched_get_priority_max (__NR_O32_Linux + 163) -#define __NR_O32_sched_get_priority_min (__NR_O32_Linux + 164) -#define __NR_O32_sched_rr_get_interval (__NR_O32_Linux + 165) -#define __NR_O32_nanosleep (__NR_O32_Linux + 166) -#define __NR_O32_mremap (__NR_O32_Linux + 167) -#define __NR_O32_accept (__NR_O32_Linux + 168) -#define __NR_O32_bind (__NR_O32_Linux + 169) -#define __NR_O32_connect (__NR_O32_Linux + 170) -#define __NR_O32_getpeername (__NR_O32_Linux + 171) -#define __NR_O32_getsockname (__NR_O32_Linux + 172) -#define __NR_O32_getsockopt (__NR_O32_Linux + 173) -#define __NR_O32_listen (__NR_O32_Linux + 174) -#define __NR_O32_recv (__NR_O32_Linux + 175) -#define __NR_O32_recvfrom (__NR_O32_Linux + 176) -#define __NR_O32_recvmsg (__NR_O32_Linux + 177) -#define __NR_O32_send (__NR_O32_Linux + 178) -#define __NR_O32_sendmsg (__NR_O32_Linux + 179) -#define __NR_O32_sendto (__NR_O32_Linux + 180) -#define __NR_O32_setsockopt (__NR_O32_Linux + 181) -#define __NR_O32_shutdown (__NR_O32_Linux + 182) -#define __NR_O32_socket (__NR_O32_Linux + 183) -#define __NR_O32_socketpair (__NR_O32_Linux + 184) -#define __NR_O32_setresuid (__NR_O32_Linux + 185) -#define __NR_O32_getresuid (__NR_O32_Linux + 186) -#define __NR_O32_query_module (__NR_O32_Linux + 187) -#define __NR_O32_poll (__NR_O32_Linux + 188) -#define __NR_O32_nfsservctl (__NR_O32_Linux + 189) -#define __NR_O32_setresgid (__NR_O32_Linux + 190) -#define __NR_O32_getresgid (__NR_O32_Linux + 191) -#define __NR_O32_prctl (__NR_O32_Linux + 192) -#define __NR_O32_rt_sigreturn (__NR_O32_Linux + 193) -#define __NR_O32_rt_sigaction (__NR_O32_Linux + 194) -#define __NR_O32_rt_sigprocmask (__NR_O32_Linux + 195) -#define __NR_O32_rt_sigpending (__NR_O32_Linux + 196) -#define __NR_O32_rt_sigtimedwait (__NR_O32_Linux + 197) -#define __NR_O32_rt_sigqueueinfo (__NR_O32_Linux + 198) -#define __NR_O32_rt_sigsuspend (__NR_O32_Linux + 199) -#define __NR_O32_pread64 (__NR_O32_Linux + 200) -#define __NR_O32_pwrite64 (__NR_O32_Linux + 201) -#define __NR_O32_chown (__NR_O32_Linux + 202) -#define __NR_O32_getcwd (__NR_O32_Linux + 203) -#define __NR_O32_capget (__NR_O32_Linux + 204) -#define __NR_O32_capset (__NR_O32_Linux + 205) -#define __NR_O32_sigaltstack (__NR_O32_Linux + 206) -#define __NR_O32_sendfile (__NR_O32_Linux + 207) -#define __NR_O32_getpmsg (__NR_O32_Linux + 208) -#define __NR_O32_putpmsg (__NR_O32_Linux + 209) -#define __NR_O32_mmap2 (__NR_O32_Linux + 210) -#define __NR_O32_truncate64 (__NR_O32_Linux + 211) -#define __NR_O32_ftruncate64 (__NR_O32_Linux + 212) -#define __NR_O32_stat64 (__NR_O32_Linux + 213) -#define __NR_O32_lstat64 (__NR_O32_Linux + 214) -#define __NR_O32_fstat64 (__NR_O32_Linux + 215) -#define __NR_O32_root_pivot (__NR_O32_Linux + 216) -#define __NR_O32_mincore (__NR_O32_Linux + 217) -#define __NR_O32_madvise (__NR_O32_Linux + 218) -#define __NR_O32_getdents64 (__NR_O32_Linux + 219) -#define __NR_O32_fcntl64 (__NR_O32_Linux + 220) -#define __NR_O32_reserved221 (__NR_O32_Linux + 221) -#define __NR_O32_gettid (__NR_O32_Linux + 222) -#define __NR_O32_readahead (__NR_O32_Linux + 223) -#define __NR_O32_setxattr (__NR_O32_Linux + 224) -#define __NR_O32_lsetxattr (__NR_O32_Linux + 225) -#define __NR_O32_fsetxattr (__NR_O32_Linux + 226) -#define __NR_O32_getxattr (__NR_O32_Linux + 227) -#define __NR_O32_lgetxattr (__NR_O32_Linux + 228) -#define __NR_O32_fgetxattr (__NR_O32_Linux + 229) -#define __NR_O32_listxattr (__NR_O32_Linux + 230) -#define __NR_O32_llistxattr (__NR_O32_Linux + 231) -#define __NR_O32_flistxattr (__NR_O32_Linux + 232) -#define __NR_O32_removexattr (__NR_O32_Linux + 233) -#define __NR_O32_lremovexattr (__NR_O32_Linux + 234) -#define __NR_O32_fremovexattr (__NR_O32_Linux + 235) -#define __NR_O32_tkill (__NR_O32_Linux + 236) -#define __NR_O32_sendfile64 (__NR_O32_Linux + 237) -#define __NR_O32_futex (__NR_O32_Linux + 238) -#define __NR_O32_sched_setaffinity (__NR_O32_Linux + 239) -#define __NR_O32_sched_getaffinity (__NR_O32_Linux + 240) -#define __NR_O32_io_setup (__NR_O32_Linux + 241) -#define __NR_O32_io_destroy (__NR_O32_Linux + 242) -#define __NR_O32_io_getevents (__NR_O32_Linux + 243) -#define __NR_O32_io_submit (__NR_O32_Linux + 244) -#define __NR_O32_io_cancel (__NR_O32_Linux + 245) -#define __NR_O32_exit_group (__NR_O32_Linux + 246) -#define __NR_O32_lookup_dcookie (__NR_O32_Linux + 247) -#define __NR_O32_epoll_create (__NR_O32_Linux + 248) -#define __NR_O32_epoll_ctl (__NR_O32_Linux + 249) -#define __NR_O32_epoll_wait (__NR_O32_Linux + 250) -#define __NR_O32_remap_file_page (__NR_O32_Linux + 251) -#define __NR_O32_set_tid_address (__NR_O32_Linux + 252) -#define __NR_O32_restart_syscall (__NR_O32_Linux + 253) -#define __NR_O32_fadvise64 (__NR_O32_Linux + 254) -#define __NR_O32_statfs64 (__NR_O32_Linux + 255) -#define __NR_O32_fstatfs64 (__NR_O32_Linux + 256) -#define __NR_O32_timer_create (__NR_O32_Linux + 257) -#define __NR_O32_timer_settime (__NR_O32_Linux + 258) -#define __NR_O32_timer_gettime (__NR_O32_Linux + 259) -#define __NR_O32_timer_getoverrun (__NR_O32_Linux + 260) -#define __NR_O32_timer_delete (__NR_O32_Linux + 261) -#define __NR_O32_clock_settime (__NR_O32_Linux + 262) -#define __NR_O32_clock_gettime (__NR_O32_Linux + 263) -#define __NR_O32_clock_getres (__NR_O32_Linux + 264) -#define __NR_O32_clock_nanosleep (__NR_O32_Linux + 265) -#define __NR_O32_tgkill (__NR_O32_Linux + 266) -#define __NR_O32_utimes (__NR_O32_Linux + 267) - -/* - * Offset of the last Linux o32 flavoured syscall - */ -#define __NR_O32_Linux_syscalls 267 - - -/* - * Linux 64-bit syscalls are in the range from 5000 to 5999. - */ -#define __NR_Linux 5000 -#define __NR_read (__NR_Linux + 0) -#define __NR_write (__NR_Linux + 1) -#define __NR_open (__NR_Linux + 2) -#define __NR_close (__NR_Linux + 3) -#define __NR_stat (__NR_Linux + 4) -#define __NR_fstat (__NR_Linux + 5) -#define __NR_lstat (__NR_Linux + 6) -#define __NR_poll (__NR_Linux + 7) -#define __NR_lseek (__NR_Linux + 8) -#define __NR_mmap (__NR_Linux + 9) -#define __NR_mprotect (__NR_Linux + 10) -#define __NR_munmap (__NR_Linux + 11) -#define __NR_brk (__NR_Linux + 12) -#define __NR_rt_sigaction (__NR_Linux + 13) -#define __NR_rt_sigprocmask (__NR_Linux + 14) -#define __NR_ioctl (__NR_Linux + 15) -#define __NR_pread64 (__NR_Linux + 16) -#define __NR_pwrite64 (__NR_Linux + 17) -#define __NR_readv (__NR_Linux + 18) -#define __NR_writev (__NR_Linux + 19) -#define __NR_access (__NR_Linux + 20) -#define __NR_pipe (__NR_Linux + 21) -#define __NR__newselect (__NR_Linux + 22) -#define __NR_sched_yield (__NR_Linux + 23) -#define __NR_mremap (__NR_Linux + 24) -#define __NR_msync (__NR_Linux + 25) -#define __NR_mincore (__NR_Linux + 26) -#define __NR_madvise (__NR_Linux + 27) -#define __NR_shmget (__NR_Linux + 28) -#define __NR_shmat (__NR_Linux + 29) -#define __NR_shmctl (__NR_Linux + 30) -#define __NR_dup (__NR_Linux + 31) -#define __NR_dup2 (__NR_Linux + 32) -#define __NR_pause (__NR_Linux + 33) -#define __NR_nanosleep (__NR_Linux + 34) -#define __NR_getitimer (__NR_Linux + 35) -#define __NR_setitimer (__NR_Linux + 36) -#define __NR_alarm (__NR_Linux + 37) -#define __NR_getpid (__NR_Linux + 38) -#define __NR_sendfile (__NR_Linux + 39) -#define __NR_socket (__NR_Linux + 40) -#define __NR_connect (__NR_Linux + 41) -#define __NR_accept (__NR_Linux + 42) -#define __NR_sendto (__NR_Linux + 43) -#define __NR_recvfrom (__NR_Linux + 44) -#define __NR_sendmsg (__NR_Linux + 45) -#define __NR_recvmsg (__NR_Linux + 46) -#define __NR_shutdown (__NR_Linux + 47) -#define __NR_bind (__NR_Linux + 48) -#define __NR_listen (__NR_Linux + 49) -#define __NR_getsockname (__NR_Linux + 50) -#define __NR_getpeername (__NR_Linux + 51) -#define __NR_socketpair (__NR_Linux + 52) -#define __NR_setsockopt (__NR_Linux + 53) -#define __NR_getsockopt (__NR_Linux + 54) -#define __NR_clone (__NR_Linux + 55) -#define __NR_fork (__NR_Linux + 56) -#define __NR_execve (__NR_Linux + 57) -#define __NR_exit (__NR_Linux + 58) -#define __NR_wait4 (__NR_Linux + 59) -#define __NR_kill (__NR_Linux + 60) -#define __NR_uname (__NR_Linux + 61) -#define __NR_semget (__NR_Linux + 62) -#define __NR_semop (__NR_Linux + 63) -#define __NR_semctl (__NR_Linux + 64) -#define __NR_shmdt (__NR_Linux + 65) -#define __NR_msgget (__NR_Linux + 66) -#define __NR_msgsnd (__NR_Linux + 67) -#define __NR_msgrcv (__NR_Linux + 68) -#define __NR_msgctl (__NR_Linux + 69) -#define __NR_fcntl (__NR_Linux + 70) -#define __NR_flock (__NR_Linux + 71) -#define __NR_fsync (__NR_Linux + 72) -#define __NR_fdatasync (__NR_Linux + 73) -#define __NR_truncate (__NR_Linux + 74) -#define __NR_ftruncate (__NR_Linux + 75) -#define __NR_getdents (__NR_Linux + 76) -#define __NR_getcwd (__NR_Linux + 77) -#define __NR_chdir (__NR_Linux + 78) -#define __NR_fchdir (__NR_Linux + 79) -#define __NR_rename (__NR_Linux + 80) -#define __NR_mkdir (__NR_Linux + 81) -#define __NR_rmdir (__NR_Linux + 82) -#define __NR_creat (__NR_Linux + 83) -#define __NR_link (__NR_Linux + 84) -#define __NR_unlink (__NR_Linux + 85) -#define __NR_symlink (__NR_Linux + 86) -#define __NR_readlink (__NR_Linux + 87) -#define __NR_chmod (__NR_Linux + 88) -#define __NR_fchmod (__NR_Linux + 89) -#define __NR_chown (__NR_Linux + 90) -#define __NR_fchown (__NR_Linux + 91) -#define __NR_lchown (__NR_Linux + 92) -#define __NR_umask (__NR_Linux + 93) -#define __NR_gettimeofday (__NR_Linux + 94) -#define __NR_getrlimit (__NR_Linux + 95) -#define __NR_getrusage (__NR_Linux + 96) -#define __NR_sysinfo (__NR_Linux + 97) -#define __NR_times (__NR_Linux + 98) -#define __NR_ptrace (__NR_Linux + 99) -#define __NR_getuid (__NR_Linux + 100) -#define __NR_syslog (__NR_Linux + 101) -#define __NR_getgid (__NR_Linux + 102) -#define __NR_setuid (__NR_Linux + 103) -#define __NR_setgid (__NR_Linux + 104) -#define __NR_geteuid (__NR_Linux + 105) -#define __NR_getegid (__NR_Linux + 106) -#define __NR_setpgid (__NR_Linux + 107) -#define __NR_getppid (__NR_Linux + 108) -#define __NR_getpgrp (__NR_Linux + 109) -#define __NR_setsid (__NR_Linux + 110) -#define __NR_setreuid (__NR_Linux + 111) -#define __NR_setregid (__NR_Linux + 112) -#define __NR_getgroups (__NR_Linux + 113) -#define __NR_setgroups (__NR_Linux + 114) -#define __NR_setresuid (__NR_Linux + 115) -#define __NR_getresuid (__NR_Linux + 116) -#define __NR_setresgid (__NR_Linux + 117) -#define __NR_getresgid (__NR_Linux + 118) -#define __NR_getpgid (__NR_Linux + 119) -#define __NR_setfsuid (__NR_Linux + 120) -#define __NR_setfsgid (__NR_Linux + 121) -#define __NR_getsid (__NR_Linux + 122) -#define __NR_capget (__NR_Linux + 123) -#define __NR_capset (__NR_Linux + 124) -#define __NR_rt_sigpending (__NR_Linux + 125) -#define __NR_rt_sigtimedwait (__NR_Linux + 126) -#define __NR_rt_sigqueueinfo (__NR_Linux + 127) -#define __NR_rt_sigsuspend (__NR_Linux + 128) -#define __NR_sigaltstack (__NR_Linux + 129) -#define __NR_utime (__NR_Linux + 130) -#define __NR_mknod (__NR_Linux + 131) -#define __NR_personality (__NR_Linux + 132) -#define __NR_ustat (__NR_Linux + 133) -#define __NR_statfs (__NR_Linux + 134) -#define __NR_fstatfs (__NR_Linux + 135) -#define __NR_sysfs (__NR_Linux + 136) -#define __NR_getpriority (__NR_Linux + 137) -#define __NR_setpriority (__NR_Linux + 138) -#define __NR_sched_setparam (__NR_Linux + 139) -#define __NR_sched_getparam (__NR_Linux + 140) -#define __NR_sched_setscheduler (__NR_Linux + 141) -#define __NR_sched_getscheduler (__NR_Linux + 142) -#define __NR_sched_get_priority_max (__NR_Linux + 143) -#define __NR_sched_get_priority_min (__NR_Linux + 144) -#define __NR_sched_rr_get_interval (__NR_Linux + 145) -#define __NR_mlock (__NR_Linux + 146) -#define __NR_munlock (__NR_Linux + 147) -#define __NR_mlockall (__NR_Linux + 148) -#define __NR_munlockall (__NR_Linux + 149) -#define __NR_vhangup (__NR_Linux + 150) -#define __NR_pivot_root (__NR_Linux + 151) -#define __NR__sysctl (__NR_Linux + 152) -#define __NR_prctl (__NR_Linux + 153) -#define __NR_adjtimex (__NR_Linux + 154) -#define __NR_setrlimit (__NR_Linux + 155) -#define __NR_chroot (__NR_Linux + 156) -#define __NR_sync (__NR_Linux + 157) -#define __NR_acct (__NR_Linux + 158) -#define __NR_settimeofday (__NR_Linux + 159) -#define __NR_mount (__NR_Linux + 160) -#define __NR_umount2 (__NR_Linux + 161) -#define __NR_swapon (__NR_Linux + 162) -#define __NR_swapoff (__NR_Linux + 163) -#define __NR_reboot (__NR_Linux + 164) -#define __NR_sethostname (__NR_Linux + 165) -#define __NR_setdomainname (__NR_Linux + 166) -#define __NR_create_module (__NR_Linux + 167) -#define __NR_init_module (__NR_Linux + 168) -#define __NR_delete_module (__NR_Linux + 169) -#define __NR_get_kernel_syms (__NR_Linux + 170) -#define __NR_query_module (__NR_Linux + 171) -#define __NR_quotactl (__NR_Linux + 172) -#define __NR_nfsservctl (__NR_Linux + 173) -#define __NR_getpmsg (__NR_Linux + 174) -#define __NR_putpmsg (__NR_Linux + 175) -#define __NR_afs_syscall (__NR_Linux + 176) -#define __NR_reserved177 (__NR_Linux + 177) -#define __NR_gettid (__NR_Linux + 178) -#define __NR_readahead (__NR_Linux + 179) -#define __NR_setxattr (__NR_Linux + 180) -#define __NR_lsetxattr (__NR_Linux + 181) -#define __NR_fsetxattr (__NR_Linux + 182) -#define __NR_getxattr (__NR_Linux + 183) -#define __NR_lgetxattr (__NR_Linux + 184) -#define __NR_fgetxattr (__NR_Linux + 185) -#define __NR_listxattr (__NR_Linux + 186) -#define __NR_llistxattr (__NR_Linux + 187) -#define __NR_flistxattr (__NR_Linux + 188) -#define __NR_removexattr (__NR_Linux + 189) -#define __NR_lremovexattr (__NR_Linux + 190) -#define __NR_fremovexattr (__NR_Linux + 191) -#define __NR_tkill (__NR_Linux + 192) -#define __NR_time (__NR_Linux + 193) -#define __NR_futex (__NR_Linux + 194) -#define __NR_sched_setaffinity (__NR_Linux + 195) -#define __NR_sched_getaffinity (__NR_Linux + 196) -#define __NR_cacheflush (__NR_Linux + 197) -#define __NR_cachectl (__NR_Linux + 198) -#define __NR_sysmips (__NR_Linux + 199) -#define __NR_io_setup (__NR_Linux + 200) -#define __NR_io_destroy (__NR_Linux + 201) -#define __NR_io_getevents (__NR_Linux + 202) -#define __NR_io_submit (__NR_Linux + 203) -#define __NR_io_cancel (__NR_Linux + 204) -#define __NR_exit_group (__NR_Linux + 205) -#define __NR_lookup_dcookie (__NR_Linux + 206) -#define __NR_epoll_create (__NR_Linux + 207) -#define __NR_epoll_ctl (__NR_Linux + 208) -#define __NR_epoll_wait (__NR_Linux + 209) -#define __NR_remap_file_page (__NR_Linux + 210) -#define __NR_rt_sigreturn (__NR_Linux + 211) -#define __NR_set_tid_address (__NR_Linux + 212) -#define __NR_restart_syscall (__NR_Linux + 213) -#define __NR_semtimedop (__NR_Linux + 214) -#define __NR_fadvise64 (__NR_Linux + 215) -#define __NR_timer_create (__NR_Linux + 216) -#define __NR_timer_settime (__NR_Linux + 217) -#define __NR_timer_gettime (__NR_Linux + 218) -#define __NR_timer_getoverrun (__NR_Linux + 219) -#define __NR_timer_delete (__NR_Linux + 220) -#define __NR_clock_settime (__NR_Linux + 221) -#define __NR_clock_gettime (__NR_Linux + 222) -#define __NR_clock_getres (__NR_Linux + 223) -#define __NR_clock_nanosleep (__NR_Linux + 224) -#define __NR_tgkill (__NR_Linux + 225) -#define __NR_utimes (__NR_Linux + 226) - -/* - * Offset of the last Linux flavoured syscall - */ -#define __NR_Linux_syscalls 226 - -/* - * Linux N32 syscalls are in the range from 6000 to 6999. - */ -#define __NR_N32_Linux 6000 -#define __NR_N32_read (__NR_N32_Linux + 0) -#define __NR_N32_write (__NR_N32_Linux + 1) -#define __NR_N32_open (__NR_N32_Linux + 2) -#define __NR_N32_close (__NR_N32_Linux + 3) -#define __NR_N32_stat (__NR_N32_Linux + 4) -#define __NR_N32_fstat (__NR_N32_Linux + 5) -#define __NR_N32_lstat (__NR_N32_Linux + 6) -#define __NR_N32_poll (__NR_N32_Linux + 7) -#define __NR_N32_lseek (__NR_N32_Linux + 8) -#define __NR_N32_mmap (__NR_N32_Linux + 9) -#define __NR_N32_mprotect (__NR_N32_Linux + 10) -#define __NR_N32_munmap (__NR_N32_Linux + 11) -#define __NR_N32_brk (__NR_N32_Linux + 12) -#define __NR_N32_rt_sigaction (__NR_N32_Linux + 13) -#define __NR_N32_rt_sigprocmask (__NR_N32_Linux + 14) -#define __NR_N32_ioctl (__NR_N32_Linux + 15) -#define __NR_N32_pread64 (__NR_N32_Linux + 16) -#define __NR_N32_pwrite64 (__NR_N32_Linux + 17) -#define __NR_N32_readv (__NR_N32_Linux + 18) -#define __NR_N32_writev (__NR_N32_Linux + 19) -#define __NR_N32_access (__NR_N32_Linux + 20) -#define __NR_N32_pipe (__NR_N32_Linux + 21) -#define __NR_N32__newselect (__NR_N32_Linux + 22) -#define __NR_N32_sched_yield (__NR_N32_Linux + 23) -#define __NR_N32_mremap (__NR_N32_Linux + 24) -#define __NR_N32_msync (__NR_N32_Linux + 25) -#define __NR_N32_mincore (__NR_N32_Linux + 26) -#define __NR_N32_madvise (__NR_N32_Linux + 27) -#define __NR_N32_shmget (__NR_N32_Linux + 28) -#define __NR_N32_shmat (__NR_N32_Linux + 29) -#define __NR_N32_shmctl (__NR_N32_Linux + 30) -#define __NR_N32_dup (__NR_N32_Linux + 31) -#define __NR_N32_dup2 (__NR_N32_Linux + 32) -#define __NR_N32_pause (__NR_N32_Linux + 33) -#define __NR_N32_nanosleep (__NR_N32_Linux + 34) -#define __NR_N32_getitimer (__NR_N32_Linux + 35) -#define __NR_N32_setitimer (__NR_N32_Linux + 36) -#define __NR_N32_alarm (__NR_N32_Linux + 37) -#define __NR_N32_getpid (__NR_N32_Linux + 38) -#define __NR_N32_sendfile (__NR_N32_Linux + 39) -#define __NR_N32_socket (__NR_N32_Linux + 40) -#define __NR_N32_connect (__NR_N32_Linux + 41) -#define __NR_N32_accept (__NR_N32_Linux + 42) -#define __NR_N32_sendto (__NR_N32_Linux + 43) -#define __NR_N32_recvfrom (__NR_N32_Linux + 44) -#define __NR_N32_sendmsg (__NR_N32_Linux + 45) -#define __NR_N32_recvmsg (__NR_N32_Linux + 46) -#define __NR_N32_shutdown (__NR_N32_Linux + 47) -#define __NR_N32_bind (__NR_N32_Linux + 48) -#define __NR_N32_listen (__NR_N32_Linux + 49) -#define __NR_N32_getsockname (__NR_N32_Linux + 50) -#define __NR_N32_getpeername (__NR_N32_Linux + 51) -#define __NR_N32_socketpair (__NR_N32_Linux + 52) -#define __NR_N32_setsockopt (__NR_N32_Linux + 53) -#define __NR_N32_getsockopt (__NR_N32_Linux + 54) -#define __NR_N32_clone (__NR_N32_Linux + 55) -#define __NR_N32_fork (__NR_N32_Linux + 56) -#define __NR_N32_execve (__NR_N32_Linux + 57) -#define __NR_N32_exit (__NR_N32_Linux + 58) -#define __NR_N32_wait4 (__NR_N32_Linux + 59) -#define __NR_N32_kill (__NR_N32_Linux + 60) -#define __NR_N32_uname (__NR_N32_Linux + 61) -#define __NR_N32_semget (__NR_N32_Linux + 62) -#define __NR_N32_semop (__NR_N32_Linux + 63) -#define __NR_N32_semctl (__NR_N32_Linux + 64) -#define __NR_N32_shmdt (__NR_N32_Linux + 65) -#define __NR_N32_msgget (__NR_N32_Linux + 66) -#define __NR_N32_msgsnd (__NR_N32_Linux + 67) -#define __NR_N32_msgrcv (__NR_N32_Linux + 68) -#define __NR_N32_msgctl (__NR_N32_Linux + 69) -#define __NR_N32_fcntl (__NR_N32_Linux + 70) -#define __NR_N32_flock (__NR_N32_Linux + 71) -#define __NR_N32_fsync (__NR_N32_Linux + 72) -#define __NR_N32_fdatasync (__NR_N32_Linux + 73) -#define __NR_N32_truncate (__NR_N32_Linux + 74) -#define __NR_N32_ftruncate (__NR_N32_Linux + 75) -#define __NR_N32_getdents (__NR_N32_Linux + 76) -#define __NR_N32_getcwd (__NR_N32_Linux + 77) -#define __NR_N32_chdir (__NR_N32_Linux + 78) -#define __NR_N32_fchdir (__NR_N32_Linux + 79) -#define __NR_N32_rename (__NR_N32_Linux + 80) -#define __NR_N32_mkdir (__NR_N32_Linux + 81) -#define __NR_N32_rmdir (__NR_N32_Linux + 82) -#define __NR_N32_creat (__NR_N32_Linux + 83) -#define __NR_N32_link (__NR_N32_Linux + 84) -#define __NR_N32_unlink (__NR_N32_Linux + 85) -#define __NR_N32_symlink (__NR_N32_Linux + 86) -#define __NR_N32_readlink (__NR_N32_Linux + 87) -#define __NR_N32_chmod (__NR_N32_Linux + 88) -#define __NR_N32_fchmod (__NR_N32_Linux + 89) -#define __NR_N32_chown (__NR_N32_Linux + 90) -#define __NR_N32_fchown (__NR_N32_Linux + 91) -#define __NR_N32_lchown (__NR_N32_Linux + 92) -#define __NR_N32_umask (__NR_N32_Linux + 93) -#define __NR_N32_gettimeofday (__NR_N32_Linux + 94) -#define __NR_N32_getrlimit (__NR_N32_Linux + 95) -#define __NR_N32_getrusage (__NR_N32_Linux + 96) -#define __NR_N32_sysinfo (__NR_N32_Linux + 97) -#define __NR_N32_times (__NR_N32_Linux + 98) -#define __NR_N32_ptrace (__NR_N32_Linux + 99) -#define __NR_N32_getuid (__NR_N32_Linux + 100) -#define __NR_N32_syslog (__NR_N32_Linux + 101) -#define __NR_N32_getgid (__NR_N32_Linux + 102) -#define __NR_N32_setuid (__NR_N32_Linux + 103) -#define __NR_N32_setgid (__NR_N32_Linux + 104) -#define __NR_N32_geteuid (__NR_N32_Linux + 105) -#define __NR_N32_getegid (__NR_N32_Linux + 106) -#define __NR_N32_setpgid (__NR_N32_Linux + 107) -#define __NR_N32_getppid (__NR_N32_Linux + 108) -#define __NR_N32_getpgrp (__NR_N32_Linux + 109) -#define __NR_N32_setsid (__NR_N32_Linux + 110) -#define __NR_N32_setreuid (__NR_N32_Linux + 111) -#define __NR_N32_setregid (__NR_N32_Linux + 112) -#define __NR_N32_getgroups (__NR_N32_Linux + 113) -#define __NR_N32_setgroups (__NR_N32_Linux + 114) -#define __NR_N32_setresuid (__NR_N32_Linux + 115) -#define __NR_N32_getresuid (__NR_N32_Linux + 116) -#define __NR_N32_setresgid (__NR_N32_Linux + 117) -#define __NR_N32_getresgid (__NR_N32_Linux + 118) -#define __NR_N32_getpgid (__NR_N32_Linux + 119) -#define __NR_N32_setfsuid (__NR_N32_Linux + 120) -#define __NR_N32_setfsgid (__NR_N32_Linux + 121) -#define __NR_N32_getsid (__NR_N32_Linux + 122) -#define __NR_N32_capget (__NR_N32_Linux + 123) -#define __NR_N32_capset (__NR_N32_Linux + 124) -#define __NR_N32_rt_sigpending (__NR_N32_Linux + 125) -#define __NR_N32_rt_sigtimedwait (__NR_N32_Linux + 126) -#define __NR_N32_rt_sigqueueinfo (__NR_N32_Linux + 127) -#define __NR_N32_rt_sigsuspend (__NR_N32_Linux + 128) -#define __NR_N32_sigaltstack (__NR_N32_Linux + 129) -#define __NR_N32_utime (__NR_N32_Linux + 130) -#define __NR_N32_mknod (__NR_N32_Linux + 131) -#define __NR_N32_personality (__NR_N32_Linux + 132) -#define __NR_N32_ustat (__NR_N32_Linux + 133) -#define __NR_N32_statfs (__NR_N32_Linux + 134) -#define __NR_N32_fstatfs (__NR_N32_Linux + 135) -#define __NR_N32_sysfs (__NR_N32_Linux + 136) -#define __NR_N32_getpriority (__NR_N32_Linux + 137) -#define __NR_N32_setpriority (__NR_N32_Linux + 138) -#define __NR_N32_sched_setparam (__NR_N32_Linux + 139) -#define __NR_N32_sched_getparam (__NR_N32_Linux + 140) -#define __NR_N32_sched_setscheduler (__NR_N32_Linux + 141) -#define __NR_N32_sched_getscheduler (__NR_N32_Linux + 142) -#define __NR_N32_sched_get_priority_max (__NR_N32_Linux + 143) -#define __NR_N32_sched_get_priority_min (__NR_N32_Linux + 144) -#define __NR_N32_sched_rr_get_interval (__NR_N32_Linux + 145) -#define __NR_N32_mlock (__NR_N32_Linux + 146) -#define __NR_N32_munlock (__NR_N32_Linux + 147) -#define __NR_N32_mlockall (__NR_N32_Linux + 148) -#define __NR_N32_munlockall (__NR_N32_Linux + 149) -#define __NR_N32_vhangup (__NR_N32_Linux + 150) -#define __NR_N32_pivot_root (__NR_N32_Linux + 151) -#define __NR_N32__sysctl (__NR_N32_Linux + 152) -#define __NR_N32_prctl (__NR_N32_Linux + 153) -#define __NR_N32_adjtimex (__NR_N32_Linux + 154) -#define __NR_N32_setrlimit (__NR_N32_Linux + 155) -#define __NR_N32_chroot (__NR_N32_Linux + 156) -#define __NR_N32_sync (__NR_N32_Linux + 157) -#define __NR_N32_acct (__NR_N32_Linux + 158) -#define __NR_N32_settimeofday (__NR_N32_Linux + 159) -#define __NR_N32_mount (__NR_N32_Linux + 160) -#define __NR_N32_umount2 (__NR_N32_Linux + 161) -#define __NR_N32_swapon (__NR_N32_Linux + 162) -#define __NR_N32_swapoff (__NR_N32_Linux + 163) -#define __NR_N32_reboot (__NR_N32_Linux + 164) -#define __NR_N32_sethostname (__NR_N32_Linux + 165) -#define __NR_N32_setdomainname (__NR_N32_Linux + 166) -#define __NR_N32_create_module (__NR_N32_Linux + 167) -#define __NR_N32_init_module (__NR_N32_Linux + 168) -#define __NR_N32_delete_module (__NR_N32_Linux + 169) -#define __NR_N32_get_kernel_syms (__NR_N32_Linux + 170) -#define __NR_N32_query_module (__NR_N32_Linux + 171) -#define __NR_N32_quotactl (__NR_N32_Linux + 172) -#define __NR_N32_nfsservctl (__NR_N32_Linux + 173) -#define __NR_N32_getpmsg (__NR_N32_Linux + 174) -#define __NR_N32_putpmsg (__NR_N32_Linux + 175) -#define __NR_N32_afs_syscall (__NR_N32_Linux + 176) -#define __NR_N32_reserved177 (__NR_N32_Linux + 177) -#define __NR_N32_gettid (__NR_N32_Linux + 178) -#define __NR_N32_readahead (__NR_N32_Linux + 179) -#define __NR_N32_setxattr (__NR_N32_Linux + 180) -#define __NR_N32_lsetxattr (__NR_N32_Linux + 181) -#define __NR_N32_fsetxattr (__NR_N32_Linux + 182) -#define __NR_N32_getxattr (__NR_N32_Linux + 183) -#define __NR_N32_lgetxattr (__NR_N32_Linux + 184) -#define __NR_N32_fgetxattr (__NR_N32_Linux + 185) -#define __NR_N32_listxattr (__NR_N32_Linux + 186) -#define __NR_N32_llistxattr (__NR_N32_Linux + 187) -#define __NR_N32_flistxattr (__NR_N32_Linux + 188) -#define __NR_N32_removexattr (__NR_N32_Linux + 189) -#define __NR_N32_lremovexattr (__NR_N32_Linux + 190) -#define __NR_N32_fremovexattr (__NR_N32_Linux + 191) -#define __NR_N32_tkill (__NR_N32_Linux + 192) -#define __NR_N32_time (__NR_N32_Linux + 193) -#define __NR_N32_futex (__NR_N32_Linux + 194) -#define __NR_N32_sched_setaffinity (__NR_N32_Linux + 195) -#define __NR_N32_sched_getaffinity (__NR_N32_Linux + 196) -#define __NR_N32_cacheflush (__NR_N32_Linux + 197) -#define __NR_N32_cachectl (__NR_N32_Linux + 198) -#define __NR_N32_sysmips (__NR_N32_Linux + 199) -#define __NR_N32_io_setup (__NR_N32_Linux + 200) -#define __NR_N32_io_destroy (__NR_N32_Linux + 201) -#define __NR_N32_io_getevents (__NR_N32_Linux + 202) -#define __NR_N32_io_submit (__NR_N32_Linux + 203) -#define __NR_N32_io_cancel (__NR_N32_Linux + 204) -#define __NR_N32_exit_group (__NR_N32_Linux + 205) -#define __NR_N32_lookup_dcookie (__NR_N32_Linux + 206) -#define __NR_N32_epoll_create (__NR_N32_Linux + 207) -#define __NR_N32_epoll_ctl (__NR_N32_Linux + 208) -#define __NR_N32_epoll_wait (__NR_N32_Linux + 209) -#define __NR_N32_remap_file_page (__NR_N32_Linux + 210) -#define __NR_N32_rt_sigreturn (__NR_N32_Linux + 211) -#define __NR_N32_fcntl64 (__NR_N32_Linux + 212) -#define __NR_N32_set_tid_address (__NR_N32_Linux + 213) -#define __NR_N32_restart_syscall (__NR_N32_Linux + 214) -#define __NR_N32_semtimedop (__NR_N32_Linux + 215) -#define __NR_N32_fadvise64 (__NR_N32_Linux + 216) -#define __NR_N32_statfs64 (__NR_N32_Linux + 217) -#define __NR_N32_fstatfs64 (__NR_N32_Linux + 218) -#define __NR_N32_sendfile64 (__NR_N32_Linux + 219) -#define __NR_N32_timer_create (__NR_N32_Linux + 221) -#define __NR_N32_timer_settime (__NR_N32_Linux + 222) -#define __NR_N32_timer_gettime (__NR_N32_Linux + 223) -#define __NR_N32_timer_getoverrun (__NR_N32_Linux + 224) -#define __NR_N32_timer_delete (__NR_N32_Linux + 225) -#define __NR_N32_clock_settime (__NR_N32_Linux + 226) -#define __NR_N32_clock_gettime (__NR_N32_Linux + 227) -#define __NR_N32_clock_getres (__NR_N32_Linux + 228) -#define __NR_N32_clock_nanosleep (__NR_N32_Linux + 229) -#define __NR_N32_tgkill (__NR_N32_Linux + 230) -#define __NR_N32_utimes (__NR_N32_Linux + 231) - -/* - * Offset of the last N32 flavoured syscall - */ -#define __NR_N32_Linux_syscalls 231 - -#ifndef __ASSEMBLY__ - -/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ -#define _syscall0(type,name) \ -type name(void) \ -{ \ - register unsigned long __a3 asm("$7"); \ - unsigned long __v0; \ - \ - __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - "li\t$2, %2\t\t\t# " #name "\n\t" \ - "syscall\n\t" \ - "move\t%0, $2\n\t" \ - ".set\treorder" \ - : "=&r" (__v0), "=r" (__a3) \ - : "i" (__NR_##name) \ - : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ - \ - if (__a3 == 0) \ - return (type) __v0; \ - errno = __v0; \ - return -1; \ -} - -/* - * DANGER: This macro isn't usable for the pipe(2) call - * which has a unusual return convention. - */ -#define _syscall1(type,name,atype,a) \ -type name(atype a) \ -{ \ - register unsigned long __a0 asm("$4") = (unsigned long) a; \ - register unsigned long __a3 asm("$7"); \ - unsigned long __v0; \ - \ - __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - "li\t$2, %3\t\t\t# " #name "\n\t" \ - "syscall\n\t" \ - "move\t%0, $2\n\t" \ - ".set\treorder" \ - : "=&r" (__v0), "=r" (__a3) \ - : "r" (__a0), "i" (__NR_##name) \ - : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ - \ - if (__a3 == 0) \ - return (type) __v0; \ - errno = __v0; \ - return -1; \ -} - -#define _syscall2(type,name,atype,a,btype,b) \ -type name(atype a, btype b) \ -{ \ - register unsigned long __a0 asm("$4") = (unsigned long) a; \ - register unsigned long __a1 asm("$5") = (unsigned long) b; \ - register unsigned long __a3 asm("$7"); \ - unsigned long __v0; \ - \ - __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - "li\t$2, %4\t\t\t# " #name "\n\t" \ - "syscall\n\t" \ - "move\t%0, $2\n\t" \ - ".set\treorder" \ - : "=&r" (__v0), "=r" (__a3) \ - : "r" (__a0), "r" (__a1), "i" (__NR_##name) \ - : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ - \ - if (__a3 == 0) \ - return (type) __v0; \ - errno = __v0; \ - return -1; \ -} - -#define _syscall3(type,name,atype,a,btype,b,ctype,c) \ -type name(atype a, btype b, ctype c) \ -{ \ - register unsigned long __a0 asm("$4") = (unsigned long) a; \ - register unsigned long __a1 asm("$5") = (unsigned long) b; \ - register unsigned long __a2 asm("$6") = (unsigned long) c; \ - register unsigned long __a3 asm("$7"); \ - unsigned long __v0; \ - \ - __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - "li\t$2, %5\t\t\t# " #name "\n\t" \ - "syscall\n\t" \ - "move\t%0, $2\n\t" \ - ".set\treorder" \ - : "=&r" (__v0), "=r" (__a3) \ - : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \ - : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ - \ - if (__a3 == 0) \ - return (type) __v0; \ - errno = __v0; \ - return -1; \ -} - -#define _syscall4(type,name,atype,a,btype,b,ctype,c,dtype,d) \ -type name(atype a, btype b, ctype c, dtype d) \ -{ \ - register unsigned long __a0 asm("$4") = (unsigned long) a; \ - register unsigned long __a1 asm("$5") = (unsigned long) b; \ - register unsigned long __a2 asm("$6") = (unsigned long) c; \ - register unsigned long __a3 asm("$7") = (unsigned long) d; \ - unsigned long __v0; \ - \ - __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - "li\t$2, %5\t\t\t# " #name "\n\t" \ - "syscall\n\t" \ - "move\t%0, $2\n\t" \ - ".set\treorder" \ - : "=&r" (__v0), "+r" (__a3) \ - : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \ - : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ - \ - if (__a3 == 0) \ - return (type) __v0; \ - errno = __v0; \ - return -1; \ -} - -#if (_MIPS_SIM == _ABIN32) || (_MIPS_SIM == _ABI64) - -#define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ -type name (atype a,btype b,ctype c,dtype d,etype e) \ -{ \ - register unsigned long __a0 asm("$4") = (unsigned long) a; \ - register unsigned long __a1 asm("$5") = (unsigned long) b; \ - register unsigned long __a2 asm("$6") = (unsigned long) c; \ - register unsigned long __a3 asm("$7") = (unsigned long) d; \ - register unsigned long __a4 asm("$8") = (unsigned long) e; \ - unsigned long __v0; \ - \ - __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - "li\t$2, %6\t\t\t# " #name "\n\t" \ - "syscall\n\t" \ - "move\t%0, $2\n\t" \ - ".set\treorder" \ - : "=&r" (__v0), "+r" (__a3), "+r" (__a4) \ - : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \ - : "$2","$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ - \ - if (__a3 == 0) \ - return (type) __v0; \ - errno = __v0; \ - return -1; \ -} - -#define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \ -type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \ -{ \ - register unsigned long __a0 asm("$4") = (unsigned long) a; \ - register unsigned long __a1 asm("$5") = (unsigned long) b; \ - register unsigned long __a2 asm("$6") = (unsigned long) c; \ - register unsigned long __a3 asm("$7") = (unsigned long) d; \ - register unsigned long __a4 asm("$8") = (unsigned long) e; \ - register unsigned long __a5 asm("$9") = (unsigned long) f; \ - unsigned long __v0; \ - \ - __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - "li\t$2, %6\t\t\t# " #name "\n\t" \ - "syscall\n\t" \ - "move\t%0, $2\n\t" \ - ".set\treorder" \ - : "=&r" (__v0), "+r" (__a3) \ - : "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "r" (__a5), \ - "i" (__NR_##name) \ - : "$2","$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ - \ - if (__a3 == 0) \ - return (type) __v0; \ - errno = __v0; \ - return -1; \ -} - -#else /* not N32 or 64 ABI */ - -/* - * Using those means your brain needs more than an oil change ;-) - */ - -#define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ -type name(atype a, btype b, ctype c, dtype d, etype e) \ -{ \ - register unsigned long __a0 asm("$4") = (unsigned long) a; \ - register unsigned long __a1 asm("$5") = (unsigned long) b; \ - register unsigned long __a2 asm("$6") = (unsigned long) c; \ - register unsigned long __a3 asm("$7") = (unsigned long) d; \ - unsigned long __v0; \ - \ - __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - "lw\t$2, %6\n\t" \ - "subu\t$29, 32\n\t" \ - "sw\t$2, 16($29)\n\t" \ - "li\t$2, %5\t\t\t# " #name "\n\t" \ - "syscall\n\t" \ - "move\t%0, $2\n\t" \ - "addiu\t$29, 32\n\t" \ - ".set\treorder" \ - : "=&r" (__v0), "+r" (__a3) \ - : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name), \ - "m" ((unsigned long)e) \ - : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ - \ - if (__a3 == 0) \ - return (type) __v0; \ - errno = __v0; \ - return -1; \ -} - -#define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \ -type name(atype a, btype b, ctype c, dtype d, etype e, ftype f) \ -{ \ - register unsigned long __a0 asm("$4") = (unsigned long) a; \ - register unsigned long __a1 asm("$5") = (unsigned long) b; \ - register unsigned long __a2 asm("$6") = (unsigned long) c; \ - register unsigned long __a3 asm("$7") = (unsigned long) d; \ - unsigned long __v0; \ - \ - __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - "lw\t$2, %6\n\t" \ - "lw\t$8, %7\n\t" \ - "subu\t$29, 32\n\t" \ - "sw\t$2, 16($29)\n\t" \ - "sw\t$8, 20($29)\n\t" \ - "li\t$2, %5\t\t\t# " #name "\n\t" \ - "syscall\n\t" \ - "move\t%0, $2\n\t" \ - "addiu\t$29, 32\n\t" \ - ".set\treorder" \ - : "=&r" (__v0), "+r" (__a3) \ - : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name), \ - "m" ((unsigned long)e), "m" ((unsigned long)f) \ - : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \ - \ - if (__a3 == 0) \ - return (type) __v0; \ - errno = __v0; \ - return -1; \ -} - -#endif - -#ifdef __KERNEL_SYSCALLS__ - -/* - * we need this inline - forking from kernel space will result - * in NO COPY ON WRITE (!!!), until an execve is executed. This - * is no problem, but for the stack. This is handled by not letting - * main() use the stack at all after fork(). Thus, no function - * calls - which means inline code for fork too, as otherwise we - * would use the stack upon exit from 'fork()'. - * - * Actually only pause and fork are needed inline, so that there - * won't be any messing with the stack from main(), but we define - * some others too. - */ -#define __NR__exit __NR_exit -static inline _syscall0(pid_t,setsid) -static inline _syscall3(int,write,int,fd,const char *,buf,off_t,count) -static inline _syscall3(int,read,int,fd,char *,buf,off_t,count) -static inline _syscall3(off_t,lseek,int,fd,off_t,offset,int,count) -static inline _syscall1(int,dup,int,fd) -static inline _syscall3(int,execve,const char *,file,char **,argv,char **,envp) -static inline _syscall3(int,open,const char *,file,int,flag,int,mode) -static inline _syscall1(int,close,int,fd) -static inline _syscall1(int,_exit,int,exitcode) -struct rusage; -static inline _syscall4(pid_t,wait4,pid_t,pid,int *,stat_addr,int,options,struct rusage *,ru) - -static inline pid_t waitpid(int pid, int * wait_stat, int flags) -{ - return wait4(pid, wait_stat, flags, NULL); -} - -#endif /* __KERNEL_SYSCALLS__ */ -#endif /* !__ASSEMBLY__ */ - -/* - * "Conditional" syscalls - * - * What we want is __attribute__((weak,alias("sys_ni_syscall"))), - * but it doesn't work on all toolchains, so we just do it by hand - */ -#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall"); - -#endif /* _ASM_UNISTD_H */ diff --git a/include/asm-mips64/user.h b/include/asm-mips64/user.h deleted file mode 100644 index 0d55bd46f4f..00000000000 --- a/include/asm-mips64/user.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle - */ -#ifndef _ASM_USER_H -#define _ASM_USER_H - -#include -#include - -/* - * Core file format: The core file is written in such a way that gdb - * can understand it and provide useful information to the user (under - * linux we use the `trad-core' bfd, NOT the irix-core). The file - * contents are as follows: - * - * upage: 1 page consisting of a user struct that tells gdb - * what is present in the file. Directly after this is a - * copy of the task_struct, which is currently not used by gdb, - * but it may come in handy at some point. All of the registers - * are stored as part of the upage. The upage should always be - * only one page long. - * data: The data segment follows next. We use current->end_text to - * current->brk to pick up all of the user variables, plus any memory - * that may have been sbrk'ed. No attempt is made to determine if a - * page is demand-zero or if a page is totally unused, we just cover - * the entire range. All of the addresses are rounded in such a way - * that an integral number of pages is written. - * stack: We need the stack information in order to get a meaningful - * backtrace. We need to write the data from usp to - * current->start_stack, so we round each of these in order to be able - * to write an integer number of pages. - */ -struct user { - unsigned long regs[EF_SIZE/8+64]; /* integer and fp regs */ - size_t u_tsize; /* text size (pages) */ - size_t u_dsize; /* data size (pages) */ - size_t u_ssize; /* stack size (pages) */ - unsigned long start_code; /* text starting address */ - unsigned long start_data; /* data starting address */ - unsigned long start_stack; /* stack starting address */ - long int signal; /* signal causing core dump */ - struct regs * u_ar0; /* help gdb find registers */ - unsigned long magic; /* identifies a core file */ - char u_comm[32]; /* user command name */ -}; - -#define NBPG PAGE_SIZE -#define UPAGES 1 -#define HOST_TEXT_START_ADDR (u.start_code) -#define HOST_DATA_START_ADDR (u.start_data) -#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) - -#endif /* _ASM_USER_H */ diff --git a/include/asm-mips64/vga.h b/include/asm-mips64/vga.h deleted file mode 100644 index 6b35cf054c7..00000000000 --- a/include/asm-mips64/vga.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Access to VGA videoram - * - * (c) 1998 Martin Mares - */ -#ifndef _ASM_VGA_H -#define _ASM_VGA_H - -/* - * On the PC, we can just recalculate addresses and then - * access the videoram directly without any black magic. - */ - -#define VGA_MAP_MEM(x) (0xb0000000L + (unsigned long)(x)) - -#define vga_readb(x) (*(x)) -#define vga_writeb(x,y) (*(y) = (x)) - -#endif /* _ASM_VGA_H */ diff --git a/include/asm-mips64/war.h b/include/asm-mips64/war.h deleted file mode 100644 index a62c7d63240..00000000000 --- a/include/asm-mips64/war.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002 by Ralf Baechle - */ -#ifndef _ASM_WAR_H -#define _ASM_WAR_H - -#include - -/* - * Pleassures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: - * - * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, - * Hit_Invalidate_D and Create_Dirty_Excl_D should only be - * executed if there is no other dcache activity. If the dcache is - * accessed for another instruction immeidately preceding when these - * cache instructions are executing, it is possible that the dcache - * tag match outputs used by these cache instructions will be - * incorrect. These cache instructions should be preceded by at least - * four instructions that are not any kind of load or store - * instruction. - * - * This is not allowed: lw - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - * - * This is allowed: lw - * nop - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - * - * #define R4600_V1_HIT_CACHEOP_WAR 1 - */ - - -/* - * Writeback and invalidate the primary cache dcache before DMA. - * - * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, - * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only - * operate correctly if the internal data cache refill buffer is empty. These - * CACHE instructions should be separated from any potential data cache miss - * by a load instruction to an uncached address to empty the response buffer." - * (Revision 2.0 device errata from IDT available on http://www.idt.com/ - * in .pdf format.) - * - * #define R4600_V2_HIT_CACHEOP_WAR 1 - */ - -/* - * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. - */ -#ifdef CONFIG_SGI_IP22 - -#define R4600_V1_HIT_CACHEOP_WAR 1 -#define R4600_V2_HIT_CACHEOP_WAR 1 - -#endif - -/* - * But the RM200C seems to have been shipped only with V2.0 R4600s - */ -#ifdef CONFIG_SNI_RM200_PCI - -#define R4600_V2_HIT_CACHEOP_WAR 1 - -#endif - -#ifdef CONFIG_CPU_R5432 - -/* - * When an interrupt happens on a CP0 register read instruction, CPU may - * lock up or read corrupted values of CP0 registers after it enters - * the exception handler. - * - * This workaround makes sure that we read a "safe" CP0 register as the - * first thing in the exception handler, which breaks one of the - * pre-conditions for this problem. - */ -#define R5432_CP0_INTERRUPT_WAR 1 - -#endif - -#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ - defined(CONFIG_SB1_PASS_2_WORKAROUNDS) - -/* - * Workaround for the Sibyte M3 errata the text of which can be found at - * - * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt - * - * This will enable the use of a special TLB refill handler which does a - * consistency check on the information in c0_badvaddr and c0_entryhi and - * will just return and take the exception again if the information was - * found to be inconsistent. - */ -#define BCM1250_M3_WAR 1 - -/* - * This is a DUART workaround related to glitches around register accesses - */ -#define SIBYTE_1956_WAR 1 - -#endif - -/* - * Workarounds default to off - */ -#ifndef R4600_V1_HIT_CACHEOP_WAR -#define R4600_V1_HIT_CACHEOP_WAR 0 -#endif -#ifndef R4600_V2_HIT_CACHEOP_WAR -#define R4600_V2_HIT_CACHEOP_WAR 0 -#endif -#ifndef R5432_CP0_INTERRUPT_WAR -#define R5432_CP0_INTERRUPT_WAR 0 -#endif -#ifndef BCM1250_M3_WAR -#define BCM1250_M3_WAR 0 -#endif -#ifndef SIBYTE_1956_WAR -#define SIBYTE_1956_WAR 0 -#endif - -#endif /* _ASM_WAR_H */ diff --git a/include/asm-mips64/watch.h b/include/asm-mips64/watch.h deleted file mode 100644 index 5cde1f2ae37..00000000000 --- a/include/asm-mips64/watch.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001 by Ralf Baechle - */ -#ifndef _ASM_WATCH_H -#define _ASM_WATCH_H - -#include - -/* - * Types of reference for watch_set() - */ -enum wref_type { - wr_save = 1, - wr_load = 2 -}; - -extern asmlinkage void __watch_set(unsigned long addr, enum wref_type ref); -extern asmlinkage void __watch_clear(void); -extern asmlinkage void __watch_reenable(void); - -#define watch_set(addr, ref) \ - if (cpu_has_watch) \ - __watch_set(addr, ref) -#define watch_clear() \ - if (cpu_has_watch) \ - __watch_clear() -#define watch_reenable() \ - if (cpu_has_watch) \ - __watch_reenable() - -#endif /* _ASM_WATCH_H */ diff --git a/include/asm-mips64/wbflush.h b/include/asm-mips64/wbflush.h deleted file mode 100644 index a54c1195690..00000000000 --- a/include/asm-mips64/wbflush.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Header file for using the wbflush routine - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 1998 Harald Koerfgen - * Copyright (C) 2002 Maciej W. Rozycki - */ -#ifndef __ASM_MIPS64_WBFLUSH_H -#define __ASM_MIPS64_WBFLUSH_H - -#define wbflush_setup() do { } while (0) - -#define wbflush() fast_iob() - -#endif /* __ASM_MIPS64_WBFLUSH_H */ diff --git a/include/asm-mips64/xor.h b/include/asm-mips64/xor.h deleted file mode 100644 index c82eb12a5b1..00000000000 --- a/include/asm-mips64/xor.h +++ /dev/null @@ -1 +0,0 @@ -#include -- 2.11.4.GIT