From 393f12a08f01f3dd48828e88a7fa174336d1ab19 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Fri, 13 Jun 2003 14:19:56 +0000 Subject: [PATCH] Feed the mess through indent. --- arch/mips/pci/common.c | 17 +- arch/mips/pci/fixup-au1000.c | 30 +-- arch/mips/pci/fixup-ite8172g.c | 228 ++++++++++---------- arch/mips/pci/fixup-ivr.c | 152 ++++++------- arch/mips/pci/fixup-jmr3927.c | 17 +- arch/mips/pci/fixup-ocelot.c | 20 +- arch/mips/pci/fixup-tb0226.c | 31 +-- arch/mips/pci/fixup-tb0229.c | 24 ++- arch/mips/pci/fixups-ev96100.c | 22 +- arch/mips/pci/ops-au1000.c | 165 +++++++------- arch/mips/pci/ops-ddb5074.c | 172 +++++++-------- arch/mips/pci/ops-ddb5476.c | 166 +++++++------- arch/mips/pci/ops-ddb5477.c | 94 ++++---- arch/mips/pci/ops-ev64120.c | 10 +- arch/mips/pci/ops-ev96100.c | 110 +++++----- arch/mips/pci/ops-it8172.c | 66 +++--- arch/mips/pci/ops-jmr3927.c | 216 ++++++++++--------- arch/mips/pci/ops-ocelot.c | 133 +++++++----- arch/mips/pci/ops-vrc4173.c | 19 +- arch/mips/pci/pci-auto.c | 296 +++++++++++++------------ arch/mips/pci/pci-cobalt.c | 130 ++++++----- arch/mips/pci/pci-ddb5074.c | 98 ++++----- arch/mips/pci/pci-ddb5476.c | 42 ++-- arch/mips/pci/pci-ddb5477.c | 149 +++++++------ arch/mips/pci/pci-hplj.c | 477 ++++++++++++++++++++++------------------- arch/mips/pci/pci-ip27.c | 104 +++++---- arch/mips/pci/pci-ip32.c | 278 ++++++++++++------------ arch/mips/pci/pci-lasat.c | 131 ++++++----- arch/mips/pci/pci-mips.c | 176 +++++++-------- arch/mips/pci/pci-ocelot-c.c | 43 ++-- arch/mips/pci/pci-ocelot-g.c | 113 +++++----- arch/mips/pci/pci-sb1250.c | 40 ++-- arch/mips/pci/pci-sni.c | 50 ++--- arch/mips/pci/pci-vr41xx.c | 48 ++--- arch/mips/pci/pci-vr41xx.h | 12 +- arch/mips/pci/pci.c | 31 +-- 36 files changed, 2060 insertions(+), 1850 deletions(-) rewrite arch/mips/pci/pci-hplj.c (60%) diff --git a/arch/mips/pci/common.c b/arch/mips/pci/common.c index 1cc7ab08845..1692c007ac1 100644 --- a/arch/mips/pci/common.c +++ b/arch/mips/pci/common.c @@ -11,14 +11,16 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask) pci_read_config_word(dev, PCI_COMMAND, &cmd); old_cmd = cmd; - for(idx=0; idx<6; idx++) { + for (idx = 0; idx < 6; idx++) { /* Only set up the requested stuff */ - if (!(mask & (1<resource[idx]; if (!r->start && r->end) { - printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name); + printk(KERN_ERR + "PCI: Device %s not available because of resource collisions\n", + dev->slot_name); return -EINVAL; } if (r->flags & IORESOURCE_IO) @@ -29,7 +31,8 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask) if (dev->resource[PCI_ROM_RESOURCE].start) cmd |= PCI_COMMAND_MEMORY; if (cmd != old_cmd) { - printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd); + printk("PCI: Enabling device %s (%04x -> %04x)\n", + dev->slot_name, old_cmd, cmd); pci_write_config_word(dev, PCI_COMMAND, cmd); } return 0; @@ -46,7 +49,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) } void __init pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) + unsigned long size, unsigned long align) { panic("Uhhoh called pcibios_align_resource"); } @@ -58,9 +61,9 @@ unsigned __init int pcibios_assign_all_busses(void) char *pcibios_setup(char *str) { - return str; + return str; } struct pci_fixup pcibios_fixups[] = { - { 0 } + {0} }; diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c index 24803505f7e..6f6f88fbd38 100644 --- a/arch/mips/pci/fixup-au1000.c +++ b/arch/mips/pci/fixup-au1000.c @@ -45,7 +45,7 @@ #define DBG(x...) #endif -static void fixup_resource(int r_num, struct pci_dev *dev) ; +static void fixup_resource(int r_num, struct pci_dev *dev); #ifdef CONFIG_SOC_AU1500 static unsigned long virt_io_addr; #endif @@ -60,9 +60,10 @@ void __init pcibios_fixup(void) #ifdef CONFIG_SOC_AU1500 int i; struct pci_dev *dev; - - virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, - Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); + + virt_io_addr = (unsigned long) ioremap(Au1500_PCI_IO_START, + Au1500_PCI_IO_END - + Au1500_PCI_IO_START + 1); if (!virt_io_addr) { printk(KERN_ERR "Unable to ioremap pci space\n"); @@ -72,17 +73,18 @@ void __init pcibios_fixup(void) set_io_port_base(virt_io_addr); #endif -#ifdef CONFIG_MIPS_PB1000 /* This is truly board specific */ +#ifdef CONFIG_MIPS_PB1000 /* This is truly board specific */ unsigned long pci_mem_start = (unsigned long) PCI_MEM_START; - au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0 - au_writel(0, SDRAM_MBAR); // set mbar to 0 - au_writel(0x2, SDRAM_CMD); // enable memory accesses + au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0 + au_writel(0, SDRAM_MBAR); // set mbar to 0 + au_writel(0x2, SDRAM_CMD); // enable memory accesses au_sync_delay(1); // set extend byte to mbar of ext slot au_writel(((pci_mem_start >> 24) & 0xff) | - (1 << 8 | 1 << 9 | 1 << 10 | 1 << 27), PCI_BRIDGE_CONFIG); + (1 << 8 | 1 << 9 | 1 << 10 | 1 << 27), + PCI_BRIDGE_CONFIG); DBG("Set bridge config to %x\n", au_readl(PCI_BRIDGE_CONFIG)); #endif } @@ -101,10 +103,10 @@ void __init pcibios_fixup_irqs(void) dev->irq = 0xff; slot = PCI_SLOT(dev->devfn); switch (slot) { - case 12: - case 13: - dev->irq = AU1000_PCI_INTA; - break; + case 12: + case 13: + dev->irq = AU1000_PCI_INTA; + break; } pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); @@ -117,6 +119,6 @@ unsigned int pcibios_assign_all_busses(void) return 0; } -static void fixup_resource(int r_num, struct pci_dev *dev) +static void fixup_resource(int r_num, struct pci_dev *dev) { } diff --git a/arch/mips/pci/fixup-ite8172g.c b/arch/mips/pci/fixup-ite8172g.c index 676393fe1ed..a1c56a5c55c 100644 --- a/arch/mips/pci/fixup-ite8172g.c +++ b/arch/mips/pci/fixup-ite8172g.c @@ -48,15 +48,15 @@ void __init pcibios_fixup_irqs(void) unsigned int slot, func; unsigned char pin; struct pci_dev *dev; - const int internal_func_irqs[7] = { - IT8172_AC97_IRQ, - IT8172_DMA_IRQ, - IT8172_CDMA_IRQ, - IT8172_USB_IRQ, - IT8172_BRIDGE_MASTER_IRQ, - IT8172_IDE_IRQ, - IT8172_MC68K_IRQ - }; + const int internal_func_irqs[7] = { + IT8172_AC97_IRQ, + IT8172_DMA_IRQ, + IT8172_CDMA_IRQ, + IT8172_USB_IRQ, + IT8172_BRIDGE_MASTER_IRQ, + IT8172_IDE_IRQ, + IT8172_MC68K_IRQ + }; pci_for_each_dev(dev) { if (dev->bus->number != 0) { @@ -68,121 +68,121 @@ void __init pcibios_fixup_irqs(void) func = PCI_FUNC(dev->devfn); switch (slot) { - case 0x01: - /* - * Internal device 1 is actually 7 different - * internal devices on the IT8172G (a multi- - * function device). - */ - if (func < 7) + case 0x01: + /* + * Internal device 1 is actually 7 different + * internal devices on the IT8172G (a multi- + * function device). + */ + if (func < 7) dev->irq = internal_func_irqs[func]; - break; - case 0x10: - switch (pin) { - case 1: /* pin A */ - dev->irq = IT8172_PCI_INTA_IRQ; - break; - case 2: /* pin B */ - dev->irq = IT8172_PCI_INTB_IRQ; - break; - case 3: /* pin C */ - dev->irq = IT8172_PCI_INTC_IRQ; - break; - case 4: /* pin D */ - dev->irq = IT8172_PCI_INTD_IRQ; - break; - default: - dev->irq = 0xff; - break; - - } - break; - case 0x11: - switch (pin) { - case 1: /* pin A */ - dev->irq = IT8172_PCI_INTA_IRQ; - break; - case 2: /* pin B */ - dev->irq = IT8172_PCI_INTB_IRQ; - break; - case 3: /* pin C */ - dev->irq = IT8172_PCI_INTC_IRQ; - break; - case 4: /* pin D */ - dev->irq = IT8172_PCI_INTD_IRQ; - break; - default: - dev->irq = 0xff; - break; + break; + case 0x10: + switch (pin) { + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + default: + dev->irq = 0xff; + break; - } - break; - case 0x12: - switch (pin) { - case 1: /* pin A */ - dev->irq = IT8172_PCI_INTB_IRQ; - break; - case 2: /* pin B */ - dev->irq = IT8172_PCI_INTC_IRQ; - break; - case 3: /* pin C */ - dev->irq = IT8172_PCI_INTD_IRQ; - break; - case 4: /* pin D */ - dev->irq = IT8172_PCI_INTA_IRQ; - break; - default: - dev->irq = 0xff; - break; + } + break; + case 0x11: + switch (pin) { + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + default: + dev->irq = 0xff; + break; - } - break; - case 0x13: - switch (pin) { - case 1: /* pin A */ - dev->irq = IT8172_PCI_INTC_IRQ; - break; - case 2: /* pin B */ - dev->irq = IT8172_PCI_INTD_IRQ; - break; - case 3: /* pin C */ - dev->irq = IT8172_PCI_INTA_IRQ; - break; - case 4: /* pin D */ - dev->irq = IT8172_PCI_INTB_IRQ; - break; - default: - dev->irq = 0xff; - break; + } + break; + case 0x12: + switch (pin) { + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + default: + dev->irq = 0xff; + break; - } - break; - case 0x14: - switch (pin) { - case 1: /* pin A */ - dev->irq = IT8172_PCI_INTD_IRQ; - break; - case 2: /* pin B */ - dev->irq = IT8172_PCI_INTA_IRQ; - break; - case 3: /* pin C */ - dev->irq = IT8172_PCI_INTB_IRQ; - break; - case 4: /* pin D */ - dev->irq = IT8172_PCI_INTC_IRQ; - break; - default: - dev->irq = 0xff; - break; + } + break; + case 0x13: + switch (pin) { + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + default: + dev->irq = 0xff; + break; - } + } + break; + case 0x14: + switch (pin) { + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTC_IRQ; break; default: - continue; /* do nothing */ + dev->irq = 0xff; + break; + + } + break; + default: + continue; /* do nothing */ } #ifdef DEBUG printk("irq fixup: slot %d, int line %d, int number %d\n", - slot, pin, dev->irq); + slot, pin, dev->irq); #endif pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); } diff --git a/arch/mips/pci/fixup-ivr.c b/arch/mips/pci/fixup-ivr.c index 400299c56b2..4d573686a47 100644 --- a/arch/mips/pci/fixup-ivr.c +++ b/arch/mips/pci/fixup-ivr.c @@ -49,15 +49,15 @@ void __init pcibios_fixup_irqs(void) unsigned int slot, func; unsigned char pin; struct pci_dev *dev; - const int internal_func_irqs[7] = { - IT8172_AC97_IRQ, - IT8172_DMA_IRQ, - IT8172_CDMA_IRQ, - IT8172_USB_IRQ, - IT8172_BRIDGE_MASTER_IRQ, - IT8172_IDE_IRQ, - IT8172_MC68K_IRQ - }; + const int internal_func_irqs[7] = { + IT8172_AC97_IRQ, + IT8172_DMA_IRQ, + IT8172_CDMA_IRQ, + IT8172_USB_IRQ, + IT8172_BRIDGE_MASTER_IRQ, + IT8172_IDE_IRQ, + IT8172_MC68K_IRQ + }; pci_for_each_dev(dev) { if (dev->bus->number != 0) @@ -68,84 +68,84 @@ void __init pcibios_fixup_irqs(void) func = PCI_FUNC(dev->devfn); switch (slot) { - case 0x01: - /* - * Internal device 1 is actually 7 different - * internal devices on the IT8172G (multi-function - * device). - */ - if (func < 7) + case 0x01: + /* + * Internal device 1 is actually 7 different + * internal devices on the IT8172G (multi-function + * device). + */ + if (func < 7) dev->irq = internal_func_irqs[func]; - break; - case 0x11: // Realtek RTL-8139 - switch (pin) { - case 0: /* pin A, hardware bug */ - case 1: /* pin A */ - dev->irq = IT8172_PCI_INTC_IRQ; - break; - case 2: /* pin B */ - dev->irq = IT8172_PCI_INTD_IRQ; - break; - case 3: /* pin C */ - dev->irq = IT8172_PCI_INTA_IRQ; - break; - case 4: /* pin D */ - dev->irq = IT8172_PCI_INTB_IRQ; - break; - default: - dev->irq = 0xff; - break; - - } + break; + case 0x11: // Realtek RTL-8139 + switch (pin) { + case 0: /* pin A, hardware bug */ + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + default: + dev->irq = 0xff; break; - case 0x12: // ivr slot - switch (pin) { - case 0: /* pin A, hardware bug */ - case 1: /* pin A */ - dev->irq = IT8172_PCI_INTB_IRQ; - break; - case 2: /* pin B */ - dev->irq = IT8172_PCI_INTB_IRQ; - break; - case 3: /* pin C */ - dev->irq = IT8172_PCI_INTC_IRQ; - break; - case 4: /* pin D */ - dev->irq = IT8172_PCI_INTD_IRQ; - break; - default: - dev->irq = 0xff; - break; - } + } + break; + case 0x12: // ivr slot + switch (pin) { + case 0: /* pin A, hardware bug */ + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + default: + dev->irq = 0xff; break; - case 0x13: // expansion slot - switch (pin) { - case 0: /* pin A, hardware bug */ - case 1: /* pin A */ - dev->irq = IT8172_PCI_INTA_IRQ; - break; - case 2: /* pin B */ - dev->irq = IT8172_PCI_INTB_IRQ; - break; - case 3: /* pin C */ - dev->irq = IT8172_PCI_INTC_IRQ; - break; - case 4: /* pin D */ - dev->irq = IT8172_PCI_INTD_IRQ; - break; - default: - dev->irq = 0xff; - break; - } + } + break; + case 0x13: // expansion slot + switch (pin) { + case 0: /* pin A, hardware bug */ + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTD_IRQ; break; default: + dev->irq = 0xff; break; + + } + break; + default: + break; } #ifdef DEBUG printk("irq fixup: slot %d, int line %d, int number %d\n", - slot, pin, dev->irq); + slot, pin, dev->irq); #endif pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); } diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index 3e11e520a23..0cbd2089d38 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -56,7 +56,7 @@ int pci_get_irq(struct pci_dev *dev, int pin) unsigned char irq = pin; /* IRQ rotation (PICMG) */ - irq--; /* 0-3 */ + irq--; /* 0-3 */ if (dev->bus->parent == NULL && PCI_SLOT(dev->devfn) == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) { /* PCI CardSlot (IDSEL=A23, DevNu=12) */ @@ -64,7 +64,8 @@ int pci_get_irq(struct pci_dev *dev, int pin) /* NOTE: JMR3927 JP1 must be set to OPEN */ irq = (irq + 2) % 4; } else if (dev->bus->parent == NULL && - PCI_SLOT(dev->devfn) == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) { + PCI_SLOT(dev->devfn) == + TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) { /* PCI CardSlot (IDSEL=A22, DevNu=11) */ /* PCIA => PCIA (IDSEL=A22) */ /* NOTE: JMR3927 JP1 must be set to OPEN */ @@ -72,13 +73,14 @@ int pci_get_irq(struct pci_dev *dev, int pin) } else { /* PCI Backplane */ irq = (irq + 3 + PCI_SLOT(dev->devfn)) % 4; -#if 0 /* ??? */ - for (bus = dev->bus; bus->parent != NULL; bus = bus->parent) { +#if 0 /* ??? */ + for (bus = dev->bus; bus->parent != NULL; + bus = bus->parent) { irq = (irq + 3 + PCI_SLOT(bus->self->devfn)) % 4; } #endif } - irq++; /* 1-4 */ + irq++; /* 1-4 */ switch (irq) { case 1: @@ -113,7 +115,7 @@ int pci_get_irq(struct pci_dev *dev, int pin) void __init pcibios_fixup_irqs(void) { unsigned char irq; - struct pci_dev *dev; + struct pci_dev *dev; pci_for_each_dev(dev) { pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); @@ -124,7 +126,8 @@ void __init pcibios_fixup_irqs(void) if (!(dev->vendor == PCI_VENDOR_ID_EFAR && dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1)) { irq = pci_get_irq(dev, irq); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + irq); } pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); diff --git a/arch/mips/pci/fixup-ocelot.c b/arch/mips/pci/fixup-ocelot.c index 576b137fac0..226b6df6bfc 100644 --- a/arch/mips/pci/fixup-ocelot.c +++ b/arch/mips/pci/fixup-ocelot.c @@ -37,35 +37,37 @@ void __devinit gt64120_board_pcibios_fixup_bus(struct pci_bus *bus) * we double-check against that assumption */ if ((devices->vendor != 0x8086) || - (devices->device != 0x1209) ) { - panic("gt64120_board_pcibios_fixup_bus: found " - "unexpected PCI device in slot 1."); + (devices->device != 0x1209)) { + panic + ("gt64120_board_pcibios_fixup_bus: found " + "unexpected PCI device in slot 1."); } - devices->irq = 2; /* irq_nr is 2 for INT0 */ + devices->irq = 2; /* irq_nr is 2 for INT0 */ } else if (PCI_SLOT(devices->devfn) == 2) { /* * Slot 2 is secondary ether port, i21143 * we double-check against that assumption */ if ((devices->vendor != 0x1011) || - (devices->device != 0x19) ) { + (devices->device != 0x19)) { panic("galileo_pcibios_fixup_bus: " "found unexpected PCI device in slot 2."); } - devices->irq = 3; /* irq_nr is 3 for INT1 */ + devices->irq = 3; /* irq_nr is 3 for INT1 */ } else if (PCI_SLOT(devices->devfn) == 4) { /* PMC Slot 1 */ - devices->irq = 8; /* irq_nr is 8 for INT6 */ + devices->irq = 8; /* irq_nr is 8 for INT6 */ } else if (PCI_SLOT(devices->devfn) == 5) { /* PMC Slot 1 */ - devices->irq = 9; /* irq_nr is 9 for INT7 */ + devices->irq = 9; /* irq_nr is 9 for INT7 */ } else { /* We don't have assign interrupts for other devices. */ devices->irq = 0xff; } /* Assign an interrupt number for the device */ - bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, devices->irq); + bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, + devices->irq); /* enable master */ bus->ops->read_word(devices, PCI_COMMAND, &cmd); diff --git a/arch/mips/pci/fixup-tb0226.c b/arch/mips/pci/fixup-tb0226.c index ca3831ff920..115385c18d4 100644 --- a/arch/mips/pci/fixup-tb0226.c +++ b/arch/mips/pci/fixup-tb0226.c @@ -37,14 +37,16 @@ void __init pcibios_fixup_irqs(void) switch (slot) { case 12: - vr41xx_set_irq_trigger(GD82559_1_PIN, TRIGGER_LEVEL, - SIGNAL_THROUGH); + vr41xx_set_irq_trigger(GD82559_1_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); vr41xx_set_irq_level(GD82559_1_PIN, LEVEL_LOW); dev->irq = GD82559_1_IRQ; break; case 13: - vr41xx_set_irq_trigger(GD82559_2_PIN, TRIGGER_LEVEL, - SIGNAL_THROUGH); + vr41xx_set_irq_trigger(GD82559_2_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); vr41xx_set_irq_level(GD82559_2_PIN, LEVEL_LOW); dev->irq = GD82559_2_IRQ; break; @@ -53,23 +55,26 @@ void __init pcibios_fixup_irqs(void) switch (pin) { case 1: vr41xx_set_irq_trigger(UPD720100_INTA_PIN, - TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(UPD720100_INTA_PIN, LEVEL_LOW); + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(UPD720100_INTA_PIN, + LEVEL_LOW); dev->irq = UPD720100_INTA_IRQ; break; case 2: vr41xx_set_irq_trigger(UPD720100_INTB_PIN, - TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(UPD720100_INTB_PIN, LEVEL_LOW); + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(UPD720100_INTB_PIN, + LEVEL_LOW); dev->irq = UPD720100_INTB_IRQ; break; case 3: vr41xx_set_irq_trigger(UPD720100_INTC_PIN, - TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(UPD720100_INTC_PIN, LEVEL_LOW); + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(UPD720100_INTC_PIN, + LEVEL_LOW); dev->irq = UPD720100_INTC_IRQ; break; } diff --git a/arch/mips/pci/fixup-tb0229.c b/arch/mips/pci/fixup-tb0229.c index dd17cfa8654..fbcb170d312 100644 --- a/arch/mips/pci/fixup-tb0229.c +++ b/arch/mips/pci/fixup-tb0229.c @@ -39,21 +39,27 @@ void __init pcibios_fixup_irqs(void) switch (slot) { case 12: - vr41xx_set_irq_trigger(TB0219_PCI_SLOT1_PIN , TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT1_PIN, LEVEL_LOW); + vr41xx_set_irq_trigger(TB0219_PCI_SLOT1_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(TB0219_PCI_SLOT1_PIN, + LEVEL_LOW); dev->irq = TB0219_PCI_SLOT1_IRQ; break; case 13: - vr41xx_set_irq_trigger(TB0219_PCI_SLOT2_PIN , TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT2_PIN, LEVEL_LOW); + vr41xx_set_irq_trigger(TB0219_PCI_SLOT2_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(TB0219_PCI_SLOT2_PIN, + LEVEL_LOW); dev->irq = TB0219_PCI_SLOT2_IRQ; break; case 14: - vr41xx_set_irq_trigger(TB0219_PCI_SLOT3_PIN , TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT3_PIN, LEVEL_LOW); + vr41xx_set_irq_trigger(TB0219_PCI_SLOT3_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(TB0219_PCI_SLOT3_PIN, + LEVEL_LOW); dev->irq = TB0219_PCI_SLOT3_IRQ; break; default: diff --git a/arch/mips/pci/fixups-ev96100.c b/arch/mips/pci/fixups-ev96100.c index 3465749900d..7797f04df36 100644 --- a/arch/mips/pci/fixups-ev96100.c +++ b/arch/mips/pci/fixups-ev96100.c @@ -54,34 +54,34 @@ void __init pcibios_fixup_irqs(void) unsigned short gt_devid = get_gt_devid(); /* - ** EV96100/A interrupt routing for pci bus 0 - ** - ** Note: EV96100A board with irq jumper set on 'VxWorks' - ** for EV96100 compatibility. - */ + ** EV96100/A interrupt routing for pci bus 0 + ** + ** Note: EV96100A board with irq jumper set on 'VxWorks' + ** for EV96100 compatibility. + */ pci_for_each_dev(dev) { if (dev->bus->number != 0) return; slot = PCI_SLOT(dev->devfn); - pci_read_config_dword(dev, PCI_SUBSYSTEM_VENDOR_ID, &vendor); + pci_read_config_dword(dev, PCI_SUBSYSTEM_VENDOR_ID, + &vendor); #ifdef DEBUG printk("devfn %x, slot %d devid %x\n", - dev->devfn, slot, gt_devid); + dev->devfn, slot, gt_devid); #endif /* fixup irq line based on slot # */ if (slot == 8) { dev->irq = 5; pci_write_config_byte(dev, PCI_INTERRUPT_LINE, - dev->irq); - } - else if (slot == 9) { + dev->irq); + } else if (slot == 9) { dev->irq = 2; pci_write_config_byte(dev, PCI_INTERRUPT_LINE, - dev->irq); + dev->irq); } } } diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c index f3bdcb7d309..e03bc59596e 100644 --- a/arch/mips/pci/ops-au1000.c +++ b/arch/mips/pci/ops-au1000.c @@ -47,29 +47,29 @@ #ifdef DEBUG #define DBG(x...) printk(x) #else -#define DBG(x...) +#define DBG(x...) #endif /* TBD */ static struct resource pci_io_resource = { - "pci IO space", - (u32)PCI_IO_START, - (u32)PCI_IO_END, + "pci IO space", + (u32) PCI_IO_START, + (u32) PCI_IO_END, IORESOURCE_IO }; static struct resource pci_mem_resource = { - "pci memory space", - (u32)PCI_MEM_START, - (u32)PCI_MEM_END, + "pci memory space", + (u32) PCI_MEM_START, + (u32) PCI_MEM_END, IORESOURCE_MEM }; extern struct pci_ops au1x_pci_ops; struct pci_channel mips_pci_channels[] = { - {&au1x_pci_ops, &pci_io_resource, &pci_mem_resource, - PCI_FIRST_DEVFN,PCI_LAST_DEVFN}, + {&au1x_pci_ops, &pci_io_resource, &pci_mem_resource, + PCI_FIRST_DEVFN, PCI_LAST_DEVFN}, {(struct pci_ops *) NULL, (struct resource *) NULL, (struct resource *) NULL, (int) NULL, (int) NULL} }; @@ -103,9 +103,10 @@ static int config_access(unsigned char access_type, struct pci_dev *dev, au_sync_udelay(1); DBG("config_access: %d bus %d dev_fn %x at %x *data %x, conf %x\n", - access_type, bus, dev_fn, where, *data, config); + access_type, bus, dev_fn, where, *data, config); - DBG("bridge config reg: %x (%x)\n", au_readl(PCI_BRIDGE_CONFIG), *data); + DBG("bridge config reg: %x (%x)\n", au_readl(PCI_BRIDGE_CONFIG), + *data); if (au_readl(PCI_BRIDGE_CONFIG) & (1 << 16)) { *data = 0xffffffff; @@ -117,48 +118,54 @@ static int config_access(unsigned char access_type, struct pci_dev *dev, #else -static int config_access(unsigned char access_type, struct pci_bus *bus, - unsigned int devfn, unsigned char where, u32 *data) +static int config_access(unsigned char access_type, struct pci_bus *bus, + unsigned int devfn, unsigned char where, + u32 * data) { #ifdef CONFIG_SOC_AU1500 unsigned int device = PCI_SLOT(devfn); unsigned int function = PCI_FUNC(devfn); unsigned long config, status; - unsigned long cfg_addr; + unsigned long cfg_addr; if (device > 19) { *data = 0xffffffff; return -1; } - au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)), - Au1500_PCI_STATCMD); + au_writel(((0x2000 << 16) | + (au_readl(Au1500_PCI_STATCMD) & 0xffff)), + Au1500_PCI_STATCMD); //au_writel(au_readl(Au1500_PCI_CFG) & ~PCI_ERROR, Au1500_PCI_CFG); au_sync_udelay(1); - /* setup the config window */ - if (bus->number == 0) { - cfg_addr = (unsigned long)ioremap(Au1500_EXT_CFG | - ((1<number<<16) | (device<<11), 0x00100000); - } + /* setup the config window */ + if (bus->number == 0) { + cfg_addr = (unsigned long) ioremap(Au1500_EXT_CFG | + ((1 << device) << 11), + 0x00100000); + } else { + cfg_addr = (unsigned long) ioremap(Au1500_EXT_CFG_TYPE1 | + (bus-> + number << 16) | (device + << + 11), + 0x00100000); + } - if (!cfg_addr) - panic (KERN_ERR "PCI unable to ioremap cfg space\n"); + if (!cfg_addr) + panic(KERN_ERR "PCI unable to ioremap cfg space\n"); - /* setup the lower bits of the 36 bit address */ - config = cfg_addr | (function << 8) | (where & ~0x3); + /* setup the lower bits of the 36 bit address */ + config = cfg_addr | (function << 8) | (where & ~0x3); #if 0 if (access_type == PCI_ACCESS_WRITE) { printk("cfg write: "); - } - else { + } else { printk("cfg read: "); } - printk("devfn %x, device %x func %x \n", devfn, device, function); + printk("devfn %x, device %x func %x \n", devfn, device, function); if (access_type == PCI_ACCESS_WRITE) { printk("data %x\n", *data); } @@ -172,11 +179,11 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, au_sync_udelay(2); - DBG("config_access: %d bus %d device %d at %x *data %x, conf %x\n", - access_type, bus->number, device, where, *data, config); + DBG("config_access: %d bus %d device %d at %x *data %x, conf %x\n", + access_type, bus->number, device, where, *data, config); - /* unmap io space */ - iounmap( (void *)cfg_addr ); + /* unmap io space */ + iounmap((void *) cfg_addr); /* check master abort */ status = au_readl(Au1500_PCI_STATCMD); @@ -185,7 +192,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, printk("read data: %x\n", *data); } #endif - if (status & (1<<29)) { + if (status & (1 << 29)) { *data = 0xffffffff; return -1; } else if ((status >> 28) & 0xf) { @@ -199,34 +206,37 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, } #endif -static int read_config_byte(struct pci_bus *bus, unsigned int devfn, - int where, u8 * val) +static int read_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 * val) { u32 data; int ret; ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (where & 1) data >>= 8; - if (where & 2) data >>= 16; - *val = data & 0xff; + if (where & 1) + data >>= 8; + if (where & 2) + data >>= 16; + *val = data & 0xff; return ret; } -static int read_config_word(struct pci_bus *bus, unsigned int devfn, - int where, u16 * val) +static int read_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 * val) { u32 data; int ret; ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (where & 2) data >>= 16; - *val = data & 0xffff; + if (where & 2) + data >>= 16; + *val = data & 0xffff; return ret; } -static int read_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, u32 * val) +static int read_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 * val) { int ret; @@ -234,8 +244,9 @@ static int read_config_dword(struct pci_bus *bus, unsigned int devfn, return ret; } -static int -write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val) +static int +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, + u8 val) { u32 data = 0; @@ -243,7 +254,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val) return -1; data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + (val << ((where & 3) << 3)); if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) return -1; @@ -251,62 +262,64 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val) return PCIBIOS_SUCCESSFUL; } -static int -write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val) +static int +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, + u16 val) { - u32 data = 0; + u32 data = 0; if (where & 1) return PCIBIOS_BAD_REGISTER_NUMBER; - if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + (val << ((where & 3) << 3)); if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return -1; + return -1; return PCIBIOS_SUCCESSFUL; } -static int -write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) +static int +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, + u32 val) { if (where & 3) return PCIBIOS_BAD_REGISTER_NUMBER; if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) - return -1; + return -1; return PCIBIOS_SUCCESSFUL; } -static int config_read (struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) +static int config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) { switch (size) { - case 1: - return read_config_byte(bus, devfn, where, (u8 *)val); - case 2: - return read_config_word(bus, devfn, where, (u16 *)val); - default: - return read_config_dword(bus, devfn, where, val); + case 1: + return read_config_byte(bus, devfn, where, (u8 *) val); + case 2: + return read_config_word(bus, devfn, where, (u16 *) val); + default: + return read_config_dword(bus, devfn, where, val); } } -static int config_write (struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) +static int config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) { switch (size) { - case 1: - return write_config_byte(bus, devfn, where, (u8)val); - case 2: - return write_config_word(bus, devfn, where, (u16)val); - default: - return write_config_dword(bus, devfn, where, val); + case 1: + return write_config_byte(bus, devfn, where, (u8) val); + case 2: + return write_config_word(bus, devfn, where, (u16) val); + default: + return write_config_dword(bus, devfn, where, val); } } diff --git a/arch/mips/pci/ops-ddb5074.c b/arch/mips/pci/ops-ddb5074.c index 844a7a58a56..bfb773833ba 100644 --- a/arch/mips/pci/ops-ddb5074.c +++ b/arch/mips/pci/ops-ddb5074.c @@ -30,12 +30,12 @@ * original values for future restoring. */ struct pci_config_swap { - u32 pdar; - u32 pmr; - u32 config_base; - u32 config_size; - u32 pdar_backup; - u32 pmr_backup; + u32 pdar; + u32 pmr; + u32 config_base; + u32 config_size; + u32 pdar_backup; + u32 pmr_backup; }; /* @@ -48,25 +48,25 @@ struct pci_config_swap ext_pci_swap = { DDB_PCI_CONFIG_SIZE }; -static int pci_config_workaround=1; +static int pci_config_workaround = 1; /* * access config space */ -static inline u32 ddb_access_config_base(struct pci_config_swap *swap, - u32 bus,/* 0 means top level bus */ +static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ u32 slot_num) { u32 pci_addr = 0; u32 pciinit_offset = 0; - u32 virt_addr = swap->config_base; + u32 virt_addr = swap->config_base; u32 option; if (pci_config_workaround) { - if (slot_num == 5) slot_num = 14; - } - else { - if (slot_num == 5) return DDB_BASE + DDB_PCI_BASE; + if (slot_num == 5) + slot_num = 14; + } else { + if (slot_num == 5) + return DDB_BASE + DDB_PCI_BASE; } /* minimum pdar (window) size is 2MB */ @@ -80,10 +80,7 @@ static inline u32 ddb_access_config_base(struct pci_config_swap *swap, swap->pmr_backup = ddb_in32(swap->pmr); /* set the pdar (pci window) register */ - ddb_set_pdar(swap->pdar, - swap->config_base, - swap->config_size, - 32, /* 32 bit wide */ + ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ 0, /* not on local memory bus */ 0); /* not visible from PCI bus (N/A) */ @@ -97,7 +94,8 @@ static inline u32 ddb_access_config_base(struct pci_config_swap *swap, } else { /* type 1 config */ pci_addr = 0x00040000 << slot_num; - panic("ddb_access_config_base: we don't support type 1 config Yet"); + panic + ("ddb_access_config_base: we don't support type 1 config Yet"); } /* @@ -109,14 +107,15 @@ static inline u32 ddb_access_config_base(struct pci_config_swap *swap, virt_addr = KSEG1ADDR(swap->config_base + pci_addr); pciinit_offset = 0; } else { - db_assert( (pci_addr & (swap->config_size - 1)) == 0); + db_assert((pci_addr & (swap->config_size - 1)) == 0); virt_addr = KSEG1ADDR(swap->config_base); pciinit_offset = pci_addr; } /* set the pmr register */ option = DDB_PCI_ACCESS_32; - if (bus != 0) option |= DDB_PCI_CFGTYPE1; + if (bus != 0) + option |= DDB_PCI_CFGTYPE1; ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); return virt_addr; @@ -129,9 +128,7 @@ static inline void ddb_close_config_base(struct pci_config_swap *swap) } static int read_config_dword(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u32 *val) + struct pci_dev *dev, u32 where, u32 * val) { u32 bus, slot_num, func_num; u32 base; @@ -150,46 +147,43 @@ static int read_config_dword(struct pci_config_swap *swap, slot_num = PCI_SLOT(dev->devfn); func_num = PCI_FUNC(dev->devfn); base = ddb_access_config_base(swap, bus, slot_num); - *val = *(volatile u32*) (base + (func_num << 8) + where); + *val = *(volatile u32 *) (base + (func_num << 8) + where); ddb_close_config_base(swap); return PCIBIOS_SUCCESSFUL; } static int read_config_word(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u16 *val) + struct pci_dev *dev, u32 where, u16 * val) { - int status; - u32 result; + int status; + u32 result; db_assert((where & 1) == 0); - status = read_config_dword(swap, dev, where & ~3, &result); - if (where & 2) result >>= 16; - *val = result & 0xffff; - return status; + status = read_config_dword(swap, dev, where & ~3, &result); + if (where & 2) + result >>= 16; + *val = result & 0xffff; + return status; } static int read_config_byte(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u8 *val) + struct pci_dev *dev, u32 where, u8 * val) { - int status; - u32 result; - - status = read_config_dword(swap, dev, where & ~3, &result); - if (where & 1) result >>= 8; - if (where & 2) result >>= 16; - *val = result & 0xff; - return status; + int status; + u32 result; + + status = read_config_dword(swap, dev, where & ~3, &result); + if (where & 1) + result >>= 8; + if (where & 2) + result >>= 16; + *val = result & 0xff; + return status; } static int write_config_dword(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u32 val) + struct pci_dev *dev, u32 where, u32 val) { u32 bus, slot_num, func_num; u32 base; @@ -208,49 +202,47 @@ static int write_config_dword(struct pci_config_swap *swap, slot_num = PCI_SLOT(dev->devfn); func_num = PCI_FUNC(dev->devfn); base = ddb_access_config_base(swap, bus, slot_num); - *(volatile u32*) (base + (func_num << 8) + where) = val; + *(volatile u32 *) (base + (func_num << 8) + where) = val; ddb_close_config_base(swap); return PCIBIOS_SUCCESSFUL; } static int write_config_word(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u16 val) + struct pci_dev *dev, u32 where, u16 val) { - int status, shift=0; + int status, shift = 0; u32 result; db_assert((where & 1) == 0); status = read_config_dword(swap, dev, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) return status; - - if (where & 2) - shift += 16; - result &= ~(0xffff << shift); - result |= val << shift; - return write_config_dword(swap, dev, where & ~3, result); + if (status != PCIBIOS_SUCCESSFUL) + return status; + + if (where & 2) + shift += 16; + result &= ~(0xffff << shift); + result |= val << shift; + return write_config_dword(swap, dev, where & ~3, result); } static int write_config_byte(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u8 val) + struct pci_dev *dev, u32 where, u8 val) { - int status, shift=0; + int status, shift = 0; u32 result; status = read_config_dword(swap, dev, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) return status; - - if (where & 2) - shift += 16; - if (where & 1) - shift += 8; - result &= ~(0xff << shift); - result |= val << shift; - return write_config_dword(swap, dev, where & ~3, result); + if (status != PCIBIOS_SUCCESSFUL) + return status; + + if (where & 2) + shift += 16; + if (where & 1) + shift += 8; + result &= ~(0xff << shift); + result |= val << shift; + return write_config_dword(swap, dev, where & ~3, result); } #define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \ @@ -263,14 +255,14 @@ static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, uni } MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap) -MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap) -MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap) + MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap) + MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap) -MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap) -MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap) -MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap) -struct pci_ops ddb5476_ext_pci_ops ={ +struct pci_ops ddb5476_ext_pci_ops = { extpci_read_config_byte, extpci_read_config_word, extpci_read_config_dword, @@ -294,8 +286,8 @@ void jsun_scan_pci_bus(void) dev.bus = &bus; dev.sysdata = NULL; - /* scan ext pci bus and io pci bus*/ - for (j=0; j< 1; j++) { + /* scan ext pci bus and io pci bus */ + for (j = 0; j < 1; j++) { printk(KERN_INFO "scan ddb5476 external PCI bus:\n"); bus.ops = &ddb5476_ext_pci_ops; @@ -307,11 +299,12 @@ void jsun_scan_pci_bus(void) dev.devfn = devfn; db_verify(pci_read_config_dword(&dev, 0, &temp), - == PCIBIOS_SUCCESSFUL); - if (temp == 0xffffffff) continue; + == PCIBIOS_SUCCESSFUL); + if (temp == 0xffffffff) + continue; - printk(KERN_INFO "slot %d: (addr %d) \n", devfn/8, - 11+devfn/8); + printk(KERN_INFO "slot %d: (addr %d) \n", + devfn / 8, 11 + devfn / 8); /* verify read word and byte */ db_verify(pci_read_config_word(&dev, 2, &temp16), @@ -324,13 +317,14 @@ void jsun_scan_pci_bus(void) == PCIBIOS_SUCCESSFUL); db_assert(temp8 == ((temp >> 8) & 0xff)); - for (i=0; i < 16; i++) { - if ((i%4) == 0) + for (i = 0; i < 16; i++) { + if ((i % 4) == 0) printk(KERN_INFO); - db_verify(pci_read_config_dword(&dev, i*4, &temp), + db_verify(pci_read_config_dword + (&dev, i * 4, &temp), == PCIBIOS_SUCCESSFUL); printk("\t%08X", temp); - if ((i%4) == 3) + if ((i % 4) == 3) printk("\n"); } } diff --git a/arch/mips/pci/ops-ddb5476.c b/arch/mips/pci/ops-ddb5476.c index 407d4c3027c..1953aa09f88 100644 --- a/arch/mips/pci/ops-ddb5476.c +++ b/arch/mips/pci/ops-ddb5476.c @@ -30,12 +30,12 @@ * original values for future restoring. */ struct pci_config_swap { - u32 pdar; - u32 pmr; - u32 config_base; - u32 config_size; - u32 pdar_backup; - u32 pmr_backup; + u32 pdar; + u32 pmr; + u32 config_base; + u32 config_size; + u32 pdar_backup; + u32 pmr_backup; }; /* @@ -48,29 +48,30 @@ struct pci_config_swap ext_pci_swap = { DDB_PCI_CONFIG_SIZE }; -static int pci_config_workaround=1; +static int pci_config_workaround = 1; /* * access config space */ -static inline u32 ddb_access_config_base(struct pci_config_swap *swap, - u32 bus,/* 0 means top level bus */ +static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ u32 slot_num) { u32 pci_addr = 0; u32 pciinit_offset = 0; - u32 virt_addr = swap->config_base; + u32 virt_addr = swap->config_base; u32 option; if (pci_config_workaround) { /* [jsun] work around Vrc5476 controller itself, returnning * slot 0 essentially makes vrc5476 invisible */ - if (slot_num == 12) slot_num = 0; + if (slot_num == 12) + slot_num = 0; #if 0 /* BUG : skip P2P bridge for now */ - if (slot_num == 5) slot_num = 0; + if (slot_num == 5) + slot_num = 0; #endif } else { @@ -95,10 +96,7 @@ static inline u32 ddb_access_config_base(struct pci_config_swap *swap, swap->pmr_backup = ddb_in32(swap->pmr); /* set the pdar (pci window) register */ - ddb_set_pdar(swap->pdar, - swap->config_base, - swap->config_size, - 32, /* 32 bit wide */ + ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ 0, /* not on local memory bus */ 0); /* not visible from PCI bus (N/A) */ @@ -124,14 +122,15 @@ static inline u32 ddb_access_config_base(struct pci_config_swap *swap, virt_addr = KSEG1ADDR(swap->config_base + pci_addr); pciinit_offset = 0; } else { - db_assert( (pci_addr & (swap->config_size - 1)) == 0); + db_assert((pci_addr & (swap->config_size - 1)) == 0); virt_addr = KSEG1ADDR(swap->config_base); pciinit_offset = pci_addr; } /* set the pmr register */ option = DDB_PCI_ACCESS_32; - if (bus != 0) option |= DDB_PCI_CFGTYPE1; + if (bus != 0) + option |= DDB_PCI_CFGTYPE1; ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); return virt_addr; @@ -144,9 +143,7 @@ static inline void ddb_close_config_base(struct pci_config_swap *swap) } static int read_config_dword(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u32 *val) + struct pci_dev *dev, u32 where, u32 * val) { u32 bus, slot_num, func_num; u32 base; @@ -165,46 +162,43 @@ static int read_config_dword(struct pci_config_swap *swap, slot_num = PCI_SLOT(dev->devfn); func_num = PCI_FUNC(dev->devfn); base = ddb_access_config_base(swap, bus, slot_num); - *val = *(volatile u32*) (base + (func_num << 8) + where); + *val = *(volatile u32 *) (base + (func_num << 8) + where); ddb_close_config_base(swap); return PCIBIOS_SUCCESSFUL; } static int read_config_word(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u16 *val) + struct pci_dev *dev, u32 where, u16 * val) { - int status; - u32 result; + int status; + u32 result; db_assert((where & 1) == 0); - status = read_config_dword(swap, dev, where & ~3, &result); - if (where & 2) result >>= 16; - *val = result & 0xffff; - return status; + status = read_config_dword(swap, dev, where & ~3, &result); + if (where & 2) + result >>= 16; + *val = result & 0xffff; + return status; } static int read_config_byte(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u8 *val) + struct pci_dev *dev, u32 where, u8 * val) { - int status; - u32 result; - - status = read_config_dword(swap, dev, where & ~3, &result); - if (where & 1) result >>= 8; - if (where & 2) result >>= 16; - *val = result & 0xff; - return status; + int status; + u32 result; + + status = read_config_dword(swap, dev, where & ~3, &result); + if (where & 1) + result >>= 8; + if (where & 2) + result >>= 16; + *val = result & 0xff; + return status; } static int write_config_dword(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u32 val) + struct pci_dev *dev, u32 where, u32 val) { u32 bus, slot_num, func_num; u32 base; @@ -223,49 +217,47 @@ static int write_config_dword(struct pci_config_swap *swap, slot_num = PCI_SLOT(dev->devfn); func_num = PCI_FUNC(dev->devfn); base = ddb_access_config_base(swap, bus, slot_num); - *(volatile u32*) (base + (func_num << 8) + where) = val; + *(volatile u32 *) (base + (func_num << 8) + where) = val; ddb_close_config_base(swap); return PCIBIOS_SUCCESSFUL; } static int write_config_word(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u16 val) + struct pci_dev *dev, u32 where, u16 val) { - int status, shift=0; + int status, shift = 0; u32 result; db_assert((where & 1) == 0); status = read_config_dword(swap, dev, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) return status; - - if (where & 2) - shift += 16; - result &= ~(0xffff << shift); - result |= val << shift; - return write_config_dword(swap, dev, where & ~3, result); + if (status != PCIBIOS_SUCCESSFUL) + return status; + + if (where & 2) + shift += 16; + result &= ~(0xffff << shift); + result |= val << shift; + return write_config_dword(swap, dev, where & ~3, result); } static int write_config_byte(struct pci_config_swap *swap, - struct pci_dev *dev, - u32 where, - u8 val) + struct pci_dev *dev, u32 where, u8 val) { - int status, shift=0; + int status, shift = 0; u32 result; status = read_config_dword(swap, dev, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) return status; - - if (where & 2) - shift += 16; - if (where & 1) - shift += 8; - result &= ~(0xff << shift); - result |= val << shift; - return write_config_dword(swap, dev, where & ~3, result); + if (status != PCIBIOS_SUCCESSFUL) + return status; + + if (where & 2) + shift += 16; + if (where & 1) + shift += 8; + result &= ~(0xff << shift); + result |= val << shift; + return write_config_dword(swap, dev, where & ~3, result); } #define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \ @@ -278,14 +270,14 @@ static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, uni } MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap) -MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap) -MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap) + MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap) + MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap) -MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap) -MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap) -MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap) -struct pci_ops ddb5476_ext_pci_ops ={ +struct pci_ops ddb5476_ext_pci_ops = { extpci_read_config_byte, extpci_read_config_word, extpci_read_config_dword, @@ -309,8 +301,8 @@ void jsun_scan_pci_bus(void) dev.bus = &bus; dev.sysdata = NULL; - /* scan ext pci bus and io pci bus*/ - for (j=0; j< 1; j++) { + /* scan ext pci bus and io pci bus */ + for (j = 0; j < 1; j++) { printk(KERN_INFO "scan ddb5476 external PCI bus:\n"); bus.ops = &ddb5476_ext_pci_ops; @@ -322,11 +314,12 @@ void jsun_scan_pci_bus(void) dev.devfn = devfn; db_verify(pci_read_config_dword(&dev, 0, &temp), - == PCIBIOS_SUCCESSFUL); - if (temp == 0xffffffff) continue; + == PCIBIOS_SUCCESSFUL); + if (temp == 0xffffffff) + continue; - printk(KERN_INFO "slot %d: (addr %d) \n", devfn/8, - 11+devfn/8); + printk(KERN_INFO "slot %d: (addr %d) \n", + devfn / 8, 11 + devfn / 8); /* verify read word and byte */ db_verify(pci_read_config_word(&dev, 2, &temp16), @@ -339,13 +332,14 @@ void jsun_scan_pci_bus(void) == PCIBIOS_SUCCESSFUL); db_assert(temp8 == ((temp >> 8) & 0xff)); - for (i=0; i < 16; i++) { - if ((i%4) == 0) + for (i = 0; i < 16; i++) { + if ((i % 4) == 0) printk(KERN_INFO); - db_verify(pci_read_config_dword(&dev, i*4, &temp), + db_verify(pci_read_config_dword + (&dev, i * 4, &temp), == PCIBIOS_SUCCESSFUL); printk("\t%08X", temp); - if ((i%4) == 3) + if ((i % 4) == 3) printk("\n"); } } diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c index e25e5f49c84..d7b17502c31 100644 --- a/arch/mips/pci/ops-ddb5477.c +++ b/arch/mips/pci/ops-ddb5477.c @@ -34,12 +34,12 @@ * original values for future restoring. */ struct pci_config_swap { - u32 pdar; - u32 pmr; - u32 config_base; - u32 config_size; - u32 pdar_backup; - u32 pmr_backup; + u32 pdar; + u32 pmr; + u32 config_base; + u32 config_size; + u32 pdar_backup; + u32 pmr_backup; }; /* @@ -62,8 +62,7 @@ struct pci_config_swap io_pci_swap = { /* * access config space */ -static inline u32 ddb_access_config_base(struct pci_config_swap *swap, - u32 bus,/* 0 means top level bus */ +static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ u32 slot_num) { u32 pci_addr = 0; @@ -82,10 +81,7 @@ static inline u32 ddb_access_config_base(struct pci_config_swap *swap, swap->pmr_backup = ddb_in32(swap->pmr); /* set the pdar (pci window) register */ - ddb_set_pdar(swap->pdar, - swap->config_base, - swap->config_size, - 32, /* 32 bit wide */ + ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ 0, /* not on local memory bus */ 0); /* not visible from PCI bus (N/A) */ @@ -110,14 +106,15 @@ static inline u32 ddb_access_config_base(struct pci_config_swap *swap, virt_addr = KSEG1ADDR(swap->config_base + pci_addr); pciinit_offset = 0; } else { - db_assert( (pci_addr & (swap->config_size - 1)) == 0); + db_assert((pci_addr & (swap->config_size - 1)) == 0); virt_addr = KSEG1ADDR(swap->config_base); pciinit_offset = pci_addr; } /* set the pmr register */ option = DDB_PCI_ACCESS_32; - if (bus != 0) option |= DDB_PCI_CFGTYPE1; + if (bus != 0) + option |= DDB_PCI_CFGTYPE1; ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); return virt_addr; @@ -129,8 +126,8 @@ static inline void ddb_close_config_base(struct pci_config_swap *swap) ddb_out32(swap->pmr, swap->pmr_backup); } -static int read_config_dword(struct pci_config_swap *swap, struct pci_bus *bus, - u32 where, u32 *val) +static int read_config_dword(struct pci_config_swap *swap, + struct pci_bus *bus, u32 where, u32 * val) { u32 bus, slot_num, func_num; u32 base; @@ -149,13 +146,13 @@ static int read_config_dword(struct pci_config_swap *swap, struct pci_bus *bus, slot_num = PCI_SLOT(dev->devfn); func_num = PCI_FUNC(dev->devfn); base = ddb_access_config_base(swap, bus, slot_num); - *val = *(volatile u32*) (base + (func_num << 8) + where); + *val = *(volatile u32 *) (base + (func_num << 8) + where); ddb_close_config_base(swap); return PCIBIOS_SUCCESSFUL; } -static int read_config_word(struct pci_config_swap *swap, struct pci_bus *bus, - u32 where, u16 *val) +static int read_config_word(struct pci_config_swap *swap, + struct pci_bus *bus, u32 where, u16 * val) { int status; u32 result; @@ -163,13 +160,15 @@ static int read_config_word(struct pci_config_swap *swap, struct pci_bus *bus, db_assert((where & 1) == 0); status = read_config_dword(swap, bus, where & ~3, &result); - if (where & 2) result >>= 16; + if (where & 2) + result >>= 16; *val = result & 0xffff; return status; } -static int read_config_byte(struct pci_config_swap *swap, struct pci_bus *bus, - unsigned int devfn, u8 *val) +static int read_config_byte(struct pci_config_swap *swap, + struct pci_bus *bus, unsigned int devfn, + u8 * val) { int status; u32 result; @@ -184,8 +183,9 @@ static int read_config_byte(struct pci_config_swap *swap, struct pci_bus *bus, return status; } -static int write_config_dword(struct pci_config_swap *swap, struct pci_bus *bus, - unsigned int devfn, u32 val) +static int write_config_dword(struct pci_config_swap *swap, + struct pci_bus *bus, unsigned int devfn, + u32 val) { u32 busno, slot_num, func_num; u32 base; @@ -204,42 +204,46 @@ static int write_config_dword(struct pci_config_swap *swap, struct pci_bus *bus, slot_num = PCI_SLOT(devfn); func_num = PCI_FUNC(devfn); base = ddb_access_config_base(swap, busno, slot_num); - *(volatile u32*) (base + (func_num << 8) + where) = val; + *(volatile u32 *) (base + (func_num << 8) + where) = val; ddb_close_config_base(swap); return PCIBIOS_SUCCESSFUL; } -static int write_config_word(struct pci_config_swap *swap, struct pci_bus *bus, - unsigned int devfn, int where, u16 val) +static int write_config_word(struct pci_config_swap *swap, + struct pci_bus *bus, unsigned int devfn, + int where, u16 val) { - int status, shift=0; + int status, shift = 0; u32 result; db_assert((where & 1) == 0); status = read_config_dword(swap, dev, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) return status; + if (status != PCIBIOS_SUCCESSFUL) + return status; if (where & 2) - shift += 16; + shift += 16; result &= ~(0xffff << shift); result |= val << shift; return write_config_dword(swap, dev, where & ~3, result); } -static int write_config_byte(struct pci_config_swap *swap, struct pci_bus *bus, - unsigned int devfn, int where, u8 val) +static int write_config_byte(struct pci_config_swap *swap, + struct pci_bus *bus, unsigned int devfn, + int where, u8 val) { - int status, shift=0; + int status, shift = 0; u32 result; status = read_config_dword(swap, dev, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) return status; + if (status != PCIBIOS_SUCCESSFUL) + return status; if (where & 2) - shift += 16; + shift += 16; if (where & 1) - shift += 8; + shift += 8; result &= ~(0xff << shift); result |= val << shift; return write_config_dword(swap, dev, where & ~3, result); @@ -260,18 +264,18 @@ static int prefix##_##rw##_config(struct pci_bus *bus, int where, int size, unit } MAKE_PCI_OPS(extpci, read, &ext_pci_swap) -MAKE_PCI_OPS(extpci, write, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, &ext_pci_swap) -MAKE_PCI_OPS(iopci, read, &io_pci_swap) -MAKE_PCI_OPS(iopci, write, &io_pci_swap) + MAKE_PCI_OPS(iopci, read, &io_pci_swap) + MAKE_PCI_OPS(iopci, write, &io_pci_swap) -struct pci_ops ddb5477_ext_pci_ops ={ - .read = extpci_read_config, - .write = extpci_write_config +struct pci_ops ddb5477_ext_pci_ops = { + .read = extpci_read_config, + .write = extpci_write_config }; -struct pci_ops ddb5477_io_pci_ops ={ - .read = iopci_read_config, - .write = iopci_write_config +struct pci_ops ddb5477_io_pci_ops = { + .read = iopci_read_config, + .write = iopci_write_config }; diff --git a/arch/mips/pci/ops-ev64120.c b/arch/mips/pci/ops-ev64120.c index 5375e5e310e..121805908db 100644 --- a/arch/mips/pci/ops-ev64120.c +++ b/arch/mips/pci/ops-ev64120.c @@ -133,7 +133,8 @@ static void galileo_pcibios_set_master(struct pci_dev *dev); * pci0MapIOspace - Maps PCI0 IO space for the master. * Inputs: base and length of pci0Io */ -static void pci0MapIOspace(unsigned int pci0IoBase, unsigned int pci0IoLength) +static void pci0MapIOspace(unsigned int pci0IoBase, + unsigned int pci0IoLength) { unsigned int pci0IoTop = (unsigned int) (pci0IoBase + pci0IoLength); @@ -493,7 +494,7 @@ static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device) if (PCI_SLOT(device->devfn) == SELF) { /* This board */ GT_READ(GT_PCI0_CFGDATA_OFS, &data); return data; - } else { /* The PCI is working in LE Mode so swap the Data. */ + } else { /* The PCI is working in LE Mode so swap the Data. */ GT_READ(GT_PCI0_CFGDATA_OFS, &data); return cpu_to_le32(data); } @@ -661,8 +662,9 @@ static int galileo_pcibios_read_config_word(struct pci_dev *device, return PCIBIOS_BAD_REGISTER_NUMBER; if (bus == 0) - *val = (unsigned short) (pci0ReadConfigReg(offset, device) >> - ((offset & ~0x3) * 8)); + *val = + (unsigned short) (pci0ReadConfigReg(offset, device) >> + ((offset & ~0x3) * 8)); // if (bus == 1) *val = (unsigned short) (pci1ReadConfigReg(offset,device) >> ((offset & ~0x3) * 8)); DBG(KERN_INFO "rr: rcw dev %d offset %x %x\n", dev, offset, *val); diff --git a/arch/mips/pci/ops-ev96100.c b/arch/mips/pci/ops-ev96100.c index 48bcf460848..3d22c3b37f2 100644 --- a/arch/mips/pci/ops-ev96100.c +++ b/arch/mips/pci/ops-ev96100.c @@ -39,7 +39,7 @@ #include #include -#include +#include #include #include @@ -62,57 +62,59 @@ static struct resource pci_io_resource = { "io pci IO space", 0x10000000, 0x10000000 + 0x02000000, - IORESOURCE_IO}; + IORESOURCE_IO +}; static struct resource pci_mem_resource = { "ext pci memory space", 0x12000000, 0x12000000 + 0x02000000, - IORESOURCE_MEM}; + IORESOURCE_MEM +}; extern struct pci_ops gt96100_pci_ops; struct pci_channel mips_pci_channels[] = { - { >96100_pci_ops, &pci_io_resource, &pci_mem_resource, 1, 0xff }, - { NULL, NULL, NULL, NULL, NULL} + {>96100_pci_ops, &pci_io_resource, &pci_mem_resource, 1, 0xff}, + {NULL, NULL, NULL, NULL, NULL} }; int -static gt96100_config_access(unsigned char access_type, struct pci_dev *dev, - unsigned char where, u32 *data) +static gt96100_config_access(unsigned char access_type, + struct pci_dev *dev, unsigned char where, + u32 * data) { unsigned char bus = dev->bus->number; unsigned char dev_fn = dev->devfn; - u32 intr; + u32 intr; - if ((bus == 0) && (dev_fn >= PCI_DEVFN(31,0))) { - return -1; /* Because of a bug in the galileo (for slot 31). */ - } + if ((bus == 0) && (dev_fn >= PCI_DEVFN(31, 0))) { + return -1; /* Because of a bug in the galileo (for slot 31). */ + } /* Clear cause register bits */ GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT)); + GT_INTRCAUSE_TARABORT0_BIT)); /* Setup address */ GT_WRITE(GT_PCI0_CFGADDR_OFS, - (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) | - (dev_fn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | - ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (dev_fn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | GT_PCI0_CFGADDR_CONFIGEN_BIT); udelay(2); if (access_type == PCI_ACCESS_WRITE) { if (dev_fn != 0) { - *data = le32_to_cpu(*data); + *data = le32_to_cpu(*data); } GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); - } - else { + } else { GT_READ(GT_PCI0_CFGDATA_OFS, *data); if (dev_fn != 0) { - *data = le32_to_cpu(*data); + *data = le32_to_cpu(*data); } } @@ -121,14 +123,14 @@ static gt96100_config_access(unsigned char access_type, struct pci_dev *dev, /* Check for master or target abort */ GT_READ(GT_INTRCAUSE_OFS, intr); - if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) - { + if (intr & + (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { //printk("config access error: %x:%x\n", dev_fn,where); - /* Error occured */ + /* Error occured */ - /* Clear bits */ - GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT) ); + /* Clear bits */ + GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); if (access_type == PCI_ACCESS_READ) { *data = 0xffffffff; @@ -143,8 +145,7 @@ static gt96100_config_access(unsigned char access_type, struct pci_dev *dev, * We can't address 8 and 16 bit words directly. Instead we have to * read/write a 32bit word and mask/modify the data we actually want. */ -static int -read_config_byte (struct pci_dev *dev, int where, u8 *val) +static int read_config_byte(struct pci_dev *dev, int where, u8 * val) { u32 data = 0; @@ -154,15 +155,14 @@ read_config_byte (struct pci_dev *dev, int where, u8 *val) } *val = (data >> ((where & 3) << 3)) & 0xff; - DBG("cfg read byte: bus %d dev_fn %x where %x: val %x\n", - dev->bus->number, dev->devfn, where, *val); + DBG("cfg read byte: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, *val); return PCIBIOS_SUCCESSFUL; } -static int -read_config_word (struct pci_dev *dev, int where, u16 *val) +static int read_config_word(struct pci_dev *dev, int where, u16 * val) { u32 data = 0; @@ -175,14 +175,13 @@ read_config_word (struct pci_dev *dev, int where, u16 *val) } *val = (data >> ((where & 3) << 3)) & 0xffff; - DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n", - dev->bus->number, dev->devfn, where, *val); + DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, *val); return PCIBIOS_SUCCESSFUL; } -static int -read_config_dword (struct pci_dev *dev, int where, u32 *val) +static int read_config_dword(struct pci_dev *dev, int where, u32 * val) { u32 data = 0; @@ -195,15 +194,14 @@ read_config_dword (struct pci_dev *dev, int where, u32 *val) } *val = data; - DBG("cfg read dword: bus %d dev_fn %x where %x: val %x\n", - dev->bus->number, dev->devfn, where, *val); + DBG("cfg read dword: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, *val); return PCIBIOS_SUCCESSFUL; } -static int -write_config_byte (struct pci_dev *dev, int where, u8 val) +static int write_config_byte(struct pci_dev *dev, int where, u8 val) { u32 data = 0; @@ -211,9 +209,9 @@ write_config_byte (struct pci_dev *dev, int where, u8 val) return -1; data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - DBG("cfg write byte: bus %d dev_fn %x where %x: val %x\n", - dev->bus->number, dev->devfn, where, val); + (val << ((where & 3) << 3)); + DBG("cfg write byte: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, val); if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data)) return -1; @@ -221,46 +219,44 @@ write_config_byte (struct pci_dev *dev, int where, u8 val) return PCIBIOS_SUCCESSFUL; } -static int -write_config_word (struct pci_dev *dev, int where, u16 val) +static int write_config_word(struct pci_dev *dev, int where, u16 val) { - u32 data = 0; + u32 data = 0; if (where & 1) return PCIBIOS_BAD_REGISTER_NUMBER; - if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) - return -1; + if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) + return -1; data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - DBG("cfg write word: bus %d dev_fn %x where %x: val %x\n", - dev->bus->number, dev->devfn, where, val); + (val << ((where & 3) << 3)); + DBG("cfg write word: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, val); if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data)) - return -1; + return -1; return PCIBIOS_SUCCESSFUL; } -static int -write_config_dword(struct pci_dev *dev, int where, u32 val) +static int write_config_dword(struct pci_dev *dev, int where, u32 val) { if (where & 3) return PCIBIOS_BAD_REGISTER_NUMBER; if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &val)) - return -1; - DBG("cfg write dword: bus %d dev_fn %x where %x: val %x\n", - dev->bus->number, dev->devfn, where, val); + return -1; + DBG("cfg write dword: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, val); return PCIBIOS_SUCCESSFUL; } struct pci_ops gt96100_pci_ops = { read_config_byte, - read_config_word, + read_config_word, read_config_dword, write_config_byte, write_config_word, diff --git a/arch/mips/pci/ops-it8172.c b/arch/mips/pci/ops-it8172.c index 1aed7215001..381155a9bac 100644 --- a/arch/mips/pci/ops-it8172.c +++ b/arch/mips/pci/ops-it8172.c @@ -78,12 +78,15 @@ static struct resource pci_mem_resource_1 = { extern struct pci_ops it8172_pci_ops; struct pci_channel mips_pci_channels[] = { - { &it8172_pci_ops, &pci_io_resource, &pci_mem_resource_0, 0x10, 0xff }, - { NULL, NULL, NULL, NULL, NULL} + {&it8172_pci_ops, &pci_io_resource, &pci_mem_resource_0, 0x10, + 0xff}, + {NULL, NULL, NULL, NULL, NULL} }; static int it8172_pcibios_config_access(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, int where, u32 *data) + struct pci_bus *bus, + unsigned int devfn, int where, + u32 * data) { /* * config cycles are on 4 byte boundary only @@ -91,12 +94,11 @@ static int it8172_pcibios_config_access(unsigned char access_type, /* Setup address */ IT_WRITE(IT_CONFADDR, (bus->number << IT_BUSNUM_SHF) | - (devfn << IT_FUNCNUM_SHF) | (where & ~0x3)); + (devfn << IT_FUNCNUM_SHF) | (where & ~0x3)); if (access_type == PCI_ACCESS_WRITE) { IT_WRITE(IT_CONFDATA, *data); - } - else { + } else { IT_READ(IT_CONFDATA, *data); } @@ -112,15 +114,15 @@ static int it8172_pcibios_config_access(unsigned char access_type, * read/write a 32bit word and mask/modify the data we actually want. */ static write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) + int size, u32 val) { u32 data = 0; switch (size) { case 1: - if (it8172_pcibios_config_access(PCI_ACCESS_READ, dev, where, - &data)) - return -1; + if (it8172_pcibios_config_access + (PCI_ACCESS_READ, dev, where, &data)) + return -1; *val = (data >> ((where & 3) << 3)) & 0xff; @@ -131,9 +133,9 @@ static write_config(struct pci_bus *bus, unsigned int devfn, int where, if (where & 1) return PCIBIOS_BAD_REGISTER_NUMBER; - if (it8172_pcibios_config_access(PCI_ACCESS_READ, dev, where, - &data)) - return -1; + if (it8172_pcibios_config_access + (PCI_ACCESS_READ, dev, where, &data)) + return -1; *val = (data >> ((where & 3) << 3)) & 0xffff; DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n", @@ -146,8 +148,8 @@ static write_config(struct pci_bus *bus, unsigned int devfn, int where, if (where & 3) return PCIBIOS_BAD_REGISTER_NUMBER; - if (it8172_pcibios_config_access(PCI_ACCESS_READ, dev, where, - &data)) + if (it8172_pcibios_config_access + (PCI_ACCESS_READ, dev, where, &data)) return -1; *val = data; @@ -158,21 +160,21 @@ static write_config(struct pci_bus *bus, unsigned int devfn, int where, static write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) + int size, u32 val) { u32 data = 0; switch (size) { case 1: - if (it8172_pcibios_config_access(PCI_ACCESS_READ, dev, where, - &data)) + if (it8172_pcibios_config_access + (PCI_ACCESS_READ, dev, where, &data)) return -1; data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + (val << ((where & 3) << 3)); - if (it8172_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, - &data)) + if (it8172_pcibios_config_access + (PCI_ACCESS_WRITE, dev, where, &data)) return -1; return PCIBIOS_SUCCESSFUL; @@ -181,15 +183,15 @@ static write_config(struct pci_bus *bus, unsigned int devfn, int where, if (where & 1) return PCIBIOS_BAD_REGISTER_NUMBER; - if (it8172_pcibios_config_access(PCI_ACCESS_READ, dev, where, - &data)) - eturn -1; + if (it8172_pcibios_config_access + (PCI_ACCESS_READ, dev, where, &data)) + eturn - 1; data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + (val << ((where & 3) << 3)); - if (it8172_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, - &data)) + if (it8172_pcibios_config_access + (PCI_ACCESS_WRITE, dev, where, &data)) return -1; return PCIBIOS_SUCCESSFUL; @@ -198,17 +200,17 @@ static write_config(struct pci_bus *bus, unsigned int devfn, int where, if (where & 3) return PCIBIOS_BAD_REGISTER_NUMBER; - if (it8172_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, - &val)) - return -1; + if (it8172_pcibios_config_access + (PCI_ACCESS_WRITE, dev, where, &val)) + return -1; return PCIBIOS_SUCCESSFUL; } } struct pci_ops it8172_pci_ops = { - .read = read_config, - .write = write_config, + .read = read_config, + .write = write_config, }; unsigned __init int pcibios_assign_all_busses(void) diff --git a/arch/mips/pci/ops-jmr3927.c b/arch/mips/pci/ops-jmr3927.c index 5a13a36879b..a5ecad97fa0 100644 --- a/arch/mips/pci/ops-jmr3927.c +++ b/arch/mips/pci/ops-jmr3927.c @@ -44,21 +44,23 @@ struct resource pci_io_resource = { "pci IO space", - 0x1000, /* reserve regacy I/O space */ - 0x1000 + JMR3927_PCIIO_SIZE -1, - IORESOURCE_IO}; + 0x1000, /* reserve regacy I/O space */ + 0x1000 + JMR3927_PCIIO_SIZE - 1, + IORESOURCE_IO +}; struct resource pci_mem_resource = { "pci memory space", JMR3927_PCIMEM, - JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE -1, - IORESOURCE_MEM}; + JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1, + IORESOURCE_MEM +}; extern struct pci_ops jmr3927_pci_ops; struct pci_channel mips_pci_channels[] = { - { &jmr3927_pci_ops, &pci_io_resource, &pci_mem_resource, 0, 0xff }, - { NULL, NULL, NULL, NULL, NULL} + {&jmr3927_pci_ops, &pci_io_resource, &pci_mem_resource, 0, 0xff}, + {NULL, NULL, NULL, NULL, NULL} }; unsigned int pcibios_assign_all_busses(void) @@ -67,28 +69,27 @@ unsigned int pcibios_assign_all_busses(void) } static int -mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where, int *flagsp) +mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where, + int *flagsp) { if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0)) return -1; - tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | - (where & 0xfc); + tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | (where & 0xfc); /* clear M_ABORT and Disable M_ABORT Int. */ tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT; return 0; } -static int -check_abort(int flags) +static int check_abort(int flags) { int code = PCIBIOS_SUCCESSFUL; if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) { tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT; - code =PCIBIOS_DEVICE_NOT_FOUND; + code = PCIBIOS_DEVICE_NOT_FOUND; } return code; } @@ -97,9 +98,8 @@ check_abort(int flags) * We can't address 8 and 16 bit words directly. Instead we have to * read/write a 32bit word and mask/modify the data we actually want. */ -static int jmr3927_pcibios_read_config_byte (struct pci_dev *dev, - int where, - unsigned char *val) +static int jmr3927_pcibios_read_config_byte(struct pci_dev *dev, + int where, unsigned char *val) { int flags; unsigned char bus, func_num; @@ -118,13 +118,13 @@ static int jmr3927_pcibios_read_config_byte (struct pci_dev *dev, func_num = PCI_FUNC(dev->devfn); if (mkaddr(bus, dev->devfn, where, &flags)) return -1; - *val = *(volatile u8 *)((ulong)&tx3927_pcicptr->icd | (where&3)); + *val = + *(volatile u8 *) ((ulong) & tx3927_pcicptr->icd | (where & 3)); return check_abort(flags); } -static int jmr3927_pcibios_read_config_word (struct pci_dev *dev, - int where, - unsigned short *val) +static int jmr3927_pcibios_read_config_word(struct pci_dev *dev, + int where, unsigned short *val) { int flags; unsigned char bus, func_num; @@ -146,13 +146,14 @@ static int jmr3927_pcibios_read_config_word (struct pci_dev *dev, func_num = PCI_FUNC(dev->devfn); if (mkaddr(bus, dev->devfn, where, &flags)) return -1; - *val = le16_to_cpu(*(volatile u16 *)((ulong)&tx3927_pcicptr->icd | (where&3))); + *val = + le16_to_cpu(*(volatile u16 *) + ((ulong) & tx3927_pcicptr->icd | (where & 3))); return check_abort(flags); } -static int jmr3927_pcibios_read_config_dword (struct pci_dev *dev, - int where, - unsigned int *val) +static int jmr3927_pcibios_read_config_dword(struct pci_dev *dev, + int where, unsigned int *val) { int flags; unsigned char bus, func_num; @@ -178,9 +179,8 @@ static int jmr3927_pcibios_read_config_dword (struct pci_dev *dev, return check_abort(flags); } -static int jmr3927_pcibios_write_config_byte (struct pci_dev *dev, - int where, - unsigned char val) +static int jmr3927_pcibios_write_config_byte(struct pci_dev *dev, + int where, unsigned char val) { int flags; unsigned char bus, func_num; @@ -196,13 +196,13 @@ static int jmr3927_pcibios_write_config_byte (struct pci_dev *dev, func_num = PCI_FUNC(dev->devfn); if (mkaddr(bus, dev->devfn, where, &flags)) return -1; - *(volatile u8 *)((ulong)&tx3927_pcicptr->icd | (where&3)) = val; + *(volatile u8 *) ((ulong) & tx3927_pcicptr->icd | (where & 3)) = + val; return check_abort(flags); } -static int jmr3927_pcibios_write_config_word (struct pci_dev *dev, - int where, - unsigned short val) +static int jmr3927_pcibios_write_config_word(struct pci_dev *dev, + int where, unsigned short val) { int flags; unsigned char bus, func_num; @@ -221,13 +221,13 @@ static int jmr3927_pcibios_write_config_word (struct pci_dev *dev, func_num = PCI_FUNC(dev->devfn); if (mkaddr(bus, dev->devfn, where, &flags)) return -1; - *(volatile u16 *)((ulong)&tx3927_pcicptr->icd | (where&3)) = cpu_to_le16(val); + *(volatile u16 *) ((ulong) & tx3927_pcicptr->icd | (where & 3)) = + cpu_to_le16(val); return check_abort(flags); } -static int jmr3927_pcibios_write_config_dword (struct pci_dev *dev, - int where, - unsigned int val) +static int jmr3927_pcibios_write_config_dword(struct pci_dev *dev, + int where, unsigned int val) { int flags; unsigned char bus, func_num; @@ -259,37 +259,44 @@ struct pci_ops jmr3927_pci_ops = { }; #ifndef JMR3927_INIT_INDIRECT_PCI -inline unsigned long tc_readl(volatile __u32 *addr) +inline unsigned long tc_readl(volatile __u32 * addr) { return readl(addr); } -inline void tc_writel(unsigned long data, volatile __u32 *addr) +inline void tc_writel(unsigned long data, volatile __u32 * addr) { writel(data, addr); } #else -unsigned long tc_readl(volatile __u32 *addr) +unsigned long tc_readl(volatile __u32 * addr) { unsigned long val; addr = PHYSADDR(addr); - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)addr; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe = - (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG; - while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ; - val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata); + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) addr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) | + PCI_IPCIBE_IBE_LONG; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + val = + le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> + ipcidata); /* clear by setting */ tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; return val; } -void tc_writel(unsigned long data, volatile __u32 *addr) +void tc_writel(unsigned long data, volatile __u32 * addr) { addr = PHYSADDR(addr); - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = cpu_to_le32(data); - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)addr; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe = - (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG; - while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = + cpu_to_le32(data); + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) addr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) | + PCI_IPCIBE_IBE_LONG; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); /* clear by setting */ tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; } @@ -300,8 +307,8 @@ unsigned char tx_ioinb(unsigned char *addr) int offset; int byte; - ioaddr = (unsigned long)addr; - offset = ioaddr & 0x3; + ioaddr = (unsigned long) addr; + offset = ioaddr & 0x3; if (offset == 0) byte = 0x7; else if (offset == 1) @@ -310,11 +317,14 @@ unsigned char tx_ioinb(unsigned char *addr) byte = 0xd; else if (offset == 3) byte = 0xe; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe = + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte; - while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ; - val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata); + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + val = + le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> + ipcidata); val = val & 0xff; /* clear by setting */ tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; @@ -327,8 +337,8 @@ void tx_iooutb(unsigned long data, unsigned char *addr) int byte; data = data | (data << 8) | (data << 16) | (data << 24); - ioaddr = (unsigned long)addr; - offset = ioaddr & 0x3; + ioaddr = (unsigned long) addr; + offset = ioaddr & 0x3; if (offset == 0) byte = 0x7; else if (offset == 1) @@ -337,11 +347,12 @@ void tx_iooutb(unsigned long data, unsigned char *addr) byte = 0xd; else if (offset == 3) byte = 0xe; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = data; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe = - (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte; - while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = data; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); /* clear by setting */ tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; } @@ -352,17 +363,20 @@ unsigned short tx_ioinw(unsigned short *addr) int offset; int byte; - ioaddr = (unsigned long)addr; - offset = ioaddr & 0x3; + ioaddr = (unsigned long) addr; + offset = ioaddr & 0x3; if (offset == 0) byte = 0x3; else if (offset == 2) byte = 0xc; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe = + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte; - while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ; - val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata); + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + val = + le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> + ipcidata); val = val & 0xffff; /* clear by setting */ tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; @@ -376,17 +390,18 @@ void tx_iooutw(unsigned long data, unsigned short *addr) int byte; data = data | (data << 16); - ioaddr = (unsigned long)addr; - offset = ioaddr & 0x3; + ioaddr = (unsigned long) addr; + offset = ioaddr & 0x3; if (offset == 0) byte = 0x3; else if (offset == 2) byte = 0xc; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = data; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe = - (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte; - while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = data; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); /* clear by setting */ tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; } @@ -395,12 +410,16 @@ unsigned long tx_ioinl(unsigned int *addr) unsigned long val; __u32 ioaddr; - ioaddr = (unsigned long)addr; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe = - (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG; - while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ; - val = le32_to_cpu(*(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata); + ioaddr = (unsigned long) addr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | + PCI_IPCIBE_IBE_LONG; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + val = + le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> + ipcidata); /* clear by setting */ tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; return val; @@ -409,16 +428,19 @@ void tx_iooutl(unsigned long data, unsigned int *addr) { __u32 ioaddr; - ioaddr = (unsigned long)addr; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcidata = cpu_to_le32(data); - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipciaddr = (unsigned long)ioaddr; - *(volatile u32 *)(ulong)&tx3927_pcicptr->ipcibe = - (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | PCI_IPCIBE_IBE_LONG; - while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)) ; + ioaddr = (unsigned long) addr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = + cpu_to_le32(data); + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | + PCI_IPCIBE_IBE_LONG; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); /* clear by setting */ tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; } -void tx_insbyte(unsigned char *addr,void *buffer,unsigned int count) +void tx_insbyte(unsigned char *addr, void *buffer, unsigned int count) { unsigned char *ptr = (unsigned char *) buffer; @@ -426,7 +448,7 @@ void tx_insbyte(unsigned char *addr,void *buffer,unsigned int count) *ptr++ = tx_ioinb(addr); } } -void tx_insword(unsigned short *addr,void *buffer,unsigned int count) +void tx_insword(unsigned short *addr, void *buffer, unsigned int count) { unsigned short *ptr = (unsigned short *) buffer; @@ -434,7 +456,7 @@ void tx_insword(unsigned short *addr,void *buffer,unsigned int count) *ptr++ = tx_ioinw(addr); } } -void tx_inslong(unsigned int *addr,void *buffer,unsigned int count) +void tx_inslong(unsigned int *addr, void *buffer, unsigned int count) { unsigned long *ptr = (unsigned long *) buffer; @@ -442,28 +464,28 @@ void tx_inslong(unsigned int *addr,void *buffer,unsigned int count) *ptr++ = tx_ioinl(addr); } } -void tx_outsbyte(unsigned char *addr,void *buffer,unsigned int count) +void tx_outsbyte(unsigned char *addr, void *buffer, unsigned int count) { unsigned char *ptr = (unsigned char *) buffer; while (count--) { - tx_iooutb(*ptr++,addr); + tx_iooutb(*ptr++, addr); } } -void tx_outsword(unsigned short *addr,void *buffer,unsigned int count) +void tx_outsword(unsigned short *addr, void *buffer, unsigned int count) { unsigned short *ptr = (unsigned short *) buffer; while (count--) { - tx_iooutw(*ptr++,addr); + tx_iooutw(*ptr++, addr); } } -void tx_outslong(unsigned int *addr,void *buffer,unsigned int count) +void tx_outslong(unsigned int *addr, void *buffer, unsigned int count) { unsigned long *ptr = (unsigned long *) buffer; while (count--) { - tx_iooutl(*ptr++,addr); + tx_iooutl(*ptr++, addr); } } #endif diff --git a/arch/mips/pci/ops-ocelot.c b/arch/mips/pci/ops-ocelot.c index ec58506d0cb..db4033ab6e6 100644 --- a/arch/mips/pci/ops-ocelot.c +++ b/arch/mips/pci/ops-ocelot.c @@ -106,9 +106,9 @@ static unsigned int pci1GetMemory1Size(void); /* Functions to implement "pci ops" */ static int galileo_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int offset, int size, u32 * val); + int offset, int size, u32 * val); static int galileo_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int offset, int size, u32 val); + int offset, int size, u32 val); static void galileo_pcibios_set_master(struct pci_dev *dev); /* @@ -489,7 +489,7 @@ static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device) if (PCI_SLOT(device->devfn) == SELF) { /* This board */ GT_READ(GT_PCI0_CFGDATA_OFS, &data); return data; - } else { /* The PCI is working in LE Mode so swap the Data. */ + } else { /* The PCI is working in LE Mode so swap the Data. */ GT_READ(GT_PCI0_CFGDATA_OFS, &data); return cpu_to_le32(data); } @@ -585,7 +585,7 @@ static void pci1WriteConfigReg(unsigned int offset, */ DataForRegCf8 |= 0x80; GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - } else { /* configuration Transaction over the pci. */ + } else { /* configuration Transaction over the pci. */ /* The PCI is working in LE Mode so swap the Data. */ GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8); } @@ -616,7 +616,8 @@ static void pci1WriteConfigReg(unsigned int offset, * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned */ -static int galileo_pcibios_read (struct pci_bus *bus, unsigned int devfn, int offset, int size, u32 * val) +static int galileo_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int offset, int size, u32 * val) { int dev, busnum; @@ -624,10 +625,10 @@ static int galileo_pcibios_read (struct pci_bus *bus, unsigned int devfn, int of dev = PCI_SLOT(devfn); if (pci_range_ck(busnum, dev)) { - if(size == 1) - *val = (u8)0xff; + if (size == 1) + *val = (u8) 0xff; else if (size == 2) - *val = (u16)0xffff; + *val = (u16) 0xffff; else if (size == 4) *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; @@ -638,13 +639,14 @@ static int galileo_pcibios_read (struct pci_bus *bus, unsigned int devfn, int of return PCIBIOS_BAD_REGISTER_NUMBER; if (busnum == 0) { - if(size == 1) { - *val = (u8)(pci0ReadConfigReg(offset, bus->dev) >> + if (size == 1) { + *val = (u8) (pci0ReadConfigReg(offset, bus->dev) >> ((offset & ~0x3) * 8)); - }else if (size == 2) { - *val = (u16)(pci0ReadConfigReg(offset, bus->dev) >> - ((offset & ~0x3) * 8)); - }else if (size == 4) { + } else if (size == 2) { + *val = + (u16) (pci0ReadConfigReg(offset, bus->dev) >> + ((offset & ~0x3) * 8)); + } else if (size == 4) { *val = pci0ReadConfigReg(offset, bus->dev); } } @@ -654,27 +656,27 @@ static int galileo_pcibios_read (struct pci_bus *bus, unsigned int devfn, int of * value if we're not attached to anything. */ switch (size) { - case 1: - if ((offset == 0xe) && (*val == (u8)0xff)) { - u32 MasterAbort; - GT_READ(GT_INTRCAUSE_OFS, &MasterAbort); - if (MasterAbort & 0x40000) { - GT_WRITE(GT_INTRCAUSE_OFS, - (MasterAbort & 0xfffbffff)); - return PCIBIOS_DEVICE_NOT_FOUND; - } - } - break; - case 4: - if ((offset == 0) && (*val == 0xffffffff)) { + case 1: + if ((offset == 0xe) && (*val == (u8) 0xff)) { + u32 MasterAbort; + GT_READ(GT_INTRCAUSE_OFS, &MasterAbort); + if (MasterAbort & 0x40000) { + GT_WRITE(GT_INTRCAUSE_OFS, + (MasterAbort & 0xfffbffff)); return PCIBIOS_DEVICE_NOT_FOUND; } - break - } + } + break; + case 4: + if ((offset == 0) && (*val == 0xffffffff)) { + return PCIBIOS_DEVICE_NOT_FOUND; + } + break} return PCIBIOS_SUCCESSFUL; } -static int galileo_pcibios_write(struct pci_bus *bus, unsigned int devfn, int offset, int size, u32 val) +static int galileo_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int offset, int size, u32 val) { int dev, busnum; unsigned long tmp; @@ -687,30 +689,41 @@ static int galileo_pcibios_write(struct pci_bus *bus, unsigned int devfn, int of if (size == 4) { if (offset & 0x3) return PCIBIOS_BAD_REGISTER_NUMBER; - if(busnum == 0) + if (busnum == 0) pci0WriteConfigReg(offset, bus->dev, val); //if (busnum == 1) pci1WriteConfigReg (offset,bus->dev,val); return PCIBIOS_SUCCESSFUL; } if ((size == 2) && (offset & 0x1)) return PCIBIOS_BAD_REGISTER_NUMBER; - if (busnum == 0){ + if (busnum == 0) { tmp = pci0ReadConfigReg(offset, bus->dev); //if (busnum == 1) tmp = pci1ReadConfigReg (offset,bus->dev); if (size == 1) { if ((offset % 4) == 0) - tmp = (tmp & 0xffffff00) | (val & (u8)0xff); + tmp = + (tmp & 0xffffff00) | (val & (u8) 0xff); if ((offset % 4) == 1) - tmp = (tmp & 0xffff00ff) | ((val & (u8)0xff) << 8); + tmp = + (tmp & 0xffff00ff) | ((val & (u8) 0xff) + << 8); if ((offset % 4) == 2) - tmp = (tmp & 0xff00ffff) | ((val & (u8)0xff) << 16); + tmp = + (tmp & 0xff00ffff) | ((val & (u8) 0xff) + << 16); if ((offset % 4) == 3) - tmp = (tmp & 0x00ffffff) | ((val & (u8)0xff) << 24); + tmp = + (tmp & 0x00ffffff) | ((val & (u8) 0xff) + << 24); } else if (size == 2) { if ((offset % 4) == 0) - tmp = (tmp & 0xffff0000) | (val & (u16)0xffff); + tmp = + (tmp & 0xffff0000) | (val & (u16) + 0xffff); if ((offset % 4) == 2) - tmp = (tmp & 0x0000ffff) | ((val & (u16)0xffff) << 16); + tmp = + (tmp & 0x0000ffff) | + ((val & (u16) 0xffff) << 16); } if (busnum == 0) pci0WriteConfigReg(offset, bus->dev, tmp); @@ -753,7 +766,8 @@ int pcibios_enable_resources(struct pci_dev *dev) cmd |= PCI_COMMAND_MEMORY; } if (cmd != old_cmd) { - galileo_pcibios_write(dev->bus, dev->devfn, PCI_COMMAND, 2, cmd); + galileo_pcibios_write(dev->bus, dev->devfn, PCI_COMMAND, 2, + cmd); } /* @@ -761,17 +775,22 @@ int pcibios_enable_resources(struct pci_dev *dev) * line size = 32 bytes / sizeof dword (4) = 8. * Latency timer must be > 8. 32 is random but appears to work. */ - galileo_pcibios_read(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 1, &tmp1); + galileo_pcibios_read(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 1, + &tmp1); if (tmp1 != 8) { - printk(KERN_WARNING "PCI setting cache line size to 8 from " - "%d\n", tmp1); - galileo_pcibios_write(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 1, 8); + printk(KERN_WARNING + "PCI setting cache line size to 8 from " "%d\n", + tmp1); + galileo_pcibios_write(dev->bus, dev->devfn, + PCI_CACHE_LINE_SIZE, 1, 8); } - galileo_pcibios_read(dev->bus, dev->devfn, PCI_LATENCY_TIMER, 1, &tmp1); + galileo_pcibios_read(dev->bus, dev->devfn, PCI_LATENCY_TIMER, 1, + &tmp1); if (tmp1 < 32) { - printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n", - tmp1); - galileo_pcibios_write(dev->bus, dev->devfn, PCI_LATENCY_TIMER, 1, 32); + printk(KERN_WARNING + "PCI setting latency timer to 32 from %d\n", tmp1); + galileo_pcibios_write(dev->bus, dev->devfn, + PCI_LATENCY_TIMER, 1, 32); } return 0; @@ -796,7 +815,7 @@ void pcibios_align_resource(void *data, struct resource *res, if (size > 0x100) { printk(KERN_ERR "PCI: I/O Region %s/%d too large" " (%ld bytes)\n", dev->slot_name, - dev->resource - res, size); + dev->resource - res, size); } start = (start + 1024 - 1) & ~(1024 - 1); @@ -805,8 +824,8 @@ void pcibios_align_resource(void *data, struct resource *res, } struct pci_ops galileo_pci_ops = { - .read = galileo_pcibios_read, - .write = galileo_pcibios_write, + .read = galileo_pcibios_read, + .write = galileo_pcibios_write, }; struct pci_fixup pcibios_fixups[] = { @@ -899,7 +918,7 @@ static u32 __init scan_pci_bus(struct pci_device *pci_devices) arrayCounter++; } /* found a device */ - } /* slot counter */ + } /* slot counter */ if (arrayCounter < MAX_PCI_DEVS) pci_devices[arrayCounter].slot = -1; @@ -1009,9 +1028,9 @@ static int __init pcibios_init(void) * Reset PCI I/O and PCI MEM values to ones supported by EVM. */ ioport_resource.start = GT_PCI_IO_BASE; - ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; - iomem_resource.start = GT_PCI_MEM_BASE; - iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1; + ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; + iomem_resource.start = GT_PCI_MEM_BASE; + iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1; pci_scan_bus(0, &galileo_pci_ops, NULL); @@ -1025,10 +1044,10 @@ subsys_initcall(pcibios_init); */ char *pcibios_setup(char *str) { - printk(KERN_INFO "rr: pcibios_setup\n"); - /* Nothing to do for now. */ + printk(KERN_INFO "rr: pcibios_setup\n"); + /* Nothing to do for now. */ - return str; + return str; } unsigned __init int pcibios_assign_all_busses(void) diff --git a/arch/mips/pci/ops-vrc4173.c b/arch/mips/pci/ops-vrc4173.c index b6a50b978d8..ce4e7029a5a 100644 --- a/arch/mips/pci/ops-vrc4173.c +++ b/arch/mips/pci/ops-vrc4173.c @@ -40,18 +40,18 @@ #define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18) #define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14) - + static inline void config_writeb(u8 reg, u8 val) { u32 data; int shift; writel((1UL << 0x1e) | (reg & 0xfc), PCI_CONFIG_ADDR); - data = readl(PCI_CONFIG_DATA); + data = readl(PCI_CONFIG_DATA); shift = (reg & 3) << 3; data &= ~(0xff << shift); - data |= (((u32)val) << shift); + data |= (((u32) val) << shift); writel(data, PCI_CONFIG_DATA); } @@ -60,15 +60,15 @@ static inline u16 config_readw(u8 reg) { u32 data; - writel(((1UL << 30) | (reg & 0xfc)) , PCI_CONFIG_ADDR); + writel(((1UL << 30) | (reg & 0xfc)), PCI_CONFIG_ADDR); data = readl(PCI_CONFIG_DATA); - return (u16)(data >> ((reg & 2) << 3)); + return (u16) (data >> ((reg & 2) << 3)); } static inline u32 config_readl(u8 reg) { - writel(((1UL << 30) | (reg & 0xfc)) , PCI_CONFIG_ADDR); + writel(((1UL << 30) | (reg & 0xfc)), PCI_CONFIG_ADDR); return readl(PCI_CONFIG_DATA); } @@ -92,10 +92,9 @@ void __init vrc4173_preinit(void) */ cmdsts = config_readl(PCI_COMMAND); config_writel(PCI_COMMAND, - cmdsts | - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); + cmdsts | + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); config_writeb(PCI_LATENCY_TIMER, 0x80); diff --git a/arch/mips/pci/pci-auto.c b/arch/mips/pci/pci-auto.c index c006bd2f016..1d25569b1fc 100644 --- a/arch/mips/pci/pci-auto.c +++ b/arch/mips/pci/pci-auto.c @@ -53,7 +53,7 @@ * and all of the pci_dev and pci_bus structures have been created. */ static struct pci_dev *fake_pci_dev(struct pci_channel *hose, - int top_bus, int busnr, int devfn) + int top_bus, int busnr, int devfn) { static struct pci_dev dev; static struct pci_bus bus; @@ -64,7 +64,7 @@ static struct pci_dev *fake_pci_dev(struct pci_channel *hose, bus.number = busnr; bus.ops = hose->pci_ops; - if(busnr != top_bus) + if (busnr != top_bus) /* Fake a parent bus structure. */ bus.parent = &bus; else @@ -83,11 +83,11 @@ int early_##rw##_config_##size(struct pci_channel *hose, \ } EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, word, u16 *) -EARLY_PCI_OP(read, dword, u32 *) -EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, word, u16) -EARLY_PCI_OP(write, dword, u32) + EARLY_PCI_OP(read, word, u16 *) + EARLY_PCI_OP(read, dword, u32 *) + EARLY_PCI_OP(write, byte, u8) + EARLY_PCI_OP(write, word, u16) + EARLY_PCI_OP(write, dword, u32) static struct resource *io_resource_inuse; static struct resource *mem_resource_inuse; @@ -101,28 +101,22 @@ static u32 pciauto_upper_memspc; void __init pciauto_setup_bars(struct pci_channel *hose, int top_bus, - int current_bus, - int pci_devfn, - int bar_limit) + int current_bus, int pci_devfn, int bar_limit) { u32 bar_response, bar_size, bar_value; u32 bar, addr_mask, bar_nr = 0; - u32 * upper_limit; - u32 * lower_limit; + u32 *upper_limit; + u32 *lower_limit; int found_mem64 = 0; - for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) { + for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar += 4) { /* Tickle the BAR and get the response */ early_write_config_dword(hose, top_bus, current_bus, - pci_devfn, - bar, - 0xffffffff); + pci_devfn, bar, 0xffffffff); early_read_config_dword(hose, top_bus, current_bus, - pci_devfn, - bar, - &bar_response); + pci_devfn, bar, &bar_response); /* If BAR is not implemented go to the next BAR */ if (!bar_response) @@ -136,7 +130,7 @@ pciauto_setup_bars(struct pci_channel *hose, if (!(bar_response & 0xffff0000)) bar_response |= 0xffff0000; -retry: + retry: /* Check the BAR type and set our address mask */ if (bar_response & PCI_BASE_ADDRESS_SPACE) { addr_mask = PCI_BASE_ADDRESS_IO_MASK; @@ -144,8 +138,8 @@ retry: lower_limit = &pciauto_lower_iospc; DBG(" I/O"); } else { - if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == - PCI_BASE_ADDRESS_MEM_TYPE_64) + if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) + == PCI_BASE_ADDRESS_MEM_TYPE_64) found_mem64 = 1; addr_mask = PCI_BASE_ADDRESS_MEM_MASK; @@ -159,28 +153,29 @@ retry: bar_size = ~(bar_response & addr_mask) + 1; /* Allocate a base address */ - bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size; + bar_value = + ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size; if ((bar_value + bar_size) > *upper_limit) { if (bar_response & PCI_BASE_ADDRESS_SPACE) { if (io_resource_inuse->child) { io_resource_inuse = - io_resource_inuse->child; + io_resource_inuse->child; pciauto_lower_iospc = - io_resource_inuse->start; + io_resource_inuse->start; pciauto_upper_iospc = - io_resource_inuse->end + 1; + io_resource_inuse->end + 1; goto retry; } } else { if (mem_resource_inuse->child) { mem_resource_inuse = - mem_resource_inuse->child; + mem_resource_inuse->child; pciauto_lower_memspc = - mem_resource_inuse->start; + mem_resource_inuse->start; pciauto_upper_memspc = - mem_resource_inuse->end + 1; + mem_resource_inuse->end + 1; goto retry; } } @@ -189,8 +184,8 @@ retry: } /* Write it out and update our limit */ - early_write_config_dword(hose, top_bus, current_bus, pci_devfn, - bar, bar_value); + early_write_config_dword(hose, top_bus, current_bus, + pci_devfn, bar, bar_value); *lower_limit = bar_value + bar_size; @@ -204,8 +199,7 @@ retry: early_write_config_dword(hose, top_bus, current_bus, pci_devfn, - bar, - 0x00000000); + bar, 0x00000000); } DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size); @@ -218,13 +212,11 @@ retry: void __init pciauto_prescan_setup_bridge(struct pci_channel *hose, int top_bus, - int current_bus, - int pci_devfn, - int sub_bus) + int current_bus, int pci_devfn, int sub_bus) { /* Configure bus number registers */ early_write_config_byte(hose, top_bus, current_bus, pci_devfn, - PCI_PRIMARY_BUS, current_bus); + PCI_PRIMARY_BUS, current_bus); early_write_config_byte(hose, top_bus, current_bus, pci_devfn, PCI_SECONDARY_BUS, sub_bus + 1); early_write_config_byte(hose, top_bus, current_bus, pci_devfn, @@ -232,17 +224,20 @@ pciauto_prescan_setup_bridge(struct pci_channel *hose, /* Align memory and I/O to 1MB and 4KB boundaries. */ pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1)) - & ~(0x100000 - 1); + & ~(0x100000 - 1); pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1)) - & ~(0x1000 - 1); + & ~(0x1000 - 1); /* Set base (lower limit) of address range behind bridge. */ early_write_config_word(hose, top_bus, current_bus, pci_devfn, - PCI_MEMORY_BASE, pciauto_lower_memspc >> 16); + PCI_MEMORY_BASE, + pciauto_lower_memspc >> 16); early_write_config_byte(hose, top_bus, current_bus, pci_devfn, - PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8); + PCI_IO_BASE, + (pciauto_lower_iospc & 0x0000f000) >> 8); early_write_config_word(hose, top_bus, current_bus, pci_devfn, - PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16); + PCI_IO_BASE_UPPER16, + pciauto_lower_iospc >> 16); /* We don't support prefetchable memory for now, so disable */ early_write_config_word(hose, top_bus, current_bus, pci_devfn, @@ -254,9 +249,7 @@ pciauto_prescan_setup_bridge(struct pci_channel *hose, void __init pciauto_postscan_setup_bridge(struct pci_channel *hose, int top_bus, - int current_bus, - int pci_devfn, - int sub_bus) + int current_bus, int pci_devfn, int sub_bus) { u32 temp; @@ -274,59 +267,62 @@ pciauto_postscan_setup_bridge(struct pci_channel *hose, /* Set upper limit of address range behind bridge. */ early_write_config_word(hose, top_bus, current_bus, pci_devfn, - PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16); + PCI_MEMORY_LIMIT, + pciauto_lower_memspc >> 16); early_write_config_byte(hose, top_bus, current_bus, pci_devfn, - PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8); + PCI_IO_LIMIT, + (pciauto_lower_iospc & 0x0000f000) >> 8); early_write_config_word(hose, top_bus, current_bus, pci_devfn, - PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16); + PCI_IO_LIMIT_UPPER16, + pciauto_lower_iospc >> 16); /* Align memory and I/O to 1MB and 4KB boundaries. */ pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1)) - & ~(0x100000 - 1); + & ~(0x100000 - 1); pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1)) - & ~(0x1000 - 1); + & ~(0x1000 - 1); /* Enable memory and I/O accesses, enable bus master */ early_read_config_dword(hose, top_bus, current_bus, pci_devfn, - PCI_COMMAND, &temp); + PCI_COMMAND, &temp); early_write_config_dword(hose, top_bus, current_bus, pci_devfn, - PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY - | PCI_COMMAND_MASTER); + PCI_COMMAND, + temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY + | PCI_COMMAND_MASTER); } void __init pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose, - int top_bus, - int current_bus, - int pci_devfn, - int sub_bus) + int top_bus, + int current_bus, + int pci_devfn, int sub_bus) { - /* Configure bus number registers */ - early_write_config_byte(hose, top_bus, current_bus, pci_devfn, - PCI_PRIMARY_BUS, current_bus); - early_write_config_byte(hose, top_bus, current_bus, pci_devfn, - PCI_SECONDARY_BUS, sub_bus + 1); - early_write_config_byte(hose, top_bus, current_bus, pci_devfn, - PCI_SUBORDINATE_BUS, 0xff); - - /* Align memory and I/O to 4KB and 4 byte boundaries. */ - pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1)) - & ~(0x1000 - 1); - pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1)) - & ~(0x4 - 1); - - early_write_config_dword(hose, top_bus, current_bus, pci_devfn, - PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc); - early_write_config_dword(hose, top_bus, current_bus, pci_devfn, - PCI_CB_IO_BASE_0, pciauto_lower_iospc); + /* Configure bus number registers */ + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_PRIMARY_BUS, current_bus); + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_SECONDARY_BUS, sub_bus + 1); + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_SUBORDINATE_BUS, 0xff); + + /* Align memory and I/O to 4KB and 4 byte boundaries. */ + pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1)) + & ~(0x1000 - 1); + pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1)) + & ~(0x4 - 1); + + early_write_config_dword(hose, top_bus, current_bus, pci_devfn, + PCI_CB_MEMORY_BASE_0, + pciauto_lower_memspc); + early_write_config_dword(hose, top_bus, current_bus, pci_devfn, + PCI_CB_IO_BASE_0, pciauto_lower_iospc); } void __init pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose, - int top_bus, - int current_bus, - int pci_devfn, - int sub_bus) + int top_bus, + int current_bus, + int pci_devfn, int sub_bus) { u32 temp; @@ -337,8 +333,8 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose, * adapter contains a P2P or CB2CB bridge. */ - early_write_config_byte(hose, top_bus, current_bus, pci_devfn, - PCI_SUBORDINATE_BUS, sub_bus); + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_SUBORDINATE_BUS, sub_bus); /* * Reserve an additional 4MB for mem space and 16KB for @@ -359,21 +355,24 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose, /* Align memory and I/O to 4KB and 4 byte boundaries. */ pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1)) - & ~(0x1000 - 1); + & ~(0x1000 - 1); pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1)) - & ~(0x4 - 1); + & ~(0x4 - 1); /* Set up memory and I/O filter limits, assume 32-bit I/O space */ early_write_config_dword(hose, top_bus, current_bus, pci_devfn, - PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1); + PCI_CB_MEMORY_LIMIT_0, + pciauto_lower_memspc - 1); early_write_config_dword(hose, top_bus, current_bus, pci_devfn, - PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1); - + PCI_CB_IO_LIMIT_0, + pciauto_lower_iospc - 1); + /* Enable memory and I/O accesses, enable bus master */ early_read_config_dword(hose, top_bus, current_bus, pci_devfn, - PCI_COMMAND, &temp); + PCI_COMMAND, &temp); early_write_config_dword(hose, top_bus, current_bus, pci_devfn, - PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY - | PCI_COMMAND_MASTER); + PCI_COMMAND, + temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY + | PCI_COMMAND_MASTER); } #define PCIAUTO_IDE_MODE_MASK 0x05 @@ -382,7 +381,7 @@ int __init pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus) { int sub_bus; - u32 pci_devfn, pci_class, cmdstat, found_multi=0; + u32 pci_devfn, pci_class, cmdstat, found_multi = 0; unsigned short vid, did; unsigned char header_type; int devfn_start = 0; @@ -395,101 +394,112 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus) if (hose->last_devfn) devfn_stop = hose->last_devfn; - for (pci_devfn=devfn_start; pci_devfn> 16, vid, did); + current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn), + pci_class >> 16, vid, did); if (pci_class & 0xff) DBG(" (rev %.2x)", pci_class & 0xff); DBG("\n"); if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) { - DBG(" Bridge: primary=%.2x, secondary=%.2x\n", - current_bus, sub_bus + 1); - pciauto_setup_bars(hose, top_bus, current_bus, - pci_devfn, PCI_BASE_ADDRESS_1); - pciauto_prescan_setup_bridge(hose, top_bus, current_bus, + DBG(" Bridge: primary=%.2x, secondary=%.2x\n", current_bus, sub_bus + 1); + pciauto_setup_bars(hose, top_bus, current_bus, + pci_devfn, PCI_BASE_ADDRESS_1); + pciauto_prescan_setup_bridge(hose, top_bus, + current_bus, pci_devfn, sub_bus); - DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n", - sub_bus + 1, - pciauto_lower_iospc, pciauto_lower_memspc); - sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1); + DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n", sub_bus + 1, pciauto_lower_iospc, pciauto_lower_memspc); + sub_bus = + pciauto_bus_scan(hose, top_bus, sub_bus + 1); DBG("Back to bus %.2x\n", current_bus); - pciauto_postscan_setup_bridge(hose, top_bus, current_bus, + pciauto_postscan_setup_bridge(hose, top_bus, + current_bus, pci_devfn, sub_bus); continue; - } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) { - DBG(" CARDBUS Bridge: primary=%.2x, secondary=%.2x\n", - current_bus, sub_bus + 1); - DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn)); - /* Place CardBus Socket/ExCA registers */ - pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0); - - pciauto_prescan_setup_cardbus_bridge(hose, top_bus, - current_bus, pci_devfn, sub_bus); - - DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n", - sub_bus + 1, - pciauto_lower_iospc, pciauto_lower_memspc); - sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1); - DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus); - pciauto_postscan_setup_cardbus_bridge(hose, top_bus, - current_bus, pci_devfn, sub_bus); - continue; + } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) { + DBG(" CARDBUS Bridge: primary=%.2x, secondary=%.2x\n", current_bus, sub_bus + 1); + DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn)); + /* Place CardBus Socket/ExCA registers */ + pciauto_setup_bars(hose, top_bus, current_bus, + pci_devfn, PCI_BASE_ADDRESS_0); + + pciauto_prescan_setup_cardbus_bridge(hose, top_bus, + current_bus, + pci_devfn, + sub_bus); + + DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n", sub_bus + 1, pciauto_lower_iospc, pciauto_lower_memspc); + sub_bus = + pciauto_bus_scan(hose, top_bus, sub_bus + 1); + DBG("Back to bus %.2x, sub_bus is %x\n", + current_bus, sub_bus); + pciauto_postscan_setup_cardbus_bridge(hose, + top_bus, + current_bus, + pci_devfn, + sub_bus); + continue; } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) { unsigned char prg_iface; early_read_config_byte(hose, top_bus, current_bus, - pci_devfn, PCI_CLASS_PROG, &prg_iface); + pci_devfn, PCI_CLASS_PROG, + &prg_iface); if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { DBG("Skipping legacy mode IDE controller\n"); continue; } } - /* + /* * Found a peripheral, enable some standard * settings */ - early_read_config_dword(hose, top_bus, current_bus, pci_devfn, - PCI_COMMAND, &cmdstat); - early_write_config_dword(hose, top_bus, current_bus, pci_devfn, - PCI_COMMAND, cmdstat | PCI_COMMAND_IO | + early_read_config_dword(hose, top_bus, current_bus, + pci_devfn, PCI_COMMAND, &cmdstat); + early_write_config_dword(hose, top_bus, current_bus, + pci_devfn, PCI_COMMAND, + cmdstat | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - early_write_config_byte(hose, top_bus, current_bus, pci_devfn, - PCI_LATENCY_TIMER, 0x80); + early_write_config_byte(hose, top_bus, current_bus, + pci_devfn, PCI_LATENCY_TIMER, + 0x80); /* Allocate PCI I/O and/or memory space */ - pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5); + pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, + PCI_BASE_ADDRESS_5); } return sub_bus; } -int __init -pciauto_assign_resources(int busno, struct pci_channel *hose) +int __init pciauto_assign_resources(int busno, struct pci_channel *hose) { /* setup resource limits */ io_resource_inuse = hose->io_resource; @@ -501,8 +511,8 @@ pciauto_assign_resources(int busno, struct pci_channel *hose) pciauto_upper_memspc = mem_resource_inuse->end + 1; DBG("Autoconfig PCI channel 0x%p\n", hose); DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n", - busno, pciauto_lower_iospc, pciauto_upper_iospc, - pciauto_lower_memspc, pciauto_upper_memspc); + busno, pciauto_lower_iospc, pciauto_upper_iospc, + pciauto_lower_memspc, pciauto_upper_memspc); return pciauto_bus_scan(hose, busno, busno); } diff --git a/arch/mips/pci/pci-cobalt.c b/arch/mips/pci/pci-cobalt.c index dd3e4114a40..96bc1329e08 100644 --- a/arch/mips/pci/pci-cobalt.c +++ b/arch/mips/pci/pci-cobalt.c @@ -27,41 +27,44 @@ static void qube_expansion_slot_bist(struct pci_dev *dev) int timeout = 100000; pci_read_config_byte(dev, PCI_BIST, &ctrl); - if(!(ctrl & PCI_BIST_CAPABLE)) + if (!(ctrl & PCI_BIST_CAPABLE)) return; - pci_write_config_byte(dev, PCI_BIST, ctrl|PCI_BIST_START); + pci_write_config_byte(dev, PCI_BIST, ctrl | PCI_BIST_START); do { pci_read_config_byte(dev, PCI_BIST, &ctrl); - if(!(ctrl & PCI_BIST_START)) + if (!(ctrl & PCI_BIST_START)) break; - } while(--timeout > 0); - if((timeout <= 0) || (ctrl & PCI_BIST_CODE_MASK)) - printk("PCI: Expansion slot card failed BIST with code %x\n", - (ctrl & PCI_BIST_CODE_MASK)); + } while (--timeout > 0); + if ((timeout <= 0) || (ctrl & PCI_BIST_CODE_MASK)) + printk + ("PCI: Expansion slot card failed BIST with code %x\n", + (ctrl & PCI_BIST_CODE_MASK)); } static void qube_expansion_slot_fixup(struct pci_dev *dev) { unsigned short pci_cmd; - unsigned long ioaddr_base = 0x10108000; /* It's magic, ask Doug. */ + unsigned long ioaddr_base = 0x10108000; /* It's magic, ask Doug. */ unsigned long memaddr_base = 0x12001000; int i; /* Enable bits in COMMAND so driver can talk to it. */ pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); - pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_cmd |= + (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); pci_write_config_word(dev, PCI_COMMAND, pci_cmd); /* Give it a working IRQ. */ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_QUBE_SLOT_IRQ); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + COBALT_QUBE_SLOT_IRQ); dev->irq = COBALT_QUBE_SLOT_IRQ; ioaddr_base += 0x2000 * PCI_FUNC(dev->devfn); memaddr_base += 0x2000 * PCI_FUNC(dev->devfn); /* Fixup base addresses, we only support I/O at the moment. */ - for(i = 0; i <= 5; i++) { + for (i = 0; i <= 5; i++) { unsigned int regaddr = (PCI_BASE_ADDRESS_0 + (i * 4)); unsigned int rval, mask, size, alignme, aspace; unsigned long *basep = &ioaddr_base; @@ -69,7 +72,7 @@ static void qube_expansion_slot_fixup(struct pci_dev *dev) /* Check type first, punt if non-IO. */ pci_read_config_dword(dev, regaddr, &rval); aspace = (rval & PCI_BASE_ADDRESS_SPACE); - if(aspace != PCI_BASE_ADDRESS_SPACE_IO) + if (aspace != PCI_BASE_ADDRESS_SPACE_IO) basep = &memaddr_base; /* Figure out how much it wants, if anything. */ @@ -77,21 +80,21 @@ static void qube_expansion_slot_fixup(struct pci_dev *dev) pci_read_config_dword(dev, regaddr, &rval); /* Unused? */ - if(rval == 0) + if (rval == 0) continue; rval &= PCI_BASE_ADDRESS_IO_MASK; mask = (~rval << 1) | 0x1; size = (mask & rval) & 0xffffffff; alignme = size; - if(alignme < 0x400) + if (alignme < 0x400) alignme = 0x400; rval = ((*basep + (alignme - 1)) & ~(alignme - 1)); *basep = (rval + size); pci_write_config_dword(dev, regaddr, rval | aspace); dev->resource[i].start = rval; dev->resource[i].end = *basep - 1; - if(aspace == PCI_BASE_ADDRESS_SPACE_IO) { + if (aspace == PCI_BASE_ADDRESS_SPACE_IO) { dev->resource[i].start -= 0x10000000; dev->resource[i].end -= 0x10000000; } @@ -114,7 +117,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) /* Set latency timer to reasonable value. */ pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); - if(lt < 64) + if (lt < 64) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); } @@ -135,9 +138,10 @@ static void qube_raq_tulip_fixup(struct pci_dev *dev) dev->resource[1].start = 0x12000000; dev->resource[1].end = dev->resource[1].start + 0x3ff; - pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, dev->resource[1].start); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, + dev->resource[1].start); - /* Fixup the second tulip located at device PCICONF_ETH1 */ + /* Fixup the second tulip located at device PCICONF_ETH1 */ } else if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH1) { /* Enable the second Tulip device. */ @@ -147,7 +151,7 @@ static void qube_raq_tulip_fixup(struct pci_dev *dev) /* Give it it's IRQ. */ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, - COBALT_ETH1_IRQ); + COBALT_ETH1_IRQ); dev->irq = COBALT_ETH1_IRQ; /* And finally, a usable I/O space allocation, right after what @@ -158,7 +162,8 @@ static void qube_raq_tulip_fixup(struct pci_dev *dev) dev->resource[1].start = 0x12000400; dev->resource[1].end = dev->resource[1].start + 0x3ff; - pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, dev->resource[1].start); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, + dev->resource[1].start); } } @@ -166,11 +171,11 @@ static void qube_raq_scsi_fixup(struct pci_dev *dev) { unsigned short pci_cmd; - /* - * Tell the SCSI device that we expect an interrupt at - * IRQ 7 and not the default 0. - */ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_SCSI_IRQ); + /* + * Tell the SCSI device that we expect an interrupt at + * IRQ 7 and not the default 0. + */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_SCSI_IRQ); dev->irq = COBALT_SCSI_IRQ; if (cobalt_board_id == COBALT_BRD_ID_RAQ2) { @@ -178,12 +183,14 @@ static void qube_raq_scsi_fixup(struct pci_dev *dev) /* Enable the device. */ pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); - pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY - | PCI_COMMAND_INVALIDATE); + pci_cmd |= + (PCI_COMMAND_IO | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE); pci_write_config_word(dev, PCI_COMMAND, pci_cmd); /* Give it it's RAQ IRQ. */ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_RAQ_SCSI_IRQ); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + COBALT_RAQ_SCSI_IRQ); dev->irq = COBALT_RAQ_SCSI_IRQ; /* And finally, a usable I/O space allocation, right after what @@ -191,10 +198,13 @@ static void qube_raq_scsi_fixup(struct pci_dev *dev) */ dev->resource[0].start = 0x102000; dev->resource[0].end = dev->resource[0].start + 0xff; - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x10102000); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, + 0x10102000); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x00002000); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0x00100000); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, + 0x00002000); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, + 0x00100000); } } @@ -216,7 +226,7 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) * something sensible when using the new Galileo. */ pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id); - galileo_id &= 0xff; /* mask off class info */ + galileo_id &= 0xff; /* mask off class info */ if (galileo_id >= 0x10) { /* New Galileo, assumes PCI stop line to VIA is connected. */ GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); @@ -229,8 +239,7 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) } } -static void -qube_pcibios_fixup(struct pci_dev *dev) +static void qube_pcibios_fixup(struct pci_dev *dev) { if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_PCISLOT) { unsigned int tmp; @@ -239,29 +248,33 @@ qube_pcibios_fixup(struct pci_dev *dev) * discover its resources and fixup whatever we need to */ pci_read_config_dword(dev, PCI_VENDOR_ID, &tmp); - if(tmp != 0xffffffff && tmp != 0x00000000) + if (tmp != 0xffffffff && tmp != 0x00000000) qube_expansion_slot_fixup(dev); } } struct pci_fixup pcibios_fixups[] = { - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, qube_raq_via_bmIDE_fixup }, - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, qube_raq_tulip_fixup }, - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, qube_raq_galileo_fixup }, - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, qube_raq_scsi_fixup }, - { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, qube_pcibios_fixup } + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, + qube_raq_via_bmIDE_fixup}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, + qube_raq_tulip_fixup}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, + qube_raq_galileo_fixup}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, + qube_raq_scsi_fixup}, + {PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, qube_pcibios_fixup} }; static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn) { - if ((bus->number == 0) - && ((PCI_SLOT(devfn) == 0) - || ((PCI_SLOT(devfn) > 6) - && (PCI_SLOT (devfn) <= 12)))) - return 0; /* OK device number */ + if ((bus->number == 0) + && ((PCI_SLOT(devfn) == 0) + || ((PCI_SLOT(devfn) > 6) + && (PCI_SLOT(devfn) <= 12)))) + return 0; /* OK device number */ - return -1; /* NOT ok device number */ + return -1; /* NOT ok device number */ } #define PCI_CFG_SET(devfn,where) \ @@ -271,7 +284,7 @@ static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn) static int qube_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) + int where, int size, u32 * val) { switch (size) { case 4: @@ -294,7 +307,7 @@ static int qube_pci_read_config(struct pci_bus *bus, unsigned int devfn, } PCI_CFG_SET(devfn, (where & ~0x3)); *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) - >> ((where & 3) * 8); + >> ((where & 3) * 8); return PCIBIOS_SUCCESSFUL; case 1: @@ -304,19 +317,19 @@ static int qube_pci_read_config(struct pci_bus *bus, unsigned int devfn, } PCI_CFG_SET(devfn, (where & ~0x3)); *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) - >> ((where & 3) * 8); + >> ((where & 3) * 8); return PCIBIOS_SUCCESSFUL; } } static int qube_pci_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) + int where, int size, u32 val) { u32 tmp; switch (size) { case 4: - if(where & 0x3) + if (where & 0x3) return PCIBIOS_BAD_REGISTER_NUMBER; if (pci_range_ck(bus, devfn)) return PCIBIOS_DEVICE_NOT_FOUND; @@ -333,7 +346,7 @@ static int qube_pci_write_config(struct pci_bus *bus, unsigned int devfn, PCI_CFG_SET(devfn, (where & ~0x3)); tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); tmp &= ~(0xffff << ((where & 0x3) * 8)); - tmp |= (val << ((where & 0x3) * 8)); + tmp |= (val << ((where & 0x3) * 8)); GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); return PCIBIOS_SUCCESSFUL; @@ -345,7 +358,7 @@ static int qube_pci_write_config(struct pci_bus *bus, unsigned int devfn, PCI_CFG_SET(devfn, (where & ~0x3)); tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); tmp &= ~(0xff << ((where & 0x3) * 8)); - tmp |= (val << ((where & 0x3) * 8)); + tmp |= (val << ((where & 0x3) * 8)); GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); return PCIBIOS_SUCCESSFUL; @@ -353,8 +366,8 @@ static int qube_pci_write_config(struct pci_bus *bus, unsigned int devfn, } struct pci_ops qube_pci_ops = { - .read = qube_pci_read_config, - .write = qube_pci_write_config, + .read = qube_pci_read_config, + .write = qube_pci_write_config, }; static int __init pcibios_init(void) @@ -366,7 +379,7 @@ static int __init pcibios_init(void) /* Read the cobalt id register out of the PCI config space */ PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS) - >> ((VIA_COBALT_BRD_ID_REG & 3) * 8); + >> ((VIA_COBALT_BRD_ID_REG & 3) * 8); cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); printk("Cobalt Board ID: %d\n", cobalt_board_id); @@ -395,14 +408,15 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) pci_read_config_word(dev, PCI_COMMAND, &cmd); pci_read_config_word(dev, PCI_STATUS, &status); - printk("PCI: Enabling device %s (%04x %04x)\n", dev->slot_name, cmd, status); + printk("PCI: Enabling device %s (%04x %04x)\n", dev->slot_name, + cmd, status); /* We'll sort this out when we know it isn't enabled ;) */ return 0; } void pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) + unsigned long size, unsigned long align) { panic("Uhhoh called pcibios_align_resource\n"); diff --git a/arch/mips/pci/pci-ddb5074.c b/arch/mips/pci/pci-ddb5074.c index f6c152f57bc..91e4792a6dc 100644 --- a/arch/mips/pci/pci-ddb5074.c +++ b/arch/mips/pci/pci-ddb5074.c @@ -9,22 +9,24 @@ #include static struct resource extpci_io_resource = { - "pci IO space", - 0x1000, /* leave some room for ISA bus */ - DDB_PCI_IO_SIZE -1, - IORESOURCE_IO}; + "pci IO space", + 0x1000, /* leave some room for ISA bus */ + DDB_PCI_IO_SIZE - 1, + IORESOURCE_IO +}; static struct resource extpci_mem_resource = { - "pci memory space", - DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ - DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE -1, - IORESOURCE_MEM}; + "pci memory space", + DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ + DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1, + IORESOURCE_MEM +}; extern struct pci_ops ddb5476_ext_pci_ops; struct pci_channel mips_pci_channels[] = { - { &ddb5476_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource }, - { NULL, NULL, NULL} + {&ddb5476_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource}, + {NULL, NULL, NULL} }; #define PCI_EXT_INTA 8 @@ -52,7 +54,8 @@ static unsigned char irq_map[MAX_SLOT_NUM] = { /* SLOT: 13 */ nile4_to_irq(PCI_EXT_INTE), }; -void __init pcibios_fixup_irqs(void) { +void __init pcibios_fixup_irqs(void) +{ struct pci_dev *dev; int slot_num; @@ -60,12 +63,12 @@ void __init pcibios_fixup_irqs(void) { pci_for_each_dev(dev) { slot_num = PCI_SLOT(dev->devfn); db_assert(slot_num < MAX_SLOT_NUM); -printk("irq_map[%d]: %02x\n",slot_num, irq_map[slot_num]); + printk("irq_map[%d]: %02x\n", slot_num, irq_map[slot_num]); db_assert(irq_map[slot_num] != 0xff); pci_write_config_byte(dev, - PCI_INTERRUPT_LINE, - irq_map[slot_num]); + PCI_INTERRUPT_LINE, + irq_map[slot_num]); dev->irq = irq_map[slot_num]; } @@ -73,27 +76,27 @@ printk("irq_map[%d]: %02x\n",slot_num, irq_map[slot_num]); void __init ddb_pci_reset_bus(void) { - u32 temp; - - /* - * I am not sure about the "official" procedure, the following - * steps work as far as I know: - * We first set PCI cold reset bit (bit 31) in PCICTRL-H. - * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. - * The same is true for both PCI channels. - */ - temp = ddb_in32(DDB_PCICTRL+4); - temp |= 0x80000000; - ddb_out32(DDB_PCICTRL+4, temp); - temp &= ~0xc0000000; - ddb_out32(DDB_PCICTRL+4, temp); + u32 temp; + + /* + * I am not sure about the "official" procedure, the following + * steps work as far as I know: + * We first set PCI cold reset bit (bit 31) in PCICTRL-H. + * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. + * The same is true for both PCI channels. + */ + temp = ddb_in32(DDB_PCICTRL + 4); + temp |= 0x80000000; + ddb_out32(DDB_PCICTRL + 4, temp); + temp &= ~0xc0000000; + ddb_out32(DDB_PCICTRL + 4, temp); } unsigned __init int pcibios_assign_all_busses(void) { - /* we hope pci_auto has assigned the bus numbers to all buses */ - return 1; + /* we hope pci_auto has assigned the bus numbers to all buses */ + return 1; } void __init pcibios_fixup_resources(struct pci_dev *dev) @@ -106,25 +109,24 @@ void __init pcibios_fixup(void) pci_for_each_dev(dev) { if (dev->vendor == PCI_VENDOR_ID_AL && - dev->device == PCI_DEVICE_ID_AL_M7101) { - /* - * It's nice to have the LEDs on the GPIO pins - * available for debugging - */ - extern struct pci_dev *pci_pmu; - u8 t8; - - pci_pmu = dev; /* for LEDs D2 and D3 */ - /* Program the lines for LEDs D2 and D3 to output */ - pci_read_config_byte(dev, 0x7d, &t8); - t8 |= 0xc0; - pci_write_config_byte(dev, 0x7d, t8); - /* Turn LEDs D2 and D3 off */ - pci_read_config_byte(dev, 0x7e, &t8); - t8 |= 0xc0; - pci_write_config_byte(dev, 0x7e, t8); + dev->device == PCI_DEVICE_ID_AL_M7101) { + /* + * It's nice to have the LEDs on the GPIO pins + * available for debugging + */ + extern struct pci_dev *pci_pmu; + u8 t8; + + pci_pmu = dev; /* for LEDs D2 and D3 */ + /* Program the lines for LEDs D2 and D3 to output */ + pci_read_config_byte(dev, 0x7d, &t8); + t8 |= 0xc0; + pci_write_config_byte(dev, 0x7d, t8); + /* Turn LEDs D2 and D3 off */ + pci_read_config_byte(dev, 0x7e, &t8); + t8 |= 0xc0; + pci_write_config_byte(dev, 0x7e, t8); } } } - diff --git a/arch/mips/pci/pci-ddb5476.c b/arch/mips/pci/pci-ddb5476.c index cca87b5cc5b..f656ad2b929 100644 --- a/arch/mips/pci/pci-ddb5476.c +++ b/arch/mips/pci/pci-ddb5476.c @@ -11,21 +11,23 @@ static struct resource extpci_io_resource = { "pci IO space", - 0x1000, /* leave some room for ISA bus */ - DDB_PCI_IO_SIZE -1, - IORESOURCE_IO}; + 0x1000, /* leave some room for ISA bus */ + DDB_PCI_IO_SIZE - 1, + IORESOURCE_IO +}; static struct resource extpci_mem_resource = { "pci memory space", DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ - DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE -1, - IORESOURCE_MEM}; + DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1, + IORESOURCE_MEM +}; extern struct pci_ops ddb5476_ext_pci_ops; struct pci_channel mips_pci_channels[] = { - { &ddb5476_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource }, - { NULL, NULL, NULL} + {&ddb5476_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource}, + {NULL, NULL, NULL} }; @@ -53,10 +55,13 @@ struct pci_channel mips_pci_channels[] = { static unsigned char irq_map[MAX_SLOT_NUM] = { /* SLOT: 0, AD:11 */ 0xff, /* SLOT: 1, AD:12 */ 0xff, - /* SLOT: 2, AD:13 */ 9, /* USB */ - /* SLOT: 3, AD:14 */ 10, /* PMU */ + /* SLOT: 2, AD:13 */ 9, + /* USB */ + /* SLOT: 3, AD:14 */ 10, + /* PMU */ /* SLOT: 4, AD:15 */ 0xff, - /* SLOT: 5, AD:16 */ 0x0, /* P2P bridge */ + /* SLOT: 5, AD:16 */ 0x0, + /* P2P bridge */ /* SLOT: 6, AD:17 */ nile4_to_irq(PCI_EXT_INTB), /* SLOT: 7, AD:18 */ nile4_to_irq(PCI_EXT_INTC), /* SLOT: 8, AD:19 */ nile4_to_irq(PCI_EXT_INTD), @@ -64,7 +69,8 @@ static unsigned char irq_map[MAX_SLOT_NUM] = { /* SLOT: 10, AD:21 */ 0xff, /* SLOT: 11, AD:22 */ 0xff, /* SLOT: 12, AD:23 */ 0xff, - /* SLOT: 13, AD:24 */ 14, /* HD controller, M5229 */ + /* SLOT: 13, AD:24 */ 14, + /* HD controller, M5229 */ /* SLOT: 14, AD:25 */ 0xff, /* SLOT: 15, AD:26 */ 0xff, /* SLOT: 16, AD:27 */ 0xff, @@ -77,15 +83,16 @@ static unsigned char irq_map[MAX_SLOT_NUM] = { extern int vrc5477_irq_to_irq(int irq); void __init pcibios_fixup_irqs(void) { - struct pci_dev *dev; - int slot_num; + struct pci_dev *dev; + int slot_num; pci_for_each_dev(dev) { slot_num = PCI_SLOT(dev->devfn); /* we don't do IRQ fixup for sub-bus yet */ if (dev->bus->parent != NULL) { - db_run(printk("Don't know how to fixup irq for PCI device %d on sub-bus %d\n", + db_run(printk + ("Don't know how to fixup irq for PCI device %d on sub-bus %d\n", slot_num, dev->bus->number)); continue; } @@ -115,11 +122,11 @@ void __init ddb_pci_reset_bus(void) * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. * The same is true for both PCI channels. */ - temp = ddb_in32(DDB_PCICTRL+4); + temp = ddb_in32(DDB_PCICTRL + 4); temp |= 0x80000000; - ddb_out32(DDB_PCICTRL+4, temp); + ddb_out32(DDB_PCICTRL + 4, temp); temp &= ~0xc0000000; - ddb_out32(DDB_PCICTRL+4, temp); + ddb_out32(DDB_PCICTRL + 4, temp); } @@ -136,4 +143,3 @@ void __init pcibios_fixup_resources(struct pci_dev *dev) void __init pcibios_fixup(void) { } - diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c index 4e93d1556da..94262013b82 100644 --- a/arch/mips/pci/pci-ddb5477.c +++ b/arch/mips/pci/pci-ddb5477.c @@ -24,34 +24,38 @@ static struct resource extpci_io_resource = { "ext pci IO space", DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000, - DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE -1, - IORESOURCE_IO}; + DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1, + IORESOURCE_IO +}; static struct resource extpci_mem_resource = { "ext pci memory space", DDB_PCI0_MEM_BASE + 0x100000, - DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE -1, - IORESOURCE_MEM}; + DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1, + IORESOURCE_MEM +}; static struct resource iopci_io_resource = { "io pci IO space", DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE, - DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE -1, - IORESOURCE_IO}; + DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1, + IORESOURCE_IO +}; static struct resource iopci_mem_resource = { "ext pci memory space", DDB_PCI1_MEM_BASE, - DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE -1, - IORESOURCE_MEM}; + DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1, + IORESOURCE_MEM +}; extern struct pci_ops ddb5477_ext_pci_ops; extern struct pci_ops ddb5477_io_pci_ops; struct pci_channel mips_pci_channels[] = { - { &ddb5477_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource }, - { &ddb5477_io_pci_ops, &iopci_io_resource, &iopci_mem_resource }, - { NULL, NULL, NULL} + {&ddb5477_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource}, + {&ddb5477_io_pci_ops, &iopci_io_resource, &iopci_mem_resource}, + {NULL, NULL, NULL} }; @@ -78,11 +82,16 @@ static unsigned char irq_map[MAX_SLOT_NUM] = { /* SLOT: 1, AD:12 */ 0xff, /* SLOT: 2, AD:13 */ 0xff, /* SLOT: 3, AD:14 */ 0xff, - /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */ - /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */ - /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */ - /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */ - /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */ + /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, + /* onboard tulip */ + /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, + /* slot 1 */ + /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, + /* slot 2 */ + /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, + /* slot 3 */ + /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, + /* slot 4 */ /* SLOT: 9, AD:20 */ 0xff, /* SLOT: 10, AD:21 */ 0xff, /* SLOT: 11, AD:22 */ 0xff, @@ -92,40 +101,54 @@ static unsigned char irq_map[MAX_SLOT_NUM] = { /* SLOT: 15, AD:26 */ 0xff, /* SLOT: 16, AD:27 */ 0xff, /* SLOT: 17, AD:28 */ 0xff, - /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */ - /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */ - /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */ + /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, + /* vrc5477 ac97 */ + /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, + /* vrc5477 usb peri */ + /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, + /* vrc5477 usb host */ }; static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = { /* SLOT: 0, AD:11 */ 0xff, - /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */ + /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, + /* onboard AMD PCNET */ /* SLOT: 2, AD:13 */ 0xff, /* SLOT: 3, AD:14 */ 0xff, - /* SLOT: 4, AD:15 */ 14, /* M5229 ide ISA irq */ - /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */ - /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */ - /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */ - /* SLOT: 8, AD:19 */ 0, /* M5457 modem nop */ - /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */ - /* SLOT: 10, AD:21 */ 0xff, + /* SLOT: 4, AD:15 */ 14, + /* M5229 ide ISA irq */ + /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, + /* slot 3 */ + /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, + /* slot 4 */ + /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, + /* slot 5 */ + /* SLOT: 8, AD:19 */ 0, + /* M5457 modem nop */ + /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, + /* slot 2 */ + /* SLOT: 10, AD:21 */ 0xff, /* SLOT: 11, AD:22 */ 0xff, /* SLOT: 12, AD:23 */ 0xff, /* SLOT: 13, AD:24 */ 0xff, /* SLOT: 14, AD:25 */ 0xff, /* SLOT: 15, AD:26 */ 0xff, /* SLOT: 16, AD:27 */ 0xff, - /* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */ - /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */ - /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */ - /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */ + /* SLOT: 17, AD:28 */ 0, + /* M7101 PMU nop */ + /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, + /* vrc5477 ac97 */ + /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, + /* vrc5477 usb peri */ + /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, + /* vrc5477 usb host */ }; void __init pcibios_fixup_irqs(void) { - struct pci_dev *dev; - int slot_num; - unsigned char *slot_irq_map; - unsigned char irq; + struct pci_dev *dev; + int slot_num; + unsigned char *slot_irq_map; + unsigned char irq; if (mips_machtype == MACH_NEC_ROCKHOPPERII) slot_irq_map = rockhopperII_irq_map; @@ -139,11 +162,9 @@ void __init pcibios_fixup_irqs(void) db_assert(slot_num < MAX_SLOT_NUM); - db_assert(irq != 0xff); + db_assert(irq != 0xff); - pci_write_config_byte(dev, - PCI_INTERRUPT_LINE, - irq); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); dev->irq = irq; @@ -154,7 +175,7 @@ void __init pcibios_fixup_irqs(void) * Make the M1535 USB - ISA IRQ number 9. */ if (slot_num == 20 && dev->bus->number == 0) { - pci_write_config_byte(dev, + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 9); dev->irq = 9; @@ -217,16 +238,16 @@ void __init fix_amd_lance(struct pci_dev *dev) unsigned long ioaddr; u16 temp; - ioaddr=pci_resource_start(dev, 0); + ioaddr = pci_resource_start(dev, 0); - inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ + inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ - /* bcr_18 |= 0x0800 */ - outw (18, ioaddr + PCNET32_WIO_RAP); - temp = inw (ioaddr + PCNET32_WIO_BDP); + /* bcr_18 |= 0x0800 */ + outw(18, ioaddr + PCNET32_WIO_RAP); + temp = inw(ioaddr + PCNET32_WIO_BDP); temp |= 0x0800; - outw (18, ioaddr + PCNET32_WIO_RAP); - outw (temp, ioaddr + PCNET32_WIO_BDP); + outw(18, ioaddr + PCNET32_WIO_RAP); + outw(temp, ioaddr + PCNET32_WIO_BDP); } void __init pcibios_fixup(void) @@ -240,7 +261,8 @@ void __init pcibios_fixup(void) printk("Configuring ALI M1535 Super I/O mouse irq.\n"); - request_region(M1535_CONFIG_PORT, 2, "M1535 Super I/O config"); + request_region(M1535_CONFIG_PORT, 2, + "M1535 Super I/O config"); /* Enter config mode. */ outb(0x51, M1535_CONFIG_PORT); @@ -257,21 +279,24 @@ void __init pcibios_fixup(void) /* Exit config mode. */ outb(0xbb, M1535_CONFIG_PORT); - pci_for_each_dev(dev) { - if(dev->vendor == PCI_VENDOR_ID_AL) - if(dev->device == PCI_DEVICE_ID_AL_M1535 - || dev->device == PCI_DEVICE_ID_AL_M1533) { - u8 old; - printk("Enabling ALI M1533/35 PS2 keyboard/mouse.\n"); - pci_read_config_byte(dev, 0x41, &old); - pci_write_config_byte(dev, 0x41, old | 0xd0); - } - - if (dev->vendor == PCI_VENDOR_ID_AMD && - dev->device == PCI_DEVICE_ID_AMD_LANCE) + pci_for_each_dev(dev) { + if (dev->vendor == PCI_VENDOR_ID_AL) + if (dev->device == PCI_DEVICE_ID_AL_M1535 + || dev->device == + PCI_DEVICE_ID_AL_M1533) { + u8 old; + printk + ("Enabling ALI M1533/35 PS2 keyboard/mouse.\n"); + pci_read_config_byte(dev, 0x41, + &old); + pci_write_config_byte(dev, 0x41, + old | 0xd0); + } + + if (dev->vendor == PCI_VENDOR_ID_AMD && + dev->device == PCI_DEVICE_ID_AMD_LANCE) fix_amd_lance(dev); } - + } } - diff --git a/arch/mips/pci/pci-hplj.c b/arch/mips/pci/pci-hplj.c dissimilarity index 60% index 0a877d3a436..d78e2d663b9 100644 --- a/arch/mips/pci/pci-hplj.c +++ b/arch/mips/pci/pci-hplj.c @@ -1,224 +1,253 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * SNI specific PCI support for RM200/RM300. - * - * Copyright (C) 1997 - 2000 Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include - -volatile u32* pci_config_address_reg = (volatile u32*)0xfdead000; -volatile u32* pci_config_data_reg = (volatile u32*)0xfdead000; - - - -#define cfgaddr(dev, where) (((dev->bus->number & 0xff) << 0x10) | \ - ((dev->devfn & 0xff) << 0x08) | \ - (where & 0xfc)) - -/* - * We can't address 8 and 16 bit words directly. Instead we have to - * read/write a 32bit word and mask/modify the data we actually want. - */ -static int pcimt_read_config_byte (struct pci_dev *dev, - int where, unsigned char *val) -{ - *pci_config_address_reg = cfgaddr(dev, where); - *val = (le32_to_cpu(*pci_config_data_reg) >> ((where&3)<<3)) & 0xff; - //printk("pci_read_byte 0x%x == 0x%x\n", where, *val); - return PCIBIOS_SUCCESSFUL; -} - -static int pcimt_read_config_word (struct pci_dev *dev, - int where, unsigned short *val) -{ - if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; - *pci_config_address_reg = cfgaddr(dev, where); - *val = (le32_to_cpu(*pci_config_data_reg) >> ((where&3)<<3)) & 0xffff; - //printk("pci_read_word 0x%x == 0x%x\n", where, *val); - return PCIBIOS_SUCCESSFUL; -} - -int pcimt_read_config_dword (struct pci_dev *dev, - int where, unsigned int *val) -{ - if (where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; - *pci_config_address_reg = cfgaddr(dev, where); - *val = le32_to_cpu(*pci_config_data_reg); - //printk("pci_read_dword 0x%x == 0x%x\n", where, *val); - return PCIBIOS_SUCCESSFUL; -} - -static int pcimt_write_config_byte (struct pci_dev *dev, - int where, unsigned char val) -{ - *pci_config_address_reg = cfgaddr(dev, where); - *(volatile u8 *)(((int)pci_config_data_reg) + (where & 3)) = val; - //printk("pci_write_byte 0x%x = 0x%x\n", where, val); - return PCIBIOS_SUCCESSFUL; -} - -static int pcimt_write_config_word (struct pci_dev *dev, - int where, unsigned short val) -{ - if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; - *pci_config_address_reg = cfgaddr(dev, where); - *(volatile u16 *)(((int)pci_config_data_reg) + (where & 2)) = - le16_to_cpu(val); - //printk("pci_write_word 0x%x = 0x%x\n", where, val); - return PCIBIOS_SUCCESSFUL; -} - -int pcimt_write_config_dword (struct pci_dev *dev, - int where, unsigned int val) -{ - if (where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; - *pci_config_address_reg = cfgaddr(dev, where); - *pci_config_data_reg = le32_to_cpu(val); - //printk("pci_write_dword 0x%x = 0x%x\n", where, val); - return PCIBIOS_SUCCESSFUL; -} - - - -struct pci_ops hp_pci_ops = { - pcimt_read_config_byte, - pcimt_read_config_word, - pcimt_read_config_dword, - pcimt_write_config_byte, - pcimt_write_config_word, - pcimt_write_config_dword -}; - - -struct pci_channel mips_pci_channels[] = { - { &hp_pci_ops, &ioport_resource, &iomem_resource }, - { NULL, NULL, NULL } -}; - -unsigned __init int pcibios_assign_all_busses(void) -{ - return 1; -} - -void __init pcibios_fixup(void) -{ -} - - -void __init pcibios_fixup_irqs(void) -{ - struct pci_dev *dev; - int slot_num; - - - pci_for_each_dev(dev) { - slot_num = PCI_SLOT(dev->devfn); - switch(slot_num) { - case 2: dev->irq = 3; break; - case 3: dev->irq = 4; break; - case 4: dev->irq = 5; break; - default: break; - } - } -} - -#define IO_MEM_LOGICAL_START 0x3e000000 -#define IO_MEM_LOGICAL_END 0x3fefffff - -#define IO_PORT_LOGICAL_START 0x3ff00000 -#define IO_PORT_LOGICAL_END 0x3fffffff - - -#define IO_MEM_VIRTUAL_OFFSET 0xb0000000 -#define IO_PORT_VIRTUAL_OFFSET 0xb0000000 - -#define ONE_MEG (1024 * 1024) - -void __init pci_setup(void) -{ - u32 pci_regs_base_offset = 0xfdead000; - - switch(GetAsicId()) { - case AndrosAsic: pci_regs_base_offset = 0xbff80000; break; - case HarmonyAsic: pci_regs_base_offset = 0xbff70000; break; - default: - printk("ERROR: PCI does not support %s Asic\n", GetAsicName()); - while(1); - break; - } - - // set bus stat/command reg - // REVIST this setting may need vary depending on the hardware - *((volatile unsigned int*)(pci_regs_base_offset | 0x0004)) = 0x38000007; - - - iomem_resource.start = IO_MEM_LOGICAL_START + IO_MEM_VIRTUAL_OFFSET; - iomem_resource.end = IO_MEM_LOGICAL_END + IO_MEM_VIRTUAL_OFFSET; - - ioport_resource.start = IO_PORT_LOGICAL_START + IO_PORT_VIRTUAL_OFFSET; - ioport_resource.end = IO_PORT_LOGICAL_END + IO_PORT_VIRTUAL_OFFSET; - - // KLUDGE (mips_io_port_base is screwed up, we've got to work around it here) - // by letting both low (illegal) and high (legal) addresses appear in pci io space - ioport_resource.start = 0x0; - - set_io_port_base(IO_PORT_LOGICAL_START + IO_PORT_VIRTUAL_OFFSET); - - // map the PCI address space - // global map - all levels & processes can access - // except that the range is outside user space - // parameters: lo0, lo1, hi, pagemask - // lo indicates physical page, hi indicates virtual address - add_wired_entry((IO_MEM_LOGICAL_START >> 6) | 0x17, - ((IO_MEM_LOGICAL_START + (16 * ONE_MEG)) >> 6) | 0x17, - 0xee000000, PM_16M); - - - // These are used in pci r/w routines so need to preceed bus scan - pci_config_data_reg = (u32*) (((u32)mips_io_port_base) | 0xcfc); - pci_config_address_reg = (u32*) (((u32)pci_regs_base_offset) | 0xcf8); - -} - - -void __init pcibios_fixup_resources(struct pci_dev *dev) -{ - int pos; - int bases; - - printk("adjusting pci device: %s\n", dev->name); - - switch (dev->hdr_type) { - case PCI_HEADER_TYPE_NORMAL: bases = 6; break; - case PCI_HEADER_TYPE_BRIDGE: bases = 2; break; - case PCI_HEADER_TYPE_CARDBUS: bases = 1; break; - default: bases = 0; break; - } - for (pos=0; pos < bases; pos++) { - struct resource* res = &dev->resource[pos]; - if (res->start >= IO_MEM_LOGICAL_START && - res->end <= IO_MEM_LOGICAL_END) { - res->start += IO_MEM_VIRTUAL_OFFSET; - res->end += IO_MEM_VIRTUAL_OFFSET; - } - if (res->start >= IO_PORT_LOGICAL_START && - res->end <= IO_PORT_LOGICAL_END) { - res->start += IO_PORT_VIRTUAL_OFFSET; - res->end += IO_PORT_VIRTUAL_OFFSET; - } - } - -} +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * SNI specific PCI support for RM200/RM300. + * + * Copyright (C) 1997 - 2000 Ralf Baechle + */ +#include +#include +#include +#include +#include +#include +#include + +volatile u32 *pci_config_address_reg = (volatile u32 *) 0xfdead000; +volatile u32 *pci_config_data_reg = (volatile u32 *) 0xfdead000; + + + +#define cfgaddr(dev, where) (((dev->bus->number & 0xff) << 0x10) | \ + ((dev->devfn & 0xff) << 0x08) | \ + (where & 0xfc)) + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int pcimt_read_config_byte(struct pci_dev *dev, + int where, unsigned char *val) +{ + *pci_config_address_reg = cfgaddr(dev, where); + *val = + (le32_to_cpu(*pci_config_data_reg) >> ((where & 3) << 3)) & + 0xff; + //printk("pci_read_byte 0x%x == 0x%x\n", where, *val); + return PCIBIOS_SUCCESSFUL; +} + +static int pcimt_read_config_word(struct pci_dev *dev, + int where, unsigned short *val) +{ + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + *pci_config_address_reg = cfgaddr(dev, where); + *val = + (le32_to_cpu(*pci_config_data_reg) >> ((where & 3) << 3)) & + 0xffff; + //printk("pci_read_word 0x%x == 0x%x\n", where, *val); + return PCIBIOS_SUCCESSFUL; +} + +int pcimt_read_config_dword(struct pci_dev *dev, + int where, unsigned int *val) +{ + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + *pci_config_address_reg = cfgaddr(dev, where); + *val = le32_to_cpu(*pci_config_data_reg); + //printk("pci_read_dword 0x%x == 0x%x\n", where, *val); + return PCIBIOS_SUCCESSFUL; +} + +static int pcimt_write_config_byte(struct pci_dev *dev, + int where, unsigned char val) +{ + *pci_config_address_reg = cfgaddr(dev, where); + *(volatile u8 *) (((int) pci_config_data_reg) + (where & 3)) = val; + //printk("pci_write_byte 0x%x = 0x%x\n", where, val); + return PCIBIOS_SUCCESSFUL; +} + +static int pcimt_write_config_word(struct pci_dev *dev, + int where, unsigned short val) +{ + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + *pci_config_address_reg = cfgaddr(dev, where); + *(volatile u16 *) (((int) pci_config_data_reg) + (where & 2)) = + le16_to_cpu(val); + //printk("pci_write_word 0x%x = 0x%x\n", where, val); + return PCIBIOS_SUCCESSFUL; +} + +int pcimt_write_config_dword(struct pci_dev *dev, + int where, unsigned int val) +{ + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + *pci_config_address_reg = cfgaddr(dev, where); + *pci_config_data_reg = le32_to_cpu(val); + //printk("pci_write_dword 0x%x = 0x%x\n", where, val); + return PCIBIOS_SUCCESSFUL; +} + + + +struct pci_ops hp_pci_ops = { + pcimt_read_config_byte, + pcimt_read_config_word, + pcimt_read_config_dword, + pcimt_write_config_byte, + pcimt_write_config_word, + pcimt_write_config_dword +}; + + +struct pci_channel mips_pci_channels[] = { + {&hp_pci_ops, &ioport_resource, &iomem_resource}, + {NULL, NULL, NULL} +}; + +unsigned __init int pcibios_assign_all_busses(void) +{ + return 1; +} + +void __init pcibios_fixup(void) +{ +} + + +void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev; + int slot_num; + + + pci_for_each_dev(dev) { + slot_num = PCI_SLOT(dev->devfn); + switch (slot_num) { + case 2: + dev->irq = 3; + break; + case 3: + dev->irq = 4; + break; + case 4: + dev->irq = 5; + break; + default: + break; + } + } +} + +#define IO_MEM_LOGICAL_START 0x3e000000 +#define IO_MEM_LOGICAL_END 0x3fefffff + +#define IO_PORT_LOGICAL_START 0x3ff00000 +#define IO_PORT_LOGICAL_END 0x3fffffff + + +#define IO_MEM_VIRTUAL_OFFSET 0xb0000000 +#define IO_PORT_VIRTUAL_OFFSET 0xb0000000 + +#define ONE_MEG (1024 * 1024) + +void __init pci_setup(void) +{ + u32 pci_regs_base_offset = 0xfdead000; + + switch (GetAsicId()) { + case AndrosAsic: + pci_regs_base_offset = 0xbff80000; + break; + case HarmonyAsic: + pci_regs_base_offset = 0xbff70000; + break; + default: + printk("ERROR: PCI does not support %s Asic\n", + GetAsicName()); + while (1); + break; + } + + // set bus stat/command reg + // REVIST this setting may need vary depending on the hardware + *((volatile unsigned int *) (pci_regs_base_offset | 0x0004)) = + 0x38000007; + + + iomem_resource.start = + IO_MEM_LOGICAL_START + IO_MEM_VIRTUAL_OFFSET; + iomem_resource.end = IO_MEM_LOGICAL_END + IO_MEM_VIRTUAL_OFFSET; + + ioport_resource.start = + IO_PORT_LOGICAL_START + IO_PORT_VIRTUAL_OFFSET; + ioport_resource.end = IO_PORT_LOGICAL_END + IO_PORT_VIRTUAL_OFFSET; + + // KLUDGE (mips_io_port_base is screwed up, we've got to work around it here) + // by letting both low (illegal) and high (legal) addresses appear in pci io space + ioport_resource.start = 0x0; + + set_io_port_base(IO_PORT_LOGICAL_START + IO_PORT_VIRTUAL_OFFSET); + + // map the PCI address space + // global map - all levels & processes can access + // except that the range is outside user space + // parameters: lo0, lo1, hi, pagemask + // lo indicates physical page, hi indicates virtual address + add_wired_entry((IO_MEM_LOGICAL_START >> 6) | 0x17, + ((IO_MEM_LOGICAL_START + + (16 * ONE_MEG)) >> 6) | 0x17, 0xee000000, + PM_16M); + + + // These are used in pci r/w routines so need to preceed bus scan + pci_config_data_reg = (u32 *) (((u32) mips_io_port_base) | 0xcfc); + pci_config_address_reg = + (u32 *) (((u32) pci_regs_base_offset) | 0xcf8); + +} + + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ + int pos; + int bases; + + printk("adjusting pci device: %s\n", dev->name); + + switch (dev->hdr_type) { + case PCI_HEADER_TYPE_NORMAL: + bases = 6; + break; + case PCI_HEADER_TYPE_BRIDGE: + bases = 2; + break; + case PCI_HEADER_TYPE_CARDBUS: + bases = 1; + break; + default: + bases = 0; + break; + } + for (pos = 0; pos < bases; pos++) { + struct resource *res = &dev->resource[pos]; + if (res->start >= IO_MEM_LOGICAL_START && + res->end <= IO_MEM_LOGICAL_END) { + res->start += IO_MEM_VIRTUAL_OFFSET; + res->end += IO_MEM_VIRTUAL_OFFSET; + } + if (res->start >= IO_PORT_LOGICAL_START && + res->end <= IO_PORT_LOGICAL_END) { + res->start += IO_PORT_VIRTUAL_OFFSET; + res->end += IO_PORT_VIRTUAL_OFFSET; + } + } + +} diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index a8f9cb583d8..42453760ab5 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -64,9 +64,9 @@ do { \ } while (0) static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *value) + int where, int size, u32 * value) { - u32 vprod; + u32 vprod; CF0_READ_PCI_CFG(bus, devfn, PCI_VENDOR_ID, &vprod, 0, 0xffffffff); if (vprod == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)) @@ -78,9 +78,11 @@ static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, if (size == 1) CF0_READ_PCI_CFG(bus, devfn, where, (u8 *) value, 3, 0xff); else if (size == 2) - CF0_READ_PCI_CFG(bus, devfn, where, (u16 *) value, 2, 0xffff); + CF0_READ_PCI_CFG(bus, devfn, where, (u16 *) value, 2, + 0xffff); else - CF0_READ_PCI_CFG(bus, devfn, where, (u32 *) value, 0, 0xffffffff); + CF0_READ_PCI_CFG(bus, devfn, where, (u32 *) value, 0, + 0xffffffff); } #define CF0_WRITE_PCI_CFG(bus,devfn,where,value,bm,mask) \ @@ -106,9 +108,9 @@ do { \ } while (0) static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 value) + int where, int size, u32 value) { - u32 vprod; + u32 vprod; CF0_READ_PCI_CFG(bus, devfn, PCI_VENDOR_ID, &vprod, 0, 0xffffffff); if (vprod == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)) @@ -117,26 +119,28 @@ static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn, } if (size == 1) - CF0_WRITE_PCI_CFG(bus, devfn, where, (u8) value, 3,0xff); + CF0_WRITE_PCI_CFG(bus, devfn, where, (u8) value, 3, 0xff); else if (size == 2) - CF0_WRITE_PCI_CFG(bus, devfn, where, (u16) value, 2,0xffff); + CF0_WRITE_PCI_CFG(bus, devfn, where, (u16) value, 2, + 0xffff); else - CF0_WRITE_PCI_CFG(bus, devfn, where, (u32) value, 0,0xffffffff); + CF0_WRITE_PCI_CFG(bus, devfn, where, (u32) value, 0, + 0xffffffff); } static struct pci_ops bridge_pci_ops = { - .read = pci_conf0_read_config, - .write = pci_conf0_write_config, + .read = pci_conf0_read_config, + .write = pci_conf0_write_config, }; static int __init pcibios_init(void) { struct pci_ops *ops = &bridge_pci_ops; - int i; + int i; ioport_resource.end = ~0UL; - for (i=0; i < num_bridges; i++) { + for (i = 0; i < num_bridges; i++) { printk("PCI: Probing PCI hardware on host bus %2d.\n", i); pci_scan_bus(i, ops, NULL); } @@ -148,10 +152,10 @@ subsys_initcall(pcibios_init); static inline u8 bridge_swizzle(u8 pin, u8 slot) { - return (((pin-1) + slot) % 4) + 1; + return (((pin - 1) + slot) % 4) + 1; } -static u8 __devinit pci_swizzle(struct pci_dev *dev, u8 *pinp) +static u8 __devinit pci_swizzle(struct pci_dev *dev, u8 * pinp) { u8 pin = *pinp; @@ -211,7 +215,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) } void pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) + unsigned long size, unsigned long align) { } @@ -220,7 +224,7 @@ unsigned int pcibios_assign_all_busses(void) return 0; } -char * __devinit pcibios_setup(char *str) +char *__devinit pcibios_setup(char *str) { /* Nothing to do for now. */ @@ -238,34 +242,35 @@ static void __init pci_disable_swapping(struct pci_dev *dev) { unsigned int bus_id = (unsigned) dev->bus->number; bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], - bus_to_wid[bus_id]); - int slot = PCI_SLOT(dev->devfn); + bus_to_wid[bus_id]); + int slot = PCI_SLOT(dev->devfn); /* Turn off byte swapping */ bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR; - bridge->b_widget.w_tflush; /* Flush */ + bridge->b_widget.w_tflush; /* Flush */ } static void __init pci_enable_swapping(struct pci_dev *dev) { unsigned int bus_id = (unsigned) dev->bus->number; bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], - bus_to_wid[bus_id]); - int slot = PCI_SLOT(dev->devfn); + bus_to_wid[bus_id]); + int slot = PCI_SLOT(dev->devfn); /* Turn on byte swapping */ bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; - bridge->b_widget.w_tflush; /* Flush */ + bridge->b_widget.w_tflush; /* Flush */ } static void __init pci_fixup_ioc3(struct pci_dev *d) { unsigned long bus_id = (unsigned) d->bus->number; - printk("PCI: Fixing base addresses for IOC3 device %s\n", d->slot_name); + printk("PCI: Fixing base addresses for IOC3 device %s\n", + d->slot_name); d->resource[0].start |= NODE_OFFSET(bus_to_nid[bus_id]); - d->resource[0].end |= NODE_OFFSET(bus_to_nid[bus_id]); + d->resource[0].end |= NODE_OFFSET(bus_to_nid[bus_id]); pci_disable_swapping(d); } @@ -274,7 +279,8 @@ static void __init pci_fixup_isp1020(struct pci_dev *d) { unsigned short command; - d->resource[0].start |= ((unsigned long)(bus_to_nid[d->bus->number])<<32); + d->resource[0].start |= + ((unsigned long) (bus_to_nid[d->bus->number]) << 32); printk("PCI: Fixing isp1020 in [bus:slot.fn] %s\n", d->slot_name); /* @@ -298,17 +304,17 @@ static void __init pci_fixup_isp2x00(struct pci_dev *d) { unsigned int bus_id = (unsigned) d->bus->number; bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], - bus_to_wid[bus_id]); - bridgereg_t devreg; - int i; - int slot = PCI_SLOT(d->devfn); - unsigned int start; + bus_to_wid[bus_id]); + bridgereg_t devreg; + int i; + int slot = PCI_SLOT(d->devfn); + unsigned int start; unsigned short command; printk("PCI: Fixing isp2x00 in [bus:slot.fn] %s\n", d->slot_name); /* set the resource struct for this device */ - start = (u32) (u64)bridge; /* yes, we want to lose the upper 32 bits here */ + start = (u32) (u64) bridge; /* yes, we want to lose the upper 32 bits here */ start |= BRIDGE_DEVIO(slot); d->resource[0].start = start; @@ -335,10 +341,10 @@ static void __init pci_fixup_isp2x00(struct pci_dev *d) //pci_write_config_dword(d, PCI_BASE_ADDRESS_1, 0x8b00000); //pci_write_config_dword(d, PCI_ROM_ADDRESS, 0x8b20000); - /* I got these from booting irix on system...*/ + /* I got these from booting irix on system... */ pci_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x200001); //pci_write_config_dword(d, PCI_BASE_ADDRESS_1, 0xf800000); - pci_write_config_dword(d, PCI_ROM_ADDRESS, 0x10200000); + pci_write_config_dword(d, PCI_ROM_ADDRESS, 0x10200000); pci_write_config_dword(d, PCI_BASE_ADDRESS_1, start); //pci_write_config_dword(d, PCI_ROM_ADDRESS, (start | 0x20000)); @@ -355,9 +361,10 @@ static void __init pci_fixup_isp2x00(struct pci_dev *d) bridge->b_int_host_err = 0x44; bridge->b_wid_tflush; - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ - for (i=0; i<8; i++) - printk("PCI: device(%d)= 0x%x\n",i,bridge->b_device[i].reg); + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + for (i = 0; i < 8; i++) + printk("PCI: device(%d)= 0x%x\n", i, + bridge->b_device[i].reg); /* configure device to allow bus mastering, i/o and memory mapping */ pci_set_master(d); @@ -365,17 +372,20 @@ static void __init pci_fixup_isp2x00(struct pci_dev *d) command |= PCI_COMMAND_MEMORY; command |= PCI_COMMAND_IO; pci_write_config_word(d, PCI_COMMAND, command); - /*d->resource[1].flags |= 1;*/ + /*d->resource[1].flags |= 1; */ } struct pci_fixup pcibios_fixups[] = { - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, - pci_fixup_ioc3 }, - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP1020, - pci_fixup_isp1020 }, - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100, - pci_fixup_isp2x00 }, - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200, - pci_fixup_isp2x00 }, - { 0 } + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, + pci_fixup_ioc3}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, + PCI_DEVICE_ID_QLOGIC_ISP1020, + pci_fixup_isp1020}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, + PCI_DEVICE_ID_QLOGIC_ISP2100, + pci_fixup_isp2x00}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, + PCI_DEVICE_ID_QLOGIC_ISP2200, + pci_fixup_isp2x00}, + {0} }; diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c index a15af7b59b6..e85c3ea4bc0 100644 --- a/arch/mips/pci/pci-ip32.c +++ b/arch/mips/pci/pci-ip32.c @@ -38,92 +38,98 @@ do { \ #define mkaddr(_devfn, where) \ ((((_devfn) & 0xffUL) << 8) | ((where) & 0xfcUL)) -void macepci_error (int irq, void *dev, struct pt_regs *regs); +void macepci_error(int irq, void *dev, struct pt_regs *regs); static int macepci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) + int where, int size, u32 * val) { switch (size) { case 1: *val = 0xff; - chkslot (bus,devfn); - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (devfn, where)); - *val = mace_read_8 (MACEPCI_CONFIG_DATA + ((where & 3UL) ^ 3UL)); + chkslot(bus, devfn); + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + *val = + mace_read_8(MACEPCI_CONFIG_DATA + + ((where & 3UL) ^ 3UL)); return PCIBIOS_SUCCESSFUL; case 2: *val = 0xffff; - chkslot (bus,devfn); + chkslot(bus, devfn); if (where & 1) return PCIBIOS_BAD_REGISTER_NUMBER; - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (devfn, where)); - *val = mace_read_16 (MACEPCI_CONFIG_DATA + ((where & 2UL) ^ 2UL)); + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + *val = + mace_read_16(MACEPCI_CONFIG_DATA + + ((where & 2UL) ^ 2UL)); return PCIBIOS_SUCCESSFUL; case 4: *val = 0xffffffff; - chkslot (bus,devfn); + chkslot(bus, devfn); if (where & 3) return PCIBIOS_BAD_REGISTER_NUMBER; - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (devfn, where)); - *val = mace_read_32 (MACEPCI_CONFIG_DATA); + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + *val = mace_read_32(MACEPCI_CONFIG_DATA); return PCIBIOS_SUCCESSFUL; } } static int macepci_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) + int where, int size, u32 val) { switch (size) { case 1: - chkslot (bus,devfn); - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (devfn, where)); - mace_write_8 (MACEPCI_CONFIG_DATA + ((where & 3UL) ^ 3UL), val); + chkslot(bus, devfn); + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + mace_write_8(MACEPCI_CONFIG_DATA + ((where & 3UL) ^ 3UL), + val); return PCIBIOS_SUCCESSFUL; case 2: - chkslot (bus,devfn); + chkslot(bus, devfn); if (where & 1) return PCIBIOS_BAD_REGISTER_NUMBER; - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (devfn, where)); - mace_write_16 (MACEPCI_CONFIG_DATA + ((where & 2UL) ^ 2UL), val); + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + mace_write_16(MACEPCI_CONFIG_DATA + ((where & 2UL) ^ 2UL), + val); return PCIBIOS_SUCCESSFUL; case 4: - chkslot (bus,devfn); + chkslot(bus, devfn); if (where & 3) return PCIBIOS_BAD_REGISTER_NUMBER; - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (devfn, where)); - mace_write_32 (MACEPCI_CONFIG_DATA, val); + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + mace_write_32(MACEPCI_CONFIG_DATA, val); return PCIBIOS_SUCCESSFUL; } } static struct pci_ops macepci_ops = { - .read = macepci_read_config, - .write = macepci_write_config, + .read = macepci_read_config, + .write = macepci_write_config, }; -struct pci_fixup pcibios_fixups[] = { { 0 } }; +struct pci_fixup pcibios_fixups[] = { {0} }; -static int __init pcibios_init (void) +static int __init pcibios_init(void) { struct pci_dev *dev; u32 start, size; u16 cmd; - u32 base_io = 0x3000; /* The first i/o address to assign after SCSI */ - u32 base_mem = 0x80100000; /* Likewise */ - u32 rev = mace_read_32 (MACEPCI_REV); + u32 base_io = 0x3000; /* The first i/o address to assign after SCSI */ + u32 base_mem = 0x80100000; /* Likewise */ + u32 rev = mace_read_32(MACEPCI_REV); int i; - printk ("MACE: PCI rev %d detected at %016lx\n", rev, - (u64) MACE_BASE + MACE_PCI); + printk("MACE: PCI rev %d detected at %016lx\n", rev, + (u64) MACE_BASE + MACE_PCI); /* These are *bus* addresses */ ioport_resource.start = 0; @@ -132,30 +138,31 @@ static int __init pcibios_init (void) iomem_resource.end = 0xffffffffUL; /* Clear any outstanding errors and enable interrupts */ - mace_write_32 (MACEPCI_ERROR_ADDR, 0); - mace_write_32 (MACEPCI_ERROR_FLAGS, 0); - mace_write_32 (MACEPCI_CONTROL, 0xff008500); - crime_write_64 (CRIME_HARD_INT, 0UL); - crime_write_64 (CRIME_SOFT_INT, 0UL); - crime_write_64 (CRIME_INT_STAT, 0x000000000000ff00UL); - - if (request_irq (MACE_PCI_BRIDGE_IRQ, macepci_error, 0, - "MACE PCI error", NULL)) + mace_write_32(MACEPCI_ERROR_ADDR, 0); + mace_write_32(MACEPCI_ERROR_FLAGS, 0); + mace_write_32(MACEPCI_CONTROL, 0xff008500); + crime_write_64(CRIME_HARD_INT, 0UL); + crime_write_64(CRIME_SOFT_INT, 0UL); + crime_write_64(CRIME_INT_STAT, 0x000000000000ff00UL); + + if (request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0, + "MACE PCI error", NULL)) panic("PCI bridge can't get interrupt; can't happen."); - pci_scan_bus (0, &macepci_ops, NULL); + pci_scan_bus(0, &macepci_ops, NULL); #ifdef DEBUG_MACE_PCI - pci_for_each_dev (dev) { - printk ("Device: %d/%d/%d ARCS-assigned bus resource map\n", - dev->bus->number, PCI_SLOT (dev->devfn), - PCI_FUNC (dev->devfn)); - for (i=0; i < DEVICE_COUNT_RESOURCE; i++) { + pci_for_each_dev(dev) { + printk("Device: %d/%d/%d ARCS-assigned bus resource map\n", + dev->bus->number, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn)); + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { if (dev->resource[i].start == 0) continue; - printk ("%d: %016lx - %016lx (flags %04lx)\n", - i, dev->resource[i].start, - dev->resource[i].end, dev->resource[i].flags); + printk("%d: %016lx - %016lx (flags %04lx)\n", + i, dev->resource[i].start, + dev->resource[i].end, + dev->resource[i].flags); } } #endif @@ -165,58 +172,63 @@ static int __init pcibios_init (void) * which we must assign, and a 1-page memory region which is * assigned by the system firmware. */ - pci_for_each_dev (dev) { - switch (PCI_SLOT (dev->devfn)) { - case 1: /* SCSI bus 0 */ + pci_for_each_dev(dev) { + switch (PCI_SLOT(dev->devfn)) { + case 1: /* SCSI bus 0 */ dev->resource[0].start = 0x1000UL; dev->resource[0].end = 0x10ffUL; break; - case 2: /* SCSI bus 1 */ + case 2: /* SCSI bus 1 */ dev->resource[0].start = 0x2000UL; dev->resource[0].end = 0x20ffUL; break; - default: /* Slots - I guess we have only 1 */ - for (i=0; i < 6; i++) { + default: /* Slots - I guess we have only 1 */ + for (i = 0; i < 6; i++) { size = dev->resource[i].end - - dev->resource[i].start; + - dev->resource[i].start; if (!size || !(dev->resource[i].flags - & (IORESOURCE_IO|IORESOURCE_MEM))) { - dev->resource[i].start - = dev->resource[i].end = 0UL; + & (IORESOURCE_IO | + IORESOURCE_MEM))) { + dev->resource[i].start = + dev->resource[i].end = 0UL; continue; } if (dev->resource[i].flags & IORESOURCE_IO) { dev->resource[i].start = base_io; - base_io += PAGE_ALIGN (size); + base_io += PAGE_ALIGN(size); } else { dev->resource[i].start = base_mem; base_mem += 0x100000UL; } dev->resource[i].end = - dev->resource[i].start + size; + dev->resource[i].start + size; } break; } - for (i=0; i < 6; i++) { + for (i = 0; i < 6; i++) { if (dev->resource[i].start == 0) continue; start = dev->resource[i].start; if (dev->resource[i].flags & IORESOURCE_IO) start |= 1; - pci_write_config_dword (dev, - PCI_BASE_ADDRESS_0 + (i << 2), (u32) start); + pci_write_config_dword(dev, + PCI_BASE_ADDRESS_0 + + (i << 2), (u32) start); } - pci_write_config_byte (dev, PCI_CACHE_LINE_SIZE, 0x20); - pci_write_config_byte (dev, PCI_LATENCY_TIMER, 0x30); - pci_read_config_word (dev, PCI_COMMAND, &cmd); - cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY); - pci_write_config_word (dev, PCI_COMMAND, cmd); - pci_set_master (dev); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x20); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x30); + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= + (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | + PCI_COMMAND_PARITY); + pci_write_config_word(dev, PCI_COMMAND, cmd); + pci_set_master(dev); } - /* - * Fixup O2 PCI slot. Bad hack. - */ + /* + * Fixup O2 PCI slot. Bad hack. + */ /* devtag = pci_make_tag(0, 0, 3, 0); slot = macepci_conf_read(0, devtag, PCI_COMMAND_STATUS_REG); @@ -235,19 +247,20 @@ static int __init pcibios_init (void) } */ #ifdef DEBUG_MACE_PCI - printk ("Triggering PCI bridge interrupt...\n"); - mace_write_32 (MACEPCI_ERROR_FLAGS, MACEPCI_ERROR_INTERRUPT_TEST); - - pci_for_each_dev (dev) { - printk ("Device: %d/%d/%d final bus resource map\n", - dev->bus->number, PCI_SLOT (dev->devfn), - PCI_FUNC (dev->devfn)); - for (i=0; i < DEVICE_COUNT_RESOURCE; i++) { + printk("Triggering PCI bridge interrupt...\n"); + mace_write_32(MACEPCI_ERROR_FLAGS, MACEPCI_ERROR_INTERRUPT_TEST); + + pci_for_each_dev(dev) { + printk("Device: %d/%d/%d final bus resource map\n", + dev->bus->number, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn)); + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { if (dev->resource[i].start == 0) continue; - printk ("%d: %016lx - %016lx (flags %04lx)\n", - i, dev->resource[i].start, - dev->resource[i].end, dev->resource[i].flags); + printk("%d: %016lx - %016lx (flags %04lx)\n", + i, dev->resource[i].start, + dev->resource[i].end, + dev->resource[i].flags); } } #endif @@ -266,7 +279,7 @@ subsys_initcall(pcibios_init); */ static int __devinit macepci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - chkslot (dev->bus,dev->devfn); + chkslot(dev->bus, dev->devfn); if (pin == 0) pin = 1; switch (slot) { @@ -320,13 +333,13 @@ static int __devinit macepci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) * It's not entirely clear what this does in a system with no bridges. * In any case, bridges are not supported by Linux in O2. */ -static u8 __init macepci_swizzle(struct pci_dev *dev, u8 *pinp) +static u8 __init macepci_swizzle(struct pci_dev *dev, u8 * pinp) { - if (PCI_SLOT (dev->devfn) == 2) + if (PCI_SLOT(dev->devfn) == 2) *pinp = 2; else *pinp = 1; - return PCI_SLOT (dev->devfn); + return PCI_SLOT(dev->devfn); } /* All devices are enabled during initialization. */ @@ -335,24 +348,24 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return PCIBIOS_SUCCESSFUL; } -char * __init pcibios_setup (char *str) +char *__init pcibios_setup(char *str) { return str; } void pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) + unsigned long size, unsigned long align) { } void __init pcibios_update_irq(struct pci_dev *dev, int irq) { - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } void __devinit pcibios_fixup_bus(struct pci_bus *b) { - pci_fixup_irqs (macepci_swizzle, macepci_map_irq); + pci_fixup_irqs(macepci_swizzle, macepci_map_irq); } /* @@ -366,72 +379,73 @@ void macepci_error(int irq, void *dev, struct pt_regs *regs) u32 flags, error_addr; char space; - flags = mace_read_32 (MACEPCI_ERROR_FLAGS); - error_addr = mace_read_32 (MACEPCI_ERROR_ADDR); + flags = mace_read_32(MACEPCI_ERROR_FLAGS); + error_addr = mace_read_32(MACEPCI_ERROR_ADDR); if (flags & MACEPCI_ERROR_MEMORY_ADDR) space = 'M'; else if (flags & MACEPCI_ERROR_CONFIG_ADDR) space = 'C'; - else space = 'X'; + else + space = 'X'; if (flags & MACEPCI_ERROR_MASTER_ABORT) { - printk ("MACEPCI: Master abort at 0x%08x (%c)\n", error_addr, - space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_MASTER_ABORT); + printk("MACEPCI: Master abort at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, + flags & ~MACEPCI_ERROR_MASTER_ABORT); } if (flags & MACEPCI_ERROR_TARGET_ABORT) { - printk ("MACEPCI: Target abort at 0x%08x (%c)\n", error_addr, - space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_TARGET_ABORT); + printk("MACEPCI: Target abort at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, + flags & ~MACEPCI_ERROR_TARGET_ABORT); } if (flags & MACEPCI_ERROR_DATA_PARITY_ERR) { - printk ("MACEPCI: Data parity error at 0x%08x (%c)\n", - error_addr, space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_DATA_PARITY_ERR); + printk("MACEPCI: Data parity error at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_DATA_PARITY_ERR); } if (flags & MACEPCI_ERROR_RETRY_ERR) { - printk ("MACEPCI: Retry error at 0x%08x (%c)\n", error_addr, - space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_RETRY_ERR); + printk("MACEPCI: Retry error at 0x%08x (%c)\n", error_addr, + space); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_RETRY_ERR); } if (flags & MACEPCI_ERROR_ILLEGAL_CMD) { - printk ("MACEPCI: Illegal command at 0x%08x (%c)\n", - error_addr, space); - mace_write_32 (MACEPCI_ERROR_FLAGS, - flags & ~MACEPCI_ERROR_ILLEGAL_CMD); + printk("MACEPCI: Illegal command at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, + flags & ~MACEPCI_ERROR_ILLEGAL_CMD); } if (flags & MACEPCI_ERROR_SYSTEM_ERR) { - printk ("MACEPCI: System error at 0x%08x (%c)\n", - error_addr, space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_SYSTEM_ERR); + printk("MACEPCI: System error at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_SYSTEM_ERR); } if (flags & MACEPCI_ERROR_PARITY_ERR) { - printk ("MACEPCI: Parity error at 0x%08x (%c)\n", error_addr, - space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_PARITY_ERR); + printk("MACEPCI: Parity error at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, + flags & ~MACEPCI_ERROR_PARITY_ERR); } if (flags & MACEPCI_ERROR_OVERRUN) { - printk ("MACEPCI: Overrun error at 0x%08x (%c)\n", - error_addr, space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_OVERRUN); + printk("MACEPCI: Overrun error at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_OVERRUN); } if (flags & MACEPCI_ERROR_SIG_TABORT) { - printk ("MACEPCI: Signaled target abort (clearing)\n"); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_SIG_TABORT); + printk("MACEPCI: Signaled target abort (clearing)\n"); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_SIG_TABORT); } if (flags & MACEPCI_ERROR_INTERRUPT_TEST) { - printk ("MACEPCI: Interrupt test triggered (clearing)\n"); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_INTERRUPT_TEST); + printk("MACEPCI: Interrupt test triggered (clearing)\n"); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_INTERRUPT_TEST); } } diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c index 45bdcad09be..971153fd871 100644 --- a/arch/mips/pci/pci-lasat.c +++ b/arch/mips/pci/pci-lasat.c @@ -17,8 +17,10 @@ #define Dprintk(fmt...) #endif -static int (*lasat_pcibios_config_access)(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, int where, u32 *val); +static int (*lasat_pcibios_config_access) (unsigned char access_type, + struct pci_bus * bus, + unsigned int devfn, int where, + u32 * val); /* * Because of an error/peculiarity in the Galileo chip, we need to swap the @@ -31,41 +33,43 @@ static int (*lasat_pcibios_config_access)(unsigned char access_type, static int lasat_pcibios_config_access_100(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, int where, u32 *val) + struct pci_bus *bus, + unsigned int devfn, int where, + u32 * val) { unsigned char busnum = bus->number; - u32 intr; + u32 intr; - if ((busnum == 0) && (devfn >= PCI_DEVFN(31,0))) - return -1; /* Because of a bug in the Galileo (for slot 31). */ + if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) + return -1; /* Because of a bug in the Galileo (for slot 31). */ /* Clear cause register bits */ - GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT) ); + GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); /* Setup address */ - GT_WRITE( GT_PCI0_CFGADDR_OFS, - (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) | - (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | - ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | - GT_PCI0_CFGADDR_CONFIGEN_BIT ); + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + GT_PCI0_CFGADDR_CONFIGEN_BIT); if (access_type == PCI_ACCESS_WRITE) { - GT_WRITE( GT_PCI0_CFGDATA_OFS, *val ); + GT_WRITE(GT_PCI0_CFGDATA_OFS, *val); } else { - GT_READ( GT_PCI0_CFGDATA_OFS, *val ); + GT_READ(GT_PCI0_CFGDATA_OFS, *val); } /* Check for master or target abort */ - GT_READ( GT_INTRCAUSE_OFS, intr ); + GT_READ(GT_INTRCAUSE_OFS, intr); - if( intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT) ) - { - /* Error occurred */ + if (intr & + (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { + /* Error occurred */ - /* Clear bits */ - GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT) ); + /* Clear bits */ + GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); return -1; } @@ -76,10 +80,12 @@ static int lasat_pcibios_config_access_100(unsigned char access_type, #define LO(reg) (reg / 4) #define HI(reg) (reg / 4 + 1) -volatile unsigned long * const vrc_pciregs = (void *)Vrc5074_BASE; +volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE; static int lasat_pcibios_config_access_200(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, int where, u32 *val) + struct pci_bus *bus, + unsigned int devfn, int where, + u32 * val) { unsigned char busnum = bus->number; u32 adr, mask, err; @@ -90,19 +96,20 @@ static int lasat_pcibios_config_access_200(unsigned char access_type, * controller itself) */ return -1; - if ((busnum == 0) && (devfn == PCI_DEVFN(0,0))) { + if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) { /* Access controller registers directly */ if (access_type == PCI_ACCESS_WRITE) { - vrc_pciregs[(0x200+where) >> 2] = *val; + vrc_pciregs[(0x200 + where) >> 2] = *val; } else { - *val = vrc_pciregs[(0x200+where) >> 2]; + *val = vrc_pciregs[(0x200 + where) >> 2]; } - return 0; + return 0; } /* Temporarily map PCI Window 1 to config space */ mask = vrc_pciregs[LO(NILE4_PCIINIT1)]; - vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0); + vrc_pciregs[LO(NILE4_PCIINIT1)] = + 0x0000001a | (busnum ? 0x200 : 0); /* Clear PCI Error register. This also clears the Error Type * bits in the Control register */ @@ -111,18 +118,24 @@ static int lasat_pcibios_config_access_200(unsigned char access_type, /* Setup address */ if (busnum == 0) - adr = KSEG1ADDR(PCI_WINDOW1) + ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8) | (where & ~3)); + adr = + KSEG1ADDR(PCI_WINDOW1) + + ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8) + | (where & ~3)); else - adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) | (where & ~3); + adr = + KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) + | (where & ~3); #ifdef DEBUG_PCI - printk("PCI config %s: adr %x", access_type == PCI_ACCESS_WRITE ? "write" : "read", adr); + printk("PCI config %s: adr %x", + access_type == PCI_ACCESS_WRITE ? "write" : "read", adr); #endif if (access_type == PCI_ACCESS_WRITE) { - *(u32 *)adr = *val; + *(u32 *) adr = *val; } else { - *val = *(u32 *)adr; + *val = *(u32 *) adr; } #ifdef DEBUG_PCI @@ -135,11 +148,11 @@ static int lasat_pcibios_config_access_200(unsigned char access_type, /* Restore PCI Window 1 */ vrc_pciregs[LO(NILE4_PCIINIT1)] = mask; - if (err) - { + if (err) { /* Error occured */ #ifdef DEBUG_PCI - printk("\terror %x at adr %x\n", err, vrc_pciregs[LO(PCIERR)]); + printk("\terror %x at adr %x\n", err, + vrc_pciregs[LO(PCIERR)]); #endif return -1; } @@ -147,8 +160,8 @@ static int lasat_pcibios_config_access_200(unsigned char access_type, return 0; } -static int lasat_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) +static int lasat_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) { u32 data = 0; @@ -158,8 +171,8 @@ static int lasat_pcibios_read(struct pci_bus *bus, unsigned int devfn, return PCIBIOS_BAD_REGISTER_NUMBER; if (lasat_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, - &data)) - return -1; + &data)) + return -1; if (size == 1) *val = (data >> ((where & 3) << 3)) & 0xff; @@ -172,39 +185,39 @@ static int lasat_pcibios_read(struct pci_bus *bus, unsigned int devfn, } static int lasat_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) + int where, int size, u32 val) { - u32 data = 0; + u32 data = 0; if ((size == 2) && (where & 1)) return PCIBIOS_BAD_REGISTER_NUMBER; else if ((size == 4) && (where & 3)) return PCIBIOS_BAD_REGISTER_NUMBER; - if (lasat_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, - &data)) - return -1; + if (lasat_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data)) + return -1; if (size == 1) data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + (val << ((where & 3) << 3)); else if (size == 2) data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + (val << ((where & 3) << 3)); - if (lasat_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, - &data)) - return -1; + if (lasat_pcibios_config_access + (PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; return PCIBIOS_SUCCESSFUL; } struct pci_ops lasat_pci_ops = { - .read = lasat_pcibios_read, - .write = lasat_pcibios_write, + .read = lasat_pcibios_read, + .write = lasat_pcibios_write, }; -char * __init pcibios_setup(char *str) +char *__init pcibios_setup(char *str) { return str; } @@ -213,10 +226,12 @@ static int __init pcibios_init(void) { switch (mips_machtype) { case MACH_LASAT_100: - lasat_pcibios_config_access = &lasat_pcibios_config_access_100; + lasat_pcibios_config_access = + &lasat_pcibios_config_access_100; break; case MACH_LASAT_200: - lasat_pcibios_config_access = &lasat_pcibios_config_access_200; + lasat_pcibios_config_access = + &lasat_pcibios_config_access_200; break; default: panic("pcibios_init: mips_machtype incorrect"); @@ -241,7 +256,7 @@ int __init pcibios_enable_device(struct pci_dev *dev, int mask) } void __init pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) + unsigned long size, unsigned long align) { } @@ -251,5 +266,5 @@ unsigned __init int pcibios_assign_all_busses(void) } struct pci_fixup pcibios_fixups[] = { - { 0 } + {0} }; diff --git a/arch/mips/pci/pci-mips.c b/arch/mips/pci/pci-mips.c index a10cf0540e8..5abc260bb92 100644 --- a/arch/mips/pci/pci-mips.c +++ b/arch/mips/pci/pci-mips.c @@ -49,21 +49,23 @@ #define PCI_CFG_TYPE1_BUS_SHF 16 static int mips_pcibios_config_access(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, int where, u32 *data) + struct pci_bus *bus, + unsigned int devfn, int where, + u32 * data) { unsigned char busnum = bus->number; unsigned char type; u32 intr, dummy; u64 pci_addr; - switch(mips_revision_corid) { + switch (mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: - /* Galileo GT64120 system controller. */ + /* Galileo GT64120 system controller. */ - if ((busnum == 0) && (devfn >= PCI_DEVFN(31,0))) - return -1; /* Because of a bug in the galileo (for slot 31). */ + if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) + return -1; /* Because of a bug in the galileo (for slot 31). */ /* Clear cause register bits */ GT_READ(GT_INTRCAUSE_OFS, intr); @@ -73,9 +75,9 @@ static int mips_pcibios_config_access(unsigned char access_type, /* Setup address */ GT_WRITE(GT_PCI0_CFGADDR_OFS, - (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) | - (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | - ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | GT_PCI0_CFGADDR_CONFIGEN_BIT); if (access_type == PCI_ACCESS_WRITE) { @@ -104,8 +106,7 @@ static int mips_pcibios_config_access(unsigned char access_type, GT_READ(GT_INTRCAUSE_OFS, intr); if (intr & (GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT)) - { + GT_INTRCAUSE_TARABORT0_BIT)) { /* Error occurred */ /* Clear bits */ @@ -121,10 +122,10 @@ static int mips_pcibios_config_access(unsigned char access_type, case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: - /* Algorithmics Bonito64 system controller. */ + /* Algorithmics Bonito64 system controller. */ - if ((busnum == 0) && (PCI_SLOT(devfn) == 0)) { - return -1; + if ((busnum == 0) && (PCI_SLOT(devfn) == 0)) { + return -1; } /* Clear cause register bits */ @@ -136,14 +137,15 @@ static int mips_pcibios_config_access(unsigned char access_type, * Type 0 cycle */ if (busnum == 0) { - /* IDSEL */ - pci_addr = (u64)1 << (PCI_SLOT(devfn) + 10); + /* IDSEL */ + pci_addr = (u64) 1 << (PCI_SLOT(devfn) + 10); } else { - /* Bus number */ - pci_addr = busnum << PCI_CFG_TYPE1_BUS_SHF; + /* Bus number */ + pci_addr = busnum << PCI_CFG_TYPE1_BUS_SHF; /* Device number */ - pci_addr |= PCI_SLOT(devfn) << PCI_CFG_TYPE1_DEV_SHF; + pci_addr |= + PCI_SLOT(devfn) << PCI_CFG_TYPE1_DEV_SHF; } /* Function (same for Type 0/1) */ @@ -153,50 +155,50 @@ static int mips_pcibios_config_access(unsigned char access_type, pci_addr |= (where & ~0x3) << PCI_CFG_TYPE0_REG_SHF; if (busnum == 0) { - /* Type 0 */ - BONITO_PCIMAP_CFG = pci_addr >> 16; + /* Type 0 */ + BONITO_PCIMAP_CFG = pci_addr >> 16; } else { - /* Type 1 */ - BONITO_PCIMAP_CFG = (pci_addr >> 16) | 0x10000; + /* Type 1 */ + BONITO_PCIMAP_CFG = (pci_addr >> 16) | 0x10000; } /* Flush Bonito register block */ dummy = BONITO_PCIMAP_CFG; - iob(); /* sync */ + iob(); /* sync */ /* Perform access */ if (access_type == PCI_ACCESS_WRITE) { - *(volatile u32 *)(KSEG1ADDR(BONITO_PCICFG_BASE + - (pci_addr & 0xffff))) = *(u32 *)data; + *(volatile u32 *) (KSEG1ADDR(BONITO_PCICFG_BASE + + (pci_addr & 0xffff))) + = *(u32 *) data; /* Wait till done */ - while (BONITO_PCIMSTAT & 0xF) - ; + while (BONITO_PCIMSTAT & 0xF); } else { - *(u32 *)data = - *(volatile u32 *)(KSEG1ADDR(BONITO_PCICFG_BASE + + *(u32 *) data = + *(volatile u32 + *) (KSEG1ADDR(BONITO_PCICFG_BASE + (pci_addr & 0xffff))); } /* Detect Master/Target abort */ if (BONITO_PCICMD & (BONITO_PCICMD_MABORT_CLR | - BONITO_PCICMD_MTABORT_CLR) ) - { - /* Error occurred */ + BONITO_PCICMD_MTABORT_CLR)) { + /* Error occurred */ - /* Clear bits */ - BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR | + /* Clear bits */ + BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR); return -1; } - break; + break; case MIPS_REVISION_CORID_CORE_MSC: - /* MIPS system controller. */ + /* MIPS system controller. */ - if ((busnum == 0) && (PCI_SLOT(devfn) == 0)) { - return -1; + if ((busnum == 0) && (PCI_SLOT(devfn) == 0)) { + return -1; } /* Clear status register bits. */ @@ -206,20 +208,22 @@ static int mips_pcibios_config_access(unsigned char access_type, /* Setup address */ if (busnum == 0) - type = 0; /* Type 0 */ + type = 0; /* Type 0 */ else - type = 1; /* Type 1 */ + type = 1; /* Type 1 */ MSC_WRITE(MSC01_PCI_CFGADDR, - ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) | - (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) | - (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) | - ((where /4 ) << MSC01_PCI_CFGADDR_RNUM_SHF) | - (type))); + ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) | + (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) + | (PCI_FUNC(devfn) << + MSC01_PCI_CFGADDR_FNUM_SHF) | ((where / + 4) << + MSC01_PCI_CFGADDR_RNUM_SHF) + | (type))); /* Perform access */ if (access_type == PCI_ACCESS_WRITE) { - MSC_WRITE(MSC01_PCI_CFGDATA, *data); + MSC_WRITE(MSC01_PCI_CFGDATA, *data); } else { MSC_READ(MSC01_PCI_CFGDATA, *data); } @@ -227,11 +231,10 @@ static int mips_pcibios_config_access(unsigned char access_type, /* Detect Master/Target abort */ MSC_READ(MSC01_PCI_INTSTAT, intr); if (intr & (MSC01_PCI_INTCFG_MA_BIT | - MSC01_PCI_INTCFG_TA_BIT)) - { - /* Error occurred */ + MSC01_PCI_INTCFG_TA_BIT)) { + /* Error occurred */ - /* Clear bits */ + /* Clear bits */ MSC_READ(MSC01_PCI_INTSTAT, intr); MSC_WRITE(MSC01_PCI_INTSTAT, (MSC01_PCI_INTCFG_MA_BIT | @@ -239,9 +242,10 @@ static int mips_pcibios_config_access(unsigned char access_type, return -1; } - break; + break; default: - printk("Unknown Core card, don't know the system controller.\n"); + printk + ("Unknown Core card, don't know the system controller.\n"); return -1; } @@ -253,8 +257,8 @@ static int mips_pcibios_config_access(unsigned char access_type, * We can't address 8 and 16 bit words directly. Instead we have to * read/write a 32bit word and mask/modify the data we actually want. */ -static int mips_pcibios_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *val) +static int mips_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) { u32 data = 0; @@ -264,8 +268,8 @@ static int mips_pcibios_read(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_BAD_REGISTER_NUMBER; if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, - &data)) - return -1; + &data)) + return -1; if (size == 1) *val = (data >> ((where & 3) << 3)) & 0xff; @@ -278,7 +282,7 @@ static int mips_pcibios_read(struct pci_bus *bus, unsigned int devfn, int where, } static int mips_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) + int where, int size, u32 val) { u32 data = 0; @@ -287,39 +291,39 @@ static int mips_pcibios_write(struct pci_bus *bus, unsigned int devfn, else if ((size == 4) && (where & 3)) return PCIBIOS_BAD_REGISTER_NUMBER; - if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, - &data)) - return -1; + if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data)) + return -1; if (size == 1) data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + (val << ((where & 3) << 3)); else if (size == 2) data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + (val << ((where & 3) << 3)); if (mips_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, - &data)) - return -1; + &data)) + return -1; return PCIBIOS_SUCCESSFUL; } struct pci_ops mips_pci_ops = { - .read = mips_pcibios_read, - .write = mips_pcibios_write + .read = mips_pcibios_read, + .write = mips_pcibios_write }; int mips_pcibios_iack(void) { int irq; - u32 dummy; + u32 dummy; /* * Determine highest priority pending interrupt by performing * a PCI Interrupt Acknowledge cycle. */ - switch(mips_revision_corid) { + switch (mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: @@ -341,15 +345,16 @@ int mips_pcibios_iack(void) /* Flush Bonito register block */ dummy = BONITO_PCIMAP_CFG; - iob(); /* sync */ + iob(); /* sync */ - irq = *(volatile u32 *)(KSEG1ADDR(BONITO_PCICFG_BASE)); - iob(); /* sync */ + irq = *(volatile u32 *) (KSEG1ADDR(BONITO_PCICFG_BASE)); + iob(); /* sync */ irq &= 0xff; BONITO_PCIMAP_CFG = 0; break; default: - printk("Unknown Core card, don't know the system controller.\n"); + printk + ("Unknown Core card, don't know the system controller.\n"); return -1; } return irq; @@ -365,7 +370,7 @@ static int __init pcibios_init(void) printk("PCI: Probing PCI hardware on host bus 0.\n"); pci_scan_bus(0, &mips_pci_ops, NULL); - switch(mips_revision_corid) { + switch (mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: @@ -376,15 +381,14 @@ static int __init pcibios_init(void) * fixed in a later revision of YAMON (the MIPS boards * boot prom). */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ - (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ - (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ - ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ - GT_PCI0_CFGADDR_CONFIGEN_BIT ); + GT_WRITE(GT_PCI0_CFGADDR_OFS, (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ + (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ + (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0 */ + ((0x20 / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4 */ + GT_PCI0_CFGADDR_CONFIGEN_BIT); /* Perform the write */ - GT_WRITE( GT_PCI0_CFGDATA_OFS, PHYSADDR(MIPS_GT_BASE)); + GT_WRITE(GT_PCI0_CFGDATA_OFS, PHYSADDR(MIPS_GT_BASE)); break; } @@ -397,9 +401,9 @@ static int __init pcibios_init(void) * IDE Decode enable. */ pci_read_config_byte(pdev, 0x41, ®_val); - pci_write_config_byte(pdev, 0x41, reg_val | 0x80); + pci_write_config_byte(pdev, 0x41, reg_val | 0x80); pci_read_config_byte(pdev, 0x43, ®_val); - pci_write_config_byte(pdev, 0x43, reg_val | 0x80); + pci_write_config_byte(pdev, 0x43, reg_val | 0x80); } if ((pdev->vendor == PCI_VENDOR_ID_INTEL) @@ -418,7 +422,7 @@ static int __init pcibios_init(void) * Activate Floppy Controller in the SMSC FDC37M817 Super I/O * Controller. * This should be done in the bios/bootprom and will be fixed in - * a later revision of YAMON (the MIPS boards boot prom). + * a later revision of YAMON (the MIPS boards boot prom). */ /* Entering config state. */ SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); @@ -445,11 +449,11 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) } void pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) + unsigned long size, unsigned long align) { } -char * __init pcibios_setup(char *str) +char *__init pcibios_setup(char *str) { /* Nothing to do for now. */ @@ -457,7 +461,7 @@ char * __init pcibios_setup(char *str) } struct pci_fixup pcibios_fixups[] = { - { 0 } + {0} }; /* diff --git a/arch/mips/pci/pci-ocelot-c.c b/arch/mips/pci/pci-ocelot-c.c index 84e4fb21ce5..d015b694407 100644 --- a/arch/mips/pci/pci-ocelot-c.c +++ b/arch/mips/pci/pci-ocelot-c.c @@ -40,7 +40,7 @@ #define MAX_PCI_DEVS 10 -void mv64340_board_pcibios_fixup_bus(struct pci_bus* c); +void mv64340_board_pcibios_fixup_bus(struct pci_bus *c); /* Functions to implement "pci ops" */ static int marvell_pcibios_read_config_word(struct pci_dev *dev, @@ -106,7 +106,7 @@ static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev) */ static int marvell_pcibios_read_config_dword(struct pci_dev *device, - int offset, u32* val) + int offset, u32 * val) { int dev, bus, func; uint32_t address_reg, data_reg; @@ -130,7 +130,7 @@ static int marvell_pcibios_read_config_dword(struct pci_dev *device, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ MV_WRITE(address_reg, address); @@ -143,7 +143,7 @@ static int marvell_pcibios_read_config_dword(struct pci_dev *device, static int marvell_pcibios_read_config_word(struct pci_dev *device, - int offset, u16* val) + int offset, u16 * val) { int dev, bus, func; uint32_t address_reg, data_reg; @@ -167,7 +167,7 @@ static int marvell_pcibios_read_config_word(struct pci_dev *device, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ MV_WRITE(address_reg, address); @@ -179,7 +179,7 @@ static int marvell_pcibios_read_config_word(struct pci_dev *device, } static int marvell_pcibios_read_config_byte(struct pci_dev *device, - int offset, u8* val) + int offset, u8 * val) { int dev, bus, func; uint32_t address_reg, data_reg; @@ -203,7 +203,7 @@ static int marvell_pcibios_read_config_byte(struct pci_dev *device, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ MV_WRITE(address_reg, address); @@ -239,7 +239,7 @@ static int marvell_pcibios_write_config_dword(struct pci_dev *device, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ MV_WRITE(address_reg, address); @@ -276,7 +276,7 @@ static int marvell_pcibios_write_config_word(struct pci_dev *device, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ MV_WRITE(address_reg, address); @@ -312,7 +312,7 @@ static int marvell_pcibios_write_config_byte(struct pci_dev *device, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ MV_WRITE(address_reg, address); @@ -367,15 +367,16 @@ int pcibios_enable_resources(struct pci_dev *dev) */ marvell_pcibios_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1); if (tmp1 != 8) { - printk(KERN_WARNING "PCI setting cache line size to 8 from " - "%d\n", tmp1); + printk(KERN_WARNING + "PCI setting cache line size to 8 from " "%d\n", + tmp1); marvell_pcibios_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); } marvell_pcibios_read_config_byte(dev, PCI_LATENCY_TIMER, &tmp1); if (tmp1 < 32) { - printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n", - tmp1); + printk(KERN_WARNING + "PCI setting latency timer to 32 from %d\n", tmp1); marvell_pcibios_write_config_byte(dev, PCI_LATENCY_TIMER, 32); } @@ -402,7 +403,7 @@ void pcibios_align_resource(void *data, struct resource *res, if (size > 0x100) { printk(KERN_ERR "PCI: I/O Region %s/%d too large" " (%ld bytes)\n", dev->slot_name, - dev->resource - res, size); + dev->resource - res, size); } start = (start + 1024 - 1) & ~(1024 - 1); @@ -432,9 +433,9 @@ void __init pcibios_init(void) { /* Reset PCI I/O and PCI MEM values */ ioport_resource.start = 0xe0000000; - ioport_resource.end = 0xe0000000 + 0x20000000 - 1; - iomem_resource.start = 0xc0000000; - iomem_resource.end = 0xc0000000 + 0x20000000 - 1; + ioport_resource.end = 0xe0000000 + 0x20000000 - 1; + iomem_resource.start = 0xc0000000; + iomem_resource.end = 0xc0000000 + 0x20000000 - 1; pci_scan_bus(0, &marvell_pci_ops, NULL); pci_scan_bus(1, &marvell_pci_ops, NULL); @@ -445,10 +446,10 @@ void __init pcibios_init(void) */ char *pcibios_setup(char *str) { - printk(KERN_INFO "rr: pcibios_setup\n"); - /* Nothing to do for now. */ + printk(KERN_INFO "rr: pcibios_setup\n"); + /* Nothing to do for now. */ - return str; + return str; } unsigned __init int pcibios_assign_all_busses(void) diff --git a/arch/mips/pci/pci-ocelot-g.c b/arch/mips/pci/pci-ocelot-g.c index b55c70d0b90..7255d230243 100644 --- a/arch/mips/pci/pci-ocelot-g.c +++ b/arch/mips/pci/pci-ocelot-g.c @@ -43,7 +43,7 @@ #define MAX_PCI_DEVS 10 -void gt64240_board_pcibios_fixup_bus(struct pci_bus* c); +void gt64240_board_pcibios_fixup_bus(struct pci_bus *c); /* Functions to implement "pci ops" */ static int galileo_pcibios_read_config_word(int bus, int devfn, @@ -63,9 +63,9 @@ static void galileo_pcibios_set_master(struct pci_dev *dev); #endif static int pci_read(struct pci_bus *bus, unsigned int devfs, int where, - int size, u32* val); + int size, u32 * val); static int pci_write(struct pci_bus *bus, unsigned int devfs, int where, - int size, u32 val); + int size, u32 val); /* * General-purpose PCI functions. @@ -116,7 +116,7 @@ static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev) */ static int galileo_pcibios_read_config_dword(int bus, int devfn, - int offset, u32* val) + int offset, u32 * val) { int dev, func; uint32_t address_reg, data_reg; @@ -143,7 +143,7 @@ static int galileo_pcibios_read_config_dword(int bus, int devfn, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ GT_WRITE(address_reg, address); @@ -156,7 +156,7 @@ static int galileo_pcibios_read_config_dword(int bus, int devfn, static int galileo_pcibios_read_config_word(int bus, int devfn, - int offset, u16* val) + int offset, u16 * val) { int dev, func; uint32_t address_reg, data_reg; @@ -183,7 +183,7 @@ static int galileo_pcibios_read_config_word(int bus, int devfn, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ GT_WRITE(address_reg, address); @@ -195,7 +195,7 @@ static int galileo_pcibios_read_config_word(int bus, int devfn, } static int galileo_pcibios_read_config_byte(int bus, int devfn, - int offset, u8* val) + int offset, u8 * val) { int dev, func; uint32_t address_reg, data_reg; @@ -220,7 +220,7 @@ static int galileo_pcibios_read_config_byte(int bus, int devfn, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ GT_WRITE(address_reg, address); @@ -257,7 +257,7 @@ static int galileo_pcibios_write_config_dword(int bus, int devfn, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ GT_WRITE(address_reg, address); @@ -295,7 +295,7 @@ static int galileo_pcibios_write_config_word(int bus, int devfn, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ GT_WRITE(address_reg, address); @@ -332,7 +332,7 @@ static int galileo_pcibios_write_config_byte(int bus, int devfn, } address = (bus << 16) | (dev << 11) | (func << 8) | - (offset & 0xfc) | 0x80000000; + (offset & 0xfc) | 0x80000000; /* start the configuration cycle */ GT_WRITE(address_reg, address); @@ -363,7 +363,7 @@ int pcibios_enable_resources(struct pci_dev *dev) int idx; struct resource *r; - pci_read(dev->bus, dev->devfn, PCI_COMMAND, 2, (u32*)&cmd); + pci_read(dev->bus, dev->devfn, PCI_COMMAND, 2, (u32 *) & cmd); old_cmd = cmd; for (idx = 0; idx < 6; idx++) { r = &dev->resource[idx]; @@ -387,16 +387,19 @@ int pcibios_enable_resources(struct pci_dev *dev) * line size = 32 bytes / sizeof dword (4) = 8. * Latency timer must be > 8. 32 is random but appears to work. */ - pci_read(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 1, (u32*)&tmp1); + pci_read(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 1, + (u32 *) & tmp1); if (tmp1 != 8) { - printk(KERN_WARNING "PCI setting cache line size to 8 from " - "%d\n", tmp1); + printk(KERN_WARNING + "PCI setting cache line size to 8 from " "%d\n", + tmp1); pci_write(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 1, 8); } - pci_read(dev->bus, dev->devfn, PCI_LATENCY_TIMER, 1, (u32*)&tmp1); + pci_read(dev->bus, dev->devfn, PCI_LATENCY_TIMER, 1, + (u32 *) & tmp1); if (tmp1 < 32) { - printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n", - tmp1); + printk(KERN_WARNING + "PCI setting latency timer to 32 from %d\n", tmp1); pci_write(dev->bus, dev->devfn, PCI_LATENCY_TIMER, 1, 32); } @@ -422,7 +425,7 @@ void pcibios_align_resource(void *data, struct resource *res, if (size > 0x100) { printk(KERN_ERR "PCI: I/O Region %s/%d too large" " (%ld bytes)\n", dev->slot_name, - dev->resource - res, size); + dev->resource - res, size); } start = (start + 1024 - 1) & ~(1024 - 1); @@ -436,35 +439,41 @@ struct pci_ops galileo_pci_ops = { }; static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32* val) + int size, u32 * val) { switch (size) { - case 1: - return galileo_pcibios_read_config_byte(bus->number, - devfn, where, (u8*) val); - case 2: - return galileo_pcibios_read_config_word(bus->number, - devfn, where, (u16*) val); - case 4: - return galileo_pcibios_read_config_dword(bus->number, - devfn, where, (u32*) val); + case 1: + return galileo_pcibios_read_config_byte(bus->number, + devfn, where, + (u8 *) val); + case 2: + return galileo_pcibios_read_config_word(bus->number, + devfn, where, + (u16 *) val); + case 4: + return galileo_pcibios_read_config_dword(bus->number, + devfn, where, + (u32 *) val); } return PCIBIOS_FUNC_NOT_SUPPORTED; } static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) + int size, u32 val) { switch (size) { - case 1: - return galileo_pcibios_write_config_byte(bus->number, - devfn, where, val); - case 2: - return galileo_pcibios_write_config_word(bus->number, - devfn, where, val); - case 4: - return galileo_pcibios_write_config_dword(bus->number, - devfn, where, val); + case 1: + return galileo_pcibios_write_config_byte(bus->number, + devfn, where, + val); + case 2: + return galileo_pcibios_write_config_word(bus->number, + devfn, where, + val); + case 4: + return galileo_pcibios_write_config_dword(bus->number, + devfn, where, + val); } return PCIBIOS_FUNC_NOT_SUPPORTED; } @@ -493,13 +502,13 @@ void __devinit pcibios_fixup_bus(struct pci_bus *c) * * Returns: true. */ -void pci0P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh, - unsigned int busNum,unsigned int devNum) +void pci0P2PConfig(unsigned int SecondBusLow, unsigned int SecondBusHigh, + unsigned int busNum, unsigned int devNum) { uint32_t regData; regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); + ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); GT_WRITE(PCI_0P2P_CONFIGURATION, regData); } @@ -517,13 +526,13 @@ void pci0P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh, * * Returns: true. */ -void pci1P2PConfig(unsigned int SecondBusLow,unsigned int SecondBusHigh, - unsigned int busNum,unsigned int devNum) +void pci1P2PConfig(unsigned int SecondBusLow, unsigned int SecondBusHigh, + unsigned int busNum, unsigned int devNum) { uint32_t regData; regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); + ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); GT_WRITE(PCI_1P2P_CONFIGURATION, regData); } @@ -534,9 +543,9 @@ static int __init pcibios_init(void) { /* Reset PCI I/O and PCI MEM values */ ioport_resource.start = 0xe0000000; - ioport_resource.end = 0xe0000000 + 0x20000000 - 1; - iomem_resource.start = 0xc0000000; - iomem_resource.end = 0xc0000000 + 0x20000000 - 1; + ioport_resource.end = 0xe0000000 + 0x20000000 - 1; + iomem_resource.start = 0xc0000000; + iomem_resource.end = 0xc0000000 + 0x20000000 - 1; pci_scan_bus(0, &galileo_pci_ops, NULL); pci_scan_bus(1, &galileo_pci_ops, NULL); @@ -551,10 +560,10 @@ subsys_initcall(pcibios_init); */ char *pcibios_setup(char *str) { - printk(KERN_INFO "rr: pcibios_setup\n"); - /* Nothing to do for now. */ + printk(KERN_INFO "rr: pcibios_setup\n"); + /* Nothing to do for now. */ - return str; + return str; } unsigned __init int pcibios_assign_all_busses(void) diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index ff0d5e93fa8..6aa4dab9a72 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -73,12 +73,12 @@ unsigned long ldt_eoi_space; */ static inline u32 READCFG32(u32 addr) { - return *(u32 *)(cfg_space + (addr&~3)); + return *(u32 *) (cfg_space + (addr & ~3)); } static inline void WRITECFG32(u32 addr, u32 data) { - *(u32 *)(cfg_space + (addr & ~3)) = data; + *(u32 *) (cfg_space + (addr & ~3)) = data; } /* @@ -96,8 +96,8 @@ static int sb1250_pci_can_access(struct pci_bus *bus, int devfn) if (bus->number == 0) { devno = PCI_SLOT(devfn); if (devno == LDT_BRIDGE_DEVICE) - return (sb1250_bus_status & LDT_BUS_ENABLED) != 0; - else if (sb1250_bus_status & PCI_DEVICE_MODE) + return (sb1250_bus_status & LDT_BUS_ENABLED) != 0; + else if (sb1250_bus_status & PCI_DEVICE_MODE) return 0; else return 1; @@ -112,7 +112,7 @@ static int sb1250_pci_can_access(struct pci_bus *bus, int devfn) */ static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) + int where, int size, u32 * val) { u32 data = 0; @@ -137,7 +137,7 @@ static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn, } static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) + int where, int size, u32 val) { u32 cfgaddr = CFGADDR(bus, devfn, where); u32 data = 0; @@ -154,10 +154,10 @@ static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn, if (size == 1) data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + (val << ((where & 3) << 3)); else if (size == 2) data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); + (val << ((where & 3) << 3)); WRITECFG32(cfgaddr, data); @@ -165,8 +165,8 @@ static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn, } struct pci_ops sb1250_pci_ops = { - .read = sb1250_pcibios_read, - .write = sb1250_pcibios_write + .read = sb1250_pcibios_read, + .write = sb1250_pcibios_write }; @@ -175,7 +175,8 @@ void __init pcibios_init(void) uint32_t cmdreg; uint64_t reg; - cfg_space = ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16*1024*1024); + cfg_space = + ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024); /* * See if the PCI bus has been configured by the firmware. @@ -184,8 +185,10 @@ void __init pcibios_init(void) if (!(reg & M_SYS_PCI_HOST)) { sb1250_bus_status |= PCI_DEVICE_MODE; } else { - cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), - PCI_COMMAND)); + cmdreg = + READCFG32(CFGOFFSET + (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), + PCI_COMMAND)); if (!(cmdreg & PCI_COMMAND_MASTER)) { printk ("PCI: Skipping PCI probe. Bus is not initialized.\n"); @@ -205,9 +208,9 @@ void __init pcibios_init(void) */ set_io_port_base((unsigned long) - ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536)); + ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536)); isa_slot_offset = (unsigned long) - ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024*1024); + ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024); #ifdef CONFIG_SIBYTE_HAS_LDT /* @@ -226,7 +229,8 @@ void __init pcibios_init(void) * (Kseg2/Kseg3) for 32-bit kernel. */ ldt_eoi_space = (unsigned long) - ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES, 4*1024*1024); + ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES, + 4 * 1024 * 1024); } #endif @@ -236,7 +240,7 @@ void __init pcibios_init(void) pci_scan_bus(0, &sb1250_pci_ops, NULL); #ifdef CONFIG_VGA_CONSOLE - take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1); + take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1); #endif } @@ -247,7 +251,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) } void pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) + unsigned long size, unsigned long align) { } diff --git a/arch/mips/pci/pci-sni.c b/arch/mips/pci/pci-sni.c index 49eb1a5b351..5f7e2116e55 100644 --- a/arch/mips/pci/pci-sni.c +++ b/arch/mips/pci/pci-sni.c @@ -26,7 +26,7 @@ do { \ #if 0 /* To do: Bring this uptodate ... */ -static void pcimt_pcibios_fixup (void) +static void pcimt_pcibios_fixup(void) { struct pci_dev *dev; @@ -37,7 +37,8 @@ static void pcimt_pcibios_fixup (void) */ if (dev->devfn == PCI_DEVFN(1, 0)) { /* Evil hack ... */ - set_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NO_WA); + set_cp0_config(CONF_CM_CMASK, + CONF_CM_CACHABLE_NO_WA); dev->irq = PCIMT_IRQ_SCSI; continue; } @@ -46,8 +47,8 @@ static void pcimt_pcibios_fixup (void) continue; } - switch(dev->irq) { - case 1 ... 4: + switch (dev->irq) { + case 1...4: dev->irq += PCIMT_IRQ_INTA - 1; break; case 0: @@ -66,30 +67,31 @@ static void pcimt_pcibios_fixup (void) * We can't address 8 and 16 bit words directly. Instead we have to * read/write a 32bit word and mask/modify the data we actually want. */ -static int pcimt_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) +static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 * val) { u32 res; switch (size) { case 1: mkaddr(bus, devfn, where); - res = *(volatile u32 *)PCIMT_CONFIG_DATA; + res = *(volatile u32 *) PCIMT_CONFIG_DATA; res = (le32_to_cpu(res) >> ((where & 3) << 3)) & 0xff; - *val = (u8)res; + *val = (u8) res; break; case 2: if (where & 1) return PCIBIOS_BAD_REGISTER_NUMBER; mkaddr(bus, devfn, where); - res = *(volatile u32 *)PCIMT_CONFIG_DATA; + res = *(volatile u32 *) PCIMT_CONFIG_DATA; res = (le32_to_cpu(res) >> ((where & 3) << 3)) & 0xffff; - *val = (u16)res; + *val = (u16) res; break; case 4: if (where & 3) return PCIBIOS_BAD_REGISTER_NUMBER; mkaddr(bus, devfn, where); - res = *(volatile u32 *)PCIMT_CONFIG_DATA; + res = *(volatile u32 *) PCIMT_CONFIG_DATA; res = le32_to_cpu(res); *val = res; break; @@ -98,26 +100,27 @@ static int pcimt_read (struct pci_bus *bus, unsigned int devfn, int where, int s return PCIBIOS_SUCCESSFUL; } -static int pcimt_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) +static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) { switch (size) { case 1: mkaddr(bus, devfn, where); - *(volatile u8 *)(PCIMT_CONFIG_DATA + (where & 3)) = - (u8)le32_to_cpu(val); + *(volatile u8 *) (PCIMT_CONFIG_DATA + (where & 3)) = + (u8) le32_to_cpu(val); break; case 2: if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; + return PCIBIOS_BAD_REGISTER_NUMBER; mkaddr(bus, devfn, where); - *(volatile u16 *)(PCIMT_CONFIG_DATA + (where & 3)) = - (u16)le32_to_cpu(val); + *(volatile u16 *) (PCIMT_CONFIG_DATA + (where & 3)) = + (u16) le32_to_cpu(val); break; case 4: if (where & 3) return PCIBIOS_BAD_REGISTER_NUMBER; mkaddr(bus, devfn, where); - *(volatile u32 *)PCIMT_CONFIG_DATA = le32_to_cpu(val); + *(volatile u32 *) PCIMT_CONFIG_DATA = le32_to_cpu(val); break; } @@ -125,15 +128,15 @@ static int pcimt_write (struct pci_bus *bus, unsigned int devfn, int where, int } struct pci_ops sni_pci_ops = { - .read = pcimt_read, - .write = pcimt_write, + .read = pcimt_read, + .write = pcimt_write, }; void __devinit pcibios_fixup_bus(struct pci_bus *b) { } -static int __init pcibios_init(void) +static int __init pcibios_init(void) { struct pci_ops *ops = &sni_pci_ops; @@ -151,7 +154,7 @@ int __init pcibios_enable_device(struct pci_dev *dev, int mask) } void pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) + unsigned long size, unsigned long align) { } @@ -160,8 +163,7 @@ unsigned __init int pcibios_assign_all_busses(void) return 0; } -char * __init -pcibios_setup(char *str) +char *__init pcibios_setup(char *str) { /* Nothing to do for now. */ @@ -169,5 +171,5 @@ pcibios_setup(char *str) } struct pci_fixup pcibios_fixups[] = { - { 0 } + {0} }; diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c index 5f1ae0cfad7..dbf784e0823 100644 --- a/arch/mips/pci/pci-vr41xx.c +++ b/arch/mips/pci/pci-vr41xx.c @@ -53,7 +53,8 @@ extern unsigned long vr41xx_vtclock; -static inline int vr41xx_pci_config_access(unsigned char bus, unsigned int devfn, int where) +static inline int vr41xx_pci_config_access(unsigned char bus, + unsigned int devfn, int where) { if (bus == 0) { /* @@ -62,10 +63,9 @@ static inline int vr41xx_pci_config_access(unsigned char bus, unsigned int devf if (PCI_SLOT(devfn) < 11 || where > 255) return -1; - writel((1UL << PCI_SLOT(devfn)) | - (PCI_FUNC(devfn) << 8) | - (where & 0xfc), - PCICONFAREG); + writel((1UL << PCI_SLOT(devfn)) | + (PCI_FUNC(devfn) << 8) | + (where & 0xfc), PCICONFAREG); } else { /* * Type 1 configuration @@ -73,17 +73,15 @@ static inline int vr41xx_pci_config_access(unsigned char bus, unsigned int devf if (where > 255) return -1; - writel((bus << 16) | - (devfn << 8) | - (where & 0xfc) | - 1UL, - PCICONFAREG); + writel((bus << 16) | + (devfn << 8) | (where & 0xfc) | 1UL, PCICONFAREG); } return 0; } -static int vr41xx_pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) +static int vr41xx_pci_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) { u32 data; @@ -110,7 +108,8 @@ static int vr41xx_pci_config_read(struct pci_bus *bus, unsigned int devfn, int w return PCIBIOS_SUCCESSFUL; } -static int vr41xx_pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) +static int vr41xx_pci_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) { u32 data; int shift; @@ -144,8 +143,8 @@ static int vr41xx_pci_config_write(struct pci_bus *bus, unsigned int devfn, int } struct pci_ops vr41xx_pci_ops = { - .read = vr41xx_pci_config_read, - .write = vr41xx_pci_config_write, + .read = vr41xx_pci_config_read, + .write = vr41xx_pci_config_write, }; void __init vr41xx_pciu_init(struct vr41xx_pci_address_map *map) @@ -189,22 +188,22 @@ void __init vr41xx_pciu_init(struct vr41xx_pci_address_map *map) if (map->mem1 != NULL) { s = map->mem1; config = (s->internal_base & 0xff000000) | - ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) | - ((s->pci_base & 0xff000000) >> 24); + ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) | + ((s->pci_base & 0xff000000) >> 24); writel(config, PCIMMAW1REG); } if (map->mem2 != NULL) { s = map->mem2; config = (s->internal_base & 0xff000000) | - ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) | - ((s->pci_base & 0xff000000) >> 24); + ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) | + ((s->pci_base & 0xff000000) >> 24); writel(config, PCIMMAW2REG); } if (map->io != NULL) { s = map->io; config = (s->internal_base & 0xff000000) | - ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) | - ((s->pci_base & 0xff000000) >> 24); + ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) | + ((s->pci_base & 0xff000000) >> 24); writel(config, PCIMIOAWREG); } @@ -227,9 +226,8 @@ void __init vr41xx_pciu_init(struct vr41xx_pci_address_map *map) writel(CONFIG_DONE, PCIENREG); pciu_write_config_dword(PCI_COMMAND, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | - PCI_COMMAND_PARITY | - PCI_COMMAND_SERR); + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR); } diff --git a/arch/mips/pci/pci-vr41xx.h b/arch/mips/pci/pci-vr41xx.h index bf666c7c156..0d281e26d3e 100644 --- a/arch/mips/pci/pci-vr41xx.h +++ b/arch/mips/pci/pci-vr41xx.h @@ -110,17 +110,17 @@ #define PCIU_CLOCK 0x0080 #define PCI_CLOCK 0x2000 -static inline int pciu_read_config_byte(int where, u8 *val) +static inline int pciu_read_config_byte(int where, u8 * val) { u32 data; data = readl(PCIU_CONFIGREGS_BASE + where); - *val = (u8)(data >> ((where & 3) << 3)); + *val = (u8) (data >> ((where & 3) << 3)); return PCIBIOS_SUCCESSFUL; } -static inline int pciu_read_config_word(int where, u16 *val) +static inline int pciu_read_config_word(int where, u16 * val) { u32 data; @@ -128,12 +128,12 @@ static inline int pciu_read_config_word(int where, u16 *val) return PCIBIOS_BAD_REGISTER_NUMBER; data = readl(PCIU_CONFIGREGS_BASE + where); - *val = (u16)(data >> ((where & 2) << 3)); + *val = (u16) (data >> ((where & 2) << 3)); return PCIBIOS_SUCCESSFUL; } -static inline int pciu_read_config_dword(int where, u32 *val) +static inline int pciu_read_config_dword(int where, u32 * val) { if (where & 3) return PCIBIOS_BAD_REGISTER_NUMBER; @@ -164,4 +164,4 @@ static inline int pciu_write_config_dword(int where, u32 val) return 0; } -#endif /* __VR41XX_PCIU_H */ +#endif /* __VR41XX_PCIU_H */ diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 3c9b2c9d985..957ba7f5879 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -66,8 +66,8 @@ extern void pcibios_fixup(void); extern void pcibios_fixup_irqs(void); -void __init pcibios_fixup_irqs(void) /* HP-LJ */ -{ +void __init pcibios_fixup_irqs(void) +{ /* HP-LJ */ struct pci_dev *dev; int slot_num; @@ -90,8 +90,8 @@ void __init pcibios_fixup_irqs(void) /* HP-LJ */ } } -void __init pcibios_fixup_resources(struct pci_dev *dev) /* HP-LJ */ -{ +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ /* HP-LJ */ int pos; int bases; @@ -128,11 +128,12 @@ void __init pcibios_fixup_resources(struct pci_dev *dev) /* HP-LJ */ } struct pci_fixup pcibios_fixups[] = { - { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources }, - { 0 } + {PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, + pcibios_fixup_resources}, + {0} }; -extern int pciauto_assign_resources(int busno, struct pci_channel * hose); +extern int pciauto_assign_resources(int busno, struct pci_channel *hose); static int __init pcibios_init(void) { @@ -142,17 +143,17 @@ static int __init pcibios_init(void) #ifdef CONFIG_PCI_AUTO /* assign resources */ - busno=0; - for (p= mips_pci_channels; p->pci_ops != NULL; p++) { + busno = 0; + for (p = mips_pci_channels; p->pci_ops != NULL; p++) { busno = pciauto_assign_resources(busno, p) + 1; } #endif /* scan the buses */ busno = 0; - for (p= mips_pci_channels; p->pci_ops != NULL; p++) { + for (p = mips_pci_channels; p->pci_ops != NULL; p++) { bus = pci_scan_bus(busno, p->pci_ops, p); - busno = bus->subordinate+1; + busno = bus->subordinate + 1; } /* machine dependent fixups */ @@ -203,9 +204,9 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) just link its resources to the bus ones */ int i; - for(i=0; i<3; i++) { + for (i = 0; i < 3; i++) { bus->resource[i] = - &dev->resource[PCI_BRIDGE_RESOURCES+i]; + &dev->resource[PCI_BRIDGE_RESOURCES + i]; bus->resource[i]->name = bus->name; } bus->resource[0]->flags |= pci_bridge_check_io(dev); @@ -215,7 +216,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) bus->resource[0]->end = hose->io_resource->end; bus->resource[1]->end = hose->mem_resource->end; /* Turn off downstream PF memory address range by default */ - bus->resource[2]->start = 1024*1024; + bus->resource[2]->start = 1024 * 1024; bus->resource[2]->end = bus->resource[2]->start - 1; } } @@ -226,7 +227,7 @@ char *pcibios_setup(char *str) } void pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) + unsigned long size, unsigned long align) { /* this should not be called */ } -- 2.11.4.GIT