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Goodbye mips64. 31704 lines of code bite the dust.
[linux-2.6/linux-mips.git] / include / sound / emu10k1.h
blob73b0b39352752de87615178b1273fd3e5cfe6729
1 #ifndef __SOUND_EMU10K1_H
2 #define __SOUND_EMU10K1_H
3
4 /*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
6 * Creative Labs, Inc.
7 * Definitions for EMU10K1 (SB Live!) chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26 #ifdef __KERNEL__
27
28 #include <sound/pcm.h>
29 #include <sound/rawmidi.h>
30 #include <sound/hwdep.h>
31 #include <sound/ac97_codec.h>
32 #include <sound/util_mem.h>
33 #include <linux/interrupt.h>
34 #include <asm/io.h>
35
36 #ifndef PCI_VENDOR_ID_CREATIVE
37 #define PCI_VENDOR_ID_CREATIVE 0x1102
38 #endif
39 #ifndef PCI_DEVICE_ID_CREATIVE_EMU10K1
40 #define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002
41 #endif
42
43 /* ------------------- DEFINES -------------------- */
44
45 #define EMUPAGESIZE 4096
46 #define MAXREQVOICES 8
47 #define MAXPAGES 8192
48 #define RESERVED 0
49 #define NUM_MIDI 16
50 #define NUM_G 64 /* use all channels */
51 #define NUM_FXSENDS 4
52
53 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
54 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit */
55
56 #define TMEMSIZE 256*1024
57 #define TMEMSIZEREG 4
58
59 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
60
61 // Audigy specify registers are prefixed with 'A_'
62
63 /************************************************************************************************/
64 /* PCI function 0 registers, address = <val> + PCIBASE0 */
65 /************************************************************************************************/
66
67 #define PTR 0x00 /* Indexed register set pointer register */
68 /* NOTE: The CHANNELNUM and ADDRESS words can */
69 /* be modified independently of each other. */
70 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
71 /* channel number of the register to be */
72 /* accessed. For non per-channel registers the */
73 /* value should be set to zero. */
74 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
75 #define A_PTR_ADDRESS_MASK 0x0fff0000
76
77 #define DATA 0x04 /* Indexed register set data register */
78
79 #define IPR 0x08 /* Global interrupt pending register */
80 /* Clear pending interrupts by writing a 1 to */
81 /* the relevant bits and zero to the other bits */
82
83 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
84 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
85 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
86
87 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
88 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
89 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
90 #define IPR_PCIERROR 0x00200000 /* PCI bus error */
91 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
92 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
93 #define IPR_MUTE 0x00040000 /* Mute button pressed */
94 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
95 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
96 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
97 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
98 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
99 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
100 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
101 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
102 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
103 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
104 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
105 #define IPR_CHANNELLOOP 0x00000040 /* One or more channel loop interrupts pending */
106 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
107 /* Highest set channel in CLIPL or CLIPH. When */
108 /* IP is written with CL set, the bit in CLIPL */
109 /* or CLIPH corresponding to the CIN value */
110 /* written will be cleared. */
111
112 #define INTE 0x0c /* Interrupt enable register */
113 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
114 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
115 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
116 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
117 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
118 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
119 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
120 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
121 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
122 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
123 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
124 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
125 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
126 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
127 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
128 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
129 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
130 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
131
132 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
133 /* NOTE: There is no reason to use this under */
134 /* Linux, and it will cause odd hardware */
135 /* behavior and possibly random segfaults and */
136 /* lockups if enabled. */
137
138 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
139 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
140 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
141
142
143 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
144 /* NOTE: This bit must always be enabled */
145 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
146 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
147 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
148 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
149 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
150 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
151 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
152 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
153 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
154 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
155 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
156 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
157 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
158
159 #define WC 0x10 /* Wall Clock register */
160 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
161 #define WC_SAMPLECOUNTER 0x14060010
162 #define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
163 /* NOTE: Each channel takes 1/64th of a sample */
164 /* period to be serviced. */
165
166 #define HCFG 0x14 /* Hardware config register */
167 /* NOTE: There is no reason to use the legacy */
168 /* SoundBlaster emulation stuff described below */
169 /* under Linux, and all kinds of weird hardware */
170 /* behavior can result if you try. Don't. */
171 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
172 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
173 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
174 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
175 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
176 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
177 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
178 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
179 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
180 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
181 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
182 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
183 /* NOTE: The rest of the bits in this register */
184 /* _are_ relevant under Linux. */
185 #define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */
186 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
187 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
188 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
189 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
190 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
191 #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
192 #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
193 #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
194 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
195 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
196 /* 1 = Force all 3 async digital inputs to use */
197 /* the same async sample rate tracker (ZVIDEO) */
198 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
199 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
200 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
201 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
202 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
203 /* will automatically mute their output when */
204 /* they are not rate-locked to the external */
205 /* async audio source */
206 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
207 /* NOTE: This should generally never be used. */
208 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
209 /* NOTE: This should generally never be used. */
210 #define HCFG_LOCKTANKCACHE 0x01020014
211 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
212 /* NOTE: This is a 'cheap' way to implement a */
213 /* master mute function on the mute button, and */
214 /* in general should not be used unless a more */
215 /* sophisticated master mute function has not */
216 /* been written. */
217 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
218 /* Should be set to 1 when the EMU10K1 is */
219 /* completely initialized. */
220
221 //For Audigy, MPU port move to 0x70-0x74 ptr register
222
223 #define MUDATA 0x18 /* MPU401 data register (8 bits) */
224
225 #define MUCMD 0x19 /* MPU401 command register (8 bits) */
226 #define MUCMD_RESET 0xff /* RESET command */
227 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
228 /* NOTE: All other commands are ignored */
229
230 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
231 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
232 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
233
234 #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
235 #define A_GPINPUT_MASK 0xff00
236 #define A_GPOUTPUT_MASK 0x00ff
237 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital? */
238 #define A_IOCFG_GPOUT1 0x0002 /* IR */
239 #define A_IOCFG_GPOUT2 0x0001 /* IR */
240
241 #define TIMER 0x1a /* Timer terminal count register */
242 /* NOTE: After the rate is changed, a maximum */
243 /* of 1024 sample periods should be allowed */
244 /* before the new rate is guaranteed accurate. */
245 #define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
246 /* 0 == 1024 periods, [1..4] are not useful */
247 #define TIMER_RATE 0x0a00001a
248
249 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
250
251 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
252 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
253 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
254
255 /************************************************************************************************/
256 /* PCI function 1 registers, address = <val> + PCIBASE1 */
257 /************************************************************************************************/
258
259 #define JOYSTICK1 0x00 /* Analog joystick port register */
260 #define JOYSTICK2 0x01 /* Analog joystick port register */
261 #define JOYSTICK3 0x02 /* Analog joystick port register */
262 #define JOYSTICK4 0x03 /* Analog joystick port register */
263 #define JOYSTICK5 0x04 /* Analog joystick port register */
264 #define JOYSTICK6 0x05 /* Analog joystick port register */
265 #define JOYSTICK7 0x06 /* Analog joystick port register */
266 #define JOYSTICK8 0x07 /* Analog joystick port register */
267
268 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
269 /* When reading, use these bitfields: */
270 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
271 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
272
273
274 /********************************************************************************************************/
275 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
276 /********************************************************************************************************/
277
278 #define CPF 0x00 /* Current pitch and fraction register */
279 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
280 #define CPF_CURRENTPITCH 0x10100000
281 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
282 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
283 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
284
285 #define PTRX 0x01 /* Pitch target and send A/B amounts register */
286 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
287 #define PTRX_PITCHTARGET 0x10100001
288 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
289 #define PTRX_FXSENDAMOUNT_A 0x08080001
290 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
291 #define PTRX_FXSENDAMOUNT_B 0x08000001
292
293 #define CVCF 0x02 /* Current volume and filter cutoff register */
294 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
295 #define CVCF_CURRENTVOL 0x10100002
296 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
297 #define CVCF_CURRENTFILTER 0x10000002
298
299 #define VTFT 0x03 /* Volume target and filter cutoff target register */
300 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
301 #define VTFT_VOLUMETARGET 0x10100003
302 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
303 #define VTFT_FILTERTARGET 0x10000003
304
305 #define Z1 0x05 /* Filter delay memory 1 register */
306
307 #define Z2 0x04 /* Filter delay memory 2 register */
308
309 #define PSST 0x06 /* Send C amount and loop start address register */
310 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
311
312 #define PSST_FXSENDAMOUNT_C 0x08180006
313
314 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
315 #define PSST_LOOPSTARTADDR 0x18000006
316
317 #define DSL 0x07 /* Send D amount and loop start address register */
318 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
319
320 #define DSL_FXSENDAMOUNT_D 0x08180007
321
322 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
323 #define DSL_LOOPENDADDR 0x18000007
324
325 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
326 #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
327 #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
328 /* 1 == full band, 7 == lowpass */
329 /* ROM 0 is used when pitch shifting downward or less */
330 /* then 3 semitones upward. Increasingly higher ROM */
331 /* numbers are used, typically in steps of 3 semitones, */
332 /* as upward pitch shifting is performed. */
333 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
334 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
335 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
336 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
337 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
338 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
339 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
340 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
341 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
342 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
343 #define CCCA_CURRADDR 0x18000008
344
345 #define CCR 0x09 /* Cache control register */
346 #define CCR_CACHEINVALIDSIZE 0x07190009
347 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
348 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
349 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
350 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
351 #define CCR_READADDRESS 0x06100009
352 #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
353 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
354 /* NOTE: This is valid only if CACHELOOPFLAG is set */
355 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
356 #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
357
358 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
359 /* NOTE: This register is normally not used */
360 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
361
362 #define FXRT 0x0b /* Effects send routing register */
363 /* NOTE: It is illegal to assign the same routing to */
364 /* two effects sends. */
365 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
366 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
367 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
368 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
369
370 #define MAPA 0x0c /* Cache map A */
371
372 #define MAPB 0x0d /* Cache map B */
373
374 #define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
375 #define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
376
377 #define ENVVOL 0x10 /* Volume envelope register */
378 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
379 /* 0x8000-n == 666*n usec delay */
380
381 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
382 #define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
383 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
384 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
385 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
386
387 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
388 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
389 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
390 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
391 /* this channel and from writing to pitch, filter and */
392 /* volume targets. */
393 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
394 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
395
396 #define LFOVAL1 0x13 /* Modulation LFO value */
397 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
398 /* 0x8000-n == 666*n usec delay */
399
400 #define ENVVAL 0x14 /* Modulation envelope register */
401 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
402 /* 0x8000-n == 666*n usec delay */
403
404 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
405 #define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
406 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
407 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
408 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
409
410 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
411 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
412 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
413 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
414 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
415
416 #define LFOVAL2 0x17 /* Vibrato LFO register */
417 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
418 /* 0x8000-n == 666*n usec delay */
419
420 #define IP 0x18 /* Initial pitch register */
421 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
422 /* 4 bits of octave, 12 bits of fractional octave */
423 #define IP_UNITY 0x0000e000 /* Unity pitch shift */
424
425 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
426 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
427 /* 6 most significant bits are semitones */
428 /* 2 least significant bits are fractions */
429 #define IFATN_FILTERCUTOFF 0x08080019
430 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
431 #define IFATN_ATTENUATION 0x08000019
432
433
434 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
435 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
436 /* Signed 2's complement, +/- one octave peak extremes */
437 #define PEFE_PITCHAMOUNT 0x0808001a
438 #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
439 /* Signed 2's complement, +/- six octaves peak extremes */
440 #define PEFE_FILTERAMOUNT 0x0800001a
441 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
442 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
443 /* Signed 2's complement, +/- one octave extremes */
444 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
445 /* Signed 2's complement, +/- three octave extremes */
446
447
448 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
449 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
450 /* Signed 2's complement, with +/- 12dB extremes */
451
452 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
453 /* ??Hz steps, maximum of ?? Hz. */
454 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
455 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
456 /* Signed 2's complement, +/- one octave extremes */
457 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
458 /* 0.039Hz steps, maximum of 9.85 Hz. */
459
460 #define TEMPENV 0x1e /* Tempory envelope register */
461 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
462 /* NOTE: All channels contain internal variables; do */
463 /* not write to these locations. */
464
465 #define CD0 0x20 /* Cache data 0 register */
466 #define CD1 0x21 /* Cache data 1 register */
467 #define CD2 0x22 /* Cache data 2 register */
468 #define CD3 0x23 /* Cache data 3 register */
469 #define CD4 0x24 /* Cache data 4 register */
470 #define CD5 0x25 /* Cache data 5 register */
471 #define CD6 0x26 /* Cache data 6 register */
472 #define CD7 0x27 /* Cache data 7 register */
473 #define CD8 0x28 /* Cache data 8 register */
474 #define CD9 0x29 /* Cache data 9 register */
475 #define CDA 0x2a /* Cache data A register */
476 #define CDB 0x2b /* Cache data B register */
477 #define CDC 0x2c /* Cache data C register */
478 #define CDD 0x2d /* Cache data D register */
479 #define CDE 0x2e /* Cache data E register */
480 #define CDF 0x2f /* Cache data F register */
481
482 #define PTB 0x40 /* Page table base register */
483 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
484
485 #define TCB 0x41 /* Tank cache base register */
486 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
487
488 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
489 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
490 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
491 /* NOTE: To guarantee phase coherency, both channels */
492 /* must be disabled prior to enabling both channels. */
493 #define A_ADCCR_RCHANENABLE 0x00000020
494 #define A_ADCCR_LCHANENABLE 0x00000010
495
496 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
497 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
498 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
499 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
500 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
501 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
502 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
503 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
504 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
505 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
506 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
507 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
508 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
509
510 #define FXWC 0x43 /* FX output write channels register */
511 /* When set, each bit enables the writing of the */
512 /* corresponding FX output channel into host memory */
513 #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
514 #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
515 #define FXWC_DEFAULTROUTE_A (1<<12)
516 #define FXWC_DEFAULTROUTE_D (1<<13)
517 #define FXWC_ADCLEFT (1<<18)
518 #define FXWC_CDROMSPDIFLEFT (1<<18)
519 #define FXWC_ADCRIGHT (1<<19)
520 #define FXWC_CDROMSPDIFRIGHT (1<<19)
521 #define FXWC_MIC (1<<20)
522 #define FXWC_ZOOMLEFT (1<<20)
523 #define FXWC_ZOOMRIGHT (1<<21)
524 #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
525 #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
526
527 #define TCBS 0x44 /* Tank cache buffer size register */
528 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
529 #define TCBS_BUFFSIZE_16K 0x00000000
530 #define TCBS_BUFFSIZE_32K 0x00000001
531 #define TCBS_BUFFSIZE_64K 0x00000002
532 #define TCBS_BUFFSIZE_128K 0x00000003
533 #define TCBS_BUFFSIZE_256K 0x00000004
534 #define TCBS_BUFFSIZE_512K 0x00000005
535 #define TCBS_BUFFSIZE_1024K 0x00000006
536 #define TCBS_BUFFSIZE_2048K 0x00000007
537
538 #define MICBA 0x45 /* AC97 microphone buffer address register */
539 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
540
541 #define ADCBA 0x46 /* ADC buffer address register */
542 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
543
544 #define FXBA 0x47 /* FX Buffer Address */
545 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
546
547 #define MICBS 0x49 /* Microphone buffer size register */
548
549 #define ADCBS 0x4a /* ADC buffer size register */
550
551 #define FXBS 0x4b /* FX buffer size register */
552
553 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
554 #define ADCBS_BUFSIZE_NONE 0x00000000
555 #define ADCBS_BUFSIZE_384 0x00000001
556 #define ADCBS_BUFSIZE_448 0x00000002
557 #define ADCBS_BUFSIZE_512 0x00000003
558 #define ADCBS_BUFSIZE_640 0x00000004
559 #define ADCBS_BUFSIZE_768 0x00000005
560 #define ADCBS_BUFSIZE_896 0x00000006
561 #define ADCBS_BUFSIZE_1024 0x00000007
562 #define ADCBS_BUFSIZE_1280 0x00000008
563 #define ADCBS_BUFSIZE_1536 0x00000009
564 #define ADCBS_BUFSIZE_1792 0x0000000a
565 #define ADCBS_BUFSIZE_2048 0x0000000b
566 #define ADCBS_BUFSIZE_2560 0x0000000c
567 #define ADCBS_BUFSIZE_3072 0x0000000d
568 #define ADCBS_BUFSIZE_3584 0x0000000e
569 #define ADCBS_BUFSIZE_4096 0x0000000f
570 #define ADCBS_BUFSIZE_5120 0x00000010
571 #define ADCBS_BUFSIZE_6144 0x00000011
572 #define ADCBS_BUFSIZE_7168 0x00000012
573 #define ADCBS_BUFSIZE_8192 0x00000013
574 #define ADCBS_BUFSIZE_10240 0x00000014
575 #define ADCBS_BUFSIZE_12288 0x00000015
576 #define ADCBS_BUFSIZE_14366 0x00000016
577 #define ADCBS_BUFSIZE_16384 0x00000017
578 #define ADCBS_BUFSIZE_20480 0x00000018
579 #define ADCBS_BUFSIZE_24576 0x00000019
580 #define ADCBS_BUFSIZE_28672 0x0000001a
581 #define ADCBS_BUFSIZE_32768 0x0000001b
582 #define ADCBS_BUFSIZE_40960 0x0000001c
583 #define ADCBS_BUFSIZE_49152 0x0000001d
584 #define ADCBS_BUFSIZE_57344 0x0000001e
585 #define ADCBS_BUFSIZE_65536 0x0000001f
586
587
588 #define CDCS 0x50 /* CD-ROM digital channel status register */
589
590 #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
591
592 #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
593
594 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
595
596 #define A_DBG 0x53
597 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
598 #define A_DBG_ZC 0x40000000 /* zero tram counter */
599 #define A_DBG_STEP_ADDR 0x000003ff
600 #define A_DBG_SATURATION_OCCURED 0x20000000
601 #define A_DBG_SATURATION_ADDR 0x0ffc0000
602
603 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
604
605 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
606
607 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
608
609 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
610 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
611 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
612 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
613 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
614 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
615 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
616 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
617 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
618 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
619 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
620 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
621 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
622 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
623 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
624 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
625 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
626 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
627 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
628 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
629 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
630 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
631 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
632
633 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
634 #define CLIEL 0x58 /* Channel loop interrupt enable low register */
635
636 #define CLIEH 0x59 /* Channel loop interrupt enable high register */
637
638 #define CLIPL 0x5a /* Channel loop interrupt pending low register */
639
640 #define CLIPH 0x5b /* Channel loop interrupt pending high register */
641
642 #define SOLEL 0x5c /* Stop on loop enable low register */
643
644 #define SOLEH 0x5d /* Stop on loop enable high register */
645
646 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
647 #define SPBYPASS_ENABLE 0x00000001 /* Enable SPDIF bypass mode */
648
649 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
650 #define AC97SLOT_CNTR 0x10 /* Center enable */
651 #define AC97SLOT_LFE 0x20 /* LFE enable */
652
653 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
654
655 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
656
657 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
658 /* NOTE: This one has no SPDIFLOCKED field */
659 /* Assumes sample lock */
660
661 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
662 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
663 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
664 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
665
666 /* Note that these values can vary +/- by a small amount */
667 #define SRCS_SPDIFRATE_44 0x0003acd9
668 #define SRCS_SPDIFRATE_48 0x00040000
669 #define SRCS_SPDIFRATE_96 0x00080000
670
671 #define MICIDX 0x63 /* Microphone recording buffer index register */
672 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
673 #define MICIDX_IDX 0x10000063
674
675 #define ADCIDX 0x64 /* ADC recording buffer index register */
676 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
677 #define ADCIDX_IDX 0x10000064
678
679 #define A_ADCIDX 0x63
680 #define A_ADCIDX_IDX 0x10000063
681
682 #define FXIDX 0x65 /* FX recording buffer index register */
683 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
684 #define FXIDX_IDX 0x10000065
685
686 /* This is the MPU port on the card (via the game port) */
687 #define A_MUDATA1 0x70
688 #define A_MUCMD1 0x71
689 #define A_MUSTAT1 A_MUCMD1
690
691 /* This is the MPU port on the Audigy Drive */
692 #define A_MUDATA2 0x72
693 #define A_MUCMD2 0x73
694 #define A_MUSTAT2 A_MUCMD2
695
696 /* The next two are the Audigy equivalent of FXWC */
697 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
698 /* Each bit selects a channel for recording */
699 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
700 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
701
702 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
703 #define A_SPDIF_48000 0x00000080
704 #define A_SPDIF_44100 0x00000000
705 #define A_SPDIF_96000 0x00000040
706
707 #define A_FXRT2 0x7c
708 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
709 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
710 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
711 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
712
713 #define A_SENDAMOUNTS 0x7d
714 #define A_FXSENDAMOUNT_E_MASK 0xFF000000
715 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000
716 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00
717 #define A_FXSENDAMOUNT_H_MASK 0x000000FF
718
719 /* The send amounts for this one are the same as used with the emu10k1 */
720 #define A_FXRT1 0x7e
721 #define A_FXRT_CHANNELA 0x0000003f
722 #define A_FXRT_CHANNELB 0x00003f00
723 #define A_FXRT_CHANNELC 0x003f0000
724 #define A_FXRT_CHANNELD 0x3f000000
725
726
727 /* Each FX general purpose register is 32 bits in length, all bits are used */
728 #define FXGPREGBASE 0x100 /* FX general purpose registers base */
729 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
730
731 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
732 /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
733 /* locations are for external TRAM. */
734 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
735 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
736
737 /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
738 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
739 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
740 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
741 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
742 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
743 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
744
745 #define MICROCODEBASE 0x400 /* Microcode data base address */
746
747 /* Each DSP microcode instruction is mapped into 2 doublewords */
748 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
749 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
750 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
751 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
752 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
753 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
754
755
756 /* Audigy Soundcard have a different instruction format */
757 #define A_MICROCODEBASE 0x600
758 #define A_LOWORD_OPY_MASK 0x000007ff
759 #define A_LOWORD_OPX_MASK 0x007ff000
760 #define A_HIWORD_OPCODE_MASK 0x0f000000
761 #define A_HIWORD_RESULT_MASK 0x007ff000
762 #define A_HIWORD_OPA_MASK 0x000007ff
763
764
765 /* ------------------- STRUCTURES -------------------- */
766
767 typedef struct _snd_emu10k1 emu10k1_t;
768 typedef struct _snd_emu10k1_voice emu10k1_voice_t;
769 typedef struct _snd_emu10k1_pcm emu10k1_pcm_t;
770
771 typedef enum {
772 EMU10K1_PCM,
773 EMU10K1_SYNTH,
774 EMU10K1_MIDI
775 } emu10k1_voice_type_t;
776
777 struct _snd_emu10k1_voice {
778 emu10k1_t *emu;
779 int number;
780 int use: 1,
781 pcm: 1,
782 synth: 1,
783 midi: 1;
784 void (*interrupt)(emu10k1_t *emu, emu10k1_voice_t *pvoice);
785
786 emu10k1_pcm_t *epcm;
787 };
788
789 typedef enum {
790 PLAYBACK_EMUVOICE,
791 CAPTURE_AC97ADC,
792 CAPTURE_AC97MIC,
793 CAPTURE_EFX
794 } snd_emu10k1_pcm_type_t;
795
796 struct _snd_emu10k1_pcm {
797 emu10k1_t *emu;
798 snd_emu10k1_pcm_type_t type;
799 snd_pcm_substream_t *substream;
800 emu10k1_voice_t *voices[2];
801 emu10k1_voice_t *extra;
802 unsigned short running;
803 unsigned short first_ptr;
804 snd_util_memblk_t *memblk;
805 unsigned int start_addr;
806 unsigned int ccca_start_addr;
807 unsigned int capture_ipr; /* interrupt acknowledge mask */
808 unsigned int capture_inte; /* interrupt enable mask */
809 unsigned int capture_ba_reg; /* buffer address register */
810 unsigned int capture_bs_reg; /* buffer size register */
811 unsigned int capture_idx_reg; /* buffer index register */
812 unsigned int capture_cr_val; /* control value */
813 unsigned int capture_cr_val2; /* control value2 (for audigy) */
814 unsigned int capture_bs_val; /* buffer size value */
815 unsigned int capture_bufsize; /* buffer size in bytes */
816 };
817
818 typedef struct {
819 unsigned char send_routing[3][8];
820 unsigned char send_volume[3][8];
821 unsigned short attn[3];
822 emu10k1_pcm_t *epcm;
823 } emu10k1_pcm_mixer_t;
824
825 #define snd_emu10k1_compose_send_routing(route) \
826 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
827
828 #define snd_emu10k1_compose_audigy_fxrt1(route) \
829 (((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 12)) << 24)
830
831 #define snd_emu10k1_compose_audigy_fxrt2(route) \
832 (((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 12)) << 24)
833
834 typedef struct snd_emu10k1_memblk {
835 snd_util_memblk_t mem;
836 /* private part */
837 short first_page, last_page, pages, mapped_page;
838 unsigned int map_locked;
839 struct list_head mapped_link;
840 struct list_head mapped_order_link;
841 } emu10k1_memblk_t;
842
843 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
844
845 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
846
847 typedef struct {
848 struct list_head list; /* list link container */
849 unsigned int vcount;
850 unsigned int count; /* count of GPR (1..16) */
851 unsigned char gpr[32]; /* GPR number(s) */
852 unsigned int value[32];
853 unsigned int min; /* minimum range */
854 unsigned int max; /* maximum range */
855 unsigned int translation; /* translation type (EMU10K1_GRP_TRANSLATION*) */
856 snd_kcontrol_t *kcontrol;
857 } snd_emu10k1_fx8010_ctl_t;
858
859 typedef void (snd_fx8010_irq_handler_t)(emu10k1_t *emu, void *private_data);
860
861 typedef struct _snd_emu10k1_fx8010_irq {
862 struct _snd_emu10k1_fx8010_irq *next;
863 snd_fx8010_irq_handler_t *handler;
864 unsigned char gpr_running;
865 void *private_data;
866 } snd_emu10k1_fx8010_irq_t;
867
868 typedef struct {
869 unsigned int valid: 1,
870 opened: 1,
871 active: 1;
872 unsigned int channels; /* 16-bit channels count */
873 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
874 unsigned int buffer_size; /* count of buffered samples */
875 unsigned char gpr_size; /* GPR containing size of ring buffer in samples (host) */
876 unsigned char gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
877 unsigned char gpr_count; /* GPR containing count of samples between two interrupts (host) */
878 unsigned char gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
879 unsigned char gpr_trigger; /* GPR containing trigger (activate) information (host) */
880 unsigned char gpr_running; /* GPR containing info if PCM is running (FX8010) */
881 unsigned char etram[32]; /* external TRAM address & data */
882 unsigned int sw_data, hw_data;
883 unsigned int sw_io, hw_io;
884 unsigned int sw_ready, hw_ready;
885 unsigned int appl_ptr;
886 unsigned int tram_pos;
887 unsigned int tram_shift;
888 snd_emu10k1_fx8010_irq_t *irq;
889 } snd_emu10k1_fx8010_pcm_t;
890
891 typedef struct {
892 unsigned short fxbus_mask; /* used FX buses (bitmask) */
893 unsigned short extin_mask; /* used external inputs (bitmask) */
894 unsigned short extout_mask; /* used external outputs (bitmask) */
895 unsigned short pad1;
896 unsigned int itram_size; /* internal TRAM size in samples */
897 unsigned int etram_size; /* external TRAM size in samples */
898 void *etram_pages; /* allocated pages for external TRAM */
899 dma_addr_t etram_pages_dmaaddr;
900 unsigned int dbg; /* FX debugger register */
901 unsigned char name[128];
902 int gpr_size; /* size of allocated GPR controls */
903 int gpr_count; /* count of used kcontrols */
904 struct list_head gpr_ctl; /* GPR controls */
905 struct semaphore lock;
906 snd_emu10k1_fx8010_pcm_t pcm[8];
907 spinlock_t irq_lock;
908 snd_emu10k1_fx8010_irq_t *irq_handlers;
909 } snd_emu10k1_fx8010_t;
910
911 #define emu10k1_gpr_ctl(n) list_entry(n, snd_emu10k1_fx8010_ctl_t, list)
912
913 typedef struct {
914 struct _snd_emu10k1 *emu;
915 snd_rawmidi_t *rmidi;
916 snd_rawmidi_substream_t *substream_input;
917 snd_rawmidi_substream_t *substream_output;
918 unsigned int midi_mode;
919 spinlock_t input_lock;
920 spinlock_t output_lock;
921 spinlock_t open_lock;
922 int tx_enable, rx_enable;
923 int port;
924 int ipr_tx, ipr_rx;
925 void (*interrupt)(emu10k1_t *emu, unsigned int status);
926 } emu10k1_midi_t;
927
928 struct _snd_emu10k1 {
929 int irq;
930
931 unsigned long port; /* I/O port number */
932 struct resource *res_port;
933 int APS: 1, /* APS flag */
934 tos_link: 1; /* tos link detected */
935 unsigned int audigy; /* is Audigy? */
936 unsigned int revision; /* chip revision */
937 unsigned int serial; /* serial number */
938 unsigned short model; /* subsystem id */
939 unsigned int card_type; /* EMU10K1_CARD_* */
940 unsigned int ecard_ctrl; /* ecard control bits */
941 unsigned long dma_mask; /* PCI DMA mask */
942 int max_cache_pages; /* max memory size / PAGE_SIZE */
943 void *silent_page; /* silent page */
944 dma_addr_t silent_page_dmaaddr;
945 volatile u32 *ptb_pages; /* page table pages */
946 dma_addr_t ptb_pages_dmaaddr;
947 snd_util_memhdr_t *memhdr; /* page allocation list */
948 emu10k1_memblk_t *reserved_page; /* reserved page */
949
950 struct list_head mapped_link_head;
951 struct list_head mapped_order_link_head;
952 void **page_ptr_table;
953 unsigned long *page_addr_table;
954 spinlock_t memblk_lock;
955
956 unsigned int spdif_bits[3]; /* s/pdif out setup */
957
958 snd_emu10k1_fx8010_t fx8010; /* FX8010 info */
959 int gpr_base;
960
961 ac97_t *ac97;
962
963 struct pci_dev *pci;
964 snd_card_t *card;
965 snd_pcm_t *pcm;
966 snd_pcm_t *pcm_mic;
967 snd_pcm_t *pcm_efx;
968 snd_pcm_t *pcm_fx8010;
969
970 spinlock_t synth_lock;
971 void *synth;
972 int (*get_synth_voice)(emu10k1_t *emu);
973
974 spinlock_t reg_lock;
975 spinlock_t emu_lock;
976 spinlock_t voice_lock;
977 struct semaphore ptb_lock;
978
979 emu10k1_voice_t voices[64];
980 emu10k1_pcm_mixer_t pcm_mixer[32];
981 snd_kcontrol_t *ctl_send_routing;
982 snd_kcontrol_t *ctl_send_volume;
983 snd_kcontrol_t *ctl_attn;
984
985 void (*hwvol_interrupt)(emu10k1_t *emu, unsigned int status);
986 void (*capture_interrupt)(emu10k1_t *emu, unsigned int status);
987 void (*capture_mic_interrupt)(emu10k1_t *emu, unsigned int status);
988 void (*capture_efx_interrupt)(emu10k1_t *emu, unsigned int status);
989 void (*timer_interrupt)(emu10k1_t *emu);
990 void (*spdif_interrupt)(emu10k1_t *emu, unsigned int status);
991 void (*dsp_interrupt)(emu10k1_t *emu);
992
993 snd_pcm_substream_t *pcm_capture_substream;
994 snd_pcm_substream_t *pcm_capture_mic_substream;
995 snd_pcm_substream_t *pcm_capture_efx_substream;
996
997 emu10k1_midi_t midi;
998 emu10k1_midi_t midi2; /* for audigy */
999
1000 unsigned int efx_voices_mask[2];
1001 };
1002
1003 int snd_emu10k1_create(snd_card_t * card,
1004 struct pci_dev *pci,
1005 unsigned short extin_mask,
1006 unsigned short extout_mask,
1007 long max_cache_bytes,
1008 int enable_ir,
1009 emu10k1_t ** remu);
1010
1011 int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1012 int snd_emu10k1_pcm_mic(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1013 int snd_emu10k1_pcm_efx(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1014 int snd_emu10k1_fx8010_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1015 int snd_emu10k1_mixer(emu10k1_t * emu);
1016 int snd_emu10k1_fx8010_new(emu10k1_t *emu, int device, snd_hwdep_t ** rhwdep);
1017
1018 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id, struct pt_regs *regs);
1019
1020 /* initialization */
1021 void snd_emu10k1_voice_init(emu10k1_t * emu, int voice);
1022 int snd_emu10k1_init_efx(emu10k1_t *emu);
1023 void snd_emu10k1_free_efx(emu10k1_t *emu);
1024 int snd_emu10k1_fx8010_tram_setup(emu10k1_t *emu, u32 size);
1025
1026 /* I/O functions */
1027 unsigned int snd_emu10k1_ptr_read(emu10k1_t * emu, unsigned int reg, unsigned int chn);
1028 void snd_emu10k1_ptr_write(emu10k1_t *emu, unsigned int reg, unsigned int chn, unsigned int data);
1029 void snd_emu10k1_efx_write(emu10k1_t *emu, unsigned int pc, unsigned int data);
1030 unsigned int snd_emu10k1_efx_read(emu10k1_t *emu, unsigned int pc);
1031 void snd_emu10k1_intr_enable(emu10k1_t *emu, unsigned int intrenb);
1032 void snd_emu10k1_intr_disable(emu10k1_t *emu, unsigned int intrenb);
1033 void snd_emu10k1_voice_intr_enable(emu10k1_t *emu, unsigned int voicenum);
1034 void snd_emu10k1_voice_intr_disable(emu10k1_t *emu, unsigned int voicenum);
1035 void snd_emu10k1_voice_intr_ack(emu10k1_t *emu, unsigned int voicenum);
1036 void snd_emu10k1_voice_set_loop_stop(emu10k1_t *emu, unsigned int voicenum);
1037 void snd_emu10k1_voice_clear_loop_stop(emu10k1_t *emu, unsigned int voicenum);
1038 void snd_emu10k1_wait(emu10k1_t *emu, unsigned int wait);
1039 static inline unsigned int snd_emu10k1_wc(emu10k1_t *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1040 unsigned short snd_emu10k1_ac97_read(ac97_t *ac97, unsigned short reg);
1041 void snd_emu10k1_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short data);
1042 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1043 unsigned char snd_emu10k1_sum_vol_attn(unsigned int value);
1044
1045 /* memory allocation */
1046 snd_util_memblk_t *snd_emu10k1_alloc_pages(emu10k1_t *emu, snd_pcm_substream_t *substream);
1047 int snd_emu10k1_free_pages(emu10k1_t *emu, snd_util_memblk_t *blk);
1048 snd_util_memblk_t *snd_emu10k1_synth_alloc(emu10k1_t *emu, unsigned int size);
1049 int snd_emu10k1_synth_free(emu10k1_t *emu, snd_util_memblk_t *blk);
1050 int snd_emu10k1_synth_bzero(emu10k1_t *emu, snd_util_memblk_t *blk, int offset, int size);
1051 int snd_emu10k1_synth_copy_from_user(emu10k1_t *emu, snd_util_memblk_t *blk, int offset, const char *data, int size);
1052 int snd_emu10k1_memblk_map(emu10k1_t *emu, emu10k1_memblk_t *blk);
1053
1054 /* voice allocation */
1055 int snd_emu10k1_voice_alloc(emu10k1_t *emu, emu10k1_voice_type_t type, int pair, emu10k1_voice_t **rvoice);
1056 int snd_emu10k1_voice_free(emu10k1_t *emu, emu10k1_voice_t *pvoice);
1057
1058 /* MIDI uart */
1059 int snd_emu10k1_midi(emu10k1_t * emu);
1060 int snd_emu10k1_audigy_midi(emu10k1_t * emu);
1061
1062 /* proc interface */
1063 int snd_emu10k1_proc_init(emu10k1_t * emu);
1064
1065 #endif /* __KERNEL__ */
1066
1067 /*
1068 * ---- FX8010 ----
1069 */
1070
1071 #define EMU10K1_CARD_CREATIVE 0x00000000
1072 #define EMU10K1_CARD_EMUAPS 0x00000001
1073
1074 #define EMU10K1_FX8010_PCM_COUNT 8
1075
1076 /* instruction set */
1077 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
1078 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
1079 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
1080 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
1081 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
1082 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
1083 #define iACC3 0x06 /* R = A + X + Y ; saturation */
1084 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
1085 #define iANDXOR 0x08 /* R = (A & X) ^ Y */
1086 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
1087 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
1088 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
1089 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
1090 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
1091 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
1092 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
1093
1094 /* GPRs */
1095 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
1096 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
1097 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f */
1098 #define C_00000000 0x40
1099 #define C_00000001 0x41
1100 #define C_00000002 0x42
1101 #define C_00000003 0x43
1102 #define C_00000004 0x44
1103 #define C_00000008 0x45
1104 #define C_00000010 0x46
1105 #define C_00000020 0x47
1106 #define C_00000100 0x48
1107 #define C_00010000 0x49
1108 #define C_00080000 0x4a
1109 #define C_10000000 0x4b
1110 #define C_20000000 0x4c
1111 #define C_40000000 0x4d
1112 #define C_80000000 0x4e
1113 #define C_7fffffff 0x4f
1114 #define C_ffffffff 0x50
1115 #define C_fffffffe 0x51
1116 #define C_c0000000 0x52
1117 #define C_4f1bbcdc 0x53
1118 #define C_5a7ef9db 0x54
1119 #define C_00100000 0x55 /* ?? */
1120 #define GPR_ACCU 0x56 /* ACCUM, accumulator */
1121 #define GPR_COND 0x57 /* CCR, condition register */
1122 #define GPR_NOISE0 0x58 /* noise source */
1123 #define GPR_NOISE1 0x59 /* noise source */
1124 #define GPR_IRQ 0x5a /* IRQ register */
1125 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
1126 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
1127 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1128 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1129 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1130 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1131
1132 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f? */
1133 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x1f? */
1134 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f? */
1135 #define A_GPR(x) (A_FXGPREGBASE + (x))
1136
1137 /* cc_reg constants */
1138 #define CC_REG_NORMALIZED C_00000001
1139 #define CC_REG_BORROW C_00000002
1140 #define CC_REG_MINUS C_00000004
1141 #define CC_REG_ZERO C_00000008
1142 #define CC_REG_SATURATE C_00000010
1143 #define CC_REG_NONZERO C_00000100
1144
1145 /* FX buses */
1146 #define FXBUS_PCM_LEFT 0x00
1147 #define FXBUS_PCM_RIGHT 0x01
1148 #define FXBUS_PCM_LEFT_REAR 0x02
1149 #define FXBUS_PCM_RIGHT_REAR 0x03
1150 #define FXBUS_MIDI_LEFT 0x04
1151 #define FXBUS_MIDI_RIGHT 0x05
1152 #define FXBUS_PCM_CENTER 0x06
1153 #define FXBUS_PCM_LFE 0x07
1154 #define FXBUS_MIDI_REVERB 0x0c
1155 #define FXBUS_MIDI_CHORUS 0x0d
1156
1157 /* Inputs */
1158 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
1159 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
1160 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
1161 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
1162 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
1163 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
1164 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
1165 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
1166 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
1167 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
1168 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
1169 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
1170 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
1171 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
1172
1173 /* Outputs */
1174 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
1175 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
1176 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
1177 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
1178 #define EXTOUT_CENTER 0x04 /* SB Live 5.1 - center */
1179 #define EXTOUT_LFE 0x05 /* SB Live 5.1 - LFE */
1180 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
1181 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
1182 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
1183 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
1184 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
1185 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
1186 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
1187 #define EXTOUT_ACENTER 0x11 /* Analog Center */
1188 #define EXTOUT_ALFE 0x12 /* Analog LFE */
1189
1190 /* Audigy Inputs */
1191 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
1192 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
1193 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
1194 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
1195 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
1196 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
1197 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
1198 #define A_EXTIN_LINE2_R 0x09 /* right */
1199 #define A_EXTIN_RCA_SPDIF_L 0x0a /* audigy drive RCA SPDIF - left */
1200 #define A_EXTIN_RCA_SPDIF_R 0x0b /* right */
1201 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
1202 #define A_EXTIN_AUX2_R 0x0d /* - right */
1203
1204 /* Audigiy Outputs */
1205 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
1206 #define A_EXTOUT_FRONT_R 0x01 /* right */
1207 #define A_EXTOUT_CENTER 0x02 /* digital front center */
1208 #define A_EXTOUT_LFE 0x03 /* digital front lfe */
1209 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
1210 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
1211 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
1212 #define A_EXTOUT_REAR_R 0x07 /* right */
1213 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
1214 #define A_EXTOUT_AFRONT_R 0x09 /* right */
1215 #define A_EXTOUT_ACENTER 0x0a /* analog center */
1216 #define A_EXTOUT_ALFE 0x0b /* analog LFE */
1217 /* 0x0c ?? */
1218 /* 0x0d ?? */
1219 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
1220 #define A_EXTOUT_AREAR_R 0x0f /* right */
1221 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
1222 #define A_EXTOUT_AC97_R 0x11 /* right */
1223 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
1224 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
1225
1226 /* Audigy constants */
1227 #define A_C_00000000 0xc0
1228 #define A_C_00000001 0xc1
1229 #define A_C_00000002 0xc2
1230 #define A_C_00000003 0xc3
1231 #define A_C_00000004 0xc4
1232 #define A_C_00000008 0xc5
1233 #define A_C_00000010 0xc6
1234 #define A_C_00000020 0xc7
1235 #define A_C_00000100 0xc8
1236 #define A_C_00010000 0xc9
1237 #define A_C_00000800 0xca
1238 #define A_C_10000000 0xcb
1239 #define A_C_20000000 0xcc
1240 #define A_C_40000000 0xcd
1241 #define A_C_80000000 0xce
1242 #define A_C_7fffffff 0xcf
1243 #define A_C_ffffffff 0xd0
1244 #define A_C_fffffffe 0xd1
1245 #define A_C_c0000000 0xd2
1246 #define A_C_4f1bbcdc 0xd3
1247 #define A_C_5a7ef9db 0xd4
1248 #define A_C_00100000 0xd5
1249 /* 0xd6 = 0x7fffffff (?) ACCUM? */
1250 /* 0xd7 = 0x0000000 CCR */
1251 /* 0xd8 = noise1 */
1252 /* 0xd9 = noise2 */
1253
1254 /* definitions for debug register */
1255 #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
1256 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
1257 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
1258 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
1259 #define EMU10K1_DBG_STEP 0x00004000 /* start single step */
1260 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
1261 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
1262
1263 /* tank memory address line */
1264 #ifndef __KERNEL__
1265 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
1266 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
1267 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
1268 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
1269 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
1270 #endif
1271
1272 typedef struct {
1273 unsigned int card; /* card type */
1274 unsigned int internal_tram_size; /* in samples */
1275 unsigned int external_tram_size; /* in samples */
1276 char fxbus_names[16][32]; /* names of FXBUSes */
1277 char extin_names[16][32]; /* names of external inputs */
1278 char extout_names[32][32]; /* names of external outputs */
1279 unsigned int gpr_controls; /* count of GPR controls */
1280 } emu10k1_fx8010_info_t;
1281
1282 #define EMU10K1_GPR_TRANSLATION_NONE 0
1283 #define EMU10K1_GPR_TRANSLATION_TABLE100 1
1284 #define EMU10K1_GRP_TRANSLATION_BASS 2
1285 #define EMU10K1_GRP_TRANSLATION_TREBLE 3
1286 #define EMU10K1_GPR_TRANSLATION_ONOFF 4
1287
1288 typedef struct {
1289 snd_ctl_elem_id_t id; /* full control ID definition */
1290 unsigned int vcount; /* visible count */
1291 unsigned int count; /* count of GPR (1..16) */
1292 unsigned char gpr[32]; /* GPR number(s) */
1293 unsigned int value[32]; /* initial values */
1294 unsigned int min; /* minimum range */
1295 unsigned int max; /* maximum range */
1296 unsigned int translation; /* translation type (EMU10K1_GRP_TRANSLATION*) */
1297 } emu10k1_fx8010_control_gpr_t;
1298
1299 typedef struct {
1300 char name[128];
1301
1302 unsigned long gpr_valid[0x100/(sizeof(unsigned long)*8)]; /* bitmask of valid initializers */
1303 unsigned int gpr_map[0x100]; /* initializers */
1304
1305 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
1306 emu10k1_fx8010_control_gpr_t *gpr_add_controls; /* GPR controls to add/replace */
1307
1308 unsigned int gpr_del_control_count; /* count of GPR controls to remove */
1309 snd_ctl_elem_id_t *gpr_del_controls; /* IDs of GPR controls to remove */
1310
1311 unsigned int gpr_list_control_count; /* count of GPR controls to list */
1312 unsigned int gpr_list_control_total; /* total count of GPR controls */
1313 emu10k1_fx8010_control_gpr_t *gpr_list_controls; /* listed GPR controls */
1314
1315 unsigned long tram_valid[0xa0/(sizeof(unsigned long)*8)]; /* bitmask of valid initializers */
1316 unsigned int tram_data_map[0xa0]; /* data initializers */
1317 unsigned int tram_addr_map[0xa0]; /* map initializers */
1318
1319 unsigned long code_valid[512/(sizeof(unsigned long)*8)]; /* bitmask of valid instructions */
1320 unsigned int code[512][2]; /* one instruction - 64 bits */
1321 } emu10k1_fx8010_code_t;
1322
1323 typedef struct {
1324 unsigned int address; /* 31.bit == 1 -> external TRAM */
1325 unsigned int size; /* size in samples (4 bytes) */
1326 unsigned int *samples; /* pointer to samples (20-bit) */
1327 /* NULL->clear memory */
1328 } emu10k1_fx8010_tram_t;
1329
1330 typedef struct {
1331 unsigned int substream; /* substream number */
1332 unsigned int res1; /* reserved */
1333 unsigned int channels; /* 16-bit channels count, zero = remove this substream */
1334 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
1335 unsigned int buffer_size; /* count of buffered samples */
1336 unsigned char gpr_size; /* GPR containing size of ringbuffer in samples (host) */
1337 unsigned char gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1338 unsigned char gpr_count; /* GPR containing count of samples between two interrupts (host) */
1339 unsigned char gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1340 unsigned char gpr_trigger; /* GPR containing trigger (activate) information (host) */
1341 unsigned char gpr_running; /* GPR containing info if PCM is running (FX8010) */
1342 unsigned char pad; /* reserved */
1343 unsigned char etram[32]; /* external TRAM address & data (one per channel) */
1344 unsigned int res2; /* reserved */
1345 } emu10k1_fx8010_pcm_t;
1346
1347 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, emu10k1_fx8010_info_t)
1348 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, emu10k1_fx8010_code_t)
1349 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOW ('H', 0x12, emu10k1_fx8010_code_t)
1350 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
1351 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, emu10k1_fx8010_tram_t)
1352 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOR ('H', 0x22, emu10k1_fx8010_tram_t)
1353 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, emu10k1_fx8010_pcm_t)
1354 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, emu10k1_fx8010_pcm_t)
1355 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
1356 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
1357 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
1358 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
1359 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
1360
1361 #endif /* __SOUND_EMU10K1_H */
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