include/asm-ia64/pal.h

   1 #ifndef _ASM_IA64_PAL_H
   2 #define _ASM_IA64_PAL_H
   3
   4 /*
   5  * Processor Abstraction Layer definitions.
   6  *
   7  * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
   8  * chapter 11 IA-64 Processor Abstraction Layer
   9  *
  10  * Copyright (C) 1998-2001 Hewlett-Packard Co
  11  *      David Mosberger-Tang <davidm@hpl.hp.com>
  12  *      Stephane Eranian <eranian@hpl.hp.com>
  13  * Copyright (C) 1999 VA Linux Systems
  14  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  15  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
  16  *
  17  * 99/10/01     davidm  Make sure we pass zero for reserved parameters.
  18  * 00/03/07     davidm  Updated pal_cache_flush() to be in sync with PAL v2.6.
  19  * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
  20  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
  21  * 00/05/25     eranian Support for stack calls, and static physical calls
  22  * 00/06/18     eranian Support for stacked physical calls
  23  */
  24
  25 /*
  26  * Note that some of these calls use a static-register only calling
  27  * convention which has nothing to do with the regular calling
  28  * convention.
  29  */
  30 #define PAL_CACHE_FLUSH         1       /* flush i/d cache */
  31 #define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
  32 #define PAL_CACHE_INIT          3       /* initialize i/d cache */
  33 #define PAL_CACHE_SUMMARY       4       /* get summary of cache heirarchy */
  34 #define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
  35 #define PAL_PTCE_INFO           6       /* purge TLB info */
  36 #define PAL_VM_INFO             7       /* return supported virtual memory features */
  37 #define PAL_VM_SUMMARY          8       /* return summary on supported vm features */
  38 #define PAL_BUS_GET_FEATURES    9       /* return processor bus interface features settings */
  39 #define PAL_BUS_SET_FEATURES    10      /* set processor bus features */
  40 #define PAL_DEBUG_INFO          11      /* get number of debug registers */
  41 #define PAL_FIXED_ADDR          12      /* get fixed component of processors's directed address */
  42 #define PAL_FREQ_BASE           13      /* base frequency of the platform */
  43 #define PAL_FREQ_RATIOS         14      /* ratio of processor, bus and ITC frequency */
  44 #define PAL_PERF_MON_INFO       15      /* return performance monitor info */
  45 #define PAL_PLATFORM_ADDR       16      /* set processor interrupt block and IO port space addr */
  46 #define PAL_PROC_GET_FEATURES   17      /* get configurable processor features & settings */
  47 #define PAL_PROC_SET_FEATURES   18      /* enable/disable configurable processor features */
  48 #define PAL_RSE_INFO            19      /* return rse information */
  49 #define PAL_VERSION             20      /* return version of PAL code */
  50 #define PAL_MC_CLEAR_LOG        21      /* clear all processor log info */
  51 #define PAL_MC_DRAIN            22      /* drain operations which could result in an MCA */
  52 #define PAL_MC_EXPECTED         23      /* set/reset expected MCA indicator */
  53 #define PAL_MC_DYNAMIC_STATE    24      /* get processor dynamic state */
  54 #define PAL_MC_ERROR_INFO       25      /* get processor MCA info and static state */
  55 #define PAL_MC_RESUME           26      /* Return to interrupted process */
  56 #define PAL_MC_REGISTER_MEM     27      /* Register memory for PAL to use during MCAs and inits */
  57 #define PAL_HALT                28      /* enter the low power HALT state */
  58 #define PAL_HALT_LIGHT          29      /* enter the low power light halt state*/
  59 #define PAL_COPY_INFO           30      /* returns info needed to relocate PAL */
  60 #define PAL_CACHE_LINE_INIT     31      /* init tags & data of cache line */
  61 #define PAL_PMI_ENTRYPOINT      32      /* register PMI memory entry points with the processor */
  62 #define PAL_ENTER_IA_32_ENV     33      /* enter IA-32 system environment */
  63 #define PAL_VM_PAGE_SIZE        34      /* return vm TC and page walker page sizes */
  64
  65 #define PAL_MEM_FOR_TEST        37      /* get amount of memory needed for late processor test */
  66 #define PAL_CACHE_PROT_INFO     38      /* get i/d cache protection info */
  67 #define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
  68 #define PAL_SHUTDOWN            40      /* enter processor shutdown state */
  69 #define PAL_PREFETCH_VISIBILITY 41
  70
  71 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
  72 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
  73 #define PAL_TEST_PROC           258     /* perform late processor self-test */
  74 #define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
  75 #define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
  76 #define PAL_VM_TR_READ          261     /* read contents of translation register */
  77
  78 #ifndef __ASSEMBLY__
  79
  80 #include <linux/types.h>
  81 #include <asm/fpu.h>
  82
  83 /*
  84  * Data types needed to pass information into PAL procedures and
  85  * interpret information returned by them.
  86  */
  87
  88 /* Return status from the PAL procedure */
  89 typedef s64                             pal_status_t;
  90
  91 #define PAL_STATUS_SUCCESS              0       /* No error */
  92 #define PAL_STATUS_UNIMPLEMENTED        (-1)    /* Unimplemented procedure */
  93 #define PAL_STATUS_EINVAL               (-2)    /* Invalid argument */
  94 #define PAL_STATUS_ERROR                (-3)    /* Error */
  95 #define PAL_STATUS_CACHE_INIT_FAIL      (-4)    /* Could not initialize the
  96                                                  * specified level and type of
  97                                                  * cache without sideeffects
  98                                                  * and "restrict" was 1
  99                                                  */
 100
 101 /* Processor cache level in the heirarchy */
 102 typedef u64                             pal_cache_level_t;
 103 #define PAL_CACHE_LEVEL_L0              0       /* L0 */
 104 #define PAL_CACHE_LEVEL_L1              1       /* L1 */
 105 #define PAL_CACHE_LEVEL_L2              2       /* L2 */
 106
 107
 108 /* Processor cache type at a particular level in the heirarchy */
 109
 110 typedef u64                             pal_cache_type_t;
 111 #define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
 112 #define PAL_CACHE_TYPE_DATA             2       /* Data or unified cache */
 113 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3       /* Both Data & Instruction */
 114
 115
 116 #define PAL_CACHE_FLUSH_INVALIDATE      1       /* Invalidate clean lines */
 117 #define PAL_CACHE_FLUSH_CHK_INTRS       2       /* check for interrupts/mc while flushing */
 118
 119 /* Processor cache line size in bytes  */
 120 typedef int                             pal_cache_line_size_t;
 121
 122 /* Processor cache line state */
 123 typedef u64                             pal_cache_line_state_t;
 124 #define PAL_CACHE_LINE_STATE_INVALID    0       /* Invalid */
 125 #define PAL_CACHE_LINE_STATE_SHARED     1       /* Shared */
 126 #define PAL_CACHE_LINE_STATE_EXCLUSIVE  2       /* Exclusive */
 127 #define PAL_CACHE_LINE_STATE_MODIFIED   3       /* Modified */
 128
 129 typedef struct pal_freq_ratio {
 130         u64 den : 32, num : 32; /* numerator & denominator */
 131 } itc_ratio, proc_ratio;
 132
 133 typedef union  pal_cache_config_info_1_s {
 134         struct {
 135                 u64             u               : 1,    /* 0 Unified cache ? */
 136                                 at              : 2,    /* 2-1 Cache mem attr*/
 137                                 reserved        : 5,    /* 7-3 Reserved */
 138                                 associativity   : 8,    /* 16-8 Associativity*/
 139                                 line_size       : 8,    /* 23-17 Line size */
 140                                 stride          : 8,    /* 31-24 Stride */
 141                                 store_latency   : 8,    /*39-32 Store latency*/
 142                                 load_latency    : 8,    /* 47-40 Load latency*/
 143                                 store_hints     : 8,    /* 55-48 Store hints*/
 144                                 load_hints      : 8;    /* 63-56 Load hints */
 145         } pcci1_bits;
 146         u64                     pcci1_data;
 147 } pal_cache_config_info_1_t;
 148
 149 typedef union  pal_cache_config_info_2_s {
 150         struct {
 151                 u64             cache_size      : 32,   /*cache size in bytes*/
 152
 153
 154                                 alias_boundary  : 8,    /* 39-32 aliased addr
 155                                                          * separation for max
 156                                                          * performance.
 157                                                          */
 158                                 tag_ls_bit      : 8,    /* 47-40 LSb of addr*/
 159                                 tag_ms_bit      : 8,    /* 55-48 MSb of addr*/
 160                                 reserved        : 8;    /* 63-56 Reserved */
 161         } pcci2_bits;
 162         u64                     pcci2_data;
 163 } pal_cache_config_info_2_t;
 164
 165
 166 typedef struct pal_cache_config_info_s {
 167         pal_status_t                    pcci_status;
 168         pal_cache_config_info_1_t       pcci_info_1;
 169         pal_cache_config_info_2_t       pcci_info_2;
 170         u64                             pcci_reserved;
 171 } pal_cache_config_info_t;
 172
 173 #define pcci_ld_hints           pcci_info_1.pcci1_bits.load_hints
 174 #define pcci_st_hints           pcci_info_1.pcci1_bits.store_hints
 175 #define pcci_ld_latency         pcci_info_1.pcci1_bits.load_latency
 176 #define pcci_st_latency         pcci_info_1.pcci1_bits.store_latency
 177 #define pcci_stride             pcci_info_1.pcci1_bits.stride
 178 #define pcci_line_size          pcci_info_1.pcci1_bits.line_size
 179 #define pcci_assoc              pcci_info_1.pcci1_bits.associativity
 180 #define pcci_cache_attr         pcci_info_1.pcci1_bits.at
 181 #define pcci_unified            pcci_info_1.pcci1_bits.u
 182 #define pcci_tag_msb            pcci_info_2.pcci2_bits.tag_ms_bit
 183 #define pcci_tag_lsb            pcci_info_2.pcci2_bits.tag_ls_bit
 184 #define pcci_alias_boundary     pcci_info_2.pcci2_bits.alias_boundary
 185 #define pcci_cache_size         pcci_info_2.pcci2_bits.cache_size
 186
 187
 188
 189 /* Possible values for cache attributes */
 190
 191 #define PAL_CACHE_ATTR_WT               0       /* Write through cache */
 192 #define PAL_CACHE_ATTR_WB               1       /* Write back cache */
 193 #define PAL_CACHE_ATTR_WT_OR_WB         2       /* Either write thru or write
 194                                                  * back depending on TLB
 195                                                  * memory attributes
 196                                                  */
 197
 198
 199 /* Possible values for cache hints */
 200
 201 #define PAL_CACHE_HINT_TEMP_1           0       /* Temporal level 1 */
 202 #define PAL_CACHE_HINT_NTEMP_1          1       /* Non-temporal level 1 */
 203 #define PAL_CACHE_HINT_NTEMP_ALL        3       /* Non-temporal all levels */
 204
 205 /* Processor cache protection  information */
 206 typedef union pal_cache_protection_element_u {
 207         u32                     pcpi_data;
 208         struct {
 209                 u32             data_bits       : 8, /* # data bits covered by
 210                                                       * each unit of protection
 211                                                       */
 212
 213                                 tagprot_lsb     : 6, /* Least -do- */
 214                                 tagprot_msb     : 6, /* Most Sig. tag address
 215                                                       * bit that this
 216                                                       * protection covers.
 217                                                       */
 218                                 prot_bits       : 6, /* # of protection bits */
 219                                 method          : 4, /* Protection method */
 220                                 t_d             : 2; /* Indicates which part
 221                                                       * of the cache this
 222                                                       * protection encoding
 223                                                       * applies.
 224                                                       */
 225         } pcp_info;
 226 } pal_cache_protection_element_t;
 227
 228 #define pcpi_cache_prot_part    pcp_info.t_d
 229 #define pcpi_prot_method        pcp_info.method
 230 #define pcpi_prot_bits          pcp_info.prot_bits
 231 #define pcpi_tagprot_msb        pcp_info.tagprot_msb
 232 #define pcpi_tagprot_lsb        pcp_info.tagprot_lsb
 233 #define pcpi_data_bits          pcp_info.data_bits
 234
 235 /* Processor cache part encodings */
 236 #define PAL_CACHE_PROT_PART_DATA        0       /* Data protection  */
 237 #define PAL_CACHE_PROT_PART_TAG         1       /* Tag  protection */
 238 #define PAL_CACHE_PROT_PART_TAG_DATA    2       /* Tag+data protection (tag is
 239                                                  * more significant )
 240                                                  */
 241 #define PAL_CACHE_PROT_PART_DATA_TAG    3       /* Data+tag protection (data is
 242                                                  * more significant )
 243                                                  */
 244 #define PAL_CACHE_PROT_PART_MAX         6
 245
 246
 247 typedef struct pal_cache_protection_info_s {
 248         pal_status_t                    pcpi_status;
 249         pal_cache_protection_element_t  pcp_info[PAL_CACHE_PROT_PART_MAX];
 250 } pal_cache_protection_info_t;
 251
 252
 253 /* Processor cache protection method encodings */
 254 #define PAL_CACHE_PROT_METHOD_NONE              0       /* No protection */
 255 #define PAL_CACHE_PROT_METHOD_ODD_PARITY        1       /* Odd parity */
 256 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY       2       /* Even parity */
 257 #define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
 258
 259
 260 /* Processor cache line identification in the heirarchy */
 261 typedef union pal_cache_line_id_u {
 262         u64                     pclid_data;
 263         struct {
 264                 u64             cache_type      : 8,    /* 7-0 cache type */
 265                                 level           : 8,    /* 15-8 level of the
 266                                                          * cache in the
 267                                                          * heirarchy.
 268                                                          */
 269                                 way             : 8,    /* 23-16 way in the set
 270                                                          */
 271                                 part            : 8,    /* 31-24 part of the
 272                                                          * cache
 273                                                          */
 274                                 reserved        : 32;   /* 63-32 is reserved*/
 275         } pclid_info_read;
 276         struct {
 277                 u64             cache_type      : 8,    /* 7-0 cache type */
 278                                 level           : 8,    /* 15-8 level of the
 279                                                          * cache in the
 280                                                          * heirarchy.
 281                                                          */
 282                                 way             : 8,    /* 23-16 way in the set
 283                                                          */
 284                                 part            : 8,    /* 31-24 part of the
 285                                                          * cache
 286                                                          */
 287                                 mesi            : 8,    /* 39-32 cache line
 288                                                          * state
 289                                                          */
 290                                 start           : 8,    /* 47-40 lsb of data to
 291                                                          * invert
 292                                                          */
 293                                 length          : 8,    /* 55-48 #bits to
 294                                                          * invert
 295                                                          */
 296                                 trigger         : 8;    /* 63-56 Trigger error
 297                                                          * by doing a load
 298                                                          * after the write
 299                                                          */
 300
 301         } pclid_info_write;
 302 } pal_cache_line_id_u_t;
 303
 304 #define pclid_read_part         pclid_info_read.part
 305 #define pclid_read_way          pclid_info_read.way
 306 #define pclid_read_level        pclid_info_read.level
 307 #define pclid_read_cache_type   pclid_info_read.cache_type
 308
 309 #define pclid_write_trigger     pclid_info_write.trigger
 310 #define pclid_write_length      pclid_info_write.length
 311 #define pclid_write_start       pclid_info_write.start
 312 #define pclid_write_mesi        pclid_info_write.mesi
 313 #define pclid_write_part        pclid_info_write.part
 314 #define pclid_write_way         pclid_info_write.way
 315 #define pclid_write_level       pclid_info_write.level
 316 #define pclid_write_cache_type  pclid_info_write.cache_type
 317
 318 /* Processor cache line part encodings */
 319 #define PAL_CACHE_LINE_ID_PART_DATA             0       /* Data */
 320 #define PAL_CACHE_LINE_ID_PART_TAG              1       /* Tag */
 321 #define PAL_CACHE_LINE_ID_PART_DATA_PROT        2       /* Data protection */
 322 #define PAL_CACHE_LINE_ID_PART_TAG_PROT         3       /* Tag protection */
 323 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT    4       /* Data+tag
 324                                                          * protection
 325                                                          */
 326 typedef struct pal_cache_line_info_s {
 327         pal_status_t            pcli_status;            /* Return status of the read cache line
 328                                                          * info call.
 329                                                          */
 330         u64                     pcli_data;              /* 64-bit data, tag, protection bits .. */
 331         u64                     pcli_data_len;          /* data length in bits */
 332         pal_cache_line_state_t  pcli_cache_line_state;  /* mesi state */
 333
 334 } pal_cache_line_info_t;
 335
 336
 337 /* Machine Check related crap */
 338
 339 /* Pending event status bits  */
 340 typedef u64                                     pal_mc_pending_events_t;
 341
 342 #define PAL_MC_PENDING_MCA                      (1 << 0)
 343 #define PAL_MC_PENDING_INIT                     (1 << 1)
 344
 345 /* Error information type */
 346 typedef u64                                     pal_mc_info_index_t;
 347
 348 #define PAL_MC_INFO_PROCESSOR                   0       /* Processor */
 349 #define PAL_MC_INFO_CACHE_CHECK                 1       /* Cache check */
 350 #define PAL_MC_INFO_TLB_CHECK                   2       /* Tlb check */
 351 #define PAL_MC_INFO_BUS_CHECK                   3       /* Bus check */
 352 #define PAL_MC_INFO_REQ_ADDR                    4       /* Requestor address */
 353 #define PAL_MC_INFO_RESP_ADDR                   5       /* Responder address */
 354 #define PAL_MC_INFO_TARGET_ADDR                 6       /* Target address */
 355 #define PAL_MC_INFO_IMPL_DEP                    7       /* Implementation
 356                                                          * dependent
 357                                                          */
 358
 359
 360 typedef struct pal_process_state_info_s {
 361         u64             reserved1       : 2,
 362                         rz              : 1,    /* PAL_CHECK processor
 363                                                  * rendezvous
 364                                                  * successful.
 365                                                  */
 366
 367                         ra              : 1,    /* PAL_CHECK attempted
 368                                                  * a rendezvous.
 369                                                  */
 370                         me              : 1,    /* Distinct multiple
 371                                                  * errors occurred
 372                                                  */
 373
 374                         mn              : 1,    /* Min. state save
 375                                                  * area has been
 376                                                  * registered with PAL
 377                                                  */
 378
 379                         sy              : 1,    /* Storage integrity
 380                                                  * synched
 381                                                  */
 382
 383
 384                         co              : 1,    /* Continuable */
 385                         ci              : 1,    /* MC isolated */
 386                         us              : 1,    /* Uncontained storage
 387                                                  * damage.
 388                                                  */
 389
 390
 391                         hd              : 1,    /* Non-essential hw
 392                                                  * lost (no loss of
 393                                                  * functionality)
 394                                                  * causing the
 395                                                  * processor to run in
 396                                                  * degraded mode.
 397                                                  */
 398
 399                         tl              : 1,    /* 1 => MC occurred
 400                                                  * after an instr was
 401                                                  * executed but before
 402                                                  * the trap that
 403                                                  * resulted from instr
 404                                                  * execution was
 405                                                  * generated.
 406                                                  * (Trap Lost )
 407                                                  */
 408                         op              : 3,    /* Operation that
 409                                                  * caused the machine
 410                                                  * check
 411                                                  */
 412
 413                         dy              : 1,    /* Processor dynamic
 414                                                  * state valid
 415                                                  */
 416
 417
 418                         in              : 1,    /* 0 = MC, 1 = INIT */
 419                         rs              : 1,    /* RSE valid */
 420                         cm              : 1,    /* MC corrected */
 421                         ex              : 1,    /* MC is expected */
 422                         cr              : 1,    /* Control regs valid*/
 423                         pc              : 1,    /* Perf cntrs valid */
 424                         dr              : 1,    /* Debug regs valid */
 425                         tr              : 1,    /* Translation regs
 426                                                  * valid
 427                                                  */
 428                         rr              : 1,    /* Region regs valid */
 429                         ar              : 1,    /* App regs valid */
 430                         br              : 1,    /* Branch regs valid */
 431                         pr              : 1,    /* Predicate registers
 432                                                  * valid
 433                                                  */
 434
 435                         fp              : 1,    /* fp registers valid*/
 436                         b1              : 1,    /* Preserved bank one
 437                                                  * general registers
 438                                                  * are valid
 439                                                  */
 440                         b0              : 1,    /* Preserved bank zero
 441                                                  * general registers
 442                                                  * are valid
 443                                                  */
 444                         gr              : 1,    /* General registers
 445                                                  * are valid
 446                                                  * (excl. banked regs)
 447                                                  */
 448                         dsize           : 16,   /* size of dynamic
 449                                                  * state returned
 450                                                  * by the processor
 451                                                  */
 452
 453                         reserved2       : 12,
 454                         cc              : 1,    /* Cache check */
 455                         tc              : 1,    /* TLB check */
 456                         bc              : 1,    /* Bus check */
 457                         uc              : 1;    /* Unknown check */
 458
 459 } pal_processor_state_info_t;
 460
 461 typedef struct pal_cache_check_info_s {
 462         u64             reserved1       : 16,
 463                         way             : 5,    /* Way in which the
 464                                                  * error occurred
 465                                                  */
 466                         reserved2       : 1,
 467                         mc              : 1,    /* Machine check corrected */
 468                         tv              : 1,    /* Target address
 469                                                  * structure is valid
 470                                                  */
 471
 472                         wv              : 1,    /* Way field valid */
 473                         op              : 3,    /* Type of cache
 474                                                  * operation that
 475                                                  * caused the machine
 476                                                  * check.
 477                                                  */
 478
 479                         dl              : 1,    /* Failure in data part
 480                                                  * of cache line
 481                                                  */
 482                         tl              : 1,    /* Failure in tag part
 483                                                  * of cache line
 484                                                  */
 485                         dc              : 1,    /* Failure in dcache */
 486                         ic              : 1,    /* Failure in icache */
 487                         index           : 24,   /* Cache line index */
 488                         mv              : 1,    /* mesi valid */
 489                         mesi            : 3,    /* Cache line state */
 490                         level           : 4;    /* Cache level */
 491
 492 } pal_cache_check_info_t;
 493
 494 typedef struct pal_tlb_check_info_s {
 495
 496         u64             tr_slot         : 8,    /* Slot# of TR where
 497                                                  * error occurred
 498                                                  */
 499                         reserved2       : 8,
 500                         dtr             : 1,    /* Fail in data TR */
 501                         itr             : 1,    /* Fail in inst TR */
 502                         dtc             : 1,    /* Fail in data TC */
 503                         itc             : 1,    /* Fail in inst. TC */
 504                         mc              : 1,    /* Machine check corrected */
 505                         reserved1       : 43;
 506
 507 } pal_tlb_check_info_t;
 508
 509 typedef struct pal_bus_check_info_s {
 510         u64             size            : 5,    /* Xaction size*/
 511                         ib              : 1,    /* Internal bus error */
 512                         eb              : 1,    /* External bus error */
 513                         cc              : 1,    /* Error occurred
 514                                                  * during cache-cache
 515                                                  * transfer.
 516                                                  */
 517                         type            : 8,    /* Bus xaction type*/
 518                         sev             : 5,    /* Bus error severity*/
 519                         tv              : 1,    /* Targ addr valid */
 520                         rp              : 1,    /* Resp addr valid */
 521                         rq              : 1,    /* Req addr valid */
 522                         bsi             : 8,    /* Bus error status
 523                                                  * info
 524                                                  */
 525                         mc              : 1,    /* Machine check corrected */
 526                         reserved1       : 31;
 527 } pal_bus_check_info_t;
 528
 529 typedef union pal_mc_error_info_u {
 530         u64                             pmei_data;
 531         pal_processor_state_info_t      pme_processor;
 532         pal_cache_check_info_t          pme_cache;
 533         pal_tlb_check_info_t            pme_tlb;
 534         pal_bus_check_info_t            pme_bus;
 535 } pal_mc_error_info_t;
 536
 537 #define pmci_proc_unknown_check                 pme_processor.uc
 538 #define pmci_proc_bus_check                     pme_processor.bc
 539 #define pmci_proc_tlb_check                     pme_processor.tc
 540 #define pmci_proc_cache_check                   pme_processor.cc
 541 #define pmci_proc_dynamic_state_size            pme_processor.dsize
 542 #define pmci_proc_gpr_valid                     pme_processor.gr
 543 #define pmci_proc_preserved_bank0_gpr_valid     pme_processor.b0
 544 #define pmci_proc_preserved_bank1_gpr_valid     pme_processor.b1
 545 #define pmci_proc_fp_valid                      pme_processor.fp
 546 #define pmci_proc_predicate_regs_valid          pme_processor.pr
 547 #define pmci_proc_branch_regs_valid             pme_processor.br
 548 #define pmci_proc_app_regs_valid                pme_processor.ar
 549 #define pmci_proc_region_regs_valid             pme_processor.rr
 550 #define pmci_proc_translation_regs_valid        pme_processor.tr
 551 #define pmci_proc_debug_regs_valid              pme_processor.dr
 552 #define pmci_proc_perf_counters_valid           pme_processor.pc
 553 #define pmci_proc_control_regs_valid            pme_processor.cr
 554 #define pmci_proc_machine_check_expected        pme_processor.ex
 555 #define pmci_proc_machine_check_corrected       pme_processor.cm
 556 #define pmci_proc_rse_valid                     pme_processor.rs
 557 #define pmci_proc_machine_check_or_init         pme_processor.in
 558 #define pmci_proc_dynamic_state_valid           pme_processor.dy
 559 #define pmci_proc_operation                     pme_processor.op
 560 #define pmci_proc_trap_lost                     pme_processor.tl
 561 #define pmci_proc_hardware_damage               pme_processor.hd
 562 #define pmci_proc_uncontained_storage_damage    pme_processor.us
 563 #define pmci_proc_machine_check_isolated        pme_processor.ci
 564 #define pmci_proc_continuable                   pme_processor.co
 565 #define pmci_proc_storage_intergrity_synced     pme_processor.sy
 566 #define pmci_proc_min_state_save_area_regd      pme_processor.mn
 567 #define pmci_proc_distinct_multiple_errors      pme_processor.me
 568 #define pmci_proc_pal_attempted_rendezvous      pme_processor.ra
 569 #define pmci_proc_pal_rendezvous_complete       pme_processor.rz
 570
 571
 572 #define pmci_cache_level                        pme_cache.level
 573 #define pmci_cache_line_state                   pme_cache.mesi
 574 #define pmci_cache_line_state_valid             pme_cache.mv
 575 #define pmci_cache_line_index                   pme_cache.index
 576 #define pmci_cache_instr_cache_fail             pme_cache.ic
 577 #define pmci_cache_data_cache_fail              pme_cache.dc
 578 #define pmci_cache_line_tag_fail                pme_cache.tl
 579 #define pmci_cache_line_data_fail               pme_cache.dl
 580 #define pmci_cache_operation                    pme_cache.op
 581 #define pmci_cache_way_valid                    pme_cache.wv
 582 #define pmci_cache_target_address_valid         pme_cache.tv
 583 #define pmci_cache_way                          pme_cache.way
 584 #define pmci_cache_mc                           pme_cache.mc
 585
 586 #define pmci_tlb_instr_translation_cache_fail   pme_tlb.itc
 587 #define pmci_tlb_data_translation_cache_fail    pme_tlb.dtc
 588 #define pmci_tlb_instr_translation_reg_fail     pme_tlb.itr
 589 #define pmci_tlb_data_translation_reg_fail      pme_tlb.dtr
 590 #define pmci_tlb_translation_reg_slot           pme_tlb.tr_slot
 591 #define pmci_tlb_mc                             pme_tlb.mc
 592
 593 #define pmci_bus_status_info                    pme_bus.bsi
 594 #define pmci_bus_req_address_valid              pme_bus.rq
 595 #define pmci_bus_resp_address_valid             pme_bus.rp
 596 #define pmci_bus_target_address_valid           pme_bus.tv
 597 #define pmci_bus_error_severity                 pme_bus.sev
 598 #define pmci_bus_transaction_type               pme_bus.type
 599 #define pmci_bus_cache_cache_transfer           pme_bus.cc
 600 #define pmci_bus_transaction_size               pme_bus.size
 601 #define pmci_bus_internal_error                 pme_bus.ib
 602 #define pmci_bus_external_error                 pme_bus.eb
 603 #define pmci_bus_mc                             pme_bus.mc
 604
 605 /*
 606  * NOTE: this min_state_save area struct only includes the 1KB
 607  * architectural state save area.  The other 3 KB is scratch space
 608  * for PAL.
 609  */
 610
 611 typedef struct pal_min_state_area_s {
 612         u64     pmsa_nat_bits;          /* nat bits for saved GRs  */
 613         u64     pmsa_gr[15];            /* GR1  - GR15             */
 614         u64     pmsa_bank0_gr[16];      /* GR16 - GR31             */
 615         u64     pmsa_bank1_gr[16];      /* GR16 - GR31             */
 616         u64     pmsa_pr;                /* predicate registers     */
 617         u64     pmsa_br0;               /* branch register 0       */
 618         u64     pmsa_rsc;               /* ar.rsc                  */
 619         u64     pmsa_iip;               /* cr.iip                  */
 620         u64     pmsa_ipsr;              /* cr.ipsr                 */
 621         u64     pmsa_ifs;               /* cr.ifs                  */
 622         u64     pmsa_xip;               /* previous iip            */
 623         u64     pmsa_xpsr;              /* previous psr            */
 624         u64     pmsa_xfs;               /* previous ifs            */
 625         u64     pmsa_br1;               /* branch register 1       */
 626         u64     pmsa_reserved[70];      /* pal_min_state_area should total to 1KB */
 627 } pal_min_state_area_t;
 628
 629
 630 struct ia64_pal_retval {
 631         /*
 632          * A zero status value indicates call completed without error.
 633          * A negative status value indicates reason of call failure.
 634          * A positive status value indicates success but an
 635          * informational value should be printed (e.g., "reboot for
 636          * change to take effect").
 637          */
 638         s64 status;
 639         u64 v0;
 640         u64 v1;
 641         u64 v2;
 642 };
 643
 644 /*
 645  * Note: Currently unused PAL arguments are generally labeled
 646  * "reserved" so the value specified in the PAL documentation
 647  * (generally 0) MUST be passed.  Reserved parameters are not optional
 648  * parameters.
 649  */
 650 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
 651 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
 652 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
 653 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
 654 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
 655 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
 656
 657 #define PAL_CALL(iprv,a0,a1,a2,a3) do {                 \
 658         struct ia64_fpreg fr[6];                        \
 659         ia64_save_scratch_fpregs(fr);                   \
 660         iprv = ia64_pal_call_static(a0, a1, a2, a3, 0); \
 661         ia64_load_scratch_fpregs(fr);                   \
 662 } while (0)
 663
 664 #define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do {          \
 665         struct ia64_fpreg fr[6];                        \
 666         ia64_save_scratch_fpregs(fr);                   \
 667         iprv = ia64_pal_call_static(a0, a1, a2, a3, 1); \
 668         ia64_load_scratch_fpregs(fr);                   \
 669 } while (0)
 670
 671 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {             \
 672         struct ia64_fpreg fr[6];                        \
 673         ia64_save_scratch_fpregs(fr);                   \
 674         iprv = ia64_pal_call_stacked(a0, a1, a2, a3);   \
 675         ia64_load_scratch_fpregs(fr);                   \
 676 } while (0)
 677
 678 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {                    \
 679         struct ia64_fpreg fr[6];                                \
 680         ia64_save_scratch_fpregs(fr);                           \
 681         iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);       \
 682         ia64_load_scratch_fpregs(fr);                           \
 683 } while (0)
 684
 685 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {                \
 686         struct ia64_fpreg fr[6];                                \
 687         ia64_save_scratch_fpregs(fr);                           \
 688         iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);      \
 689         ia64_load_scratch_fpregs(fr);                           \
 690 } while (0)
 691
 692 typedef int (*ia64_pal_handler) (u64, ...);
 693 extern ia64_pal_handler ia64_pal;
 694 extern void ia64_pal_handler_init (void *);
 695
 696 extern ia64_pal_handler ia64_pal;
 697
 698 extern pal_cache_config_info_t          l0d_cache_config_info;
 699 extern pal_cache_config_info_t          l0i_cache_config_info;
 700 extern pal_cache_config_info_t          l1_cache_config_info;
 701 extern pal_cache_config_info_t          l2_cache_config_info;
 702
 703 extern pal_cache_protection_info_t      l0d_cache_protection_info;
 704 extern pal_cache_protection_info_t      l0i_cache_protection_info;
 705 extern pal_cache_protection_info_t      l1_cache_protection_info;
 706 extern pal_cache_protection_info_t      l2_cache_protection_info;
 707
 708 extern pal_cache_config_info_t          pal_cache_config_info_get(pal_cache_level_t,
 709                                                                   pal_cache_type_t);
 710
 711 extern pal_cache_protection_info_t      pal_cache_protection_info_get(pal_cache_level_t,
 712                                                                       pal_cache_type_t);
 713
 714
 715 extern void                             pal_error(int);
 716
 717
 718 /* Useful wrappers for the current list of pal procedures */
 719
 720 typedef union pal_bus_features_u {
 721         u64     pal_bus_features_val;
 722         struct {
 723                 u64     pbf_reserved1                           :       29;
 724                 u64     pbf_req_bus_parking                     :       1;
 725                 u64     pbf_bus_lock_mask                       :       1;
 726                 u64     pbf_enable_half_xfer_rate               :       1;
 727                 u64     pbf_reserved2                           :       22;
 728                 u64     pbf_disable_xaction_queueing            :       1;
 729                 u64     pbf_disable_resp_err_check              :       1;
 730                 u64     pbf_disable_berr_check                  :       1;
 731                 u64     pbf_disable_bus_req_internal_err_signal :       1;
 732                 u64     pbf_disable_bus_req_berr_signal         :       1;
 733                 u64     pbf_disable_bus_init_event_check        :       1;
 734                 u64     pbf_disable_bus_init_event_signal       :       1;
 735                 u64     pbf_disable_bus_addr_err_check          :       1;
 736                 u64     pbf_disable_bus_addr_err_signal         :       1;
 737                 u64     pbf_disable_bus_data_err_check          :       1;
 738         } pal_bus_features_s;
 739 } pal_bus_features_u_t;
 740
 741 extern void pal_bus_features_print (u64);
 742
 743 /* Provide information about configurable processor bus features */
 744 static inline s64
 745 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
 746                            pal_bus_features_u_t *features_status,
 747                            pal_bus_features_u_t *features_control)
 748 {
 749         struct ia64_pal_retval iprv;
 750         PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
 751         if (features_avail)
 752                 features_avail->pal_bus_features_val = iprv.v0;
 753         if (features_status)
 754                 features_status->pal_bus_features_val = iprv.v1;
 755         if (features_control)
 756                 features_control->pal_bus_features_val = iprv.v2;
 757         return iprv.status;
 758 }
 759
 760 /* Enables/disables specific processor bus features */
 761 static inline s64
 762 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
 763 {
 764         struct ia64_pal_retval iprv;
 765         PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
 766         return iprv.status;
 767 }
 768
 769 /* Get detailed cache information */
 770 static inline s64
 771 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
 772 {
 773         struct ia64_pal_retval iprv;
 774
 775         PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
 776
 777         if (iprv.status == 0) {
 778                 conf->pcci_status                 = iprv.status;
 779                 conf->pcci_info_1.pcci1_data      = iprv.v0;
 780                 conf->pcci_info_2.pcci2_data      = iprv.v1;
 781                 conf->pcci_reserved               = iprv.v2;
 782         }
 783         return iprv.status;
 784
 785 }
 786
 787 /* Get detailed cche protection information */
 788 static inline s64
 789 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
 790 {
 791         struct ia64_pal_retval iprv;
 792
 793         PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
 794
 795         if (iprv.status == 0) {
 796                 prot->pcpi_status           = iprv.status;
 797                 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
 798                 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
 799                 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
 800                 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
 801                 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
 802                 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
 803         }
 804         return iprv.status;
 805 }
 806
 807 /*
 808  * Flush the processor instruction or data caches.  *PROGRESS must be
 809  * initialized to zero before calling this for the first time..
 810  */
 811 static inline s64
 812 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
 813 {
 814         struct ia64_pal_retval iprv;
 815         PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
 816         if (vector)
 817                 *vector = iprv.v0;
 818         *progress = iprv.v1;
 819         return iprv.status;
 820 }
 821
 822
 823 /* Initialize the processor controlled caches */
 824 static inline s64
 825 ia64_pal_cache_init (u64 level, u64 cache_type, u64 restrict)
 826 {
 827         struct ia64_pal_retval iprv;
 828         PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, restrict);
 829         return iprv.status;
 830 }
 831
 832 /* Initialize the tags and data of a data or unified cache line of
 833  * processor controlled cache to known values without the availability
 834  * of backing memory.
 835  */
 836 static inline s64
 837 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
 838 {
 839         struct ia64_pal_retval iprv;
 840         PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
 841         return iprv.status;
 842 }
 843
 844
 845 /* Read the data and tag of a processor controlled cache line for diags */
 846 static inline s64
 847 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
 848 {
 849         struct ia64_pal_retval iprv;
 850         PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
 851         return iprv.status;
 852 }
 853
 854 /* Return summary information about the heirarchy of caches controlled by the processor */
 855 static inline s64
 856 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
 857 {
 858         struct ia64_pal_retval iprv;
 859         PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
 860         if (cache_levels)
 861                 *cache_levels = iprv.v0;
 862         if (unique_caches)
 863                 *unique_caches = iprv.v1;
 864         return iprv.status;
 865 }
 866
 867 /* Write the data and tag of a processor-controlled cache line for diags */
 868 static inline s64
 869 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
 870 {
 871         struct ia64_pal_retval iprv;
 872         PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
 873         return iprv.status;
 874 }
 875
 876
 877 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
 878 static inline s64
 879 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
 880                     u64 *buffer_size, u64 *buffer_align)
 881 {
 882         struct ia64_pal_retval iprv;
 883         PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
 884         if (buffer_size)
 885                 *buffer_size = iprv.v0;
 886         if (buffer_align)
 887                 *buffer_align = iprv.v1;
 888         return iprv.status;
 889 }
 890
 891 /* Copy relocatable PAL procedures from ROM to memory */
 892 static inline s64
 893 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
 894 {
 895         struct ia64_pal_retval iprv;
 896         PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
 897         if (pal_proc_offset)
 898                 *pal_proc_offset = iprv.v0;
 899         return iprv.status;
 900 }
 901
 902 /* Return the number of instruction and data debug register pairs */
 903 static inline s64
 904 ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs)
 905 {
 906         struct ia64_pal_retval iprv;
 907         PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
 908         if (inst_regs)
 909                 *inst_regs = iprv.v0;
 910         if (data_regs)
 911                 *data_regs = iprv.v1;
 912
 913         return iprv.status;
 914 }
 915
 916 #ifdef TBD
 917 /* Switch from IA64-system environment to IA-32 system environment */
 918 static inline s64
 919 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
 920 {
 921         struct ia64_pal_retval iprv;
 922         PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
 923         return iprv.status;
 924 }
 925 #endif
 926
 927 /* Get unique geographical address of this processor on its bus */
 928 static inline s64
 929 ia64_pal_fixed_addr (u64 *global_unique_addr)
 930 {
 931         struct ia64_pal_retval iprv;
 932         PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
 933         if (global_unique_addr)
 934                 *global_unique_addr = iprv.v0;
 935         return iprv.status;
 936 }
 937
 938 /* Get base frequency of the platform if generated by the processor */
 939 static inline s64
 940 ia64_pal_freq_base (u64 *platform_base_freq)
 941 {
 942         struct ia64_pal_retval iprv;
 943         PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
 944         if (platform_base_freq)
 945                 *platform_base_freq = iprv.v0;
 946         return iprv.status;
 947 }
 948
 949 /*
 950  * Get the ratios for processor frequency, bus frequency and interval timer to
 951  * to base frequency of the platform
 952  */
 953 static inline s64
 954 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
 955                       struct pal_freq_ratio *itc_ratio)
 956 {
 957         struct ia64_pal_retval iprv;
 958         PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
 959         if (proc_ratio)
 960                 *(u64 *)proc_ratio = iprv.v0;
 961         if (bus_ratio)
 962                 *(u64 *)bus_ratio = iprv.v1;
 963         if (itc_ratio)
 964                 *(u64 *)itc_ratio = iprv.v2;
 965         return iprv.status;
 966 }
 967
 968 /* Make the processor enter HALT or one of the implementation dependent low
 969  * power states where prefetching and execution are suspended and cache and
 970  * TLB coherency is not maintained.
 971  */
 972 static inline s64
 973 ia64_pal_halt (u64 halt_state)
 974 {
 975         struct ia64_pal_retval iprv;
 976         PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
 977         return iprv.status;
 978 }
 979
 980 typedef union pal_power_mgmt_info_u {
 981         u64                     ppmi_data;
 982         struct {
 983                u64              exit_latency            : 16,
 984                                 entry_latency           : 16,
 985                                 power_consumption       : 28,
 986                                 im                      : 1,
 987                                 co                      : 1,
 988                                 reserved                : 2;
 989         } pal_power_mgmt_info_s;
 990 } pal_power_mgmt_info_u_t;
 991
 992 /* Return information about processor's optional power management capabilities. */
 993 static inline s64
 994 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
 995 {
 996         struct ia64_pal_retval iprv;
 997         PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
 998         return iprv.status;
 999 }
1000
1001 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1002  * suspended, but cache and TLB coherency is maintained.
1003  */
1004 static inline s64
1005 ia64_pal_halt_light (void)
1006 {
1007         struct ia64_pal_retval iprv;
1008         PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1009         return iprv.status;
1010 }
1011
1012 /* Clear all the processor error logging   registers and reset the indicator that allows
1013  * the error logging registers to be written. This procedure also checks the pending
1014  * machine check bit and pending INIT bit and reports their states.
1015  */
1016 static inline s64
1017 ia64_pal_mc_clear_log (u64 *pending_vector)
1018 {
1019         struct ia64_pal_retval iprv;
1020         PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1021         if (pending_vector)
1022                 *pending_vector = iprv.v0;
1023         return iprv.status;
1024 }
1025
1026 /* Ensure that all outstanding transactions in a processor are completed or that any
1027  * MCA due to thes outstanding transaction is taken.
1028  */
1029 static inline s64
1030 ia64_pal_mc_drain (void)
1031 {
1032         struct ia64_pal_retval iprv;
1033         PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1034         return iprv.status;
1035 }
1036
1037 /* Return the machine check dynamic processor state */
1038 static inline s64
1039 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1040 {
1041         struct ia64_pal_retval iprv;
1042         PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1043         if (size)
1044                 *size = iprv.v0;
1045         if (pds)
1046                 *pds = iprv.v1;
1047         return iprv.status;
1048 }
1049
1050 /* Return processor machine check information */
1051 static inline s64
1052 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1053 {
1054         struct ia64_pal_retval iprv;
1055         PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1056         if (size)
1057                 *size = iprv.v0;
1058         if (error_info)
1059                 *error_info = iprv.v1;
1060         return iprv.status;
1061 }
1062
1063 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1064  * attempt to correct any expected machine checks.
1065  */
1066 static inline s64
1067 ia64_pal_mc_expected (u64 expected, u64 *previous)
1068 {
1069         struct ia64_pal_retval iprv;
1070         PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1071         if (previous)
1072                 *previous = iprv.v0;
1073         return iprv.status;
1074 }
1075
1076 /* Register a platform dependent location with PAL to which it can save
1077  * minimal processor state in the event of a machine check or initialization
1078  * event.
1079  */
1080 static inline s64
1081 ia64_pal_mc_register_mem (u64 physical_addr)
1082 {
1083         struct ia64_pal_retval iprv;
1084         PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1085         return iprv.status;
1086 }
1087
1088 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1089  * and resume execution
1090  */
1091 static inline s64
1092 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1093 {
1094         struct ia64_pal_retval iprv;
1095         PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1096         return iprv.status;
1097 }
1098
1099 /* Return the memory attributes implemented by the processor */
1100 static inline s64
1101 ia64_pal_mem_attrib (u64 *mem_attrib)
1102 {
1103         struct ia64_pal_retval iprv;
1104         PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1105         if (mem_attrib)
1106                 *mem_attrib = iprv.v0 & 0xff;
1107         return iprv.status;
1108 }
1109
1110 /* Return the amount of memory needed for second phase of processor
1111  * self-test and the required alignment of memory.
1112  */
1113 static inline s64
1114 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1115 {
1116         struct ia64_pal_retval iprv;
1117         PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1118         if (bytes_needed)
1119                 *bytes_needed = iprv.v0;
1120         if (alignment)
1121                 *alignment = iprv.v1;
1122         return iprv.status;
1123 }
1124
1125 typedef union pal_perf_mon_info_u {
1126         u64                       ppmi_data;
1127         struct {
1128                u64              generic         : 8,
1129                                 width           : 8,
1130                                 cycles          : 8,
1131                                 retired         : 8,
1132                                 reserved        : 32;
1133         } pal_perf_mon_info_s;
1134 } pal_perf_mon_info_u_t;
1135
1136 /* Return the performance monitor information about what can be counted
1137  * and how to configure the monitors to count the desired events.
1138  */
1139 static inline s64
1140 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1141 {
1142         struct ia64_pal_retval iprv;
1143         PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1144         if (pm_info)
1145                 pm_info->ppmi_data = iprv.v0;
1146         return iprv.status;
1147 }
1148
1149 /* Specifies the physical address of the processor interrupt block
1150  * and I/O port space.
1151  */
1152 static inline s64
1153 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1154 {
1155         struct ia64_pal_retval iprv;
1156         PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1157         return iprv.status;
1158 }
1159
1160 /* Set the SAL PMI entrypoint in memory */
1161 static inline s64
1162 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1163 {
1164         struct ia64_pal_retval iprv;
1165         PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1166         return iprv.status;
1167 }
1168
1169 struct pal_features_s;
1170 /* Provide information about configurable processor features */
1171 static inline s64
1172 ia64_pal_proc_get_features (u64 *features_avail,
1173                             u64 *features_status,
1174                             u64 *features_control)
1175 {
1176         struct ia64_pal_retval iprv;
1177         PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1178         if (iprv.status == 0) {
1179                 *features_avail   = iprv.v0;
1180                 *features_status  = iprv.v1;
1181                 *features_control = iprv.v2;
1182         }
1183         return iprv.status;
1184 }
1185
1186 /* Enable/disable processor dependent features */
1187 static inline s64
1188 ia64_pal_proc_set_features (u64 feature_select)
1189 {
1190         struct ia64_pal_retval iprv;
1191         PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1192         return iprv.status;
1193 }
1194
1195 /*
1196  * Put everything in a struct so we avoid the global offset table whenever
1197  * possible.
1198  */
1199 typedef struct ia64_ptce_info_s {
1200         u64             base;
1201         u32             count[2];
1202         u32             stride[2];
1203 } ia64_ptce_info_t;
1204
1205 /* Return the information required for the architected loop used to purge
1206  * (initialize) the entire TC
1207  */
1208 static inline s64
1209 ia64_get_ptce (ia64_ptce_info_t *ptce)
1210 {
1211         struct ia64_pal_retval iprv;
1212
1213         if (!ptce)
1214                 return -1;
1215
1216         PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1217         if (iprv.status == 0) {
1218                 ptce->base = iprv.v0;
1219                 ptce->count[0] = iprv.v1 >> 32;
1220                 ptce->count[1] = iprv.v1 & 0xffffffff;
1221                 ptce->stride[0] = iprv.v2 >> 32;
1222                 ptce->stride[1] = iprv.v2 & 0xffffffff;
1223         }
1224         return iprv.status;
1225 }
1226
1227 /* Return info about implemented application and control registers. */
1228 static inline s64
1229 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1230 {
1231         struct ia64_pal_retval iprv;
1232         PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1233         if (reg_info_1)
1234                 *reg_info_1 = iprv.v0;
1235         if (reg_info_2)
1236                 *reg_info_2 = iprv.v1;
1237         return iprv.status;
1238 }
1239
1240 typedef union pal_hints_u {
1241         u64                     ph_data;
1242         struct {
1243                u64              si              : 1,
1244                                 li              : 1,
1245                                 reserved        : 62;
1246         } pal_hints_s;
1247 } pal_hints_u_t;
1248
1249 /* Return information about the register stack and RSE for this processor
1250  * implementation.
1251  */
1252 static inline s64
1253 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1254 {
1255         struct ia64_pal_retval iprv;
1256         PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1257         if (num_phys_stacked)
1258                 *num_phys_stacked = iprv.v0;
1259         if (hints)
1260                 hints->ph_data = iprv.v1;
1261         return iprv.status;
1262 }
1263
1264 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1265  * suspended, but cause cache and TLB coherency to be maintained.
1266  * This is usually called in IA-32 mode.
1267  */
1268 static inline s64
1269 ia64_pal_shutdown (void)
1270 {
1271         struct ia64_pal_retval iprv;
1272         PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1273         return iprv.status;
1274 }
1275
1276 /* Perform the second phase of processor self-test. */
1277 static inline s64
1278 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1279 {
1280         struct ia64_pal_retval iprv;
1281         PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1282         if (self_test_state)
1283                 *self_test_state = iprv.v0;
1284         return iprv.status;
1285 }
1286
1287 typedef union  pal_version_u {
1288         u64     pal_version_val;
1289         struct {
1290                 u64     pv_pal_b_rev            :       8;
1291                 u64     pv_pal_b_model          :       8;
1292                 u64     pv_reserved1            :       8;
1293                 u64     pv_pal_vendor           :       8;
1294                 u64     pv_pal_a_rev            :       8;
1295                 u64     pv_pal_a_model          :       8;
1296                 u64     pv_reserved2            :       16;
1297         } pal_version_s;
1298 } pal_version_u_t;
1299
1300
1301 /* Return PAL version information */
1302 static inline s64
1303 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1304 {
1305         struct ia64_pal_retval iprv;
1306         PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1307         if (pal_min_version)
1308                 pal_min_version->pal_version_val = iprv.v0;
1309
1310         if (pal_cur_version)
1311                 pal_cur_version->pal_version_val = iprv.v1;
1312
1313         return iprv.status;
1314 }
1315
1316 typedef union pal_tc_info_u {
1317         u64                     pti_val;
1318         struct {
1319                u64              num_sets        :       8,
1320                                 associativity   :       8,
1321                                 num_entries     :       16,
1322                                 pf              :       1,
1323                                 unified         :       1,
1324                                 reduce_tr       :       1,
1325                                 reserved        :       29;
1326         } pal_tc_info_s;
1327 } pal_tc_info_u_t;
1328
1329 #define tc_reduce_tr            pal_tc_info_s.reduce_tr
1330 #define tc_unified              pal_tc_info_s.unified
1331 #define tc_pf                   pal_tc_info_s.pf
1332 #define tc_num_entries          pal_tc_info_s.num_entries
1333 #define tc_associativity        pal_tc_info_s.associativity
1334 #define tc_num_sets             pal_tc_info_s.num_sets
1335
1336
1337 /* Return information about the virtual memory characteristics of the processor
1338  * implementation.
1339  */
1340 static inline s64
1341 ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
1342 {
1343         struct ia64_pal_retval iprv;
1344         PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1345         if (tc_info)
1346                 tc_info->pti_val = iprv.v0;
1347         if (tc_pages)
1348                 *tc_pages = iprv.v1;
1349         return iprv.status;
1350 }
1351
1352 /* Get page size information about the virtual memory characteristics of the processor
1353  * implementation.
1354  */
1355 static inline s64
1356 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1357 {
1358         struct ia64_pal_retval iprv;
1359         PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1360         if (tr_pages)
1361                 *tr_pages = iprv.v0;
1362         if (vw_pages)
1363                 *vw_pages = iprv.v1;
1364         return iprv.status;
1365 }
1366
1367 typedef union pal_vm_info_1_u {
1368         u64                     pvi1_val;
1369         struct {
1370                 u64             vw              : 1,
1371                                 phys_add_size   : 7,
1372                                 key_size        : 8,
1373                                 max_pkr         : 8,
1374                                 hash_tag_id     : 8,
1375                                 max_dtr_entry   : 8,
1376                                 max_itr_entry   : 8,
1377                                 max_unique_tcs  : 8,
1378                                 num_tc_levels   : 8;
1379         } pal_vm_info_1_s;
1380 } pal_vm_info_1_u_t;
1381
1382 typedef union pal_vm_info_2_u {
1383         u64                     pvi2_val;
1384         struct {
1385                 u64             impl_va_msb     : 8,
1386                                 rid_size        : 8,
1387                                 reserved        : 48;
1388         } pal_vm_info_2_s;
1389 } pal_vm_info_2_u_t;
1390
1391 /* Get summary information about the virtual memory characteristics of the processor
1392  * implementation.
1393  */
1394 static inline s64
1395 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1396 {
1397         struct ia64_pal_retval iprv;
1398         PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1399         if (vm_info_1)
1400                 vm_info_1->pvi1_val = iprv.v0;
1401         if (vm_info_2)
1402                 vm_info_2->pvi2_val = iprv.v1;
1403         return iprv.status;
1404 }
1405
1406 typedef union pal_itr_valid_u {
1407         u64                     piv_val;
1408         struct {
1409                u64              access_rights_valid     : 1,
1410                                 priv_level_valid        : 1,
1411                                 dirty_bit_valid         : 1,
1412                                 mem_attr_valid          : 1,
1413                                 reserved                : 60;
1414         } pal_tr_valid_s;
1415 } pal_tr_valid_u_t;
1416
1417 /* Read a translation register */
1418 static inline s64
1419 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1420 {
1421         struct ia64_pal_retval iprv;
1422         PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)__pa(tr_buffer));
1423         if (tr_valid)
1424                 tr_valid->piv_val = iprv.v0;
1425         return iprv.status;
1426 }
1427
1428 static inline s64
1429 ia64_pal_prefetch_visibility (void)
1430 {
1431         struct ia64_pal_retval iprv;
1432         PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, 0, 0, 0);
1433         return iprv.status;
1434 }
1435
1436 #endif /* __ASSEMBLY__ */
1437
1438 #endif /* _ASM_IA64_PAL_H */