1 /* $Id: hfc_2bs0.c,v 1.14 2000/06/26 08:59:13 keil Exp $
3 * specific routines for CCD's HFC 2BS0
5 * Author Karsten Keil (keil@isdn4linux.de)
7 * This file is (c) under GNU PUBLIC LICENSE
11 #define __NO_VERSION__
16 #include <linux/interrupt.h>
19 WaitForBusy(struct IsdnCardState
*cs
)
27 while (!(cs
->BC_Read_Reg(cs
, HFC_STATUS
, 0) & HFC_BUSY
) && to
) {
28 val
= cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2
|
29 (cs
->hw
.hfc
.cip
& 3));
35 printk(KERN_WARNING
"HiSax: waitforBusy timeout\n");
42 WaitNoBusy(struct IsdnCardState
*cs
)
46 while ((cs
->BC_Read_Reg(cs
, HFC_STATUS
, 0) & HFC_BUSY
) && to
) {
51 printk(KERN_WARNING
"HiSax: waitforBusy timeout\n");
58 GetFreeFifoBytes(struct BCState
*bcs
)
62 if (bcs
->hw
.hfc
.f1
== bcs
->hw
.hfc
.f2
)
63 return (bcs
->cs
->hw
.hfc
.fifosize
);
64 s
= bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
] - bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f2
];
66 s
+= bcs
->cs
->hw
.hfc
.fifosize
;
67 s
= bcs
->cs
->hw
.hfc
.fifosize
- s
;
72 ReadZReg(struct BCState
*bcs
, u_char reg
)
77 val
= 256 * bcs
->cs
->BC_Read_Reg(bcs
->cs
, HFC_DATA
, reg
| HFC_CIP
| HFC_Z_HIGH
);
79 val
+= bcs
->cs
->BC_Read_Reg(bcs
->cs
, HFC_DATA
, reg
| HFC_CIP
| HFC_Z_LOW
);
84 hfc_sched_event(struct BCState
*bcs
, int event
)
86 bcs
->event
|= 1 << event
;
87 queue_task(&bcs
->tqueue
, &tq_immediate
);
88 mark_bh(IMMEDIATE_BH
);
92 hfc_clear_fifo(struct BCState
*bcs
)
94 struct IsdnCardState
*cs
= bcs
->cs
;
100 if ((cs
->debug
& L1_DEB_HSCX
) && !(cs
->debug
& L1_DEB_HSCX_FIFO
))
101 debugl1(cs
, "hfc_clear_fifo");
104 cip
= HFC_CIP
| HFC_F1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
105 if ((cip
& 0xc3) != (cs
->hw
.hfc
.cip
& 0xc3)) {
106 cs
->BC_Write_Reg(cs
, HFC_STATUS
, cip
, cip
);
110 f1
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
111 cip
= HFC_CIP
| HFC_F2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
113 f2
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
114 z1
= ReadZReg(bcs
, HFC_Z1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
115 z2
= ReadZReg(bcs
, HFC_Z2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
117 while (((f1
!= f2
) || (z1
!= z2
)) && cnt
--) {
118 if (cs
->debug
& L1_DEB_HSCX
)
119 debugl1(cs
, "hfc clear %d f1(%d) f2(%d)",
120 bcs
->channel
, f1
, f2
);
123 rcnt
+= cs
->hw
.hfc
.fifosize
;
126 if (cs
->debug
& L1_DEB_HSCX
)
127 debugl1(cs
, "hfc clear %d z1(%x) z2(%x) cnt(%d)",
128 bcs
->channel
, z1
, z2
, rcnt
);
129 cip
= HFC_CIP
| HFC_FIFO_OUT
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
131 while ((idx
< rcnt
) && WaitNoBusy(cs
)) {
132 cs
->BC_Read_Reg(cs
, HFC_DATA_NODEB
, cip
);
137 cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2_INC
| HFC_REC
|
138 HFC_CHANNEL(bcs
->channel
));
141 cip
= HFC_CIP
| HFC_F1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
143 f1
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
144 cip
= HFC_CIP
| HFC_F2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
146 f2
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
147 z1
= ReadZReg(bcs
, HFC_Z1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
148 z2
= ReadZReg(bcs
, HFC_Z2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
150 restore_flags(flags
);
155 static struct sk_buff
157 hfc_empty_fifo(struct BCState
*bcs
, int count
)
161 struct IsdnCardState
*cs
= bcs
->cs
;
166 if ((cs
->debug
& L1_DEB_HSCX
) && !(cs
->debug
& L1_DEB_HSCX_FIFO
))
167 debugl1(cs
, "hfc_empty_fifo");
169 if (count
> HSCX_BUFMAX
+ 3) {
170 if (cs
->debug
& L1_DEB_WARN
)
171 debugl1(cs
, "hfc_empty_fifo: incoming packet too large");
172 cip
= HFC_CIP
| HFC_FIFO_OUT
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
173 while ((idx
++ < count
) && WaitNoBusy(cs
))
174 cs
->BC_Read_Reg(cs
, HFC_DATA_NODEB
, cip
);
176 stat
= cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2_INC
| HFC_REC
|
177 HFC_CHANNEL(bcs
->channel
));
181 if ((count
< 4) && (bcs
->mode
!= L1_MODE_TRANS
)) {
182 if (cs
->debug
& L1_DEB_WARN
)
183 debugl1(cs
, "hfc_empty_fifo: incoming packet too small");
184 cip
= HFC_CIP
| HFC_FIFO_OUT
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
185 while ((idx
++ < count
) && WaitNoBusy(cs
))
186 cs
->BC_Read_Reg(cs
, HFC_DATA_NODEB
, cip
);
188 stat
= cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2_INC
| HFC_REC
|
189 HFC_CHANNEL(bcs
->channel
));
191 #ifdef ERROR_STATISTIC
196 if (bcs
->mode
== L1_MODE_TRANS
)
200 if (!(skb
= dev_alloc_skb(count
)))
201 printk(KERN_WARNING
"HFC: receive out of memory\n");
203 ptr
= skb_put(skb
, count
);
205 cip
= HFC_CIP
| HFC_FIFO_OUT
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
206 while ((idx
< count
- 3) && WaitNoBusy(cs
)) {
207 *ptr
++ = cs
->BC_Read_Reg(cs
, HFC_DATA_NODEB
, cip
);
211 debugl1(cs
, "RFIFO BUSY error");
212 printk(KERN_WARNING
"HFC FIFO channel %d BUSY Error\n", bcs
->channel
);
213 dev_kfree_skb_any(skb
);
214 if (bcs
->mode
!= L1_MODE_TRANS
) {
216 stat
= cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2_INC
| HFC_REC
|
217 HFC_CHANNEL(bcs
->channel
));
222 if (bcs
->mode
!= L1_MODE_TRANS
) {
224 chksum
= (cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
) << 8);
226 chksum
+= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
228 stat
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
229 if (cs
->debug
& L1_DEB_HSCX
)
230 debugl1(cs
, "hfc_empty_fifo %d chksum %x stat %x",
231 bcs
->channel
, chksum
, stat
);
233 debugl1(cs
, "FIFO CRC error");
234 dev_kfree_skb_any(skb
);
236 #ifdef ERROR_STATISTIC
241 stat
= cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F2_INC
| HFC_REC
|
242 HFC_CHANNEL(bcs
->channel
));
250 hfc_fill_fifo(struct BCState
*bcs
)
252 struct IsdnCardState
*cs
= bcs
->cs
;
261 if (bcs
->tx_skb
->len
<= 0)
266 cip
= HFC_CIP
| HFC_F1
| HFC_SEND
| HFC_CHANNEL(bcs
->channel
);
267 if ((cip
& 0xc3) != (cs
->hw
.hfc
.cip
& 0xc3)) {
268 cs
->BC_Write_Reg(cs
, HFC_STATUS
, cip
, cip
);
272 if (bcs
->mode
!= L1_MODE_TRANS
) {
273 bcs
->hw
.hfc
.f1
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
274 cip
= HFC_CIP
| HFC_F2
| HFC_SEND
| HFC_CHANNEL(bcs
->channel
);
276 bcs
->hw
.hfc
.f2
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
277 bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
] = ReadZReg(bcs
, HFC_Z1
| HFC_SEND
| HFC_CHANNEL(bcs
->channel
));
278 if (cs
->debug
& L1_DEB_HSCX
)
279 debugl1(cs
, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
280 bcs
->channel
, bcs
->hw
.hfc
.f1
, bcs
->hw
.hfc
.f2
,
281 bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
]);
282 fcnt
= bcs
->hw
.hfc
.f1
- bcs
->hw
.hfc
.f2
;
286 if (cs
->debug
& L1_DEB_HSCX
)
287 debugl1(cs
, "hfc_fill_fifo more as 30 frames");
288 restore_flags(flags
);
291 count
= GetFreeFifoBytes(bcs
);
295 z1
= ReadZReg(bcs
, HFC_Z1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
296 z2
= ReadZReg(bcs
, HFC_Z2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
299 count
+= cs
->hw
.hfc
.fifosize
;
300 } /* L1_MODE_TRANS */
301 if (cs
->debug
& L1_DEB_HSCX
)
302 debugl1(cs
, "hfc_fill_fifo %d count(%ld/%d)",
303 bcs
->channel
, bcs
->tx_skb
->len
,
305 if (count
< bcs
->tx_skb
->len
) {
306 if (cs
->debug
& L1_DEB_HSCX
)
307 debugl1(cs
, "hfc_fill_fifo no fifo mem");
308 restore_flags(flags
);
311 cip
= HFC_CIP
| HFC_FIFO_IN
| HFC_SEND
| HFC_CHANNEL(bcs
->channel
);
313 while ((idx
< bcs
->tx_skb
->len
) && WaitNoBusy(cs
))
314 cs
->BC_Write_Reg(cs
, HFC_DATA_NODEB
, cip
, bcs
->tx_skb
->data
[idx
++]);
315 if (idx
!= bcs
->tx_skb
->len
) {
316 debugl1(cs
, "FIFO Send BUSY error");
317 printk(KERN_WARNING
"HFC S FIFO channel %d BUSY Error\n", bcs
->channel
);
319 count
= bcs
->tx_skb
->len
;
320 bcs
->tx_cnt
-= count
;
321 if (PACKET_NOACK
== bcs
->tx_skb
->pkt_type
)
323 dev_kfree_skb_any(bcs
->tx_skb
);
325 if (bcs
->mode
!= L1_MODE_TRANS
) {
328 cs
->BC_Read_Reg(cs
, HFC_DATA
, HFC_CIP
| HFC_F1_INC
| HFC_SEND
| HFC_CHANNEL(bcs
->channel
));
330 if (bcs
->st
->lli
.l1writewakeup
&& (count
>= 0))
331 bcs
->st
->lli
.l1writewakeup(bcs
->st
, count
);
332 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
334 restore_flags(flags
);
339 main_irq_hfc(struct BCState
*bcs
)
342 struct IsdnCardState
*cs
= bcs
->cs
;
345 int receive
, transmit
, count
= 5;
352 cip
= HFC_CIP
| HFC_F1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
353 if ((cip
& 0xc3) != (cs
->hw
.hfc
.cip
& 0xc3)) {
354 cs
->BC_Write_Reg(cs
, HFC_STATUS
, cip
, cip
);
359 if (bcs
->mode
== L1_MODE_HDLC
) {
360 f1
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
361 cip
= HFC_CIP
| HFC_F2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
);
363 f2
= cs
->BC_Read_Reg(cs
, HFC_DATA
, cip
);
365 if (cs
->debug
& L1_DEB_HSCX
)
366 debugl1(cs
, "hfc rec %d f1(%d) f2(%d)",
367 bcs
->channel
, f1
, f2
);
371 if (receive
|| (bcs
->mode
== L1_MODE_TRANS
)) {
373 z1
= ReadZReg(bcs
, HFC_Z1
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
374 z2
= ReadZReg(bcs
, HFC_Z2
| HFC_REC
| HFC_CHANNEL(bcs
->channel
));
377 rcnt
+= cs
->hw
.hfc
.fifosize
;
378 if ((bcs
->mode
== L1_MODE_HDLC
) || (rcnt
)) {
380 if (cs
->debug
& L1_DEB_HSCX
)
381 debugl1(cs
, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
382 bcs
->channel
, z1
, z2
, rcnt
);
384 if ((skb
= hfc_empty_fifo(bcs
, rcnt
))) {
385 skb_queue_tail(&bcs
->rqueue
, skb
);
386 hfc_sched_event(bcs
, B_RCVBUFREADY
);
391 restore_flags(flags
);
396 test_and_set_bit(BC_FLG_BUSY
, &bcs
->Flag
);
398 if (test_bit(BC_FLG_BUSY
, &bcs
->Flag
))
401 if ((bcs
->tx_skb
= skb_dequeue(&bcs
->squeue
))) {
403 test_and_set_bit(BC_FLG_BUSY
, &bcs
->Flag
);
405 if (test_bit(BC_FLG_BUSY
, &bcs
->Flag
))
409 hfc_sched_event(bcs
, B_XMTBUFREADY
);
412 restore_flags(flags
);
413 if ((receive
|| transmit
) && count
)
419 mode_hfc(struct BCState
*bcs
, int mode
, int bc
)
421 struct IsdnCardState
*cs
= bcs
->cs
;
423 if (cs
->debug
& L1_DEB_HSCX
)
424 debugl1(cs
, "HFC 2BS0 mode %d bchan %d/%d",
425 mode
, bc
, bcs
->channel
);
432 cs
->hw
.hfc
.ctmt
&= ~1;
433 cs
->hw
.hfc
.isac_spcr
&= ~0x03;
436 cs
->hw
.hfc
.ctmt
&= ~2;
437 cs
->hw
.hfc
.isac_spcr
&= ~0x0c;
440 case (L1_MODE_TRANS
):
441 cs
->hw
.hfc
.ctmt
&= ~(1 << bc
); /* set HDLC mode */
442 cs
->BC_Write_Reg(cs
, HFC_STATUS
, cs
->hw
.hfc
.ctmt
, cs
->hw
.hfc
.ctmt
);
443 hfc_clear_fifo(bcs
); /* complete fifo clear */
445 cs
->hw
.hfc
.ctmt
|= 1;
446 cs
->hw
.hfc
.isac_spcr
&= ~0x03;
447 cs
->hw
.hfc
.isac_spcr
|= 0x02;
449 cs
->hw
.hfc
.ctmt
|= 2;
450 cs
->hw
.hfc
.isac_spcr
&= ~0x0c;
451 cs
->hw
.hfc
.isac_spcr
|= 0x08;
456 cs
->hw
.hfc
.ctmt
&= ~1;
457 cs
->hw
.hfc
.isac_spcr
&= ~0x03;
458 cs
->hw
.hfc
.isac_spcr
|= 0x02;
460 cs
->hw
.hfc
.ctmt
&= ~2;
461 cs
->hw
.hfc
.isac_spcr
&= ~0x0c;
462 cs
->hw
.hfc
.isac_spcr
|= 0x08;
466 cs
->BC_Write_Reg(cs
, HFC_STATUS
, cs
->hw
.hfc
.ctmt
, cs
->hw
.hfc
.ctmt
);
467 cs
->writeisac(cs
, ISAC_SPCR
, cs
->hw
.hfc
.isac_spcr
);
468 if (mode
== L1_MODE_HDLC
)
473 hfc_l2l1(struct PStack
*st
, int pr
, void *arg
)
475 struct sk_buff
*skb
= arg
;
479 case (PH_DATA
| REQUEST
):
482 if (st
->l1
.bcs
->tx_skb
) {
483 skb_queue_tail(&st
->l1
.bcs
->squeue
, skb
);
484 restore_flags(flags
);
486 st
->l1
.bcs
->tx_skb
= skb
;
487 test_and_set_bit(BC_FLG_BUSY
, &st
->l1
.bcs
->Flag
);
488 st
->l1
.bcs
->cs
->BC_Send_Data(st
->l1
.bcs
);
489 restore_flags(flags
);
492 case (PH_PULL
| INDICATION
):
493 if (st
->l1
.bcs
->tx_skb
) {
494 printk(KERN_WARNING
"hfc_l2l1: this shouldn't happen\n");
499 test_and_set_bit(BC_FLG_BUSY
, &st
->l1
.bcs
->Flag
);
500 st
->l1
.bcs
->tx_skb
= skb
;
501 st
->l1
.bcs
->cs
->BC_Send_Data(st
->l1
.bcs
);
502 restore_flags(flags
);
504 case (PH_PULL
| REQUEST
):
505 if (!st
->l1
.bcs
->tx_skb
) {
506 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
507 st
->l1
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
509 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
511 case (PH_ACTIVATE
| REQUEST
):
512 test_and_set_bit(BC_FLG_ACTIV
, &st
->l1
.bcs
->Flag
);
513 mode_hfc(st
->l1
.bcs
, st
->l1
.mode
, st
->l1
.bc
);
514 l1_msg_b(st
, pr
, arg
);
516 case (PH_DEACTIVATE
| REQUEST
):
517 l1_msg_b(st
, pr
, arg
);
519 case (PH_DEACTIVATE
| CONFIRM
):
520 test_and_clear_bit(BC_FLG_ACTIV
, &st
->l1
.bcs
->Flag
);
521 test_and_clear_bit(BC_FLG_BUSY
, &st
->l1
.bcs
->Flag
);
522 mode_hfc(st
->l1
.bcs
, 0, st
->l1
.bc
);
523 st
->l1
.l1l2(st
, PH_DEACTIVATE
| CONFIRM
, NULL
);
530 close_hfcstate(struct BCState
*bcs
)
532 mode_hfc(bcs
, 0, bcs
->channel
);
533 if (test_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
534 discard_queue(&bcs
->rqueue
);
535 discard_queue(&bcs
->squeue
);
537 dev_kfree_skb_any(bcs
->tx_skb
);
539 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
542 test_and_clear_bit(BC_FLG_INIT
, &bcs
->Flag
);
546 open_hfcstate(struct IsdnCardState
*cs
, struct BCState
*bcs
)
548 if (!test_and_set_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
549 skb_queue_head_init(&bcs
->rqueue
);
550 skb_queue_head_init(&bcs
->squeue
);
553 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
560 setstack_hfc(struct PStack
*st
, struct BCState
*bcs
)
562 bcs
->channel
= st
->l1
.bc
;
563 if (open_hfcstate(st
->l1
.hardware
, bcs
))
566 st
->l2
.l2l1
= hfc_l2l1
;
567 setstack_manager(st
);
574 init_send(struct BCState
*bcs
))
578 if (!(bcs
->hw
.hfc
.send
= kmalloc(32 * sizeof(unsigned int), GFP_ATOMIC
))) {
580 "HiSax: No memory for hfc.send\n");
583 for (i
= 0; i
< 32; i
++)
584 bcs
->hw
.hfc
.send
[i
] = 0x1fff;
588 inithfc(struct IsdnCardState
*cs
))
590 init_send(&cs
->bcs
[0]);
591 init_send(&cs
->bcs
[1]);
592 cs
->BC_Send_Data
= &hfc_fill_fifo
;
593 cs
->bcs
[0].BC_SetStack
= setstack_hfc
;
594 cs
->bcs
[1].BC_SetStack
= setstack_hfc
;
595 cs
->bcs
[0].BC_Close
= close_hfcstate
;
596 cs
->bcs
[1].BC_Close
= close_hfcstate
;
597 mode_hfc(cs
->bcs
, 0, 0);
598 mode_hfc(cs
->bcs
+ 1, 0, 0);
602 releasehfc(struct IsdnCardState
*cs
)
604 if (cs
->bcs
[0].hw
.hfc
.send
) {
605 kfree(cs
->bcs
[0].hw
.hfc
.send
);
606 cs
->bcs
[0].hw
.hfc
.send
= NULL
;
608 if (cs
->bcs
[1].hw
.hfc
.send
) {
609 kfree(cs
->bcs
[1].hw
.hfc
.send
);
610 cs
->bcs
[1].hw
.hfc
.send
= NULL
;