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Merge with Linux 2.5.74.
[linux-2.6/linux-mips.git] / drivers / pci / hotplug / ibmphp_hpc.c
blobb95264f62420439d3436dc1f11223bab7074807b
1 /*
2 * IBM Hot Plug Controller Driver
3 *
4 * Written By: Jyoti Shah, IBM Corporation
5 *
6 * Copyright (c) 2001-2003 IBM Corp.
7 *
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
18 * NON INFRINGEMENT. See the GNU General Public License for more
19 * details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Send feedback to <gregkh@us.ibm.com>
26 * <jshah@us.ibm.com>
27 *
28 */
29
30 #include <linux/wait.h>
31 #include <linux/time.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/smp_lock.h>
35 #include <linux/init.h>
36 #include "ibmphp.h"
37
38 static int to_debug = FALSE;
39 #define debug_polling(fmt, arg...) do { if (to_debug) debug (fmt, arg); } while (0)
40
41 //----------------------------------------------------------------------------
42 // timeout values
43 //----------------------------------------------------------------------------
44 #define CMD_COMPLETE_TOUT_SEC 60 // give HPC 60 sec to finish cmd
45 #define HPC_CTLR_WORKING_TOUT 60 // give HPC 60 sec to finish cmd
46 #define HPC_GETACCESS_TIMEOUT 60 // seconds
47 #define POLL_INTERVAL_SEC 2 // poll HPC every 2 seconds
48 #define POLL_LATCH_CNT 5 // poll latch 5 times, then poll slots
49
50 //----------------------------------------------------------------------------
51 // Winnipeg Architected Register Offsets
52 //----------------------------------------------------------------------------
53 #define WPG_I2CMBUFL_OFFSET 0x08 // I2C Message Buffer Low
54 #define WPG_I2CMOSUP_OFFSET 0x10 // I2C Master Operation Setup Reg
55 #define WPG_I2CMCNTL_OFFSET 0x20 // I2C Master Control Register
56 #define WPG_I2CPARM_OFFSET 0x40 // I2C Parameter Register
57 #define WPG_I2CSTAT_OFFSET 0x70 // I2C Status Register
58
59 //----------------------------------------------------------------------------
60 // Winnipeg Store Type commands (Add this commands to the register offset)
61 //----------------------------------------------------------------------------
62 #define WPG_I2C_AND 0x1000 // I2C AND operation
63 #define WPG_I2C_OR 0x2000 // I2C OR operation
64
65 //----------------------------------------------------------------------------
66 // Command set for I2C Master Operation Setup Regisetr
67 //----------------------------------------------------------------------------
68 #define WPG_READATADDR_MASK 0x00010000 // read,bytes,I2C shifted,index
69 #define WPG_WRITEATADDR_MASK 0x40010000 // write,bytes,I2C shifted,index
70 #define WPG_READDIRECT_MASK 0x10010000
71 #define WPG_WRITEDIRECT_MASK 0x60010000
72
73
74 //----------------------------------------------------------------------------
75 // bit masks for I2C Master Control Register
76 //----------------------------------------------------------------------------
77 #define WPG_I2CMCNTL_STARTOP_MASK 0x00000002 // Start the Operation
78
79 //----------------------------------------------------------------------------
80 //
81 //----------------------------------------------------------------------------
82 #define WPG_I2C_IOREMAP_SIZE 0x2044 // size of linear address interval
83
84 //----------------------------------------------------------------------------
85 // command index
86 //----------------------------------------------------------------------------
87 #define WPG_1ST_SLOT_INDEX 0x01 // index - 1st slot for ctlr
88 #define WPG_CTLR_INDEX 0x0F // index - ctlr
89 #define WPG_1ST_EXTSLOT_INDEX 0x10 // index - 1st ext slot for ctlr
90 #define WPG_1ST_BUS_INDEX 0x1F // index - 1st bus for ctlr
91
92 //----------------------------------------------------------------------------
93 // macro utilities
94 //----------------------------------------------------------------------------
95 // if bits 20,22,25,26,27,29,30 are OFF return TRUE
96 #define HPC_I2CSTATUS_CHECK(s) ((u8)((s & 0x00000A76) ? FALSE : TRUE))
97
98 //----------------------------------------------------------------------------
99 // global variables
100 //----------------------------------------------------------------------------
101 static int ibmphp_shutdown;
102 static int tid_poll;
103 static struct semaphore sem_hpcaccess; // lock access to HPC
104 static struct semaphore semOperations; // lock all operations and
105 // access to data structures
106 static struct semaphore sem_exit; // make sure polling thread goes away
107 //----------------------------------------------------------------------------
108 // local function prototypes
109 //----------------------------------------------------------------------------
110 static u8 i2c_ctrl_read (struct controller *, void *, u8);
111 static u8 i2c_ctrl_write (struct controller *, void *, u8, u8);
112 static u8 hpc_writecmdtoindex (u8, u8);
113 static u8 hpc_readcmdtoindex (u8, u8);
114 static void get_hpc_access (void);
115 static void free_hpc_access (void);
116 static void poll_hpc (void);
117 static int process_changeinstatus (struct slot *, struct slot *);
118 static int process_changeinlatch (u8, u8, struct controller *);
119 static int hpc_poll_thread (void *);
120 static int hpc_wait_ctlr_notworking (int, struct controller *, void *, u8 *);
121 //----------------------------------------------------------------------------
122
123
124 /*----------------------------------------------------------------------
125 * Name: ibmphp_hpc_initvars
126 *
127 * Action: initialize semaphores and variables
128 *---------------------------------------------------------------------*/
129 void __init ibmphp_hpc_initvars (void)
130 {
131 debug ("%s - Entry\n", __FUNCTION__);
132
133 init_MUTEX (&sem_hpcaccess);
134 init_MUTEX (&semOperations);
135 init_MUTEX_LOCKED (&sem_exit);
136 to_debug = FALSE;
137 ibmphp_shutdown = FALSE;
138 tid_poll = 0;
139
140 debug ("%s - Exit\n", __FUNCTION__);
141 }
142
143 /*----------------------------------------------------------------------
144 * Name: i2c_ctrl_read
145 *
146 * Action: read from HPC over I2C
147 *
148 *---------------------------------------------------------------------*/
149 static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void *WPGBbar, u8 index)
150 {
151 u8 status;
152 int i;
153 void *wpg_addr; // base addr + offset
154 unsigned long wpg_data; // data to/from WPG LOHI format
155 unsigned long ultemp;
156 unsigned long data; // actual data HILO format
157
158 debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __FUNCTION__, WPGBbar, index);
159
160 //--------------------------------------------------------------------
161 // READ - step 1
162 // read at address, byte length, I2C address (shifted), index
163 // or read direct, byte length, index
164 if (ctlr_ptr->ctlr_type == 0x02) {
165 data = WPG_READATADDR_MASK;
166 // fill in I2C address
167 ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr;
168 ultemp = ultemp >> 1;
169 data |= (ultemp << 8);
170
171 // fill in index
172 data |= (unsigned long)index;
173 } else if (ctlr_ptr->ctlr_type == 0x04) {
174 data = WPG_READDIRECT_MASK;
175
176 // fill in index
177 ultemp = (unsigned long)index;
178 ultemp = ultemp << 8;
179 data |= ultemp;
180 } else {
181 err ("this controller type is not supported \n");
182 return HPC_ERROR;
183 }
184
185 wpg_data = swab32 (data); // swap data before writing
186 wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET;
187 writel (wpg_data, wpg_addr);
188
189 //--------------------------------------------------------------------
190 // READ - step 2 : clear the message buffer
191 data = 0x00000000;
192 wpg_data = swab32 (data);
193 wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
194 writel (wpg_data, wpg_addr);
195
196 //--------------------------------------------------------------------
197 // READ - step 3 : issue start operation, I2C master control bit 30:ON
198 // 2020 : [20] OR operation at [20] offset 0x20
199 data = WPG_I2CMCNTL_STARTOP_MASK;
200 wpg_data = swab32 (data);
201 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR;
202 writel (wpg_data, wpg_addr);
203
204 //--------------------------------------------------------------------
205 // READ - step 4 : wait until start operation bit clears
206 i = CMD_COMPLETE_TOUT_SEC;
207 while (i) {
208 long_delay (1 * HZ / 100);
209 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET;
210 wpg_data = readl (wpg_addr);
211 data = swab32 (wpg_data);
212 if (!(data & WPG_I2CMCNTL_STARTOP_MASK))
213 break;
214 i--;
215 }
216 if (i == 0) {
217 debug ("%s - Error : WPG timeout\n", __FUNCTION__);
218 return HPC_ERROR;
219 }
220 //--------------------------------------------------------------------
221 // READ - step 5 : read I2C status register
222 i = CMD_COMPLETE_TOUT_SEC;
223 while (i) {
224 long_delay (1 * HZ / 100);
225 wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET;
226 wpg_data = readl (wpg_addr);
227 data = swab32 (wpg_data);
228 if (HPC_I2CSTATUS_CHECK (data))
229 break;
230 i--;
231 }
232 if (i == 0) {
233 debug ("ctrl_read - Exit Error:I2C timeout\n");
234 return HPC_ERROR;
235 }
236
237 //--------------------------------------------------------------------
238 // READ - step 6 : get DATA
239 wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
240 wpg_data = readl (wpg_addr);
241 data = swab32 (wpg_data);
242
243 status = (u8) data;
244
245 debug_polling ("%s - Exit index[%x] status[%x]\n", __FUNCTION__, index, status);
246
247 return (status);
248 }
249
250 /*----------------------------------------------------------------------
251 * Name: i2c_ctrl_write
252 *
253 * Action: write to HPC over I2C
254 *
255 * Return 0 or error codes
256 *---------------------------------------------------------------------*/
257 static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void *WPGBbar, u8 index, u8 cmd)
258 {
259 u8 rc;
260 void *wpg_addr; // base addr + offset
261 unsigned long wpg_data; // data to/from WPG LOHI format
262 unsigned long ultemp;
263 unsigned long data; // actual data HILO format
264 int i;
265
266 debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __FUNCTION__, WPGBbar, index, cmd);
267
268 rc = 0;
269 //--------------------------------------------------------------------
270 // WRITE - step 1
271 // write at address, byte length, I2C address (shifted), index
272 // or write direct, byte length, index
273 data = 0x00000000;
274
275 if (ctlr_ptr->ctlr_type == 0x02) {
276 data = WPG_WRITEATADDR_MASK;
277 // fill in I2C address
278 ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr;
279 ultemp = ultemp >> 1;
280 data |= (ultemp << 8);
281
282 // fill in index
283 data |= (unsigned long)index;
284 } else if (ctlr_ptr->ctlr_type == 0x04) {
285 data = WPG_WRITEDIRECT_MASK;
286
287 // fill in index
288 ultemp = (unsigned long)index;
289 ultemp = ultemp << 8;
290 data |= ultemp;
291 } else {
292 err ("this controller type is not supported \n");
293 return HPC_ERROR;
294 }
295
296 wpg_data = swab32 (data); // swap data before writing
297 wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET;
298 writel (wpg_data, wpg_addr);
299
300 //--------------------------------------------------------------------
301 // WRITE - step 2 : clear the message buffer
302 data = 0x00000000 | (unsigned long)cmd;
303 wpg_data = swab32 (data);
304 wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
305 writel (wpg_data, wpg_addr);
306
307 //--------------------------------------------------------------------
308 // WRITE - step 3 : issue start operation,I2C master control bit 30:ON
309 // 2020 : [20] OR operation at [20] offset 0x20
310 data = WPG_I2CMCNTL_STARTOP_MASK;
311 wpg_data = swab32 (data);
312 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR;
313 writel (wpg_data, wpg_addr);
314
315 //--------------------------------------------------------------------
316 // WRITE - step 4 : wait until start operation bit clears
317 i = CMD_COMPLETE_TOUT_SEC;
318 while (i) {
319 long_delay (1 * HZ / 100);
320 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET;
321 wpg_data = readl (wpg_addr);
322 data = swab32 (wpg_data);
323 if (!(data & WPG_I2CMCNTL_STARTOP_MASK))
324 break;
325 i--;
326 }
327 if (i == 0) {
328 debug ("%s - Exit Error:WPG timeout\n", __FUNCTION__);
329 rc = HPC_ERROR;
330 }
331
332 //--------------------------------------------------------------------
333 // WRITE - step 5 : read I2C status register
334 i = CMD_COMPLETE_TOUT_SEC;
335 while (i) {
336 long_delay (1 * HZ / 100);
337 wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET;
338 wpg_data = readl (wpg_addr);
339 data = swab32 (wpg_data);
340 if (HPC_I2CSTATUS_CHECK (data))
341 break;
342 i--;
343 }
344 if (i == 0) {
345 debug ("ctrl_read - Error : I2C timeout\n");
346 rc = HPC_ERROR;
347 }
348
349 debug_polling ("%s Exit rc[%x]\n", __FUNCTION__, rc);
350 return (rc);
351 }
352
353 //------------------------------------------------------------
354 // Read from ISA type HPC
355 //------------------------------------------------------------
356 static u8 isa_ctrl_read (struct controller *ctlr_ptr, u8 offset)
357 {
358 u16 start_address;
359 u16 end_address;
360 u8 data;
361
362 start_address = ctlr_ptr->u.isa_ctlr.io_start;
363 end_address = ctlr_ptr->u.isa_ctlr.io_end;
364 data = inb (start_address + offset);
365 return data;
366 }
367
368 //--------------------------------------------------------------
369 // Write to ISA type HPC
370 //--------------------------------------------------------------
371 static void isa_ctrl_write (struct controller *ctlr_ptr, u8 offset, u8 data)
372 {
373 u16 start_address;
374 u16 port_address;
375
376 start_address = ctlr_ptr->u.isa_ctlr.io_start;
377 port_address = start_address + (u16) offset;
378 outb (data, port_address);
379 }
380
381 static u8 pci_ctrl_read (struct controller *ctrl, u8 offset)
382 {
383 u8 data = 0x00;
384 debug ("inside pci_ctrl_read\n");
385 if (ctrl->ctrl_dev)
386 pci_read_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, &data);
387 return data;
388 }
389
390 static u8 pci_ctrl_write (struct controller *ctrl, u8 offset, u8 data)
391 {
392 u8 rc = -ENODEV;
393 debug ("inside pci_ctrl_write\n");
394 if (ctrl->ctrl_dev) {
395 pci_write_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, data);
396 rc = 0;
397 }
398 return rc;
399 }
400
401 static u8 ctrl_read (struct controller *ctlr, void *base, u8 offset)
402 {
403 u8 rc;
404 switch (ctlr->ctlr_type) {
405 case 0:
406 rc = isa_ctrl_read (ctlr, offset);
407 break;
408 case 1:
409 rc = pci_ctrl_read (ctlr, offset);
410 break;
411 case 2:
412 case 4:
413 rc = i2c_ctrl_read (ctlr, base, offset);
414 break;
415 default:
416 return -ENODEV;
417 }
418 return rc;
419 }
420
421 static u8 ctrl_write (struct controller *ctlr, void *base, u8 offset, u8 data)
422 {
423 u8 rc = 0;
424 switch (ctlr->ctlr_type) {
425 case 0:
426 isa_ctrl_write(ctlr, offset, data);
427 break;
428 case 1:
429 rc = pci_ctrl_write (ctlr, offset, data);
430 break;
431 case 2:
432 case 4:
433 rc = i2c_ctrl_write(ctlr, base, offset, data);
434 break;
435 default:
436 return -ENODEV;
437 }
438 return rc;
439 }
440 /*----------------------------------------------------------------------
441 * Name: hpc_writecmdtoindex()
442 *
443 * Action: convert a write command to proper index within a controller
444 *
445 * Return index, HPC_ERROR
446 *---------------------------------------------------------------------*/
447 static u8 hpc_writecmdtoindex (u8 cmd, u8 index)
448 {
449 u8 rc;
450
451 switch (cmd) {
452 case HPC_CTLR_ENABLEIRQ: // 0x00.N.15
453 case HPC_CTLR_CLEARIRQ: // 0x06.N.15
454 case HPC_CTLR_RESET: // 0x07.N.15
455 case HPC_CTLR_IRQSTEER: // 0x08.N.15
456 case HPC_CTLR_DISABLEIRQ: // 0x01.N.15
457 case HPC_ALLSLOT_ON: // 0x11.N.15
458 case HPC_ALLSLOT_OFF: // 0x12.N.15
459 rc = 0x0F;
460 break;
461
462 case HPC_SLOT_OFF: // 0x02.Y.0-14
463 case HPC_SLOT_ON: // 0x03.Y.0-14
464 case HPC_SLOT_ATTNOFF: // 0x04.N.0-14
465 case HPC_SLOT_ATTNON: // 0x05.N.0-14
466 case HPC_SLOT_BLINKLED: // 0x13.N.0-14
467 rc = index;
468 break;
469
470 case HPC_BUS_33CONVMODE:
471 case HPC_BUS_66CONVMODE:
472 case HPC_BUS_66PCIXMODE:
473 case HPC_BUS_100PCIXMODE:
474 case HPC_BUS_133PCIXMODE:
475 rc = index + WPG_1ST_BUS_INDEX - 1;
476 break;
477
478 default:
479 err ("hpc_writecmdtoindex - Error invalid cmd[%x]\n", cmd);
480 rc = HPC_ERROR;
481 }
482
483 return rc;
484 }
485
486 /*----------------------------------------------------------------------
487 * Name: hpc_readcmdtoindex()
488 *
489 * Action: convert a read command to proper index within a controller
490 *
491 * Return index, HPC_ERROR
492 *---------------------------------------------------------------------*/
493 static u8 hpc_readcmdtoindex (u8 cmd, u8 index)
494 {
495 u8 rc;
496
497 switch (cmd) {
498 case READ_CTLRSTATUS:
499 rc = 0x0F;
500 break;
501 case READ_SLOTSTATUS:
502 case READ_ALLSTAT:
503 rc = index;
504 break;
505 case READ_EXTSLOTSTATUS:
506 rc = index + WPG_1ST_EXTSLOT_INDEX;
507 break;
508 case READ_BUSSTATUS:
509 rc = index + WPG_1ST_BUS_INDEX - 1;
510 break;
511 case READ_SLOTLATCHLOWREG:
512 rc = 0x28;
513 break;
514 case READ_REVLEVEL:
515 rc = 0x25;
516 break;
517 case READ_HPCOPTIONS:
518 rc = 0x27;
519 break;
520 default:
521 rc = HPC_ERROR;
522 }
523 return rc;
524 }
525
526 /*----------------------------------------------------------------------
527 * Name: HPCreadslot()
528 *
529 * Action: issue a READ command to HPC
530 *
531 * Input: pslot - can not be NULL for READ_ALLSTAT
532 * pstatus - can be NULL for READ_ALLSTAT
533 *
534 * Return 0 or error codes
535 *---------------------------------------------------------------------*/
536 int ibmphp_hpc_readslot (struct slot * pslot, u8 cmd, u8 * pstatus)
537 {
538 void *wpg_bbar = NULL;
539 struct controller *ctlr_ptr;
540 struct list_head *pslotlist;
541 u8 index, status;
542 int rc = 0;
543 int busindex;
544
545 debug_polling ("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __FUNCTION__, pslot, cmd, pstatus);
546
547 if ((pslot == NULL)
548 || ((pstatus == NULL) && (cmd != READ_ALLSTAT) && (cmd != READ_BUSSTATUS))) {
549 rc = -EINVAL;
550 err ("%s - Error invalid pointer, rc[%d]\n", __FUNCTION__, rc);
551 return rc;
552 }
553
554 if (cmd == READ_BUSSTATUS) {
555 busindex = ibmphp_get_bus_index (pslot->bus);
556 if (busindex < 0) {
557 rc = -EINVAL;
558 err ("%s - Exit Error:invalid bus, rc[%d]\n", __FUNCTION__, rc);
559 return rc;
560 } else
561 index = (u8) busindex;
562 } else
563 index = pslot->ctlr_index;
564
565 index = hpc_readcmdtoindex (cmd, index);
566
567 if (index == HPC_ERROR) {
568 rc = -EINVAL;
569 err ("%s - Exit Error:invalid index, rc[%d]\n", __FUNCTION__, rc);
570 return rc;
571 }
572
573 ctlr_ptr = pslot->ctrl;
574
575 get_hpc_access ();
576
577 //--------------------------------------------------------------------
578 // map physical address to logical address
579 //--------------------------------------------------------------------
580 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
581 wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
582
583 //--------------------------------------------------------------------
584 // check controller status before reading
585 //--------------------------------------------------------------------
586 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status);
587 if (!rc) {
588 switch (cmd) {
589 case READ_ALLSTAT:
590 // update the slot structure
591 pslot->ctrl->status = status;
592 pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index);
593 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar,
594 &status);
595 if (!rc)
596 pslot->ext_status = ctrl_read (ctlr_ptr, wpg_bbar, index + WPG_1ST_EXTSLOT_INDEX);
597
598 break;
599
600 case READ_SLOTSTATUS:
601 // DO NOT update the slot structure
602 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
603 break;
604
605 case READ_EXTSLOTSTATUS:
606 // DO NOT update the slot structure
607 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
608 break;
609
610 case READ_CTLRSTATUS:
611 // DO NOT update the slot structure
612 *pstatus = status;
613 break;
614
615 case READ_BUSSTATUS:
616 pslot->busstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
617 break;
618 case READ_REVLEVEL:
619 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
620 break;
621 case READ_HPCOPTIONS:
622 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
623 break;
624 case READ_SLOTLATCHLOWREG:
625 // DO NOT update the slot structure
626 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index);
627 break;
628
629 // Not used
630 case READ_ALLSLOT:
631 list_for_each (pslotlist, &ibmphp_slot_head) {
632 pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
633 index = pslot->ctlr_index;
634 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr,
635 wpg_bbar, &status);
636 if (!rc) {
637 pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index);
638 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT,
639 ctlr_ptr, wpg_bbar, &status);
640 if (!rc)
641 pslot->ext_status =
642 ctrl_read (ctlr_ptr, wpg_bbar,
643 index + WPG_1ST_EXTSLOT_INDEX);
644 } else {
645 err ("%s - Error ctrl_read failed\n", __FUNCTION__);
646 rc = -EINVAL;
647 break;
648 }
649 }
650 break;
651 default:
652 rc = -EINVAL;
653 break;
654 }
655 }
656 //--------------------------------------------------------------------
657 // cleanup
658 //--------------------------------------------------------------------
659
660 // remove physical to logical address mapping
661 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
662 iounmap (wpg_bbar);
663
664 free_hpc_access ();
665
666 debug_polling ("%s - Exit rc[%d]\n", __FUNCTION__, rc);
667 return rc;
668 }
669
670 /*----------------------------------------------------------------------
671 * Name: ibmphp_hpc_writeslot()
672 *
673 * Action: issue a WRITE command to HPC
674 *---------------------------------------------------------------------*/
675 int ibmphp_hpc_writeslot (struct slot * pslot, u8 cmd)
676 {
677 void *wpg_bbar = NULL;
678 struct controller *ctlr_ptr;
679 u8 index, status;
680 int busindex;
681 u8 done;
682 int rc = 0;
683 int timeout;
684
685 debug_polling ("%s - Entry pslot[%p] cmd[%x]\n", __FUNCTION__, pslot, cmd);
686 if (pslot == NULL) {
687 rc = -EINVAL;
688 err ("%s - Error Exit rc[%d]\n", __FUNCTION__, rc);
689 return rc;
690 }
691
692 if ((cmd == HPC_BUS_33CONVMODE) || (cmd == HPC_BUS_66CONVMODE) ||
693 (cmd == HPC_BUS_66PCIXMODE) || (cmd == HPC_BUS_100PCIXMODE) ||
694 (cmd == HPC_BUS_133PCIXMODE)) {
695 busindex = ibmphp_get_bus_index (pslot->bus);
696 if (busindex < 0) {
697 rc = -EINVAL;
698 err ("%s - Exit Error:invalid bus, rc[%d]\n", __FUNCTION__, rc);
699 return rc;
700 } else
701 index = (u8) busindex;
702 } else
703 index = pslot->ctlr_index;
704
705 index = hpc_writecmdtoindex (cmd, index);
706
707 if (index == HPC_ERROR) {
708 rc = -EINVAL;
709 err ("%s - Error Exit rc[%d]\n", __FUNCTION__, rc);
710 return rc;
711 }
712
713 ctlr_ptr = pslot->ctrl;
714
715 get_hpc_access ();
716
717 //--------------------------------------------------------------------
718 // map physical address to logical address
719 //--------------------------------------------------------------------
720 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) {
721 wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
722
723 debug ("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __FUNCTION__,
724 ctlr_ptr->ctlr_id, (ulong) (ctlr_ptr->u.wpeg_ctlr.wpegbbar), (ulong) wpg_bbar,
725 ctlr_ptr->u.wpeg_ctlr.i2c_addr);
726 }
727 //--------------------------------------------------------------------
728 // check controller status before writing
729 //--------------------------------------------------------------------
730 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status);
731 if (!rc) {
732
733 ctrl_write (ctlr_ptr, wpg_bbar, index, cmd);
734
735 //--------------------------------------------------------------------
736 // check controller is still not working on the command
737 //--------------------------------------------------------------------
738 timeout = CMD_COMPLETE_TOUT_SEC;
739 done = FALSE;
740 while (!done) {
741 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar,
742 &status);
743 if (!rc) {
744 if (NEEDTOCHECK_CMDSTATUS (cmd)) {
745 if (CTLR_FINISHED (status) == HPC_CTLR_FINISHED_YES)
746 done = TRUE;
747 } else
748 done = TRUE;
749 }
750 if (!done) {
751 long_delay (1 * HZ);
752 if (timeout < 1) {
753 done = TRUE;
754 err ("%s - Error command complete timeout\n", __FUNCTION__);
755 rc = -EFAULT;
756 } else
757 timeout--;
758 }
759 }
760 ctlr_ptr->status = status;
761 }
762 // cleanup
763
764 // remove physical to logical address mapping
765 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
766 iounmap (wpg_bbar);
767 free_hpc_access ();
768
769 debug_polling ("%s - Exit rc[%d]\n", __FUNCTION__, rc);
770 return rc;
771 }
772
773 /*----------------------------------------------------------------------
774 * Name: get_hpc_access()
775 *
776 * Action: make sure only one process can access HPC at one time
777 *---------------------------------------------------------------------*/
778 static void get_hpc_access (void)
779 {
780 down (&sem_hpcaccess);
781 }
782
783 /*----------------------------------------------------------------------
784 * Name: free_hpc_access()
785 *---------------------------------------------------------------------*/
786 void free_hpc_access (void)
787 {
788 up (&sem_hpcaccess);
789 }
790
791 /*----------------------------------------------------------------------
792 * Name: ibmphp_lock_operations()
793 *
794 * Action: make sure only one process can change the data structure
795 *---------------------------------------------------------------------*/
796 void ibmphp_lock_operations (void)
797 {
798 down (&semOperations);
799 to_debug = TRUE;
800 }
801
802 /*----------------------------------------------------------------------
803 * Name: ibmphp_unlock_operations()
804 *---------------------------------------------------------------------*/
805 void ibmphp_unlock_operations (void)
806 {
807 debug ("%s - Entry\n", __FUNCTION__);
808 up (&semOperations);
809 to_debug = FALSE;
810 debug ("%s - Exit\n", __FUNCTION__);
811 }
812
813 /*----------------------------------------------------------------------
814 * Name: poll_hpc()
815 *---------------------------------------------------------------------*/
816 #define POLL_LATCH_REGISTER 0
817 #define POLL_SLOTS 1
818 #define POLL_SLEEP 2
819 static void poll_hpc (void)
820 {
821 struct slot myslot;
822 struct slot *pslot = NULL;
823 struct list_head *pslotlist;
824 int rc;
825 int poll_state = POLL_LATCH_REGISTER;
826 u8 oldlatchlow = 0x00;
827 u8 curlatchlow = 0x00;
828 int poll_count = 0;
829 u8 ctrl_count = 0x00;
830
831 debug ("%s - Entry\n", __FUNCTION__);
832
833 while (!ibmphp_shutdown) {
834 if (ibmphp_shutdown)
835 break;
836
837 /* try to get the lock to do some kind of harware access */
838 down (&semOperations);
839
840 switch (poll_state) {
841 case POLL_LATCH_REGISTER:
842 oldlatchlow = curlatchlow;
843 ctrl_count = 0x00;
844 list_for_each (pslotlist, &ibmphp_slot_head) {
845 if (ctrl_count >= ibmphp_get_total_controllers())
846 break;
847 pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
848 if (pslot->ctrl->ctlr_relative_id == ctrl_count) {
849 ctrl_count++;
850 if (READ_SLOT_LATCH (pslot->ctrl)) {
851 rc = ibmphp_hpc_readslot (pslot,
852 READ_SLOTLATCHLOWREG,
853 &curlatchlow);
854 if (oldlatchlow != curlatchlow)
855 process_changeinlatch (oldlatchlow,
856 curlatchlow,
857 pslot->ctrl);
858 }
859 }
860 }
861 ++poll_count;
862 poll_state = POLL_SLEEP;
863 break;
864 case POLL_SLOTS:
865 list_for_each (pslotlist, &ibmphp_slot_head) {
866 pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
867 // make a copy of the old status
868 memcpy ((void *) &myslot, (void *) pslot,
869 sizeof (struct slot));
870 rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL);
871 if ((myslot.status != pslot->status)
872 || (myslot.ext_status != pslot->ext_status))
873 process_changeinstatus (pslot, &myslot);
874 }
875 ctrl_count = 0x00;
876 list_for_each (pslotlist, &ibmphp_slot_head) {
877 if (ctrl_count >= ibmphp_get_total_controllers())
878 break;
879 pslot = list_entry (pslotlist, struct slot, ibm_slot_list);
880 if (pslot->ctrl->ctlr_relative_id == ctrl_count) {
881 ctrl_count++;
882 if (READ_SLOT_LATCH (pslot->ctrl))
883 rc = ibmphp_hpc_readslot (pslot,
884 READ_SLOTLATCHLOWREG,
885 &curlatchlow);
886 }
887 }
888 ++poll_count;
889 poll_state = POLL_SLEEP;
890 break;
891 case POLL_SLEEP:
892 /* don't sleep with a lock on the hardware */
893 up (&semOperations);
894 long_delay (POLL_INTERVAL_SEC * HZ);
895
896 if (ibmphp_shutdown)
897 break;
898
899 down (&semOperations);
900
901 if (poll_count >= POLL_LATCH_CNT) {
902 poll_count = 0;
903 poll_state = POLL_SLOTS;
904 } else
905 poll_state = POLL_LATCH_REGISTER;
906 break;
907 }
908 /* give up the harware semaphore */
909 up (&semOperations);
910 /* sleep for a short time just for good measure */
911 set_current_state (TASK_INTERRUPTIBLE);
912 schedule_timeout (HZ/10);
913 }
914 up (&sem_exit);
915 debug ("%s - Exit\n", __FUNCTION__);
916 }
917
918
919 /*----------------------------------------------------------------------
920 * Name: process_changeinstatus
921 *
922 * Action: compare old and new slot status, process the change in status
923 *
924 * Input: pointer to slot struct, old slot struct
925 *
926 * Return 0 or error codes
927 * Value:
928 *
929 * Side
930 * Effects: None.
931 *
932 * Notes:
933 *---------------------------------------------------------------------*/
934 static int process_changeinstatus (struct slot *pslot, struct slot *poldslot)
935 {
936 u8 status;
937 int rc = 0;
938 u8 disable = FALSE;
939 u8 update = FALSE;
940
941 debug ("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot, poldslot);
942
943 // bit 0 - HPC_SLOT_POWER
944 if ((pslot->status & 0x01) != (poldslot->status & 0x01))
945 update = TRUE;
946
947 // bit 1 - HPC_SLOT_CONNECT
948 // ignore
949
950 // bit 2 - HPC_SLOT_ATTN
951 if ((pslot->status & 0x04) != (poldslot->status & 0x04))
952 update = TRUE;
953
954 // bit 3 - HPC_SLOT_PRSNT2
955 // bit 4 - HPC_SLOT_PRSNT1
956 if (((pslot->status & 0x08) != (poldslot->status & 0x08))
957 || ((pslot->status & 0x10) != (poldslot->status & 0x10)))
958 update = TRUE;
959
960 // bit 5 - HPC_SLOT_PWRGD
961 if ((pslot->status & 0x20) != (poldslot->status & 0x20))
962 // OFF -> ON: ignore, ON -> OFF: disable slot
963 if ((poldslot->status & 0x20) && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status)))
964 disable = TRUE;
965
966 // bit 6 - HPC_SLOT_BUS_SPEED
967 // ignore
968
969 // bit 7 - HPC_SLOT_LATCH
970 if ((pslot->status & 0x80) != (poldslot->status & 0x80)) {
971 update = TRUE;
972 // OPEN -> CLOSE
973 if (pslot->status & 0x80) {
974 if (SLOT_PWRGD (pslot->status)) {
975 // power goes on and off after closing latch
976 // check again to make sure power is still ON
977 long_delay (1 * HZ);
978 rc = ibmphp_hpc_readslot (pslot, READ_SLOTSTATUS, &status);
979 if (SLOT_PWRGD (status))
980 update = TRUE;
981 else // overwrite power in pslot to OFF
982 pslot->status &= ~HPC_SLOT_POWER;
983 }
984 }
985 // CLOSE -> OPEN
986 else if ((SLOT_PWRGD (poldslot->status) == HPC_SLOT_PWRGD_GOOD)
987 && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) {
988 disable = TRUE;
989 }
990 // else - ignore
991 }
992 // bit 4 - HPC_SLOT_BLINK_ATTN
993 if ((pslot->ext_status & 0x08) != (poldslot->ext_status & 0x08))
994 update = TRUE;
995
996 if (disable) {
997 debug ("process_changeinstatus - disable slot\n");
998 pslot->flag = FALSE;
999 rc = ibmphp_do_disable_slot (pslot);
1000 }
1001
1002 if (update || disable) {
1003 ibmphp_update_slot_info (pslot);
1004 }
1005
1006 debug ("%s - Exit rc[%d] disable[%x] update[%x]\n", __FUNCTION__, rc, disable, update);
1007
1008 return rc;
1009 }
1010
1011 /*----------------------------------------------------------------------
1012 * Name: process_changeinlatch
1013 *
1014 * Action: compare old and new latch reg status, process the change
1015 *
1016 * Input: old and current latch register status
1017 *
1018 * Return 0 or error codes
1019 * Value:
1020 *---------------------------------------------------------------------*/
1021 static int process_changeinlatch (u8 old, u8 new, struct controller *ctrl)
1022 {
1023 struct slot myslot, *pslot;
1024 u8 i;
1025 u8 mask;
1026 int rc = 0;
1027
1028 debug ("%s - Entry old[%x], new[%x]\n", __FUNCTION__, old, new);
1029 // bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots
1030
1031 for (i = ctrl->starting_slot_num; i <= ctrl->ending_slot_num; i++) {
1032 mask = 0x01 << i;
1033 if ((mask & old) != (mask & new)) {
1034 pslot = ibmphp_get_slot_from_physical_num (i);
1035 if (pslot) {
1036 memcpy ((void *) &myslot, (void *) pslot, sizeof (struct slot));
1037 rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL);
1038 debug ("%s - call process_changeinstatus for slot[%d]\n", __FUNCTION__, i);
1039 process_changeinstatus (pslot, &myslot);
1040 } else {
1041 rc = -EINVAL;
1042 err ("%s - Error bad pointer for slot[%d]\n", __FUNCTION__, i);
1043 }
1044 }
1045 }
1046 debug ("%s - Exit rc[%d]\n", __FUNCTION__, rc);
1047 return rc;
1048 }
1049
1050 /*----------------------------------------------------------------------
1051 * Name: hpc_poll_thread
1052 *
1053 * Action: polling
1054 *
1055 * Return 0
1056 * Value:
1057 *---------------------------------------------------------------------*/
1058 static int hpc_poll_thread (void *data)
1059 {
1060 debug ("%s - Entry\n", __FUNCTION__);
1061
1062 daemonize("hpc_poll");
1063 allow_signal(SIGKILL);
1064
1065 poll_hpc ();
1066
1067 tid_poll = 0;
1068 debug ("%s - Exit\n", __FUNCTION__);
1069 return 0;
1070 }
1071
1072
1073 /*----------------------------------------------------------------------
1074 * Name: ibmphp_hpc_start_poll_thread
1075 *
1076 * Action: start polling thread
1077 *---------------------------------------------------------------------*/
1078 int __init ibmphp_hpc_start_poll_thread (void)
1079 {
1080 int rc = 0;
1081
1082 debug ("%s - Entry\n", __FUNCTION__);
1083
1084 tid_poll = kernel_thread (hpc_poll_thread, 0, 0);
1085 if (tid_poll < 0) {
1086 err ("%s - Error, thread not started\n", __FUNCTION__);
1087 rc = -1;
1088 }
1089
1090 debug ("%s - Exit tid_poll[%d] rc[%d]\n", __FUNCTION__, tid_poll, rc);
1091 return rc;
1092 }
1093
1094 /*----------------------------------------------------------------------
1095 * Name: ibmphp_hpc_stop_poll_thread
1096 *
1097 * Action: stop polling thread and cleanup
1098 *---------------------------------------------------------------------*/
1099 void __exit ibmphp_hpc_stop_poll_thread (void)
1100 {
1101 debug ("%s - Entry\n", __FUNCTION__);
1102
1103 ibmphp_shutdown = TRUE;
1104 debug ("before locking operations \n");
1105 ibmphp_lock_operations ();
1106 debug ("after locking operations \n");
1107
1108 // wait for poll thread to exit
1109 debug ("before sem_exit down \n");
1110 down (&sem_exit);
1111 debug ("after sem_exit down \n");
1112
1113 // cleanup
1114 debug ("before free_hpc_access \n");
1115 free_hpc_access ();
1116 debug ("after free_hpc_access \n");
1117 ibmphp_unlock_operations ();
1118 debug ("after unlock operations \n");
1119 up (&sem_exit);
1120 debug ("after sem exit up\n");
1121
1122 debug ("%s - Exit\n", __FUNCTION__);
1123 }
1124
1125 /*----------------------------------------------------------------------
1126 * Name: hpc_wait_ctlr_notworking
1127 *
1128 * Action: wait until the controller is in a not working state
1129 *
1130 * Return 0, HPC_ERROR
1131 * Value:
1132 *---------------------------------------------------------------------*/
1133 static int hpc_wait_ctlr_notworking (int timeout, struct controller *ctlr_ptr, void *wpg_bbar,
1134 u8 * pstatus)
1135 {
1136 int rc = 0;
1137 u8 done = FALSE;
1138
1139 debug_polling ("hpc_wait_ctlr_notworking - Entry timeout[%d]\n", timeout);
1140
1141 while (!done) {
1142 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, WPG_CTLR_INDEX);
1143 if (*pstatus == HPC_ERROR) {
1144 rc = HPC_ERROR;
1145 done = TRUE;
1146 }
1147 if (CTLR_WORKING (*pstatus) == HPC_CTLR_WORKING_NO)
1148 done = TRUE;
1149 if (!done) {
1150 long_delay (1 * HZ);
1151 if (timeout < 1) {
1152 done = TRUE;
1153 err ("HPCreadslot - Error ctlr timeout\n");
1154 rc = HPC_ERROR;
1155 } else
1156 timeout--;
1157 }
1158 }
1159 debug_polling ("hpc_wait_ctlr_notworking - Exit rc[%x] status[%x]\n", rc, *pstatus);
1160 return rc;
1161 }
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