2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/capability.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/bootmem.h>
24 #include <linux/module.h>
27 #include <asm/processor.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/byteorder.h>
33 #include <asm/uaccess.h>
34 #include <asm/ppcdebug.h>
36 #include <asm/pci_dma.h>
40 unsigned long pci_probe_only
= 1;
41 unsigned long pci_assign_all_buses
= 0;
43 unsigned int pcibios_assign_all_busses(void)
45 return pci_assign_all_buses
;
48 /* pci_io_base -- the base address from which io bars are offsets.
49 * This is the lowest I/O base address (so bar values are always positive),
50 * and it *must* be the start of ISA space if an ISA bus exists because
51 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
52 * page is mapped and isa_io_limit prevents access to it.
54 unsigned long isa_io_base
; /* NULL if no ISA bus */
55 unsigned long pci_io_base
;
57 void pcibios_name_device(struct pci_dev
* dev
);
58 void pcibios_final_fixup(void);
59 static void fixup_broken_pcnet32(struct pci_dev
* dev
);
60 static void fixup_windbond_82c105(struct pci_dev
* dev
);
62 void iSeries_pcibios_init(void);
64 struct pci_controller
*hose_head
;
65 struct pci_controller
**hose_tail
= &hose_head
;
67 int global_phb_number
; /* Global phb counter */
69 /* Cached ISA bridge dev. */
70 struct pci_dev
*ppc64_isabridge_dev
= NULL
;
72 struct pci_fixup pcibios_fixups
[] = {
73 { PCI_FIXUP_HEADER
, PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
},
74 { PCI_FIXUP_HEADER
, PCI_VENDOR_ID_WINBOND
, PCI_DEVICE_ID_WINBOND_82C105
, fixup_windbond_82c105
},
75 { PCI_FIXUP_HEADER
, PCI_ANY_ID
, PCI_ANY_ID
, pcibios_name_device
},
79 static void fixup_broken_pcnet32(struct pci_dev
* dev
)
81 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
82 dev
->vendor
= PCI_VENDOR_ID_AMD
;
83 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
88 static void fixup_windbond_82c105(struct pci_dev
* dev
)
90 /* Assume the windbond 82c105 is the IDE controller on a
91 * p610. We should probably be more careful in case
92 * someone tries to plug in a similar adapter.
97 printk("Using INTC for W82c105 IDE controller.\n");
98 pci_read_config_dword(dev
, 0x40, ®
);
99 /* Enable LEGIRQ to use INTC instead of ISA interrupts */
100 pci_write_config_dword(dev
, 0x40, reg
| (1<<11));
102 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; ++i
) {
103 /* zap the 2nd function of the winbond chip */
104 if (dev
->resource
[i
].flags
& IORESOURCE_IO
105 && dev
->bus
->number
== 0 && dev
->devfn
== 0x81)
106 dev
->resource
[i
].flags
&= ~IORESOURCE_IO
;
110 /* Given an mmio phys address, find a pci device that implements
111 * this address. This is of course expensive, but only used
112 * for device initialization or error paths.
113 * For io BARs it is assumed the pci_io_base has already been added
116 * Bridges are ignored although they could be used to optimize the search.
118 struct pci_dev
*pci_find_dev_by_addr(unsigned long addr
)
120 struct pci_dev
*dev
= NULL
;
122 unsigned long ioaddr
;
124 ioaddr
= (addr
> isa_io_base
) ? addr
- isa_io_base
: 0;
126 while ((dev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
127 if ((dev
->class >> 16) == PCI_BASE_CLASS_BRIDGE
)
129 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
130 unsigned long start
= pci_resource_start(dev
,i
);
131 unsigned long end
= pci_resource_end(dev
,i
);
132 unsigned int flags
= pci_resource_flags(dev
,i
);
133 if (start
== 0 || ~start
== 0 ||
134 end
== 0 || ~end
== 0)
136 if ((flags
& IORESOURCE_IO
) &&
137 (ioaddr
>= start
&& ioaddr
<= end
))
139 else if ((flags
& IORESOURCE_MEM
) &&
140 (addr
>= start
&& addr
<= end
))
148 pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
149 struct resource
*res
)
151 unsigned long offset
= 0;
152 struct pci_controller
*hose
= PCI_GET_PHB_PTR(dev
);
157 if (res
->flags
& IORESOURCE_IO
)
158 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
160 if (res
->flags
& IORESOURCE_MEM
)
161 offset
= hose
->pci_mem_offset
;
163 region
->start
= res
->start
- offset
;
164 region
->end
= res
->end
- offset
;
167 #ifdef CONFIG_HOTPLUG
168 EXPORT_SYMBOL(pcibios_resource_to_bus
);
172 * We need to avoid collisions with `mirrored' VGA ports
173 * and other strange ISA hardware, so we always want the
174 * addresses to be allocated in the 0x000-0x0ff region
177 * Why? Because some silly external IO cards only decode
178 * the low 10 bits of the IO address. The 0x00-0xff region
179 * is reserved for motherboard devices that decode all 16
180 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
181 * but we want to try to avoid allocating at 0x2900-0x2bff
182 * which might have be mirrored at 0x0100-0x03ff..
184 void pcibios_align_resource(void *data
, struct resource
*res
,
185 unsigned long size
, unsigned long align
)
187 struct pci_dev
*dev
= data
;
188 struct pci_controller
*hose
= PCI_GET_PHB_PTR(dev
);
189 unsigned long start
= res
->start
;
190 unsigned long alignto
;
192 if (res
->flags
& IORESOURCE_IO
) {
193 unsigned long offset
= (unsigned long)hose
->io_base_virt
-
195 /* Make sure we start at our min on all hoses */
196 if (start
- offset
< PCIBIOS_MIN_IO
)
197 start
= PCIBIOS_MIN_IO
+ offset
;
200 * Put everything into 0x00-0xff region modulo 0x400
203 start
= (start
+ 0x3ff) & ~0x3ff;
205 } else if (res
->flags
& IORESOURCE_MEM
) {
206 /* Make sure we start at our min on all hoses */
207 if (start
- hose
->pci_mem_offset
< PCIBIOS_MIN_MEM
)
208 start
= PCIBIOS_MIN_MEM
+ hose
->pci_mem_offset
;
210 /* Align to multiple of size of minimum base. */
211 alignto
= max(0x1000UL
, align
);
212 start
= ALIGN(start
, alignto
);
219 * Allocate pci_controller(phb) initialized common variables.
221 struct pci_controller
* __init
222 pci_alloc_pci_controller(enum phb_types controller_type
)
224 struct pci_controller
*hose
;
227 hose
= (struct pci_controller
*)alloc_bootmem(sizeof(struct pci_controller
));
229 printk(KERN_ERR
"PCI: Allocate pci_controller failed.\n");
232 memset(hose
, 0, sizeof(struct pci_controller
));
234 switch(controller_type
) {
235 case phb_type_python
:
238 case phb_type_speedwagon
:
241 case phb_type_winnipeg
:
249 if(strlen(model
) < 8)
250 strcpy(hose
->what
,model
);
252 memcpy(hose
->what
,model
,7);
253 hose
->type
= controller_type
;
254 hose
->global_number
= global_phb_number
++;
257 hose_tail
= &hose
->next
;
261 static void __init
pcibios_claim_one_bus(struct pci_bus
*b
)
263 struct list_head
*ld
;
264 struct pci_bus
*child_bus
;
266 for (ld
= b
->devices
.next
; ld
!= &b
->devices
; ld
= ld
->next
) {
267 struct pci_dev
*dev
= pci_dev_b(ld
);
270 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
271 struct resource
*r
= &dev
->resource
[i
];
273 if (r
->parent
|| !r
->start
|| !r
->flags
)
275 pci_claim_resource(dev
, i
);
279 list_for_each_entry(child_bus
, &b
->children
, node
)
280 pcibios_claim_one_bus(child_bus
);
283 static void __init
pcibios_claim_of_setup(void)
285 struct list_head
*lb
;
287 for (lb
= pci_root_buses
.next
; lb
!= &pci_root_buses
; lb
= lb
->next
) {
288 struct pci_bus
*b
= pci_bus_b(lb
);
289 pcibios_claim_one_bus(b
);
293 static int __init
pcibios_init(void)
295 struct pci_controller
*hose
;
298 #ifdef CONFIG_PPC_ISERIES
299 iSeries_pcibios_init();
302 //ppc64_boot_msg(0x40, "PCI Probe");
303 printk("PCI: Probing PCI hardware\n");
305 /* Scan all of the recorded PCI controllers. */
306 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
307 hose
->last_busno
= 0xff;
308 bus
= pci_scan_bus(hose
->first_busno
, hose
->ops
,
311 hose
->last_busno
= bus
->subordinate
;
315 pcibios_claim_of_setup();
317 /* FIXME: `else' will be removed when
318 pci_assign_unassigned_resources() is able to work
319 correctly with [partially] allocated PCI tree. */
320 pci_assign_unassigned_resources();
322 /* Call machine dependent fixup */
323 pcibios_final_fixup();
325 /* Cache the location of the ISA bridge (if we have one) */
326 ppc64_isabridge_dev
= pci_find_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
327 if (ppc64_isabridge_dev
!= NULL
)
328 printk("ISA bridge at %s\n", ppc64_isabridge_dev
->slot_name
);
330 printk("PCI: Probing PCI hardware done\n");
331 //ppc64_boot_msg(0x41, "PCI Done");
336 subsys_initcall(pcibios_init
);
338 char __init
*pcibios_setup(char *str
)
343 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
348 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
351 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
352 struct resource
*res
= &dev
->resource
[i
];
354 /* Only set up the requested stuff */
355 if (!(mask
& (1<<i
)))
358 if (res
->flags
& IORESOURCE_IO
)
359 cmd
|= PCI_COMMAND_IO
;
360 if (res
->flags
& IORESOURCE_MEM
)
361 cmd
|= PCI_COMMAND_MEMORY
;
365 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
366 dev
->slot_name
, cmd
);
367 /* Enable the appropriate bits in the PCI command register. */
368 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
374 * Return the domain number for this bus.
376 int pci_domain_nr(struct pci_bus
*bus
)
378 struct pci_controller
*hose
= PCI_GET_PHB_PTR(bus
);
380 return hose
->global_number
;
383 /* Set the name of the bus as it appears in /proc/bus/pci */
384 int pci_name_bus(char *name
, struct pci_bus
*bus
)
386 struct pci_controller
*hose
= PCI_GET_PHB_PTR(bus
);
389 sprintf(name
, "%04x:%02x", pci_domain_nr(bus
), bus
->number
);
391 sprintf(name
, "%02x", bus
->number
);
397 * Platform support for /proc/bus/pci/X/Y mmap()s,
398 * modelled on the sparc64 implementation by Dave Miller.
403 * Adjust vm_pgoff of VMA such that it is the physical page offset
404 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
406 * Basically, the user finds the base address for his device which he wishes
407 * to mmap. They read the 32-bit value from the config space base register,
408 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
409 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
411 * Returns negative error code on failure, zero on success.
413 static __inline__
int
414 __pci_mmap_make_offset(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
415 enum pci_mmap_state mmap_state
)
417 struct pci_controller
*hose
= PCI_GET_PHB_PTR(dev
);
418 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
419 unsigned long io_offset
= 0;
423 return -EINVAL
; /* should never happen */
425 /* If memory, add on the PCI bridge address offset */
426 if (mmap_state
== pci_mmap_mem
) {
427 offset
+= hose
->pci_mem_offset
;
428 res_bit
= IORESOURCE_MEM
;
430 io_offset
= (unsigned long)hose
->io_base_virt
;
432 res_bit
= IORESOURCE_IO
;
436 * Check that the offset requested corresponds to one of the
437 * resources of the device.
439 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
440 struct resource
*rp
= &dev
->resource
[i
];
441 int flags
= rp
->flags
;
443 /* treat ROM as memory (should be already) */
444 if (i
== PCI_ROM_RESOURCE
)
445 flags
|= IORESOURCE_MEM
;
447 /* Active and same type? */
448 if ((flags
& res_bit
) == 0)
451 /* In the range of this resource? */
452 if (offset
< (rp
->start
& PAGE_MASK
) || offset
> rp
->end
)
455 /* found it! construct the final physical address */
456 if (mmap_state
== pci_mmap_io
)
457 offset
+= hose
->io_base_phys
- io_offset
;
459 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
467 * Set vm_flags of VMA, as appropriate for this architecture, for a pci device
470 static __inline__
void
471 __pci_mmap_set_flags(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
472 enum pci_mmap_state mmap_state
)
474 vma
->vm_flags
|= VM_SHM
| VM_LOCKED
| VM_IO
;
478 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
481 static __inline__
void
482 __pci_mmap_set_pgprot(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
483 enum pci_mmap_state mmap_state
, int write_combine
)
485 long prot
= pgprot_val(vma
->vm_page_prot
);
487 /* XXX would be nice to have a way to ask for write-through */
488 prot
|= _PAGE_NO_CACHE
;
490 prot
|= _PAGE_GUARDED
;
491 vma
->vm_page_prot
= __pgprot(prot
);
495 * Perform the actual remap of the pages for a PCI device mapping, as
496 * appropriate for this architecture. The region in the process to map
497 * is described by vm_start and vm_end members of VMA, the base physical
498 * address is found in vm_pgoff.
499 * The pci device structure is provided so that architectures may make mapping
500 * decisions on a per-device or per-bus basis.
502 * Returns a negative error code on failure, zero on success.
504 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
505 enum pci_mmap_state mmap_state
,
510 ret
= __pci_mmap_make_offset(dev
, vma
, mmap_state
);
514 __pci_mmap_set_flags(dev
, vma
, mmap_state
);
515 __pci_mmap_set_pgprot(dev
, vma
, mmap_state
, write_combine
);
517 ret
= remap_page_range(vma
, vma
->vm_start
, vma
->vm_pgoff
<< PAGE_SHIFT
,
518 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);