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Fix typos.
[linux-2.6/linux-mips.git] / drivers / isdn / hisax / hisax_hfcpci.c
blob8537978b932870930f2500d73f2170679bdfd4cd
1 /*
2 * Driver for HFC PCI based cards
3 *
4 * Author Kai Germaschewski
5 * Copyright 2002 by Kai Germaschewski <kai.germaschewski@gmx.de>
6 * 2000 by Karsten Keil <keil@isdn4linux.de>
7 * 2000 by Werner Cornelius <werner@isdn4linux.de>
8 *
9 * based upon Werner Cornelius's original hfc_pci.c driver
10 *
11 * This software may be used and distributed according to the terms
12 * of the GNU General Public License, incorporated herein by reference.
13 *
14 */
15
16 // XXX timer3
17
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22 #include <linux/kmod.h>
23 #include <linux/slab.h>
24 #include <linux/skbuff.h>
25 #include <linux/netdevice.h>
26 #include <asm/delay.h>
27 #include "hisax_hfcpci.h"
28
29 // debugging cruft
30 #define __debug_variable debug
31 #include "hisax_debug.h"
32
33 #ifdef CONFIG_HISAX_DEBUG
34 static int debug = 0;
35 MODULE_PARM(debug, "i");
36 #endif
37
38 MODULE_AUTHOR("Kai Germaschewski <kai.germaschewski@gmx.de>/Werner Cornelius <werner@isdn4linux.de>");
39 MODULE_DESCRIPTION("HFC PCI ISDN driver");
40
41 #define ID(ven, dev, name) \
42 { .vendor = PCI_VENDOR_ID_##ven, \
43 .device = PCI_DEVICE_ID_##dev, \
44 .subvendor = PCI_ANY_ID, \
45 .subdevice = PCI_ANY_ID, \
46 .class = 0, \
47 .class_mask = 0, \
48 .driver_data = (unsigned long) name }
49
50 static struct pci_device_id hfcpci_ids[] __devinitdata = {
51 ID(CCD, CCD_2BD0, "CCD/Billion/Asuscom 2BD0"),
52 ID(CCD, CCD_B000, "Billion B000"),
53 ID(CCD, CCD_B006, "Billion B006"),
54 ID(CCD, CCD_B007, "Billion B007"),
55 ID(CCD, CCD_B008, "Billion B008"),
56 ID(CCD, CCD_B009, "Billion B009"),
57 ID(CCD, CCD_B00A, "Billion B00A"),
58 ID(CCD, CCD_B00B, "Billion B00B"),
59 ID(CCD, CCD_B00C, "Billion B00C"),
60 ID(CCD, CCD_B100, "Seyeon"),
61 ID(ABOCOM, ABOCOM_2BD1, "Abocom/Magitek"),
62 ID(ASUSTEK, ASUSTEK_0675, "Asuscom/Askey"),
63 ID(BERKOM, BERKOM_T_CONCEPT, "German Telekom T-Concept"),
64 ID(BERKOM, BERKOM_A1T, "German Telekom A1T"),
65 ID(ANIGMA, ANIGMA_MC145575, "Motorola MC145575"),
66 ID(ZOLTRIX, ZOLTRIX_2BD0, "Zoltrix 2BD0"),
67 ID(DIGI, DIGI_DF_M_IOM2_E, "Digi DataFire Micro V IOM2 (Europe)"),
68 ID(DIGI, DIGI_DF_M_E, "Digi DataFire Micro V (Europe)"),
69 ID(DIGI, DIGI_DF_M_IOM2_A, "Digi DataFire Micro V IOM2 (America)"),
70 ID(DIGI, DIGI_DF_M_A, "Digi DataFire Micro V (America)"),
71 { }
72 };
73 MODULE_DEVICE_TABLE(pci, hfcpci_ids);
74
75 #undef ID
76
77 static int protocol = 2; /* EURO-ISDN Default */
78 MODULE_PARM(protocol, "i");
79
80 // ----------------------------------------------------------------------
81 //
82
83 #define DBG_WARN 0x0001
84 #define DBG_INFO 0x0002
85 #define DBG_IRQ 0x0010
86 #define DBG_L1M 0x0020
87 #define DBG_PR 0x0040
88 #define DBG_D_XMIT 0x0100
89 #define DBG_D_RECV 0x0200
90 #define DBG_B_XMIT 0x1000
91 #define DBG_B_RECV 0x2000
92
93 /* memory window base address offset (in config space) */
94
95 #define HFCPCI_MWBA 0x80
96
97 /* GCI/IOM bus monitor registers */
98
99 #define HCFPCI_C_I 0x08
100 #define HFCPCI_TRxR 0x0C
101 #define HFCPCI_MON1_D 0x28
102 #define HFCPCI_MON2_D 0x2C
103
104
105 /* GCI/IOM bus timeslot registers */
106
107 #define HFCPCI_B1_SSL 0x80
108 #define HFCPCI_B2_SSL 0x84
109 #define HFCPCI_AUX1_SSL 0x88
110 #define HFCPCI_AUX2_SSL 0x8C
111 #define HFCPCI_B1_RSL 0x90
112 #define HFCPCI_B2_RSL 0x94
113 #define HFCPCI_AUX1_RSL 0x98
114 #define HFCPCI_AUX2_RSL 0x9C
115
116 /* GCI/IOM bus data registers */
117
118 #define HFCPCI_B1_D 0xA0
119 #define HFCPCI_B2_D 0xA4
120 #define HFCPCI_AUX1_D 0xA8
121 #define HFCPCI_AUX2_D 0xAC
122
123 /* GCI/IOM bus configuration registers */
124
125 #define HFCPCI_MST_EMOD 0xB4
126 #define HFCPCI_MST_MODE 0xB8
127 #define HFCPCI_CONNECT 0xBC
128
129
130 /* Interrupt and status registers */
131
132 #define HFCPCI_FIFO_EN 0x44
133 #define HFCPCI_TRM 0x48
134 #define HFCPCI_B_MODE 0x4C
135 #define HFCPCI_CHIP_ID 0x58
136 #define HFCPCI_CIRM 0x60
137 #define HFCPCI_CTMT 0x64
138 #define HFCPCI_INT_M1 0x68
139 #define HFCPCI_INT_M2 0x6C
140 #define HFCPCI_INT_S1 0x78
141 #define HFCPCI_INT_S2 0x7C
142 #define HFCPCI_STATUS 0x70
143
144 /* S/T section registers */
145
146 #define HFCPCI_STATES 0xC0
147 #define HFCPCI_SCTRL 0xC4
148 #define HFCPCI_SCTRL_E 0xC8
149 #define HFCPCI_SCTRL_R 0xCC
150 #define HFCPCI_SQ 0xD0
151 #define HFCPCI_CLKDEL 0xDC
152 #define HFCPCI_B1_REC 0xF0
153 #define HFCPCI_B1_SEND 0xF0
154 #define HFCPCI_B2_REC 0xF4
155 #define HFCPCI_B2_SEND 0xF4
156 #define HFCPCI_D_REC 0xF8
157 #define HFCPCI_D_SEND 0xF8
158 #define HFCPCI_E_REC 0xFC
159
160
161 /* bits in status register (READ) */
162 #define HFCPCI_PCI_PROC 0x02
163 #define HFCPCI_NBUSY 0x04
164 #define HFCPCI_TIMER_ELAP 0x10
165 #define HFCPCI_STATINT 0x20
166 #define HFCPCI_FRAMEINT 0x40
167 #define HFCPCI_ANYINT 0x80
168
169 /* bits in CTMT (Write) */
170 #define HFCPCI_CLTIMER 0x80
171 #define HFCPCI_TIM3_125 0x04
172 #define HFCPCI_TIM25 0x10
173 #define HFCPCI_TIM50 0x14
174 #define HFCPCI_TIM400 0x18
175 #define HFCPCI_TIM800 0x1C
176 #define HFCPCI_AUTO_TIMER 0x20
177 #define HFCPCI_TRANSB2 0x02
178 #define HFCPCI_TRANSB1 0x01
179
180 /* bits in CIRM (Write) */
181 #define HFCPCI_AUX_MSK 0x07
182 #define HFCPCI_RESET 0x08
183 #define HFCPCI_B1_REV 0x40
184 #define HFCPCI_B2_REV 0x80
185
186 /* bits in INT_M1 and INT_S1 */
187 #define HFCPCI_INTS_B1TRANS 0x01
188 #define HFCPCI_INTS_B2TRANS 0x02
189 #define HFCPCI_INTS_DTRANS 0x04
190 #define HFCPCI_INTS_B1REC 0x08
191 #define HFCPCI_INTS_B2REC 0x10
192 #define HFCPCI_INTS_DREC 0x20
193 #define HFCPCI_INTS_L1STATE 0x40
194 #define HFCPCI_INTS_TIMER 0x80
195
196 /* bits in INT_M2 */
197 #define HFCPCI_PROC_TRANS 0x01
198 #define HFCPCI_GCI_I_CHG 0x02
199 #define HFCPCI_GCI_MON_REC 0x04
200 #define HFCPCI_IRQ_ENABLE 0x08
201 #define HFCPCI_PMESEL 0x80
202
203 /* bits in STATES */
204 #define HFCPCI_STATE_MSK 0x0F
205 #define HFCPCI_LOAD_STATE 0x10
206 #define HFCPCI_ACTIVATE 0x20
207 #define HFCPCI_DO_ACTION 0x40
208 #define HFCPCI_NT_G2_G3 0x80
209
210 /* bits in HFCD_MST_MODE */
211 #define HFCPCI_MASTER 0x01
212 #define HFCPCI_SLAVE 0x00
213 /* remaining bits are for codecs control */
214
215 /* bits in HFCD_SCTRL */
216 #define SCTRL_B1_ENA 0x01
217 #define SCTRL_B2_ENA 0x02
218 #define SCTRL_MODE_TE 0x00
219 #define SCTRL_MODE_NT 0x04
220 #define SCTRL_LOW_PRIO 0x08
221 #define SCTRL_SQ_ENA 0x10
222 #define SCTRL_TEST 0x20
223 #define SCTRL_NONE_CAP 0x40
224 #define SCTRL_PWR_DOWN 0x80
225
226 /* bits in SCTRL_E */
227 #define HFCPCI_AUTO_AWAKE 0x01
228 #define HFCPCI_DBIT_1 0x04
229 #define HFCPCI_IGNORE_COL 0x08
230 #define HFCPCI_CHG_B1_B2 0x80
231
232 /* bits in FIFO_EN register */
233 #define HFCPCI_FIFOEN_B1 0x03
234 #define HFCPCI_FIFOEN_B2 0x0C
235 #define HFCPCI_FIFOEN_DTX 0x10
236 #define HFCPCI_FIFOEN_DRX 0x20
237 #define HFCPCI_FIFOEN_B1TX 0x01
238 #define HFCPCI_FIFOEN_B1RX 0x02
239 #define HFCPCI_FIFOEN_B2TX 0x04
240 #define HFCPCI_FIFOEN_B2RX 0x08
241
242 /*
243 * thresholds for transparent B-channel mode
244 * change mask and threshold simultaneously
245 */
246 #define HFCPCI_BTRANS_THRESHOLD 128
247 #define HFCPCI_BTRANS_THRESMASK 0x00
248
249 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
250 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
251
252 #define MAX_D_FRAMES 0x10
253 #define MAX_B_FRAMES 0x20
254 #define B_FIFO_START 0x0200
255 #define B_FIFO_END 0x2000
256 #define B_FIFO_SIZE (B_FIFO_END - B_FIFO_START)
257 #define D_FIFO_START 0x0000
258 #define D_FIFO_END 0x0200
259 #define D_FIFO_SIZE (D_FIFO_END - D_FIFO_START)
260
261 // ----------------------------------------------------------------------
262 // push messages to the upper layers
263
264 static inline void D_L1L2(struct hfcpci_adapter *adapter, int pr, void *arg)
265 {
266 struct hisax_if *ifc = (struct hisax_if *) &adapter->d_if;
267
268 DBG(DBG_PR, "pr %#x", pr);
269 ifc->l1l2(ifc, pr, arg);
270 }
271
272 static inline void B_L1L2(struct hfcpci_bcs *bcs, int pr, void *arg)
273 {
274 struct hisax_if *ifc = (struct hisax_if *) &bcs->b_if;
275
276 DBG(DBG_PR, "pr %#x", pr);
277 ifc->l1l2(ifc, pr, arg);
278 }
279
280 // ----------------------------------------------------------------------
281 // MMIO
282
283 static inline void
284 hfcpci_writeb(struct hfcpci_adapter *adapter, u8 b, unsigned char offset)
285 {
286 writeb(b, adapter->mmio + offset);
287 }
288
289 static inline u8
290 hfcpci_readb(struct hfcpci_adapter *adapter, unsigned char offset)
291 {
292 return readb(adapter->mmio + offset);
293 }
294
295 // ----------------------------------------------------------------------
296 // magic to define the various F/Z counter accesses
297
298 #define DECL_B_F(r, f) \
299 static inline u8 \
300 get_b_##r##_##f (struct hfcpci_bcs *bcs) \
301 { \
302 u16 off = bcs->channel ? OFF_B2_##r##_##f : OFF_B1_##r##_##f; \
303 \
304 return *(bcs->adapter->fifo + off); \
305 } \
306 \
307 static inline void \
308 set_b_##r##_##f (struct hfcpci_bcs *bcs, u8 f) \
309 { \
310 u16 off = bcs->channel ? OFF_B2_##r##_##f : OFF_B1_##r##_##f; \
311 \
312 *(bcs->adapter->fifo + off) = f; \
313 }
314
315 #define OFF_B1_rx_f1 0x6080
316 #define OFF_B2_rx_f1 0x6180
317 #define OFF_B1_rx_f2 0x6081
318 #define OFF_B2_rx_f2 0x6181
319
320 #define OFF_B1_tx_f1 0x2080
321 #define OFF_B2_tx_f1 0x2180
322 #define OFF_B1_tx_f2 0x2081
323 #define OFF_B2_tx_f2 0x2181
324
325 DECL_B_F(rx, f1)
326 DECL_B_F(rx, f2)
327 DECL_B_F(tx, f1)
328 DECL_B_F(tx, f2)
329
330 #undef DECL_B_F
331
332 #define DECL_B_Z(r, z) \
333 static inline u16 \
334 get_b_##r##_##z (struct hfcpci_bcs *bcs, u8 f) \
335 { \
336 u16 off = bcs->channel ? OFF_B2_##r##_##z : OFF_B1_##r##_##z; \
337 \
338 return le16_to_cpu(*((u16 *) (bcs->adapter->fifo + off + f * 4))); \
339 } \
340 \
341 static inline void \
342 set_b_##r##_##z(struct hfcpci_bcs *bcs, u8 f, u16 z) \
343 { \
344 u16 off = bcs->channel ? OFF_B2_##r##_##z : OFF_B1_##r##_##z; \
345 \
346 *((u16 *) (bcs->adapter->fifo + off + f * 4)) = cpu_to_le16(z); \
347 }
348
349 #define OFF_B1_rx_z1 0x6000
350 #define OFF_B2_rx_z1 0x6100
351 #define OFF_B1_rx_z2 0x6002
352 #define OFF_B2_rx_z2 0x6102
353
354 #define OFF_B1_tx_z1 0x2000
355 #define OFF_B2_tx_z1 0x2100
356 #define OFF_B1_tx_z2 0x2002
357 #define OFF_B2_tx_z2 0x2102
358
359 DECL_B_Z(rx, z1)
360 DECL_B_Z(rx, z2)
361 DECL_B_Z(tx, z1)
362 DECL_B_Z(tx, z2)
363
364 #undef DECL_B_Z
365
366 #define DECL_D_F(r, f) \
367 static inline u8 \
368 get_d_##r##_##f (struct hfcpci_adapter *adapter) \
369 { \
370 u16 off = OFF_D_##r##_##f; \
371 \
372 return *(adapter->fifo + off) & 0xf; \
373 } \
374 \
375 static inline void \
376 set_d_##r##_##f (struct hfcpci_adapter *adapter, u8 f) \
377 { \
378 u16 off = OFF_D_##r##_##f; \
379 \
380 *(adapter->fifo + off) = f | 0x10; \
381 }
382
383 #define OFF_D_rx_f1 0x60a0
384 #define OFF_D_rx_f2 0x60a1
385
386 #define OFF_D_tx_f1 0x20a0
387 #define OFF_D_tx_f2 0x20a1
388
389 DECL_D_F(rx, f1)
390 DECL_D_F(rx, f2)
391 DECL_D_F(tx, f1)
392 DECL_D_F(tx, f2)
393
394 #undef DECL_D_F
395
396 #define DECL_D_Z(r, z) \
397 static inline u16 \
398 get_d_##r##_##z (struct hfcpci_adapter *adapter, u8 f) \
399 { \
400 u16 off = OFF_D_##r##_##z; \
401 \
402 return le16_to_cpu(*((u16 *) (adapter->fifo + off + (f | 0x10) * 4)));\
403 } \
404 \
405 static inline void \
406 set_d_##r##_##z(struct hfcpci_adapter *adapter, u8 f, u16 z) \
407 { \
408 u16 off = OFF_D_##r##_##z; \
409 \
410 *((u16 *) (adapter->fifo + off + (f | 0x10) * 4)) = cpu_to_le16(z); \
411 }
412
413 #define OFF_D_rx_z1 0x6080
414 #define OFF_D_rx_z2 0x6082
415
416 #define OFF_D_tx_z1 0x2080
417 #define OFF_D_tx_z2 0x2082
418
419 DECL_D_Z(rx, z1)
420 DECL_D_Z(rx, z2)
421 DECL_D_Z(tx, z1)
422 DECL_D_Z(tx, z2)
423
424 #undef DECL_B_Z
425
426 // ----------------------------------------------------------------------
427 // fill b / d fifos
428
429 static inline void
430 hfcpci_fill_d_fifo(struct hfcpci_adapter *adapter)
431 {
432 u8 f1, f2;
433 u16 z1, z2;
434 int cnt, fcnt;
435 char *fifo_adr = adapter->fifo;
436 struct sk_buff *tx_skb = adapter->tx_skb;
437
438 f1 = get_d_tx_f1(adapter);
439 f2 = get_d_tx_f2(adapter);
440 DBG(DBG_D_XMIT, "f1 %#x f2 %#x", f1, f2);
441
442 fcnt = f1 - f2;
443 if (fcnt < 0)
444 fcnt += MAX_D_FRAMES;
445
446 if (fcnt) {
447 printk("BUG\n");
448 return;
449 }
450
451 z1 = get_d_tx_z1(adapter, f1);
452 z2 = get_d_tx_z2(adapter, f1); //XXX
453 DBG(DBG_D_XMIT, "z1 %#x z2 %#x", z1, z2);
454
455 cnt = z2 - z1;
456 if (cnt <= 0)
457 cnt += D_FIFO_SIZE;
458
459 if (tx_skb->len > cnt) {
460 printk("BUG\n");
461 return;
462 }
463
464 cnt = tx_skb->len;
465 if (z1 + cnt <= D_FIFO_END) {
466 memcpy(fifo_adr + z1, tx_skb->data, cnt);
467 } else {
468 memcpy(fifo_adr + z1, tx_skb->data, D_FIFO_END - z1);
469 memcpy(fifo_adr + D_FIFO_START,
470 tx_skb->data + (D_FIFO_END - z1),
471 cnt - (D_FIFO_END - z1));
472 }
473 z1 += cnt;
474 if (z1 >= D_FIFO_END)
475 z1 -= D_FIFO_SIZE;
476
477 f1 = (f1 + 1) & (MAX_D_FRAMES - 1);
478 mb();
479 set_d_tx_z1(adapter, f1, z1);
480 mb();
481 set_d_tx_f1(adapter, f1);
482 }
483
484 static inline void
485 hfcpci_fill_b_fifo_hdlc(struct hfcpci_bcs *bcs)
486 {
487 u8 f1, f2;
488 u16 z1, z2;
489 int cnt, fcnt;
490 char *fifo_adr = bcs->adapter->fifo + (bcs->channel ? 0x2000 : 0x0000);
491 struct sk_buff *tx_skb = bcs->tx_skb;
492
493 f1 = get_b_tx_f1(bcs);
494 f2 = get_b_tx_f2(bcs);
495 DBG(DBG_B_XMIT, "f1 %#x f2 %#x", f1, f2);
496
497 fcnt = f1 - f2;
498 if (fcnt < 0)
499 fcnt += MAX_B_FRAMES;
500
501 if (fcnt) {
502 printk("BUG\n");
503 return;
504 }
505
506 z1 = get_b_tx_z1(bcs, f1);
507 z2 = get_b_tx_z2(bcs, f1); //XXX
508 DBG(DBG_B_XMIT, "z1 %#x z2 %#x", z1, z2);
509
510 cnt = z2 - z1;
511 if (cnt <= 0)
512 cnt += B_FIFO_SIZE;
513
514 if (tx_skb->len > cnt) {
515 printk("BUG\n");
516 return;
517 }
518
519 cnt = tx_skb->len;
520 if (z1 + cnt <= B_FIFO_END) {
521 memcpy(fifo_adr + z1, tx_skb->data, cnt);
522 } else {
523 memcpy(fifo_adr + z1, tx_skb->data, B_FIFO_END - z1);
524 memcpy(fifo_adr + B_FIFO_START,
525 tx_skb->data + (B_FIFO_END - z1),
526 cnt - (B_FIFO_END - z1));
527 }
528 z1 += cnt;
529 if (z1 >= B_FIFO_END)
530 z1 -= B_FIFO_SIZE;
531
532 f1 = (f1 + 1) & (MAX_B_FRAMES - 1);
533 mb();
534 set_b_tx_z1(bcs, f1, z1);
535 mb();
536 set_b_tx_f1(bcs, f1);
537 }
538
539 static inline void
540 hfcpci_fill_b_fifo_trans(struct hfcpci_bcs *bcs)
541 {
542 int cnt;
543 char *fifo_adr = bcs->adapter->fifo + (bcs->channel ? 0x2000 : 0x0000);
544 struct sk_buff *tx_skb = bcs->tx_skb;
545 u8 f1, f2;
546 u16 z1, z2;
547
548 f1 = get_b_tx_f1(bcs);
549 f2 = get_b_tx_f2(bcs);
550
551 if (f1 != f2)
552 BUG();
553
554 z1 = get_b_tx_z1(bcs, f1);
555 z2 = get_b_tx_z2(bcs, f1);
556
557 cnt = z2 - z1;
558 if (cnt <= 0)
559 cnt += B_FIFO_SIZE;
560
561 if (tx_skb->len > cnt)
562 BUG();
563
564 if (z1 + cnt <= B_FIFO_END) {
565 memcpy(fifo_adr + z1, tx_skb->data, cnt);
566 } else {
567 memcpy(fifo_adr + z1, tx_skb->data, B_FIFO_END - z1);
568 memcpy(fifo_adr + B_FIFO_START,
569 tx_skb->data + (B_FIFO_END - z1),
570 cnt - (B_FIFO_END - z1));
571 }
572 z1 += cnt;
573 if (z1 >= B_FIFO_END)
574 z1 -= B_FIFO_SIZE;
575
576 mb();
577 set_b_tx_z1(bcs, f1, z1);
578 }
579
580 static inline void
581 hfcpci_fill_b_fifo(struct hfcpci_bcs *bcs)
582 {
583 if (!bcs->tx_skb) {
584 DBG(DBG_WARN, "?");
585 return;
586 }
587
588 switch (bcs->mode) {
589 case L1_MODE_TRANS:
590 hfcpci_fill_b_fifo_trans(bcs);
591 break;
592 case L1_MODE_HDLC:
593 hfcpci_fill_b_fifo_hdlc(bcs);
594 break;
595 default:
596 DBG(DBG_WARN, "?");
597 }
598 }
599
600 static void hfcpci_clear_b_rx_fifo(struct hfcpci_bcs *bcs);
601 static void hfcpci_clear_b_tx_fifo(struct hfcpci_bcs *bcs);
602
603 static void
604 hfcpci_b_mode(struct hfcpci_bcs *bcs, int mode)
605 {
606 struct hfcpci_adapter *adapter = bcs->adapter;
607
608 DBG(DBG_B_XMIT, "B%d mode %d --> %d",
609 bcs->channel + 1, bcs->mode, mode);
610
611 if (bcs->mode == mode)
612 return;
613
614 switch (mode) {
615 case L1_MODE_NULL:
616 if (bcs->channel == 0) {
617 adapter->sctrl &= ~SCTRL_B1_ENA;
618 adapter->sctrl_r &= ~SCTRL_B1_ENA;
619 adapter->fifo_en &= ~HFCPCI_FIFOEN_B1;
620 adapter->int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
621 } else {
622 adapter->sctrl &= ~SCTRL_B2_ENA;
623 adapter->sctrl_r &= ~SCTRL_B2_ENA;
624 adapter->fifo_en &= ~HFCPCI_FIFOEN_B2;
625 adapter->int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
626 }
627 break;
628 case L1_MODE_TRANS:
629 case L1_MODE_HDLC:
630 hfcpci_clear_b_rx_fifo(bcs);
631 hfcpci_clear_b_tx_fifo(bcs);
632 if (bcs->channel == 0) {
633 adapter->sctrl |= SCTRL_B1_ENA;
634 adapter->sctrl_r |= SCTRL_B1_ENA;
635 adapter->fifo_en |= HFCPCI_FIFOEN_B1;
636 adapter->int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
637
638 if (mode == L1_MODE_TRANS)
639 adapter->ctmt |= 1;
640 else
641 adapter->ctmt &= ~1;
642
643 } else {
644 adapter->sctrl |= SCTRL_B2_ENA;
645 adapter->sctrl_r |= SCTRL_B2_ENA;
646 adapter->fifo_en |= HFCPCI_FIFOEN_B2;
647 adapter->int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
648
649 if (mode == L1_MODE_TRANS)
650 adapter->ctmt |= 2;
651 else
652 adapter->ctmt &= ~2;
653
654 }
655 break;
656 }
657 hfcpci_writeb(adapter, adapter->int_m1, HFCPCI_INT_M1);
658 hfcpci_writeb(adapter, adapter->fifo_en, HFCPCI_FIFO_EN);
659 hfcpci_writeb(adapter, adapter->sctrl, HFCPCI_SCTRL);
660 hfcpci_writeb(adapter, adapter->sctrl_r, HFCPCI_SCTRL_R);
661 hfcpci_writeb(adapter, adapter->ctmt, HFCPCI_CTMT);
662 hfcpci_writeb(adapter, adapter->conn, HFCPCI_CONNECT);
663
664 bcs->mode = mode;
665 }
666
667 // ----------------------------------------------------------------------
668 // Layer 1 state machine
669
670 static struct Fsm l1fsm;
671
672 enum {
673 ST_L1_F0,
674 ST_L1_F2,
675 ST_L1_F3,
676 ST_L1_F4,
677 ST_L1_F5,
678 ST_L1_F6,
679 ST_L1_F7,
680 ST_L1_F8,
681 };
682
683 #define L1_STATE_COUNT (ST_L1_F8+1)
684
685 static char *strL1State[] =
686 {
687 "ST_L1_F0",
688 "ST_L1_F2",
689 "ST_L1_F3",
690 "ST_L1_F4",
691 "ST_L1_F5",
692 "ST_L1_F6",
693 "ST_L1_F7",
694 "ST_L1_F8",
695 };
696
697 enum {
698 EV_PH_F0,
699 EV_PH_1,
700 EV_PH_F2,
701 EV_PH_F3,
702 EV_PH_F4,
703 EV_PH_F5,
704 EV_PH_F6,
705 EV_PH_F7,
706 EV_PH_F8,
707 EV_PH_ACTIVATE_REQ,
708 EV_PH_DEACTIVATE_REQ,
709 EV_TIMER3,
710 };
711
712 #define L1_EVENT_COUNT (EV_TIMER3 + 1)
713
714 static char *strL1Event[] =
715 {
716 "EV_PH_F0",
717 "EV_PH_1",
718 "EV_PH_F2",
719 "EV_PH_F3",
720 "EV_PH_F4",
721 "EV_PH_F5",
722 "EV_PH_F6",
723 "EV_PH_F7",
724 "EV_PH_F8",
725 "EV_PH_ACTIVATE_REQ",
726 "EV_PH_DEACTIVATE_REQ",
727 "EV_TIMER3",
728 };
729
730 static void l1_ignore(struct FsmInst *fi, int event, void *arg)
731 {
732 }
733
734 static void l1_go_f3(struct FsmInst *fi, int event, void *arg)
735 {
736 FsmChangeState(fi, ST_L1_F3);
737 }
738
739 static void l1_go_f3_deact_ind(struct FsmInst *fi, int event, void *arg)
740 {
741 struct hfcpci_adapter *adapter = fi->userdata;
742
743 FsmChangeState(fi, ST_L1_F3);
744 D_L1L2(adapter, PH_DEACTIVATE | INDICATION, NULL);
745 }
746
747 static void l1_go_f4(struct FsmInst *fi, int event, void *arg)
748 {
749 FsmChangeState(fi, ST_L1_F3);
750 }
751
752 static void l1_go_f5(struct FsmInst *fi, int event, void *arg)
753 {
754 FsmChangeState(fi, ST_L1_F3);
755 }
756
757 static void l1_go_f6(struct FsmInst *fi, int event, void *arg)
758 {
759 FsmChangeState(fi, ST_L1_F6);
760 }
761
762 static void l1_go_f6_deact_ind(struct FsmInst *fi, int event, void *arg)
763 {
764 struct hfcpci_adapter *adapter = fi->userdata;
765
766 FsmChangeState(fi, ST_L1_F6);
767 D_L1L2(adapter, PH_DEACTIVATE | INDICATION, NULL);
768 }
769
770 static void l1_go_f7(struct FsmInst *fi, int event, void *arg)
771 {
772 FsmChangeState(fi, ST_L1_F7);
773 }
774
775 static void l1_go_f7_act_ind(struct FsmInst *fi, int event, void *arg)
776 {
777 struct hfcpci_adapter *adapter = fi->userdata;
778
779 FsmChangeState(fi, ST_L1_F7);
780 D_L1L2(adapter, PH_ACTIVATE | INDICATION, NULL);
781 }
782
783 static void l1_go_f8(struct FsmInst *fi, int event, void *arg)
784 {
785 FsmChangeState(fi, ST_L1_F8);
786 }
787
788 static void l1_go_f8_deact_ind(struct FsmInst *fi, int event, void *arg)
789 {
790 struct hfcpci_adapter *adapter = fi->userdata;
791
792 FsmChangeState(fi, ST_L1_F8);
793 D_L1L2(adapter, PH_DEACTIVATE | INDICATION, NULL);
794 }
795
796 static void l1_act_req(struct FsmInst *fi, int event, void *arg)
797 {
798 struct hfcpci_adapter *adapter = fi->userdata;
799
800 hfcpci_writeb(adapter, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION, HFCPCI_STATES);
801 }
802
803 static struct FsmNode L1FnList[] __initdata =
804 {
805 {ST_L1_F2, EV_PH_F3, l1_go_f3},
806 {ST_L1_F2, EV_PH_F6, l1_go_f6},
807 {ST_L1_F2, EV_PH_F7, l1_go_f7_act_ind},
808
809 {ST_L1_F3, EV_PH_F3, l1_ignore},
810 {ST_L1_F3, EV_PH_F4, l1_go_f4},
811 {ST_L1_F3, EV_PH_F5, l1_go_f5},
812 {ST_L1_F3, EV_PH_F6, l1_go_f6},
813 {ST_L1_F3, EV_PH_F7, l1_go_f7_act_ind},
814 {ST_L1_F3, EV_PH_ACTIVATE_REQ, l1_act_req},
815
816 {ST_L1_F4, EV_PH_F7, l1_ignore},
817 {ST_L1_F4, EV_PH_F3, l1_go_f3},
818 {ST_L1_F4, EV_PH_F5, l1_go_f5},
819 {ST_L1_F4, EV_PH_F6, l1_go_f6},
820 {ST_L1_F4, EV_PH_F7, l1_go_f7},
821
822 {ST_L1_F5, EV_PH_F7, l1_ignore},
823 {ST_L1_F5, EV_PH_F3, l1_go_f3},
824 {ST_L1_F5, EV_PH_F6, l1_go_f6},
825 {ST_L1_F5, EV_PH_F7, l1_go_f7},
826
827 {ST_L1_F6, EV_PH_F7, l1_ignore},
828 {ST_L1_F6, EV_PH_F3, l1_go_f3},
829 {ST_L1_F6, EV_PH_F7, l1_go_f7_act_ind},
830 {ST_L1_F6, EV_PH_F8, l1_go_f8},
831
832 {ST_L1_F7, EV_PH_F7, l1_ignore},
833 {ST_L1_F7, EV_PH_F3, l1_go_f3_deact_ind},
834 {ST_L1_F7, EV_PH_F6, l1_go_f6_deact_ind},
835 {ST_L1_F7, EV_PH_F8, l1_go_f8_deact_ind},
836
837 {ST_L1_F8, EV_PH_F7, l1_ignore},
838 {ST_L1_F8, EV_PH_F3, l1_go_f3},
839 {ST_L1_F8, EV_PH_F6, l1_go_f6},
840 {ST_L1_F8, EV_PH_F7, l1_go_f7_act_ind},
841
842 };
843
844 static void l1m_debug(struct FsmInst *fi, char *fmt, ...)
845 {
846 va_list args;
847 char buf[256];
848
849 va_start(args, fmt);
850 vsprintf(buf, fmt, args);
851 DBG(DBG_L1M, "%s", buf);
852 va_end(args);
853 }
854
855 // ----------------------------------------------------------------------
856 // clear FIFOs
857
858 static void
859 hfcpci_clear_d_rx_fifo(struct hfcpci_adapter *adapter)
860 {
861 u8 fifo_state;
862
863 DBG(DBG_D_RECV, "");
864
865 fifo_state = adapter->fifo_en & HFCPCI_FIFOEN_DRX;
866
867 if (fifo_state) { // enabled
868 // XXX locking
869 adapter->fifo_en &= ~fifo_state;
870 hfcpci_writeb(adapter, adapter->fifo_en, HFCPCI_FIFO_EN);
871 }
872
873 adapter->last_fcnt = 0;
874
875 set_d_rx_z1(adapter, MAX_D_FRAMES - 1, D_FIFO_END - 1);
876 set_d_rx_z2(adapter, MAX_D_FRAMES - 1, D_FIFO_END - 1);
877 mb();
878 set_d_rx_f1(adapter, MAX_D_FRAMES - 1);
879 set_d_rx_f2(adapter, MAX_D_FRAMES - 1);
880 mb();
881
882 if (fifo_state) {
883 adapter->fifo_en |= fifo_state;
884 hfcpci_writeb(adapter, adapter->fifo_en, HFCPCI_FIFO_EN);
885 }
886 }
887
888 static void
889 hfcpci_clear_b_rx_fifo(struct hfcpci_bcs *bcs)
890 {
891 struct hfcpci_adapter *adapter = bcs->adapter;
892 int nr = bcs->channel;
893 u8 fifo_state;
894
895 DBG(DBG_B_RECV, "");
896
897 fifo_state = adapter->fifo_en &
898 (nr ? HFCPCI_FIFOEN_B2RX : HFCPCI_FIFOEN_B1RX);
899
900 if (fifo_state) { // enabled
901 adapter->fifo_en &= ~fifo_state;
902 hfcpci_writeb(adapter, adapter->fifo_en, HFCPCI_FIFO_EN);
903 }
904
905 bcs->last_fcnt = 0;
906
907 set_b_rx_z1(bcs, MAX_B_FRAMES - 1, B_FIFO_END - 1);
908 set_b_rx_z2(bcs, MAX_B_FRAMES - 1, B_FIFO_END - 1);
909 mb();
910 set_b_rx_f1(bcs, MAX_B_FRAMES - 1);
911 set_b_rx_f2(bcs, MAX_B_FRAMES - 1);
912 mb();
913
914 if (fifo_state) {
915 adapter->fifo_en |= fifo_state;
916 hfcpci_writeb(adapter, adapter->fifo_en, HFCPCI_FIFO_EN);
917 }
918 }
919
920 // XXX clear d_tx_fifo?
921
922 static void
923 hfcpci_clear_b_tx_fifo(struct hfcpci_bcs *bcs)
924 {
925 struct hfcpci_adapter *adapter = bcs->adapter;
926 int nr = bcs->channel;
927 u8 fifo_state;
928
929 fifo_state = adapter->fifo_en &
930 (nr ? HFCPCI_FIFOEN_B2TX : HFCPCI_FIFOEN_B1TX);
931
932 if (fifo_state) { // enabled
933 adapter->fifo_en &= ~fifo_state;
934 hfcpci_writeb(adapter, adapter->fifo_en, HFCPCI_FIFO_EN);
935 }
936
937 bcs->last_fcnt = 0;
938
939 set_b_rx_z1(bcs, MAX_B_FRAMES - 1, B_FIFO_END - 1);
940 set_b_rx_z2(bcs, MAX_B_FRAMES - 1, B_FIFO_END - 1);
941 mb();
942 set_b_rx_f1(bcs, MAX_B_FRAMES - 1);
943 set_b_rx_f2(bcs, MAX_B_FRAMES - 1);
944 mb();
945
946 if (fifo_state) {
947 adapter->fifo_en |= fifo_state;
948 hfcpci_writeb(adapter, adapter->fifo_en, HFCPCI_FIFO_EN);
949 }
950 }
951
952 // ----------------------------------------------------------------------
953 // receive messages from upper layers
954
955 static void
956 hfcpci_d_l2l1(struct hisax_if *ifc, int pr, void *arg)
957 {
958 struct hfcpci_adapter *adapter = ifc->priv;
959 struct sk_buff *skb = arg;
960
961 DBG(DBG_PR, "pr %#x", pr);
962
963 switch (pr) {
964 case PH_ACTIVATE | REQUEST:
965 FsmEvent(&adapter->l1m, EV_PH_ACTIVATE_REQ, NULL);
966 break;
967 case PH_DEACTIVATE | REQUEST:
968 FsmEvent(&adapter->l1m, EV_PH_DEACTIVATE_REQ, NULL);
969 break;
970 case PH_DATA | REQUEST:
971 DBG(DBG_PR, "PH_DATA REQUEST len %d", skb->len);
972 DBG_SKB(DBG_D_XMIT, skb);
973 if (adapter->l1m.state != ST_L1_F7) {
974 DBG(DBG_WARN, "L1 wrong state %d", adapter->l1m.state);
975 break;
976 }
977 if (adapter->tx_skb)
978 BUG();
979
980 adapter->tx_skb = skb;
981 hfcpci_fill_d_fifo(adapter);
982 break;
983 }
984 }
985
986 static void
987 hfcpci_b_l2l1(struct hisax_if *ifc, int pr, void *arg)
988 {
989 struct hfcpci_bcs *bcs = ifc->priv;
990 struct sk_buff *skb = arg;
991 int mode;
992
993 DBG(DBG_PR, "pr %#x", pr);
994
995 switch (pr) {
996 case PH_DATA | REQUEST:
997 if (bcs->tx_skb)
998 BUG();
999
1000 bcs->tx_skb = skb;
1001 DBG_SKB(DBG_B_XMIT, skb);
1002 hfcpci_fill_b_fifo(bcs);
1003 break;
1004 case PH_ACTIVATE | REQUEST:
1005 mode = (int) arg;
1006 DBG(DBG_PR,"B%d,PH_ACTIVATE_REQUEST %d", bcs->channel + 1, mode);
1007 hfcpci_b_mode(bcs, mode);
1008 B_L1L2(bcs, PH_ACTIVATE | INDICATION, NULL);
1009 break;
1010 case PH_DEACTIVATE | REQUEST:
1011 DBG(DBG_PR,"B%d,PH_DEACTIVATE_REQUEST", bcs->channel + 1);
1012 hfcpci_b_mode(bcs, L1_MODE_NULL);
1013 B_L1L2(bcs, PH_DEACTIVATE | INDICATION, NULL);
1014 break;
1015 }
1016 }
1017
1018 // ----------------------------------------------------------------------
1019 // receive IRQ
1020
1021 static inline void
1022 hfcpci_d_recv_irq(struct hfcpci_adapter *adapter)
1023 {
1024 struct sk_buff *skb;
1025 char *fifo_adr = adapter->fifo + 0x4000;
1026 char *p;
1027 int cnt, fcnt;
1028 int loop = 5;
1029 u8 f1, f2;
1030 u16 z1, z2;
1031
1032 while (loop-- > 0) {
1033 f1 = get_d_rx_f1(adapter);
1034 f2 = get_d_rx_f2(adapter);
1035 DBG(DBG_D_RECV, "f1 %#x f2 %#x", f1, f2);
1036
1037 fcnt = f1 - f2;
1038 if (fcnt < 0)
1039 fcnt += 16;
1040
1041 if (!fcnt)
1042 return;
1043
1044 if (fcnt < adapter->last_fcnt)
1045 /* overrun */
1046 hfcpci_clear_d_rx_fifo(adapter);
1047 // XXX init last_fcnt
1048
1049 z1 = get_d_rx_z1(adapter, f2);
1050 z2 = get_d_rx_z2(adapter, f2);
1051 DBG(DBG_D_RECV, "z1 %#x z2 %#x", z1, z2);
1052
1053 cnt = z1 - z2;
1054 if (cnt < 0)
1055 cnt += D_FIFO_SIZE;
1056 cnt++;
1057
1058 if (cnt < 4) {
1059 DBG(DBG_WARN, "frame too short");
1060 goto next;
1061 }
1062 if (fifo_adr[z1] != 0) {
1063 DBG(DBG_WARN, "CRC error");
1064 goto next;
1065 }
1066 cnt -= 3;
1067 skb = dev_alloc_skb(cnt);
1068 if (!skb) {
1069 DBG(DBG_WARN, "no mem");
1070 goto next;
1071 }
1072 p = skb_put(skb, cnt);
1073 if (z2 + cnt <= D_FIFO_END) {
1074 memcpy(p, fifo_adr + z2, cnt);
1075 } else {
1076 memcpy(p, fifo_adr + z2, D_FIFO_END - z2);
1077 memcpy(p + (D_FIFO_END - z2), fifo_adr + D_FIFO_START,
1078 cnt - (D_FIFO_END - z2));
1079 }
1080
1081 DBG_SKB(DBG_D_RECV, skb);
1082 D_L1L2(adapter, PH_DATA | INDICATION, skb);
1083
1084 next:
1085 if (++z1 >= D_FIFO_END)
1086 z1 -= D_FIFO_START;
1087
1088 f2 = (f2 + 1) & (MAX_D_FRAMES - 1);
1089 mb();
1090 set_d_rx_z2(adapter, f2, z1);
1091 mb();
1092 set_d_rx_f2(adapter, f2);
1093
1094 adapter->last_fcnt = fcnt - 1;
1095 }
1096 }
1097
1098 static inline void
1099 hfcpci_b_recv_hdlc_irq(struct hfcpci_adapter *adapter, int nr)
1100 {
1101 struct hfcpci_bcs *bcs = &adapter->bcs[nr];
1102 struct sk_buff *skb;
1103 char *fifo_adr = adapter->fifo + (nr ? 0x6000 : 0x4000);
1104 char *p;
1105 int cnt, fcnt;
1106 int loop = 5;
1107 u8 f1, f2;
1108 u16 z1, z2;
1109
1110 while (loop-- > 0) {
1111 f1 = get_b_rx_f1(bcs);
1112 f2 = get_b_rx_f2(bcs);
1113 DBG(DBG_B_RECV, "f1 %d f2 %d", f1, f2);
1114
1115 fcnt = f1 - f2;
1116 if (fcnt < 0)
1117 fcnt += 32;
1118
1119 if (!fcnt)
1120 return;
1121
1122 if (fcnt < bcs->last_fcnt)
1123 /* overrun */
1124 hfcpci_clear_b_rx_fifo(bcs);
1125 // XXX init last_fcnt
1126
1127 z1 = get_b_rx_z1(bcs, f2);
1128 z2 = get_b_rx_z2(bcs, f2);
1129 DBG(DBG_B_RECV, "z1 %d z2 %d", z1, z2);
1130
1131 cnt = z1 - z2;
1132 if (cnt < 0)
1133 cnt += B_FIFO_SIZE;
1134 cnt++;
1135
1136 if (cnt < 4) {
1137 DBG(DBG_WARN, "frame too short");
1138 goto next;
1139 }
1140 if (fifo_adr[z1] != 0) {
1141 DBG(DBG_WARN, "CRC error");
1142 goto next;
1143 }
1144 cnt -= 3;
1145 skb = dev_alloc_skb(cnt);
1146 if (!skb) {
1147 DBG(DBG_WARN, "no mem");
1148 goto next;
1149 }
1150 p = skb_put(skb, cnt);
1151 if (z2 + cnt <= B_FIFO_END) {
1152 memcpy(p, fifo_adr + z2, cnt);
1153 } else {
1154 memcpy(p, fifo_adr + z2, B_FIFO_END - z2);
1155 memcpy(p + (B_FIFO_END - z2), fifo_adr + B_FIFO_START,
1156 cnt - (B_FIFO_END - z2));
1157 }
1158
1159 DBG_SKB(DBG_B_RECV, skb);
1160 B_L1L2(bcs, PH_DATA | INDICATION, skb);
1161
1162 next:
1163 if (++z1 >= B_FIFO_END)
1164 z1 -= B_FIFO_SIZE;
1165
1166 f2 = (f2 + 1) & (MAX_B_FRAMES - 1);
1167 mb();
1168 set_b_rx_z2(bcs, f2, z1);
1169 mb();
1170 set_b_rx_f2(bcs, f2);
1171
1172 bcs->last_fcnt = fcnt - 1;
1173 }
1174 }
1175
1176 static inline void
1177 hfcpci_b_recv_trans_irq(struct hfcpci_adapter *adapter, int nr)
1178 {
1179 struct hfcpci_bcs *bcs = &adapter->bcs[nr];
1180 struct sk_buff *skb;
1181 char *fifo_adr = adapter->fifo + (nr ? 0x6000 : 0x4000);
1182 char *p;
1183 int cnt;
1184 int loop = 5;
1185 u8 f1, f2;
1186 u16 z1, z2;
1187
1188 f1 = get_b_rx_f1(bcs);
1189 f2 = get_b_rx_f2(bcs);
1190
1191 if (f1 != f2)
1192 BUG();
1193
1194 while (loop-- > 0) {
1195 z1 = get_b_rx_z1(bcs, f2);
1196 z2 = get_b_rx_z2(bcs, f2);
1197
1198 cnt = z1 - z2;
1199 if (!cnt)
1200 /* no data available */
1201 return;
1202
1203 if (cnt < 0)
1204 cnt += B_FIFO_SIZE;
1205
1206 if (cnt > HFCPCI_BTRANS_THRESHOLD)
1207 cnt = HFCPCI_BTRANS_THRESHOLD;
1208
1209 skb = dev_alloc_skb(cnt);
1210 if (!skb) {
1211 DBG(DBG_WARN, "no mem");
1212 goto next;
1213 }
1214
1215 p = skb_put(skb, cnt);
1216 if (z2 + cnt <= 0x2000) {
1217 memcpy(p, fifo_adr + z2, cnt);
1218 } else {
1219 memcpy(p, fifo_adr + z2, 0x2000 - z2);
1220 p += 0x2000 - z2;
1221 memcpy(p, fifo_adr + 0x200, cnt - (0x2000 - z2));
1222 }
1223
1224 DBG_SKB(DBG_B_RECV, skb);
1225 B_L1L2(bcs, PH_DATA | INDICATION, skb);
1226
1227 next:
1228 z2 += cnt;
1229 if (z2 >= 0x2000)
1230 z2 -= B_FIFO_SIZE;
1231
1232 mb();
1233 set_b_rx_z2(bcs, f2, z2);
1234 // XXX always receive buffers of a given size
1235 }
1236 }
1237
1238 static inline void
1239 hfcpci_b_recv_irq(struct hfcpci_adapter *adapter, int nr)
1240 {
1241 DBG(DBG_B_RECV, "");
1242
1243 switch (adapter->bcs[nr].mode) {
1244 case L1_MODE_NULL:
1245 DBG(DBG_WARN, "?");
1246 break;
1247
1248 case L1_MODE_HDLC:
1249 hfcpci_b_recv_hdlc_irq(adapter, nr);
1250 break;
1251
1252 case L1_MODE_TRANS:
1253 hfcpci_b_recv_trans_irq(adapter, nr);
1254 break;
1255 }
1256 }
1257
1258 // ----------------------------------------------------------------------
1259 // transmit IRQ
1260
1261 // XXX make xmit FIFO deeper than 1
1262
1263 static inline void
1264 hfcpci_d_xmit_irq(struct hfcpci_adapter *adapter)
1265 {
1266 struct sk_buff *skb;
1267
1268 DBG(DBG_D_XMIT, "");
1269
1270 skb = adapter->tx_skb;
1271 if (!skb) {
1272 DBG(DBG_WARN, "?");
1273 return;
1274 }
1275
1276 adapter->tx_skb = NULL;
1277 D_L1L2(adapter, PH_DATA | CONFIRM, (void *) skb->truesize);
1278 dev_kfree_skb_irq(skb);
1279 }
1280
1281 static inline void
1282 hfcpci_b_xmit_irq(struct hfcpci_adapter *adapter, int nr)
1283 {
1284 struct hfcpci_bcs *bcs = &adapter->bcs[nr];
1285 struct sk_buff *skb;
1286
1287 DBG(DBG_B_XMIT, "");
1288
1289 skb = bcs->tx_skb;
1290 if (!skb) {
1291 DBG(DBG_WARN, "?");
1292 return;
1293 }
1294
1295 bcs->tx_skb = NULL;
1296 B_L1L2(bcs, PH_DATA | CONFIRM, skb);
1297 }
1298
1299 // ----------------------------------------------------------------------
1300 // Layer 1 state change IRQ
1301
1302 static inline void
1303 hfcpci_state_irq(struct hfcpci_adapter *adapter)
1304 {
1305 u8 val;
1306
1307 val = hfcpci_readb(adapter, HFCPCI_STATES);
1308 DBG(DBG_L1M, "STATES %#x", val);
1309 FsmEvent(&adapter->l1m, val & 0xf, NULL);
1310 }
1311
1312 // ----------------------------------------------------------------------
1313 // Timer IRQ
1314
1315 static inline void
1316 hfcpci_timer_irq(struct hfcpci_adapter *adapter)
1317 {
1318 hfcpci_writeb(adapter, adapter->ctmt | HFCPCI_CLTIMER, HFCPCI_CTMT);
1319 }
1320
1321 // ----------------------------------------------------------------------
1322 // IRQ handler
1323
1324 static irqreturn_t
1325 hfcpci_irq(int intno, void *dev, struct pt_regs *regs)
1326 {
1327 struct hfcpci_adapter *adapter = dev;
1328 int loop = 15;
1329 u8 val, stat;
1330
1331 if (!(adapter->int_m2 & 0x08))
1332 return IRQ_NONE; /* not initialised */ // XX
1333
1334 stat = hfcpci_readb(adapter, HFCPCI_STATUS);
1335 if (!(stat & HFCPCI_ANYINT))
1336 return IRQ_NONE;
1337
1338 spin_lock(&adapter->hw_lock);
1339 while (loop-- > 0) {
1340 val = hfcpci_readb(adapter, HFCPCI_INT_S1);
1341 DBG(DBG_IRQ, "stat %02x s1 %02x", stat, val);
1342 val &= adapter->int_m1;
1343
1344 if (!val)
1345 break;
1346
1347 if (val & 0x08)
1348 hfcpci_b_recv_irq(adapter, 0);
1349
1350 if (val & 0x10)
1351 hfcpci_b_recv_irq(adapter, 1);
1352
1353 if (val & 0x01)
1354 hfcpci_b_xmit_irq(adapter, 0);
1355
1356 if (val & 0x02)
1357 hfcpci_b_xmit_irq(adapter, 1);
1358
1359 if (val & 0x20)
1360 hfcpci_d_recv_irq(adapter);
1361
1362 if (val & 0x04)
1363 hfcpci_d_xmit_irq(adapter);
1364
1365 if (val & 0x40)
1366 hfcpci_state_irq(adapter);
1367
1368 if (val & 0x80)
1369 hfcpci_timer_irq(adapter);
1370 }
1371 spin_unlock(&adapter->hw_lock);
1372 return IRQ_HANDLED;
1373 }
1374
1375 // ----------------------------------------------------------------------
1376 // reset hardware
1377
1378 static void
1379 hfcpci_reset(struct hfcpci_adapter *adapter)
1380 {
1381 /* disable all interrupts */
1382 adapter->int_m1 = 0;
1383 adapter->int_m2 = 0;
1384 hfcpci_writeb(adapter, adapter->int_m1, HFCPCI_INT_M1);
1385 hfcpci_writeb(adapter, adapter->int_m2, HFCPCI_INT_M2);
1386
1387 /* reset */
1388 hfcpci_writeb(adapter, HFCPCI_RESET, HFCPCI_CIRM);
1389 set_current_state(TASK_UNINTERRUPTIBLE);
1390 schedule_timeout((30 * HZ) / 1000);
1391 hfcpci_writeb(adapter, 0, HFCPCI_CIRM);
1392 set_current_state(TASK_UNINTERRUPTIBLE);
1393 schedule_timeout((20 * HZ) / 1000);
1394 if (hfcpci_readb(adapter, HFCPCI_STATUS) & 2) // XX
1395 printk(KERN_WARNING "HFC-PCI init bit busy\n");
1396 }
1397
1398 // ----------------------------------------------------------------------
1399 // init hardware
1400
1401 static void
1402 hfcpci_hw_init(struct hfcpci_adapter *adapter)
1403 {
1404 adapter->fifo_en = 0x30; /* only D fifos enabled */ // XX
1405 hfcpci_writeb(adapter, adapter->fifo_en, HFCPCI_FIFO_EN);
1406
1407 /* no echo connect , threshold */
1408 adapter->trm = HFCPCI_BTRANS_THRESMASK;
1409 hfcpci_writeb(adapter, adapter->trm, HFCPCI_TRM);
1410
1411 /* ST-Bit delay for TE-Mode */
1412 hfcpci_writeb(adapter, CLKDEL_TE, HFCPCI_CLKDEL);
1413
1414 /* S/T Auto awake */
1415 adapter->sctrl_e = HFCPCI_AUTO_AWAKE;
1416 hfcpci_writeb(adapter, adapter->sctrl_e, HFCPCI_SCTRL_E);
1417
1418 /* no exchange */
1419 adapter->bswapped = 0;
1420 /* we are in TE mode */
1421 adapter->nt_mode = 0;
1422
1423 adapter->ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
1424 hfcpci_writeb(adapter, adapter->ctmt, HFCPCI_CTMT);
1425
1426 adapter->int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
1427 HFCPCI_INTS_L1STATE;
1428 hfcpci_writeb(adapter, adapter->int_m1, HFCPCI_INT_M1);
1429
1430 /* clear already pending ints */
1431 hfcpci_readb(adapter, HFCPCI_INT_S1);
1432
1433 adapter->l1m.state = 2;
1434 hfcpci_writeb(adapter, HFCPCI_LOAD_STATE | 2, HFCPCI_STATES); // XX /* HFC ST 2 */
1435 udelay(10);
1436 hfcpci_writeb(adapter, 2, HFCPCI_STATES); /* HFC ST 2 */
1437
1438 /* HFC Master Mode */
1439 adapter->mst_m = HFCPCI_MASTER;
1440 hfcpci_writeb(adapter, adapter->mst_m, HFCPCI_MST_MODE);
1441
1442 /* set tx_lo mode, error in datasheet ! */
1443 adapter->sctrl = 0x40;
1444 hfcpci_writeb(adapter, adapter->sctrl, HFCPCI_SCTRL);
1445
1446 adapter->sctrl_r = 0;
1447 hfcpci_writeb(adapter, adapter->sctrl_r, HFCPCI_SCTRL_R);
1448
1449 // XXX
1450 /* Init GCI/IOM2 in master mode */
1451 /* Slots 0 and 1 are set for B-chan 1 and 2 */
1452 /* D- and monitor/CI channel are not enabled */
1453 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
1454 /* STIO2 is used as data input, B1+B2 from IOM->ST */
1455 /* ST B-channel send disabled -> continous 1s */
1456 /* The IOM slots are always enabled */
1457 adapter->conn = 0; /* set data flow directions */
1458 hfcpci_writeb(adapter, adapter->conn, HFCPCI_CONNECT);
1459 hfcpci_writeb(adapter, 0x80, HFCPCI_B1_SSL); /* B1-Slot 0 STIO1 out enabled */
1460 hfcpci_writeb(adapter, 0x81, HFCPCI_B2_SSL); /* B2-Slot 1 STIO1 out enabled */
1461 hfcpci_writeb(adapter, 0x80, HFCPCI_B1_RSL); /* B1-Slot 0 STIO2 in enabled */
1462 hfcpci_writeb(adapter, 0x81, HFCPCI_B2_RSL); /* B2-Slot 1 STIO2 in enabled */
1463
1464 /* Finally enable IRQ output */
1465 adapter->int_m2 = HFCPCI_IRQ_ENABLE;
1466 hfcpci_writeb(adapter, adapter->int_m2, HFCPCI_INT_M2);
1467
1468 hfcpci_readb(adapter, HFCPCI_INT_S2);
1469 }
1470
1471 // ----------------------------------------------------------------------
1472 // probe / remove
1473
1474 static struct hfcpci_adapter * __devinit
1475 new_adapter(struct pci_dev *pdev)
1476 {
1477 struct hfcpci_adapter *adapter;
1478 struct hisax_b_if *b_if[2];
1479 int i;
1480
1481 adapter = kmalloc(sizeof(struct hfcpci_adapter), GFP_KERNEL);
1482 if (!adapter)
1483 return NULL;
1484
1485 memset(adapter, 0, sizeof(struct hfcpci_adapter));
1486
1487 adapter->d_if.owner = THIS_MODULE;
1488 adapter->d_if.ifc.priv = adapter;
1489 adapter->d_if.ifc.l2l1 = hfcpci_d_l2l1;
1490
1491 for (i = 0; i < 2; i++) {
1492 adapter->bcs[i].adapter = adapter;
1493 adapter->bcs[i].channel = i;
1494 adapter->bcs[i].b_if.ifc.priv = &adapter->bcs[i];
1495 adapter->bcs[i].b_if.ifc.l2l1 = hfcpci_b_l2l1;
1496 }
1497
1498 pci_set_drvdata(pdev, adapter);
1499
1500 for (i = 0; i < 2; i++)
1501 b_if[i] = &adapter->bcs[i].b_if;
1502
1503 hisax_register(&adapter->d_if, b_if, "hfcpci", protocol);
1504
1505 return adapter;
1506 }
1507
1508 static void delete_adapter(struct hfcpci_adapter *adapter)
1509 {
1510 hisax_unregister(&adapter->d_if);
1511 kfree(adapter);
1512 }
1513
1514 static int __devinit hfcpci_probe(struct pci_dev *pdev,
1515 const struct pci_device_id *ent)
1516 {
1517 struct hfcpci_adapter *adapter;
1518 int retval;
1519
1520 DBG(DBG_INFO, "");
1521 retval = -ENOMEM;
1522 adapter = new_adapter(pdev);
1523 if (!adapter)
1524 goto err;
1525
1526 retval = pci_enable_device(pdev);
1527 if (retval)
1528 goto err_free;
1529
1530 adapter->irq = pdev->irq;
1531 retval = request_irq(adapter->irq, hfcpci_irq, SA_SHIRQ,
1532 "hfcpci", adapter);
1533 if (retval)
1534 goto err_free;
1535
1536 retval = -EBUSY;
1537 if (!request_mem_region(pci_resource_start(pdev, 1), 256, "hfcpci"))
1538 goto err_free_irq;
1539
1540 adapter->mmio = ioremap(pci_resource_start(pdev, 1), 256); // XX pci_io
1541 if (!adapter->mmio)
1542 goto err_release_region;
1543
1544 /* Allocate 32K for FIFOs */
1545 if (pci_set_dma_mask(pdev, 0xffffffff))
1546 goto err_unmap;
1547
1548 adapter->fifo = pci_alloc_consistent(pdev, 32768, &adapter->fifo_dma);
1549 if (!adapter->fifo)
1550 goto err_unmap;
1551
1552 pci_write_config_dword(pdev, HFCPCI_MWBA, (u32) adapter->fifo_dma);
1553 pci_set_master(pdev);
1554
1555 adapter->l1m.fsm = &l1fsm;
1556 adapter->l1m.state = ST_L1_F0;
1557 #ifdef CONFIG_HISAX_DEBUG
1558 adapter->l1m.debug = 1;
1559 #else
1560 adapter->l1m.debug = 0;
1561 #endif
1562 adapter->l1m.userdata = adapter;
1563 adapter->l1m.printdebug = l1m_debug;
1564 FsmInitTimer(&adapter->l1m, &adapter->timer);
1565
1566 hfcpci_reset(adapter);
1567 hfcpci_hw_init(adapter);
1568
1569 printk(KERN_INFO "hisax_hfcpci: found adapter %s at %s\n",
1570 (char *) ent->driver_data, pdev->slot_name);
1571
1572 return 0;
1573
1574 err_unmap:
1575 iounmap(adapter->mmio);
1576 err_release_region:
1577 release_mem_region(pci_resource_start(pdev, 1), 256);
1578 err_free_irq:
1579 free_irq(adapter->irq, adapter);
1580 err_free:
1581 delete_adapter(adapter);
1582 err:
1583 return retval;
1584 }
1585
1586 static void __devexit hfcpci_remove(struct pci_dev *pdev)
1587 {
1588 struct hfcpci_adapter *adapter = pci_get_drvdata(pdev);
1589
1590 hfcpci_reset(adapter);
1591
1592 // del_timer(&cs->hw.hfcpci.timer); XX
1593
1594 /* disable DMA */
1595 pci_disable_device(pdev);
1596 pci_write_config_dword(pdev, HFCPCI_MWBA, 0);
1597 pci_free_consistent(pdev, 32768, adapter->fifo, adapter->fifo_dma);
1598
1599 iounmap(adapter->mmio);
1600 release_mem_region(pci_resource_start(pdev, 1), 256);
1601 free_irq(adapter->irq, adapter);
1602 delete_adapter(adapter);
1603 }
1604
1605 static struct pci_driver hfcpci_driver = {
1606 .name = "hfcpci",
1607 .probe = hfcpci_probe,
1608 .remove = __devexit_p(hfcpci_remove),
1609 .id_table = hfcpci_ids,
1610 };
1611
1612 static int __init hisax_hfcpci_init(void)
1613 {
1614 int retval;
1615
1616 printk(KERN_INFO "hisax_hfcpcipnp: HFC PCI ISDN driver v0.0.1\n");
1617
1618 l1fsm.state_count = L1_STATE_COUNT;
1619 l1fsm.event_count = L1_EVENT_COUNT;
1620 l1fsm.strState = strL1State;
1621 l1fsm.strEvent = strL1Event;
1622 retval = FsmNew(&l1fsm, L1FnList, ARRAY_SIZE(L1FnList));
1623 if (retval)
1624 goto err;
1625
1626 retval = pci_module_init(&hfcpci_driver);
1627 if (retval)
1628 goto err_fsm;
1629
1630 return 0;
1631
1632 err_fsm:
1633 FsmFree(&l1fsm);
1634 err:
1635 return retval;
1636 }
1637
1638 static void __exit hisax_hfcpci_exit(void)
1639 {
1640 FsmFree(&l1fsm);
1641 pci_unregister_driver(&hfcpci_driver);
1642 }
1643
1644 module_init(hisax_hfcpci_init);
1645 module_exit(hisax_hfcpci_exit);
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