arch/mips/kernel/traps.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
   7  * Copyright (C) 1995, 1996 Paul M. Antoine
   8  * Copyright (C) 1998 Ulf Carlsson
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 2000, 01 MIPS Technologies, Inc.
  12  * Copyright (C) 2002, 2003, 2004, 2005  Maciej W. Rozycki
  13  */
  14 #include <linux/init.h>
  15 #include <linux/mm.h>
  16 #include <linux/module.h>
  17 #include <linux/sched.h>
  18 #include <linux/smp.h>
  19 #include <linux/smp_lock.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kallsyms.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/interrupt.h>
  24
  25 #include <asm/bootinfo.h>
  26 #include <asm/branch.h>
  27 #include <asm/break.h>
  28 #include <asm/cpu.h>
  29 #include <asm/dsp.h>
  30 #include <asm/fpu.h>
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/module.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/ptrace.h>
  36 #include <asm/sections.h>
  37 #include <asm/system.h>
  38 #include <asm/tlbdebug.h>
  39 #include <asm/traps.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/mmu_context.h>
  42 #include <asm/watch.h>
  43 #include <asm/types.h>
  44 #include <asm/stacktrace.h>
  45
  46 extern asmlinkage void handle_int(void);
  47 extern asmlinkage void handle_tlbm(void);
  48 extern asmlinkage void handle_tlbl(void);
  49 extern asmlinkage void handle_tlbs(void);
  50 extern asmlinkage void handle_adel(void);
  51 extern asmlinkage void handle_ades(void);
  52 extern asmlinkage void handle_ibe(void);
  53 extern asmlinkage void handle_dbe(void);
  54 extern asmlinkage void handle_sys(void);
  55 extern asmlinkage void handle_bp(void);
  56 extern asmlinkage void handle_ri(void);
  57 extern asmlinkage void handle_cpu(void);
  58 extern asmlinkage void handle_ov(void);
  59 extern asmlinkage void handle_tr(void);
  60 extern asmlinkage void handle_fpe(void);
  61 extern asmlinkage void handle_mdmx(void);
  62 extern asmlinkage void handle_watch(void);
  63 extern asmlinkage void handle_mt(void);
  64 extern asmlinkage void handle_dsp(void);
  65 extern asmlinkage void handle_mcheck(void);
  66 extern asmlinkage void handle_reserved(void);
  67
  68 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
  69         struct mips_fpu_struct *ctx, int has_fpu);
  70
  71 void (*board_be_init)(void);
  72 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
  73 void (*board_nmi_handler_setup)(void);
  74 void (*board_ejtag_handler_setup)(void);
  75 void (*board_bind_eic_interrupt)(int irq, int regset);
  76
  77
  78 static void show_raw_backtrace(unsigned long reg29)
  79 {
  80         unsigned long *sp = (unsigned long *)reg29;
  81         unsigned long addr;
  82
  83         printk("Call Trace:");
  84 #ifdef CONFIG_KALLSYMS
  85         printk("\n");
  86 #endif
  87         while (!kstack_end(sp)) {
  88                 addr = *sp++;
  89                 if (__kernel_text_address(addr))
  90                         print_ip_sym(addr);
  91         }
  92         printk("\n");
  93 }
  94
  95 #ifdef CONFIG_KALLSYMS
  96 int raw_show_trace;
  97 static int __init set_raw_show_trace(char *str)
  98 {
  99         raw_show_trace = 1;
 100         return 1;
 101 }
 102 __setup("raw_show_trace", set_raw_show_trace);
 103 #endif
 104
 105 static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
 106 {
 107         unsigned long sp = regs->regs[29];
 108         unsigned long ra = regs->regs[31];
 109         unsigned long pc = regs->cp0_epc;
 110
 111         if (raw_show_trace || !__kernel_text_address(pc)) {
 112                 show_raw_backtrace(sp);
 113                 return;
 114         }
 115         printk("Call Trace:\n");
 116         do {
 117                 print_ip_sym(pc);
 118                 pc = unwind_stack(task, &sp, pc, &ra);
 119         } while (pc);
 120         printk("\n");
 121 }
 122
 123 /*
 124  * This routine abuses get_user()/put_user() to reference pointers
 125  * with at least a bit of error checking ...
 126  */
 127 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
 128 {
 129         const int field = 2 * sizeof(unsigned long);
 130         long stackdata;
 131         int i;
 132         unsigned long *sp = (unsigned long *)regs->regs[29];
 133
 134         printk("Stack :");
 135         i = 0;
 136         while ((unsigned long) sp & (PAGE_SIZE - 1)) {
 137                 if (i && ((i % (64 / field)) == 0))
 138                         printk("\n       ");
 139                 if (i > 39) {
 140                         printk(" ...");
 141                         break;
 142                 }
 143
 144                 if (__get_user(stackdata, sp++)) {
 145                         printk(" (Bad stack address)");
 146                         break;
 147                 }
 148
 149                 printk(" %0*lx", field, stackdata);
 150                 i++;
 151         }
 152         printk("\n");
 153         show_backtrace(task, regs);
 154 }
 155
 156 void show_stack(struct task_struct *task, unsigned long *sp)
 157 {
 158         struct pt_regs regs;
 159         if (sp) {
 160                 regs.regs[29] = (unsigned long)sp;
 161                 regs.regs[31] = 0;
 162                 regs.cp0_epc = 0;
 163         } else {
 164                 if (task && task != current) {
 165                         regs.regs[29] = task->thread.reg29;
 166                         regs.regs[31] = 0;
 167                         regs.cp0_epc = task->thread.reg31;
 168                 } else {
 169                         prepare_frametrace(&regs);
 170                 }
 171         }
 172         show_stacktrace(task, &regs);
 173 }
 174
 175 /*
 176  * The architecture-independent dump_stack generator
 177  */
 178 void dump_stack(void)
 179 {
 180         struct pt_regs regs;
 181
 182         prepare_frametrace(&regs);
 183         show_backtrace(current, &regs);
 184 }
 185
 186 EXPORT_SYMBOL(dump_stack);
 187
 188 void show_code(unsigned int *pc)
 189 {
 190         long i;
 191
 192         printk("\nCode:");
 193
 194         for(i = -3 ; i < 6 ; i++) {
 195                 unsigned int insn;
 196                 if (__get_user(insn, pc + i)) {
 197                         printk(" (Bad address in epc)\n");
 198                         break;
 199                 }
 200                 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
 201         }
 202 }
 203
 204 void show_regs(struct pt_regs *regs)
 205 {
 206         const int field = 2 * sizeof(unsigned long);
 207         unsigned int cause = regs->cp0_cause;
 208         int i;
 209
 210         printk("Cpu %d\n", smp_processor_id());
 211
 212         /*
 213          * Saved main processor registers
 214          */
 215         for (i = 0; i < 32; ) {
 216                 if ((i % 4) == 0)
 217                         printk("$%2d   :", i);
 218                 if (i == 0)
 219                         printk(" %0*lx", field, 0UL);
 220                 else if (i == 26 || i == 27)
 221                         printk(" %*s", field, "");
 222                 else
 223                         printk(" %0*lx", field, regs->regs[i]);
 224
 225                 i++;
 226                 if ((i % 4) == 0)
 227                         printk("\n");
 228         }
 229
 230         printk("Hi    : %0*lx\n", field, regs->hi);
 231         printk("Lo    : %0*lx\n", field, regs->lo);
 232
 233         /*
 234          * Saved cp0 registers
 235          */
 236         printk("epc   : %0*lx ", field, regs->cp0_epc);
 237         print_symbol("%s ", regs->cp0_epc);
 238         printk("    %s\n", print_tainted());
 239         printk("ra    : %0*lx ", field, regs->regs[31]);
 240         print_symbol("%s\n", regs->regs[31]);
 241
 242         printk("Status: %08x    ", (uint32_t) regs->cp0_status);
 243
 244         if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
 245                 if (regs->cp0_status & ST0_KUO)
 246                         printk("KUo ");
 247                 if (regs->cp0_status & ST0_IEO)
 248                         printk("IEo ");
 249                 if (regs->cp0_status & ST0_KUP)
 250                         printk("KUp ");
 251                 if (regs->cp0_status & ST0_IEP)
 252                         printk("IEp ");
 253                 if (regs->cp0_status & ST0_KUC)
 254                         printk("KUc ");
 255                 if (regs->cp0_status & ST0_IEC)
 256                         printk("IEc ");
 257         } else {
 258                 if (regs->cp0_status & ST0_KX)
 259                         printk("KX ");
 260                 if (regs->cp0_status & ST0_SX)
 261                         printk("SX ");
 262                 if (regs->cp0_status & ST0_UX)
 263                         printk("UX ");
 264                 switch (regs->cp0_status & ST0_KSU) {
 265                 case KSU_USER:
 266                         printk("USER ");
 267                         break;
 268                 case KSU_SUPERVISOR:
 269                         printk("SUPERVISOR ");
 270                         break;
 271                 case KSU_KERNEL:
 272                         printk("KERNEL ");
 273                         break;
 274                 default:
 275                         printk("BAD_MODE ");
 276                         break;
 277                 }
 278                 if (regs->cp0_status & ST0_ERL)
 279                         printk("ERL ");
 280                 if (regs->cp0_status & ST0_EXL)
 281                         printk("EXL ");
 282                 if (regs->cp0_status & ST0_IE)
 283                         printk("IE ");
 284         }
 285         printk("\n");
 286
 287         printk("Cause : %08x\n", cause);
 288
 289         cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 290         if (1 <= cause && cause <= 5)
 291                 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
 292
 293         printk("PrId  : %08x\n", read_c0_prid());
 294 }
 295
 296 void show_registers(struct pt_regs *regs)
 297 {
 298         show_regs(regs);
 299         print_modules();
 300         printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
 301                 current->comm, current->pid, current_thread_info(), current);
 302         show_stacktrace(current, regs);
 303         show_code((unsigned int *) regs->cp0_epc);
 304         printk("\n");
 305 }
 306
 307 static DEFINE_SPINLOCK(die_lock);
 308
 309 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
 310 {
 311         static int die_counter;
 312 #ifdef CONFIG_MIPS_MT_SMTC
 313         unsigned long dvpret = dvpe();
 314 #endif /* CONFIG_MIPS_MT_SMTC */
 315
 316         console_verbose();
 317         spin_lock_irq(&die_lock);
 318         bust_spinlocks(1);
 319 #ifdef CONFIG_MIPS_MT_SMTC
 320         mips_mt_regdump(dvpret);
 321 #endif /* CONFIG_MIPS_MT_SMTC */
 322         printk("%s[#%d]:\n", str, ++die_counter);
 323         show_registers(regs);
 324         spin_unlock_irq(&die_lock);
 325
 326         if (in_interrupt())
 327                 panic("Fatal exception in interrupt");
 328
 329         if (panic_on_oops) {
 330                 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
 331                 ssleep(5);
 332                 panic("Fatal exception");
 333         }
 334
 335         do_exit(SIGSEGV);
 336 }
 337
 338 extern const struct exception_table_entry __start___dbe_table[];
 339 extern const struct exception_table_entry __stop___dbe_table[];
 340
 341 void __declare_dbe_table(void)
 342 {
 343         __asm__ __volatile__(
 344         ".section\t__dbe_table,\"a\"\n\t"
 345         ".previous"
 346         );
 347 }
 348
 349 /* Given an address, look for it in the exception tables. */
 350 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
 351 {
 352         const struct exception_table_entry *e;
 353
 354         e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
 355         if (!e)
 356                 e = search_module_dbetables(addr);
 357         return e;
 358 }
 359
 360 asmlinkage void do_be(struct pt_regs *regs)
 361 {
 362         const int field = 2 * sizeof(unsigned long);
 363         const struct exception_table_entry *fixup = NULL;
 364         int data = regs->cp0_cause & 4;
 365         int action = MIPS_BE_FATAL;
 366
 367         /* XXX For now.  Fixme, this searches the wrong table ...  */
 368         if (data && !user_mode(regs))
 369                 fixup = search_dbe_tables(exception_epc(regs));
 370
 371         if (fixup)
 372                 action = MIPS_BE_FIXUP;
 373
 374         if (board_be_handler)
 375                 action = board_be_handler(regs, fixup != 0);
 376
 377         switch (action) {
 378         case MIPS_BE_DISCARD:
 379                 return;
 380         case MIPS_BE_FIXUP:
 381                 if (fixup) {
 382                         regs->cp0_epc = fixup->nextinsn;
 383                         return;
 384                 }
 385                 break;
 386         default:
 387                 break;
 388         }
 389
 390         /*
 391          * Assume it would be too dangerous to continue ...
 392          */
 393         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
 394                data ? "Data" : "Instruction",
 395                field, regs->cp0_epc, field, regs->regs[31]);
 396         die_if_kernel("Oops", regs);
 397         force_sig(SIGBUS, current);
 398 }
 399
 400 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
 401 {
 402         unsigned int __user *epc;
 403
 404         epc = (unsigned int __user *) regs->cp0_epc +
 405               ((regs->cp0_cause & CAUSEF_BD) != 0);
 406         if (!get_user(*opcode, epc))
 407                 return 0;
 408
 409         force_sig(SIGSEGV, current);
 410         return 1;
 411 }
 412
 413 /*
 414  * ll/sc emulation
 415  */
 416
 417 #define OPCODE 0xfc000000
 418 #define BASE   0x03e00000
 419 #define RT     0x001f0000
 420 #define OFFSET 0x0000ffff
 421 #define LL     0xc0000000
 422 #define SC     0xe0000000
 423 #define SPEC3  0x7c000000
 424 #define RD     0x0000f800
 425 #define FUNC   0x0000003f
 426 #define RDHWR  0x0000003b
 427
 428 /*
 429  * The ll_bit is cleared by r*_switch.S
 430  */
 431
 432 unsigned long ll_bit;
 433
 434 static struct task_struct *ll_task = NULL;
 435
 436 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
 437 {
 438         unsigned long value, __user *vaddr;
 439         long offset;
 440         int signal = 0;
 441
 442         /*
 443          * analyse the ll instruction that just caused a ri exception
 444          * and put the referenced address to addr.
 445          */
 446
 447         /* sign extend offset */
 448         offset = opcode & OFFSET;
 449         offset <<= 16;
 450         offset >>= 16;
 451
 452         vaddr = (unsigned long __user *)
 453                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 454
 455         if ((unsigned long)vaddr & 3) {
 456                 signal = SIGBUS;
 457                 goto sig;
 458         }
 459         if (get_user(value, vaddr)) {
 460                 signal = SIGSEGV;
 461                 goto sig;
 462         }
 463
 464         preempt_disable();
 465
 466         if (ll_task == NULL || ll_task == current) {
 467                 ll_bit = 1;
 468         } else {
 469                 ll_bit = 0;
 470         }
 471         ll_task = current;
 472
 473         preempt_enable();
 474
 475         compute_return_epc(regs);
 476
 477         regs->regs[(opcode & RT) >> 16] = value;
 478
 479         return;
 480
 481 sig:
 482         force_sig(signal, current);
 483 }
 484
 485 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
 486 {
 487         unsigned long __user *vaddr;
 488         unsigned long reg;
 489         long offset;
 490         int signal = 0;
 491
 492         /*
 493          * analyse the sc instruction that just caused a ri exception
 494          * and put the referenced address to addr.
 495          */
 496
 497         /* sign extend offset */
 498         offset = opcode & OFFSET;
 499         offset <<= 16;
 500         offset >>= 16;
 501
 502         vaddr = (unsigned long __user *)
 503                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 504         reg = (opcode & RT) >> 16;
 505
 506         if ((unsigned long)vaddr & 3) {
 507                 signal = SIGBUS;
 508                 goto sig;
 509         }
 510
 511         preempt_disable();
 512
 513         if (ll_bit == 0 || ll_task != current) {
 514                 compute_return_epc(regs);
 515                 regs->regs[reg] = 0;
 516                 preempt_enable();
 517                 return;
 518         }
 519
 520         preempt_enable();
 521
 522         if (put_user(regs->regs[reg], vaddr)) {
 523                 signal = SIGSEGV;
 524                 goto sig;
 525         }
 526
 527         compute_return_epc(regs);
 528         regs->regs[reg] = 1;
 529
 530         return;
 531
 532 sig:
 533         force_sig(signal, current);
 534 }
 535
 536 /*
 537  * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
 538  * opcodes are supposed to result in coprocessor unusable exceptions if
 539  * executed on ll/sc-less processors.  That's the theory.  In practice a
 540  * few processors such as NEC's VR4100 throw reserved instruction exceptions
 541  * instead, so we're doing the emulation thing in both exception handlers.
 542  */
 543 static inline int simulate_llsc(struct pt_regs *regs)
 544 {
 545         unsigned int opcode;
 546
 547         if (unlikely(get_insn_opcode(regs, &opcode)))
 548                 return -EFAULT;
 549
 550         if ((opcode & OPCODE) == LL) {
 551                 simulate_ll(regs, opcode);
 552                 return 0;
 553         }
 554         if ((opcode & OPCODE) == SC) {
 555                 simulate_sc(regs, opcode);
 556                 return 0;
 557         }
 558
 559         return -EFAULT;                 /* Strange things going on ... */
 560 }
 561
 562 /*
 563  * Simulate trapping 'rdhwr' instructions to provide user accessible
 564  * registers not implemented in hardware.  The only current use of this
 565  * is the thread area pointer.
 566  */
 567 static inline int simulate_rdhwr(struct pt_regs *regs)
 568 {
 569         struct thread_info *ti = task_thread_info(current);
 570         unsigned int opcode;
 571
 572         if (unlikely(get_insn_opcode(regs, &opcode)))
 573                 return -EFAULT;
 574
 575         if (unlikely(compute_return_epc(regs)))
 576                 return -EFAULT;
 577
 578         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 579                 int rd = (opcode & RD) >> 11;
 580                 int rt = (opcode & RT) >> 16;
 581                 switch (rd) {
 582                         case 29:
 583                                 regs->regs[rt] = ti->tp_value;
 584                                 return 0;
 585                         default:
 586                                 return -EFAULT;
 587                 }
 588         }
 589
 590         /* Not ours.  */
 591         return -EFAULT;
 592 }
 593
 594 asmlinkage void do_ov(struct pt_regs *regs)
 595 {
 596         siginfo_t info;
 597
 598         die_if_kernel("Integer overflow", regs);
 599
 600         info.si_code = FPE_INTOVF;
 601         info.si_signo = SIGFPE;
 602         info.si_errno = 0;
 603         info.si_addr = (void __user *) regs->cp0_epc;
 604         force_sig_info(SIGFPE, &info, current);
 605 }
 606
 607 /*
 608  * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
 609  */
 610 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 611 {
 612         die_if_kernel("FP exception in kernel code", regs);
 613
 614         if (fcr31 & FPU_CSR_UNI_X) {
 615                 int sig;
 616
 617                 preempt_disable();
 618
 619 #ifdef CONFIG_PREEMPT
 620                 if (!is_fpu_owner()) {
 621                         /* We might lose fpu before disabling preempt... */
 622                         own_fpu();
 623                         BUG_ON(!used_math());
 624                         restore_fp(current);
 625                 }
 626 #endif
 627                 /*
 628                  * Unimplemented operation exception.  If we've got the full
 629                  * software emulator on-board, let's use it...
 630                  *
 631                  * Force FPU to dump state into task/thread context.  We're
 632                  * moving a lot of data here for what is probably a single
 633                  * instruction, but the alternative is to pre-decode the FP
 634                  * register operands before invoking the emulator, which seems
 635                  * a bit extreme for what should be an infrequent event.
 636                  */
 637                 save_fp(current);
 638                 /* Ensure 'resume' not overwrite saved fp context again. */
 639                 lose_fpu();
 640
 641                 preempt_enable();
 642
 643                 /* Run the emulator */
 644                 sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu, 1);
 645
 646                 preempt_disable();
 647
 648                 own_fpu();      /* Using the FPU again.  */
 649                 /*
 650                  * We can't allow the emulated instruction to leave any of
 651                  * the cause bit set in $fcr31.
 652                  */
 653                 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
 654
 655                 /* Restore the hardware register state */
 656                 restore_fp(current);
 657
 658                 preempt_enable();
 659
 660                 /* If something went wrong, signal */
 661                 if (sig)
 662                         force_sig(sig, current);
 663
 664                 return;
 665         }
 666
 667         force_sig(SIGFPE, current);
 668 }
 669
 670 asmlinkage void do_bp(struct pt_regs *regs)
 671 {
 672         unsigned int opcode, bcode;
 673         siginfo_t info;
 674
 675         die_if_kernel("Break instruction in kernel code", regs);
 676
 677         if (get_insn_opcode(regs, &opcode))
 678                 return;
 679
 680         /*
 681          * There is the ancient bug in the MIPS assemblers that the break
 682          * code starts left to bit 16 instead to bit 6 in the opcode.
 683          * Gas is bug-compatible, but not always, grrr...
 684          * We handle both cases with a simple heuristics.  --macro
 685          */
 686         bcode = ((opcode >> 6) & ((1 << 20) - 1));
 687         if (bcode < (1 << 10))
 688                 bcode <<= 10;
 689
 690         /*
 691          * (A short test says that IRIX 5.3 sends SIGTRAP for all break
 692          * insns, even for break codes that indicate arithmetic failures.
 693          * Weird ...)
 694          * But should we continue the brokenness???  --macro
 695          */
 696         switch (bcode) {
 697         case BRK_OVERFLOW << 10:
 698         case BRK_DIVZERO << 10:
 699                 if (bcode == (BRK_DIVZERO << 10))
 700                         info.si_code = FPE_INTDIV;
 701                 else
 702                         info.si_code = FPE_INTOVF;
 703                 info.si_signo = SIGFPE;
 704                 info.si_errno = 0;
 705                 info.si_addr = (void __user *) regs->cp0_epc;
 706                 force_sig_info(SIGFPE, &info, current);
 707                 break;
 708         default:
 709                 force_sig(SIGTRAP, current);
 710         }
 711 }
 712
 713 asmlinkage void do_tr(struct pt_regs *regs)
 714 {
 715         unsigned int opcode, tcode = 0;
 716         siginfo_t info;
 717
 718         die_if_kernel("Trap instruction in kernel code", regs);
 719
 720         if (get_insn_opcode(regs, &opcode))
 721                 return;
 722
 723         /* Immediate versions don't provide a code.  */
 724         if (!(opcode & OPCODE))
 725                 tcode = ((opcode >> 6) & ((1 << 10) - 1));
 726
 727         /*
 728          * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
 729          * insns, even for trap codes that indicate arithmetic failures.
 730          * Weird ...)
 731          * But should we continue the brokenness???  --macro
 732          */
 733         switch (tcode) {
 734         case BRK_OVERFLOW:
 735         case BRK_DIVZERO:
 736                 if (tcode == BRK_DIVZERO)
 737                         info.si_code = FPE_INTDIV;
 738                 else
 739                         info.si_code = FPE_INTOVF;
 740                 info.si_signo = SIGFPE;
 741                 info.si_errno = 0;
 742                 info.si_addr = (void __user *) regs->cp0_epc;
 743                 force_sig_info(SIGFPE, &info, current);
 744                 break;
 745         default:
 746                 force_sig(SIGTRAP, current);
 747         }
 748 }
 749
 750 asmlinkage void do_ri(struct pt_regs *regs)
 751 {
 752         die_if_kernel("Reserved instruction in kernel code", regs);
 753
 754         if (!cpu_has_llsc)
 755                 if (!simulate_llsc(regs))
 756                         return;
 757
 758         if (!simulate_rdhwr(regs))
 759                 return;
 760
 761         force_sig(SIGILL, current);
 762 }
 763
 764 asmlinkage void do_cpu(struct pt_regs *regs)
 765 {
 766         unsigned int cpid;
 767
 768         die_if_kernel("do_cpu invoked from kernel context!", regs);
 769
 770         cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
 771
 772         switch (cpid) {
 773         case 0:
 774                 if (!cpu_has_llsc)
 775                         if (!simulate_llsc(regs))
 776                                 return;
 777
 778                 if (!simulate_rdhwr(regs))
 779                         return;
 780
 781                 break;
 782
 783         case 1:
 784                 preempt_disable();
 785
 786                 own_fpu();
 787                 if (used_math()) {      /* Using the FPU again.  */
 788                         restore_fp(current);
 789                 } else {                        /* First time FPU user.  */
 790                         init_fpu();
 791                         set_used_math();
 792                 }
 793
 794                 if (cpu_has_fpu) {
 795                         preempt_enable();
 796                 } else {
 797                         int sig;
 798                         preempt_enable();
 799                         sig = fpu_emulator_cop1Handler(regs,
 800                                                 &current->thread.fpu, 0);
 801                         if (sig)
 802                                 force_sig(sig, current);
 803 #ifdef CONFIG_MIPS_MT_FPAFF
 804                         else {
 805                         /*
 806                          * MIPS MT processors may have fewer FPU contexts
 807                          * than CPU threads. If we've emulated more than
 808                          * some threshold number of instructions, force
 809                          * migration to a "CPU" that has FP support.
 810                          */
 811                          if(mt_fpemul_threshold > 0
 812                          && ((current->thread.emulated_fp++
 813                             > mt_fpemul_threshold))) {
 814                           /*
 815                            * If there's no FPU present, or if the
 816                            * application has already restricted
 817                            * the allowed set to exclude any CPUs
 818                            * with FPUs, we'll skip the procedure.
 819                            */
 820                           if (cpus_intersects(current->cpus_allowed,
 821                                                 mt_fpu_cpumask)) {
 822                             cpumask_t tmask;
 823
 824                             cpus_and(tmask,
 825                                         current->thread.user_cpus_allowed,
 826                                         mt_fpu_cpumask);
 827                             set_cpus_allowed(current, tmask);
 828                             current->thread.mflags |= MF_FPUBOUND;
 829                           }
 830                          }
 831                         }
 832 #endif /* CONFIG_MIPS_MT_FPAFF */
 833                 }
 834
 835                 return;
 836
 837         case 2:
 838         case 3:
 839                 die_if_kernel("do_cpu invoked from kernel context!", regs);
 840                 break;
 841         }
 842
 843         force_sig(SIGILL, current);
 844 }
 845
 846 asmlinkage void do_mdmx(struct pt_regs *regs)
 847 {
 848         force_sig(SIGILL, current);
 849 }
 850
 851 asmlinkage void do_watch(struct pt_regs *regs)
 852 {
 853         /*
 854          * We use the watch exception where available to detect stack
 855          * overflows.
 856          */
 857         dump_tlb_all();
 858         show_regs(regs);
 859         panic("Caught WATCH exception - probably caused by stack overflow.");
 860 }
 861
 862 asmlinkage void do_mcheck(struct pt_regs *regs)
 863 {
 864         const int field = 2 * sizeof(unsigned long);
 865         int multi_match = regs->cp0_status & ST0_TS;
 866
 867         show_regs(regs);
 868
 869         if (multi_match) {
 870                 printk("Index   : %0x\n", read_c0_index());
 871                 printk("Pagemask: %0x\n", read_c0_pagemask());
 872                 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
 873                 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
 874                 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
 875                 printk("\n");
 876                 dump_tlb_all();
 877         }
 878
 879         show_code((unsigned int *) regs->cp0_epc);
 880
 881         /*
 882          * Some chips may have other causes of machine check (e.g. SB1
 883          * graduation timer)
 884          */
 885         panic("Caught Machine Check exception - %scaused by multiple "
 886               "matching entries in the TLB.",
 887               (multi_match) ? "" : "not ");
 888 }
 889
 890 asmlinkage void do_mt(struct pt_regs *regs)
 891 {
 892         int subcode;
 893
 894         subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
 895                         >> VPECONTROL_EXCPT_SHIFT;
 896         switch (subcode) {
 897         case 0:
 898                 printk(KERN_DEBUG "Thread Underflow\n");
 899                 break;
 900         case 1:
 901                 printk(KERN_DEBUG "Thread Overflow\n");
 902                 break;
 903         case 2:
 904                 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
 905                 break;
 906         case 3:
 907                 printk(KERN_DEBUG "Gating Storage Exception\n");
 908                 break;
 909         case 4:
 910                 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
 911                 break;
 912         case 5:
 913                 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
 914                 break;
 915         default:
 916                 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
 917                         subcode);
 918                 break;
 919         }
 920         die_if_kernel("MIPS MT Thread exception in kernel", regs);
 921
 922         force_sig(SIGILL, current);
 923 }
 924
 925
 926 asmlinkage void do_dsp(struct pt_regs *regs)
 927 {
 928         if (cpu_has_dsp)
 929                 panic("Unexpected DSP exception\n");
 930
 931         force_sig(SIGILL, current);
 932 }
 933
 934 asmlinkage void do_reserved(struct pt_regs *regs)
 935 {
 936         /*
 937          * Game over - no way to handle this if it ever occurs.  Most probably
 938          * caused by a new unknown cpu type or after another deadly
 939          * hard/software error.
 940          */
 941         show_regs(regs);
 942         panic("Caught reserved exception %ld - should not happen.",
 943               (regs->cp0_cause & 0x7f) >> 2);
 944 }
 945
 946 asmlinkage void do_default_vi(struct pt_regs *regs)
 947 {
 948         show_regs(regs);
 949         panic("Caught unexpected vectored interrupt.");
 950 }
 951
 952 /*
 953  * Some MIPS CPUs can enable/disable for cache parity detection, but do
 954  * it different ways.
 955  */
 956 static inline void parity_protection_init(void)
 957 {
 958         switch (current_cpu_data.cputype) {
 959         case CPU_24K:
 960         case CPU_34K:
 961         case CPU_5KC:
 962                 write_c0_ecc(0x80000000);
 963                 back_to_back_c0_hazard();
 964                 /* Set the PE bit (bit 31) in the c0_errctl register. */
 965                 printk(KERN_INFO "Cache parity protection %sabled\n",
 966                        (read_c0_ecc() & 0x80000000) ? "en" : "dis");
 967                 break;
 968         case CPU_20KC:
 969         case CPU_25KF:
 970                 /* Clear the DE bit (bit 16) in the c0_status register. */
 971                 printk(KERN_INFO "Enable cache parity protection for "
 972                        "MIPS 20KC/25KF CPUs.\n");
 973                 clear_c0_status(ST0_DE);
 974                 break;
 975         default:
 976                 break;
 977         }
 978 }
 979
 980 asmlinkage void cache_parity_error(void)
 981 {
 982         const int field = 2 * sizeof(unsigned long);
 983         unsigned int reg_val;
 984
 985         /* For the moment, report the problem and hang. */
 986         printk("Cache error exception:\n");
 987         printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
 988         reg_val = read_c0_cacheerr();
 989         printk("c0_cacheerr == %08x\n", reg_val);
 990
 991         printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
 992                reg_val & (1<<30) ? "secondary" : "primary",
 993                reg_val & (1<<31) ? "data" : "insn");
 994         printk("Error bits: %s%s%s%s%s%s%s\n",
 995                reg_val & (1<<29) ? "ED " : "",
 996                reg_val & (1<<28) ? "ET " : "",
 997                reg_val & (1<<26) ? "EE " : "",
 998                reg_val & (1<<25) ? "EB " : "",
 999                reg_val & (1<<24) ? "EI " : "",
1000                reg_val & (1<<23) ? "E1 " : "",
1001                reg_val & (1<<22) ? "E0 " : "");
1002         printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1003
1004 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1005         if (reg_val & (1<<22))
1006                 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1007
1008         if (reg_val & (1<<23))
1009                 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1010 #endif
1011
1012         panic("Can't handle the cache error!");
1013 }
1014
1015 /*
1016  * SDBBP EJTAG debug exception handler.
1017  * We skip the instruction and return to the next instruction.
1018  */
1019 void ejtag_exception_handler(struct pt_regs *regs)
1020 {
1021         const int field = 2 * sizeof(unsigned long);
1022         unsigned long depc, old_epc;
1023         unsigned int debug;
1024
1025         printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1026         depc = read_c0_depc();
1027         debug = read_c0_debug();
1028         printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1029         if (debug & 0x80000000) {
1030                 /*
1031                  * In branch delay slot.
1032                  * We cheat a little bit here and use EPC to calculate the
1033                  * debug return address (DEPC). EPC is restored after the
1034                  * calculation.
1035                  */
1036                 old_epc = regs->cp0_epc;
1037                 regs->cp0_epc = depc;
1038                 __compute_return_epc(regs);
1039                 depc = regs->cp0_epc;
1040                 regs->cp0_epc = old_epc;
1041         } else
1042                 depc += 4;
1043         write_c0_depc(depc);
1044
1045 #if 0
1046         printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1047         write_c0_debug(debug | 0x100);
1048 #endif
1049 }
1050
1051 /*
1052  * NMI exception handler.
1053  */
1054 void nmi_exception_handler(struct pt_regs *regs)
1055 {
1056 #ifdef CONFIG_MIPS_MT_SMTC
1057         unsigned long dvpret = dvpe();
1058         bust_spinlocks(1);
1059         printk("NMI taken!!!!\n");
1060         mips_mt_regdump(dvpret);
1061 #else
1062         bust_spinlocks(1);
1063         printk("NMI taken!!!!\n");
1064 #endif /* CONFIG_MIPS_MT_SMTC */
1065         die("NMI", regs);
1066         while(1) ;
1067 }
1068
1069 #define VECTORSPACING 0x100     /* for EI/VI mode */
1070
1071 unsigned long ebase;
1072 unsigned long exception_handlers[32];
1073 unsigned long vi_handlers[64];
1074
1075 /*
1076  * As a side effect of the way this is implemented we're limited
1077  * to interrupt handlers in the address range from
1078  * KSEG0 <= x < KSEG0 + 256mb on the Nevada.  Oh well ...
1079  */
1080 void *set_except_vector(int n, void *addr)
1081 {
1082         unsigned long handler = (unsigned long) addr;
1083         unsigned long old_handler = exception_handlers[n];
1084
1085         exception_handlers[n] = handler;
1086         if (n == 0 && cpu_has_divec) {
1087                 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1088                                                  (0x03ffffff & (handler >> 2));
1089                 flush_icache_range(ebase + 0x200, ebase + 0x204);
1090         }
1091         return (void *)old_handler;
1092 }
1093
1094 #ifdef CONFIG_CPU_MIPSR2_SRS
1095 /*
1096  * MIPSR2 shadow register set allocation
1097  * FIXME: SMP...
1098  */
1099
1100 static struct shadow_registers {
1101         /*
1102          * Number of shadow register sets supported
1103          */
1104         unsigned long sr_supported;
1105         /*
1106          * Bitmap of allocated shadow registers
1107          */
1108         unsigned long sr_allocated;
1109 } shadow_registers;
1110
1111 static void mips_srs_init(void)
1112 {
1113         shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1114         printk(KERN_INFO "%d MIPSR2 register sets available\n",
1115                shadow_registers.sr_supported);
1116         shadow_registers.sr_allocated = 1;      /* Set 0 used by kernel */
1117 }
1118
1119 int mips_srs_max(void)
1120 {
1121         return shadow_registers.sr_supported;
1122 }
1123
1124 int mips_srs_alloc(void)
1125 {
1126         struct shadow_registers *sr = &shadow_registers;
1127         int set;
1128
1129 again:
1130         set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1131         if (set >= sr->sr_supported)
1132                 return -1;
1133
1134         if (test_and_set_bit(set, &sr->sr_allocated))
1135                 goto again;
1136
1137         return set;
1138 }
1139
1140 void mips_srs_free(int set)
1141 {
1142         struct shadow_registers *sr = &shadow_registers;
1143
1144         clear_bit(set, &sr->sr_allocated);
1145 }
1146
1147 static void *set_vi_srs_handler(int n, void *addr, int srs)
1148 {
1149         unsigned long handler;
1150         unsigned long old_handler = vi_handlers[n];
1151         u32 *w;
1152         unsigned char *b;
1153
1154         if (!cpu_has_veic && !cpu_has_vint)
1155                 BUG();
1156
1157         if (addr == NULL) {
1158                 handler = (unsigned long) do_default_vi;
1159                 srs = 0;
1160         } else
1161                 handler = (unsigned long) addr;
1162         vi_handlers[n] = (unsigned long) addr;
1163
1164         b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1165
1166         if (srs >= mips_srs_max())
1167                 panic("Shadow register set %d not supported", srs);
1168
1169         if (cpu_has_veic) {
1170                 if (board_bind_eic_interrupt)
1171                         board_bind_eic_interrupt (n, srs);
1172         } else if (cpu_has_vint) {
1173                 /* SRSMap is only defined if shadow sets are implemented */
1174                 if (mips_srs_max() > 1)
1175                         change_c0_srsmap (0xf << n*4, srs << n*4);
1176         }
1177
1178         if (srs == 0) {
1179                 /*
1180                  * If no shadow set is selected then use the default handler
1181                  * that does normal register saving and a standard interrupt exit
1182                  */
1183
1184                 extern char except_vec_vi, except_vec_vi_lui;
1185                 extern char except_vec_vi_ori, except_vec_vi_end;
1186 #ifdef CONFIG_MIPS_MT_SMTC
1187                 /*
1188                  * We need to provide the SMTC vectored interrupt handler
1189                  * not only with the address of the handler, but with the
1190                  * Status.IM bit to be masked before going there.
1191                  */
1192                 extern char except_vec_vi_mori;
1193                 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1194 #endif /* CONFIG_MIPS_MT_SMTC */
1195                 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1196                 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1197                 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1198
1199                 if (handler_len > VECTORSPACING) {
1200                         /*
1201                          * Sigh... panicing won't help as the console
1202                          * is probably not configured :(
1203                          */
1204                         panic ("VECTORSPACING too small");
1205                 }
1206
1207                 memcpy (b, &except_vec_vi, handler_len);
1208 #ifdef CONFIG_MIPS_MT_SMTC
1209                 if (n > 7)
1210                         printk("Vector index %d exceeds SMTC maximum\n", n);
1211                 w = (u32 *)(b + mori_offset);
1212                 *w = (*w & 0xffff0000) | (0x100 << n);
1213 #endif /* CONFIG_MIPS_MT_SMTC */
1214                 w = (u32 *)(b + lui_offset);
1215                 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1216                 w = (u32 *)(b + ori_offset);
1217                 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1218                 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1219         }
1220         else {
1221                 /*
1222                  * In other cases jump directly to the interrupt handler
1223                  *
1224                  * It is the handlers responsibility to save registers if required
1225                  * (eg hi/lo) and return from the exception using "eret"
1226                  */
1227                 w = (u32 *)b;
1228                 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1229                 *w = 0;
1230                 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1231         }
1232
1233         return (void *)old_handler;
1234 }
1235
1236 void *set_vi_handler(int n, void *addr)
1237 {
1238         return set_vi_srs_handler(n, addr, 0);
1239 }
1240
1241 #else
1242
1243 static inline void mips_srs_init(void)
1244 {
1245 }
1246
1247 #endif /* CONFIG_CPU_MIPSR2_SRS */
1248
1249 /*
1250  * This is used by native signal handling
1251  */
1252 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1253 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1254
1255 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1256 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1257
1258 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1259 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1260
1261 #ifdef CONFIG_SMP
1262 static int smp_save_fp_context(struct sigcontext *sc)
1263 {
1264         return cpu_has_fpu
1265                ? _save_fp_context(sc)
1266                : fpu_emulator_save_context(sc);
1267 }
1268
1269 static int smp_restore_fp_context(struct sigcontext *sc)
1270 {
1271         return cpu_has_fpu
1272                ? _restore_fp_context(sc)
1273                : fpu_emulator_restore_context(sc);
1274 }
1275 #endif
1276
1277 static inline void signal_init(void)
1278 {
1279 #ifdef CONFIG_SMP
1280         /* For now just do the cpu_has_fpu check when the functions are invoked */
1281         save_fp_context = smp_save_fp_context;
1282         restore_fp_context = smp_restore_fp_context;
1283 #else
1284         if (cpu_has_fpu) {
1285                 save_fp_context = _save_fp_context;
1286                 restore_fp_context = _restore_fp_context;
1287         } else {
1288                 save_fp_context = fpu_emulator_save_context;
1289                 restore_fp_context = fpu_emulator_restore_context;
1290         }
1291 #endif
1292 }
1293
1294 #ifdef CONFIG_MIPS32_COMPAT
1295
1296 /*
1297  * This is used by 32-bit signal stuff on the 64-bit kernel
1298  */
1299 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1300 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1301
1302 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1303 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1304
1305 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1306 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1307
1308 static inline void signal32_init(void)
1309 {
1310         if (cpu_has_fpu) {
1311                 save_fp_context32 = _save_fp_context32;
1312                 restore_fp_context32 = _restore_fp_context32;
1313         } else {
1314                 save_fp_context32 = fpu_emulator_save_context32;
1315                 restore_fp_context32 = fpu_emulator_restore_context32;
1316         }
1317 }
1318 #endif
1319
1320 extern void cpu_cache_init(void);
1321 extern void tlb_init(void);
1322 extern void flush_tlb_handlers(void);
1323
1324 void __init per_cpu_trap_init(void)
1325 {
1326         unsigned int cpu = smp_processor_id();
1327         unsigned int status_set = ST0_CU0;
1328 #ifdef CONFIG_MIPS_MT_SMTC
1329         int secondaryTC = 0;
1330         int bootTC = (cpu == 0);
1331
1332         /*
1333          * Only do per_cpu_trap_init() for first TC of Each VPE.
1334          * Note that this hack assumes that the SMTC init code
1335          * assigns TCs consecutively and in ascending order.
1336          */
1337
1338         if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1339             ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1340                 secondaryTC = 1;
1341 #endif /* CONFIG_MIPS_MT_SMTC */
1342
1343         /*
1344          * Disable coprocessors and select 32-bit or 64-bit addressing
1345          * and the 16/32 or 32/32 FPR register model.  Reset the BEV
1346          * flag that some firmware may have left set and the TS bit (for
1347          * IP27).  Set XX for ISA IV code to work.
1348          */
1349 #ifdef CONFIG_64BIT
1350         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1351 #endif
1352         if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1353                 status_set |= ST0_XX;
1354         change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1355                          status_set);
1356
1357         if (cpu_has_dsp)
1358                 set_c0_status(ST0_MX);
1359
1360 #ifdef CONFIG_CPU_MIPSR2
1361         write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1362 #endif
1363
1364 #ifdef CONFIG_MIPS_MT_SMTC
1365         if (!secondaryTC) {
1366 #endif /* CONFIG_MIPS_MT_SMTC */
1367
1368         /*
1369          * Interrupt handling.
1370          */
1371         if (cpu_has_veic || cpu_has_vint) {
1372                 write_c0_ebase (ebase);
1373                 /* Setting vector spacing enables EI/VI mode  */
1374                 change_c0_intctl (0x3e0, VECTORSPACING);
1375         }
1376         if (cpu_has_divec) {
1377                 if (cpu_has_mipsmt) {
1378                         unsigned int vpflags = dvpe();
1379                         set_c0_cause(CAUSEF_IV);
1380                         evpe(vpflags);
1381                 } else
1382                         set_c0_cause(CAUSEF_IV);
1383         }
1384 #ifdef CONFIG_MIPS_MT_SMTC
1385         }
1386 #endif /* CONFIG_MIPS_MT_SMTC */
1387
1388         cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1389         TLBMISS_HANDLER_SETUP();
1390
1391         atomic_inc(&init_mm.mm_count);
1392         current->active_mm = &init_mm;
1393         BUG_ON(current->mm);
1394         enter_lazy_tlb(&init_mm, current);
1395
1396 #ifdef CONFIG_MIPS_MT_SMTC
1397         if (bootTC) {
1398 #endif /* CONFIG_MIPS_MT_SMTC */
1399                 cpu_cache_init();
1400                 tlb_init();
1401 #ifdef CONFIG_MIPS_MT_SMTC
1402         }
1403 #endif /* CONFIG_MIPS_MT_SMTC */
1404 }
1405
1406 /* Install CPU exception handler */
1407 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1408 {
1409         memcpy((void *)(ebase + offset), addr, size);
1410         flush_icache_range(ebase + offset, ebase + offset + size);
1411 }
1412
1413 /* Install uncached CPU exception handler */
1414 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1415 {
1416 #ifdef CONFIG_32BIT
1417         unsigned long uncached_ebase = KSEG1ADDR(ebase);
1418 #endif
1419 #ifdef CONFIG_64BIT
1420         unsigned long uncached_ebase = TO_UNCAC(ebase);
1421 #endif
1422
1423         memcpy((void *)(uncached_ebase + offset), addr, size);
1424 }
1425
1426 void __init trap_init(void)
1427 {
1428         extern char except_vec3_generic, except_vec3_r4000;
1429         extern char except_vec4;
1430         unsigned long i;
1431
1432         if (cpu_has_veic || cpu_has_vint)
1433                 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1434         else
1435                 ebase = CAC_BASE;
1436
1437         mips_srs_init();
1438
1439         per_cpu_trap_init();
1440
1441         /*
1442          * Copy the generic exception handlers to their final destination.
1443          * This will be overriden later as suitable for a particular
1444          * configuration.
1445          */
1446         set_handler(0x180, &except_vec3_generic, 0x80);
1447
1448         /*
1449          * Setup default vectors
1450          */
1451         for (i = 0; i <= 31; i++)
1452                 set_except_vector(i, handle_reserved);
1453
1454         /*
1455          * Copy the EJTAG debug exception vector handler code to it's final
1456          * destination.
1457          */
1458         if (cpu_has_ejtag && board_ejtag_handler_setup)
1459                 board_ejtag_handler_setup ();
1460
1461         /*
1462          * Only some CPUs have the watch exceptions.
1463          */
1464         if (cpu_has_watch)
1465                 set_except_vector(23, handle_watch);
1466
1467         /*
1468          * Initialise interrupt handlers
1469          */
1470         if (cpu_has_veic || cpu_has_vint) {
1471                 int nvec = cpu_has_veic ? 64 : 8;
1472                 for (i = 0; i < nvec; i++)
1473                         set_vi_handler(i, NULL);
1474         }
1475         else if (cpu_has_divec)
1476                 set_handler(0x200, &except_vec4, 0x8);
1477
1478         /*
1479          * Some CPUs can enable/disable for cache parity detection, but does
1480          * it different ways.
1481          */
1482         parity_protection_init();
1483
1484         /*
1485          * The Data Bus Errors / Instruction Bus Errors are signaled
1486          * by external hardware.  Therefore these two exceptions
1487          * may have board specific handlers.
1488          */
1489         if (board_be_init)
1490                 board_be_init();
1491
1492         set_except_vector(0, handle_int);
1493         set_except_vector(1, handle_tlbm);
1494         set_except_vector(2, handle_tlbl);
1495         set_except_vector(3, handle_tlbs);
1496
1497         set_except_vector(4, handle_adel);
1498         set_except_vector(5, handle_ades);
1499
1500         set_except_vector(6, handle_ibe);
1501         set_except_vector(7, handle_dbe);
1502
1503         set_except_vector(8, handle_sys);
1504         set_except_vector(9, handle_bp);
1505         set_except_vector(10, handle_ri);
1506         set_except_vector(11, handle_cpu);
1507         set_except_vector(12, handle_ov);
1508         set_except_vector(13, handle_tr);
1509
1510         if (current_cpu_data.cputype == CPU_R6000 ||
1511             current_cpu_data.cputype == CPU_R6000A) {
1512                 /*
1513                  * The R6000 is the only R-series CPU that features a machine
1514                  * check exception (similar to the R4000 cache error) and
1515                  * unaligned ldc1/sdc1 exception.  The handlers have not been
1516                  * written yet.  Well, anyway there is no R6000 machine on the
1517                  * current list of targets for Linux/MIPS.
1518                  * (Duh, crap, there is someone with a triple R6k machine)
1519                  */
1520                 //set_except_vector(14, handle_mc);
1521                 //set_except_vector(15, handle_ndc);
1522         }
1523
1524
1525         if (board_nmi_handler_setup)
1526                 board_nmi_handler_setup();
1527
1528         if (cpu_has_fpu && !cpu_has_nofpuex)
1529                 set_except_vector(15, handle_fpe);
1530
1531         set_except_vector(22, handle_mdmx);
1532
1533         if (cpu_has_mcheck)
1534                 set_except_vector(24, handle_mcheck);
1535
1536         if (cpu_has_mipsmt)
1537                 set_except_vector(25, handle_mt);
1538
1539         if (cpu_has_dsp)
1540                 set_except_vector(26, handle_dsp);
1541
1542         if (cpu_has_vce)
1543                 /* Special exception: R4[04]00 uses also the divec space. */
1544                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1545         else if (cpu_has_4kex)
1546                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1547         else
1548                 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1549
1550         signal_init();
1551 #ifdef CONFIG_MIPS32_COMPAT
1552         signal32_init();
1553 #endif
1554
1555         flush_icache_range(ebase, ebase + 0x400);
1556         flush_tlb_handlers();
1557 }