2 * Regular lowlevel cardbus driver ("yenta")
4 * (C) Copyright 1999, 2000 Linus Torvalds
6 #include <linux/init.h>
8 #include <linux/sched.h>
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
13 #include <pcmcia/ss.h>
21 #define DEBUG(x,args...) printk(__FUNCTION__ ": " x,##args)
23 #define DEBUG(x,args...)
27 #define to_cycles(ns) ((ns)/120)
28 #define to_ns(cycles) ((cycles)*120)
31 * Generate easy-to-use ways of reading a cardbus sockets
32 * regular memory space ("cb_xxx"), configuration space
33 * ("config_xxx") and compatibility space ("exca_xxxx")
35 static inline u32
cb_readl(pci_socket_t
*socket
, unsigned reg
)
37 u32 val
= readl(socket
->base
+ reg
);
38 DEBUG("%p %04x %08x\n", socket
, reg
, val
);
42 static inline void cb_writel(pci_socket_t
*socket
, unsigned reg
, u32 val
)
44 DEBUG("%p %04x %08x\n", socket
, reg
, val
);
45 writel(val
, socket
->base
+ reg
);
48 static inline u8
config_readb(pci_socket_t
*socket
, unsigned offset
)
51 pci_read_config_byte(socket
->dev
, offset
, &val
);
52 DEBUG("%p %04x %02x\n", socket
, offset
, val
);
56 static inline u16
config_readw(pci_socket_t
*socket
, unsigned offset
)
59 pci_read_config_word(socket
->dev
, offset
, &val
);
60 DEBUG("%p %04x %04x\n", socket
, offset
, val
);
64 static inline u32
config_readl(pci_socket_t
*socket
, unsigned offset
)
67 pci_read_config_dword(socket
->dev
, offset
, &val
);
68 DEBUG("%p %04x %08x\n", socket
, offset
, val
);
72 static inline void config_writeb(pci_socket_t
*socket
, unsigned offset
, u8 val
)
74 DEBUG("%p %04x %02x\n", socket
, offset
, val
);
75 pci_write_config_byte(socket
->dev
, offset
, val
);
78 static inline void config_writew(pci_socket_t
*socket
, unsigned offset
, u16 val
)
80 DEBUG("%p %04x %04x\n", socket
, offset
, val
);
81 pci_write_config_word(socket
->dev
, offset
, val
);
84 static inline void config_writel(pci_socket_t
*socket
, unsigned offset
, u32 val
)
86 DEBUG("%p %04x %08x\n", socket
, offset
, val
);
87 pci_write_config_dword(socket
->dev
, offset
, val
);
90 static inline u8
exca_readb(pci_socket_t
*socket
, unsigned reg
)
92 u8 val
= readb(socket
->base
+ 0x800 + reg
);
93 DEBUG("%p %04x %02x\n", socket
, reg
, val
);
97 static inline u8
exca_readw(pci_socket_t
*socket
, unsigned reg
)
100 val
= readb(socket
->base
+ 0x800 + reg
);
101 val
|= readb(socket
->base
+ 0x800 + reg
+ 1) << 8;
102 DEBUG("%p %04x %04x\n", socket
, reg
, val
);
106 static inline void exca_writeb(pci_socket_t
*socket
, unsigned reg
, u8 val
)
108 DEBUG("%p %04x %02x\n", socket
, reg
, val
);
109 writeb(val
, socket
->base
+ 0x800 + reg
);
112 static void exca_writew(pci_socket_t
*socket
, unsigned reg
, u16 val
)
114 DEBUG("%p %04x %04x\n", socket
, reg
, val
);
115 writeb(val
, socket
->base
+ 0x800 + reg
);
116 writeb(val
>> 8, socket
->base
+ 0x800 + reg
+ 1);
120 * Ugh, mixed-mode cardbus and 16-bit pccard state: things depend
121 * on what kind of card is inserted..
123 static int yenta_get_status(pci_socket_t
*socket
, unsigned int *value
)
126 u32 state
= cb_readl(socket
, CB_SOCKET_STATE
);
128 val
= (state
& CB_3VCARD
) ? SS_3VCARD
: 0;
129 val
|= (state
& CB_XVCARD
) ? SS_XVCARD
: 0;
130 val
|= (state
& (CB_CDETECT1
| CB_CDETECT2
| CB_5VCARD
| CB_3VCARD
131 | CB_XVCARD
| CB_YVCARD
)) ? 0 : SS_PENDING
;
133 if (state
& CB_CBCARD
) {
135 val
|= (state
& CB_CARDSTS
) ? SS_STSCHG
: 0;
136 val
|= (state
& (CB_CDETECT1
| CB_CDETECT2
)) ? 0 : SS_DETECT
;
137 val
|= (state
& CB_PWRCYCLE
) ? SS_POWERON
| SS_READY
: 0;
139 u8 status
= exca_readb(socket
, I365_STATUS
);
140 val
|= ((status
& I365_CS_DETECT
) == I365_CS_DETECT
) ? SS_DETECT
: 0;
141 if (exca_readb(socket
, I365_INTCTL
) & I365_PC_IOCARD
) {
142 val
|= (status
& I365_CS_STSCHG
) ? 0 : SS_STSCHG
;
144 val
|= (status
& I365_CS_BVD1
) ? 0 : SS_BATDEAD
;
145 val
|= (status
& I365_CS_BVD2
) ? 0 : SS_BATWARN
;
147 val
|= (status
& I365_CS_WRPROT
) ? SS_WRPROT
: 0;
148 val
|= (status
& I365_CS_READY
) ? SS_READY
: 0;
149 val
|= (status
& I365_CS_POWERON
) ? SS_POWERON
: 0;
156 static int yenta_Vcc_power(u32 control
)
158 switch (control
& CB_SC_VCC_MASK
) {
159 case CB_SC_VCC_5V
: return 50;
160 case CB_SC_VCC_3V
: return 33;
165 static int yenta_Vpp_power(u32 control
)
167 switch (control
& CB_SC_VPP_MASK
) {
168 case CB_SC_VPP_12V
: return 120;
169 case CB_SC_VPP_5V
: return 50;
170 case CB_SC_VPP_3V
: return 33;
175 static int yenta_get_socket(pci_socket_t
*socket
, socket_state_t
*state
)
180 control
= cb_readl(socket
, CB_SOCKET_CONTROL
);
182 state
->Vcc
= yenta_Vcc_power(control
);
183 state
->Vpp
= yenta_Vpp_power(control
);
184 state
->io_irq
= socket
->io_irq
;
186 if (cb_readl(socket
, CB_SOCKET_STATE
) & CB_CBCARD
) {
187 u16 bridge
= config_readw(socket
, CB_BRIDGE_CONTROL
);
188 if (bridge
& CB_BRIDGE_CRST
)
189 state
->flags
|= SS_RESET
;
193 /* 16-bit card state.. */
194 reg
= exca_readb(socket
, I365_POWER
);
195 state
->flags
= (reg
& I365_PWR_AUTO
) ? SS_PWR_AUTO
: 0;
196 state
->flags
|= (reg
& I365_PWR_OUT
) ? SS_OUTPUT_ENA
: 0;
198 reg
= exca_readb(socket
, I365_INTCTL
);
199 state
->flags
|= (reg
& I365_PC_RESET
) ? 0 : SS_RESET
;
200 state
->flags
|= (reg
& I365_PC_IOCARD
) ? SS_IOCARD
: 0;
202 reg
= exca_readb(socket
, I365_CSCINT
);
203 state
->csc_mask
= (reg
& I365_CSC_DETECT
) ? SS_DETECT
: 0;
204 if (state
->flags
& SS_IOCARD
) {
205 state
->csc_mask
|= (reg
& I365_CSC_STSCHG
) ? SS_STSCHG
: 0;
207 state
->csc_mask
|= (reg
& I365_CSC_BVD1
) ? SS_BATDEAD
: 0;
208 state
->csc_mask
|= (reg
& I365_CSC_BVD2
) ? SS_BATWARN
: 0;
209 state
->csc_mask
|= (reg
& I365_CSC_READY
) ? SS_READY
: 0;
215 static void yenta_set_power(pci_socket_t
*socket
, socket_state_t
*state
)
217 u32 reg
= 0; /* CB_SC_STPCLK? */
218 switch (state
->Vcc
) {
219 case 33: reg
= CB_SC_VCC_3V
; break;
220 case 50: reg
= CB_SC_VCC_5V
; break;
221 default: reg
= 0; break;
223 switch (state
->Vpp
) {
224 case 33: reg
|= CB_SC_VPP_3V
; break;
225 case 50: reg
|= CB_SC_VPP_5V
; break;
226 case 120: reg
|= CB_SC_VPP_12V
; break;
228 if (reg
!= cb_readl(socket
, CB_SOCKET_CONTROL
))
229 cb_writel(socket
, CB_SOCKET_CONTROL
, reg
);
232 static int yenta_set_socket(pci_socket_t
*socket
, socket_state_t
*state
)
236 yenta_set_power(socket
, state
);
237 socket
->io_irq
= state
->io_irq
;
238 bridge
= config_readw(socket
, CB_BRIDGE_CONTROL
) & ~(CB_BRIDGE_CRST
| CB_BRIDGE_INTR
);
239 if (cb_readl(socket
, CB_SOCKET_STATE
) & CB_CBCARD
) {
241 bridge
|= (state
->flags
& SS_RESET
) ? CB_BRIDGE_CRST
: 0;
243 /* ISA interrupt control? */
244 intr
= exca_readb(socket
, I365_INTCTL
);
245 intr
= (intr
& ~0xf);
246 if (!socket
->cb_irq
) {
247 intr
|= state
->io_irq
;
248 bridge
|= CB_BRIDGE_INTR
;
250 exca_writeb(socket
, I365_INTCTL
, intr
);
254 bridge
|= CB_BRIDGE_INTR
;
255 reg
= exca_readb(socket
, I365_INTCTL
) & (I365_RING_ENA
| I365_INTR_ENA
);
256 reg
|= (state
->flags
& SS_RESET
) ? 0 : I365_PC_RESET
;
257 reg
|= (state
->flags
& SS_IOCARD
) ? I365_PC_IOCARD
: 0;
258 reg
|= state
->io_irq
;
259 exca_writeb(socket
, I365_INTCTL
, reg
);
261 reg
= exca_readb(socket
, I365_POWER
) & (I365_VCC_MASK
|I365_VPP1_MASK
);
262 reg
|= I365_PWR_NORESET
;
263 if (state
->flags
& SS_PWR_AUTO
) reg
|= I365_PWR_AUTO
;
264 if (state
->flags
& SS_OUTPUT_ENA
) reg
|= I365_PWR_OUT
;
265 if (exca_readb(socket
, I365_POWER
) != reg
)
266 exca_writeb(socket
, I365_POWER
, reg
);
268 /* CSC interrupt: no ISA irq for CSC */
269 reg
= I365_CSC_DETECT
;
270 if (state
->flags
& SS_IOCARD
) {
271 if (state
->csc_mask
& SS_STSCHG
) reg
|= I365_CSC_STSCHG
;
273 if (state
->csc_mask
& SS_BATDEAD
) reg
|= I365_CSC_BVD1
;
274 if (state
->csc_mask
& SS_BATWARN
) reg
|= I365_CSC_BVD2
;
275 if (state
->csc_mask
& SS_READY
) reg
|= I365_CSC_READY
;
277 exca_writeb(socket
, I365_CSCINT
, reg
);
278 exca_readb(socket
, I365_CSC
);
280 config_writew(socket
, CB_BRIDGE_CONTROL
, bridge
);
281 /* Socket event mask: get card insert/remove events.. */
282 cb_writel(socket
, CB_SOCKET_EVENT
, -1);
283 cb_writel(socket
, CB_SOCKET_MASK
, CB_CDMASK
);
287 static int yenta_get_io_map(pci_socket_t
*socket
, struct pccard_io_map
*io
)
290 unsigned char ioctl
, addr
;
296 io
->start
= exca_readw(socket
, I365_IO(map
)+I365_W_START
);
297 io
->stop
= exca_readw(socket
, I365_IO(map
)+I365_W_STOP
);
299 ioctl
= exca_readb(socket
, I365_IOCTL
);
300 addr
= exca_readb(socket
, I365_ADDRWIN
);
301 io
->speed
= to_ns(ioctl
& I365_IOCTL_WAIT(map
)) ? 1 : 0;
302 io
->flags
= (addr
& I365_ENA_IO(map
)) ? MAP_ACTIVE
: 0;
303 io
->flags
|= (ioctl
& I365_IOCTL_0WS(map
)) ? MAP_0WS
: 0;
304 io
->flags
|= (ioctl
& I365_IOCTL_16BIT(map
)) ? MAP_16BIT
: 0;
305 io
->flags
|= (ioctl
& I365_IOCTL_IOCS16(map
)) ? MAP_AUTOSZ
: 0;
310 static int yenta_set_io_map(pci_socket_t
*socket
, struct pccard_io_map
*io
)
313 unsigned char ioctl
, addr
, enable
;
320 enable
= I365_ENA_IO(map
);
321 addr
= exca_readb(socket
, I365_ADDRWIN
);
323 /* Disable the window before changing it.. */
326 exca_writeb(socket
, I365_ADDRWIN
, addr
);
329 exca_writew(socket
, I365_IO(map
)+I365_W_START
, io
->start
);
330 exca_writew(socket
, I365_IO(map
)+I365_W_STOP
, io
->stop
);
332 ioctl
= exca_readb(socket
, I365_IOCTL
) & ~I365_IOCTL_MASK(map
);
333 if (io
->flags
& MAP_0WS
) ioctl
|= I365_IOCTL_0WS(map
);
334 if (io
->flags
& MAP_16BIT
) ioctl
|= I365_IOCTL_16BIT(map
);
335 if (io
->flags
& MAP_AUTOSZ
) ioctl
|= I365_IOCTL_IOCS16(map
);
336 exca_writeb(socket
, I365_IOCTL
, ioctl
);
338 if (io
->flags
& MAP_ACTIVE
)
339 exca_writeb(socket
, I365_ADDRWIN
, addr
| enable
);
343 static int yenta_get_mem_map(pci_socket_t
*socket
, struct pccard_mem_map
*mem
)
347 unsigned int start
, stop
, page
, offset
;
353 addr
= exca_readb(socket
, I365_ADDRWIN
);
354 mem
->flags
= (addr
& I365_ENA_MEM(map
)) ? MAP_ACTIVE
: 0;
356 start
= exca_readw(socket
, I365_MEM(map
) + I365_W_START
);
357 mem
->flags
|= (start
& I365_MEM_16BIT
) ? MAP_16BIT
: 0;
358 mem
->flags
|= (start
& I365_MEM_0WS
) ? MAP_0WS
: 0;
359 start
= (start
& 0x0fff) << 12;
361 stop
= exca_readw(socket
, I365_MEM(map
) + I365_W_STOP
);
362 mem
->speed
= to_ns(stop
>> 14);
363 stop
= ((stop
& 0x0fff) << 12) + 0x0fff;
365 offset
= exca_readw(socket
, I365_MEM(map
) + I365_W_OFF
);
366 mem
->flags
|= (offset
& I365_MEM_WRPROT
) ? MAP_WRPROT
: 0;
367 mem
->flags
|= (offset
& I365_MEM_REG
) ? MAP_ATTRIB
: 0;
368 offset
= ((offset
& 0x3fff) << 12) + start
;
369 mem
->card_start
= offset
& 0x3ffffff;
371 page
= exca_readb(socket
, CB_MEM_PAGE(map
)) << 24;
372 mem
->sys_start
= start
+ page
;
373 mem
->sys_stop
= start
+ page
;
378 static int yenta_set_mem_map(pci_socket_t
*socket
, struct pccard_mem_map
*mem
)
381 unsigned char addr
, enable
;
382 unsigned int start
, stop
, card_start
;
386 start
= mem
->sys_start
;
387 stop
= mem
->sys_stop
;
388 card_start
= mem
->card_start
;
390 if (map
> 4 || start
> stop
|| ((start
^ stop
) >> 24) ||
391 (card_start
>> 26) || mem
->speed
> 1000)
394 enable
= I365_ENA_MEM(map
);
395 addr
= exca_readb(socket
, I365_ADDRWIN
);
398 exca_writeb(socket
, I365_ADDRWIN
, addr
);
401 exca_writeb(socket
, CB_MEM_PAGE(map
), start
>> 24);
403 word
= (start
>> 12) & 0x0fff;
404 if (mem
->flags
& MAP_16BIT
)
405 word
|= I365_MEM_16BIT
;
406 if (mem
->flags
& MAP_0WS
)
407 word
|= I365_MEM_0WS
;
408 exca_writew(socket
, I365_MEM(map
) + I365_W_START
, word
);
410 word
= (stop
>> 12) & 0x0fff;
411 switch (to_cycles(mem
->speed
)) {
413 case 1: word
|= I365_MEM_WS0
; break;
414 case 2: word
|= I365_MEM_WS1
; break;
415 default: word
|= I365_MEM_WS1
| I365_MEM_WS0
; break;
417 exca_writew(socket
, I365_MEM(map
) + I365_W_STOP
, word
);
419 word
= ((card_start
- start
) >> 12) & 0x3fff;
420 if (mem
->flags
& MAP_WRPROT
)
421 word
|= I365_MEM_WRPROT
;
422 if (mem
->flags
& MAP_ATTRIB
)
423 word
|= I365_MEM_REG
;
424 exca_writew(socket
, I365_MEM(map
) + I365_W_OFF
, word
);
426 if (mem
->flags
& MAP_ACTIVE
)
427 exca_writeb(socket
, I365_ADDRWIN
, addr
| enable
);
431 static void yenta_proc_setup(pci_socket_t
*socket
, struct proc_dir_entry
*base
)
436 static unsigned int yenta_events(pci_socket_t
*socket
)
442 /* Clear interrupt status for the event */
443 cb_event
= cb_readl(socket
, CB_SOCKET_EVENT
);
444 cb_writel(socket
, CB_SOCKET_EVENT
, cb_event
);
446 csc
= exca_readb(socket
, I365_CSC
);
448 events
= (cb_event
& (CB_CD1EVENT
| CB_CD2EVENT
)) ? SS_DETECT
: 0 ;
449 events
|= (csc
& I365_CSC_DETECT
) ? SS_DETECT
: 0;
450 if (exca_readb(socket
, I365_INTCTL
) & I365_PC_IOCARD
) {
451 events
|= (csc
& I365_CSC_STSCHG
) ? SS_STSCHG
: 0;
453 events
|= (csc
& I365_CSC_BVD1
) ? SS_BATDEAD
: 0;
454 events
|= (csc
& I365_CSC_BVD2
) ? SS_BATWARN
: 0;
455 events
|= (csc
& I365_CSC_READY
) ? SS_READY
: 0;
460 static void yenta_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
463 pci_socket_t
*socket
= (pci_socket_t
*) dev_id
;
465 events
= yenta_events(socket
);
467 socket
->events
|= events
;
468 wake_up_interruptible(&socket
->wait
);
473 * Only probe "regular" interrupts, don't
474 * touch dangerous spots like the mouse irq,
475 * because there are mice that apparently
476 * get really confused if they get fondled
479 * Default to 11, 10, 9, 7, 6, 5, 4, 3.
481 static u32 isa_interrupts
= 0x0ef8;
483 static unsigned int yenta_probe_irq(pci_socket_t
*socket
, u32 isa_irq_mask
)
490 /* Set up ISA irq routing to probe the ISA irqs.. */
491 bridge_ctrl
= config_readw(socket
, CB_BRIDGE_CONTROL
);
492 if (!(bridge_ctrl
& CB_BRIDGE_INTR
)) {
493 bridge_ctrl
|= CB_BRIDGE_INTR
;
494 config_writew(socket
, CB_BRIDGE_CONTROL
, bridge_ctrl
);
498 * Probe for usable interrupts using the force
499 * register to generate bogus card status events.
501 cb_writel(socket
, CB_SOCKET_EVENT
, -1);
502 cb_writel(socket
, CB_SOCKET_MASK
, CB_CSTSMASK
);
503 exca_writeb(socket
, I365_CSCINT
, 0);
504 val
= probe_irq_on() & isa_irq_mask
;
505 for (i
= 1; i
< 16; i
++) {
506 if (!((val
>> i
) & 1))
508 exca_writeb(socket
, I365_CSCINT
, I365_CSC_STSCHG
| (i
<< 4));
509 cb_writel(socket
, CB_SOCKET_FORCE
, CB_FCARDSTS
);
511 cb_writel(socket
, CB_SOCKET_EVENT
, -1);
513 cb_writel(socket
, CB_SOCKET_MASK
, 0);
514 exca_writeb(socket
, I365_CSCINT
, 0);
516 mask
= probe_irq_mask(val
) & 0xffff;
518 bridge_ctrl
&= ~CB_BRIDGE_INTR
;
519 config_writew(socket
, CB_BRIDGE_CONTROL
, bridge_ctrl
);
525 * Set static data that doesn't need re-initializing..
527 static void yenta_get_socket_capabilities(pci_socket_t
*socket
, u32 isa_irq_mask
)
529 socket
->cap
.features
|= SS_CAP_PAGE_REGS
| SS_CAP_PCCARD
| SS_CAP_CARDBUS
;
530 socket
->cap
.map_size
= 0x1000;
531 socket
->cap
.pci_irq
= socket
->cb_irq
;
532 socket
->cap
.irq_mask
= yenta_probe_irq(socket
, isa_irq_mask
);
533 socket
->cap
.cb_dev
= socket
->dev
;
534 socket
->cap
.bus
= NULL
;
536 printk("Yenta IRQ list %04x, PCI irq%d\n", socket
->cap
.irq_mask
, socket
->cb_irq
);
539 extern void cardbus_register(pci_socket_t
*socket
);
542 * Watch a socket every second (and possibly in a
543 * more timely manner if the state change interrupt
546 static int yenta_socket_thread(void * data
)
548 pci_socket_t
* socket
= (pci_socket_t
*) data
;
549 DECLARE_WAITQUEUE(wait
, current
);
553 strcpy(current
->comm
, "CardBus Watcher");
555 /* Figure out what the dang thing can do for the PCMCIA layer... */
556 yenta_get_socket_capabilities(socket
, isa_interrupts
);
557 printk("Socket status: %08x\n", cb_readl(socket
, CB_SOCKET_STATE
));
559 /* Register it with the pcmcia layer.. */
560 cardbus_register(socket
);
563 unsigned int events
= socket
->events
| yenta_events(socket
);
568 socket
->handler(socket
->info
, events
);
571 current
->state
= TASK_INTERRUPTIBLE
;
572 add_wait_queue(&socket
->wait
, &wait
);
574 schedule_timeout(HZ
);
575 remove_wait_queue(&socket
->wait
, &wait
);
576 } while (!signal_pending(current
));
581 static void yenta_clear_maps(pci_socket_t
*socket
)
584 pccard_io_map io
= { 0, 0, 0, 0, 1 };
585 pccard_mem_map mem
= { 0, 0, 0, 0, 0, 0 };
587 mem
.sys_stop
= 0x0fff;
588 yenta_set_socket(socket
, &dead_socket
);
589 for (i
= 0; i
< 2; i
++) {
591 yenta_set_io_map(socket
, &io
);
593 for (i
= 0; i
< 5; i
++) {
595 yenta_set_mem_map(socket
, &mem
);
600 * Initialize the standard cardbus registers
602 static void yenta_config_init(pci_socket_t
*socket
)
605 struct pci_dev
*dev
= socket
->dev
;
607 pci_set_power_state(socket
->dev
, 0);
609 config_writel(socket
, CB_LEGACY_MODE_BASE
, 0);
610 config_writel(socket
, PCI_BASE_ADDRESS_0
, dev
->resource
[0].start
);
611 config_writew(socket
, PCI_COMMAND
,
617 /* MAGIC NUMBERS! Fixme */
618 config_writeb(socket
, PCI_CACHE_LINE_SIZE
, 32);
619 config_writeb(socket
, PCI_LATENCY_TIMER
, 168);
620 config_writeb(socket
, PCI_SEC_LATENCY_TIMER
, 176);
621 config_writeb(socket
, PCI_PRIMARY_BUS
, dev
->bus
->number
);
622 config_writeb(socket
, PCI_SECONDARY_BUS
, dev
->subordinate
->number
);
623 config_writeb(socket
, PCI_SUBORDINATE_BUS
, dev
->subordinate
->number
);
626 * Set up the bridging state:
627 * - enable write posting.
628 * - memory window 0 prefetchable, window 1 non-prefetchable
629 * - PCI interrupts enabled if a PCI interrupt exists..
631 bridge
= config_readw(socket
, CB_BRIDGE_CONTROL
);
632 bridge
&= ~(CB_BRIDGE_CRST
| CB_BRIDGE_PREFETCH1
| CB_BRIDGE_INTR
| CB_BRIDGE_ISAEN
| CB_BRIDGE_VGAEN
);
633 bridge
|= CB_BRIDGE_PREFETCH0
| CB_BRIDGE_POSTEN
;
635 bridge
|= CB_BRIDGE_INTR
;
636 config_writew(socket
, CB_BRIDGE_CONTROL
, bridge
);
638 exca_writeb(socket
, I365_GBLCTL
, 0x00);
639 exca_writeb(socket
, I365_GENCTL
, 0x00);
641 /* Redo card voltage interrogation */
642 cb_writel(socket
, CB_SOCKET_FORCE
, CB_CVSTEST
);
645 /* Called at resume and initialization events */
646 static int yenta_init(pci_socket_t
*socket
)
648 yenta_config_init(socket
);
649 yenta_clear_maps(socket
);
653 static int yenta_suspend(pci_socket_t
*socket
)
655 yenta_set_socket(socket
, &dead_socket
);
658 * This does not work currently. The controller
659 * loses too much informationduring D3 to come up
660 * cleanly. We should probably fix yenta_init()
661 * to update all the critical registers, notably
662 * the IO and MEM bridging region data.. That is
663 * something that pci_set_power_state() should
664 * probably know about bridges anyway.
666 pci_set_power_state(socket->dev, 3);
672 static void yenta_allocate_res(pci_socket_t
*socket
, int nr
, unsigned type
)
675 struct resource
*root
, *res
;
677 u32 align
, size
, min
, max
;
680 offset
= 0x1c + 8*nr
;
681 bus
= socket
->dev
->subordinate
;
682 res
= socket
->dev
->resource
+ PCI_BRIDGE_RESOURCES
+ nr
;
683 res
->name
= bus
->name
;
687 root
= pci_find_parent_resource(socket
->dev
, res
);
692 start
= config_readl(socket
, offset
);
693 end
= config_readl(socket
, offset
+4) | 0xfff;
694 if (start
&& end
> start
) {
697 request_resource(root
, res
);
701 align
= size
= 4*1024*1024;
702 min
= PCIBIOS_MIN_MEM
; max
= ~0U;
703 if (type
& IORESOURCE_IO
) {
706 min
= PCIBIOS_MIN_IO
;
710 if (allocate_resource(root
, res
, size
, min
, max
, align
, NULL
, NULL
) < 0)
713 config_writel(socket
, offset
, res
->start
);
714 config_writel(socket
, offset
+4, res
->end
);
718 * Allocate the bridge mappings for the device..
720 static void yenta_allocate_resources(pci_socket_t
*socket
)
722 yenta_allocate_res(socket
, 0, IORESOURCE_MEM
|IORESOURCE_PREFETCH
);
723 yenta_allocate_res(socket
, 1, IORESOURCE_MEM
);
724 yenta_allocate_res(socket
, 2, IORESOURCE_IO
);
725 yenta_allocate_res(socket
, 3, IORESOURCE_IO
); /* PCI isn't clever enough to use this one yet */
729 * Close it down - release our resources and go home..
731 static void yenta_close(pci_socket_t
*sock
)
734 free_irq(sock
->cb_irq
, sock
);
743 * Different cardbus controllers have slightly different
744 * initialization sequences etc details. List them here..
746 #define PD(x,y) PCI_VENDOR_ID_##x, PCI_DEVICE_ID_##x##_##y
747 static struct cardbus_override_struct
{
748 unsigned short vendor
;
749 unsigned short device
;
750 struct pci_socket_ops
*op
;
751 } cardbus_override
[] = {
752 { PD(TI
,1130), &ti113x_ops
},
753 { PD(TI
,1031), &ti_ops
},
754 { PD(TI
,1131), &ti113x_ops
},
755 { PD(TI
,1250), &ti1250_ops
},
756 { PD(TI
,1220), &ti_ops
},
757 { PD(TI
,1221), &ti_ops
},
758 { PD(TI
,1210), &ti_ops
},
759 { PD(TI
,1450), &ti_ops
},
760 { PD(TI
,1225), &ti_ops
},
761 { PD(TI
,1251A
), &ti_ops
},
762 { PD(TI
,1211), &ti_ops
},
763 { PD(TI
,1251B
), &ti_ops
},
764 { PD(TI
,1420), &ti_ops
},
766 { PD(RICOH
,RL5C465
), &ricoh_ops
},
767 { PD(RICOH
,RL5C466
), &ricoh_ops
},
768 { PD(RICOH
,RL5C475
), &ricoh_ops
},
769 { PD(RICOH
,RL5C476
), &ricoh_ops
},
770 { PD(RICOH
,RL5C478
), &ricoh_ops
}
773 #define NR_OVERRIDES (sizeof(cardbus_override)/sizeof(struct cardbus_override_struct))
776 * Initialize a cardbus controller. Make sure we have a usable
777 * interrupt, and that we can map the cardbus area. Fill in the
778 * socket information structure..
780 static int yenta_open(pci_socket_t
*socket
)
783 struct pci_dev
*dev
= socket
->dev
;
786 * Do some basic sanity checking..
788 if (pci_enable_device(dev
))
790 if (!pci_resource_start(dev
, 0)) {
791 printk("No cardbus resource!\n");
796 * Ok, start setup.. Map the cardbus registers,
797 * and request the IRQ.
799 socket
->base
= ioremap(pci_resource_start(dev
, 0), 0x1000);
803 yenta_config_init(socket
);
805 /* Disable all events */
806 cb_writel(socket
, CB_SOCKET_MASK
, 0x0);
808 /* Set up the bridge regions.. */
809 yenta_allocate_resources(socket
);
811 if (dev
->irq
&& !request_irq(dev
->irq
, yenta_interrupt
, SA_SHIRQ
, dev
->name
, socket
))
812 socket
->cb_irq
= dev
->irq
;
814 /* Do we have special options for the device? */
815 for (i
= 0; i
< NR_OVERRIDES
; i
++) {
816 struct cardbus_override_struct
*d
= cardbus_override
+i
;
817 if (dev
->vendor
== d
->vendor
&& dev
->device
== d
->device
) {
820 int retval
= d
->op
->open(socket
);
827 kernel_thread(yenta_socket_thread
, socket
, CLONE_FS
| CLONE_FILES
| CLONE_SIGHAND
);
832 * Standard plain cardbus - no frills, no extensions
834 struct pci_socket_ops yenta_operations
= {
848 EXPORT_SYMBOL(yenta_operations
);