| commit | 5a69dac05290bf5b45201024e20ee807f32d63cf | |
| author | David Daney <ddaney@caviumnetworks.com> | |
| Mon, 5 Jan 2009 23:29:58 +0000 (5 15:29 -0800) | ||
| committer | Ralf Baechle <ralf@linux-mips.org> | |
| Thu, 29 Jan 2009 01:56:43 +0000 (29 01:56 +0000) | ||
| tree | b02e9ba4d5da22333b0553eeb4918ba3f0d76a52 | treesnapshot (tar.gz zip) |
| parent | fcde701f5479f7584ef9adaa2713f3f45e6c78a0 | commitdiff |
MIPS: Read watch registers with interrupts disabled.
If a context switch occurred between the watch exception and reading the
watch registers, it would be possible for the new process to corrupt their
state. Enabling interrupts only after the watch registers are read avoids
this race.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
If a context switch occurred between the watch exception and reading the
watch registers, it would be possible for the new process to corrupt their
state. Enabling interrupts only after the watch registers are read avoids
this race.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| arch/mips/kernel/genex.S | diffblobblamehistory | |
| arch/mips/kernel/traps.c | diffblobblamehistory |