| commit | d110852513148a7ec44fad4e036455aeb816d713 | |
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | |
| Tue, 2 Nov 2010 09:30:46 +0000 (2 17:30 +0800) | ||
| committer | Chris Wilson <chris@chris-wilson.co.uk> | |
| Tue, 2 Nov 2010 10:05:46 +0000 (2 10:05 +0000) | ||
| tree | 5c72fa12fa653804a4d13658a641a713d6849acd | treesnapshot (tar.gz zip) |
| parent | 328fc1325f144027f4a8269b11e9f8dcf1edcb97 | commitdiff |
agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| drivers/char/agp/intel-gtt.c | diffblobblamehistory |