powerpc/eeh: PERR/SERR bit settings during EEH device recovery
commitcde274c0c789404df8ece3f9e7d6506caf0127e2
authorMike Mason <mmlnx@us.ibm.com>
Tue, 8 Jul 2008 16:04:35 +0000 (9 02:04 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Wed, 9 Jul 2008 06:30:48 +0000 (9 16:30 +1000)
treec0972e3907077f379289349ac09277ebc58ebb2d
parentb887ec620a7575f54fa025d38fa1008dc8a3b12a
powerpc/eeh: PERR/SERR bit settings during EEH device recovery

The following patch restores the PERR and SERR bits in the PCI
command register during an EEH device recovery. We have found
at least one case (an Agilent test card) where the PERR/SERR
bits are set to 1 by firmware at boot time, but are not restored
to 1 during EEH recovery.  The patch fixes the Agilent card
problem.  It has been tested on several other EEH-enabled cards
with no regressions.

Signed-off-by: Mike Mason <mmlnx@us.ibm.com>
Acked-by: Linas Vepstas <linasvepstas@gmail.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/platforms/pseries/eeh.c