| commit | ca928dcb3281838f1a52c0cfedbc59a1c1b840ad | |
| author | Will Deacon <will.deacon@arm.com> | |
| Thu, 5 Aug 2010 10:20:51 +0000 (5 11:20 +0100) | ||
| committer | Greg Kroah-Hartman <gregkh@suse.de> | |
| Fri, 13 Aug 2010 20:27:24 +0000 (13 13:27 -0700) | ||
| tree | c0f4dff8759308b51255d4bb4011b3929b8e4cf2 | treesnapshot (tar.gz zip) |
| parent | 35394fdc1277b92ebd0d1a205f9a3e783b794c26 | commitdiff |
ARM: 6299/1: errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID
commit cdf357f1e13a08a11261edacb3083746f65c1ed9 upstream.
On versions of the Cortex-A9 prior to r2p0, performing TLB invalidations by
ASID match can result in the incorrect ASID being broadcast to other CPUs.
As a consequence of this, the targetted TLB entries are not invalidated
across the system.
This workaround changes the TLB flushing routines to invalidate entries
regardless of the ASID.
Tested-by: Rob Clark <rob@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
commit cdf357f1e13a08a11261edacb3083746f65c1ed9 upstream.
On versions of the Cortex-A9 prior to r2p0, performing TLB invalidations by
ASID match can result in the incorrect ASID being broadcast to other CPUs.
As a consequence of this, the targetted TLB entries are not invalidated
across the system.
This workaround changes the TLB flushing routines to invalidate entries
regardless of the ASID.
Tested-by: Rob Clark <rob@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| arch/arm/Kconfig | diffblobblamehistory | |
| arch/arm/include/asm/tlbflush.h | diffblobblamehistory |