| commit | 8da0d5755ac88a4027e0c511a2be7c0ef0c70634 | |
| author | Kees Cook <kees.cook@canonical.com> | |
| Tue, 24 May 2011 23:29:26 +0000 (24 16:29 -0700) | ||
| committer | Greg Kroah-Hartman <gregkh@suse.de> | |
| Fri, 3 Jun 2011 01:34:11 +0000 (3 10:34 +0900) | ||
| tree | 11cc31fa3d51a5dccaacead7cfeaa1c68dc72f20 | treesnapshot (tar.gz zip) |
| parent | 497ce1c280e962b3fd87d8c84d015a18127a0d79 | commitdiff |
x86, cpufeature: Update CPU feature RDRND to RDRAND
commit 7ccafc5f75c87853f3c49845d5a884f2376e03ce upstream.
The Intel manual changed the name of the CPUID bit to match the
instruction name. We should follow suit for sanity's sake. (See Intel SDM
Volume 2, Table 3-20 "Feature Information Returned in the ECX Register".)
[ hpa: we can only do this at this time because there are currently no CPUs
with this feature on the market, hence this is pre-hardware enabling.
However, Cc:'ing stable so that stable can present a consistent ABI. ]
Signed-off-by: Kees Cook <kees.cook@canonical.com>
Link: http://lkml.kernel.org/r/20110524232926.GA27728@outflux.net
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
commit 7ccafc5f75c87853f3c49845d5a884f2376e03ce upstream.
The Intel manual changed the name of the CPUID bit to match the
instruction name. We should follow suit for sanity's sake. (See Intel SDM
Volume 2, Table 3-20 "Feature Information Returned in the ECX Register".)
[ hpa: we can only do this at this time because there are currently no CPUs
with this feature on the market, hence this is pre-hardware enabling.
However, Cc:'ing stable so that stable can present a consistent ABI. ]
Signed-off-by: Kees Cook <kees.cook@canonical.com>
Link: http://lkml.kernel.org/r/20110524232926.GA27728@outflux.net
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| arch/x86/include/asm/cpufeature.h | diffblobblamehistory |