ARM: 6385/1: setup: detect aliasing I-cache when D-cache is non-aliasing
commit8925ec4c530094b878e7e28a1fd78e7122afd973
authorWill Deacon <will.deacon@arm.com>
Mon, 13 Sep 2010 15:18:30 +0000 (13 16:18 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 4 Oct 2010 19:57:09 +0000 (4 20:57 +0100)
tree2b7200f64892299c185d3a07d1f793ea9217b5d4
parentf8b63c184ad13cc8adc3dadb557d4fbc29f76e4d
ARM: 6385/1: setup: detect aliasing I-cache when D-cache is non-aliasing

Currently, the Kernel assumes that if a CPU has a non-aliasing D-cache
then the I-cache is also non-aliasing. This may not be true on ARM cores
from v6 onwards, which may have aliasing I-caches but non-aliasing
D-caches.

This patch adds a cpu_has_aliasing_icache function, which is called from
cacheid_init and adds CACHEID_VIPT_I_ALIASING to the cacheid when
appropriate. A utility macro, icache_is_vipt_aliasing(), is also
provided.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/include/asm/cachetype.h
arch/arm/kernel/setup.c