| commit | 819a63dc792b0888edd3eda306a9e1e049dcbb1c | |
| author | Alexander Graf <agraf@suse.de> | |
| Thu, 29 Jul 2010 12:48:04 +0000 (29 14:48 +0200) | ||
| committer | Avi Kivity <avi@redhat.com> | |
| Sun, 24 Oct 2010 08:50:56 +0000 (24 10:50 +0200) | ||
| tree | 70599dcd83eb9892785cd9e7ca5d92534bedcdd7 | treesnapshot (tar.gz zip) |
| parent | 92234722ed631f472f1c4d79d35d8e5cf6910002 | commitdiff |
KVM: PPC: PV mtmsrd L=1
The PowerPC ISA has a special instruction for mtmsr that only changes the EE
and RI bits, namely the L=1 form.
Since that one is reasonably often occuring and simple to implement, let's
go with this first. Writing EE=0 is always just a store. Doing EE=1 also
requires us to check for pending interrupts and if necessary exit back to the
hypervisor.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
The PowerPC ISA has a special instruction for mtmsr that only changes the EE
and RI bits, namely the L=1 form.
Since that one is reasonably often occuring and simple to implement, let's
go with this first. Writing EE=0 is always just a store. Doing EE=1 also
requires us to check for pending interrupts and if necessary exit back to the
hypervisor.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
| arch/powerpc/kernel/kvm.c | diffblobblamehistory | |
| arch/powerpc/kernel/kvm_emul.S | diffblobblamehistory |