| commit | 6f15c506e0cec601fad9fabb7ded0d1811b8002f | |
| author | Alex Deucher <alexdeucher@gmail.com> | |
| Fri, 20 May 2011 16:36:12 +0000 (20 12:36 -0400) | ||
| committer | Dave Airlie <airlied@gmail.com> | |
| Sun, 22 May 2011 10:20:05 +0000 (22 20:20 +1000) | ||
| tree | 014495d41f3db1388f08412a4d690267b95bf99e | treesnapshot (tar.gz zip) |
| parent | d291767b6056540277497d91baa9120428d7cd1a | commitdiff |
drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices
If the ss clock is external, the CLK_REF bit needs to be set
in the SetPixelClock parameters. This should fix DP failures
in the channel equalization loop.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
If the ss clock is external, the CLK_REF bit needs to be set
in the SetPixelClock parameters. This should fix DP failures
in the channel equalization loop.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
| drivers/gpu/drm/radeon/atombios_crtc.c | diffblobblamehistory |