| commit | 6d3607b179804e8ff4e2a1304ee238a4f6dc035c | |
| author | Andiry Xu <andiry.xu@amd.com> | |
| Fri, 23 Sep 2011 21:19:50 +0000 (23 14:19 -0700) | ||
| committer | Greg Kroah-Hartman <gregkh@suse.de> | |
| Fri, 11 Nov 2011 17:36:45 +0000 (11 09:36 -0800) | ||
| tree | 6099a47c6ec167f6c1afc8a75b26ca5aeb3f9f76 | treesnapshot (tar.gz zip) |
| parent | 1c349398c8583d23bdf397363aedaae55d889c03 | commitdiff |
xHCI: Clear PLC for USB2 root hub ports
commit 6fd4562178508a0949c9fdecd8558d8b10d671bd upstream.
When the link state changes, xHC will report a port status change event
and set the PORT_PLC bit, for both USB3 and USB2 root hub ports.
The PLC will be cleared by usbcore for USB3 root hub ports, but not for
USB2 ports, because they do not report USB_PORT_STAT_C_LINK_STATE in
wPortChange.
Clear it for USB2 root hub ports in handle_port_status().
Signed-off-by: Andiry Xu <andiry.xu@amd.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
commit 6fd4562178508a0949c9fdecd8558d8b10d671bd upstream.
When the link state changes, xHC will report a port status change event
and set the PORT_PLC bit, for both USB3 and USB2 root hub ports.
The PLC will be cleared by usbcore for USB3 root hub ports, but not for
USB2 ports, because they do not report USB_PORT_STAT_C_LINK_STATE in
wPortChange.
Clear it for USB2 root hub ports in handle_port_status().
Signed-off-by: Andiry Xu <andiry.xu@amd.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| drivers/usb/host/xhci-ring.c | diffblobblamehistory |