| commit | 68e47981437686e58de1edc616d6c3043e01f07e | |
| author | Axel Lin <axel.lin@gmail.com> | |
| Thu, 27 Oct 2011 08:38:42 +0000 (27 16:38 +0800) | ||
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | |
| Thu, 27 Oct 2011 10:00:15 +0000 (27 12:00 +0200) | ||
| tree | 8ef1cbd7ea2db51466bd10aeb7a089c487eb1760 | treesnapshot (tar.gz zip) |
| parent | b01a3d69f85c0af0934451e0f5457f2f6e7f3e63 | commitdiff |
ASoC: tlv320aic3x: Clear BIT_CLK_MASTER and WORD_CLK_MASTER bits for for slave mode
According to the datasheet:
Page0 / Register8: Audio Serial Data interface Control Register A
BIT 7: Bit Clock Directional Control
0: Bit clock is an input (slave mode)
1: Bit clock is an output (master mode)
BIT 6: Word Clock Directional Control
0: Word clock is an input (slave mode)
1: Word clock is an output (master mode)
Current code sets BIT_CLK_MASTER and WORD_CLK_MASTER bits for master mode,
but does not clear these bits for slave mode.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
According to the datasheet:
Page0 / Register8: Audio Serial Data interface Control Register A
BIT 7: Bit Clock Directional Control
0: Bit clock is an input (slave mode)
1: Bit clock is an output (master mode)
BIT 6: Word Clock Directional Control
0: Word clock is an input (slave mode)
1: Word clock is an output (master mode)
Current code sets BIT_CLK_MASTER and WORD_CLK_MASTER bits for master mode,
but does not clear these bits for slave mode.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
| sound/soc/codecs/tlv320aic3x.c | diffblobblamehistory |