| commit | 400036c2e53672323a7dd743146017995ffecb27 | |
| author | David Woodhouse <David.Woodhouse@intel.com> | |
| Tue, 15 Jun 2010 09:57:57 +0000 (15 10:57 +0100) | ||
| committer | Greg Kroah-Hartman <gregkh@suse.de> | |
| Mon, 9 May 2011 22:55:37 +0000 (9 15:55 -0700) | ||
| tree | 0ae1e27cee7908ca947e8a86fde3cc684927e485 | treesnapshot (tar.gz zip) |
| parent | e281433b151dad34ac1556adc5d276e4cf077b43 | commitdiff |
intel-iommu: Force-disable IOMMU for iGFX on broken Cantiga revisions.
commit 2d9e667efdfb4e986074d98e7d9a424003c7c43b upstream.
Certain revisions of this chipset appear to be broken. There is a shadow
GTT which mirrors the real GTT but contains pre-translated physical
addresses, for performance reasons. When a GTT update happens, the
translations are done once and the resulting physical addresses written
back to the shadow GTT.
Except sometimes, the physical address is actually written back to the
_real_ GTT, not the shadow GTT. Thus we start to see faults when that
physical address is fed through translation again.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
commit 2d9e667efdfb4e986074d98e7d9a424003c7c43b upstream.
Certain revisions of this chipset appear to be broken. There is a shadow
GTT which mirrors the real GTT but contains pre-translated physical
addresses, for performance reasons. When a GTT update happens, the
translations are done once and the resulting physical addresses written
back to the shadow GTT.
Except sometimes, the physical address is actually written back to the
_real_ GTT, not the shadow GTT. Thus we start to see faults when that
physical address is fed through translation again.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| drivers/pci/intel-iommu.c | diffblobblamehistory |