| commit | 2c8c53e28f178577dfdf3a69731b998b7e3df8ae | |
| author | David Daney <ddaney@caviumnetworks.com> | |
| Tue, 28 Dec 2010 02:07:57 +0000 (27 18:07 -0800) | ||
| committer | Ralf Baechle <ralf@linux-mips.org> | |
| Tue, 18 Jan 2011 18:30:23 +0000 (18 19:30 +0100) | ||
| tree | 0b65ff7fa0ac67795698be7a50559d77d3bc72db | treesnapshot (tar.gz zip) |
| parent | bb3d68c30a00918d4c9fa02a5c17a5aacf597977 | commitdiff |
MIPS: Optimize TLB handlers for Octeon CPUs
Octeon can use scratch registers in the TLB handlers. Octeon II can
use LDX instructions.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1904/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Octeon can use scratch registers in the TLB handlers. Octeon II can
use LDX instructions.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1904/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| arch/mips/mm/tlbex.c | diffblobblamehistory |